2 * Copyright (c) 2015-2016 Solarflare Communications Inc.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are met:
8 * 1. Redistributions of source code must retain the above copyright notice,
9 * this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright notice,
11 * this list of conditions and the following disclaimer in the documentation
12 * and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
15 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
16 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
17 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
18 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
19 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
20 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
21 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
22 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
23 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
24 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26 * The views and conclusions contained in the software and documentation are
27 * those of the authors and should not be interpreted as representing official
28 * policies, either expressed or implied, of the FreeBSD Project.
37 static __checkReturn efx_rc_t
38 efx_mcdi_get_rxdp_config(
40 __out uint32_t *end_paddingp)
43 EFX_MCDI_DECLARE_BUF(payload, MC_CMD_GET_RXDP_CONFIG_IN_LEN,
44 MC_CMD_GET_RXDP_CONFIG_OUT_LEN);
48 req.emr_cmd = MC_CMD_GET_RXDP_CONFIG;
49 req.emr_in_buf = payload;
50 req.emr_in_length = MC_CMD_GET_RXDP_CONFIG_IN_LEN;
51 req.emr_out_buf = payload;
52 req.emr_out_length = MC_CMD_GET_RXDP_CONFIG_OUT_LEN;
54 efx_mcdi_execute(enp, &req);
55 if (req.emr_rc != 0) {
60 if (MCDI_OUT_DWORD_FIELD(req, GET_RXDP_CONFIG_OUT_DATA,
61 GET_RXDP_CONFIG_OUT_PAD_HOST_DMA) == 0) {
62 /* RX DMA end padding is disabled */
65 switch (MCDI_OUT_DWORD_FIELD(req, GET_RXDP_CONFIG_OUT_DATA,
66 GET_RXDP_CONFIG_OUT_PAD_HOST_LEN)) {
67 case MC_CMD_SET_RXDP_CONFIG_IN_PAD_HOST_64:
70 case MC_CMD_SET_RXDP_CONFIG_IN_PAD_HOST_128:
73 case MC_CMD_SET_RXDP_CONFIG_IN_PAD_HOST_256:
82 *end_paddingp = end_padding;
89 EFSYS_PROBE1(fail1, efx_rc_t, rc);
94 static __checkReturn efx_rc_t
95 medford_nic_get_required_pcie_bandwidth(
97 __out uint32_t *bandwidth_mbpsp)
100 uint32_t current_mode;
104 if ((rc = efx_mcdi_get_port_modes(enp, &port_modes,
105 ¤t_mode)) != 0) {
106 /* No port mode info available. */
111 if ((rc = ef10_nic_get_port_mode_bandwidth(current_mode,
116 *bandwidth_mbpsp = bandwidth;
121 EFSYS_PROBE1(fail1, efx_rc_t, rc);
126 __checkReturn efx_rc_t
130 efx_mcdi_iface_t *emip = &(enp->en_mcdi.em_emip);
131 efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
132 uint8_t mac_addr[6] = { 0 };
133 uint32_t board_type = 0;
134 ef10_link_state_t els;
135 efx_port_t *epp = &(enp->en_port);
140 uint32_t sysclk, dpcpu_clk;
142 uint32_t end_padding;
147 * FIXME: Likely to be incomplete and incorrect.
148 * Parts of this should be shared with Huntington.
151 if ((rc = efx_mcdi_get_port_assignment(enp, &port)) != 0)
155 * NOTE: The MCDI protocol numbers ports from zero.
156 * The common code MCDI interface numbers ports from one.
158 emip->emi_port = port + 1;
160 if ((rc = ef10_external_port_mapping(enp, port,
161 &encp->enc_external_port)) != 0)
165 * Get PCIe function number from firmware (used for
166 * per-function privilege and dynamic config info).
167 * - PCIe PF: pf = PF number, vf = 0xffff.
168 * - PCIe VF: pf = parent PF, vf = VF number.
170 if ((rc = efx_mcdi_get_function_info(enp, &pf, &vf)) != 0)
176 /* MAC address for this function */
177 if (EFX_PCI_FUNCTION_IS_PF(encp)) {
178 rc = efx_mcdi_get_mac_address_pf(enp, mac_addr);
179 #if EFSYS_OPT_ALLOW_UNCONFIGURED_NIC
180 /* Disable static config checking for Medford NICs, ONLY
181 * for manufacturing test and setup at the factory, to
182 * allow the static config to be installed.
184 #else /* EFSYS_OPT_ALLOW_UNCONFIGURED_NIC */
185 if ((rc == 0) && (mac_addr[0] & 0x02)) {
187 * If the static config does not include a global MAC
188 * address pool then the board may return a locally
189 * administered MAC address (this should only happen on
190 * incorrectly programmed boards).
194 #endif /* EFSYS_OPT_ALLOW_UNCONFIGURED_NIC */
196 rc = efx_mcdi_get_mac_address_vf(enp, mac_addr);
201 EFX_MAC_ADDR_COPY(encp->enc_mac_addr, mac_addr);
203 /* Board configuration */
204 rc = efx_mcdi_get_board_cfg(enp, &board_type, NULL, NULL);
206 /* Unprivileged functions may not be able to read board cfg */
213 encp->enc_board_type = board_type;
214 encp->enc_clk_mult = 1; /* not used for Medford */
216 /* Fill out fields in enp->en_port and enp->en_nic_cfg from MCDI */
217 if ((rc = efx_mcdi_get_phy_cfg(enp)) != 0)
220 /* Obtain the default PHY advertised capabilities */
221 if ((rc = ef10_phy_get_link(enp, &els)) != 0)
223 epp->ep_default_adv_cap_mask = els.els_adv_cap_mask;
224 epp->ep_adv_cap_mask = els.els_adv_cap_mask;
227 * Enable firmware workarounds for hardware errata.
228 * Expected responses are:
230 * Success: workaround enabled or disabled as requested.
231 * - MC_CMD_ERR_ENOSYS (reported as ENOTSUP):
232 * Firmware does not support the MC_CMD_WORKAROUND request.
233 * (assume that the workaround is not supported).
234 * - MC_CMD_ERR_ENOENT (reported as ENOENT):
235 * Firmware does not support the requested workaround.
236 * - MC_CMD_ERR_EPERM (reported as EACCES):
237 * Unprivileged function cannot enable/disable workarounds.
239 * See efx_mcdi_request_errcode() for MCDI error translations.
243 if (EFX_PCI_FUNCTION_IS_VF(encp)) {
245 * Interrupt testing does not work for VFs. See bug50084.
246 * FIXME: Does this still apply to Medford?
248 encp->enc_bug41750_workaround = B_TRUE;
251 /* Chained multicast is always enabled on Medford */
252 encp->enc_bug26807_workaround = B_TRUE;
255 * If the bug61265 workaround is enabled, then interrupt holdoff timers
256 * cannot be controlled by timer table writes, so MCDI must be used
257 * (timer table writes can still be used for wakeup timers).
259 rc = efx_mcdi_set_workaround(enp, MC_CMD_WORKAROUND_BUG61265, B_TRUE,
261 if ((rc == 0) || (rc == EACCES))
262 encp->enc_bug61265_workaround = B_TRUE;
263 else if ((rc == ENOTSUP) || (rc == ENOENT))
264 encp->enc_bug61265_workaround = B_FALSE;
268 /* Get clock frequencies (in MHz). */
269 if ((rc = efx_mcdi_get_clock(enp, &sysclk, &dpcpu_clk)) != 0)
273 * The Medford timer quantum is 1536 dpcpu_clk cycles, documented for
274 * the EV_TMR_VAL field of EV_TIMER_TBL. Scale for MHz and ns units.
276 encp->enc_evq_timer_quantum_ns = 1536000UL / dpcpu_clk; /* 1536 cycles */
277 encp->enc_evq_timer_max_us = (encp->enc_evq_timer_quantum_ns <<
278 FRF_CZ_TC_TIMER_VAL_WIDTH) / 1000;
280 /* Check capabilities of running datapath firmware */
281 if ((rc = ef10_get_datapath_caps(enp)) != 0)
284 /* Alignment for receive packet DMA buffers */
285 encp->enc_rx_buf_align_start = 1;
287 /* Get the RX DMA end padding alignment configuration */
288 if ((rc = efx_mcdi_get_rxdp_config(enp, &end_padding)) != 0) {
292 /* Assume largest tail padding size supported by hardware */
295 encp->enc_rx_buf_align_end = end_padding;
297 /* Alignment for WPTR updates */
298 encp->enc_rx_push_align = EF10_RX_WPTR_ALIGN;
301 * Maximum number of exclusive RSS contexts which can be allocated. The
302 * hardware supports 64, but 6 are reserved for shared contexts. They
303 * are a global resource so not all may be available.
305 encp->enc_rx_scale_max_exclusive_contexts = 58;
307 encp->enc_tx_dma_desc_size_max = EFX_MASK32(ESF_DZ_RX_KER_BYTE_CNT);
308 /* No boundary crossing limits */
309 encp->enc_tx_dma_desc_boundary = 0;
312 * Set resource limits for MC_CMD_ALLOC_VIS. Note that we cannot use
313 * MC_CMD_GET_RESOURCE_LIMITS here as that reports the available
314 * resources (allocated to this PCIe function), which is zero until
315 * after we have allocated VIs.
317 encp->enc_evq_limit = 1024;
318 encp->enc_rxq_limit = EFX_RXQ_LIMIT_TARGET;
319 encp->enc_txq_limit = EFX_TXQ_LIMIT_TARGET;
322 * The maximum supported transmit queue size is 2048. TXQs with 4096
323 * descriptors are not supported as the top bit is used for vfifo
326 encp->enc_txq_max_ndescs = 2048;
328 encp->enc_buftbl_limit = 0xFFFFFFFF;
330 encp->enc_piobuf_limit = MEDFORD_PIOBUF_NBUFS;
331 encp->enc_piobuf_size = MEDFORD_PIOBUF_SIZE;
332 encp->enc_piobuf_min_alloc_size = MEDFORD_MIN_PIO_ALLOC_SIZE;
335 * Get the current privilege mask. Note that this may be modified
336 * dynamically, so this value is informational only. DO NOT use
337 * the privilege mask to check for sufficient privileges, as that
338 * can result in time-of-check/time-of-use bugs.
340 if ((rc = ef10_get_privilege_mask(enp, &mask)) != 0)
342 encp->enc_privilege_mask = mask;
344 /* Get interrupt vector limits */
345 if ((rc = efx_mcdi_get_vector_cfg(enp, &base, &nvec, NULL)) != 0) {
346 if (EFX_PCI_FUNCTION_IS_PF(encp))
349 /* Ignore error (cannot query vector limits from a VF). */
353 encp->enc_intr_vec_base = base;
354 encp->enc_intr_limit = nvec;
357 * Maximum number of bytes into the frame the TCP header can start for
358 * firmware assisted TSO to work.
360 encp->enc_tx_tso_tcp_header_offset_limit = EF10_TCP_HEADER_OFFSET_LIMIT;
363 * Medford stores a single global copy of VPD, not per-PF as on
366 encp->enc_vpd_is_global = B_TRUE;
368 rc = medford_nic_get_required_pcie_bandwidth(enp, &bandwidth);
371 encp->enc_required_pcie_bandwidth_mbps = bandwidth;
372 encp->enc_max_pcie_link_gen = EFX_PCIE_LINK_SPEED_GEN3;
403 EFSYS_PROBE1(fail1, efx_rc_t, rc);
408 #endif /* EFSYS_OPT_MEDFORD */