+ .. figure:: testbed-2n-zn2.svg
+ :alt: testbed-2n-zn2
+ :align: center
+
+SUT server is populated with the following NIC models:
+
+#. NIC-1: x710-DA4 4p10GE Intel.
+#. NIC-2: xxv710-DA2 2p25GE Intel.
+#. NIC-3: cx556a-edat ConnectX5 2p100GE Mellanox.
+
+TG server runs TRex application and is populated with the following
+NIC models:
+
+#. NIC-1: x710-DA4 4p10GE Intel.
+#. NIC-2: xxv710-DA2 2p25GE Intel.
+#. NIC-3: cx556a-edat ConnectX5 2p100GE Mellanox.
+
+All AMD EPYC Zen2 7532 servers run with AMD SMT enabled, doubling the
+number of logical cores exposed to Linux.
+
+2-Node Xeon Cascade Lake (2n-clx)
+---------------------------------
+
+Three 2n-clx testbeds are in operation in FD.io labs. Each 2n-clx testbed
+is built with two SuperMicro SYS-7049GP-TRT servers, SUTs are equipped with two
+Intel Xeon Gold 6252N processors (35.75 MB Cache, 2.30 GHz, 24 cores).
+TGs are equiped with Intel Xeon Cascade Lake Platinum 8280 processors (38.5 MB
+Cache, 2.70 GHz, 28 cores). 2n-clx physical topology is shown below.
+
+.. only:: latex
+
+ .. raw:: latex
+
+ \begin{figure}[H]
+ \centering
+ \graphicspath{{../_tmp/src/introduction/}}
+ \includegraphics[width=0.90\textwidth]{testbed-2n-clx}
+ \label{fig:testbed-2n-clx}
+ \end{figure}
+
+.. only:: html
+
+ .. figure:: testbed-2n-clx.svg
+ :alt: testbed-2n-clx