config/arm/meson.build

   1 # SPDX-License-Identifier: BSD-3-Clause
   2 # Copyright(c) 2017 Intel Corporation.
   3 # Copyright(c) 2017 Cavium, Inc
   4
   5 # for checking defines we need to use the correct compiler flags
   6 march_opt = '-march=@0@'.format(machine)
   7
   8 arm_force_native_march = false
   9
  10 machine_args_generic = [
  11         ['default', ['-march=armv8-a+crc+crypto']],
  12         ['native', ['-march=native']],
  13         ['0xd03', ['-mcpu=cortex-a53']],
  14         ['0xd04', ['-mcpu=cortex-a35']],
  15         ['0xd07', ['-mcpu=cortex-a57']],
  16         ['0xd08', ['-mcpu=cortex-a72']],
  17         ['0xd09', ['-mcpu=cortex-a73']],
  18         ['0xd0a', ['-mcpu=cortex-a75']],
  19 ]
  20 machine_args_cavium = [
  21         ['default', ['-march=armv8-a+crc+crypto','-mcpu=thunderx']],
  22         ['native', ['-march=native']],
  23         ['0xa1', ['-mcpu=thunderxt88']],
  24         ['0xa2', ['-mcpu=thunderxt81']],
  25         ['0xa3', ['-mcpu=thunderxt83']]]
  26
  27 flags_common_default = [
  28         # Accelarate rte_memcpy. Be sure to run unit test (memcpy_perf_autotest)
  29         # to determine the best threshold in code. Refer to notes in source file
  30         # (lib/librte_eal/common/include/arch/arm/rte_memcpy_64.h) for more info.
  31         ['RTE_ARCH_ARM64_MEMCPY', false],
  32         #       ['RTE_ARM64_MEMCPY_ALIGNED_THRESHOLD', 2048],
  33         #       ['RTE_ARM64_MEMCPY_UNALIGNED_THRESHOLD', 512],
  34         # Leave below RTE_ARM64_MEMCPY_xxx options commented out, unless there're
  35         # strong reasons.
  36         #       ['RTE_ARM64_MEMCPY_SKIP_GCC_VER_CHECK', false],
  37         #       ['RTE_ARM64_MEMCPY_ALIGN_MASK', 0xF],
  38         #       ['RTE_ARM64_MEMCPY_STRICT_ALIGN', false],
  39
  40         ['RTE_LIBRTE_FM10K_PMD', false],
  41         ['RTE_LIBRTE_SFC_EFX_PMD', false],
  42         ['RTE_LIBRTE_AVP_PMD', false],
  43
  44         ['RTE_SCHED_VECTOR', false],
  45 ]
  46
  47 flags_generic = [
  48         ['RTE_MACHINE', '"armv8a"'],
  49         ['RTE_MAX_LCORE', 256],
  50         ['RTE_CACHE_LINE_SIZE', 128]]
  51 flags_cavium = [
  52         ['RTE_MACHINE', '"thunderx"'],
  53         ['RTE_CACHE_LINE_SIZE', 128],
  54         ['RTE_MAX_NUMA_NODES', 2],
  55         ['RTE_MAX_LCORE', 96],
  56         ['RTE_MAX_VFIO_GROUPS', 128],
  57         ['RTE_USE_C11_MEM_MODEL', false]]
  58 flags_dpaa = [
  59         ['RTE_MACHINE', '"dpaa"'],
  60         ['RTE_CACHE_LINE_SIZE', 64],
  61         ['RTE_MAX_NUMA_NODES', 1],
  62         ['RTE_MAX_LCORE', 16]]
  63 flags_dpaa2 = [
  64         ['RTE_MACHINE', '"dpaa2"'],
  65         ['RTE_CACHE_LINE_SIZE', 64],
  66         ['RTE_MAX_NUMA_NODES', 1],
  67         ['RTE_MAX_LCORE', 16],
  68         ['RTE_LIBRTE_DPAA2_USE_PHYS_IOVA', false]]
  69
  70 ## Arm implementer ID (ARM DDI 0487C.a, Section G7.2.106, Page G7-5321)
  71 impl_generic = ['Generic armv8', flags_generic, machine_args_generic]
  72 impl_0x41 = ['Arm', flags_generic, machine_args_generic]
  73 impl_0x42 = ['Broadcom', flags_generic, machine_args_generic]
  74 impl_0x43 = ['Cavium', flags_cavium, machine_args_cavium]
  75 impl_0x44 = ['DEC', flags_generic, machine_args_generic]
  76 impl_0x49 = ['Infineon', flags_generic, machine_args_generic]
  77 impl_0x4d = ['Motorola', flags_generic, machine_args_generic]
  78 impl_0x4e = ['NVIDIA', flags_generic, machine_args_generic]
  79 impl_0x50 = ['AppliedMicro', flags_generic, machine_args_generic]
  80 impl_0x51 = ['Qualcomm', flags_generic, machine_args_generic]
  81 impl_0x53 = ['Samsung', flags_generic, machine_args_generic]
  82 impl_0x56 = ['Marvell', flags_generic, machine_args_generic]
  83 impl_0x69 = ['Intel', flags_generic, machine_args_generic]
  84 impl_dpaa = ['NXP DPAA', flags_dpaa, machine_args_generic]
  85 impl_dpaa2 = ['NXP DPAA2', flags_dpaa2, machine_args_generic]
  86
  87 dpdk_conf.set('RTE_FORCE_INTRINSICS', 1)
  88
  89 if cc.sizeof('void *') != 8
  90         dpdk_conf.set('RTE_CACHE_LINE_SIZE', 64)
  91         dpdk_conf.set('RTE_ARCH_ARM', 1)
  92         dpdk_conf.set('RTE_ARCH_ARMv7', 1)
  93         # the minimum architecture supported, armv7-a, needs the following,
  94         # mk/machine/armv7a/rte.vars.mk sets it too
  95         machine_args += '-mfpu=neon'
  96 else
  97         dpdk_conf.set('RTE_CACHE_LINE_SIZE', 128)
  98         dpdk_conf.set('RTE_ARCH_ARM64', 1)
  99         dpdk_conf.set('RTE_ARCH_64', 1)
 100
 101         machine = []
 102         cmd_generic = ['generic', '', '', 'default', '']
 103         cmd_output = cmd_generic # Set generic by default
 104         machine_args = [] # Clear previous machine args
 105         if not meson.is_cross_build()
 106                 # The script returns ['Implementer', 'Variant', 'Architecture',
 107                 # 'Primary Part number', 'Revision']
 108                 detect_vendor = find_program(join_paths(
 109                                 meson.current_source_dir(), 'armv8_machine.py'))
 110                 cmd = run_command(detect_vendor.path())
 111                 if cmd.returncode() == 0
 112                         cmd_output = cmd.stdout().to_lower().strip().split(' ')
 113                 endif
 114                 # Set to generic if variable is not found
 115                 machine = get_variable('impl_' + cmd_output[0], 'generic')
 116                 if machine == 'generic'
 117                         machine = impl_generic
 118                         cmd_output = cmd_generic
 119                 endif
 120                 impl_pn = cmd_output[3]
 121                 if arm_force_native_march == true
 122                         impl_pn = 'native'
 123                 endif
 124         else
 125                 impl_id = meson.get_cross_property('implementor_id', 'generic')
 126                 impl_pn = meson.get_cross_property('implementor_pn', 'default')
 127                 machine = get_variable('impl_' + impl_id)
 128         endif
 129
 130         # Apply Common Defaults. These settings may be overwritten by machine
 131         # settings later.
 132         foreach flag: flags_common_default
 133                 if flag.length() > 0
 134                         dpdk_conf.set(flag[0], flag[1])
 135                 endif
 136         endforeach
 137
 138         message('Implementer : ' + machine[0])
 139         foreach flag: machine[1]
 140                 if flag.length() > 0
 141                         dpdk_conf.set(flag[0], flag[1])
 142                 endif
 143         endforeach
 144         # Primary part number based mcpu flags are supported
 145         # for gcc versions > 7
 146         if cc.version().version_compare(
 147                         '<7.0') or cmd_output.length() == 0
 148                 if not meson.is_cross_build() and arm_force_native_march == true
 149                         impl_pn = 'native'
 150                 else
 151                         impl_pn = 'default'
 152                 endif
 153         endif
 154         foreach marg: machine[2]
 155                 if marg[0] == impl_pn
 156                         foreach f: marg[1]
 157                                 machine_args += f
 158                         endforeach
 159                 endif
 160         endforeach
 161 endif
 162 message(machine_args)
 163
 164 if (cc.get_define('__ARM_NEON', args: machine_args) != '' or
 165     cc.get_define('__aarch64__', args: machine_args) != '')
 166         dpdk_conf.set('RTE_MACHINE_CPUFLAG_NEON', 1)
 167         compile_time_cpuflags += ['RTE_CPUFLAG_NEON']
 168 endif
 169
 170 if cc.get_define('__ARM_FEATURE_CRC32', args: machine_args) != ''
 171         dpdk_conf.set('RTE_MACHINE_CPUFLAG_CRC32', 1)
 172         compile_time_cpuflags += ['RTE_CPUFLAG_CRC32']
 173 endif
 174
 175 if cc.get_define('__ARM_FEATURE_CRYPTO', args: machine_args) != ''
 176         dpdk_conf.set('RTE_MACHINE_CPUFLAG_AES', 1)
 177         dpdk_conf.set('RTE_MACHINE_CPUFLAG_PMULL', 1)
 178         dpdk_conf.set('RTE_MACHINE_CPUFLAG_SHA1', 1)
 179         dpdk_conf.set('RTE_MACHINE_CPUFLAG_SHA2', 1)
 180         compile_time_cpuflags += ['RTE_CPUFLAG_AES', 'RTE_CPUFLAG_PMULL',
 181         'RTE_CPUFLAG_SHA1', 'RTE_CPUFLAG_SHA2']
 182 endif