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36 #include <linux/pci_regs.h>
37 #include <sys/eventfd.h>
38 #include <sys/socket.h>
39 #include <sys/ioctl.h>
45 #include <rte_bus_pci.h>
46 #include <rte_eal_memconfig.h>
47 #include <rte_malloc.h>
50 #include "eal_filesystem.h"
57 * PCI probing under linux (VFIO version)
59 * This code tries to determine if the PCI device is bound to VFIO driver,
60 * and initialize it (map BARs, set up interrupts) if that's the case.
62 * This file is only compiled if CONFIG_RTE_EAL_VFIO is set to "y".
67 #define PAGE_SIZE (sysconf(_SC_PAGESIZE))
68 #define PAGE_MASK (~(PAGE_SIZE - 1))
70 static struct rte_tailq_elem rte_vfio_tailq = {
71 .name = "VFIO_RESOURCE_LIST",
73 EAL_REGISTER_TAILQ(rte_vfio_tailq)
76 pci_vfio_read_config(const struct rte_intr_handle *intr_handle,
77 void *buf, size_t len, off_t offs)
79 return pread64(intr_handle->vfio_dev_fd, buf, len,
80 VFIO_GET_REGION_ADDR(VFIO_PCI_CONFIG_REGION_INDEX) + offs);
84 pci_vfio_write_config(const struct rte_intr_handle *intr_handle,
85 const void *buf, size_t len, off_t offs)
87 return pwrite64(intr_handle->vfio_dev_fd, buf, len,
88 VFIO_GET_REGION_ADDR(VFIO_PCI_CONFIG_REGION_INDEX) + offs);
91 /* get PCI BAR number where MSI-X interrupts are */
93 pci_vfio_get_msix_bar(int fd, struct pci_msix_table *msix_table)
98 uint8_t cap_id, cap_offset;
100 /* read PCI capability pointer from config space */
101 ret = pread64(fd, ®, sizeof(reg),
102 VFIO_GET_REGION_ADDR(VFIO_PCI_CONFIG_REGION_INDEX) +
103 PCI_CAPABILITY_LIST);
104 if (ret != sizeof(reg)) {
105 RTE_LOG(ERR, EAL, "Cannot read capability pointer from PCI "
110 /* we need first byte */
111 cap_offset = reg & 0xFF;
115 /* read PCI capability ID */
116 ret = pread64(fd, ®, sizeof(reg),
117 VFIO_GET_REGION_ADDR(VFIO_PCI_CONFIG_REGION_INDEX) +
119 if (ret != sizeof(reg)) {
120 RTE_LOG(ERR, EAL, "Cannot read capability ID from PCI "
125 /* we need first byte */
128 /* if we haven't reached MSI-X, check next capability */
129 if (cap_id != PCI_CAP_ID_MSIX) {
130 ret = pread64(fd, ®, sizeof(reg),
131 VFIO_GET_REGION_ADDR(VFIO_PCI_CONFIG_REGION_INDEX) +
133 if (ret != sizeof(reg)) {
134 RTE_LOG(ERR, EAL, "Cannot read capability pointer from PCI "
139 /* we need second byte */
140 cap_offset = (reg & 0xFF00) >> 8;
144 /* else, read table offset */
146 /* table offset resides in the next 4 bytes */
147 ret = pread64(fd, ®, sizeof(reg),
148 VFIO_GET_REGION_ADDR(VFIO_PCI_CONFIG_REGION_INDEX) +
150 if (ret != sizeof(reg)) {
151 RTE_LOG(ERR, EAL, "Cannot read table offset from PCI config "
156 ret = pread64(fd, &flags, sizeof(flags),
157 VFIO_GET_REGION_ADDR(VFIO_PCI_CONFIG_REGION_INDEX) +
159 if (ret != sizeof(flags)) {
160 RTE_LOG(ERR, EAL, "Cannot read table flags from PCI config "
165 msix_table->bar_index = reg & RTE_PCI_MSIX_TABLE_BIR;
166 msix_table->offset = reg & RTE_PCI_MSIX_TABLE_OFFSET;
168 16 * (1 + (flags & RTE_PCI_MSIX_FLAGS_QSIZE));
176 /* set PCI bus mastering */
178 pci_vfio_set_bus_master(int dev_fd, bool op)
183 ret = pread64(dev_fd, ®, sizeof(reg),
184 VFIO_GET_REGION_ADDR(VFIO_PCI_CONFIG_REGION_INDEX) +
186 if (ret != sizeof(reg)) {
187 RTE_LOG(ERR, EAL, "Cannot read command from PCI config space!\n");
192 /* set the master bit */
193 reg |= PCI_COMMAND_MASTER;
195 reg &= ~(PCI_COMMAND_MASTER);
197 ret = pwrite64(dev_fd, ®, sizeof(reg),
198 VFIO_GET_REGION_ADDR(VFIO_PCI_CONFIG_REGION_INDEX) +
201 if (ret != sizeof(reg)) {
202 RTE_LOG(ERR, EAL, "Cannot write command to PCI config space!\n");
209 /* set up interrupt support (but not enable interrupts) */
211 pci_vfio_setup_interrupts(struct rte_pci_device *dev, int vfio_dev_fd)
213 int i, ret, intr_idx;
214 enum rte_intr_mode intr_mode;
216 /* default to invalid index */
217 intr_idx = VFIO_PCI_NUM_IRQS;
219 /* Get default / configured intr_mode */
220 intr_mode = rte_eal_vfio_intr_mode();
222 /* get interrupt type from internal config (MSI-X by default, can be
223 * overridden from the command line
226 case RTE_INTR_MODE_MSIX:
227 intr_idx = VFIO_PCI_MSIX_IRQ_INDEX;
229 case RTE_INTR_MODE_MSI:
230 intr_idx = VFIO_PCI_MSI_IRQ_INDEX;
232 case RTE_INTR_MODE_LEGACY:
233 intr_idx = VFIO_PCI_INTX_IRQ_INDEX;
235 /* don't do anything if we want to automatically determine interrupt type */
236 case RTE_INTR_MODE_NONE:
239 RTE_LOG(ERR, EAL, " unknown default interrupt type!\n");
243 /* start from MSI-X interrupt type */
244 for (i = VFIO_PCI_MSIX_IRQ_INDEX; i >= 0; i--) {
245 struct vfio_irq_info irq = { .argsz = sizeof(irq) };
248 /* skip interrupt modes we don't want */
249 if (intr_mode != RTE_INTR_MODE_NONE &&
255 ret = ioctl(vfio_dev_fd, VFIO_DEVICE_GET_IRQ_INFO, &irq);
257 RTE_LOG(ERR, EAL, " cannot get IRQ info, "
258 "error %i (%s)\n", errno, strerror(errno));
262 /* if this vector cannot be used with eventfd, fail if we explicitly
263 * specified interrupt type, otherwise continue */
264 if ((irq.flags & VFIO_IRQ_INFO_EVENTFD) == 0) {
265 if (intr_mode != RTE_INTR_MODE_NONE) {
267 " interrupt vector does not support eventfd!\n");
273 /* set up an eventfd for interrupts */
274 fd = eventfd(0, EFD_NONBLOCK | EFD_CLOEXEC);
276 RTE_LOG(ERR, EAL, " cannot set up eventfd, "
277 "error %i (%s)\n", errno, strerror(errno));
281 dev->intr_handle.fd = fd;
282 dev->intr_handle.vfio_dev_fd = vfio_dev_fd;
285 case VFIO_PCI_MSIX_IRQ_INDEX:
286 intr_mode = RTE_INTR_MODE_MSIX;
287 dev->intr_handle.type = RTE_INTR_HANDLE_VFIO_MSIX;
289 case VFIO_PCI_MSI_IRQ_INDEX:
290 intr_mode = RTE_INTR_MODE_MSI;
291 dev->intr_handle.type = RTE_INTR_HANDLE_VFIO_MSI;
293 case VFIO_PCI_INTX_IRQ_INDEX:
294 intr_mode = RTE_INTR_MODE_LEGACY;
295 dev->intr_handle.type = RTE_INTR_HANDLE_VFIO_LEGACY;
298 RTE_LOG(ERR, EAL, " unknown interrupt type!\n");
305 /* if we're here, we haven't found a suitable interrupt vector */
310 pci_vfio_is_ioport_bar(int vfio_dev_fd, int bar_index)
315 ret = pread64(vfio_dev_fd, &ioport_bar, sizeof(ioport_bar),
316 VFIO_GET_REGION_ADDR(VFIO_PCI_CONFIG_REGION_INDEX)
317 + PCI_BASE_ADDRESS_0 + bar_index*4);
318 if (ret != sizeof(ioport_bar)) {
319 RTE_LOG(ERR, EAL, "Cannot read command (%x) from config space!\n",
320 PCI_BASE_ADDRESS_0 + bar_index*4);
324 return (ioport_bar & PCI_BASE_ADDRESS_SPACE_IO) != 0;
328 pci_rte_vfio_setup_device(struct rte_pci_device *dev, int vfio_dev_fd)
330 if (pci_vfio_setup_interrupts(dev, vfio_dev_fd) != 0) {
331 RTE_LOG(ERR, EAL, "Error setting up interrupts!\n");
335 /* set bus mastering for the device */
336 if (pci_vfio_set_bus_master(vfio_dev_fd, true)) {
337 RTE_LOG(ERR, EAL, "Cannot set up bus mastering!\n");
342 * Reset the device. If the device is not capable of resetting,
343 * then it updates errno as EINVAL.
345 if (ioctl(vfio_dev_fd, VFIO_DEVICE_RESET) && errno != EINVAL) {
346 RTE_LOG(ERR, EAL, "Unable to reset device! Error: %d (%s)\n",
347 errno, strerror(errno));
355 pci_vfio_mmap_bar(int vfio_dev_fd, struct mapped_pci_resource *vfio_res,
356 int bar_index, int additional_flags)
359 unsigned long offset, size;
362 struct pci_msix_table *msix_table = &vfio_res->msix_table;
363 struct pci_map *bar = &vfio_res->maps[bar_index];
369 if (msix_table->bar_index == bar_index) {
371 * VFIO will not let us map the MSI-X table,
372 * but we can map around it.
374 uint32_t table_start = msix_table->offset;
375 uint32_t table_end = table_start + msix_table->size;
376 table_end = (table_end + ~PAGE_MASK) & PAGE_MASK;
377 table_start &= PAGE_MASK;
379 if (table_start == 0 && table_end >= bar->size) {
380 /* Cannot map this BAR */
381 RTE_LOG(DEBUG, EAL, "Skipping BAR%d\n", bar_index);
387 memreg[0].offset = bar->offset;
388 memreg[0].size = table_start;
389 memreg[1].offset = bar->offset + table_end;
390 memreg[1].size = bar->size - table_end;
393 "Trying to map BAR%d that contains the MSI-X "
394 "table. Trying offsets: "
395 "0x%04lx:0x%04lx, 0x%04lx:0x%04lx\n", bar_index,
396 memreg[0].offset, memreg[0].size,
397 memreg[1].offset, memreg[1].size);
399 memreg[0].offset = bar->offset;
400 memreg[0].size = bar->size;
403 /* reserve the address using an inaccessible mapping */
404 bar_addr = mmap(bar->addr, bar->size, 0, MAP_PRIVATE |
405 MAP_ANONYMOUS | additional_flags, -1, 0);
406 if (bar_addr != MAP_FAILED) {
407 void *map_addr = NULL;
408 if (memreg[0].size) {
409 /* actual map of first part */
410 map_addr = pci_map_resource(bar_addr, vfio_dev_fd,
416 /* if there's a second part, try to map it */
417 if (map_addr != MAP_FAILED
418 && memreg[1].offset && memreg[1].size) {
419 void *second_addr = RTE_PTR_ADD(bar_addr,
421 (uintptr_t)bar->offset);
422 map_addr = pci_map_resource(second_addr,
429 if (map_addr == MAP_FAILED || !map_addr) {
430 munmap(bar_addr, bar->size);
431 bar_addr = MAP_FAILED;
432 RTE_LOG(ERR, EAL, "Failed to map pci BAR%d\n",
438 "Failed to create inaccessible mapping for BAR%d\n",
443 bar->addr = bar_addr;
448 pci_vfio_map_resource_primary(struct rte_pci_device *dev)
450 struct vfio_device_info device_info = { .argsz = sizeof(device_info) };
451 char pci_addr[PATH_MAX] = {0};
453 struct rte_pci_addr *loc = &dev->addr;
455 struct mapped_pci_resource *vfio_res = NULL;
456 struct mapped_pci_res_list *vfio_res_list =
457 RTE_TAILQ_CAST(rte_vfio_tailq.head, mapped_pci_res_list);
459 struct pci_map *maps;
461 dev->intr_handle.fd = -1;
463 /* store PCI address string */
464 snprintf(pci_addr, sizeof(pci_addr), PCI_PRI_FMT,
465 loc->domain, loc->bus, loc->devid, loc->function);
467 ret = rte_vfio_setup_device(rte_pci_get_sysfs_path(), pci_addr,
468 &vfio_dev_fd, &device_info);
472 /* allocate vfio_res and get region info */
473 vfio_res = rte_zmalloc("VFIO_RES", sizeof(*vfio_res), 0);
474 if (vfio_res == NULL) {
476 "%s(): cannot store uio mmap details\n", __func__);
477 goto err_vfio_dev_fd;
479 memcpy(&vfio_res->pci_addr, &dev->addr, sizeof(vfio_res->pci_addr));
481 /* get number of registers (up to BAR5) */
482 vfio_res->nb_maps = RTE_MIN((int) device_info.num_regions,
483 VFIO_PCI_BAR5_REGION_INDEX + 1);
486 maps = vfio_res->maps;
488 vfio_res->msix_table.bar_index = -1;
489 /* get MSI-X BAR, if any (we have to know where it is because we can't
490 * easily mmap it when using VFIO)
492 ret = pci_vfio_get_msix_bar(vfio_dev_fd, &vfio_res->msix_table);
494 RTE_LOG(ERR, EAL, " %s cannot get MSI-X BAR number!\n",
496 goto err_vfio_dev_fd;
499 for (i = 0; i < (int) vfio_res->nb_maps; i++) {
500 struct vfio_region_info reg = { .argsz = sizeof(reg) };
505 ret = ioctl(vfio_dev_fd, VFIO_DEVICE_GET_REGION_INFO, ®);
507 RTE_LOG(ERR, EAL, " %s cannot get device region info "
508 "error %i (%s)\n", pci_addr, errno, strerror(errno));
512 /* chk for io port region */
513 ret = pci_vfio_is_ioport_bar(vfio_dev_fd, i);
517 RTE_LOG(INFO, EAL, "Ignore mapping IO port bar(%d)\n",
522 /* skip non-mmapable BARs */
523 if ((reg.flags & VFIO_REGION_INFO_FLAG_MMAP) == 0)
526 /* try mapping somewhere close to the end of hugepages */
527 if (pci_map_addr == NULL)
528 pci_map_addr = pci_find_max_end_va();
530 bar_addr = pci_map_addr;
531 pci_map_addr = RTE_PTR_ADD(bar_addr, (size_t) reg.size);
533 maps[i].addr = bar_addr;
534 maps[i].offset = reg.offset;
535 maps[i].size = reg.size;
536 maps[i].path = NULL; /* vfio doesn't have per-resource paths */
538 ret = pci_vfio_mmap_bar(vfio_dev_fd, vfio_res, i, 0);
540 RTE_LOG(ERR, EAL, " %s mapping BAR%i failed: %s\n",
541 pci_addr, i, strerror(errno));
545 dev->mem_resource[i].addr = maps[i].addr;
548 if (pci_rte_vfio_setup_device(dev, vfio_dev_fd) < 0) {
549 RTE_LOG(ERR, EAL, " %s setup device failed\n", pci_addr);
553 TAILQ_INSERT_TAIL(vfio_res_list, vfio_res, next);
564 pci_vfio_map_resource_secondary(struct rte_pci_device *dev)
566 struct vfio_device_info device_info = { .argsz = sizeof(device_info) };
567 char pci_addr[PATH_MAX] = {0};
569 struct rte_pci_addr *loc = &dev->addr;
571 struct mapped_pci_resource *vfio_res = NULL;
572 struct mapped_pci_res_list *vfio_res_list =
573 RTE_TAILQ_CAST(rte_vfio_tailq.head, mapped_pci_res_list);
575 struct pci_map *maps;
577 dev->intr_handle.fd = -1;
579 /* store PCI address string */
580 snprintf(pci_addr, sizeof(pci_addr), PCI_PRI_FMT,
581 loc->domain, loc->bus, loc->devid, loc->function);
583 ret = rte_vfio_setup_device(rte_pci_get_sysfs_path(), pci_addr,
584 &vfio_dev_fd, &device_info);
588 /* if we're in a secondary process, just find our tailq entry */
589 TAILQ_FOREACH(vfio_res, vfio_res_list, next) {
590 if (rte_pci_addr_cmp(&vfio_res->pci_addr,
595 /* if we haven't found our tailq entry, something's wrong */
596 if (vfio_res == NULL) {
597 RTE_LOG(ERR, EAL, " %s cannot find TAILQ entry for PCI device!\n",
599 goto err_vfio_dev_fd;
603 maps = vfio_res->maps;
605 for (i = 0; i < (int) vfio_res->nb_maps; i++) {
606 ret = pci_vfio_mmap_bar(vfio_dev_fd, vfio_res, i, MAP_FIXED);
608 RTE_LOG(ERR, EAL, " %s mapping BAR%i failed: %s\n",
609 pci_addr, i, strerror(errno));
610 goto err_vfio_dev_fd;
613 dev->mem_resource[i].addr = maps[i].addr;
623 * map the PCI resources of a PCI device in virtual memory (VFIO version).
624 * primary and secondary processes follow almost exactly the same path
627 pci_vfio_map_resource(struct rte_pci_device *dev)
629 if (rte_eal_process_type() == RTE_PROC_PRIMARY)
630 return pci_vfio_map_resource_primary(dev);
632 return pci_vfio_map_resource_secondary(dev);
636 pci_vfio_unmap_resource(struct rte_pci_device *dev)
638 char pci_addr[PATH_MAX] = {0};
639 struct rte_pci_addr *loc = &dev->addr;
641 struct mapped_pci_resource *vfio_res = NULL;
642 struct mapped_pci_res_list *vfio_res_list;
644 struct pci_map *maps;
646 /* store PCI address string */
647 snprintf(pci_addr, sizeof(pci_addr), PCI_PRI_FMT,
648 loc->domain, loc->bus, loc->devid, loc->function);
651 if (close(dev->intr_handle.fd) < 0) {
652 RTE_LOG(INFO, EAL, "Error when closing eventfd file descriptor for %s\n",
657 if (pci_vfio_set_bus_master(dev->intr_handle.vfio_dev_fd, false)) {
658 RTE_LOG(ERR, EAL, " %s cannot unset bus mastering for PCI device!\n",
663 ret = rte_vfio_release_device(rte_pci_get_sysfs_path(), pci_addr,
664 dev->intr_handle.vfio_dev_fd);
667 "%s(): cannot release device\n", __func__);
671 vfio_res_list = RTE_TAILQ_CAST(rte_vfio_tailq.head, mapped_pci_res_list);
673 TAILQ_FOREACH(vfio_res, vfio_res_list, next) {
674 if (rte_pci_addr_cmp(&vfio_res->pci_addr, &dev->addr))
678 /* if we haven't found our tailq entry, something's wrong */
679 if (vfio_res == NULL) {
680 RTE_LOG(ERR, EAL, " %s cannot find TAILQ entry for PCI device!\n",
686 maps = vfio_res->maps;
688 RTE_LOG(INFO, EAL, "Releasing pci mapped resource for %s\n",
690 for (i = 0; i < (int) vfio_res->nb_maps; i++) {
693 * We do not need to be aware of MSI-X table BAR mappings as
694 * when mapping. Just using current maps array is enough
697 RTE_LOG(INFO, EAL, "Calling pci_unmap_resource for %s at %p\n",
698 pci_addr, maps[i].addr);
699 pci_unmap_resource(maps[i].addr, maps[i].size);
703 TAILQ_REMOVE(vfio_res_list, vfio_res, next);
709 pci_vfio_ioport_map(struct rte_pci_device *dev, int bar,
710 struct rte_pci_ioport *p)
712 if (bar < VFIO_PCI_BAR0_REGION_INDEX ||
713 bar > VFIO_PCI_BAR5_REGION_INDEX) {
714 RTE_LOG(ERR, EAL, "invalid bar (%d)!\n", bar);
719 p->base = VFIO_GET_REGION_ADDR(bar);
724 pci_vfio_ioport_read(struct rte_pci_ioport *p,
725 void *data, size_t len, off_t offset)
727 const struct rte_intr_handle *intr_handle = &p->dev->intr_handle;
729 if (pread64(intr_handle->vfio_dev_fd, data,
730 len, p->base + offset) <= 0)
732 "Can't read from PCI bar (%" PRIu64 ") : offset (%x)\n",
733 VFIO_GET_REGION_IDX(p->base), (int)offset);
737 pci_vfio_ioport_write(struct rte_pci_ioport *p,
738 const void *data, size_t len, off_t offset)
740 const struct rte_intr_handle *intr_handle = &p->dev->intr_handle;
742 if (pwrite64(intr_handle->vfio_dev_fd, data,
743 len, p->base + offset) <= 0)
745 "Can't write to PCI bar (%" PRIu64 ") : offset (%x)\n",
746 VFIO_GET_REGION_IDX(p->base), (int)offset);
750 pci_vfio_ioport_unmap(struct rte_pci_ioport *p)
757 pci_vfio_is_enabled(void)
759 return rte_vfio_is_enabled("vfio_pci");