1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2018 Cavium, Inc
5 #ifndef _CPT_HW_TYPES_H_
6 #define _CPT_HW_TYPES_H_
8 #include <rte_byteorder.h>
11 * This file defines HRM specific structs.
15 #define CPT_VF_INTR_MBOX_MASK (1<<0)
16 #define CPT_VF_INTR_DOVF_MASK (1<<1)
17 #define CPT_VF_INTR_IRDE_MASK (1<<2)
18 #define CPT_VF_INTR_NWRP_MASK (1<<3)
19 #define CPT_VF_INTR_SWERR_MASK (1<<4)
20 #define CPT_VF_INTR_HWERR_MASK (1<<5)
21 #define CPT_VF_INTR_FAULT_MASK (1<<6)
23 #define CPT_INST_SIZE (64)
24 #define CPT_NEXT_CHUNK_PTR_SIZE (8)
27 * CPT_INST_S software command definitions
43 #if RTE_BYTE_ORDER == RTE_BIG_ENDIAN
53 typedef struct cpt_vq_command {
61 * Structure cpt_inst_s
63 * CPT Instruction Structure
64 * This structure specifies the instruction layout.
65 * Instructions are stored in memory as little-endian unless
66 * CPT()_PF_Q()_CTL[INST_BE] is set.
68 typedef union cpt_inst_s {
70 struct cpt_inst_s_8s {
71 #if (RTE_BYTE_ORDER == RTE_BIG_ENDIAN) /* Word 0 - Big Endian */
72 uint64_t reserved_17_63 : 47;
73 /* [ 16: 16] Done interrupt.
74 * 0 = No interrupts related to this instruction.
75 * 1 = When the instruction completes,CPT()_VQ()_DONE[DONE]
76 * will be incremented, and based on the rules described
77 * there an interrupt may occur.
80 uint64_t reserved_0_15 : 16;
81 #else /* Word 0 - Little Endian */
82 uint64_t reserved_0_15 : 16;
84 uint64_t reserved_17_63 : 47;
85 #endif /* Word 0 - End */
86 #if (RTE_BYTE_ORDER == RTE_BIG_ENDIAN) /* Word 1 - Big Endian */
87 /* [127: 64] Result IOVA.
88 * If nonzero, specifies where to write CPT_RES_S.
89 * If zero, no result structure will be written.
90 * Address must be 16-byte aligned.
92 * Bits <63:49> are ignored by hardware; software should
93 * use a sign-extended bit <48> for forward compatibility.
95 uint64_t res_addr : 64;
96 #else /* Word 1 - Little Endian */
97 uint64_t res_addr : 64;
98 #endif /* Word 1 - End */
99 #if (RTE_BYTE_ORDER == RTE_BIG_ENDIAN) /* Word 2 - Big Endian */
100 uint64_t reserved_172_191 : 20;
101 /* [171:162] If [WQ_PTR] is nonzero, the SSO guest-group to
102 * use when CPT submits work to SSO.
103 * For the SSO to not discard the add-work request, FPA_PF_MAP()
104 * must map [GRP] and CPT()_PF_Q()_GMCTL[GMID] as valid.
107 /* [161:160] If [WQ_PTR] is nonzero, the SSO tag type to use
108 * when CPT submits work to SSO.
111 /* [159:128] If [WQ_PTR] is nonzero, the SSO tag to use when
112 * CPT submits work to SSO.
115 #else /* Word 2 - Little Endian */
119 uint64_t reserved_172_191 : 20;
120 #endif /* Word 2 - End */
121 #if (RTE_BYTE_ORDER == RTE_BIG_ENDIAN) /* Word 3 - Big Endian */
122 /** [255:192] If [WQ_PTR] is nonzero, it is a pointer to a
123 * work-queue entry that CPT submits work to SSO after all
124 * context, output data, and result write operations are
125 * visible to other CNXXXX units and the cores.
126 * Bits <2:0> must be zero.
127 * Bits <63:49> are ignored by hardware; software should use a
128 * sign-extended bit <48> for forward compatibility.
129 * Internal:Bits <63:49>, <2:0> are ignored by hardware,
130 * treated as always 0x0.
132 uint64_t wq_ptr : 64;
133 #else /* Word 3 - Little Endian */
134 uint64_t wq_ptr : 64;
135 #endif /* Word 3 - End */
136 #if (RTE_BYTE_ORDER == RTE_BIG_ENDIAN) /* Word 4 - Big Endian */
138 /** [319:256] Engine instruction word 0. Passed to the
142 vq_cmd_word0_t vq_cmd_w0;
144 #else /* Word 4 - Little Endian */
147 vq_cmd_word0_t vq_cmd_w0;
149 #endif /* Word 4 - End */
150 #if (RTE_BYTE_ORDER == RTE_BIG_ENDIAN) /* Word 5 - Big Endian */
152 /** [383:320] Engine instruction word 1. Passed to the
158 #else /* Word 5 - Little Endian */
163 #endif /* Word 5 - End */
164 #if (RTE_BYTE_ORDER == RTE_BIG_ENDIAN) /* Word 6 - Big Endian */
166 /** [447:384] Engine instruction word 2. Passed to the
172 #else /* Word 6 - Little Endian */
177 #endif /* Word 6 - End */
178 #if (RTE_BYTE_ORDER == RTE_BIG_ENDIAN) /* Word 7 - Big Endian */
180 /** [511:448] Engine instruction word 3. Passed to the
184 vq_cmd_word3_t vq_cmd_w3;
186 #else /* Word 7 - Little Endian */
189 vq_cmd_word3_t vq_cmd_w3;
191 #endif /* Word 7 - End */
196 * Structure cpt_res_s
198 * CPT Result Structure
199 * The CPT coprocessor writes the result structure after it completes a
200 * CPT_INST_S instruction. The result structure is exactly 16 bytes, and each
201 * instruction completion produces exactly one result structure.
203 * This structure is stored in memory as little-endian unless
204 * CPT()_PF_Q()_CTL[INST_BE] is set.
206 typedef union cpt_res_s {
208 struct cpt_res_s_8s {
209 #if (RTE_BYTE_ORDER == RTE_BIG_ENDIAN) /* Word 0 - Big Endian */
210 uint64_t reserved_17_63 : 47;
211 /** [ 16: 16] Done interrupt. This bit is copied from the
212 * corresponding instruction's CPT_INST_S[DONEINT].
214 uint64_t doneint : 1;
215 uint64_t reserved_8_15 : 8;
216 /** [ 7: 0] Indicates completion/error status of the CPT
217 * coprocessor for the associated instruction, as enumerated by
218 * CPT_COMP_E. Core software may write the memory location
219 * containing [COMPCODE] to 0x0 before ringing the doorbell, and
220 * then poll for completion by checking for a nonzero value.
222 * Once the core observes a nonzero [COMPCODE] value in this
223 * case, the CPT coprocessor will have also completed L2/DRAM
226 uint64_t compcode : 8;
227 #else /* Word 0 - Little Endian */
228 uint64_t compcode : 8;
229 uint64_t reserved_8_15 : 8;
230 uint64_t doneint : 1;
231 uint64_t reserved_17_63 : 47;
232 #endif /* Word 0 - End */
233 #if (RTE_BYTE_ORDER == RTE_BIG_ENDIAN) /* Word 1 - Big Endian */
234 uint64_t reserved_64_127 : 64;
235 #else /* Word 1 - Little Endian */
236 uint64_t reserved_64_127 : 64;
237 #endif /* Word 1 - End */
242 * Register (NCB) cpt#_vq#_ctl
244 * CPT VF Queue Control Registers
245 * This register configures queues. This register should be changed (other than
246 * clearing [ENA]) only when quiescent (see CPT()_VQ()_INPROG[INFLIGHT]).
250 struct cptx_vqx_ctl_s {
251 #if (RTE_BYTE_ORDER == RTE_BIG_ENDIAN) /* Word 0 - Big Endian */
252 uint64_t reserved_1_63 : 63;
253 /** [ 0: 0](R/W/H) Enables the logical instruction queue.
254 * See also CPT()_PF_Q()_CTL[CONT_ERR] and
255 * CPT()_VQ()_INPROG[INFLIGHT].
256 * 1 = Queue is enabled.
257 * 0 = Queue is disabled.
260 #else /* Word 0 - Little Endian */
262 uint64_t reserved_1_63 : 63;
263 #endif /* Word 0 - End */
268 * Register (NCB) cpt#_vq#_done
270 * CPT Queue Done Count Registers
271 * These registers contain the per-queue instruction done count.
275 struct cptx_vqx_done_s {
276 #if (RTE_BYTE_ORDER == RTE_BIG_ENDIAN) /* Word 0 - Big Endian */
277 uint64_t reserved_20_63 : 44;
278 /** [ 19: 0](R/W/H) Done count. When CPT_INST_S[DONEINT] set
279 * and that instruction completes,CPT()_VQ()_DONE[DONE] is
280 * incremented when the instruction finishes. Write to this
281 * field are for diagnostic use only; instead software writes
282 * CPT()_VQ()_DONE_ACK with the number of decrements for this
285 * Interrupts are sent as follows:
287 * When CPT()_VQ()_DONE[DONE] = 0, then no results are pending,
288 * the interrupt coalescing timer is held to zero, and an
289 * interrupt is not sent.
291 * When CPT()_VQ()_DONE[DONE] != 0, then the interrupt
292 * coalescing timer counts. If the counter is >= CPT()_VQ()_DONE
293 * _WAIT[TIME_WAIT]*1024, or CPT()_VQ()_DONE[DONE] >= CPT()_VQ()
294 * _DONE_WAIT[NUM_WAIT], i.e. enough time has passed or enough
295 * results have arrived, then the interrupt is sent. Otherwise,
296 * it is not sent due to coalescing.
298 * When CPT()_VQ()_DONE_ACK is written (or CPT()_VQ()_DONE is
299 * written but this is not typical), the interrupt coalescing
300 * timer restarts. Note after decrementing this interrupt
301 * equation is recomputed, for example if CPT()_VQ()_DONE[DONE]
302 * >= CPT()_VQ()_DONE_WAIT[NUM_WAIT] and because the timer is
303 * zero, the interrupt will be resent immediately. (This covers
304 * the race case between software acknowledging an interrupt and
305 * a result returning.)
307 * When CPT()_VQ()_DONE_ENA_W1S[DONE] = 0, interrupts are not
308 * sent, but the counting described above still occurs.
310 * Since CPT instructions complete out-of-order, if software is
311 * using completion interrupts the suggested scheme is to
312 * request a DONEINT on each request, and when an interrupt
313 * arrives perform a "greedy" scan for completions; even if a
314 * later command is acknowledged first this will not result in
315 * missing a completion.
317 * Software is responsible for making sure [DONE] does not
318 * overflow; for example by insuring there are not more than
319 * 2^20-1 instructions in flight that may request interrupts.
322 #else /* Word 0 - Little Endian */
324 uint64_t reserved_20_63 : 44;
325 #endif /* Word 0 - End */
330 * Register (NCB) cpt#_vq#_done_ack
332 * CPT Queue Done Count Ack Registers
333 * This register is written by software to acknowledge interrupts.
337 struct cptx_vqx_done_ack_s {
338 #if (RTE_BYTE_ORDER == RTE_BIG_ENDIAN) /* Word 0 - Big Endian */
339 uint64_t reserved_20_63 : 44;
340 /** [ 19: 0](R/W/H) Number of decrements to CPT()_VQ()_DONE
341 * [DONE]. Reads CPT()_VQ()_DONE[DONE].
343 * Written by software to acknowledge interrupts. If CPT()_VQ()_
344 * DONE[DONE] is still nonzero the interrupt will be re-sent if
345 * the conditions described in CPT()_VQ()_DONE[DONE] are
348 uint64_t done_ack : 20;
349 #else /* Word 0 - Little Endian */
350 uint64_t done_ack : 20;
351 uint64_t reserved_20_63 : 44;
352 #endif /* Word 0 - End */
354 } cptx_vqx_done_ack_t;
357 * Register (NCB) cpt#_vq#_done_wait
359 * CPT Queue Done Interrupt Coalescing Wait Registers
360 * Specifies the per queue interrupt coalescing settings.
364 struct cptx_vqx_done_wait_s {
365 #if (RTE_BYTE_ORDER == RTE_BIG_ENDIAN) /* Word 0 - Big Endian */
366 uint64_t reserved_48_63 : 16;
367 /** [ 47: 32](R/W) Time hold-off. When CPT()_VQ()_DONE[DONE] =
368 * 0, or CPT()_VQ()_DONE_ACK is written a timer is cleared. When
369 * the timer reaches [TIME_WAIT]*1024 then interrupt coalescing
370 * ends; see CPT()_VQ()_DONE[DONE]. If 0x0, time coalescing is
373 uint64_t time_wait : 16;
374 uint64_t reserved_20_31 : 12;
375 /** [ 19: 0](R/W) Number of messages hold-off. When
376 * CPT()_VQ()_DONE[DONE] >= [NUM_WAIT] then interrupt coalescing
377 * ends; see CPT()_VQ()_DONE[DONE]. If 0x0, same behavior as
380 uint64_t num_wait : 20;
381 #else /* Word 0 - Little Endian */
382 uint64_t num_wait : 20;
383 uint64_t reserved_20_31 : 12;
384 uint64_t time_wait : 16;
385 uint64_t reserved_48_63 : 16;
386 #endif /* Word 0 - End */
388 } cptx_vqx_done_wait_t;
391 * Register (NCB) cpt#_vq#_doorbell
393 * CPT Queue Doorbell Registers
394 * Doorbells for the CPT instruction queues.
398 struct cptx_vqx_doorbell_s {
399 #if (RTE_BYTE_ORDER == RTE_BIG_ENDIAN) /* Word 0 - Big Endian */
400 uint64_t reserved_20_63 : 44;
401 uint64_t dbell_cnt : 20;
402 /** [ 19: 0](R/W/H) Number of instruction queue 64-bit words
403 * to add to the CPT instruction doorbell count. Readback value
404 * is the the current number of pending doorbell requests.
406 * If counter overflows CPT()_VQ()_MISC_INT[DBELL_DOVF] is set.
408 * To reset the count back to zero, write one to clear
409 * CPT()_VQ()_MISC_INT_ENA_W1C[DBELL_DOVF], then write a value
410 * of 2^20 minus the read [DBELL_CNT], then write one to
411 * CPT()_VQ()_MISC_INT_W1C[DBELL_DOVF] and
412 * CPT()_VQ()_MISC_INT_ENA_W1S[DBELL_DOVF].
414 * Must be a multiple of 8. All CPT instructions are 8 words
415 * and require a doorbell count of multiple of 8.
417 #else /* Word 0 - Little Endian */
418 uint64_t dbell_cnt : 20;
419 uint64_t reserved_20_63 : 44;
420 #endif /* Word 0 - End */
422 } cptx_vqx_doorbell_t;
425 * Register (NCB) cpt#_vq#_inprog
427 * CPT Queue In Progress Count Registers
428 * These registers contain the per-queue instruction in flight registers.
432 struct cptx_vqx_inprog_s {
433 #if (RTE_BYTE_ORDER == RTE_BIG_ENDIAN) /* Word 0 - Big Endian */
434 uint64_t reserved_8_63 : 56;
435 /** [ 7: 0](RO/H) Inflight count. Counts the number of
436 * instructions for the VF for which CPT is fetching, executing
437 * or responding to instructions. However this does not include
438 * any interrupts that are awaiting software handling
439 * (CPT()_VQ()_DONE[DONE] != 0x0).
441 * A queue may not be reconfigured until:
442 * 1. CPT()_VQ()_CTL[ENA] is cleared by software.
443 * 2. [INFLIGHT] is polled until equals to zero.
445 uint64_t inflight : 8;
446 #else /* Word 0 - Little Endian */
447 uint64_t inflight : 8;
448 uint64_t reserved_8_63 : 56;
449 #endif /* Word 0 - End */
454 * Register (NCB) cpt#_vq#_misc_int
456 * CPT Queue Misc Interrupt Register
457 * These registers contain the per-queue miscellaneous interrupts.
461 struct cptx_vqx_misc_int_s {
462 #if (RTE_BYTE_ORDER == RTE_BIG_ENDIAN) /* Word 0 - Big Endian */
463 uint64_t reserved_7_63 : 57;
464 /** [ 6: 6](R/W1C/H) Translation fault detected. */
466 /** [ 5: 5](R/W1C/H) Hardware error from engines. */
468 /** [ 4: 4](R/W1C/H) Software error from engines. */
470 /** [ 3: 3](R/W1C/H) NCB result write response error. */
472 /** [ 2: 2](R/W1C/H) Instruction NCB read response error. */
474 /** [ 1: 1](R/W1C/H) Doorbell overflow. */
476 /** [ 0: 0](R/W1C/H) PF to VF mailbox interrupt. Set when
477 * CPT()_VF()_PF_MBOX(0) is written.
480 #else /* Word 0 - Little Endian */
488 uint64_t reserved_5_63 : 59;
489 #endif /* Word 0 - End */
491 } cptx_vqx_misc_int_t;
494 * Register (NCB) cpt#_vq#_saddr
496 * CPT Queue Starting Buffer Address Registers
497 * These registers set the instruction buffer starting address.
501 struct cptx_vqx_saddr_s {
502 #if (RTE_BYTE_ORDER == RTE_BIG_ENDIAN) /* Word 0 - Big Endian */
503 uint64_t reserved_49_63 : 15;
504 /** [ 48: 6](R/W/H) Instruction buffer IOVA <48:6>
505 * (64-byte aligned). When written, it is the initial buffer
506 * starting address; when read, it is the next read pointer to
507 * be requested from L2C. The PTR field is overwritten with the
508 * next pointer each time that the command buffer segment is
509 * exhausted. New commands will then be read from the newly
510 * specified command buffer pointer.
513 uint64_t reserved_0_5 : 6;
514 #else /* Word 0 - Little Endian */
515 uint64_t reserved_0_5 : 6;
517 uint64_t reserved_49_63 : 15;
518 #endif /* Word 0 - End */
522 #endif /*_CPT_HW_TYPES_H_ */