drivers/crypto/qat/qat_adf/qat_algs_build_desc.c

   1 /*
   2  *  This file is provided under a dual BSD/GPLv2 license.  When using or
   3  *  redistributing this file, you may do so under either license.
   4  *
   5  *  GPL LICENSE SUMMARY
   6  *  Copyright(c) 2015-2016 Intel Corporation.
   7  *  This program is free software; you can redistribute it and/or modify
   8  *  it under the terms of version 2 of the GNU General Public License as
   9  *  published by the Free Software Foundation.
  10  *
  11  *  This program is distributed in the hope that it will be useful, but
  12  *  WITHOUT ANY WARRANTY; without even the implied warranty of
  13  *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  *  General Public License for more details.
  15  *
  16  *  Contact Information:
  17  *  qat-linux@intel.com
  18  *
  19  *  BSD LICENSE
  20  *  Copyright(c) 2015-2017 Intel Corporation.
  21  *  Redistribution and use in source and binary forms, with or without
  22  *  modification, are permitted provided that the following conditions
  23  *  are met:
  24  *
  25  *      * Redistributions of source code must retain the above copyright
  26  *        notice, this list of conditions and the following disclaimer.
  27  *      * Redistributions in binary form must reproduce the above copyright
  28  *        notice, this list of conditions and the following disclaimer in
  29  *        the documentation and/or other materials provided with the
  30  *        distribution.
  31  *      * Neither the name of Intel Corporation nor the names of its
  32  *        contributors may be used to endorse or promote products derived
  33  *        from this software without specific prior written permission.
  34  *
  35  *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  36  *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  37  *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  38  *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  39  *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  40  *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  41  *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  42  *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  43  *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  44  *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  45  *  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  46  */
  47
  48 #include <rte_memcpy.h>
  49 #include <rte_common.h>
  50 #include <rte_spinlock.h>
  51 #include <rte_byteorder.h>
  52 #include <rte_log.h>
  53 #include <rte_malloc.h>
  54 #include <rte_crypto_sym.h>
  55
  56 #include "../qat_logs.h"
  57
  58 #include <openssl/sha.h>        /* Needed to calculate pre-compute values */
  59 #include <openssl/aes.h>        /* Needed to calculate pre-compute values */
  60 #include <openssl/md5.h>        /* Needed to calculate pre-compute values */
  61
  62 #include "qat_algs.h"
  63
  64 /* returns block size in bytes per cipher algo */
  65 int qat_cipher_get_block_size(enum icp_qat_hw_cipher_algo qat_cipher_alg)
  66 {
  67         switch (qat_cipher_alg) {
  68         case ICP_QAT_HW_CIPHER_ALGO_DES:
  69                 return ICP_QAT_HW_DES_BLK_SZ;
  70         case ICP_QAT_HW_CIPHER_ALGO_3DES:
  71                 return ICP_QAT_HW_3DES_BLK_SZ;
  72         case ICP_QAT_HW_CIPHER_ALGO_AES128:
  73         case ICP_QAT_HW_CIPHER_ALGO_AES192:
  74         case ICP_QAT_HW_CIPHER_ALGO_AES256:
  75                 return ICP_QAT_HW_AES_BLK_SZ;
  76         default:
  77                 PMD_DRV_LOG(ERR, "invalid block cipher alg %u", qat_cipher_alg);
  78                 return -EFAULT;
  79         };
  80         return -EFAULT;
  81 }
  82
  83 /*
  84  * Returns size in bytes per hash algo for state1 size field in cd_ctrl
  85  * This is digest size rounded up to nearest quadword
  86  */
  87 static int qat_hash_get_state1_size(enum icp_qat_hw_auth_algo qat_hash_alg)
  88 {
  89         switch (qat_hash_alg) {
  90         case ICP_QAT_HW_AUTH_ALGO_SHA1:
  91                 return QAT_HW_ROUND_UP(ICP_QAT_HW_SHA1_STATE1_SZ,
  92                                                 QAT_HW_DEFAULT_ALIGNMENT);
  93         case ICP_QAT_HW_AUTH_ALGO_SHA224:
  94                 return QAT_HW_ROUND_UP(ICP_QAT_HW_SHA224_STATE1_SZ,
  95                                                 QAT_HW_DEFAULT_ALIGNMENT);
  96         case ICP_QAT_HW_AUTH_ALGO_SHA256:
  97                 return QAT_HW_ROUND_UP(ICP_QAT_HW_SHA256_STATE1_SZ,
  98                                                 QAT_HW_DEFAULT_ALIGNMENT);
  99         case ICP_QAT_HW_AUTH_ALGO_SHA384:
 100                 return QAT_HW_ROUND_UP(ICP_QAT_HW_SHA384_STATE1_SZ,
 101                                                 QAT_HW_DEFAULT_ALIGNMENT);
 102         case ICP_QAT_HW_AUTH_ALGO_SHA512:
 103                 return QAT_HW_ROUND_UP(ICP_QAT_HW_SHA512_STATE1_SZ,
 104                                                 QAT_HW_DEFAULT_ALIGNMENT);
 105         case ICP_QAT_HW_AUTH_ALGO_AES_XCBC_MAC:
 106                 return QAT_HW_ROUND_UP(ICP_QAT_HW_AES_XCBC_MAC_STATE1_SZ,
 107                                                 QAT_HW_DEFAULT_ALIGNMENT);
 108         case ICP_QAT_HW_AUTH_ALGO_GALOIS_128:
 109         case ICP_QAT_HW_AUTH_ALGO_GALOIS_64:
 110                 return QAT_HW_ROUND_UP(ICP_QAT_HW_GALOIS_128_STATE1_SZ,
 111                                                 QAT_HW_DEFAULT_ALIGNMENT);
 112         case ICP_QAT_HW_AUTH_ALGO_ZUC_3G_128_EIA3:
 113                 return QAT_HW_ROUND_UP(ICP_QAT_HW_ZUC_3G_EIA3_STATE1_SZ,
 114                                                 QAT_HW_DEFAULT_ALIGNMENT);
 115         case ICP_QAT_HW_AUTH_ALGO_SNOW_3G_UIA2:
 116                 return QAT_HW_ROUND_UP(ICP_QAT_HW_SNOW_3G_UIA2_STATE1_SZ,
 117                                                 QAT_HW_DEFAULT_ALIGNMENT);
 118         case ICP_QAT_HW_AUTH_ALGO_MD5:
 119                 return QAT_HW_ROUND_UP(ICP_QAT_HW_MD5_STATE1_SZ,
 120                                                 QAT_HW_DEFAULT_ALIGNMENT);
 121         case ICP_QAT_HW_AUTH_ALGO_KASUMI_F9:
 122                 return QAT_HW_ROUND_UP(ICP_QAT_HW_KASUMI_F9_STATE1_SZ,
 123                                                 QAT_HW_DEFAULT_ALIGNMENT);
 124         case ICP_QAT_HW_AUTH_ALGO_NULL:
 125                 return QAT_HW_ROUND_UP(ICP_QAT_HW_NULL_STATE1_SZ,
 126                                                 QAT_HW_DEFAULT_ALIGNMENT);
 127         case ICP_QAT_HW_AUTH_ALGO_AES_CBC_MAC:
 128                 return QAT_HW_ROUND_UP(ICP_QAT_HW_AES_CBC_MAC_STATE1_SZ,
 129                                                 QAT_HW_DEFAULT_ALIGNMENT);
 130         case ICP_QAT_HW_AUTH_ALGO_DELIMITER:
 131                 /* return maximum state1 size in this case */
 132                 return QAT_HW_ROUND_UP(ICP_QAT_HW_SHA512_STATE1_SZ,
 133                                                 QAT_HW_DEFAULT_ALIGNMENT);
 134         default:
 135                 PMD_DRV_LOG(ERR, "invalid hash alg %u", qat_hash_alg);
 136                 return -EFAULT;
 137         };
 138         return -EFAULT;
 139 }
 140
 141 /* returns digest size in bytes  per hash algo */
 142 static int qat_hash_get_digest_size(enum icp_qat_hw_auth_algo qat_hash_alg)
 143 {
 144         switch (qat_hash_alg) {
 145         case ICP_QAT_HW_AUTH_ALGO_SHA1:
 146                 return ICP_QAT_HW_SHA1_STATE1_SZ;
 147         case ICP_QAT_HW_AUTH_ALGO_SHA224:
 148                 return ICP_QAT_HW_SHA224_STATE1_SZ;
 149         case ICP_QAT_HW_AUTH_ALGO_SHA256:
 150                 return ICP_QAT_HW_SHA256_STATE1_SZ;
 151         case ICP_QAT_HW_AUTH_ALGO_SHA384:
 152                 return ICP_QAT_HW_SHA384_STATE1_SZ;
 153         case ICP_QAT_HW_AUTH_ALGO_SHA512:
 154                 return ICP_QAT_HW_SHA512_STATE1_SZ;
 155         case ICP_QAT_HW_AUTH_ALGO_MD5:
 156                 return ICP_QAT_HW_MD5_STATE1_SZ;
 157         case ICP_QAT_HW_AUTH_ALGO_DELIMITER:
 158                 /* return maximum digest size in this case */
 159                 return ICP_QAT_HW_SHA512_STATE1_SZ;
 160         default:
 161                 PMD_DRV_LOG(ERR, "invalid hash alg %u", qat_hash_alg);
 162                 return -EFAULT;
 163         };
 164         return -EFAULT;
 165 }
 166
 167 /* returns block size in byes per hash algo */
 168 static int qat_hash_get_block_size(enum icp_qat_hw_auth_algo qat_hash_alg)
 169 {
 170         switch (qat_hash_alg) {
 171         case ICP_QAT_HW_AUTH_ALGO_SHA1:
 172                 return SHA_CBLOCK;
 173         case ICP_QAT_HW_AUTH_ALGO_SHA224:
 174                 return SHA256_CBLOCK;
 175         case ICP_QAT_HW_AUTH_ALGO_SHA256:
 176                 return SHA256_CBLOCK;
 177         case ICP_QAT_HW_AUTH_ALGO_SHA384:
 178                 return SHA512_CBLOCK;
 179         case ICP_QAT_HW_AUTH_ALGO_SHA512:
 180                 return SHA512_CBLOCK;
 181         case ICP_QAT_HW_AUTH_ALGO_GALOIS_128:
 182                 return 16;
 183         case ICP_QAT_HW_AUTH_ALGO_MD5:
 184                 return MD5_CBLOCK;
 185         case ICP_QAT_HW_AUTH_ALGO_DELIMITER:
 186                 /* return maximum block size in this case */
 187                 return SHA512_CBLOCK;
 188         default:
 189                 PMD_DRV_LOG(ERR, "invalid hash alg %u", qat_hash_alg);
 190                 return -EFAULT;
 191         };
 192         return -EFAULT;
 193 }
 194
 195 static int partial_hash_sha1(uint8_t *data_in, uint8_t *data_out)
 196 {
 197         SHA_CTX ctx;
 198
 199         if (!SHA1_Init(&ctx))
 200                 return -EFAULT;
 201         SHA1_Transform(&ctx, data_in);
 202         rte_memcpy(data_out, &ctx, SHA_DIGEST_LENGTH);
 203         return 0;
 204 }
 205
 206 static int partial_hash_sha224(uint8_t *data_in, uint8_t *data_out)
 207 {
 208         SHA256_CTX ctx;
 209
 210         if (!SHA224_Init(&ctx))
 211                 return -EFAULT;
 212         SHA256_Transform(&ctx, data_in);
 213         rte_memcpy(data_out, &ctx, SHA256_DIGEST_LENGTH);
 214         return 0;
 215 }
 216
 217 static int partial_hash_sha256(uint8_t *data_in, uint8_t *data_out)
 218 {
 219         SHA256_CTX ctx;
 220
 221         if (!SHA256_Init(&ctx))
 222                 return -EFAULT;
 223         SHA256_Transform(&ctx, data_in);
 224         rte_memcpy(data_out, &ctx, SHA256_DIGEST_LENGTH);
 225         return 0;
 226 }
 227
 228 static int partial_hash_sha384(uint8_t *data_in, uint8_t *data_out)
 229 {
 230         SHA512_CTX ctx;
 231
 232         if (!SHA384_Init(&ctx))
 233                 return -EFAULT;
 234         SHA512_Transform(&ctx, data_in);
 235         rte_memcpy(data_out, &ctx, SHA512_DIGEST_LENGTH);
 236         return 0;
 237 }
 238
 239 static int partial_hash_sha512(uint8_t *data_in, uint8_t *data_out)
 240 {
 241         SHA512_CTX ctx;
 242
 243         if (!SHA512_Init(&ctx))
 244                 return -EFAULT;
 245         SHA512_Transform(&ctx, data_in);
 246         rte_memcpy(data_out, &ctx, SHA512_DIGEST_LENGTH);
 247         return 0;
 248 }
 249
 250 static int partial_hash_md5(uint8_t *data_in, uint8_t *data_out)
 251 {
 252         MD5_CTX ctx;
 253
 254         if (!MD5_Init(&ctx))
 255                 return -EFAULT;
 256         MD5_Transform(&ctx, data_in);
 257         rte_memcpy(data_out, &ctx, MD5_DIGEST_LENGTH);
 258
 259         return 0;
 260 }
 261
 262 static int partial_hash_compute(enum icp_qat_hw_auth_algo hash_alg,
 263                         uint8_t *data_in,
 264                         uint8_t *data_out)
 265 {
 266         int digest_size;
 267         uint8_t digest[qat_hash_get_digest_size(
 268                         ICP_QAT_HW_AUTH_ALGO_DELIMITER)];
 269         uint32_t *hash_state_out_be32;
 270         uint64_t *hash_state_out_be64;
 271         int i;
 272
 273         PMD_INIT_FUNC_TRACE();
 274         digest_size = qat_hash_get_digest_size(hash_alg);
 275         if (digest_size <= 0)
 276                 return -EFAULT;
 277
 278         hash_state_out_be32 = (uint32_t *)data_out;
 279         hash_state_out_be64 = (uint64_t *)data_out;
 280
 281         switch (hash_alg) {
 282         case ICP_QAT_HW_AUTH_ALGO_SHA1:
 283                 if (partial_hash_sha1(data_in, digest))
 284                         return -EFAULT;
 285                 for (i = 0; i < digest_size >> 2; i++, hash_state_out_be32++)
 286                         *hash_state_out_be32 =
 287                                 rte_bswap32(*(((uint32_t *)digest)+i));
 288                 break;
 289         case ICP_QAT_HW_AUTH_ALGO_SHA224:
 290                 if (partial_hash_sha224(data_in, digest))
 291                         return -EFAULT;
 292                 for (i = 0; i < digest_size >> 2; i++, hash_state_out_be32++)
 293                         *hash_state_out_be32 =
 294                                 rte_bswap32(*(((uint32_t *)digest)+i));
 295                 break;
 296         case ICP_QAT_HW_AUTH_ALGO_SHA256:
 297                 if (partial_hash_sha256(data_in, digest))
 298                         return -EFAULT;
 299                 for (i = 0; i < digest_size >> 2; i++, hash_state_out_be32++)
 300                         *hash_state_out_be32 =
 301                                 rte_bswap32(*(((uint32_t *)digest)+i));
 302                 break;
 303         case ICP_QAT_HW_AUTH_ALGO_SHA384:
 304                 if (partial_hash_sha384(data_in, digest))
 305                         return -EFAULT;
 306                 for (i = 0; i < digest_size >> 3; i++, hash_state_out_be64++)
 307                         *hash_state_out_be64 =
 308                                 rte_bswap64(*(((uint64_t *)digest)+i));
 309                 break;
 310         case ICP_QAT_HW_AUTH_ALGO_SHA512:
 311                 if (partial_hash_sha512(data_in, digest))
 312                         return -EFAULT;
 313                 for (i = 0; i < digest_size >> 3; i++, hash_state_out_be64++)
 314                         *hash_state_out_be64 =
 315                                 rte_bswap64(*(((uint64_t *)digest)+i));
 316                 break;
 317         case ICP_QAT_HW_AUTH_ALGO_MD5:
 318                 if (partial_hash_md5(data_in, data_out))
 319                         return -EFAULT;
 320                 break;
 321         default:
 322                 PMD_DRV_LOG(ERR, "invalid hash alg %u", hash_alg);
 323                 return -EFAULT;
 324         }
 325
 326         return 0;
 327 }
 328 #define HMAC_IPAD_VALUE 0x36
 329 #define HMAC_OPAD_VALUE 0x5c
 330 #define HASH_XCBC_PRECOMP_KEY_NUM 3
 331
 332 static int qat_alg_do_precomputes(enum icp_qat_hw_auth_algo hash_alg,
 333                                 const uint8_t *auth_key,
 334                                 uint16_t auth_keylen,
 335                                 uint8_t *p_state_buf,
 336                                 uint16_t *p_state_len)
 337 {
 338         int block_size;
 339         uint8_t ipad[qat_hash_get_block_size(ICP_QAT_HW_AUTH_ALGO_DELIMITER)];
 340         uint8_t opad[qat_hash_get_block_size(ICP_QAT_HW_AUTH_ALGO_DELIMITER)];
 341         int i;
 342
 343         PMD_INIT_FUNC_TRACE();
 344         if (hash_alg == ICP_QAT_HW_AUTH_ALGO_AES_XCBC_MAC) {
 345                 static uint8_t qat_aes_xcbc_key_seed[
 346                                         ICP_QAT_HW_AES_XCBC_MAC_STATE2_SZ] = {
 347                         0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01,
 348                         0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01,
 349                         0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02,
 350                         0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02,
 351                         0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03,
 352                         0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03,
 353                 };
 354
 355                 uint8_t *in = NULL;
 356                 uint8_t *out = p_state_buf;
 357                 int x;
 358                 AES_KEY enc_key;
 359
 360                 in = rte_zmalloc("working mem for key",
 361                                 ICP_QAT_HW_AES_XCBC_MAC_STATE2_SZ, 16);
 362                 rte_memcpy(in, qat_aes_xcbc_key_seed,
 363                                 ICP_QAT_HW_AES_XCBC_MAC_STATE2_SZ);
 364                 for (x = 0; x < HASH_XCBC_PRECOMP_KEY_NUM; x++) {
 365                         if (AES_set_encrypt_key(auth_key, auth_keylen << 3,
 366                                 &enc_key) != 0) {
 367                                 rte_free(in -
 368                                         (x * ICP_QAT_HW_AES_XCBC_MAC_KEY_SZ));
 369                                 memset(out -
 370                                         (x * ICP_QAT_HW_AES_XCBC_MAC_KEY_SZ),
 371                                         0, ICP_QAT_HW_AES_XCBC_MAC_STATE2_SZ);
 372                                 return -EFAULT;
 373                         }
 374                         AES_encrypt(in, out, &enc_key);
 375                         in += ICP_QAT_HW_AES_XCBC_MAC_KEY_SZ;
 376                         out += ICP_QAT_HW_AES_XCBC_MAC_KEY_SZ;
 377                 }
 378                 *p_state_len = ICP_QAT_HW_AES_XCBC_MAC_STATE2_SZ;
 379                 rte_free(in - x*ICP_QAT_HW_AES_XCBC_MAC_KEY_SZ);
 380                 return 0;
 381         } else if ((hash_alg == ICP_QAT_HW_AUTH_ALGO_GALOIS_128) ||
 382                 (hash_alg == ICP_QAT_HW_AUTH_ALGO_GALOIS_64)) {
 383                 uint8_t *in = NULL;
 384                 uint8_t *out = p_state_buf;
 385                 AES_KEY enc_key;
 386
 387                 memset(p_state_buf, 0, ICP_QAT_HW_GALOIS_H_SZ +
 388                                 ICP_QAT_HW_GALOIS_LEN_A_SZ +
 389                                 ICP_QAT_HW_GALOIS_E_CTR0_SZ);
 390                 in = rte_zmalloc("working mem for key",
 391                                 ICP_QAT_HW_GALOIS_H_SZ, 16);
 392                 memset(in, 0, ICP_QAT_HW_GALOIS_H_SZ);
 393                 if (AES_set_encrypt_key(auth_key, auth_keylen << 3,
 394                         &enc_key) != 0) {
 395                         return -EFAULT;
 396                 }
 397                 AES_encrypt(in, out, &enc_key);
 398                 *p_state_len = ICP_QAT_HW_GALOIS_H_SZ +
 399                                 ICP_QAT_HW_GALOIS_LEN_A_SZ +
 400                                 ICP_QAT_HW_GALOIS_E_CTR0_SZ;
 401                 rte_free(in);
 402                 return 0;
 403         }
 404
 405         block_size = qat_hash_get_block_size(hash_alg);
 406         if (block_size <= 0)
 407                 return -EFAULT;
 408         /* init ipad and opad from key and xor with fixed values */
 409         memset(ipad, 0, block_size);
 410         memset(opad, 0, block_size);
 411
 412         if (auth_keylen > (unsigned int)block_size) {
 413                 PMD_DRV_LOG(ERR, "invalid keylen %u", auth_keylen);
 414                 return -EFAULT;
 415         }
 416         rte_memcpy(ipad, auth_key, auth_keylen);
 417         rte_memcpy(opad, auth_key, auth_keylen);
 418
 419         for (i = 0; i < block_size; i++) {
 420                 uint8_t *ipad_ptr = ipad + i;
 421                 uint8_t *opad_ptr = opad + i;
 422                 *ipad_ptr ^= HMAC_IPAD_VALUE;
 423                 *opad_ptr ^= HMAC_OPAD_VALUE;
 424         }
 425
 426         /* do partial hash of ipad and copy to state1 */
 427         if (partial_hash_compute(hash_alg, ipad, p_state_buf)) {
 428                 memset(ipad, 0, block_size);
 429                 memset(opad, 0, block_size);
 430                 PMD_DRV_LOG(ERR, "ipad precompute failed");
 431                 return -EFAULT;
 432         }
 433
 434         /*
 435          * State len is a multiple of 8, so may be larger than the digest.
 436          * Put the partial hash of opad state_len bytes after state1
 437          */
 438         *p_state_len = qat_hash_get_state1_size(hash_alg);
 439         if (partial_hash_compute(hash_alg, opad, p_state_buf + *p_state_len)) {
 440                 memset(ipad, 0, block_size);
 441                 memset(opad, 0, block_size);
 442                 PMD_DRV_LOG(ERR, "opad precompute failed");
 443                 return -EFAULT;
 444         }
 445
 446         /*  don't leave data lying around */
 447         memset(ipad, 0, block_size);
 448         memset(opad, 0, block_size);
 449         return 0;
 450 }
 451
 452 void qat_alg_init_common_hdr(struct icp_qat_fw_comn_req_hdr *header,
 453                 enum qat_crypto_proto_flag proto_flags)
 454 {
 455         PMD_INIT_FUNC_TRACE();
 456         header->hdr_flags =
 457                 ICP_QAT_FW_COMN_HDR_FLAGS_BUILD(ICP_QAT_FW_COMN_REQ_FLAG_SET);
 458         header->service_type = ICP_QAT_FW_COMN_REQ_CPM_FW_LA;
 459         header->comn_req_flags =
 460                 ICP_QAT_FW_COMN_FLAGS_BUILD(QAT_COMN_CD_FLD_TYPE_64BIT_ADR,
 461                                         QAT_COMN_PTR_TYPE_FLAT);
 462         ICP_QAT_FW_LA_PARTIAL_SET(header->serv_specif_flags,
 463                                   ICP_QAT_FW_LA_PARTIAL_NONE);
 464         ICP_QAT_FW_LA_CIPH_IV_FLD_FLAG_SET(header->serv_specif_flags,
 465                                            ICP_QAT_FW_CIPH_IV_16BYTE_DATA);
 466
 467         switch (proto_flags)            {
 468         case QAT_CRYPTO_PROTO_FLAG_NONE:
 469                 ICP_QAT_FW_LA_PROTO_SET(header->serv_specif_flags,
 470                                         ICP_QAT_FW_LA_NO_PROTO);
 471                 break;
 472         case QAT_CRYPTO_PROTO_FLAG_CCM:
 473                 ICP_QAT_FW_LA_PROTO_SET(header->serv_specif_flags,
 474                                         ICP_QAT_FW_LA_CCM_PROTO);
 475                 break;
 476         case QAT_CRYPTO_PROTO_FLAG_GCM:
 477                 ICP_QAT_FW_LA_PROTO_SET(header->serv_specif_flags,
 478                                         ICP_QAT_FW_LA_GCM_PROTO);
 479                 break;
 480         case QAT_CRYPTO_PROTO_FLAG_SNOW3G:
 481                 ICP_QAT_FW_LA_PROTO_SET(header->serv_specif_flags,
 482                                         ICP_QAT_FW_LA_SNOW_3G_PROTO);
 483                 break;
 484         case QAT_CRYPTO_PROTO_FLAG_ZUC:
 485                 ICP_QAT_FW_LA_ZUC_3G_PROTO_FLAG_SET(header->serv_specif_flags,
 486                         ICP_QAT_FW_LA_ZUC_3G_PROTO);
 487                 break;
 488         }
 489
 490         ICP_QAT_FW_LA_UPDATE_STATE_SET(header->serv_specif_flags,
 491                                            ICP_QAT_FW_LA_NO_UPDATE_STATE);
 492         ICP_QAT_FW_LA_DIGEST_IN_BUFFER_SET(header->serv_specif_flags,
 493                                         ICP_QAT_FW_LA_NO_DIGEST_IN_BUFFER);
 494 }
 495
 496 /*
 497  *      Snow3G and ZUC should never use this function
 498  *      and set its protocol flag in both cipher and auth part of content
 499  *      descriptor building function
 500  */
 501 static enum qat_crypto_proto_flag
 502 qat_get_crypto_proto_flag(uint16_t flags)
 503 {
 504         int proto = ICP_QAT_FW_LA_PROTO_GET(flags);
 505         enum qat_crypto_proto_flag qat_proto_flag =
 506                         QAT_CRYPTO_PROTO_FLAG_NONE;
 507
 508         switch (proto) {
 509         case ICP_QAT_FW_LA_GCM_PROTO:
 510                 qat_proto_flag = QAT_CRYPTO_PROTO_FLAG_GCM;
 511                 break;
 512         case ICP_QAT_FW_LA_CCM_PROTO:
 513                 qat_proto_flag = QAT_CRYPTO_PROTO_FLAG_CCM;
 514                 break;
 515         }
 516
 517         return qat_proto_flag;
 518 }
 519
 520 int qat_alg_aead_session_create_content_desc_cipher(struct qat_session *cdesc,
 521                                                 uint8_t *cipherkey,
 522                                                 uint32_t cipherkeylen)
 523 {
 524         struct icp_qat_hw_cipher_algo_blk *cipher;
 525         struct icp_qat_fw_la_bulk_req *req_tmpl = &cdesc->fw_req;
 526         struct icp_qat_fw_comn_req_hdr_cd_pars *cd_pars = &req_tmpl->cd_pars;
 527         struct icp_qat_fw_comn_req_hdr *header = &req_tmpl->comn_hdr;
 528         void *ptr = &req_tmpl->cd_ctrl;
 529         struct icp_qat_fw_cipher_cd_ctrl_hdr *cipher_cd_ctrl = ptr;
 530         struct icp_qat_fw_auth_cd_ctrl_hdr *hash_cd_ctrl = ptr;
 531         enum icp_qat_hw_cipher_convert key_convert;
 532         enum qat_crypto_proto_flag qat_proto_flag =
 533                 QAT_CRYPTO_PROTO_FLAG_NONE;
 534         uint32_t total_key_size;
 535         uint16_t cipher_offset, cd_size;
 536         uint32_t wordIndex  = 0;
 537         uint32_t *temp_key = NULL;
 538         PMD_INIT_FUNC_TRACE();
 539
 540         if (cdesc->qat_cmd == ICP_QAT_FW_LA_CMD_CIPHER) {
 541                 cd_pars->u.s.content_desc_addr = cdesc->cd_paddr;
 542                 ICP_QAT_FW_COMN_CURR_ID_SET(cipher_cd_ctrl,
 543                                         ICP_QAT_FW_SLICE_CIPHER);
 544                 ICP_QAT_FW_COMN_NEXT_ID_SET(cipher_cd_ctrl,
 545                                         ICP_QAT_FW_SLICE_DRAM_WR);
 546                 ICP_QAT_FW_LA_RET_AUTH_SET(header->serv_specif_flags,
 547                                         ICP_QAT_FW_LA_NO_RET_AUTH_RES);
 548                 ICP_QAT_FW_LA_CMP_AUTH_SET(header->serv_specif_flags,
 549                                         ICP_QAT_FW_LA_NO_CMP_AUTH_RES);
 550                 cdesc->cd_cur_ptr = (uint8_t *)&cdesc->cd;
 551         } else if (cdesc->qat_cmd == ICP_QAT_FW_LA_CMD_CIPHER_HASH) {
 552                 cd_pars->u.s.content_desc_addr = cdesc->cd_paddr;
 553                 ICP_QAT_FW_COMN_CURR_ID_SET(cipher_cd_ctrl,
 554                                         ICP_QAT_FW_SLICE_CIPHER);
 555                 ICP_QAT_FW_COMN_NEXT_ID_SET(cipher_cd_ctrl,
 556                                         ICP_QAT_FW_SLICE_AUTH);
 557                 ICP_QAT_FW_COMN_CURR_ID_SET(hash_cd_ctrl,
 558                                         ICP_QAT_FW_SLICE_AUTH);
 559                 ICP_QAT_FW_COMN_NEXT_ID_SET(hash_cd_ctrl,
 560                                         ICP_QAT_FW_SLICE_DRAM_WR);
 561                 cdesc->cd_cur_ptr = (uint8_t *)&cdesc->cd;
 562         } else if (cdesc->qat_cmd != ICP_QAT_FW_LA_CMD_HASH_CIPHER) {
 563                 PMD_DRV_LOG(ERR, "Invalid param, must be a cipher command.");
 564                 return -EFAULT;
 565         }
 566
 567         if (cdesc->qat_mode == ICP_QAT_HW_CIPHER_CTR_MODE) {
 568                 /*
 569                  * CTR Streaming ciphers are a special case. Decrypt = encrypt
 570                  * Overriding default values previously set
 571                  */
 572                 cdesc->qat_dir = ICP_QAT_HW_CIPHER_ENCRYPT;
 573                 key_convert = ICP_QAT_HW_CIPHER_NO_CONVERT;
 574         } else if (cdesc->qat_cipher_alg == ICP_QAT_HW_CIPHER_ALGO_SNOW_3G_UEA2
 575                 || cdesc->qat_cipher_alg ==
 576                         ICP_QAT_HW_CIPHER_ALGO_ZUC_3G_128_EEA3)
 577                 key_convert = ICP_QAT_HW_CIPHER_KEY_CONVERT;
 578         else if (cdesc->qat_dir == ICP_QAT_HW_CIPHER_ENCRYPT)
 579                 key_convert = ICP_QAT_HW_CIPHER_NO_CONVERT;
 580         else
 581                 key_convert = ICP_QAT_HW_CIPHER_KEY_CONVERT;
 582
 583         if (cdesc->qat_cipher_alg == ICP_QAT_HW_CIPHER_ALGO_SNOW_3G_UEA2) {
 584                 total_key_size = ICP_QAT_HW_SNOW_3G_UEA2_KEY_SZ +
 585                         ICP_QAT_HW_SNOW_3G_UEA2_IV_SZ;
 586                 cipher_cd_ctrl->cipher_state_sz =
 587                         ICP_QAT_HW_SNOW_3G_UEA2_IV_SZ >> 3;
 588                 qat_proto_flag = QAT_CRYPTO_PROTO_FLAG_SNOW3G;
 589
 590         } else if (cdesc->qat_cipher_alg == ICP_QAT_HW_CIPHER_ALGO_KASUMI) {
 591                 total_key_size = ICP_QAT_HW_KASUMI_F8_KEY_SZ;
 592                 cipher_cd_ctrl->cipher_state_sz = ICP_QAT_HW_KASUMI_BLK_SZ >> 3;
 593                 cipher_cd_ctrl->cipher_padding_sz =
 594                                         (2 * ICP_QAT_HW_KASUMI_BLK_SZ) >> 3;
 595         } else if (cdesc->qat_cipher_alg == ICP_QAT_HW_CIPHER_ALGO_3DES) {
 596                 total_key_size = ICP_QAT_HW_3DES_KEY_SZ;
 597                 cipher_cd_ctrl->cipher_state_sz = ICP_QAT_HW_3DES_BLK_SZ >> 3;
 598                 qat_proto_flag =
 599                         qat_get_crypto_proto_flag(header->serv_specif_flags);
 600         } else if (cdesc->qat_cipher_alg == ICP_QAT_HW_CIPHER_ALGO_DES) {
 601                 total_key_size = ICP_QAT_HW_DES_KEY_SZ;
 602                 cipher_cd_ctrl->cipher_state_sz = ICP_QAT_HW_DES_BLK_SZ >> 3;
 603                 qat_proto_flag =
 604                         qat_get_crypto_proto_flag(header->serv_specif_flags);
 605         } else if (cdesc->qat_cipher_alg ==
 606                 ICP_QAT_HW_CIPHER_ALGO_ZUC_3G_128_EEA3) {
 607                 total_key_size = ICP_QAT_HW_ZUC_3G_EEA3_KEY_SZ +
 608                         ICP_QAT_HW_ZUC_3G_EEA3_IV_SZ;
 609                 cipher_cd_ctrl->cipher_state_sz =
 610                         ICP_QAT_HW_ZUC_3G_EEA3_IV_SZ >> 3;
 611                 qat_proto_flag = QAT_CRYPTO_PROTO_FLAG_ZUC;
 612                 cdesc->min_qat_dev_gen = QAT_GEN2;
 613         } else {
 614                 total_key_size = cipherkeylen;
 615                 cipher_cd_ctrl->cipher_state_sz = ICP_QAT_HW_AES_BLK_SZ >> 3;
 616                 qat_proto_flag =
 617                         qat_get_crypto_proto_flag(header->serv_specif_flags);
 618         }
 619         cipher_cd_ctrl->cipher_key_sz = total_key_size >> 3;
 620         cipher_offset = cdesc->cd_cur_ptr-((uint8_t *)&cdesc->cd);
 621         cipher_cd_ctrl->cipher_cfg_offset = cipher_offset >> 3;
 622
 623         header->service_cmd_id = cdesc->qat_cmd;
 624         qat_alg_init_common_hdr(header, qat_proto_flag);
 625
 626         cipher = (struct icp_qat_hw_cipher_algo_blk *)cdesc->cd_cur_ptr;
 627         cipher->cipher_config.val =
 628             ICP_QAT_HW_CIPHER_CONFIG_BUILD(cdesc->qat_mode,
 629                                         cdesc->qat_cipher_alg, key_convert,
 630                                         cdesc->qat_dir);
 631
 632         if (cdesc->qat_cipher_alg == ICP_QAT_HW_CIPHER_ALGO_KASUMI) {
 633                 temp_key = (uint32_t *)(cdesc->cd_cur_ptr +
 634                                         sizeof(struct icp_qat_hw_cipher_config)
 635                                         + cipherkeylen);
 636                 memcpy(cipher->key, cipherkey, cipherkeylen);
 637                 memcpy(temp_key, cipherkey, cipherkeylen);
 638
 639                 /* XOR Key with KASUMI F8 key modifier at 4 bytes level */
 640                 for (wordIndex = 0; wordIndex < (cipherkeylen >> 2);
 641                                                                 wordIndex++)
 642                         temp_key[wordIndex] ^= KASUMI_F8_KEY_MODIFIER_4_BYTES;
 643
 644                 cdesc->cd_cur_ptr += sizeof(struct icp_qat_hw_cipher_config) +
 645                                         cipherkeylen + cipherkeylen;
 646         } else {
 647                 memcpy(cipher->key, cipherkey, cipherkeylen);
 648                 cdesc->cd_cur_ptr += sizeof(struct icp_qat_hw_cipher_config) +
 649                                         cipherkeylen;
 650         }
 651
 652         if (total_key_size > cipherkeylen) {
 653                 uint32_t padding_size =  total_key_size-cipherkeylen;
 654                 if ((cdesc->qat_cipher_alg == ICP_QAT_HW_CIPHER_ALGO_3DES)
 655                         && (cipherkeylen == QAT_3DES_KEY_SZ_OPT2))
 656                         /* K3 not provided so use K1 = K3*/
 657                         memcpy(cdesc->cd_cur_ptr, cipherkey, padding_size);
 658                 else
 659                         memset(cdesc->cd_cur_ptr, 0, padding_size);
 660                 cdesc->cd_cur_ptr += padding_size;
 661         }
 662         cd_size = cdesc->cd_cur_ptr-(uint8_t *)&cdesc->cd;
 663         cd_pars->u.s.content_desc_params_sz = RTE_ALIGN_CEIL(cd_size, 8) >> 3;
 664
 665         return 0;
 666 }
 667
 668 int qat_alg_aead_session_create_content_desc_auth(struct qat_session *cdesc,
 669                                                 uint8_t *authkey,
 670                                                 uint32_t authkeylen,
 671                                                 uint32_t aad_length,
 672                                                 uint32_t digestsize,
 673                                                 unsigned int operation)
 674 {
 675         struct icp_qat_hw_auth_setup *hash;
 676         struct icp_qat_hw_cipher_algo_blk *cipherconfig;
 677         struct icp_qat_fw_la_bulk_req *req_tmpl = &cdesc->fw_req;
 678         struct icp_qat_fw_comn_req_hdr_cd_pars *cd_pars = &req_tmpl->cd_pars;
 679         struct icp_qat_fw_comn_req_hdr *header = &req_tmpl->comn_hdr;
 680         void *ptr = &req_tmpl->cd_ctrl;
 681         struct icp_qat_fw_cipher_cd_ctrl_hdr *cipher_cd_ctrl = ptr;
 682         struct icp_qat_fw_auth_cd_ctrl_hdr *hash_cd_ctrl = ptr;
 683         struct icp_qat_fw_la_auth_req_params *auth_param =
 684                 (struct icp_qat_fw_la_auth_req_params *)
 685                 ((char *)&req_tmpl->serv_specif_rqpars +
 686                 sizeof(struct icp_qat_fw_la_cipher_req_params));
 687         uint16_t state1_size = 0, state2_size = 0;
 688         uint16_t hash_offset, cd_size;
 689         uint32_t *aad_len = NULL;
 690         uint32_t wordIndex  = 0;
 691         uint32_t *pTempKey;
 692         enum qat_crypto_proto_flag qat_proto_flag =
 693                 QAT_CRYPTO_PROTO_FLAG_NONE;
 694
 695         PMD_INIT_FUNC_TRACE();
 696
 697         if (cdesc->qat_cmd == ICP_QAT_FW_LA_CMD_AUTH) {
 698                 ICP_QAT_FW_COMN_CURR_ID_SET(hash_cd_ctrl,
 699                                         ICP_QAT_FW_SLICE_AUTH);
 700                 ICP_QAT_FW_COMN_NEXT_ID_SET(hash_cd_ctrl,
 701                                         ICP_QAT_FW_SLICE_DRAM_WR);
 702                 cdesc->cd_cur_ptr = (uint8_t *)&cdesc->cd;
 703         } else if (cdesc->qat_cmd == ICP_QAT_FW_LA_CMD_HASH_CIPHER) {
 704                 ICP_QAT_FW_COMN_CURR_ID_SET(hash_cd_ctrl,
 705                                 ICP_QAT_FW_SLICE_AUTH);
 706                 ICP_QAT_FW_COMN_NEXT_ID_SET(hash_cd_ctrl,
 707                                 ICP_QAT_FW_SLICE_CIPHER);
 708                 ICP_QAT_FW_COMN_CURR_ID_SET(cipher_cd_ctrl,
 709                                 ICP_QAT_FW_SLICE_CIPHER);
 710                 ICP_QAT_FW_COMN_NEXT_ID_SET(cipher_cd_ctrl,
 711                                 ICP_QAT_FW_SLICE_DRAM_WR);
 712                 cdesc->cd_cur_ptr = (uint8_t *)&cdesc->cd;
 713         } else if (cdesc->qat_cmd != ICP_QAT_FW_LA_CMD_CIPHER_HASH) {
 714                 PMD_DRV_LOG(ERR, "Invalid param, must be a hash command.");
 715                 return -EFAULT;
 716         }
 717
 718         if (operation == RTE_CRYPTO_AUTH_OP_VERIFY) {
 719                 ICP_QAT_FW_LA_RET_AUTH_SET(header->serv_specif_flags,
 720                                 ICP_QAT_FW_LA_NO_RET_AUTH_RES);
 721                 ICP_QAT_FW_LA_CMP_AUTH_SET(header->serv_specif_flags,
 722                                 ICP_QAT_FW_LA_CMP_AUTH_RES);
 723                 cdesc->auth_op = ICP_QAT_HW_AUTH_VERIFY;
 724         } else {
 725                 ICP_QAT_FW_LA_RET_AUTH_SET(header->serv_specif_flags,
 726                                            ICP_QAT_FW_LA_RET_AUTH_RES);
 727                 ICP_QAT_FW_LA_CMP_AUTH_SET(header->serv_specif_flags,
 728                                            ICP_QAT_FW_LA_NO_CMP_AUTH_RES);
 729                 cdesc->auth_op = ICP_QAT_HW_AUTH_GENERATE;
 730         }
 731
 732         /*
 733          * Setup the inner hash config
 734          */
 735         hash_offset = cdesc->cd_cur_ptr-((uint8_t *)&cdesc->cd);
 736         hash = (struct icp_qat_hw_auth_setup *)cdesc->cd_cur_ptr;
 737         hash->auth_config.reserved = 0;
 738         hash->auth_config.config =
 739                         ICP_QAT_HW_AUTH_CONFIG_BUILD(ICP_QAT_HW_AUTH_MODE1,
 740                                 cdesc->qat_hash_alg, digestsize);
 741
 742         if (cdesc->qat_hash_alg == ICP_QAT_HW_AUTH_ALGO_SNOW_3G_UIA2
 743                 || cdesc->qat_hash_alg == ICP_QAT_HW_AUTH_ALGO_KASUMI_F9
 744                 || cdesc->qat_hash_alg == ICP_QAT_HW_AUTH_ALGO_ZUC_3G_128_EIA3)
 745                 hash->auth_counter.counter = 0;
 746         else
 747                 hash->auth_counter.counter = rte_bswap32(
 748                                 qat_hash_get_block_size(cdesc->qat_hash_alg));
 749
 750         cdesc->cd_cur_ptr += sizeof(struct icp_qat_hw_auth_setup);
 751
 752         /*
 753          * cd_cur_ptr now points at the state1 information.
 754          */
 755         switch (cdesc->qat_hash_alg) {
 756         case ICP_QAT_HW_AUTH_ALGO_SHA1:
 757                 if (qat_alg_do_precomputes(ICP_QAT_HW_AUTH_ALGO_SHA1,
 758                         authkey, authkeylen, cdesc->cd_cur_ptr, &state1_size)) {
 759                         PMD_DRV_LOG(ERR, "(SHA)precompute failed");
 760                         return -EFAULT;
 761                 }
 762                 state2_size = RTE_ALIGN_CEIL(ICP_QAT_HW_SHA1_STATE2_SZ, 8);
 763                 break;
 764         case ICP_QAT_HW_AUTH_ALGO_SHA224:
 765                 if (qat_alg_do_precomputes(ICP_QAT_HW_AUTH_ALGO_SHA224,
 766                         authkey, authkeylen, cdesc->cd_cur_ptr, &state1_size)) {
 767                         PMD_DRV_LOG(ERR, "(SHA)precompute failed");
 768                         return -EFAULT;
 769                 }
 770                 state2_size = ICP_QAT_HW_SHA224_STATE2_SZ;
 771                 break;
 772         case ICP_QAT_HW_AUTH_ALGO_SHA256:
 773                 if (qat_alg_do_precomputes(ICP_QAT_HW_AUTH_ALGO_SHA256,
 774                         authkey, authkeylen, cdesc->cd_cur_ptr, &state1_size)) {
 775                         PMD_DRV_LOG(ERR, "(SHA)precompute failed");
 776                         return -EFAULT;
 777                 }
 778                 state2_size = ICP_QAT_HW_SHA256_STATE2_SZ;
 779                 break;
 780         case ICP_QAT_HW_AUTH_ALGO_SHA384:
 781                 if (qat_alg_do_precomputes(ICP_QAT_HW_AUTH_ALGO_SHA384,
 782                         authkey, authkeylen, cdesc->cd_cur_ptr, &state1_size)) {
 783                         PMD_DRV_LOG(ERR, "(SHA)precompute failed");
 784                         return -EFAULT;
 785                 }
 786                 state2_size = ICP_QAT_HW_SHA384_STATE2_SZ;
 787                 break;
 788         case ICP_QAT_HW_AUTH_ALGO_SHA512:
 789                 if (qat_alg_do_precomputes(ICP_QAT_HW_AUTH_ALGO_SHA512,
 790                         authkey, authkeylen, cdesc->cd_cur_ptr, &state1_size)) {
 791                         PMD_DRV_LOG(ERR, "(SHA)precompute failed");
 792                         return -EFAULT;
 793                 }
 794                 state2_size = ICP_QAT_HW_SHA512_STATE2_SZ;
 795                 break;
 796         case ICP_QAT_HW_AUTH_ALGO_AES_XCBC_MAC:
 797                 state1_size = ICP_QAT_HW_AES_XCBC_MAC_STATE1_SZ;
 798                 if (qat_alg_do_precomputes(ICP_QAT_HW_AUTH_ALGO_AES_XCBC_MAC,
 799                         authkey, authkeylen, cdesc->cd_cur_ptr + state1_size,
 800                         &state2_size)) {
 801                         PMD_DRV_LOG(ERR, "(XCBC)precompute failed");
 802                         return -EFAULT;
 803                 }
 804                 break;
 805         case ICP_QAT_HW_AUTH_ALGO_GALOIS_128:
 806         case ICP_QAT_HW_AUTH_ALGO_GALOIS_64:
 807                 qat_proto_flag = QAT_CRYPTO_PROTO_FLAG_GCM;
 808                 state1_size = ICP_QAT_HW_GALOIS_128_STATE1_SZ;
 809                 if (qat_alg_do_precomputes(cdesc->qat_hash_alg,
 810                         authkey, authkeylen, cdesc->cd_cur_ptr + state1_size,
 811                         &state2_size)) {
 812                         PMD_DRV_LOG(ERR, "(GCM)precompute failed");
 813                         return -EFAULT;
 814                 }
 815                 /*
 816                  * Write (the length of AAD) into bytes 16-19 of state2
 817                  * in big-endian format. This field is 8 bytes
 818                  */
 819                 auth_param->u2.aad_sz =
 820                                 RTE_ALIGN_CEIL(aad_length, 16);
 821                 auth_param->hash_state_sz = (auth_param->u2.aad_sz) >> 3;
 822
 823                 aad_len = (uint32_t *)(cdesc->cd_cur_ptr +
 824                                         ICP_QAT_HW_GALOIS_128_STATE1_SZ +
 825                                         ICP_QAT_HW_GALOIS_H_SZ);
 826                 *aad_len = rte_bswap32(aad_length);
 827                 cdesc->aad_len = aad_length;
 828                 break;
 829         case ICP_QAT_HW_AUTH_ALGO_SNOW_3G_UIA2:
 830                 qat_proto_flag = QAT_CRYPTO_PROTO_FLAG_SNOW3G;
 831                 state1_size = qat_hash_get_state1_size(
 832                                 ICP_QAT_HW_AUTH_ALGO_SNOW_3G_UIA2);
 833                 state2_size = ICP_QAT_HW_SNOW_3G_UIA2_STATE2_SZ;
 834                 memset(cdesc->cd_cur_ptr, 0, state1_size + state2_size);
 835
 836                 cipherconfig = (struct icp_qat_hw_cipher_algo_blk *)
 837                                 (cdesc->cd_cur_ptr + state1_size + state2_size);
 838                 cipherconfig->cipher_config.val =
 839                 ICP_QAT_HW_CIPHER_CONFIG_BUILD(ICP_QAT_HW_CIPHER_ECB_MODE,
 840                         ICP_QAT_HW_CIPHER_ALGO_SNOW_3G_UEA2,
 841                         ICP_QAT_HW_CIPHER_KEY_CONVERT,
 842                         ICP_QAT_HW_CIPHER_ENCRYPT);
 843                 memcpy(cipherconfig->key, authkey, authkeylen);
 844                 memset(cipherconfig->key + authkeylen,
 845                                 0, ICP_QAT_HW_SNOW_3G_UEA2_IV_SZ);
 846                 cdesc->cd_cur_ptr += sizeof(struct icp_qat_hw_cipher_config) +
 847                                 authkeylen + ICP_QAT_HW_SNOW_3G_UEA2_IV_SZ;
 848                 auth_param->hash_state_sz = ICP_QAT_HW_SNOW_3G_UEA2_IV_SZ >> 3;
 849                 break;
 850         case ICP_QAT_HW_AUTH_ALGO_ZUC_3G_128_EIA3:
 851                 hash->auth_config.config =
 852                         ICP_QAT_HW_AUTH_CONFIG_BUILD(ICP_QAT_HW_AUTH_MODE0,
 853                                 cdesc->qat_hash_alg, digestsize);
 854                 qat_proto_flag = QAT_CRYPTO_PROTO_FLAG_ZUC;
 855                 state1_size = qat_hash_get_state1_size(
 856                                 ICP_QAT_HW_AUTH_ALGO_ZUC_3G_128_EIA3);
 857                 state2_size = ICP_QAT_HW_ZUC_3G_EIA3_STATE2_SZ;
 858                 memset(cdesc->cd_cur_ptr, 0, state1_size + state2_size
 859                         + ICP_QAT_HW_ZUC_3G_EEA3_IV_SZ);
 860
 861                 memcpy(cdesc->cd_cur_ptr + state1_size, authkey, authkeylen);
 862                 cdesc->cd_cur_ptr += state1_size + state2_size
 863                         + ICP_QAT_HW_ZUC_3G_EEA3_IV_SZ;
 864                 auth_param->hash_state_sz = ICP_QAT_HW_ZUC_3G_EEA3_IV_SZ >> 3;
 865                 cdesc->min_qat_dev_gen = QAT_GEN2;
 866
 867                 break;
 868         case ICP_QAT_HW_AUTH_ALGO_MD5:
 869                 if (qat_alg_do_precomputes(ICP_QAT_HW_AUTH_ALGO_MD5,
 870                         authkey, authkeylen, cdesc->cd_cur_ptr,
 871                         &state1_size)) {
 872                         PMD_DRV_LOG(ERR, "(MD5)precompute failed");
 873                         return -EFAULT;
 874                 }
 875                 state2_size = ICP_QAT_HW_MD5_STATE2_SZ;
 876                 break;
 877         case ICP_QAT_HW_AUTH_ALGO_NULL:
 878                 state1_size = qat_hash_get_state1_size(
 879                                 ICP_QAT_HW_AUTH_ALGO_NULL);
 880                 state2_size = ICP_QAT_HW_NULL_STATE2_SZ;
 881                 break;
 882         case ICP_QAT_HW_AUTH_ALGO_AES_CBC_MAC:
 883                 qat_proto_flag = QAT_CRYPTO_PROTO_FLAG_CCM;
 884                 state1_size = qat_hash_get_state1_size(
 885                                 ICP_QAT_HW_AUTH_ALGO_AES_CBC_MAC);
 886                 state2_size = ICP_QAT_HW_AES_CBC_MAC_KEY_SZ +
 887                                 ICP_QAT_HW_AES_CCM_CBC_E_CTR0_SZ;
 888
 889                 if (aad_length > 0) {
 890                         aad_length += ICP_QAT_HW_CCM_AAD_B0_LEN +
 891                                 ICP_QAT_HW_CCM_AAD_LEN_INFO;
 892                         auth_param->u2.aad_sz =
 893                                         RTE_ALIGN_CEIL(aad_length,
 894                                         ICP_QAT_HW_CCM_AAD_ALIGNMENT);
 895                 } else {
 896                         auth_param->u2.aad_sz = ICP_QAT_HW_CCM_AAD_B0_LEN;
 897                 }
 898
 899                 cdesc->aad_len = aad_length;
 900                 hash->auth_counter.counter = 0;
 901
 902                 hash_cd_ctrl->outer_prefix_sz = digestsize;
 903                 auth_param->hash_state_sz = digestsize;
 904
 905                 memcpy(cdesc->cd_cur_ptr + state1_size, authkey, authkeylen);
 906                 break;
 907         case ICP_QAT_HW_AUTH_ALGO_KASUMI_F9:
 908                 state1_size = qat_hash_get_state1_size(
 909                                 ICP_QAT_HW_AUTH_ALGO_KASUMI_F9);
 910                 state2_size = ICP_QAT_HW_KASUMI_F9_STATE2_SZ;
 911                 memset(cdesc->cd_cur_ptr, 0, state1_size + state2_size);
 912                 pTempKey = (uint32_t *)(cdesc->cd_cur_ptr + state1_size
 913                                                         + authkeylen);
 914                 /*
 915                 * The Inner Hash Initial State2 block must contain IK
 916                 * (Initialisation Key), followed by IK XOR-ed with KM
 917                 * (Key Modifier): IK||(IK^KM).
 918                 */
 919                 /* write the auth key */
 920                 memcpy(cdesc->cd_cur_ptr + state1_size, authkey, authkeylen);
 921                 /* initialise temp key with auth key */
 922                 memcpy(pTempKey, authkey, authkeylen);
 923                 /* XOR Key with KASUMI F9 key modifier at 4 bytes level */
 924                 for (wordIndex = 0; wordIndex < (authkeylen >> 2); wordIndex++)
 925                         pTempKey[wordIndex] ^= KASUMI_F9_KEY_MODIFIER_4_BYTES;
 926                 break;
 927         default:
 928                 PMD_DRV_LOG(ERR, "Invalid HASH alg %u", cdesc->qat_hash_alg);
 929                 return -EFAULT;
 930         }
 931
 932         /* Request template setup */
 933         qat_alg_init_common_hdr(header, qat_proto_flag);
 934         header->service_cmd_id = cdesc->qat_cmd;
 935
 936         /* Auth CD config setup */
 937         hash_cd_ctrl->hash_cfg_offset = hash_offset >> 3;
 938         hash_cd_ctrl->hash_flags = ICP_QAT_FW_AUTH_HDR_FLAG_NO_NESTED;
 939         hash_cd_ctrl->inner_res_sz = digestsize;
 940         hash_cd_ctrl->final_sz = digestsize;
 941         hash_cd_ctrl->inner_state1_sz = state1_size;
 942         auth_param->auth_res_sz = digestsize;
 943
 944         hash_cd_ctrl->inner_state2_sz  = state2_size;
 945         hash_cd_ctrl->inner_state2_offset = hash_cd_ctrl->hash_cfg_offset +
 946                         ((sizeof(struct icp_qat_hw_auth_setup) +
 947                          RTE_ALIGN_CEIL(hash_cd_ctrl->inner_state1_sz, 8))
 948                                         >> 3);
 949
 950         cdesc->cd_cur_ptr += state1_size + state2_size;
 951         cd_size = cdesc->cd_cur_ptr-(uint8_t *)&cdesc->cd;
 952
 953         cd_pars->u.s.content_desc_addr = cdesc->cd_paddr;
 954         cd_pars->u.s.content_desc_params_sz = RTE_ALIGN_CEIL(cd_size, 8) >> 3;
 955
 956         return 0;
 957 }
 958
 959 int qat_alg_validate_aes_key(int key_len, enum icp_qat_hw_cipher_algo *alg)
 960 {
 961         switch (key_len) {
 962         case ICP_QAT_HW_AES_128_KEY_SZ:
 963                 *alg = ICP_QAT_HW_CIPHER_ALGO_AES128;
 964                 break;
 965         case ICP_QAT_HW_AES_192_KEY_SZ:
 966                 *alg = ICP_QAT_HW_CIPHER_ALGO_AES192;
 967                 break;
 968         case ICP_QAT_HW_AES_256_KEY_SZ:
 969                 *alg = ICP_QAT_HW_CIPHER_ALGO_AES256;
 970                 break;
 971         default:
 972                 return -EINVAL;
 973         }
 974         return 0;
 975 }
 976
 977 int qat_alg_validate_aes_docsisbpi_key(int key_len,
 978                 enum icp_qat_hw_cipher_algo *alg)
 979 {
 980         switch (key_len) {
 981         case ICP_QAT_HW_AES_128_KEY_SZ:
 982                 *alg = ICP_QAT_HW_CIPHER_ALGO_AES128;
 983                 break;
 984         default:
 985                 return -EINVAL;
 986         }
 987         return 0;
 988 }
 989
 990 int qat_alg_validate_snow3g_key(int key_len, enum icp_qat_hw_cipher_algo *alg)
 991 {
 992         switch (key_len) {
 993         case ICP_QAT_HW_SNOW_3G_UEA2_KEY_SZ:
 994                 *alg = ICP_QAT_HW_CIPHER_ALGO_SNOW_3G_UEA2;
 995                 break;
 996         default:
 997                 return -EINVAL;
 998         }
 999         return 0;
1000 }
1001
1002 int qat_alg_validate_kasumi_key(int key_len, enum icp_qat_hw_cipher_algo *alg)
1003 {
1004         switch (key_len) {
1005         case ICP_QAT_HW_KASUMI_KEY_SZ:
1006                 *alg = ICP_QAT_HW_CIPHER_ALGO_KASUMI;
1007                 break;
1008         default:
1009                 return -EINVAL;
1010         }
1011         return 0;
1012 }
1013
1014 int qat_alg_validate_des_key(int key_len, enum icp_qat_hw_cipher_algo *alg)
1015 {
1016         switch (key_len) {
1017         case ICP_QAT_HW_DES_KEY_SZ:
1018                 *alg = ICP_QAT_HW_CIPHER_ALGO_DES;
1019                 break;
1020         default:
1021                 return -EINVAL;
1022         }
1023         return 0;
1024 }
1025
1026 int qat_alg_validate_3des_key(int key_len, enum icp_qat_hw_cipher_algo *alg)
1027 {
1028         switch (key_len) {
1029         case QAT_3DES_KEY_SZ_OPT1:
1030         case QAT_3DES_KEY_SZ_OPT2:
1031                 *alg = ICP_QAT_HW_CIPHER_ALGO_3DES;
1032                 break;
1033         default:
1034                 return -EINVAL;
1035         }
1036         return 0;
1037 }
1038
1039 int qat_alg_validate_zuc_key(int key_len, enum icp_qat_hw_cipher_algo *alg)
1040 {
1041         switch (key_len) {
1042         case ICP_QAT_HW_ZUC_3G_EEA3_KEY_SZ:
1043                 *alg = ICP_QAT_HW_CIPHER_ALGO_ZUC_3G_128_EEA3;
1044                 break;
1045         default:
1046                 return -EINVAL;
1047         }
1048         return 0;
1049 }