4 * Copyright(c) 2015-2017 Intel Corporation. All rights reserved.
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
11 * * Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * * Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in
15 * the documentation and/or other materials provided with the
17 * * Neither the name of Intel Corporation nor the names of its
18 * contributors may be used to endorse or promote products derived
19 * from this software without specific prior written permission.
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
22 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
23 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
24 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
25 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40 #include <sys/queue.h>
43 #include <rte_common.h>
45 #include <rte_debug.h>
46 #include <rte_memory.h>
47 #include <rte_memzone.h>
48 #include <rte_tailq.h>
49 #include <rte_ether.h>
50 #include <rte_malloc.h>
51 #include <rte_launch.h>
53 #include <rte_per_lcore.h>
54 #include <rte_lcore.h>
55 #include <rte_atomic.h>
56 #include <rte_branch_prediction.h>
57 #include <rte_mempool.h>
59 #include <rte_string_fns.h>
60 #include <rte_spinlock.h>
61 #include <rte_hexdump.h>
62 #include <rte_crypto_sym.h>
63 #include <rte_cryptodev_pci.h>
64 #include <openssl/evp.h>
68 #include "qat_crypto.h"
69 #include "adf_transport_access_macros.h"
74 qat_is_cipher_alg_supported(enum rte_crypto_cipher_algorithm algo,
75 struct qat_pmd_private *internals) {
77 const struct rte_cryptodev_capabilities *capability;
79 while ((capability = &(internals->qat_dev_capabilities[i++]))->op !=
80 RTE_CRYPTO_OP_TYPE_UNDEFINED) {
81 if (capability->op != RTE_CRYPTO_OP_TYPE_SYMMETRIC)
84 if (capability->sym.xform_type != RTE_CRYPTO_SYM_XFORM_CIPHER)
87 if (capability->sym.cipher.algo == algo)
94 qat_is_auth_alg_supported(enum rte_crypto_auth_algorithm algo,
95 struct qat_pmd_private *internals) {
97 const struct rte_cryptodev_capabilities *capability;
99 while ((capability = &(internals->qat_dev_capabilities[i++]))->op !=
100 RTE_CRYPTO_OP_TYPE_UNDEFINED) {
101 if (capability->op != RTE_CRYPTO_OP_TYPE_SYMMETRIC)
104 if (capability->sym.xform_type != RTE_CRYPTO_SYM_XFORM_AUTH)
107 if (capability->sym.auth.algo == algo)
113 /** Encrypt a single partial block
114 * Depends on openssl libcrypto
115 * Uses ECB+XOR to do CFB encryption, same result, more performant
118 bpi_cipher_encrypt(uint8_t *src, uint8_t *dst,
119 uint8_t *iv, int ivlen, int srclen,
122 EVP_CIPHER_CTX *ctx = (EVP_CIPHER_CTX *)bpi_ctx;
124 uint8_t encrypted_iv[16];
127 /* ECB method: encrypt the IV, then XOR this with plaintext */
128 if (EVP_EncryptUpdate(ctx, encrypted_iv, &encrypted_ivlen, iv, ivlen)
130 goto cipher_encrypt_err;
132 for (i = 0; i < srclen; i++)
133 *(dst+i) = *(src+i)^(encrypted_iv[i]);
138 PMD_DRV_LOG(ERR, "libcrypto ECB cipher encrypt failed");
142 /** Decrypt a single partial block
143 * Depends on openssl libcrypto
144 * Uses ECB+XOR to do CFB encryption, same result, more performant
147 bpi_cipher_decrypt(uint8_t *src, uint8_t *dst,
148 uint8_t *iv, int ivlen, int srclen,
151 EVP_CIPHER_CTX *ctx = (EVP_CIPHER_CTX *)bpi_ctx;
153 uint8_t encrypted_iv[16];
156 /* ECB method: encrypt (not decrypt!) the IV, then XOR with plaintext */
157 if (EVP_EncryptUpdate(ctx, encrypted_iv, &encrypted_ivlen, iv, ivlen)
159 goto cipher_decrypt_err;
161 for (i = 0; i < srclen; i++)
162 *(dst+i) = *(src+i)^(encrypted_iv[i]);
167 PMD_DRV_LOG(ERR, "libcrypto ECB cipher encrypt for BPI IV failed");
171 /** Creates a context in either AES or DES in ECB mode
172 * Depends on openssl libcrypto
175 bpi_cipher_ctx_init(enum rte_crypto_cipher_algorithm cryptodev_algo,
176 enum rte_crypto_cipher_operation direction __rte_unused,
177 uint8_t *key, void **ctx)
179 const EVP_CIPHER *algo = NULL;
181 *ctx = EVP_CIPHER_CTX_new();
188 if (cryptodev_algo == RTE_CRYPTO_CIPHER_DES_DOCSISBPI)
189 algo = EVP_des_ecb();
191 algo = EVP_aes_128_ecb();
193 /* IV will be ECB encrypted whether direction is encrypt or decrypt*/
194 if (EVP_EncryptInit_ex(*ctx, algo, NULL, key, 0) != 1) {
203 EVP_CIPHER_CTX_free(*ctx);
207 /** Frees a context previously created
208 * Depends on openssl libcrypto
211 bpi_cipher_ctx_free(void *bpi_ctx)
214 EVP_CIPHER_CTX_free((EVP_CIPHER_CTX *)bpi_ctx);
217 static inline uint32_t
218 adf_modulo(uint32_t data, uint32_t shift);
221 qat_write_hw_desc_entry(struct rte_crypto_op *op, uint8_t *out_msg,
222 struct qat_crypto_op_cookie *qat_op_cookie, struct qat_qp *qp);
225 qat_crypto_sym_clear_session(struct rte_cryptodev *dev,
226 struct rte_cryptodev_sym_session *sess)
228 PMD_INIT_FUNC_TRACE();
229 uint8_t index = dev->driver_id;
230 void *sess_priv = get_session_private_data(sess, index);
231 struct qat_session *s = (struct qat_session *)sess_priv;
235 bpi_cipher_ctx_free(s->bpi_ctx);
236 memset(s, 0, qat_crypto_sym_get_session_private_size(dev));
237 struct rte_mempool *sess_mp = rte_mempool_from_obj(sess_priv);
238 set_session_private_data(sess, index, NULL);
239 rte_mempool_put(sess_mp, sess_priv);
244 qat_get_cmd_id(const struct rte_crypto_sym_xform *xform)
247 if (xform->type == RTE_CRYPTO_SYM_XFORM_CIPHER && xform->next == NULL)
248 return ICP_QAT_FW_LA_CMD_CIPHER;
250 /* Authentication Only */
251 if (xform->type == RTE_CRYPTO_SYM_XFORM_AUTH && xform->next == NULL)
252 return ICP_QAT_FW_LA_CMD_AUTH;
255 if (xform->type == RTE_CRYPTO_SYM_XFORM_AEAD) {
256 if (xform->aead.op == RTE_CRYPTO_AEAD_OP_ENCRYPT)
257 return ICP_QAT_FW_LA_CMD_CIPHER_HASH;
259 return ICP_QAT_FW_LA_CMD_HASH_CIPHER;
262 if (xform->next == NULL)
265 /* Cipher then Authenticate */
266 if (xform->type == RTE_CRYPTO_SYM_XFORM_CIPHER &&
267 xform->next->type == RTE_CRYPTO_SYM_XFORM_AUTH)
268 return ICP_QAT_FW_LA_CMD_CIPHER_HASH;
270 /* Authenticate then Cipher */
271 if (xform->type == RTE_CRYPTO_SYM_XFORM_AUTH &&
272 xform->next->type == RTE_CRYPTO_SYM_XFORM_CIPHER)
273 return ICP_QAT_FW_LA_CMD_HASH_CIPHER;
278 static struct rte_crypto_auth_xform *
279 qat_get_auth_xform(struct rte_crypto_sym_xform *xform)
282 if (xform->type == RTE_CRYPTO_SYM_XFORM_AUTH)
291 static struct rte_crypto_cipher_xform *
292 qat_get_cipher_xform(struct rte_crypto_sym_xform *xform)
295 if (xform->type == RTE_CRYPTO_SYM_XFORM_CIPHER)
296 return &xform->cipher;
305 qat_crypto_sym_configure_session_cipher(struct rte_cryptodev *dev,
306 struct rte_crypto_sym_xform *xform,
307 struct qat_session *session)
309 struct qat_pmd_private *internals = dev->data->dev_private;
310 struct rte_crypto_cipher_xform *cipher_xform = NULL;
313 /* Get cipher xform from crypto xform chain */
314 cipher_xform = qat_get_cipher_xform(xform);
316 session->cipher_iv.offset = cipher_xform->iv.offset;
317 session->cipher_iv.length = cipher_xform->iv.length;
319 switch (cipher_xform->algo) {
320 case RTE_CRYPTO_CIPHER_AES_CBC:
321 if (qat_alg_validate_aes_key(cipher_xform->key.length,
322 &session->qat_cipher_alg) != 0) {
323 PMD_DRV_LOG(ERR, "Invalid AES cipher key size");
327 session->qat_mode = ICP_QAT_HW_CIPHER_CBC_MODE;
329 case RTE_CRYPTO_CIPHER_AES_CTR:
330 if (qat_alg_validate_aes_key(cipher_xform->key.length,
331 &session->qat_cipher_alg) != 0) {
332 PMD_DRV_LOG(ERR, "Invalid AES cipher key size");
336 session->qat_mode = ICP_QAT_HW_CIPHER_CTR_MODE;
338 case RTE_CRYPTO_CIPHER_SNOW3G_UEA2:
339 if (qat_alg_validate_snow3g_key(cipher_xform->key.length,
340 &session->qat_cipher_alg) != 0) {
341 PMD_DRV_LOG(ERR, "Invalid SNOW 3G cipher key size");
345 session->qat_mode = ICP_QAT_HW_CIPHER_ECB_MODE;
347 case RTE_CRYPTO_CIPHER_NULL:
348 session->qat_mode = ICP_QAT_HW_CIPHER_ECB_MODE;
350 case RTE_CRYPTO_CIPHER_KASUMI_F8:
351 if (qat_alg_validate_kasumi_key(cipher_xform->key.length,
352 &session->qat_cipher_alg) != 0) {
353 PMD_DRV_LOG(ERR, "Invalid KASUMI cipher key size");
357 session->qat_mode = ICP_QAT_HW_CIPHER_F8_MODE;
359 case RTE_CRYPTO_CIPHER_3DES_CBC:
360 if (qat_alg_validate_3des_key(cipher_xform->key.length,
361 &session->qat_cipher_alg) != 0) {
362 PMD_DRV_LOG(ERR, "Invalid 3DES cipher key size");
366 session->qat_mode = ICP_QAT_HW_CIPHER_CBC_MODE;
368 case RTE_CRYPTO_CIPHER_DES_CBC:
369 if (qat_alg_validate_des_key(cipher_xform->key.length,
370 &session->qat_cipher_alg) != 0) {
371 PMD_DRV_LOG(ERR, "Invalid DES cipher key size");
375 session->qat_mode = ICP_QAT_HW_CIPHER_CBC_MODE;
377 case RTE_CRYPTO_CIPHER_3DES_CTR:
378 if (qat_alg_validate_3des_key(cipher_xform->key.length,
379 &session->qat_cipher_alg) != 0) {
380 PMD_DRV_LOG(ERR, "Invalid 3DES cipher key size");
384 session->qat_mode = ICP_QAT_HW_CIPHER_CTR_MODE;
386 case RTE_CRYPTO_CIPHER_DES_DOCSISBPI:
387 ret = bpi_cipher_ctx_init(
390 cipher_xform->key.data,
393 PMD_DRV_LOG(ERR, "failed to create DES BPI ctx");
396 if (qat_alg_validate_des_key(cipher_xform->key.length,
397 &session->qat_cipher_alg) != 0) {
398 PMD_DRV_LOG(ERR, "Invalid DES cipher key size");
402 session->qat_mode = ICP_QAT_HW_CIPHER_CBC_MODE;
404 case RTE_CRYPTO_CIPHER_AES_DOCSISBPI:
405 ret = bpi_cipher_ctx_init(
408 cipher_xform->key.data,
411 PMD_DRV_LOG(ERR, "failed to create AES BPI ctx");
414 if (qat_alg_validate_aes_docsisbpi_key(cipher_xform->key.length,
415 &session->qat_cipher_alg) != 0) {
416 PMD_DRV_LOG(ERR, "Invalid AES DOCSISBPI key size");
420 session->qat_mode = ICP_QAT_HW_CIPHER_CBC_MODE;
422 case RTE_CRYPTO_CIPHER_ZUC_EEA3:
423 if (!qat_is_cipher_alg_supported(
424 cipher_xform->algo, internals)) {
425 PMD_DRV_LOG(ERR, "%s not supported on this device",
426 rte_crypto_cipher_algorithm_strings
427 [cipher_xform->algo]);
431 if (qat_alg_validate_zuc_key(cipher_xform->key.length,
432 &session->qat_cipher_alg) != 0) {
433 PMD_DRV_LOG(ERR, "Invalid ZUC cipher key size");
437 session->qat_mode = ICP_QAT_HW_CIPHER_ECB_MODE;
439 case RTE_CRYPTO_CIPHER_3DES_ECB:
440 case RTE_CRYPTO_CIPHER_AES_ECB:
441 case RTE_CRYPTO_CIPHER_AES_F8:
442 case RTE_CRYPTO_CIPHER_AES_XTS:
443 case RTE_CRYPTO_CIPHER_ARC4:
444 PMD_DRV_LOG(ERR, "Crypto QAT PMD: Unsupported Cipher alg %u",
449 PMD_DRV_LOG(ERR, "Crypto: Undefined Cipher specified %u\n",
455 if (cipher_xform->op == RTE_CRYPTO_CIPHER_OP_ENCRYPT)
456 session->qat_dir = ICP_QAT_HW_CIPHER_ENCRYPT;
458 session->qat_dir = ICP_QAT_HW_CIPHER_DECRYPT;
460 if (qat_alg_aead_session_create_content_desc_cipher(session,
461 cipher_xform->key.data,
462 cipher_xform->key.length)) {
470 if (session->bpi_ctx) {
471 bpi_cipher_ctx_free(session->bpi_ctx);
472 session->bpi_ctx = NULL;
478 qat_crypto_sym_configure_session(struct rte_cryptodev *dev,
479 struct rte_crypto_sym_xform *xform,
480 struct rte_cryptodev_sym_session *sess,
481 struct rte_mempool *mempool)
483 void *sess_private_data;
486 if (rte_mempool_get(mempool, &sess_private_data)) {
488 "Couldn't get object from session mempool");
492 ret = qat_crypto_set_session_parameters(dev, xform, sess_private_data);
494 PMD_DRV_LOG(ERR, "Crypto QAT PMD: failed to configure "
495 "session parameters");
497 /* Return session to mempool */
498 rte_mempool_put(mempool, sess_private_data);
502 set_session_private_data(sess, dev->driver_id,
509 qat_crypto_set_session_parameters(struct rte_cryptodev *dev,
510 struct rte_crypto_sym_xform *xform, void *session_private)
512 struct qat_session *session = session_private;
516 PMD_INIT_FUNC_TRACE();
518 /* Set context descriptor physical address */
519 session->cd_paddr = rte_mempool_virt2phy(NULL, session) +
520 offsetof(struct qat_session, cd);
522 session->min_qat_dev_gen = QAT_GEN1;
524 /* Get requested QAT command id */
525 qat_cmd_id = qat_get_cmd_id(xform);
526 if (qat_cmd_id < 0 || qat_cmd_id >= ICP_QAT_FW_LA_CMD_DELIMITER) {
527 PMD_DRV_LOG(ERR, "Unsupported xform chain requested");
530 session->qat_cmd = (enum icp_qat_fw_la_cmd_id)qat_cmd_id;
531 switch (session->qat_cmd) {
532 case ICP_QAT_FW_LA_CMD_CIPHER:
533 ret = qat_crypto_sym_configure_session_cipher(dev, xform, session);
537 case ICP_QAT_FW_LA_CMD_AUTH:
538 ret = qat_crypto_sym_configure_session_auth(dev, xform, session);
542 case ICP_QAT_FW_LA_CMD_CIPHER_HASH:
543 if (xform->type == RTE_CRYPTO_SYM_XFORM_AEAD) {
544 ret = qat_crypto_sym_configure_session_aead(xform,
549 ret = qat_crypto_sym_configure_session_cipher(dev,
553 ret = qat_crypto_sym_configure_session_auth(dev,
559 case ICP_QAT_FW_LA_CMD_HASH_CIPHER:
560 if (xform->type == RTE_CRYPTO_SYM_XFORM_AEAD) {
561 ret = qat_crypto_sym_configure_session_aead(xform,
566 ret = qat_crypto_sym_configure_session_auth(dev,
570 ret = qat_crypto_sym_configure_session_cipher(dev,
576 case ICP_QAT_FW_LA_CMD_TRNG_GET_RANDOM:
577 case ICP_QAT_FW_LA_CMD_TRNG_TEST:
578 case ICP_QAT_FW_LA_CMD_SSL3_KEY_DERIVE:
579 case ICP_QAT_FW_LA_CMD_TLS_V1_1_KEY_DERIVE:
580 case ICP_QAT_FW_LA_CMD_TLS_V1_2_KEY_DERIVE:
581 case ICP_QAT_FW_LA_CMD_MGF1:
582 case ICP_QAT_FW_LA_CMD_AUTH_PRE_COMP:
583 case ICP_QAT_FW_LA_CMD_CIPHER_PRE_COMP:
584 case ICP_QAT_FW_LA_CMD_DELIMITER:
585 PMD_DRV_LOG(ERR, "Unsupported Service %u",
589 PMD_DRV_LOG(ERR, "Unsupported Service %u",
598 qat_crypto_sym_configure_session_auth(struct rte_cryptodev *dev,
599 struct rte_crypto_sym_xform *xform,
600 struct qat_session *session)
602 struct rte_crypto_auth_xform *auth_xform = NULL;
603 struct qat_pmd_private *internals = dev->data->dev_private;
604 auth_xform = qat_get_auth_xform(xform);
605 uint8_t *key_data = auth_xform->key.data;
606 uint8_t key_length = auth_xform->key.length;
608 switch (auth_xform->algo) {
609 case RTE_CRYPTO_AUTH_SHA1_HMAC:
610 session->qat_hash_alg = ICP_QAT_HW_AUTH_ALGO_SHA1;
612 case RTE_CRYPTO_AUTH_SHA224_HMAC:
613 session->qat_hash_alg = ICP_QAT_HW_AUTH_ALGO_SHA224;
615 case RTE_CRYPTO_AUTH_SHA256_HMAC:
616 session->qat_hash_alg = ICP_QAT_HW_AUTH_ALGO_SHA256;
618 case RTE_CRYPTO_AUTH_SHA384_HMAC:
619 session->qat_hash_alg = ICP_QAT_HW_AUTH_ALGO_SHA384;
621 case RTE_CRYPTO_AUTH_SHA512_HMAC:
622 session->qat_hash_alg = ICP_QAT_HW_AUTH_ALGO_SHA512;
624 case RTE_CRYPTO_AUTH_AES_XCBC_MAC:
625 session->qat_hash_alg = ICP_QAT_HW_AUTH_ALGO_AES_XCBC_MAC;
627 case RTE_CRYPTO_AUTH_AES_GMAC:
628 if (qat_alg_validate_aes_key(auth_xform->key.length,
629 &session->qat_cipher_alg) != 0) {
630 PMD_DRV_LOG(ERR, "Invalid AES key size");
633 session->qat_mode = ICP_QAT_HW_CIPHER_CTR_MODE;
634 session->qat_hash_alg = ICP_QAT_HW_AUTH_ALGO_GALOIS_128;
637 case RTE_CRYPTO_AUTH_SNOW3G_UIA2:
638 session->qat_hash_alg = ICP_QAT_HW_AUTH_ALGO_SNOW_3G_UIA2;
640 case RTE_CRYPTO_AUTH_MD5_HMAC:
641 session->qat_hash_alg = ICP_QAT_HW_AUTH_ALGO_MD5;
643 case RTE_CRYPTO_AUTH_NULL:
644 session->qat_hash_alg = ICP_QAT_HW_AUTH_ALGO_NULL;
646 case RTE_CRYPTO_AUTH_KASUMI_F9:
647 session->qat_hash_alg = ICP_QAT_HW_AUTH_ALGO_KASUMI_F9;
649 case RTE_CRYPTO_AUTH_ZUC_EIA3:
650 if (!qat_is_auth_alg_supported(auth_xform->algo, internals)) {
651 PMD_DRV_LOG(ERR, "%s not supported on this device",
652 rte_crypto_auth_algorithm_strings
656 session->qat_hash_alg = ICP_QAT_HW_AUTH_ALGO_ZUC_3G_128_EIA3;
658 case RTE_CRYPTO_AUTH_SHA1:
659 case RTE_CRYPTO_AUTH_SHA256:
660 case RTE_CRYPTO_AUTH_SHA512:
661 case RTE_CRYPTO_AUTH_SHA224:
662 case RTE_CRYPTO_AUTH_SHA384:
663 case RTE_CRYPTO_AUTH_MD5:
664 case RTE_CRYPTO_AUTH_AES_CMAC:
665 case RTE_CRYPTO_AUTH_AES_CBC_MAC:
666 PMD_DRV_LOG(ERR, "Crypto: Unsupported hash alg %u",
670 PMD_DRV_LOG(ERR, "Crypto: Undefined Hash algo %u specified",
675 session->auth_iv.offset = auth_xform->iv.offset;
676 session->auth_iv.length = auth_xform->iv.length;
678 if (auth_xform->algo == RTE_CRYPTO_AUTH_AES_GMAC) {
679 if (auth_xform->op == RTE_CRYPTO_AUTH_OP_GENERATE) {
680 session->qat_cmd = ICP_QAT_FW_LA_CMD_CIPHER_HASH;
681 session->qat_dir = ICP_QAT_HW_CIPHER_ENCRYPT;
683 * It needs to create cipher desc content first,
684 * then authentication
686 if (qat_alg_aead_session_create_content_desc_cipher(session,
687 auth_xform->key.data,
688 auth_xform->key.length))
691 if (qat_alg_aead_session_create_content_desc_auth(session,
695 auth_xform->digest_length,
699 session->qat_cmd = ICP_QAT_FW_LA_CMD_HASH_CIPHER;
700 session->qat_dir = ICP_QAT_HW_CIPHER_DECRYPT;
702 * It needs to create authentication desc content first,
705 if (qat_alg_aead_session_create_content_desc_auth(session,
709 auth_xform->digest_length,
713 if (qat_alg_aead_session_create_content_desc_cipher(session,
714 auth_xform->key.data,
715 auth_xform->key.length))
718 /* Restore to authentication only only */
719 session->qat_cmd = ICP_QAT_FW_LA_CMD_AUTH;
721 if (qat_alg_aead_session_create_content_desc_auth(session,
725 auth_xform->digest_length,
730 session->digest_length = auth_xform->digest_length;
735 qat_crypto_sym_configure_session_aead(struct rte_crypto_sym_xform *xform,
736 struct qat_session *session)
738 struct rte_crypto_aead_xform *aead_xform = &xform->aead;
741 * Store AEAD IV parameters as cipher IV,
742 * to avoid unnecessary memory usage
744 session->cipher_iv.offset = xform->aead.iv.offset;
745 session->cipher_iv.length = xform->aead.iv.length;
747 switch (aead_xform->algo) {
748 case RTE_CRYPTO_AEAD_AES_GCM:
749 if (qat_alg_validate_aes_key(aead_xform->key.length,
750 &session->qat_cipher_alg) != 0) {
751 PMD_DRV_LOG(ERR, "Invalid AES key size");
754 session->qat_mode = ICP_QAT_HW_CIPHER_CTR_MODE;
755 session->qat_hash_alg = ICP_QAT_HW_AUTH_ALGO_GALOIS_128;
757 case RTE_CRYPTO_AEAD_AES_CCM:
758 PMD_DRV_LOG(ERR, "Crypto QAT PMD: Unsupported AEAD alg %u",
762 PMD_DRV_LOG(ERR, "Crypto: Undefined AEAD specified %u\n",
767 if (aead_xform->op == RTE_CRYPTO_AEAD_OP_ENCRYPT) {
768 session->qat_dir = ICP_QAT_HW_CIPHER_ENCRYPT;
770 * It needs to create cipher desc content first,
771 * then authentication
773 if (qat_alg_aead_session_create_content_desc_cipher(session,
774 aead_xform->key.data,
775 aead_xform->key.length))
778 if (qat_alg_aead_session_create_content_desc_auth(session,
779 aead_xform->key.data,
780 aead_xform->key.length,
781 aead_xform->aad_length,
782 aead_xform->digest_length,
783 RTE_CRYPTO_AUTH_OP_GENERATE))
786 session->qat_dir = ICP_QAT_HW_CIPHER_DECRYPT;
788 * It needs to create authentication desc content first,
791 if (qat_alg_aead_session_create_content_desc_auth(session,
792 aead_xform->key.data,
793 aead_xform->key.length,
794 aead_xform->aad_length,
795 aead_xform->digest_length,
796 RTE_CRYPTO_AUTH_OP_VERIFY))
799 if (qat_alg_aead_session_create_content_desc_cipher(session,
800 aead_xform->key.data,
801 aead_xform->key.length))
805 session->digest_length = aead_xform->digest_length;
809 unsigned qat_crypto_sym_get_session_private_size(
810 struct rte_cryptodev *dev __rte_unused)
812 return RTE_ALIGN_CEIL(sizeof(struct qat_session), 8);
815 static inline uint32_t
816 qat_bpicipher_preprocess(struct qat_session *ctx,
817 struct rte_crypto_op *op)
819 uint8_t block_len = qat_cipher_get_block_size(ctx->qat_cipher_alg);
820 struct rte_crypto_sym_op *sym_op = op->sym;
821 uint8_t last_block_len = block_len > 0 ?
822 sym_op->cipher.data.length % block_len : 0;
824 if (last_block_len &&
825 ctx->qat_dir == ICP_QAT_HW_CIPHER_DECRYPT) {
827 /* Decrypt last block */
828 uint8_t *last_block, *dst, *iv;
829 uint32_t last_block_offset = sym_op->cipher.data.offset +
830 sym_op->cipher.data.length - last_block_len;
831 last_block = (uint8_t *) rte_pktmbuf_mtod_offset(sym_op->m_src,
832 uint8_t *, last_block_offset);
834 if (unlikely(sym_op->m_dst != NULL))
835 /* out-of-place operation (OOP) */
836 dst = (uint8_t *) rte_pktmbuf_mtod_offset(sym_op->m_dst,
837 uint8_t *, last_block_offset);
841 if (last_block_len < sym_op->cipher.data.length)
842 /* use previous block ciphertext as IV */
843 iv = last_block - block_len;
845 /* runt block, i.e. less than one full block */
846 iv = rte_crypto_op_ctod_offset(op, uint8_t *,
847 ctx->cipher_iv.offset);
849 #ifdef RTE_LIBRTE_PMD_QAT_DEBUG_TX
850 rte_hexdump(stdout, "BPI: src before pre-process:", last_block,
852 if (sym_op->m_dst != NULL)
853 rte_hexdump(stdout, "BPI: dst before pre-process:", dst,
856 bpi_cipher_decrypt(last_block, dst, iv, block_len,
857 last_block_len, ctx->bpi_ctx);
858 #ifdef RTE_LIBRTE_PMD_QAT_DEBUG_TX
859 rte_hexdump(stdout, "BPI: src after pre-process:", last_block,
861 if (sym_op->m_dst != NULL)
862 rte_hexdump(stdout, "BPI: dst after pre-process:", dst,
867 return sym_op->cipher.data.length - last_block_len;
870 static inline uint32_t
871 qat_bpicipher_postprocess(struct qat_session *ctx,
872 struct rte_crypto_op *op)
874 uint8_t block_len = qat_cipher_get_block_size(ctx->qat_cipher_alg);
875 struct rte_crypto_sym_op *sym_op = op->sym;
876 uint8_t last_block_len = block_len > 0 ?
877 sym_op->cipher.data.length % block_len : 0;
879 if (last_block_len > 0 &&
880 ctx->qat_dir == ICP_QAT_HW_CIPHER_ENCRYPT) {
882 /* Encrypt last block */
883 uint8_t *last_block, *dst, *iv;
884 uint32_t last_block_offset;
886 last_block_offset = sym_op->cipher.data.offset +
887 sym_op->cipher.data.length - last_block_len;
888 last_block = (uint8_t *) rte_pktmbuf_mtod_offset(sym_op->m_src,
889 uint8_t *, last_block_offset);
891 if (unlikely(sym_op->m_dst != NULL))
892 /* out-of-place operation (OOP) */
893 dst = (uint8_t *) rte_pktmbuf_mtod_offset(sym_op->m_dst,
894 uint8_t *, last_block_offset);
898 if (last_block_len < sym_op->cipher.data.length)
899 /* use previous block ciphertext as IV */
900 iv = dst - block_len;
902 /* runt block, i.e. less than one full block */
903 iv = rte_crypto_op_ctod_offset(op, uint8_t *,
904 ctx->cipher_iv.offset);
906 #ifdef RTE_LIBRTE_PMD_QAT_DEBUG_RX
907 rte_hexdump(stdout, "BPI: src before post-process:", last_block,
909 if (sym_op->m_dst != NULL)
910 rte_hexdump(stdout, "BPI: dst before post-process:",
911 dst, last_block_len);
913 bpi_cipher_encrypt(last_block, dst, iv, block_len,
914 last_block_len, ctx->bpi_ctx);
915 #ifdef RTE_LIBRTE_PMD_QAT_DEBUG_RX
916 rte_hexdump(stdout, "BPI: src after post-process:", last_block,
918 if (sym_op->m_dst != NULL)
919 rte_hexdump(stdout, "BPI: dst after post-process:", dst,
923 return sym_op->cipher.data.length - last_block_len;
927 qat_pmd_enqueue_op_burst(void *qp, struct rte_crypto_op **ops,
930 register struct qat_queue *queue;
931 struct qat_qp *tmp_qp = (struct qat_qp *)qp;
932 register uint32_t nb_ops_sent = 0;
933 register struct rte_crypto_op **cur_op = ops;
935 uint16_t nb_ops_possible = nb_ops;
936 register uint8_t *base_addr;
937 register uint32_t tail;
940 if (unlikely(nb_ops == 0))
943 /* read params used a lot in main loop into registers */
944 queue = &(tmp_qp->tx_q);
945 base_addr = (uint8_t *)queue->base_addr;
948 /* Find how many can actually fit on the ring */
949 overflow = rte_atomic16_add_return(&tmp_qp->inflights16, nb_ops)
950 - queue->max_inflights;
952 rte_atomic16_sub(&tmp_qp->inflights16, overflow);
953 nb_ops_possible = nb_ops - overflow;
954 if (nb_ops_possible == 0)
958 while (nb_ops_sent != nb_ops_possible) {
959 ret = qat_write_hw_desc_entry(*cur_op, base_addr + tail,
960 tmp_qp->op_cookies[tail / queue->msg_size], tmp_qp);
962 tmp_qp->stats.enqueue_err_count++;
964 * This message cannot be enqueued,
965 * decrease number of ops that wasn't sent
967 rte_atomic16_sub(&tmp_qp->inflights16,
968 nb_ops_possible - nb_ops_sent);
969 if (nb_ops_sent == 0)
974 tail = adf_modulo(tail + queue->msg_size, queue->modulo);
979 WRITE_CSR_RING_TAIL(tmp_qp->mmap_bar_addr, queue->hw_bundle_number,
980 queue->hw_queue_number, tail);
982 tmp_qp->stats.enqueued_count += nb_ops_sent;
987 qat_pmd_dequeue_op_burst(void *qp, struct rte_crypto_op **ops,
990 struct qat_queue *queue;
991 struct qat_qp *tmp_qp = (struct qat_qp *)qp;
992 uint32_t msg_counter = 0;
993 struct rte_crypto_op *rx_op;
994 struct icp_qat_fw_comn_resp *resp_msg;
996 queue = &(tmp_qp->rx_q);
997 resp_msg = (struct icp_qat_fw_comn_resp *)
998 ((uint8_t *)queue->base_addr + queue->head);
1000 while (*(uint32_t *)resp_msg != ADF_RING_EMPTY_SIG &&
1001 msg_counter != nb_ops) {
1002 rx_op = (struct rte_crypto_op *)(uintptr_t)
1003 (resp_msg->opaque_data);
1005 #ifdef RTE_LIBRTE_PMD_QAT_DEBUG_RX
1006 rte_hexdump(stdout, "qat_response:", (uint8_t *)resp_msg,
1007 sizeof(struct icp_qat_fw_comn_resp));
1010 if (ICP_QAT_FW_COMN_STATUS_FLAG_OK !=
1011 ICP_QAT_FW_COMN_RESP_CRYPTO_STAT_GET(
1012 resp_msg->comn_hdr.comn_status)) {
1013 rx_op->status = RTE_CRYPTO_OP_STATUS_AUTH_FAILED;
1015 struct qat_session *sess = (struct qat_session *)
1016 get_session_private_data(
1017 rx_op->sym->session,
1018 cryptodev_qat_driver_id);
1021 qat_bpicipher_postprocess(sess, rx_op);
1022 rx_op->status = RTE_CRYPTO_OP_STATUS_SUCCESS;
1025 *(uint32_t *)resp_msg = ADF_RING_EMPTY_SIG;
1026 queue->head = adf_modulo(queue->head +
1028 ADF_RING_SIZE_MODULO(queue->queue_size));
1029 resp_msg = (struct icp_qat_fw_comn_resp *)
1030 ((uint8_t *)queue->base_addr +
1036 if (msg_counter > 0) {
1037 WRITE_CSR_RING_HEAD(tmp_qp->mmap_bar_addr,
1038 queue->hw_bundle_number,
1039 queue->hw_queue_number, queue->head);
1040 rte_atomic16_sub(&tmp_qp->inflights16, msg_counter);
1041 tmp_qp->stats.dequeued_count += msg_counter;
1047 qat_sgl_fill_array(struct rte_mbuf *buf, uint64_t buff_start,
1048 struct qat_alg_buf_list *list, uint32_t data_len)
1052 uint32_t buf_len = rte_pktmbuf_mtophys(buf) -
1053 buff_start + rte_pktmbuf_data_len(buf);
1055 list->bufers[0].addr = buff_start;
1056 list->bufers[0].resrvd = 0;
1057 list->bufers[0].len = buf_len;
1059 if (data_len <= buf_len) {
1060 list->num_bufs = nr;
1061 list->bufers[0].len = data_len;
1067 if (unlikely(nr == QAT_SGL_MAX_NUMBER)) {
1068 PMD_DRV_LOG(ERR, "QAT PMD exceeded size of QAT SGL"
1070 QAT_SGL_MAX_NUMBER);
1074 list->bufers[nr].len = rte_pktmbuf_data_len(buf);
1075 list->bufers[nr].resrvd = 0;
1076 list->bufers[nr].addr = rte_pktmbuf_mtophys(buf);
1078 buf_len += list->bufers[nr].len;
1081 if (buf_len > data_len) {
1082 list->bufers[nr].len -=
1088 list->num_bufs = nr;
1094 set_cipher_iv(uint16_t iv_length, uint16_t iv_offset,
1095 struct icp_qat_fw_la_cipher_req_params *cipher_param,
1096 struct rte_crypto_op *op,
1097 struct icp_qat_fw_la_bulk_req *qat_req)
1099 /* copy IV into request if it fits */
1100 if (iv_length <= sizeof(cipher_param->u.cipher_IV_array)) {
1101 rte_memcpy(cipher_param->u.cipher_IV_array,
1102 rte_crypto_op_ctod_offset(op, uint8_t *,
1106 ICP_QAT_FW_LA_CIPH_IV_FLD_FLAG_SET(
1107 qat_req->comn_hdr.serv_specif_flags,
1108 ICP_QAT_FW_CIPH_IV_64BIT_PTR);
1109 cipher_param->u.s.cipher_IV_ptr =
1110 rte_crypto_op_ctophys_offset(op,
1116 qat_write_hw_desc_entry(struct rte_crypto_op *op, uint8_t *out_msg,
1117 struct qat_crypto_op_cookie *qat_op_cookie, struct qat_qp *qp)
1120 struct qat_session *ctx;
1121 struct icp_qat_fw_la_cipher_req_params *cipher_param;
1122 struct icp_qat_fw_la_auth_req_params *auth_param;
1123 register struct icp_qat_fw_la_bulk_req *qat_req;
1124 uint8_t do_auth = 0, do_cipher = 0, do_aead = 0;
1125 uint32_t cipher_len = 0, cipher_ofs = 0;
1126 uint32_t auth_len = 0, auth_ofs = 0;
1127 uint32_t min_ofs = 0;
1128 uint64_t src_buf_start = 0, dst_buf_start = 0;
1131 #ifdef RTE_LIBRTE_PMD_QAT_DEBUG_TX
1132 if (unlikely(op->type != RTE_CRYPTO_OP_TYPE_SYMMETRIC)) {
1133 PMD_DRV_LOG(ERR, "QAT PMD only supports symmetric crypto "
1134 "operation requests, op (%p) is not a "
1135 "symmetric operation.", op);
1139 if (unlikely(op->sess_type == RTE_CRYPTO_OP_SESSIONLESS)) {
1140 PMD_DRV_LOG(ERR, "QAT PMD only supports session oriented"
1141 " requests, op (%p) is sessionless.", op);
1145 ctx = (struct qat_session *)get_session_private_data(
1146 op->sym->session, cryptodev_qat_driver_id);
1148 if (unlikely(ctx == NULL)) {
1149 PMD_DRV_LOG(ERR, "Session was not created for this device");
1153 if (unlikely(ctx->min_qat_dev_gen > qp->qat_dev_gen)) {
1154 PMD_DRV_LOG(ERR, "Session alg not supported on this device gen");
1155 op->status = RTE_CRYPTO_OP_STATUS_INVALID_SESSION;
1159 qat_req = (struct icp_qat_fw_la_bulk_req *)out_msg;
1160 rte_mov128((uint8_t *)qat_req, (const uint8_t *)&(ctx->fw_req));
1161 qat_req->comn_mid.opaque_data = (uint64_t)(uintptr_t)op;
1162 cipher_param = (void *)&qat_req->serv_specif_rqpars;
1163 auth_param = (void *)((uint8_t *)cipher_param + sizeof(*cipher_param));
1165 if (ctx->qat_cmd == ICP_QAT_FW_LA_CMD_HASH_CIPHER ||
1166 ctx->qat_cmd == ICP_QAT_FW_LA_CMD_CIPHER_HASH) {
1168 if (ctx->qat_hash_alg == ICP_QAT_HW_AUTH_ALGO_GALOIS_128 ||
1169 ctx->qat_hash_alg == ICP_QAT_HW_AUTH_ALGO_GALOIS_64) {
1175 } else if (ctx->qat_cmd == ICP_QAT_FW_LA_CMD_AUTH) {
1178 } else if (ctx->qat_cmd == ICP_QAT_FW_LA_CMD_CIPHER) {
1185 if (ctx->qat_cipher_alg ==
1186 ICP_QAT_HW_CIPHER_ALGO_SNOW_3G_UEA2 ||
1187 ctx->qat_cipher_alg == ICP_QAT_HW_CIPHER_ALGO_KASUMI ||
1188 ctx->qat_cipher_alg ==
1189 ICP_QAT_HW_CIPHER_ALGO_ZUC_3G_128_EEA3) {
1192 (cipher_param->cipher_length % BYTE_LENGTH != 0)
1193 || (cipher_param->cipher_offset
1194 % BYTE_LENGTH != 0))) {
1196 "SNOW3G/KASUMI/ZUC in QAT PMD only supports byte aligned values");
1197 op->status = RTE_CRYPTO_OP_STATUS_INVALID_ARGS;
1200 cipher_len = op->sym->cipher.data.length >> 3;
1201 cipher_ofs = op->sym->cipher.data.offset >> 3;
1203 } else if (ctx->bpi_ctx) {
1204 /* DOCSIS - only send complete blocks to device
1205 * Process any partial block using CFB mode.
1206 * Even if 0 complete blocks, still send this to device
1207 * to get into rx queue for post-process and dequeuing
1209 cipher_len = qat_bpicipher_preprocess(ctx, op);
1210 cipher_ofs = op->sym->cipher.data.offset;
1212 cipher_len = op->sym->cipher.data.length;
1213 cipher_ofs = op->sym->cipher.data.offset;
1216 set_cipher_iv(ctx->cipher_iv.length, ctx->cipher_iv.offset,
1217 cipher_param, op, qat_req);
1218 min_ofs = cipher_ofs;
1223 if (ctx->qat_hash_alg == ICP_QAT_HW_AUTH_ALGO_SNOW_3G_UIA2 ||
1224 ctx->qat_hash_alg == ICP_QAT_HW_AUTH_ALGO_KASUMI_F9 ||
1225 ctx->qat_hash_alg ==
1226 ICP_QAT_HW_AUTH_ALGO_ZUC_3G_128_EIA3) {
1227 if (unlikely((auth_param->auth_off % BYTE_LENGTH != 0)
1228 || (auth_param->auth_len % BYTE_LENGTH != 0))) {
1230 "For SNOW3G/KASUMI/ZUC, QAT PMD only supports byte aligned values");
1231 op->status = RTE_CRYPTO_OP_STATUS_INVALID_ARGS;
1234 auth_ofs = op->sym->auth.data.offset >> 3;
1235 auth_len = op->sym->auth.data.length >> 3;
1237 auth_param->u1.aad_adr =
1238 rte_crypto_op_ctophys_offset(op,
1239 ctx->auth_iv.offset);
1241 } else if (ctx->qat_hash_alg ==
1242 ICP_QAT_HW_AUTH_ALGO_GALOIS_128 ||
1243 ctx->qat_hash_alg ==
1244 ICP_QAT_HW_AUTH_ALGO_GALOIS_64) {
1246 set_cipher_iv(ctx->auth_iv.length,
1247 ctx->auth_iv.offset,
1248 cipher_param, op, qat_req);
1249 auth_ofs = op->sym->auth.data.offset;
1250 auth_len = op->sym->auth.data.length;
1252 auth_param->u1.aad_adr = 0;
1253 auth_param->u2.aad_sz = 0;
1256 * If len(iv)==12B fw computes J0
1258 if (ctx->auth_iv.length == 12) {
1259 ICP_QAT_FW_LA_GCM_IV_LEN_FLAG_SET(
1260 qat_req->comn_hdr.serv_specif_flags,
1261 ICP_QAT_FW_LA_GCM_IV_LEN_12_OCTETS);
1265 auth_ofs = op->sym->auth.data.offset;
1266 auth_len = op->sym->auth.data.length;
1271 auth_param->auth_res_addr = op->sym->auth.digest.phys_addr;
1276 if (ctx->qat_hash_alg ==
1277 ICP_QAT_HW_AUTH_ALGO_GALOIS_128 ||
1278 ctx->qat_hash_alg ==
1279 ICP_QAT_HW_AUTH_ALGO_GALOIS_64) {
1281 * If len(iv)==12B fw computes J0
1283 if (ctx->cipher_iv.length == 12) {
1284 ICP_QAT_FW_LA_GCM_IV_LEN_FLAG_SET(
1285 qat_req->comn_hdr.serv_specif_flags,
1286 ICP_QAT_FW_LA_GCM_IV_LEN_12_OCTETS);
1291 cipher_len = op->sym->aead.data.length;
1292 cipher_ofs = op->sym->aead.data.offset;
1293 auth_len = op->sym->aead.data.length;
1294 auth_ofs = op->sym->aead.data.offset;
1296 auth_param->u1.aad_adr = op->sym->aead.aad.phys_addr;
1297 auth_param->auth_res_addr = op->sym->aead.digest.phys_addr;
1298 set_cipher_iv(ctx->cipher_iv.length, ctx->cipher_iv.offset,
1299 cipher_param, op, qat_req);
1300 min_ofs = op->sym->aead.data.offset;
1303 if (op->sym->m_src->next || (op->sym->m_dst && op->sym->m_dst->next))
1306 /* adjust for chain case */
1307 if (do_cipher && do_auth)
1308 min_ofs = cipher_ofs < auth_ofs ? cipher_ofs : auth_ofs;
1310 if (unlikely(min_ofs >= rte_pktmbuf_data_len(op->sym->m_src) && do_sgl))
1313 if (unlikely(op->sym->m_dst != NULL)) {
1314 /* Out-of-place operation (OOP)
1315 * Don't align DMA start. DMA the minimum data-set
1316 * so as not to overwrite data in dest buffer
1319 rte_pktmbuf_mtophys_offset(op->sym->m_src, min_ofs);
1321 rte_pktmbuf_mtophys_offset(op->sym->m_dst, min_ofs);
1324 /* In-place operation
1325 * Start DMA at nearest aligned address below min_ofs
1328 rte_pktmbuf_mtophys_offset(op->sym->m_src, min_ofs)
1329 & QAT_64_BTYE_ALIGN_MASK;
1331 if (unlikely((rte_pktmbuf_mtophys(op->sym->m_src) -
1332 rte_pktmbuf_headroom(op->sym->m_src))
1334 /* alignment has pushed addr ahead of start of mbuf
1335 * so revert and take the performance hit
1338 rte_pktmbuf_mtophys_offset(op->sym->m_src,
1341 dst_buf_start = src_buf_start;
1344 if (do_cipher || do_aead) {
1345 cipher_param->cipher_offset =
1346 (uint32_t)rte_pktmbuf_mtophys_offset(
1347 op->sym->m_src, cipher_ofs) - src_buf_start;
1348 cipher_param->cipher_length = cipher_len;
1350 cipher_param->cipher_offset = 0;
1351 cipher_param->cipher_length = 0;
1354 if (do_auth || do_aead) {
1355 auth_param->auth_off = (uint32_t)rte_pktmbuf_mtophys_offset(
1356 op->sym->m_src, auth_ofs) - src_buf_start;
1357 auth_param->auth_len = auth_len;
1359 auth_param->auth_off = 0;
1360 auth_param->auth_len = 0;
1363 qat_req->comn_mid.dst_length =
1364 qat_req->comn_mid.src_length =
1365 (cipher_param->cipher_offset + cipher_param->cipher_length)
1366 > (auth_param->auth_off + auth_param->auth_len) ?
1367 (cipher_param->cipher_offset + cipher_param->cipher_length)
1368 : (auth_param->auth_off + auth_param->auth_len);
1372 ICP_QAT_FW_COMN_PTR_TYPE_SET(qat_req->comn_hdr.comn_req_flags,
1373 QAT_COMN_PTR_TYPE_SGL);
1374 ret = qat_sgl_fill_array(op->sym->m_src, src_buf_start,
1375 &qat_op_cookie->qat_sgl_list_src,
1376 qat_req->comn_mid.src_length);
1378 PMD_DRV_LOG(ERR, "QAT PMD Cannot fill sgl array");
1382 if (likely(op->sym->m_dst == NULL))
1383 qat_req->comn_mid.dest_data_addr =
1384 qat_req->comn_mid.src_data_addr =
1385 qat_op_cookie->qat_sgl_src_phys_addr;
1387 ret = qat_sgl_fill_array(op->sym->m_dst,
1389 &qat_op_cookie->qat_sgl_list_dst,
1390 qat_req->comn_mid.dst_length);
1393 PMD_DRV_LOG(ERR, "QAT PMD Cannot "
1398 qat_req->comn_mid.src_data_addr =
1399 qat_op_cookie->qat_sgl_src_phys_addr;
1400 qat_req->comn_mid.dest_data_addr =
1401 qat_op_cookie->qat_sgl_dst_phys_addr;
1404 qat_req->comn_mid.src_data_addr = src_buf_start;
1405 qat_req->comn_mid.dest_data_addr = dst_buf_start;
1408 #ifdef RTE_LIBRTE_PMD_QAT_DEBUG_TX
1409 rte_hexdump(stdout, "qat_req:", qat_req,
1410 sizeof(struct icp_qat_fw_la_bulk_req));
1411 rte_hexdump(stdout, "src_data:",
1412 rte_pktmbuf_mtod(op->sym->m_src, uint8_t*),
1413 rte_pktmbuf_data_len(op->sym->m_src));
1415 uint8_t *cipher_iv_ptr = rte_crypto_op_ctod_offset(op,
1417 ctx->cipher_iv.offset);
1418 rte_hexdump(stdout, "cipher iv:", cipher_iv_ptr,
1419 ctx->cipher_iv.length);
1423 if (ctx->auth_iv.length) {
1424 uint8_t *auth_iv_ptr = rte_crypto_op_ctod_offset(op,
1426 ctx->auth_iv.offset);
1427 rte_hexdump(stdout, "auth iv:", auth_iv_ptr,
1428 ctx->auth_iv.length);
1430 rte_hexdump(stdout, "digest:", op->sym->auth.digest.data,
1431 ctx->digest_length);
1435 rte_hexdump(stdout, "digest:", op->sym->aead.digest.data,
1436 ctx->digest_length);
1437 rte_hexdump(stdout, "aad:", op->sym->aead.aad.data,
1444 static inline uint32_t adf_modulo(uint32_t data, uint32_t shift)
1446 uint32_t div = data >> shift;
1447 uint32_t mult = div << shift;
1452 int qat_dev_config(__rte_unused struct rte_cryptodev *dev,
1453 __rte_unused struct rte_cryptodev_config *config)
1455 PMD_INIT_FUNC_TRACE();
1459 int qat_dev_start(__rte_unused struct rte_cryptodev *dev)
1461 PMD_INIT_FUNC_TRACE();
1465 void qat_dev_stop(__rte_unused struct rte_cryptodev *dev)
1467 PMD_INIT_FUNC_TRACE();
1470 int qat_dev_close(struct rte_cryptodev *dev)
1474 PMD_INIT_FUNC_TRACE();
1476 for (i = 0; i < dev->data->nb_queue_pairs; i++) {
1477 ret = qat_crypto_sym_qp_release(dev, i);
1485 void qat_dev_info_get(struct rte_cryptodev *dev,
1486 struct rte_cryptodev_info *info)
1488 struct qat_pmd_private *internals = dev->data->dev_private;
1490 PMD_INIT_FUNC_TRACE();
1492 info->max_nb_queue_pairs =
1493 ADF_NUM_SYM_QPS_PER_BUNDLE *
1494 ADF_NUM_BUNDLES_PER_DEV;
1495 info->feature_flags = dev->feature_flags;
1496 info->capabilities = internals->qat_dev_capabilities;
1497 info->sym.max_nb_sessions = internals->max_nb_sessions;
1498 info->driver_id = cryptodev_qat_driver_id;
1499 info->pci_dev = RTE_DEV_TO_PCI(dev->device);
1503 void qat_crypto_sym_stats_get(struct rte_cryptodev *dev,
1504 struct rte_cryptodev_stats *stats)
1507 struct qat_qp **qp = (struct qat_qp **)(dev->data->queue_pairs);
1509 PMD_INIT_FUNC_TRACE();
1510 if (stats == NULL) {
1511 PMD_DRV_LOG(ERR, "invalid stats ptr NULL");
1514 for (i = 0; i < dev->data->nb_queue_pairs; i++) {
1515 if (qp[i] == NULL) {
1516 PMD_DRV_LOG(DEBUG, "Uninitialised queue pair");
1520 stats->enqueued_count += qp[i]->stats.enqueued_count;
1521 stats->dequeued_count += qp[i]->stats.dequeued_count;
1522 stats->enqueue_err_count += qp[i]->stats.enqueue_err_count;
1523 stats->dequeue_err_count += qp[i]->stats.dequeue_err_count;
1527 void qat_crypto_sym_stats_reset(struct rte_cryptodev *dev)
1530 struct qat_qp **qp = (struct qat_qp **)(dev->data->queue_pairs);
1532 PMD_INIT_FUNC_TRACE();
1533 for (i = 0; i < dev->data->nb_queue_pairs; i++)
1534 memset(&(qp[i]->stats), 0, sizeof(qp[i]->stats));
1535 PMD_DRV_LOG(DEBUG, "QAT crypto: stats cleared");