cf2d2741a87fd75e70ac0e2325776c44f3157f05
[deb_dpdk.git] / drivers / event / dpaa2 / dpaa2_eventdev.c
1 /*-
2  *   BSD LICENSE
3  *
4  *   Copyright 2017 NXP.
5  *
6  *   Redistribution and use in source and binary forms, with or without
7  *   modification, are permitted provided that the following conditions
8  *   are met:
9  *
10  *     * Redistributions of source code must retain the above copyright
11  *       notice, this list of conditions and the following disclaimer.
12  *     * Redistributions in binary form must reproduce the above copyright
13  *       notice, this list of conditions and the following disclaimer in
14  *       the documentation and/or other materials provided with the
15  *       distribution.
16  *     * Neither the name of NXP nor the names of its
17  *       contributors may be used to endorse or promote products derived
18  *       from this software without specific prior written permission.
19  *
20  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
21  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
22  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
23  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
24  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
25  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
26  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
27  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
28  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
29  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
30  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
31  */
32
33 #include <assert.h>
34 #include <stdio.h>
35 #include <stdbool.h>
36 #include <errno.h>
37 #include <stdint.h>
38 #include <string.h>
39 #include <sys/epoll.h>
40
41 #include <rte_atomic.h>
42 #include <rte_byteorder.h>
43 #include <rte_common.h>
44 #include <rte_debug.h>
45 #include <rte_dev.h>
46 #include <rte_eal.h>
47 #include <rte_fslmc.h>
48 #include <rte_lcore.h>
49 #include <rte_log.h>
50 #include <rte_malloc.h>
51 #include <rte_memcpy.h>
52 #include <rte_memory.h>
53 #include <rte_memzone.h>
54 #include <rte_pci.h>
55 #include <rte_vdev.h>
56
57 #include <fslmc_vfio.h>
58 #include <dpaa2_hw_pvt.h>
59 #include <dpaa2_hw_mempool.h>
60 #include <dpaa2_hw_dpio.h>
61 #include "dpaa2_eventdev.h"
62 #include <portal/dpaa2_hw_pvt.h>
63 #include <mc/fsl_dpci.h>
64
65 /* Clarifications
66  * Evendev = SoC Instance
67  * Eventport = DPIO Instance
68  * Eventqueue = DPCON Instance
69  * 1 Eventdev can have N Eventqueue
70  * Soft Event Flow is DPCI Instance
71  */
72
73 static uint16_t
74 dpaa2_eventdev_enqueue_burst(void *port, const struct rte_event ev[],
75                              uint16_t nb_events)
76 {
77         struct rte_eventdev *ev_dev =
78                         ((struct dpaa2_io_portal_t *)port)->eventdev;
79         struct dpaa2_eventdev *priv = ev_dev->data->dev_private;
80         uint32_t queue_id = ev[0].queue_id;
81         struct evq_info_t *evq_info = &priv->evq_info[queue_id];
82         uint32_t fqid;
83         struct qbman_swp *swp;
84         struct qbman_fd fd_arr[MAX_TX_RING_SLOTS];
85         uint32_t loop, frames_to_send;
86         struct qbman_eq_desc eqdesc[MAX_TX_RING_SLOTS];
87         uint16_t num_tx = 0;
88         int ret;
89
90         RTE_SET_USED(port);
91
92         if (unlikely(!DPAA2_PER_LCORE_DPIO)) {
93                 ret = dpaa2_affine_qbman_swp();
94                 if (ret) {
95                         PMD_DRV_LOG(ERR, "Failure in affining portal\n");
96                         return 0;
97                 }
98         }
99
100         swp = DPAA2_PER_LCORE_PORTAL;
101
102         while (nb_events) {
103                 frames_to_send = (nb_events >> 3) ?
104                         MAX_TX_RING_SLOTS : nb_events;
105
106                 for (loop = 0; loop < frames_to_send; loop++) {
107                         const struct rte_event *event = &ev[num_tx + loop];
108
109                         if (event->sched_type != RTE_SCHED_TYPE_ATOMIC)
110                                 fqid = evq_info->dpci->queue[
111                                         DPAA2_EVENT_DPCI_PARALLEL_QUEUE].fqid;
112                         else
113                                 fqid = evq_info->dpci->queue[
114                                         DPAA2_EVENT_DPCI_ATOMIC_QUEUE].fqid;
115
116                         /* Prepare enqueue descriptor */
117                         qbman_eq_desc_clear(&eqdesc[loop]);
118                         qbman_eq_desc_set_fq(&eqdesc[loop], fqid);
119                         qbman_eq_desc_set_no_orp(&eqdesc[loop], 0);
120                         qbman_eq_desc_set_response(&eqdesc[loop], 0, 0);
121
122                         if (event->impl_opaque) {
123                                 uint8_t dqrr_index = event->impl_opaque - 1;
124
125                                 qbman_eq_desc_set_dca(&eqdesc[loop], 1,
126                                                       dqrr_index, 0);
127                                 DPAA2_PER_LCORE_DPIO->dqrr_size--;
128                                 DPAA2_PER_LCORE_DPIO->dqrr_held &=
129                                         ~(1 << dqrr_index);
130                         }
131
132                         memset(&fd_arr[loop], 0, sizeof(struct qbman_fd));
133
134                         /*
135                          * todo - need to align with hw context data
136                          * to avoid copy
137                          */
138                         struct rte_event *ev_temp = rte_malloc(NULL,
139                                 sizeof(struct rte_event), 0);
140                         rte_memcpy(ev_temp, event, sizeof(struct rte_event));
141                         DPAA2_SET_FD_ADDR((&fd_arr[loop]), ev_temp);
142                         DPAA2_SET_FD_LEN((&fd_arr[loop]),
143                                          sizeof(struct rte_event));
144                 }
145                 loop = 0;
146                 while (loop < frames_to_send) {
147                         loop += qbman_swp_enqueue_multiple_eqdesc(swp,
148                                         &eqdesc[loop], &fd_arr[loop],
149                                         frames_to_send - loop);
150                 }
151                 num_tx += frames_to_send;
152                 nb_events -= frames_to_send;
153         }
154
155         return num_tx;
156 }
157
158 static uint16_t
159 dpaa2_eventdev_enqueue(void *port, const struct rte_event *ev)
160 {
161         return dpaa2_eventdev_enqueue_burst(port, ev, 1);
162 }
163
164 static void dpaa2_eventdev_dequeue_wait(uint64_t timeout_ticks)
165 {
166         struct epoll_event epoll_ev;
167         int ret, i = 0;
168
169         qbman_swp_interrupt_clear_status(DPAA2_PER_LCORE_PORTAL,
170                                          QBMAN_SWP_INTERRUPT_DQRI);
171
172 RETRY:
173         ret = epoll_wait(DPAA2_PER_LCORE_DPIO->epoll_fd,
174                          &epoll_ev, 1, timeout_ticks);
175         if (ret < 1) {
176                 /* sometimes due to some spurious interrupts epoll_wait fails
177                  * with errno EINTR. so here we are retrying epoll_wait in such
178                  * case to avoid the problem.
179                  */
180                 if (errno == EINTR) {
181                         PMD_DRV_LOG(DEBUG, "epoll_wait fails\n");
182                         if (i++ > 10)
183                                 PMD_DRV_LOG(DEBUG, "Dequeue burst Failed\n");
184                 goto RETRY;
185                 }
186         }
187 }
188
189 static void dpaa2_eventdev_process_parallel(struct qbman_swp *swp,
190                                             const struct qbman_fd *fd,
191                                             const struct qbman_result *dq,
192                                             struct rte_event *ev)
193 {
194         struct rte_event *ev_temp =
195                 (struct rte_event *)DPAA2_GET_FD_ADDR(fd);
196         rte_memcpy(ev, ev_temp, sizeof(struct rte_event));
197         rte_free(ev_temp);
198
199         qbman_swp_dqrr_consume(swp, dq);
200 }
201
202 static void dpaa2_eventdev_process_atomic(struct qbman_swp *swp,
203                                           const struct qbman_fd *fd,
204                                           const struct qbman_result *dq,
205                                           struct rte_event *ev)
206 {
207         struct rte_event *ev_temp =
208                 (struct rte_event *)DPAA2_GET_FD_ADDR(fd);
209         uint8_t dqrr_index = qbman_get_dqrr_idx(dq);
210
211         RTE_SET_USED(swp);
212
213         rte_memcpy(ev, ev_temp, sizeof(struct rte_event));
214         rte_free(ev_temp);
215         ev->impl_opaque = dqrr_index + 1;
216         DPAA2_PER_LCORE_DPIO->dqrr_size++;
217         DPAA2_PER_LCORE_DPIO->dqrr_held |= 1 << dqrr_index;
218 }
219
220 static uint16_t
221 dpaa2_eventdev_dequeue_burst(void *port, struct rte_event ev[],
222                              uint16_t nb_events, uint64_t timeout_ticks)
223 {
224         const struct qbman_result *dq;
225         struct qbman_swp *swp;
226         const struct qbman_fd *fd;
227         struct dpaa2_queue *rxq;
228         int num_pkts = 0, ret, i = 0;
229
230         RTE_SET_USED(port);
231
232         if (unlikely(!DPAA2_PER_LCORE_DPIO)) {
233                 ret = dpaa2_affine_qbman_swp();
234                 if (ret) {
235                         PMD_DRV_LOG(ERR, "Failure in affining portal\n");
236                         return 0;
237                 }
238         }
239
240         swp = DPAA2_PER_LCORE_PORTAL;
241
242         /* Check if there are atomic contexts to be released */
243         while (DPAA2_PER_LCORE_DPIO->dqrr_size) {
244                 if (DPAA2_PER_LCORE_DPIO->dqrr_held & (1 << i)) {
245                         dq = qbman_get_dqrr_from_idx(swp, i);
246                         qbman_swp_dqrr_consume(swp, dq);
247                         DPAA2_PER_LCORE_DPIO->dqrr_size--;
248                 }
249                 i++;
250         }
251         DPAA2_PER_LCORE_DPIO->dqrr_held = 0;
252
253         do {
254                 dq = qbman_swp_dqrr_next(swp);
255                 if (!dq) {
256                         if (!num_pkts && timeout_ticks) {
257                                 dpaa2_eventdev_dequeue_wait(timeout_ticks);
258                                 timeout_ticks = 0;
259                                 continue;
260                         }
261                         return num_pkts;
262                 }
263
264                 fd = qbman_result_DQ_fd(dq);
265
266                 rxq = (struct dpaa2_queue *)qbman_result_DQ_fqd_ctx(dq);
267                 if (rxq) {
268                         rxq->cb(swp, fd, dq, &ev[num_pkts]);
269                 } else {
270                         qbman_swp_dqrr_consume(swp, dq);
271                         PMD_DRV_LOG(ERR, "Null Return VQ received\n");
272                         return 0;
273                 }
274
275                 num_pkts++;
276         } while (num_pkts < nb_events);
277
278         return num_pkts;
279 }
280
281 static uint16_t
282 dpaa2_eventdev_dequeue(void *port, struct rte_event *ev,
283                        uint64_t timeout_ticks)
284 {
285         return dpaa2_eventdev_dequeue_burst(port, ev, 1, timeout_ticks);
286 }
287
288 static void
289 dpaa2_eventdev_info_get(struct rte_eventdev *dev,
290                         struct rte_event_dev_info *dev_info)
291 {
292         struct dpaa2_eventdev *priv = dev->data->dev_private;
293
294         PMD_DRV_FUNC_TRACE();
295
296         RTE_SET_USED(dev);
297
298         memset(dev_info, 0, sizeof(struct rte_event_dev_info));
299         dev_info->min_dequeue_timeout_ns =
300                 DPAA2_EVENT_MIN_DEQUEUE_TIMEOUT;
301         dev_info->max_dequeue_timeout_ns =
302                 DPAA2_EVENT_MAX_DEQUEUE_TIMEOUT;
303         dev_info->dequeue_timeout_ns =
304                 DPAA2_EVENT_MIN_DEQUEUE_TIMEOUT;
305         dev_info->max_event_queues = priv->max_event_queues;
306         dev_info->max_event_queue_flows =
307                 DPAA2_EVENT_MAX_QUEUE_FLOWS;
308         dev_info->max_event_queue_priority_levels =
309                 DPAA2_EVENT_MAX_QUEUE_PRIORITY_LEVELS;
310         dev_info->max_event_priority_levels =
311                 DPAA2_EVENT_MAX_EVENT_PRIORITY_LEVELS;
312         dev_info->max_event_ports = RTE_MAX_LCORE;
313         dev_info->max_event_port_dequeue_depth =
314                 DPAA2_EVENT_MAX_PORT_DEQUEUE_DEPTH;
315         dev_info->max_event_port_enqueue_depth =
316                 DPAA2_EVENT_MAX_PORT_ENQUEUE_DEPTH;
317         dev_info->max_num_events = DPAA2_EVENT_MAX_NUM_EVENTS;
318         dev_info->event_dev_cap = RTE_EVENT_DEV_CAP_DISTRIBUTED_SCHED |
319                 RTE_EVENT_DEV_CAP_BURST_MODE;
320 }
321
322 static int
323 dpaa2_eventdev_configure(const struct rte_eventdev *dev)
324 {
325         struct dpaa2_eventdev *priv = dev->data->dev_private;
326         struct rte_event_dev_config *conf = &dev->data->dev_conf;
327
328         PMD_DRV_FUNC_TRACE();
329
330         priv->dequeue_timeout_ns = conf->dequeue_timeout_ns;
331         priv->nb_event_queues = conf->nb_event_queues;
332         priv->nb_event_ports = conf->nb_event_ports;
333         priv->nb_event_queue_flows = conf->nb_event_queue_flows;
334         priv->nb_event_port_dequeue_depth = conf->nb_event_port_dequeue_depth;
335         priv->nb_event_port_enqueue_depth = conf->nb_event_port_enqueue_depth;
336         priv->event_dev_cfg = conf->event_dev_cfg;
337
338         PMD_DRV_LOG(DEBUG, "Configured eventdev devid=%d", dev->data->dev_id);
339         return 0;
340 }
341
342 static int
343 dpaa2_eventdev_start(struct rte_eventdev *dev)
344 {
345         PMD_DRV_FUNC_TRACE();
346
347         RTE_SET_USED(dev);
348
349         return 0;
350 }
351
352 static void
353 dpaa2_eventdev_stop(struct rte_eventdev *dev)
354 {
355         PMD_DRV_FUNC_TRACE();
356
357         RTE_SET_USED(dev);
358 }
359
360 static int
361 dpaa2_eventdev_close(struct rte_eventdev *dev)
362 {
363         PMD_DRV_FUNC_TRACE();
364
365         RTE_SET_USED(dev);
366
367         return 0;
368 }
369
370 static void
371 dpaa2_eventdev_queue_def_conf(struct rte_eventdev *dev, uint8_t queue_id,
372                               struct rte_event_queue_conf *queue_conf)
373 {
374         PMD_DRV_FUNC_TRACE();
375
376         RTE_SET_USED(dev);
377         RTE_SET_USED(queue_id);
378         RTE_SET_USED(queue_conf);
379
380         queue_conf->nb_atomic_flows = DPAA2_EVENT_QUEUE_ATOMIC_FLOWS;
381         queue_conf->event_queue_cfg = RTE_EVENT_QUEUE_CFG_ATOMIC_ONLY |
382                                       RTE_EVENT_QUEUE_CFG_PARALLEL_ONLY;
383         queue_conf->priority = RTE_EVENT_DEV_PRIORITY_NORMAL;
384 }
385
386 static void
387 dpaa2_eventdev_queue_release(struct rte_eventdev *dev, uint8_t queue_id)
388 {
389         PMD_DRV_FUNC_TRACE();
390
391         RTE_SET_USED(dev);
392         RTE_SET_USED(queue_id);
393 }
394
395 static int
396 dpaa2_eventdev_queue_setup(struct rte_eventdev *dev, uint8_t queue_id,
397                            const struct rte_event_queue_conf *queue_conf)
398 {
399         struct dpaa2_eventdev *priv = dev->data->dev_private;
400         struct evq_info_t *evq_info =
401                 &priv->evq_info[queue_id];
402
403         PMD_DRV_FUNC_TRACE();
404
405         evq_info->event_queue_cfg = queue_conf->event_queue_cfg;
406
407         return 0;
408 }
409
410 static void
411 dpaa2_eventdev_port_def_conf(struct rte_eventdev *dev, uint8_t port_id,
412                              struct rte_event_port_conf *port_conf)
413 {
414         PMD_DRV_FUNC_TRACE();
415
416         RTE_SET_USED(dev);
417         RTE_SET_USED(port_id);
418         RTE_SET_USED(port_conf);
419
420         port_conf->new_event_threshold =
421                 DPAA2_EVENT_MAX_NUM_EVENTS;
422         port_conf->dequeue_depth =
423                 DPAA2_EVENT_MAX_PORT_DEQUEUE_DEPTH;
424         port_conf->enqueue_depth =
425                 DPAA2_EVENT_MAX_PORT_ENQUEUE_DEPTH;
426 }
427
428 static void
429 dpaa2_eventdev_port_release(void *port)
430 {
431         PMD_DRV_FUNC_TRACE();
432
433         RTE_SET_USED(port);
434 }
435
436 static int
437 dpaa2_eventdev_port_setup(struct rte_eventdev *dev, uint8_t port_id,
438                           const struct rte_event_port_conf *port_conf)
439 {
440         PMD_DRV_FUNC_TRACE();
441
442         RTE_SET_USED(port_conf);
443
444         if (!dpaa2_io_portal[port_id].dpio_dev) {
445                 dpaa2_io_portal[port_id].dpio_dev =
446                                 dpaa2_get_qbman_swp(port_id);
447                 rte_atomic16_inc(&dpaa2_io_portal[port_id].dpio_dev->ref_count);
448                 if (!dpaa2_io_portal[port_id].dpio_dev)
449                         return -1;
450         }
451
452         dpaa2_io_portal[port_id].eventdev = dev;
453         dev->data->ports[port_id] = &dpaa2_io_portal[port_id];
454         return 0;
455 }
456
457 static int
458 dpaa2_eventdev_port_unlink(struct rte_eventdev *dev, void *port,
459                            uint8_t queues[], uint16_t nb_unlinks)
460 {
461         struct dpaa2_eventdev *priv = dev->data->dev_private;
462         struct dpaa2_io_portal_t *dpaa2_portal = port;
463         struct evq_info_t *evq_info;
464         int i;
465
466         PMD_DRV_FUNC_TRACE();
467
468         for (i = 0; i < nb_unlinks; i++) {
469                 evq_info = &priv->evq_info[queues[i]];
470                 qbman_swp_push_set(dpaa2_portal->dpio_dev->sw_portal,
471                                    evq_info->dpcon->channel_index, 0);
472                 dpio_remove_static_dequeue_channel(dpaa2_portal->dpio_dev->dpio,
473                                         0, dpaa2_portal->dpio_dev->token,
474                         evq_info->dpcon->dpcon_id);
475                 evq_info->link = 0;
476         }
477
478         return (int)nb_unlinks;
479 }
480
481 static int
482 dpaa2_eventdev_port_link(struct rte_eventdev *dev, void *port,
483                          const uint8_t queues[], const uint8_t priorities[],
484                         uint16_t nb_links)
485 {
486         struct dpaa2_eventdev *priv = dev->data->dev_private;
487         struct dpaa2_io_portal_t *dpaa2_portal = port;
488         struct evq_info_t *evq_info;
489         uint8_t channel_index;
490         int ret, i, n;
491
492         PMD_DRV_FUNC_TRACE();
493
494         for (i = 0; i < nb_links; i++) {
495                 evq_info = &priv->evq_info[queues[i]];
496                 if (evq_info->link)
497                         continue;
498
499                 ret = dpio_add_static_dequeue_channel(
500                         dpaa2_portal->dpio_dev->dpio,
501                         CMD_PRI_LOW, dpaa2_portal->dpio_dev->token,
502                         evq_info->dpcon->dpcon_id, &channel_index);
503                 if (ret < 0) {
504                         PMD_DRV_ERR("Static dequeue cfg failed with ret: %d\n",
505                                     ret);
506                         goto err;
507                 }
508
509                 qbman_swp_push_set(dpaa2_portal->dpio_dev->sw_portal,
510                                    channel_index, 1);
511                 evq_info->dpcon->channel_index = channel_index;
512                 evq_info->link = 1;
513         }
514
515         RTE_SET_USED(priorities);
516
517         return (int)nb_links;
518 err:
519         for (n = 0; n < i; n++) {
520                 evq_info = &priv->evq_info[queues[n]];
521                 qbman_swp_push_set(dpaa2_portal->dpio_dev->sw_portal,
522                                    evq_info->dpcon->channel_index, 0);
523                 dpio_remove_static_dequeue_channel(dpaa2_portal->dpio_dev->dpio,
524                                         0, dpaa2_portal->dpio_dev->token,
525                         evq_info->dpcon->dpcon_id);
526                 evq_info->link = 0;
527         }
528         return ret;
529 }
530
531 static int
532 dpaa2_eventdev_timeout_ticks(struct rte_eventdev *dev, uint64_t ns,
533                              uint64_t *timeout_ticks)
534 {
535         uint32_t scale = 1;
536
537         PMD_DRV_FUNC_TRACE();
538
539         RTE_SET_USED(dev);
540         *timeout_ticks = ns * scale;
541
542         return 0;
543 }
544
545 static void
546 dpaa2_eventdev_dump(struct rte_eventdev *dev, FILE *f)
547 {
548         PMD_DRV_FUNC_TRACE();
549
550         RTE_SET_USED(dev);
551         RTE_SET_USED(f);
552 }
553
554 static const struct rte_eventdev_ops dpaa2_eventdev_ops = {
555         .dev_infos_get    = dpaa2_eventdev_info_get,
556         .dev_configure    = dpaa2_eventdev_configure,
557         .dev_start        = dpaa2_eventdev_start,
558         .dev_stop         = dpaa2_eventdev_stop,
559         .dev_close        = dpaa2_eventdev_close,
560         .queue_def_conf   = dpaa2_eventdev_queue_def_conf,
561         .queue_setup      = dpaa2_eventdev_queue_setup,
562         .queue_release    = dpaa2_eventdev_queue_release,
563         .port_def_conf    = dpaa2_eventdev_port_def_conf,
564         .port_setup       = dpaa2_eventdev_port_setup,
565         .port_release     = dpaa2_eventdev_port_release,
566         .port_link        = dpaa2_eventdev_port_link,
567         .port_unlink      = dpaa2_eventdev_port_unlink,
568         .timeout_ticks    = dpaa2_eventdev_timeout_ticks,
569         .dump             = dpaa2_eventdev_dump
570 };
571
572 static int
573 dpaa2_eventdev_setup_dpci(struct dpaa2_dpci_dev *dpci_dev,
574                           struct dpaa2_dpcon_dev *dpcon_dev)
575 {
576         struct dpci_rx_queue_cfg rx_queue_cfg;
577         int ret, i;
578
579         /*Do settings to get the frame on a DPCON object*/
580         rx_queue_cfg.options = DPCI_QUEUE_OPT_DEST |
581                   DPCI_QUEUE_OPT_USER_CTX;
582         rx_queue_cfg.dest_cfg.dest_type = DPCI_DEST_DPCON;
583         rx_queue_cfg.dest_cfg.dest_id = dpcon_dev->dpcon_id;
584         rx_queue_cfg.dest_cfg.priority = DPAA2_EVENT_DEFAULT_DPCI_PRIO;
585
586         dpci_dev->queue[DPAA2_EVENT_DPCI_PARALLEL_QUEUE].cb =
587                 dpaa2_eventdev_process_parallel;
588         dpci_dev->queue[DPAA2_EVENT_DPCI_ATOMIC_QUEUE].cb =
589                 dpaa2_eventdev_process_atomic;
590
591         for (i = 0 ; i < DPAA2_EVENT_DPCI_MAX_QUEUES; i++) {
592                 rx_queue_cfg.user_ctx = (uint64_t)(&dpci_dev->queue[i]);
593                 ret = dpci_set_rx_queue(&dpci_dev->dpci,
594                                         CMD_PRI_LOW,
595                                         dpci_dev->token, i,
596                                         &rx_queue_cfg);
597                 if (ret) {
598                         PMD_DRV_LOG(ERR,
599                                     "set_rx_q failed with err code: %d", ret);
600                         return ret;
601                 }
602         }
603         return 0;
604 }
605
606 static int
607 dpaa2_eventdev_create(const char *name)
608 {
609         struct rte_eventdev *eventdev;
610         struct dpaa2_eventdev *priv;
611         struct dpaa2_dpcon_dev *dpcon_dev = NULL;
612         struct dpaa2_dpci_dev *dpci_dev = NULL;
613         int ret;
614
615         eventdev = rte_event_pmd_vdev_init(name,
616                                            sizeof(struct dpaa2_eventdev),
617                                            rte_socket_id());
618         if (eventdev == NULL) {
619                 PMD_DRV_ERR("Failed to create eventdev vdev %s", name);
620                 goto fail;
621         }
622
623         eventdev->dev_ops       = &dpaa2_eventdev_ops;
624         eventdev->schedule      = NULL;
625         eventdev->enqueue       = dpaa2_eventdev_enqueue;
626         eventdev->enqueue_burst = dpaa2_eventdev_enqueue_burst;
627         eventdev->enqueue_new_burst = dpaa2_eventdev_enqueue_burst;
628         eventdev->enqueue_forward_burst = dpaa2_eventdev_enqueue_burst;
629         eventdev->dequeue       = dpaa2_eventdev_dequeue;
630         eventdev->dequeue_burst = dpaa2_eventdev_dequeue_burst;
631
632         /* For secondary processes, the primary has done all the work */
633         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
634                 return 0;
635
636         priv = eventdev->data->dev_private;
637         priv->max_event_queues = 0;
638
639         do {
640                 dpcon_dev = rte_dpaa2_alloc_dpcon_dev();
641                 if (!dpcon_dev)
642                         break;
643                 priv->evq_info[priv->max_event_queues].dpcon = dpcon_dev;
644
645                 dpci_dev = rte_dpaa2_alloc_dpci_dev();
646                 if (!dpci_dev) {
647                         rte_dpaa2_free_dpcon_dev(dpcon_dev);
648                         break;
649                 }
650                 priv->evq_info[priv->max_event_queues].dpci = dpci_dev;
651
652                 ret = dpaa2_eventdev_setup_dpci(dpci_dev, dpcon_dev);
653                 if (ret) {
654                         PMD_DRV_LOG(ERR,
655                                     "dpci setup failed with err code: %d", ret);
656                         return ret;
657                 }
658                 priv->max_event_queues++;
659         } while (dpcon_dev && dpci_dev);
660
661         return 0;
662 fail:
663         return -EFAULT;
664 }
665
666 static int
667 dpaa2_eventdev_probe(struct rte_vdev_device *vdev)
668 {
669         const char *name;
670
671         name = rte_vdev_device_name(vdev);
672         PMD_DRV_LOG(INFO, "Initializing %s", name);
673         return dpaa2_eventdev_create(name);
674 }
675
676 static int
677 dpaa2_eventdev_remove(struct rte_vdev_device *vdev)
678 {
679         const char *name;
680
681         name = rte_vdev_device_name(vdev);
682         PMD_DRV_LOG(INFO, "Closing %s", name);
683
684         return rte_event_pmd_vdev_uninit(name);
685 }
686
687 static struct rte_vdev_driver vdev_eventdev_dpaa2_pmd = {
688         .probe = dpaa2_eventdev_probe,
689         .remove = dpaa2_eventdev_remove
690 };
691
692 RTE_PMD_REGISTER_VDEV(EVENTDEV_NAME_DPAA2_PMD, vdev_eventdev_dpaa2_pmd);