drivers/net/atlantic/hw_atl/hw_atl_llh.c

   1 // SPDX-License-Identifier: (BSD-3-Clause OR GPL-2.0)
   2 /* Copyright (C) 2014-2017 aQuantia Corporation. */
   3
   4 /* File hw_atl_llh.c: Definitions of bitfield and register access functions for
   5  * Atlantic registers.
   6  */
   7
   8 #include "hw_atl_llh.h"
   9
  10 #include "../atl_hw_regs.h"
  11 #include "hw_atl_llh_internal.h"
  12
  13 /* global */
  14 void hw_atl_reg_glb_cpu_sem_set(struct aq_hw_s *aq_hw, u32 glb_cpu_sem,
  15                                 u32 semaphore)
  16 {
  17         aq_hw_write_reg(aq_hw, HW_ATL_GLB_CPU_SEM_ADR(semaphore), glb_cpu_sem);
  18 }
  19
  20 u32 hw_atl_reg_glb_cpu_sem_get(struct aq_hw_s *aq_hw, u32 semaphore)
  21 {
  22         return aq_hw_read_reg(aq_hw, HW_ATL_GLB_CPU_SEM_ADR(semaphore));
  23 }
  24
  25 void hw_atl_glb_glb_reg_res_dis_set(struct aq_hw_s *aq_hw, u32 glb_reg_res_dis)
  26 {
  27         aq_hw_write_reg_bit(aq_hw, HW_ATL_GLB_REG_RES_DIS_ADR,
  28                             HW_ATL_GLB_REG_RES_DIS_MSK,
  29                             HW_ATL_GLB_REG_RES_DIS_SHIFT,
  30                             glb_reg_res_dis);
  31 }
  32
  33 void hw_atl_glb_soft_res_set(struct aq_hw_s *aq_hw, u32 soft_res)
  34 {
  35         aq_hw_write_reg_bit(aq_hw, HW_ATL_GLB_SOFT_RES_ADR,
  36                             HW_ATL_GLB_SOFT_RES_MSK,
  37                             HW_ATL_GLB_SOFT_RES_SHIFT, soft_res);
  38 }
  39
  40 u32 hw_atl_glb_soft_res_get(struct aq_hw_s *aq_hw)
  41 {
  42         return aq_hw_read_reg_bit(aq_hw, HW_ATL_GLB_SOFT_RES_ADR,
  43                                   HW_ATL_GLB_SOFT_RES_MSK,
  44                                   HW_ATL_GLB_SOFT_RES_SHIFT);
  45 }
  46
  47 u32 hw_atl_reg_glb_mif_id_get(struct aq_hw_s *aq_hw)
  48 {
  49         return aq_hw_read_reg(aq_hw, HW_ATL_GLB_MIF_ID_ADR);
  50 }
  51
  52 /* stats */
  53 u32 hw_atl_rpb_rx_dma_drop_pkt_cnt_get(struct aq_hw_s *aq_hw)
  54 {
  55         return aq_hw_read_reg(aq_hw, HW_ATL_RPB_RX_DMA_DROP_PKT_CNT_ADR);
  56 }
  57
  58 u32 hw_atl_stats_rx_dma_good_octet_counterlsw_get(struct aq_hw_s *aq_hw)
  59 {
  60         return aq_hw_read_reg(aq_hw, HW_ATL_STATS_RX_DMA_GOOD_OCTET_COUNTERLSW);
  61 }
  62
  63 u32 hw_atl_stats_rx_dma_good_pkt_counterlsw_get(struct aq_hw_s *aq_hw)
  64 {
  65         return aq_hw_read_reg(aq_hw, HW_ATL_STATS_RX_DMA_GOOD_PKT_COUNTERLSW);
  66 }
  67
  68 u32 hw_atl_stats_tx_dma_good_octet_counterlsw_get(struct aq_hw_s *aq_hw)
  69 {
  70         return aq_hw_read_reg(aq_hw, HW_ATL_STATS_TX_DMA_GOOD_OCTET_COUNTERLSW);
  71 }
  72
  73 u32 hw_atl_stats_tx_dma_good_pkt_counterlsw_get(struct aq_hw_s *aq_hw)
  74 {
  75         return aq_hw_read_reg(aq_hw, HW_ATL_STATS_TX_DMA_GOOD_PKT_COUNTERLSW);
  76 }
  77
  78 u32 hw_atl_stats_rx_dma_good_octet_countermsw_get(struct aq_hw_s *aq_hw)
  79 {
  80         return aq_hw_read_reg(aq_hw, HW_ATL_STATS_RX_DMA_GOOD_OCTET_COUNTERMSW);
  81 }
  82
  83 u32 hw_atl_stats_rx_dma_good_pkt_countermsw_get(struct aq_hw_s *aq_hw)
  84 {
  85         return aq_hw_read_reg(aq_hw, HW_ATL_STATS_RX_DMA_GOOD_PKT_COUNTERMSW);
  86 }
  87
  88 u32 hw_atl_stats_tx_dma_good_octet_countermsw_get(struct aq_hw_s *aq_hw)
  89 {
  90         return aq_hw_read_reg(aq_hw, HW_ATL_STATS_TX_DMA_GOOD_OCTET_COUNTERMSW);
  91 }
  92
  93 u32 hw_atl_stats_tx_dma_good_pkt_countermsw_get(struct aq_hw_s *aq_hw)
  94 {
  95         return aq_hw_read_reg(aq_hw, HW_ATL_STATS_TX_DMA_GOOD_PKT_COUNTERMSW);
  96 }
  97
  98 /* interrupt */
  99 void hw_atl_itr_irq_auto_masklsw_set(struct aq_hw_s *aq_hw,
 100                                      u32 irq_auto_masklsw)
 101 {
 102         aq_hw_write_reg(aq_hw, HW_ATL_ITR_IAMRLSW_ADR, irq_auto_masklsw);
 103 }
 104
 105 void hw_atl_itr_irq_map_en_rx_set(struct aq_hw_s *aq_hw, u32 irq_map_en_rx,
 106                                   u32 rx)
 107 {
 108 /* register address for bitfield imr_rx{r}_en */
 109         static const u32 itr_imr_rxren_adr[32] = {
 110                         0x00002100U, 0x00002100U, 0x00002104U, 0x00002104U,
 111                         0x00002108U, 0x00002108U, 0x0000210CU, 0x0000210CU,
 112                         0x00002110U, 0x00002110U, 0x00002114U, 0x00002114U,
 113                         0x00002118U, 0x00002118U, 0x0000211CU, 0x0000211CU,
 114                         0x00002120U, 0x00002120U, 0x00002124U, 0x00002124U,
 115                         0x00002128U, 0x00002128U, 0x0000212CU, 0x0000212CU,
 116                         0x00002130U, 0x00002130U, 0x00002134U, 0x00002134U,
 117                         0x00002138U, 0x00002138U, 0x0000213CU, 0x0000213CU
 118                 };
 119
 120 /* bitmask for bitfield imr_rx{r}_en */
 121         static const u32 itr_imr_rxren_msk[32] = {
 122                         0x00008000U, 0x00000080U, 0x00008000U, 0x00000080U,
 123                         0x00008000U, 0x00000080U, 0x00008000U, 0x00000080U,
 124                         0x00008000U, 0x00000080U, 0x00008000U, 0x00000080U,
 125                         0x00008000U, 0x00000080U, 0x00008000U, 0x00000080U,
 126                         0x00008000U, 0x00000080U, 0x00008000U, 0x00000080U,
 127                         0x00008000U, 0x00000080U, 0x00008000U, 0x00000080U,
 128                         0x00008000U, 0x00000080U, 0x00008000U, 0x00000080U,
 129                         0x00008000U, 0x00000080U, 0x00008000U, 0x00000080U
 130                 };
 131
 132 /* lower bit position of bitfield imr_rx{r}_en */
 133         static const u32 itr_imr_rxren_shift[32] = {
 134                         15U, 7U, 15U, 7U, 15U, 7U, 15U, 7U,
 135                         15U, 7U, 15U, 7U, 15U, 7U, 15U, 7U,
 136                         15U, 7U, 15U, 7U, 15U, 7U, 15U, 7U,
 137                         15U, 7U, 15U, 7U, 15U, 7U, 15U, 7U
 138                 };
 139
 140         aq_hw_write_reg_bit(aq_hw, itr_imr_rxren_adr[rx],
 141                             itr_imr_rxren_msk[rx],
 142                             itr_imr_rxren_shift[rx],
 143                             irq_map_en_rx);
 144 }
 145
 146 void hw_atl_itr_irq_map_en_tx_set(struct aq_hw_s *aq_hw, u32 irq_map_en_tx,
 147                                   u32 tx)
 148 {
 149 /* register address for bitfield imr_tx{t}_en */
 150         static const u32 itr_imr_txten_adr[32] = {
 151                         0x00002100U, 0x00002100U, 0x00002104U, 0x00002104U,
 152                         0x00002108U, 0x00002108U, 0x0000210CU, 0x0000210CU,
 153                         0x00002110U, 0x00002110U, 0x00002114U, 0x00002114U,
 154                         0x00002118U, 0x00002118U, 0x0000211CU, 0x0000211CU,
 155                         0x00002120U, 0x00002120U, 0x00002124U, 0x00002124U,
 156                         0x00002128U, 0x00002128U, 0x0000212CU, 0x0000212CU,
 157                         0x00002130U, 0x00002130U, 0x00002134U, 0x00002134U,
 158                         0x00002138U, 0x00002138U, 0x0000213CU, 0x0000213CU
 159                 };
 160
 161 /* bitmask for bitfield imr_tx{t}_en */
 162         static const u32 itr_imr_txten_msk[32] = {
 163                         0x80000000U, 0x00800000U, 0x80000000U, 0x00800000U,
 164                         0x80000000U, 0x00800000U, 0x80000000U, 0x00800000U,
 165                         0x80000000U, 0x00800000U, 0x80000000U, 0x00800000U,
 166                         0x80000000U, 0x00800000U, 0x80000000U, 0x00800000U,
 167                         0x80000000U, 0x00800000U, 0x80000000U, 0x00800000U,
 168                         0x80000000U, 0x00800000U, 0x80000000U, 0x00800000U,
 169                         0x80000000U, 0x00800000U, 0x80000000U, 0x00800000U,
 170                         0x80000000U, 0x00800000U, 0x80000000U, 0x00800000U
 171                 };
 172
 173 /* lower bit position of bitfield imr_tx{t}_en */
 174         static const u32 itr_imr_txten_shift[32] = {
 175                         31U, 23U, 31U, 23U, 31U, 23U, 31U, 23U,
 176                         31U, 23U, 31U, 23U, 31U, 23U, 31U, 23U,
 177                         31U, 23U, 31U, 23U, 31U, 23U, 31U, 23U,
 178                         31U, 23U, 31U, 23U, 31U, 23U, 31U, 23U
 179                 };
 180
 181         aq_hw_write_reg_bit(aq_hw, itr_imr_txten_adr[tx],
 182                             itr_imr_txten_msk[tx],
 183                             itr_imr_txten_shift[tx],
 184                             irq_map_en_tx);
 185 }
 186
 187 void hw_atl_itr_irq_map_rx_set(struct aq_hw_s *aq_hw, u32 irq_map_rx, u32 rx)
 188 {
 189 /* register address for bitfield imr_rx{r}[4:0] */
 190         static const u32 itr_imr_rxr_adr[32] = {
 191                         0x00002100U, 0x00002100U, 0x00002104U, 0x00002104U,
 192                         0x00002108U, 0x00002108U, 0x0000210CU, 0x0000210CU,
 193                         0x00002110U, 0x00002110U, 0x00002114U, 0x00002114U,
 194                         0x00002118U, 0x00002118U, 0x0000211CU, 0x0000211CU,
 195                         0x00002120U, 0x00002120U, 0x00002124U, 0x00002124U,
 196                         0x00002128U, 0x00002128U, 0x0000212CU, 0x0000212CU,
 197                         0x00002130U, 0x00002130U, 0x00002134U, 0x00002134U,
 198                         0x00002138U, 0x00002138U, 0x0000213CU, 0x0000213CU
 199                 };
 200
 201 /* bitmask for bitfield imr_rx{r}[4:0] */
 202         static const u32 itr_imr_rxr_msk[32] = {
 203                         0x00001f00U, 0x0000001FU, 0x00001F00U, 0x0000001FU,
 204                         0x00001f00U, 0x0000001FU, 0x00001F00U, 0x0000001FU,
 205                         0x00001f00U, 0x0000001FU, 0x00001F00U, 0x0000001FU,
 206                         0x00001f00U, 0x0000001FU, 0x00001F00U, 0x0000001FU,
 207                         0x00001f00U, 0x0000001FU, 0x00001F00U, 0x0000001FU,
 208                         0x00001f00U, 0x0000001FU, 0x00001F00U, 0x0000001FU,
 209                         0x00001f00U, 0x0000001FU, 0x00001F00U, 0x0000001FU,
 210                         0x00001f00U, 0x0000001FU, 0x00001F00U, 0x0000001FU
 211                 };
 212
 213 /* lower bit position of bitfield imr_rx{r}[4:0] */
 214         static const u32 itr_imr_rxr_shift[32] = {
 215                         8U, 0U, 8U, 0U, 8U, 0U, 8U, 0U,
 216                         8U, 0U, 8U, 0U, 8U, 0U, 8U, 0U,
 217                         8U, 0U, 8U, 0U, 8U, 0U, 8U, 0U,
 218                         8U, 0U, 8U, 0U, 8U, 0U, 8U, 0U
 219                 };
 220
 221         aq_hw_write_reg_bit(aq_hw, itr_imr_rxr_adr[rx],
 222                             itr_imr_rxr_msk[rx],
 223                             itr_imr_rxr_shift[rx],
 224                             irq_map_rx);
 225 }
 226
 227 void hw_atl_itr_irq_map_tx_set(struct aq_hw_s *aq_hw, u32 irq_map_tx, u32 tx)
 228 {
 229 /* register address for bitfield imr_tx{t}[4:0] */
 230         static const u32 itr_imr_txt_adr[32] = {
 231                         0x00002100U, 0x00002100U, 0x00002104U, 0x00002104U,
 232                         0x00002108U, 0x00002108U, 0x0000210CU, 0x0000210CU,
 233                         0x00002110U, 0x00002110U, 0x00002114U, 0x00002114U,
 234                         0x00002118U, 0x00002118U, 0x0000211CU, 0x0000211CU,
 235                         0x00002120U, 0x00002120U, 0x00002124U, 0x00002124U,
 236                         0x00002128U, 0x00002128U, 0x0000212CU, 0x0000212CU,
 237                         0x00002130U, 0x00002130U, 0x00002134U, 0x00002134U,
 238                         0x00002138U, 0x00002138U, 0x0000213CU, 0x0000213CU
 239                 };
 240
 241 /* bitmask for bitfield imr_tx{t}[4:0] */
 242         static const u32 itr_imr_txt_msk[32] = {
 243                         0x1f000000U, 0x001F0000U, 0x1F000000U, 0x001F0000U,
 244                         0x1f000000U, 0x001F0000U, 0x1F000000U, 0x001F0000U,
 245                         0x1f000000U, 0x001F0000U, 0x1F000000U, 0x001F0000U,
 246                         0x1f000000U, 0x001F0000U, 0x1F000000U, 0x001F0000U,
 247                         0x1f000000U, 0x001F0000U, 0x1F000000U, 0x001F0000U,
 248                         0x1f000000U, 0x001F0000U, 0x1F000000U, 0x001F0000U,
 249                         0x1f000000U, 0x001F0000U, 0x1F000000U, 0x001F0000U,
 250                         0x1f000000U, 0x001F0000U, 0x1F000000U, 0x001F0000U
 251                 };
 252
 253 /* lower bit position of bitfield imr_tx{t}[4:0] */
 254         static const u32 itr_imr_txt_shift[32] = {
 255                         24U, 16U, 24U, 16U, 24U, 16U, 24U, 16U,
 256                         24U, 16U, 24U, 16U, 24U, 16U, 24U, 16U,
 257                         24U, 16U, 24U, 16U, 24U, 16U, 24U, 16U,
 258                         24U, 16U, 24U, 16U, 24U, 16U, 24U, 16U
 259                 };
 260
 261         aq_hw_write_reg_bit(aq_hw, itr_imr_txt_adr[tx],
 262                             itr_imr_txt_msk[tx],
 263                             itr_imr_txt_shift[tx],
 264                             irq_map_tx);
 265 }
 266
 267 void hw_atl_itr_irq_msk_clearlsw_set(struct aq_hw_s *aq_hw,
 268                                      u32 irq_msk_clearlsw)
 269 {
 270         aq_hw_write_reg(aq_hw, HW_ATL_ITR_IMCRLSW_ADR, irq_msk_clearlsw);
 271 }
 272
 273 void hw_atl_itr_irq_msk_setlsw_set(struct aq_hw_s *aq_hw, u32 irq_msk_setlsw)
 274 {
 275         aq_hw_write_reg(aq_hw, HW_ATL_ITR_IMSRLSW_ADR, irq_msk_setlsw);
 276 }
 277
 278 void hw_atl_itr_irq_reg_res_dis_set(struct aq_hw_s *aq_hw, u32 irq_reg_res_dis)
 279 {
 280         aq_hw_write_reg_bit(aq_hw, HW_ATL_ITR_REG_RES_DSBL_ADR,
 281                             HW_ATL_ITR_REG_RES_DSBL_MSK,
 282                             HW_ATL_ITR_REG_RES_DSBL_SHIFT, irq_reg_res_dis);
 283 }
 284
 285 void hw_atl_itr_irq_status_clearlsw_set(struct aq_hw_s *aq_hw,
 286                                         u32 irq_status_clearlsw)
 287 {
 288         aq_hw_write_reg(aq_hw, HW_ATL_ITR_ISCRLSW_ADR, irq_status_clearlsw);
 289 }
 290
 291 u32 hw_atl_itr_irq_statuslsw_get(struct aq_hw_s *aq_hw)
 292 {
 293         return aq_hw_read_reg(aq_hw, HW_ATL_ITR_ISRLSW_ADR);
 294 }
 295
 296 u32 hw_atl_itr_res_irq_get(struct aq_hw_s *aq_hw)
 297 {
 298         return aq_hw_read_reg_bit(aq_hw, HW_ATL_ITR_RES_ADR, HW_ATL_ITR_RES_MSK,
 299                                   HW_ATL_ITR_RES_SHIFT);
 300 }
 301
 302 void hw_atl_itr_res_irq_set(struct aq_hw_s *aq_hw, u32 res_irq)
 303 {
 304         aq_hw_write_reg_bit(aq_hw, HW_ATL_ITR_RES_ADR, HW_ATL_ITR_RES_MSK,
 305                             HW_ATL_ITR_RES_SHIFT, res_irq);
 306 }
 307
 308 /* rdm */
 309 void hw_atl_rdm_cpu_id_set(struct aq_hw_s *aq_hw, u32 cpuid, u32 dca)
 310 {
 311         aq_hw_write_reg_bit(aq_hw, HW_ATL_RDM_DCADCPUID_ADR(dca),
 312                             HW_ATL_RDM_DCADCPUID_MSK,
 313                             HW_ATL_RDM_DCADCPUID_SHIFT, cpuid);
 314 }
 315
 316 void hw_atl_rdm_rx_dca_en_set(struct aq_hw_s *aq_hw, u32 rx_dca_en)
 317 {
 318         aq_hw_write_reg_bit(aq_hw, HW_ATL_RDM_DCA_EN_ADR, HW_ATL_RDM_DCA_EN_MSK,
 319                             HW_ATL_RDM_DCA_EN_SHIFT, rx_dca_en);
 320 }
 321
 322 void hw_atl_rdm_rx_dca_mode_set(struct aq_hw_s *aq_hw, u32 rx_dca_mode)
 323 {
 324         aq_hw_write_reg_bit(aq_hw, HW_ATL_RDM_DCA_MODE_ADR,
 325                             HW_ATL_RDM_DCA_MODE_MSK,
 326                             HW_ATL_RDM_DCA_MODE_SHIFT, rx_dca_mode);
 327 }
 328
 329 void hw_atl_rdm_rx_desc_data_buff_size_set(struct aq_hw_s *aq_hw,
 330                                            u32 rx_desc_data_buff_size,
 331                                            u32 descriptor)
 332 {
 333         aq_hw_write_reg_bit(aq_hw, HW_ATL_RDM_DESCDDATA_SIZE_ADR(descriptor),
 334                             HW_ATL_RDM_DESCDDATA_SIZE_MSK,
 335                             HW_ATL_RDM_DESCDDATA_SIZE_SHIFT,
 336                             rx_desc_data_buff_size);
 337 }
 338
 339 void hw_atl_rdm_rx_desc_dca_en_set(struct aq_hw_s *aq_hw, u32 rx_desc_dca_en,
 340                                    u32 dca)
 341 {
 342         aq_hw_write_reg_bit(aq_hw, HW_ATL_RDM_DCADDESC_EN_ADR(dca),
 343                             HW_ATL_RDM_DCADDESC_EN_MSK,
 344                             HW_ATL_RDM_DCADDESC_EN_SHIFT,
 345                             rx_desc_dca_en);
 346 }
 347
 348 void hw_atl_rdm_rx_desc_en_set(struct aq_hw_s *aq_hw, u32 rx_desc_en,
 349                                u32 descriptor)
 350 {
 351         aq_hw_write_reg_bit(aq_hw, HW_ATL_RDM_DESCDEN_ADR(descriptor),
 352                             HW_ATL_RDM_DESCDEN_MSK,
 353                             HW_ATL_RDM_DESCDEN_SHIFT,
 354                             rx_desc_en);
 355 }
 356
 357 void hw_atl_rdm_rx_desc_head_buff_size_set(struct aq_hw_s *aq_hw,
 358                                            u32 rx_desc_head_buff_size,
 359                                            u32 descriptor)
 360 {
 361         aq_hw_write_reg_bit(aq_hw, HW_ATL_RDM_DESCDHDR_SIZE_ADR(descriptor),
 362                             HW_ATL_RDM_DESCDHDR_SIZE_MSK,
 363                             HW_ATL_RDM_DESCDHDR_SIZE_SHIFT,
 364                             rx_desc_head_buff_size);
 365 }
 366
 367 void hw_atl_rdm_rx_desc_head_splitting_set(struct aq_hw_s *aq_hw,
 368                                            u32 rx_desc_head_splitting,
 369                                            u32 descriptor)
 370 {
 371         aq_hw_write_reg_bit(aq_hw, HW_ATL_RDM_DESCDHDR_SPLIT_ADR(descriptor),
 372                             HW_ATL_RDM_DESCDHDR_SPLIT_MSK,
 373                             HW_ATL_RDM_DESCDHDR_SPLIT_SHIFT,
 374                             rx_desc_head_splitting);
 375 }
 376
 377 u32 hw_atl_rdm_rx_desc_head_ptr_get(struct aq_hw_s *aq_hw, u32 descriptor)
 378 {
 379         return aq_hw_read_reg_bit(aq_hw, HW_ATL_RDM_DESCDHD_ADR(descriptor),
 380                                   HW_ATL_RDM_DESCDHD_MSK,
 381                                   HW_ATL_RDM_DESCDHD_SHIFT);
 382 }
 383
 384 void hw_atl_rdm_rx_desc_len_set(struct aq_hw_s *aq_hw, u32 rx_desc_len,
 385                                 u32 descriptor)
 386 {
 387         aq_hw_write_reg_bit(aq_hw, HW_ATL_RDM_DESCDLEN_ADR(descriptor),
 388                             HW_ATL_RDM_DESCDLEN_MSK, HW_ATL_RDM_DESCDLEN_SHIFT,
 389                             rx_desc_len);
 390 }
 391
 392 void hw_atl_rdm_rx_desc_res_set(struct aq_hw_s *aq_hw, u32 rx_desc_res,
 393                                 u32 descriptor)
 394 {
 395         aq_hw_write_reg_bit(aq_hw, HW_ATL_RDM_DESCDRESET_ADR(descriptor),
 396                             HW_ATL_RDM_DESCDRESET_MSK,
 397                             HW_ATL_RDM_DESCDRESET_SHIFT,
 398                             rx_desc_res);
 399 }
 400
 401 void hw_atl_rdm_rx_desc_wr_wb_irq_en_set(struct aq_hw_s *aq_hw,
 402                                          u32 rx_desc_wr_wb_irq_en)
 403 {
 404         aq_hw_write_reg_bit(aq_hw, HW_ATL_RDM_INT_DESC_WRB_EN_ADR,
 405                             HW_ATL_RDM_INT_DESC_WRB_EN_MSK,
 406                             HW_ATL_RDM_INT_DESC_WRB_EN_SHIFT,
 407                             rx_desc_wr_wb_irq_en);
 408 }
 409
 410 void hw_atl_rdm_rx_head_dca_en_set(struct aq_hw_s *aq_hw, u32 rx_head_dca_en,
 411                                    u32 dca)
 412 {
 413         aq_hw_write_reg_bit(aq_hw, HW_ATL_RDM_DCADHDR_EN_ADR(dca),
 414                             HW_ATL_RDM_DCADHDR_EN_MSK,
 415                             HW_ATL_RDM_DCADHDR_EN_SHIFT,
 416                             rx_head_dca_en);
 417 }
 418
 419 void hw_atl_rdm_rx_pld_dca_en_set(struct aq_hw_s *aq_hw, u32 rx_pld_dca_en,
 420                                   u32 dca)
 421 {
 422         aq_hw_write_reg_bit(aq_hw, HW_ATL_RDM_DCADPAY_EN_ADR(dca),
 423                             HW_ATL_RDM_DCADPAY_EN_MSK,
 424                             HW_ATL_RDM_DCADPAY_EN_SHIFT,
 425                             rx_pld_dca_en);
 426 }
 427
 428 void hw_atl_rdm_rdm_intr_moder_en_set(struct aq_hw_s *aq_hw,
 429                                       u32 rdm_intr_moder_en)
 430 {
 431         aq_hw_write_reg_bit(aq_hw, HW_ATL_RDM_INT_RIM_EN_ADR,
 432                             HW_ATL_RDM_INT_RIM_EN_MSK,
 433                             HW_ATL_RDM_INT_RIM_EN_SHIFT,
 434                             rdm_intr_moder_en);
 435 }
 436
 437 /* reg */
 438 void hw_atl_reg_gen_irq_map_set(struct aq_hw_s *aq_hw, u32 gen_intr_map,
 439                                 u32 regidx)
 440 {
 441         aq_hw_write_reg(aq_hw, HW_ATL_GEN_INTR_MAP_ADR(regidx), gen_intr_map);
 442 }
 443
 444 u32 hw_atl_reg_gen_irq_status_get(struct aq_hw_s *aq_hw)
 445 {
 446         return aq_hw_read_reg(aq_hw, HW_ATL_GEN_INTR_STAT_ADR);
 447 }
 448
 449 void hw_atl_reg_irq_glb_ctl_set(struct aq_hw_s *aq_hw, u32 intr_glb_ctl)
 450 {
 451         aq_hw_write_reg(aq_hw, HW_ATL_INTR_GLB_CTL_ADR, intr_glb_ctl);
 452 }
 453
 454 void hw_atl_reg_irq_thr_set(struct aq_hw_s *aq_hw, u32 intr_thr, u32 throttle)
 455 {
 456         aq_hw_write_reg(aq_hw, HW_ATL_INTR_THR_ADR(throttle), intr_thr);
 457 }
 458
 459 void hw_atl_reg_rx_dma_desc_base_addresslswset(struct aq_hw_s *aq_hw,
 460                                                u32 rx_dma_desc_base_addrlsw,
 461                                                u32 descriptor)
 462 {
 463         aq_hw_write_reg(aq_hw, HW_ATL_RX_DMA_DESC_BASE_ADDRLSW_ADR(descriptor),
 464                         rx_dma_desc_base_addrlsw);
 465 }
 466
 467 void hw_atl_reg_rx_dma_desc_base_addressmswset(struct aq_hw_s *aq_hw,
 468                                                u32 rx_dma_desc_base_addrmsw,
 469                                                u32 descriptor)
 470 {
 471         aq_hw_write_reg(aq_hw, HW_ATL_RX_DMA_DESC_BASE_ADDRMSW_ADR(descriptor),
 472                         rx_dma_desc_base_addrmsw);
 473 }
 474
 475 u32 hw_atl_reg_rx_dma_desc_status_get(struct aq_hw_s *aq_hw, u32 descriptor)
 476 {
 477         return aq_hw_read_reg(aq_hw, HW_ATL_RX_DMA_DESC_STAT_ADR(descriptor));
 478 }
 479
 480 void hw_atl_reg_rx_dma_desc_tail_ptr_set(struct aq_hw_s *aq_hw,
 481                                          u32 rx_dma_desc_tail_ptr,
 482                                          u32 descriptor)
 483 {
 484         aq_hw_write_reg(aq_hw, HW_ATL_RX_DMA_DESC_TAIL_PTR_ADR(descriptor),
 485                         rx_dma_desc_tail_ptr);
 486 }
 487
 488 void hw_atl_reg_rx_flr_mcst_flr_msk_set(struct aq_hw_s *aq_hw,
 489                                         u32 rx_flr_mcst_flr_msk)
 490 {
 491         aq_hw_write_reg(aq_hw, HW_ATL_RX_FLR_MCST_FLR_MSK_ADR,
 492                         rx_flr_mcst_flr_msk);
 493 }
 494
 495 void hw_atl_reg_rx_flr_mcst_flr_set(struct aq_hw_s *aq_hw, u32 rx_flr_mcst_flr,
 496                                     u32 filter)
 497 {
 498         aq_hw_write_reg(aq_hw, HW_ATL_RX_FLR_MCST_FLR_ADR(filter),
 499                         rx_flr_mcst_flr);
 500 }
 501
 502 void hw_atl_reg_rx_flr_rss_control1set(struct aq_hw_s *aq_hw,
 503                                        u32 rx_flr_rss_control1)
 504 {
 505         aq_hw_write_reg(aq_hw, HW_ATL_RX_FLR_RSS_CONTROL1_ADR,
 506                         rx_flr_rss_control1);
 507 }
 508
 509 void hw_atl_reg_rx_flr_control2_set(struct aq_hw_s *aq_hw,
 510                                     u32 rx_filter_control2)
 511 {
 512         aq_hw_write_reg(aq_hw, HW_ATL_RX_FLR_CONTROL2_ADR, rx_filter_control2);
 513 }
 514
 515 void hw_atl_reg_rx_intr_moder_ctrl_set(struct aq_hw_s *aq_hw,
 516                                        u32 rx_intr_moderation_ctl,
 517                                        u32 queue)
 518 {
 519         aq_hw_write_reg(aq_hw, HW_ATL_RX_INTR_MODERATION_CTL_ADR(queue),
 520                         rx_intr_moderation_ctl);
 521 }
 522
 523 void hw_atl_reg_tx_dma_debug_ctl_set(struct aq_hw_s *aq_hw,
 524                                      u32 tx_dma_debug_ctl)
 525 {
 526         aq_hw_write_reg(aq_hw, HW_ATL_TX_DMA_DEBUG_CTL_ADR, tx_dma_debug_ctl);
 527 }
 528
 529 void hw_atl_reg_tx_dma_desc_base_addresslswset(struct aq_hw_s *aq_hw,
 530                                                u32 tx_dma_desc_base_addrlsw,
 531                                                u32 descriptor)
 532 {
 533         aq_hw_write_reg(aq_hw, HW_ATL_TX_DMA_DESC_BASE_ADDRLSW_ADR(descriptor),
 534                         tx_dma_desc_base_addrlsw);
 535 }
 536
 537 void hw_atl_reg_tx_dma_desc_base_addressmswset(struct aq_hw_s *aq_hw,
 538                                                u32 tx_dma_desc_base_addrmsw,
 539                                                u32 descriptor)
 540 {
 541         aq_hw_write_reg(aq_hw, HW_ATL_TX_DMA_DESC_BASE_ADDRMSW_ADR(descriptor),
 542                         tx_dma_desc_base_addrmsw);
 543 }
 544
 545 void hw_atl_reg_tx_dma_desc_tail_ptr_set(struct aq_hw_s *aq_hw,
 546                                          u32 tx_dma_desc_tail_ptr,
 547                                          u32 descriptor)
 548 {
 549         rte_wmb();
 550
 551         aq_hw_write_reg(aq_hw, HW_ATL_TX_DMA_DESC_TAIL_PTR_ADR(descriptor),
 552                         tx_dma_desc_tail_ptr);
 553 }
 554
 555 void hw_atl_reg_tx_intr_moder_ctrl_set(struct aq_hw_s *aq_hw,
 556                                        u32 tx_intr_moderation_ctl,
 557                                        u32 queue)
 558 {
 559         aq_hw_write_reg(aq_hw, HW_ATL_TX_INTR_MODERATION_CTL_ADR(queue),
 560                         tx_intr_moderation_ctl);
 561 }
 562
 563 /* RPB: rx packet buffer */
 564 void hw_atl_rpb_dma_sys_lbk_set(struct aq_hw_s *aq_hw, u32 dma_sys_lbk)
 565 {
 566         aq_hw_write_reg_bit(aq_hw, HW_ATL_RPB_DMA_SYS_LBK_ADR,
 567                             HW_ATL_RPB_DMA_SYS_LBK_MSK,
 568                             HW_ATL_RPB_DMA_SYS_LBK_SHIFT, dma_sys_lbk);
 569 }
 570
 571 void hw_atl_rpb_rpf_rx_traf_class_mode_set(struct aq_hw_s *aq_hw,
 572                                            u32 rx_traf_class_mode)
 573 {
 574         aq_hw_write_reg_bit(aq_hw, HW_ATL_RPB_RPF_RX_TC_MODE_ADR,
 575                             HW_ATL_RPB_RPF_RX_TC_MODE_MSK,
 576                             HW_ATL_RPB_RPF_RX_TC_MODE_SHIFT,
 577                             rx_traf_class_mode);
 578 }
 579
 580 u32 hw_atl_rpb_rpf_rx_traf_class_mode_get(struct aq_hw_s *aq_hw)
 581 {
 582         return aq_hw_read_reg_bit(aq_hw, HW_ATL_RPB_RPF_RX_TC_MODE_ADR,
 583                         HW_ATL_RPB_RPF_RX_TC_MODE_MSK,
 584                         HW_ATL_RPB_RPF_RX_TC_MODE_SHIFT);
 585 }
 586
 587 void hw_atl_rpb_rx_buff_en_set(struct aq_hw_s *aq_hw, u32 rx_buff_en)
 588 {
 589         aq_hw_write_reg_bit(aq_hw, HW_ATL_RPB_RX_BUF_EN_ADR,
 590                             HW_ATL_RPB_RX_BUF_EN_MSK,
 591                             HW_ATL_RPB_RX_BUF_EN_SHIFT, rx_buff_en);
 592 }
 593
 594 void hw_atl_rpb_rx_buff_hi_threshold_per_tc_set(struct aq_hw_s *aq_hw,
 595                                                 u32 rx_buff_hi_threshold_per_tc,
 596                                                 u32 buffer)
 597 {
 598         aq_hw_write_reg_bit(aq_hw, HW_ATL_RPB_RXBHI_THRESH_ADR(buffer),
 599                             HW_ATL_RPB_RXBHI_THRESH_MSK,
 600                             HW_ATL_RPB_RXBHI_THRESH_SHIFT,
 601                             rx_buff_hi_threshold_per_tc);
 602 }
 603
 604 void hw_atl_rpb_rx_buff_lo_threshold_per_tc_set(struct aq_hw_s *aq_hw,
 605                                                 u32 rx_buff_lo_threshold_per_tc,
 606                                                 u32 buffer)
 607 {
 608         aq_hw_write_reg_bit(aq_hw, HW_ATL_RPB_RXBLO_THRESH_ADR(buffer),
 609                             HW_ATL_RPB_RXBLO_THRESH_MSK,
 610                             HW_ATL_RPB_RXBLO_THRESH_SHIFT,
 611                             rx_buff_lo_threshold_per_tc);
 612 }
 613
 614 void hw_atl_rpb_rx_flow_ctl_mode_set(struct aq_hw_s *aq_hw,
 615                                      u32 rx_flow_ctl_mode)
 616 {
 617         aq_hw_write_reg_bit(aq_hw, HW_ATL_RPB_RX_FC_MODE_ADR,
 618                             HW_ATL_RPB_RX_FC_MODE_MSK,
 619                             HW_ATL_RPB_RX_FC_MODE_SHIFT, rx_flow_ctl_mode);
 620 }
 621
 622 void hw_atl_rpb_rx_pkt_buff_size_per_tc_set(struct aq_hw_s *aq_hw,
 623                                             u32 rx_pkt_buff_size_per_tc,
 624                                             u32 buffer)
 625 {
 626         aq_hw_write_reg_bit(aq_hw, HW_ATL_RPB_RXBBUF_SIZE_ADR(buffer),
 627                             HW_ATL_RPB_RXBBUF_SIZE_MSK,
 628                             HW_ATL_RPB_RXBBUF_SIZE_SHIFT,
 629                             rx_pkt_buff_size_per_tc);
 630 }
 631
 632 void hw_atl_rpb_rx_xoff_en_per_tc_set(struct aq_hw_s *aq_hw,
 633                                       u32 rx_xoff_en_per_tc,
 634                                       u32 buffer)
 635 {
 636         aq_hw_write_reg_bit(aq_hw, HW_ATL_RPB_RXBXOFF_EN_ADR(buffer),
 637                             HW_ATL_RPB_RXBXOFF_EN_MSK,
 638                             HW_ATL_RPB_RXBXOFF_EN_SHIFT,
 639                             rx_xoff_en_per_tc);
 640 }
 641
 642 /* rpf */
 643
 644 void hw_atl_rpfl2broadcast_count_threshold_set(struct aq_hw_s *aq_hw,
 645                                                u32 l2broadcast_count_threshold)
 646 {
 647         aq_hw_write_reg_bit(aq_hw, HW_ATL_RPFL2BC_THRESH_ADR,
 648                             HW_ATL_RPFL2BC_THRESH_MSK,
 649                             HW_ATL_RPFL2BC_THRESH_SHIFT,
 650                             l2broadcast_count_threshold);
 651 }
 652
 653 void hw_atl_rpfl2broadcast_en_set(struct aq_hw_s *aq_hw, u32 l2broadcast_en)
 654 {
 655         aq_hw_write_reg_bit(aq_hw, HW_ATL_RPFL2BC_EN_ADR, HW_ATL_RPFL2BC_EN_MSK,
 656                             HW_ATL_RPFL2BC_EN_SHIFT, l2broadcast_en);
 657 }
 658
 659 void hw_atl_rpfl2broadcast_flr_act_set(struct aq_hw_s *aq_hw,
 660                                        u32 l2broadcast_flr_act)
 661 {
 662         aq_hw_write_reg_bit(aq_hw, HW_ATL_RPFL2BC_ACT_ADR,
 663                             HW_ATL_RPFL2BC_ACT_MSK,
 664                             HW_ATL_RPFL2BC_ACT_SHIFT, l2broadcast_flr_act);
 665 }
 666
 667 void hw_atl_rpfl2multicast_flr_en_set(struct aq_hw_s *aq_hw,
 668                                       u32 l2multicast_flr_en,
 669                                       u32 filter)
 670 {
 671         aq_hw_write_reg_bit(aq_hw, HW_ATL_RPFL2MC_ENF_ADR(filter),
 672                             HW_ATL_RPFL2MC_ENF_MSK,
 673                             HW_ATL_RPFL2MC_ENF_SHIFT, l2multicast_flr_en);
 674 }
 675
 676 void hw_atl_rpfl2promiscuous_mode_en_set(struct aq_hw_s *aq_hw,
 677                                          u32 l2promiscuous_mode_en)
 678 {
 679         aq_hw_write_reg_bit(aq_hw, HW_ATL_RPFL2PROMIS_MODE_ADR,
 680                             HW_ATL_RPFL2PROMIS_MODE_MSK,
 681                             HW_ATL_RPFL2PROMIS_MODE_SHIFT,
 682                             l2promiscuous_mode_en);
 683 }
 684
 685 void hw_atl_rpfl2unicast_flr_act_set(struct aq_hw_s *aq_hw,
 686                                      u32 l2unicast_flr_act,
 687                                      u32 filter)
 688 {
 689         aq_hw_write_reg_bit(aq_hw, HW_ATL_RPFL2UC_ACTF_ADR(filter),
 690                             HW_ATL_RPFL2UC_ACTF_MSK, HW_ATL_RPFL2UC_ACTF_SHIFT,
 691                             l2unicast_flr_act);
 692 }
 693
 694 void hw_atl_rpfl2_uc_flr_en_set(struct aq_hw_s *aq_hw, u32 l2unicast_flr_en,
 695                                 u32 filter)
 696 {
 697         aq_hw_write_reg_bit(aq_hw, HW_ATL_RPFL2UC_ENF_ADR(filter),
 698                             HW_ATL_RPFL2UC_ENF_MSK,
 699                             HW_ATL_RPFL2UC_ENF_SHIFT, l2unicast_flr_en);
 700 }
 701
 702 void hw_atl_rpfl2unicast_dest_addresslsw_set(struct aq_hw_s *aq_hw,
 703                                              u32 l2unicast_dest_addresslsw,
 704                                              u32 filter)
 705 {
 706         aq_hw_write_reg(aq_hw, HW_ATL_RPFL2UC_DAFLSW_ADR(filter),
 707                         l2unicast_dest_addresslsw);
 708 }
 709
 710 void hw_atl_rpfl2unicast_dest_addressmsw_set(struct aq_hw_s *aq_hw,
 711                                              u32 l2unicast_dest_addressmsw,
 712                                              u32 filter)
 713 {
 714         aq_hw_write_reg_bit(aq_hw, HW_ATL_RPFL2UC_DAFMSW_ADR(filter),
 715                             HW_ATL_RPFL2UC_DAFMSW_MSK,
 716                             HW_ATL_RPFL2UC_DAFMSW_SHIFT,
 717                             l2unicast_dest_addressmsw);
 718 }
 719
 720 void hw_atl_rpfl2_accept_all_mc_packets_set(struct aq_hw_s *aq_hw,
 721                                             u32 l2_accept_all_mc_packets)
 722 {
 723         aq_hw_write_reg_bit(aq_hw, HW_ATL_RPFL2MC_ACCEPT_ALL_ADR,
 724                             HW_ATL_RPFL2MC_ACCEPT_ALL_MSK,
 725                             HW_ATL_RPFL2MC_ACCEPT_ALL_SHIFT,
 726                             l2_accept_all_mc_packets);
 727 }
 728
 729 void hw_atl_rpf_rpb_user_priority_tc_map_set(struct aq_hw_s *aq_hw,
 730                                              u32 user_priority_tc_map, u32 tc)
 731 {
 732 /* register address for bitfield rx_tc_up{t}[2:0] */
 733         static const u32 rpf_rpb_rx_tc_upt_adr[8] = {
 734                         0x000054c4U, 0x000054C4U, 0x000054C4U, 0x000054C4U,
 735                         0x000054c4U, 0x000054C4U, 0x000054C4U, 0x000054C4U
 736                 };
 737
 738 /* bitmask for bitfield rx_tc_up{t}[2:0] */
 739         static const u32 rpf_rpb_rx_tc_upt_msk[8] = {
 740                         0x00000007U, 0x00000070U, 0x00000700U, 0x00007000U,
 741                         0x00070000U, 0x00700000U, 0x07000000U, 0x70000000U
 742                 };
 743
 744 /* lower bit position of bitfield rx_tc_up{t}[2:0] */
 745         static const u32 rpf_rpb_rx_tc_upt_shft[8] = {
 746                         0U, 4U, 8U, 12U, 16U, 20U, 24U, 28U
 747                 };
 748
 749         aq_hw_write_reg_bit(aq_hw, rpf_rpb_rx_tc_upt_adr[tc],
 750                             rpf_rpb_rx_tc_upt_msk[tc],
 751                             rpf_rpb_rx_tc_upt_shft[tc],
 752                             user_priority_tc_map);
 753 }
 754
 755 void hw_atl_rpf_rss_key_addr_set(struct aq_hw_s *aq_hw, u32 rss_key_addr)
 756 {
 757         aq_hw_write_reg_bit(aq_hw, HW_ATL_RPF_RSS_KEY_ADDR_ADR,
 758                             HW_ATL_RPF_RSS_KEY_ADDR_MSK,
 759                             HW_ATL_RPF_RSS_KEY_ADDR_SHIFT,
 760                             rss_key_addr);
 761 }
 762
 763 void hw_atl_rpf_rss_key_wr_data_set(struct aq_hw_s *aq_hw, u32 rss_key_wr_data)
 764 {
 765         aq_hw_write_reg(aq_hw, HW_ATL_RPF_RSS_KEY_WR_DATA_ADR,
 766                         rss_key_wr_data);
 767 }
 768
 769 u32 hw_atl_rpf_rss_key_wr_en_get(struct aq_hw_s *aq_hw)
 770 {
 771         return aq_hw_read_reg_bit(aq_hw, HW_ATL_RPF_RSS_KEY_WR_ENI_ADR,
 772                                   HW_ATL_RPF_RSS_KEY_WR_ENI_MSK,
 773                                   HW_ATL_RPF_RSS_KEY_WR_ENI_SHIFT);
 774 }
 775
 776 void hw_atl_rpf_rss_key_wr_en_set(struct aq_hw_s *aq_hw, u32 rss_key_wr_en)
 777 {
 778         aq_hw_write_reg_bit(aq_hw, HW_ATL_RPF_RSS_KEY_WR_ENI_ADR,
 779                             HW_ATL_RPF_RSS_KEY_WR_ENI_MSK,
 780                             HW_ATL_RPF_RSS_KEY_WR_ENI_SHIFT,
 781                             rss_key_wr_en);
 782 }
 783
 784 void hw_atl_rpf_rss_redir_tbl_addr_set(struct aq_hw_s *aq_hw,
 785                                        u32 rss_redir_tbl_addr)
 786 {
 787         aq_hw_write_reg_bit(aq_hw, HW_ATL_RPF_RSS_REDIR_ADDR_ADR,
 788                             HW_ATL_RPF_RSS_REDIR_ADDR_MSK,
 789                             HW_ATL_RPF_RSS_REDIR_ADDR_SHIFT,
 790                             rss_redir_tbl_addr);
 791 }
 792
 793 void hw_atl_rpf_rss_redir_tbl_wr_data_set(struct aq_hw_s *aq_hw,
 794                                           u32 rss_redir_tbl_wr_data)
 795 {
 796         aq_hw_write_reg_bit(aq_hw, HW_ATL_RPF_RSS_REDIR_WR_DATA_ADR,
 797                             HW_ATL_RPF_RSS_REDIR_WR_DATA_MSK,
 798                             HW_ATL_RPF_RSS_REDIR_WR_DATA_SHIFT,
 799                             rss_redir_tbl_wr_data);
 800 }
 801
 802 u32 hw_atl_rpf_rss_redir_wr_en_get(struct aq_hw_s *aq_hw)
 803 {
 804         return aq_hw_read_reg_bit(aq_hw, HW_ATL_RPF_RSS_REDIR_WR_ENI_ADR,
 805                                   HW_ATL_RPF_RSS_REDIR_WR_ENI_MSK,
 806                                   HW_ATL_RPF_RSS_REDIR_WR_ENI_SHIFT);
 807 }
 808
 809 void hw_atl_rpf_rss_redir_wr_en_set(struct aq_hw_s *aq_hw, u32 rss_redir_wr_en)
 810 {
 811         aq_hw_write_reg_bit(aq_hw, HW_ATL_RPF_RSS_REDIR_WR_ENI_ADR,
 812                             HW_ATL_RPF_RSS_REDIR_WR_ENI_MSK,
 813                             HW_ATL_RPF_RSS_REDIR_WR_ENI_SHIFT, rss_redir_wr_en);
 814 }
 815
 816 void hw_atl_rpf_tpo_to_rpf_sys_lbk_set(struct aq_hw_s *aq_hw,
 817                                        u32 tpo_to_rpf_sys_lbk)
 818 {
 819         aq_hw_write_reg_bit(aq_hw, HW_ATL_RPF_TPO_RPF_SYS_LBK_ADR,
 820                             HW_ATL_RPF_TPO_RPF_SYS_LBK_MSK,
 821                             HW_ATL_RPF_TPO_RPF_SYS_LBK_SHIFT,
 822                             tpo_to_rpf_sys_lbk);
 823 }
 824
 825 void hw_atl_rpf_vlan_inner_etht_set(struct aq_hw_s *aq_hw, u32 vlan_inner_etht)
 826 {
 827         aq_hw_write_reg_bit(aq_hw, HW_ATL_RPF_VL_INNER_TPID_ADR,
 828                             HW_ATL_RPF_VL_INNER_TPID_MSK,
 829                             HW_ATL_RPF_VL_INNER_TPID_SHIFT,
 830                             vlan_inner_etht);
 831 }
 832
 833 void hw_atl_rpf_vlan_outer_etht_set(struct aq_hw_s *aq_hw, u32 vlan_outer_etht)
 834 {
 835         aq_hw_write_reg_bit(aq_hw, HW_ATL_RPF_VL_OUTER_TPID_ADR,
 836                             HW_ATL_RPF_VL_OUTER_TPID_MSK,
 837                             HW_ATL_RPF_VL_OUTER_TPID_SHIFT,
 838                             vlan_outer_etht);
 839 }
 840
 841 void hw_atl_rpf_vlan_prom_mode_en_set(struct aq_hw_s *aq_hw,
 842                                       u32 vlan_prom_mode_en)
 843 {
 844         aq_hw_write_reg_bit(aq_hw, HW_ATL_RPF_VL_PROMIS_MODE_ADR,
 845                             HW_ATL_RPF_VL_PROMIS_MODE_MSK,
 846                             HW_ATL_RPF_VL_PROMIS_MODE_SHIFT,
 847                             vlan_prom_mode_en);
 848 }
 849
 850 void hw_atl_rpf_vlan_accept_untagged_packets_set(struct aq_hw_s *aq_hw,
 851                                                  u32 vlan_acc_untagged_packets)
 852 {
 853         aq_hw_write_reg_bit(aq_hw, HW_ATL_RPF_VL_ACCEPT_UNTAGGED_MODE_ADR,
 854                             HW_ATL_RPF_VL_ACCEPT_UNTAGGED_MODE_MSK,
 855                             HW_ATL_RPF_VL_ACCEPT_UNTAGGED_MODE_SHIFT,
 856                             vlan_acc_untagged_packets);
 857 }
 858
 859 void hw_atl_rpf_vlan_untagged_act_set(struct aq_hw_s *aq_hw,
 860                                       u32 vlan_untagged_act)
 861 {
 862         aq_hw_write_reg_bit(aq_hw, HW_ATL_RPF_VL_UNTAGGED_ACT_ADR,
 863                             HW_ATL_RPF_VL_UNTAGGED_ACT_MSK,
 864                             HW_ATL_RPF_VL_UNTAGGED_ACT_SHIFT,
 865                             vlan_untagged_act);
 866 }
 867
 868 void hw_atl_rpf_vlan_flr_en_set(struct aq_hw_s *aq_hw, u32 vlan_flr_en,
 869                                 u32 filter)
 870 {
 871         aq_hw_write_reg_bit(aq_hw, HW_ATL_RPF_VL_EN_F_ADR(filter),
 872                             HW_ATL_RPF_VL_EN_F_MSK,
 873                             HW_ATL_RPF_VL_EN_F_SHIFT,
 874                             vlan_flr_en);
 875 }
 876
 877 void hw_atl_rpf_vlan_flr_act_set(struct aq_hw_s *aq_hw, u32 vlan_flr_act,
 878                                  u32 filter)
 879 {
 880         aq_hw_write_reg_bit(aq_hw, HW_ATL_RPF_VL_ACT_F_ADR(filter),
 881                             HW_ATL_RPF_VL_ACT_F_MSK,
 882                             HW_ATL_RPF_VL_ACT_F_SHIFT,
 883                             vlan_flr_act);
 884 }
 885
 886 void hw_atl_rpf_vlan_id_flr_set(struct aq_hw_s *aq_hw, u32 vlan_id_flr,
 887                                 u32 filter)
 888 {
 889         aq_hw_write_reg_bit(aq_hw, HW_ATL_RPF_VL_ID_F_ADR(filter),
 890                             HW_ATL_RPF_VL_ID_F_MSK,
 891                             HW_ATL_RPF_VL_ID_F_SHIFT,
 892                             vlan_id_flr);
 893 }
 894
 895 void hw_atl_rpf_etht_flr_en_set(struct aq_hw_s *aq_hw, u32 etht_flr_en,
 896                                 u32 filter)
 897 {
 898         aq_hw_write_reg_bit(aq_hw, HW_ATL_RPF_ET_ENF_ADR(filter),
 899                             HW_ATL_RPF_ET_ENF_MSK,
 900                             HW_ATL_RPF_ET_ENF_SHIFT, etht_flr_en);
 901 }
 902
 903 void hw_atl_rpf_etht_user_priority_en_set(struct aq_hw_s *aq_hw,
 904                                           u32 etht_user_priority_en, u32 filter)
 905 {
 906         aq_hw_write_reg_bit(aq_hw, HW_ATL_RPF_ET_UPFEN_ADR(filter),
 907                             HW_ATL_RPF_ET_UPFEN_MSK, HW_ATL_RPF_ET_UPFEN_SHIFT,
 908                             etht_user_priority_en);
 909 }
 910
 911 void hw_atl_rpf_etht_rx_queue_en_set(struct aq_hw_s *aq_hw,
 912                                      u32 etht_rx_queue_en,
 913                                      u32 filter)
 914 {
 915         aq_hw_write_reg_bit(aq_hw, HW_ATL_RPF_ET_RXQFEN_ADR(filter),
 916                             HW_ATL_RPF_ET_RXQFEN_MSK,
 917                             HW_ATL_RPF_ET_RXQFEN_SHIFT,
 918                             etht_rx_queue_en);
 919 }
 920
 921 void hw_atl_rpf_etht_user_priority_set(struct aq_hw_s *aq_hw,
 922                                        u32 etht_user_priority,
 923                                        u32 filter)
 924 {
 925         aq_hw_write_reg_bit(aq_hw, HW_ATL_RPF_ET_UPF_ADR(filter),
 926                             HW_ATL_RPF_ET_UPF_MSK,
 927                             HW_ATL_RPF_ET_UPF_SHIFT, etht_user_priority);
 928 }
 929
 930 void hw_atl_rpf_etht_rx_queue_set(struct aq_hw_s *aq_hw, u32 etht_rx_queue,
 931                                   u32 filter)
 932 {
 933         aq_hw_write_reg_bit(aq_hw, HW_ATL_RPF_ET_RXQF_ADR(filter),
 934                             HW_ATL_RPF_ET_RXQF_MSK,
 935                             HW_ATL_RPF_ET_RXQF_SHIFT, etht_rx_queue);
 936 }
 937
 938 void hw_atl_rpf_etht_mgt_queue_set(struct aq_hw_s *aq_hw, u32 etht_mgt_queue,
 939                                    u32 filter)
 940 {
 941         aq_hw_write_reg_bit(aq_hw, HW_ATL_RPF_ET_MNG_RXQF_ADR(filter),
 942                             HW_ATL_RPF_ET_MNG_RXQF_MSK,
 943                             HW_ATL_RPF_ET_MNG_RXQF_SHIFT,
 944                             etht_mgt_queue);
 945 }
 946
 947 void hw_atl_rpf_etht_flr_act_set(struct aq_hw_s *aq_hw, u32 etht_flr_act,
 948                                  u32 filter)
 949 {
 950         aq_hw_write_reg_bit(aq_hw, HW_ATL_RPF_ET_ACTF_ADR(filter),
 951                             HW_ATL_RPF_ET_ACTF_MSK,
 952                             HW_ATL_RPF_ET_ACTF_SHIFT, etht_flr_act);
 953 }
 954
 955 void hw_atl_rpf_etht_flr_set(struct aq_hw_s *aq_hw, u32 etht_flr, u32 filter)
 956 {
 957         aq_hw_write_reg_bit(aq_hw, HW_ATL_RPF_ET_VALF_ADR(filter),
 958                             HW_ATL_RPF_ET_VALF_MSK,
 959                             HW_ATL_RPF_ET_VALF_SHIFT, etht_flr);
 960 }
 961
 962 /* RPO: rx packet offload */
 963 void hw_atl_rpo_ipv4header_crc_offload_en_set(struct aq_hw_s *aq_hw,
 964                                               u32 ipv4header_crc_offload_en)
 965 {
 966         aq_hw_write_reg_bit(aq_hw, HW_ATL_RPO_IPV4CHK_EN_ADR,
 967                             HW_ATL_RPO_IPV4CHK_EN_MSK,
 968                             HW_ATL_RPO_IPV4CHK_EN_SHIFT,
 969                             ipv4header_crc_offload_en);
 970 }
 971
 972 void hw_atl_rpo_rx_desc_vlan_stripping_set(struct aq_hw_s *aq_hw,
 973                                            u32 rx_desc_vlan_stripping,
 974                                            u32 descriptor)
 975 {
 976         aq_hw_write_reg_bit(aq_hw, HW_ATL_RPO_DESCDVL_STRIP_ADR(descriptor),
 977                             HW_ATL_RPO_DESCDVL_STRIP_MSK,
 978                             HW_ATL_RPO_DESCDVL_STRIP_SHIFT,
 979                             rx_desc_vlan_stripping);
 980 }
 981
 982 void hw_atl_rpo_tcp_udp_crc_offload_en_set(struct aq_hw_s *aq_hw,
 983                                            u32 tcp_udp_crc_offload_en)
 984 {
 985         aq_hw_write_reg_bit(aq_hw, HW_ATL_RPOL4CHK_EN_ADR,
 986                             HW_ATL_RPOL4CHK_EN_MSK,
 987                             HW_ATL_RPOL4CHK_EN_SHIFT, tcp_udp_crc_offload_en);
 988 }
 989
 990 void hw_atl_rpo_lro_en_set(struct aq_hw_s *aq_hw, u32 lro_en)
 991 {
 992         aq_hw_write_reg(aq_hw, HW_ATL_RPO_LRO_EN_ADR, lro_en);
 993 }
 994
 995 void hw_atl_rpo_lro_patch_optimization_en_set(struct aq_hw_s *aq_hw,
 996                                               u32 lro_patch_optimization_en)
 997 {
 998         aq_hw_write_reg_bit(aq_hw, HW_ATL_RPO_LRO_PTOPT_EN_ADR,
 999                             HW_ATL_RPO_LRO_PTOPT_EN_MSK,
1000                             HW_ATL_RPO_LRO_PTOPT_EN_SHIFT,
1001                             lro_patch_optimization_en);
1002 }
1003
1004 void hw_atl_rpo_lro_qsessions_lim_set(struct aq_hw_s *aq_hw,
1005                                       u32 lro_qsessions_lim)
1006 {
1007         aq_hw_write_reg_bit(aq_hw, HW_ATL_RPO_LRO_QSES_LMT_ADR,
1008                             HW_ATL_RPO_LRO_QSES_LMT_MSK,
1009                             HW_ATL_RPO_LRO_QSES_LMT_SHIFT,
1010                             lro_qsessions_lim);
1011 }
1012
1013 void hw_atl_rpo_lro_total_desc_lim_set(struct aq_hw_s *aq_hw,
1014                                        u32 lro_total_desc_lim)
1015 {
1016         aq_hw_write_reg_bit(aq_hw, HW_ATL_RPO_LRO_TOT_DSC_LMT_ADR,
1017                             HW_ATL_RPO_LRO_TOT_DSC_LMT_MSK,
1018                             HW_ATL_RPO_LRO_TOT_DSC_LMT_SHIFT,
1019                             lro_total_desc_lim);
1020 }
1021
1022 void hw_atl_rpo_lro_min_pay_of_first_pkt_set(struct aq_hw_s *aq_hw,
1023                                              u32 lro_min_pld_of_first_pkt)
1024 {
1025         aq_hw_write_reg_bit(aq_hw, HW_ATL_RPO_LRO_PKT_MIN_ADR,
1026                             HW_ATL_RPO_LRO_PKT_MIN_MSK,
1027                             HW_ATL_RPO_LRO_PKT_MIN_SHIFT,
1028                             lro_min_pld_of_first_pkt);
1029 }
1030
1031 void hw_atl_rpo_lro_pkt_lim_set(struct aq_hw_s *aq_hw, u32 lro_pkt_lim)
1032 {
1033         aq_hw_write_reg(aq_hw, HW_ATL_RPO_LRO_RSC_MAX_ADR, lro_pkt_lim);
1034 }
1035
1036 void hw_atl_rpo_lro_max_num_of_descriptors_set(struct aq_hw_s *aq_hw,
1037                                         u32 lro_max_number_of_descriptors,
1038                                         u32 lro)
1039 {
1040 /* Register address for bitfield lro{L}_des_max[1:0] */
1041         static const u32 rpo_lro_ldes_max_adr[32] = {
1042                         0x000055A0U, 0x000055A0U, 0x000055A0U, 0x000055A0U,
1043                         0x000055A0U, 0x000055A0U, 0x000055A0U, 0x000055A0U,
1044                         0x000055A4U, 0x000055A4U, 0x000055A4U, 0x000055A4U,
1045                         0x000055A4U, 0x000055A4U, 0x000055A4U, 0x000055A4U,
1046                         0x000055A8U, 0x000055A8U, 0x000055A8U, 0x000055A8U,
1047                         0x000055A8U, 0x000055A8U, 0x000055A8U, 0x000055A8U,
1048                         0x000055ACU, 0x000055ACU, 0x000055ACU, 0x000055ACU,
1049                         0x000055ACU, 0x000055ACU, 0x000055ACU, 0x000055ACU
1050                 };
1051
1052 /* Bitmask for bitfield lro{L}_des_max[1:0] */
1053         static const u32 rpo_lro_ldes_max_msk[32] = {
1054                         0x00000003U, 0x00000030U, 0x00000300U, 0x00003000U,
1055                         0x00030000U, 0x00300000U, 0x03000000U, 0x30000000U,
1056                         0x00000003U, 0x00000030U, 0x00000300U, 0x00003000U,
1057                         0x00030000U, 0x00300000U, 0x03000000U, 0x30000000U,
1058                         0x00000003U, 0x00000030U, 0x00000300U, 0x00003000U,
1059                         0x00030000U, 0x00300000U, 0x03000000U, 0x30000000U,
1060                         0x00000003U, 0x00000030U, 0x00000300U, 0x00003000U,
1061                         0x00030000U, 0x00300000U, 0x03000000U, 0x30000000U
1062                 };
1063
1064 /* Lower bit position of bitfield lro{L}_des_max[1:0] */
1065         static const u32 rpo_lro_ldes_max_shift[32] = {
1066                         0U, 4U, 8U, 12U, 16U, 20U, 24U, 28U,
1067                         0U, 4U, 8U, 12U, 16U, 20U, 24U, 28U,
1068                         0U, 4U, 8U, 12U, 16U, 20U, 24U, 28U,
1069                         0U, 4U, 8U, 12U, 16U, 20U, 24U, 28U
1070                 };
1071
1072         aq_hw_write_reg_bit(aq_hw, rpo_lro_ldes_max_adr[lro],
1073                             rpo_lro_ldes_max_msk[lro],
1074                             rpo_lro_ldes_max_shift[lro],
1075                             lro_max_number_of_descriptors);
1076 }
1077
1078 void hw_atl_rpo_lro_time_base_divider_set(struct aq_hw_s *aq_hw,
1079                                           u32 lro_time_base_divider)
1080 {
1081         aq_hw_write_reg_bit(aq_hw, HW_ATL_RPO_LRO_TB_DIV_ADR,
1082                             HW_ATL_RPO_LRO_TB_DIV_MSK,
1083                             HW_ATL_RPO_LRO_TB_DIV_SHIFT,
1084                             lro_time_base_divider);
1085 }
1086
1087 void hw_atl_rpo_lro_inactive_interval_set(struct aq_hw_s *aq_hw,
1088                                           u32 lro_inactive_interval)
1089 {
1090         aq_hw_write_reg_bit(aq_hw, HW_ATL_RPO_LRO_INA_IVAL_ADR,
1091                             HW_ATL_RPO_LRO_INA_IVAL_MSK,
1092                             HW_ATL_RPO_LRO_INA_IVAL_SHIFT,
1093                             lro_inactive_interval);
1094 }
1095
1096 void hw_atl_rpo_lro_max_coalescing_interval_set(struct aq_hw_s *aq_hw,
1097                                                 u32 lro_max_coal_interval)
1098 {
1099         aq_hw_write_reg_bit(aq_hw, HW_ATL_RPO_LRO_MAX_IVAL_ADR,
1100                             HW_ATL_RPO_LRO_MAX_IVAL_MSK,
1101                             HW_ATL_RPO_LRO_MAX_IVAL_SHIFT,
1102                             lro_max_coal_interval);
1103 }
1104
1105 /* rx */
1106 void hw_atl_rx_rx_reg_res_dis_set(struct aq_hw_s *aq_hw, u32 rx_reg_res_dis)
1107 {
1108         aq_hw_write_reg_bit(aq_hw, HW_ATL_RX_REG_RES_DSBL_ADR,
1109                             HW_ATL_RX_REG_RES_DSBL_MSK,
1110                             HW_ATL_RX_REG_RES_DSBL_SHIFT,
1111                             rx_reg_res_dis);
1112 }
1113
1114 /* tdm */
1115 void hw_atl_tdm_cpu_id_set(struct aq_hw_s *aq_hw, u32 cpuid, u32 dca)
1116 {
1117         aq_hw_write_reg_bit(aq_hw, HW_ATL_TDM_DCADCPUID_ADR(dca),
1118                             HW_ATL_TDM_DCADCPUID_MSK,
1119                             HW_ATL_TDM_DCADCPUID_SHIFT, cpuid);
1120 }
1121
1122 void hw_atl_tdm_large_send_offload_en_set(struct aq_hw_s *aq_hw,
1123                                           u32 large_send_offload_en)
1124 {
1125         aq_hw_write_reg(aq_hw, HW_ATL_TDM_LSO_EN_ADR, large_send_offload_en);
1126 }
1127
1128 void hw_atl_tdm_tx_dca_en_set(struct aq_hw_s *aq_hw, u32 tx_dca_en)
1129 {
1130         aq_hw_write_reg_bit(aq_hw, HW_ATL_TDM_DCA_EN_ADR, HW_ATL_TDM_DCA_EN_MSK,
1131                             HW_ATL_TDM_DCA_EN_SHIFT, tx_dca_en);
1132 }
1133
1134 void hw_atl_tdm_tx_dca_mode_set(struct aq_hw_s *aq_hw, u32 tx_dca_mode)
1135 {
1136         aq_hw_write_reg_bit(aq_hw, HW_ATL_TDM_DCA_MODE_ADR,
1137                             HW_ATL_TDM_DCA_MODE_MSK,
1138                             HW_ATL_TDM_DCA_MODE_SHIFT, tx_dca_mode);
1139 }
1140
1141 void hw_atl_tdm_tx_desc_dca_en_set(struct aq_hw_s *aq_hw, u32 tx_desc_dca_en,
1142                                    u32 dca)
1143 {
1144         aq_hw_write_reg_bit(aq_hw, HW_ATL_TDM_DCADDESC_EN_ADR(dca),
1145                             HW_ATL_TDM_DCADDESC_EN_MSK,
1146                             HW_ATL_TDM_DCADDESC_EN_SHIFT,
1147                             tx_desc_dca_en);
1148 }
1149
1150 void hw_atl_tdm_tx_desc_en_set(struct aq_hw_s *aq_hw, u32 tx_desc_en,
1151                                u32 descriptor)
1152 {
1153         aq_hw_write_reg_bit(aq_hw, HW_ATL_TDM_DESCDEN_ADR(descriptor),
1154                             HW_ATL_TDM_DESCDEN_MSK,
1155                             HW_ATL_TDM_DESCDEN_SHIFT,
1156                             tx_desc_en);
1157 }
1158
1159 u32 hw_atl_tdm_tx_desc_head_ptr_get(struct aq_hw_s *aq_hw, u32 descriptor)
1160 {
1161         return aq_hw_read_reg_bit(aq_hw, HW_ATL_TDM_DESCDHD_ADR(descriptor),
1162                                   HW_ATL_TDM_DESCDHD_MSK,
1163                                   HW_ATL_TDM_DESCDHD_SHIFT);
1164 }
1165
1166 void hw_atl_tdm_tx_desc_len_set(struct aq_hw_s *aq_hw, u32 tx_desc_len,
1167                                 u32 descriptor)
1168 {
1169         aq_hw_write_reg_bit(aq_hw, HW_ATL_TDM_DESCDLEN_ADR(descriptor),
1170                             HW_ATL_TDM_DESCDLEN_MSK,
1171                             HW_ATL_TDM_DESCDLEN_SHIFT,
1172                             tx_desc_len);
1173 }
1174
1175 void hw_atl_tdm_tx_desc_wr_wb_irq_en_set(struct aq_hw_s *aq_hw,
1176                                          u32 tx_desc_wr_wb_irq_en)
1177 {
1178         aq_hw_write_reg_bit(aq_hw, HW_ATL_TDM_INT_DESC_WRB_EN_ADR,
1179                             HW_ATL_TDM_INT_DESC_WRB_EN_MSK,
1180                             HW_ATL_TDM_INT_DESC_WRB_EN_SHIFT,
1181                             tx_desc_wr_wb_irq_en);
1182 }
1183
1184 void hw_atl_tdm_tx_desc_wr_wb_threshold_set(struct aq_hw_s *aq_hw,
1185                                             u32 tx_desc_wr_wb_threshold,
1186                                             u32 descriptor)
1187 {
1188         aq_hw_write_reg_bit(aq_hw, HW_ATL_TDM_DESCDWRB_THRESH_ADR(descriptor),
1189                             HW_ATL_TDM_DESCDWRB_THRESH_MSK,
1190                             HW_ATL_TDM_DESCDWRB_THRESH_SHIFT,
1191                             tx_desc_wr_wb_threshold);
1192 }
1193
1194 void hw_atl_tdm_tdm_intr_moder_en_set(struct aq_hw_s *aq_hw,
1195                                       u32 tdm_irq_moderation_en)
1196 {
1197         aq_hw_write_reg_bit(aq_hw, HW_ATL_TDM_INT_MOD_EN_ADR,
1198                             HW_ATL_TDM_INT_MOD_EN_MSK,
1199                             HW_ATL_TDM_INT_MOD_EN_SHIFT,
1200                             tdm_irq_moderation_en);
1201 }
1202
1203 /* thm */
1204 void hw_atl_thm_lso_tcp_flag_of_first_pkt_set(struct aq_hw_s *aq_hw,
1205                                               u32 lso_tcp_flag_of_first_pkt)
1206 {
1207         aq_hw_write_reg_bit(aq_hw, HW_ATL_THM_LSO_TCP_FLAG_FIRST_ADR,
1208                             HW_ATL_THM_LSO_TCP_FLAG_FIRST_MSK,
1209                             HW_ATL_THM_LSO_TCP_FLAG_FIRST_SHIFT,
1210                             lso_tcp_flag_of_first_pkt);
1211 }
1212
1213 void hw_atl_thm_lso_tcp_flag_of_last_pkt_set(struct aq_hw_s *aq_hw,
1214                                              u32 lso_tcp_flag_of_last_pkt)
1215 {
1216         aq_hw_write_reg_bit(aq_hw, HW_ATL_THM_LSO_TCP_FLAG_LAST_ADR,
1217                             HW_ATL_THM_LSO_TCP_FLAG_LAST_MSK,
1218                             HW_ATL_THM_LSO_TCP_FLAG_LAST_SHIFT,
1219                             lso_tcp_flag_of_last_pkt);
1220 }
1221
1222 void hw_atl_thm_lso_tcp_flag_of_middle_pkt_set(struct aq_hw_s *aq_hw,
1223                                                u32 lso_tcp_flag_of_middle_pkt)
1224 {
1225         aq_hw_write_reg_bit(aq_hw, HW_ATL_THM_LSO_TCP_FLAG_MID_ADR,
1226                             HW_ATL_THM_LSO_TCP_FLAG_MID_MSK,
1227                             HW_ATL_THM_LSO_TCP_FLAG_MID_SHIFT,
1228                             lso_tcp_flag_of_middle_pkt);
1229 }
1230
1231 /* TPB: tx packet buffer */
1232 void hw_atl_tpb_tx_buff_en_set(struct aq_hw_s *aq_hw, u32 tx_buff_en)
1233 {
1234         aq_hw_write_reg_bit(aq_hw, HW_ATL_TPB_TX_BUF_EN_ADR,
1235                             HW_ATL_TPB_TX_BUF_EN_MSK,
1236                             HW_ATL_TPB_TX_BUF_EN_SHIFT, tx_buff_en);
1237 }
1238
1239 u32 hw_atl_rpb_tps_tx_tc_mode_get(struct aq_hw_s *aq_hw)
1240 {
1241         return aq_hw_read_reg_bit(aq_hw, HW_ATL_TPB_TX_TC_MODE_ADDR,
1242                         HW_ATL_TPB_TX_TC_MODE_MSK,
1243                         HW_ATL_TPB_TX_TC_MODE_SHIFT);
1244 }
1245
1246 void hw_atl_rpb_tps_tx_tc_mode_set(struct aq_hw_s *aq_hw,
1247                                    u32 tx_traf_class_mode)
1248 {
1249         aq_hw_write_reg_bit(aq_hw, HW_ATL_TPB_TX_TC_MODE_ADDR,
1250                         HW_ATL_TPB_TX_TC_MODE_MSK,
1251                         HW_ATL_TPB_TX_TC_MODE_SHIFT,
1252                         tx_traf_class_mode);
1253 }
1254
1255 void hw_atl_tpb_tx_buff_hi_threshold_per_tc_set(struct aq_hw_s *aq_hw,
1256                                                 u32 tx_buff_hi_threshold_per_tc,
1257                                          u32 buffer)
1258 {
1259         aq_hw_write_reg_bit(aq_hw, HW_ATL_TPB_TXBHI_THRESH_ADR(buffer),
1260                             HW_ATL_TPB_TXBHI_THRESH_MSK,
1261                             HW_ATL_TPB_TXBHI_THRESH_SHIFT,
1262                             tx_buff_hi_threshold_per_tc);
1263 }
1264
1265 void hw_atl_tpb_tx_buff_lo_threshold_per_tc_set(struct aq_hw_s *aq_hw,
1266                                                 u32 tx_buff_lo_threshold_per_tc,
1267                                                 u32 buffer)
1268 {
1269         aq_hw_write_reg_bit(aq_hw, HW_ATL_TPB_TXBLO_THRESH_ADR(buffer),
1270                             HW_ATL_TPB_TXBLO_THRESH_MSK,
1271                             HW_ATL_TPB_TXBLO_THRESH_SHIFT,
1272                             tx_buff_lo_threshold_per_tc);
1273 }
1274
1275 void hw_atl_tpb_tx_dma_sys_lbk_en_set(struct aq_hw_s *aq_hw,
1276                                       u32 tx_dma_sys_lbk_en)
1277 {
1278         aq_hw_write_reg_bit(aq_hw, HW_ATL_TPB_DMA_SYS_LBK_ADR,
1279                             HW_ATL_TPB_DMA_SYS_LBK_MSK,
1280                             HW_ATL_TPB_DMA_SYS_LBK_SHIFT,
1281                             tx_dma_sys_lbk_en);
1282 }
1283
1284 void hw_atl_tpb_tx_pkt_buff_size_per_tc_set(struct aq_hw_s *aq_hw,
1285                                             u32 tx_pkt_buff_size_per_tc,
1286                                             u32 buffer)
1287 {
1288         aq_hw_write_reg_bit(aq_hw, HW_ATL_TPB_TXBBUF_SIZE_ADR(buffer),
1289                             HW_ATL_TPB_TXBBUF_SIZE_MSK,
1290                             HW_ATL_TPB_TXBBUF_SIZE_SHIFT,
1291                             tx_pkt_buff_size_per_tc);
1292 }
1293
1294 void hw_atl_tpb_tx_path_scp_ins_en_set(struct aq_hw_s *aq_hw,
1295                                        u32 tx_path_scp_ins_en)
1296 {
1297         aq_hw_write_reg_bit(aq_hw, HW_ATL_TPB_TX_SCP_INS_EN_ADR,
1298                             HW_ATL_TPB_TX_SCP_INS_EN_MSK,
1299                             HW_ATL_TPB_TX_SCP_INS_EN_SHIFT,
1300                             tx_path_scp_ins_en);
1301 }
1302
1303 /* TPO: tx packet offload */
1304 void hw_atl_tpo_ipv4header_crc_offload_en_set(struct aq_hw_s *aq_hw,
1305                                               u32 ipv4header_crc_offload_en)
1306 {
1307         aq_hw_write_reg_bit(aq_hw, HW_ATL_TPO_IPV4CHK_EN_ADR,
1308                             HW_ATL_TPO_IPV4CHK_EN_MSK,
1309                             HW_ATL_TPO_IPV4CHK_EN_SHIFT,
1310                             ipv4header_crc_offload_en);
1311 }
1312
1313 void hw_atl_tpo_tcp_udp_crc_offload_en_set(struct aq_hw_s *aq_hw,
1314                                            u32 tcp_udp_crc_offload_en)
1315 {
1316         aq_hw_write_reg_bit(aq_hw, HW_ATL_TPOL4CHK_EN_ADR,
1317                             HW_ATL_TPOL4CHK_EN_MSK,
1318                             HW_ATL_TPOL4CHK_EN_SHIFT,
1319                             tcp_udp_crc_offload_en);
1320 }
1321
1322 void hw_atl_tpo_tx_pkt_sys_lbk_en_set(struct aq_hw_s *aq_hw,
1323                                       u32 tx_pkt_sys_lbk_en)
1324 {
1325         aq_hw_write_reg_bit(aq_hw, HW_ATL_TPO_PKT_SYS_LBK_ADR,
1326                             HW_ATL_TPO_PKT_SYS_LBK_MSK,
1327                             HW_ATL_TPO_PKT_SYS_LBK_SHIFT,
1328                             tx_pkt_sys_lbk_en);
1329 }
1330
1331 /* TPS: tx packet scheduler */
1332 void hw_atl_tps_tx_pkt_shed_data_arb_mode_set(struct aq_hw_s *aq_hw,
1333                                               u32 tx_pkt_shed_data_arb_mode)
1334 {
1335         aq_hw_write_reg_bit(aq_hw, HW_ATL_TPS_DATA_TC_ARB_MODE_ADR,
1336                             HW_ATL_TPS_DATA_TC_ARB_MODE_MSK,
1337                             HW_ATL_TPS_DATA_TC_ARB_MODE_SHIFT,
1338                             tx_pkt_shed_data_arb_mode);
1339 }
1340
1341 void hw_atl_tps_tx_pkt_shed_desc_rate_curr_time_res_set(struct aq_hw_s *aq_hw,
1342                                                         u32 curr_time_res)
1343 {
1344         aq_hw_write_reg_bit(aq_hw, HW_ATL_TPS_DESC_RATE_TA_RST_ADR,
1345                             HW_ATL_TPS_DESC_RATE_TA_RST_MSK,
1346                             HW_ATL_TPS_DESC_RATE_TA_RST_SHIFT,
1347                             curr_time_res);
1348 }
1349
1350 void hw_atl_tps_tx_pkt_shed_desc_rate_lim_set(struct aq_hw_s *aq_hw,
1351                                               u32 tx_pkt_shed_desc_rate_lim)
1352 {
1353         aq_hw_write_reg_bit(aq_hw, HW_ATL_TPS_DESC_RATE_LIM_ADR,
1354                             HW_ATL_TPS_DESC_RATE_LIM_MSK,
1355                             HW_ATL_TPS_DESC_RATE_LIM_SHIFT,
1356                             tx_pkt_shed_desc_rate_lim);
1357 }
1358
1359 void hw_atl_tps_tx_pkt_shed_desc_tc_arb_mode_set(struct aq_hw_s *aq_hw,
1360                                                  u32 arb_mode)
1361 {
1362         aq_hw_write_reg_bit(aq_hw, HW_ATL_TPS_DESC_TC_ARB_MODE_ADR,
1363                             HW_ATL_TPS_DESC_TC_ARB_MODE_MSK,
1364                             HW_ATL_TPS_DESC_TC_ARB_MODE_SHIFT,
1365                             arb_mode);
1366 }
1367
1368 void hw_atl_tps_tx_pkt_shed_desc_tc_max_credit_set(struct aq_hw_s *aq_hw,
1369                                                    u32 max_credit,
1370                                                    u32 tc)
1371 {
1372         aq_hw_write_reg_bit(aq_hw, HW_ATL_TPS_DESC_TCTCREDIT_MAX_ADR(tc),
1373                             HW_ATL_TPS_DESC_TCTCREDIT_MAX_MSK,
1374                             HW_ATL_TPS_DESC_TCTCREDIT_MAX_SHIFT,
1375                             max_credit);
1376 }
1377
1378 void hw_atl_tps_tx_pkt_shed_desc_tc_weight_set(struct aq_hw_s *aq_hw,
1379                                                u32 tx_pkt_shed_desc_tc_weight,
1380                                                u32 tc)
1381 {
1382         aq_hw_write_reg_bit(aq_hw, HW_ATL_TPS_DESC_TCTWEIGHT_ADR(tc),
1383                             HW_ATL_TPS_DESC_TCTWEIGHT_MSK,
1384                             HW_ATL_TPS_DESC_TCTWEIGHT_SHIFT,
1385                             tx_pkt_shed_desc_tc_weight);
1386 }
1387
1388 void hw_atl_tps_tx_pkt_shed_desc_vm_arb_mode_set(struct aq_hw_s *aq_hw,
1389                                                  u32 arb_mode)
1390 {
1391         aq_hw_write_reg_bit(aq_hw, HW_ATL_TPS_DESC_VM_ARB_MODE_ADR,
1392                             HW_ATL_TPS_DESC_VM_ARB_MODE_MSK,
1393                             HW_ATL_TPS_DESC_VM_ARB_MODE_SHIFT,
1394                             arb_mode);
1395 }
1396
1397 void hw_atl_tps_tx_pkt_shed_tc_data_max_credit_set(struct aq_hw_s *aq_hw,
1398                                                    u32 max_credit,
1399                                                    u32 tc)
1400 {
1401         aq_hw_write_reg_bit(aq_hw, HW_ATL_TPS_DATA_TCTCREDIT_MAX_ADR(tc),
1402                             HW_ATL_TPS_DATA_TCTCREDIT_MAX_MSK,
1403                             HW_ATL_TPS_DATA_TCTCREDIT_MAX_SHIFT,
1404                             max_credit);
1405 }
1406
1407 void hw_atl_tps_tx_pkt_shed_tc_data_weight_set(struct aq_hw_s *aq_hw,
1408                                                u32 tx_pkt_shed_tc_data_weight,
1409                                                u32 tc)
1410 {
1411         aq_hw_write_reg_bit(aq_hw, HW_ATL_TPS_DATA_TCTWEIGHT_ADR(tc),
1412                             HW_ATL_TPS_DATA_TCTWEIGHT_MSK,
1413                             HW_ATL_TPS_DATA_TCTWEIGHT_SHIFT,
1414                             tx_pkt_shed_tc_data_weight);
1415 }
1416
1417 /* tx */
1418 void hw_atl_tx_tx_reg_res_dis_set(struct aq_hw_s *aq_hw, u32 tx_reg_res_dis)
1419 {
1420         aq_hw_write_reg_bit(aq_hw, HW_ATL_TX_REG_RES_DSBL_ADR,
1421                             HW_ATL_TX_REG_RES_DSBL_MSK,
1422                             HW_ATL_TX_REG_RES_DSBL_SHIFT, tx_reg_res_dis);
1423 }
1424
1425 /* msm */
1426 u32 hw_atl_msm_reg_access_status_get(struct aq_hw_s *aq_hw)
1427 {
1428         return aq_hw_read_reg_bit(aq_hw, HW_ATL_MSM_REG_ACCESS_BUSY_ADR,
1429                                   HW_ATL_MSM_REG_ACCESS_BUSY_MSK,
1430                                   HW_ATL_MSM_REG_ACCESS_BUSY_SHIFT);
1431 }
1432
1433 void hw_atl_msm_reg_addr_for_indirect_addr_set(struct aq_hw_s *aq_hw,
1434                                                u32 reg_addr_for_indirect_addr)
1435 {
1436         aq_hw_write_reg_bit(aq_hw, HW_ATL_MSM_REG_ADDR_ADR,
1437                             HW_ATL_MSM_REG_ADDR_MSK,
1438                             HW_ATL_MSM_REG_ADDR_SHIFT,
1439                             reg_addr_for_indirect_addr);
1440 }
1441
1442 void hw_atl_msm_reg_rd_strobe_set(struct aq_hw_s *aq_hw, u32 reg_rd_strobe)
1443 {
1444         aq_hw_write_reg_bit(aq_hw, HW_ATL_MSM_REG_RD_STROBE_ADR,
1445                             HW_ATL_MSM_REG_RD_STROBE_MSK,
1446                             HW_ATL_MSM_REG_RD_STROBE_SHIFT,
1447                             reg_rd_strobe);
1448 }
1449
1450 u32 hw_atl_msm_reg_rd_data_get(struct aq_hw_s *aq_hw)
1451 {
1452         return aq_hw_read_reg(aq_hw, HW_ATL_MSM_REG_RD_DATA_ADR);
1453 }
1454
1455 void hw_atl_msm_reg_wr_data_set(struct aq_hw_s *aq_hw, u32 reg_wr_data)
1456 {
1457         aq_hw_write_reg(aq_hw, HW_ATL_MSM_REG_WR_DATA_ADR, reg_wr_data);
1458 }
1459
1460 void hw_atl_msm_reg_wr_strobe_set(struct aq_hw_s *aq_hw, u32 reg_wr_strobe)
1461 {
1462         aq_hw_write_reg_bit(aq_hw, HW_ATL_MSM_REG_WR_STROBE_ADR,
1463                             HW_ATL_MSM_REG_WR_STROBE_MSK,
1464                             HW_ATL_MSM_REG_WR_STROBE_SHIFT,
1465                             reg_wr_strobe);
1466 }
1467
1468 /* pci */
1469 void hw_atl_pci_pci_reg_res_dis_set(struct aq_hw_s *aq_hw, u32 pci_reg_res_dis)
1470 {
1471         aq_hw_write_reg_bit(aq_hw, HW_ATL_PCI_REG_RES_DSBL_ADR,
1472                             HW_ATL_PCI_REG_RES_DSBL_MSK,
1473                             HW_ATL_PCI_REG_RES_DSBL_SHIFT,
1474                             pci_reg_res_dis);
1475 }
1476
1477 void hw_atl_reg_glb_cpu_scratch_scp_set(struct aq_hw_s *aq_hw,
1478                                         u32 glb_cpu_scratch_scp,
1479                                         u32 scratch_scp)
1480 {
1481         aq_hw_write_reg(aq_hw, HW_ATL_GLB_CPU_SCRATCH_SCP_ADR(scratch_scp),
1482                         glb_cpu_scratch_scp);
1483 }
1484
1485 void hw_atl_mcp_up_force_intr_set(struct aq_hw_s *aq_hw, u32 up_force_intr)
1486 {
1487         aq_hw_write_reg_bit(aq_hw, HW_ATL_MCP_UP_FORCE_INTERRUPT_ADR,
1488                         HW_ATL_MCP_UP_FORCE_INTERRUPT_MSK,
1489                         HW_ATL_MCP_UP_FORCE_INTERRUPT_SHIFT, up_force_intr);
1490 }