1 // SPDX-License-Identifier: (BSD-3-Clause OR GPL-2.0)
2 /* Copyright (C) 2014-2017 aQuantia Corporation. */
4 /* File hw_atl_utils_fw2x.c: Definition of firmware 2.x functions for
5 * Atlantic hardware abstraction layer.
9 #include "../atl_hw_regs.h"
11 #include "../atl_types.h"
12 #include "hw_atl_utils.h"
13 #include "hw_atl_llh.h"
15 #define HW_ATL_FW2X_MPI_EFUSE_ADDR 0x364
16 #define HW_ATL_FW2X_MPI_MBOX_ADDR 0x360
17 #define HW_ATL_FW2X_MPI_RPC_ADDR 0x334
19 #define HW_ATL_FW2X_MPI_CONTROL_ADDR 0x368
20 #define HW_ATL_FW2X_MPI_CONTROL2_ADDR 0x36C
21 #define HW_ATL_FW2X_MPI_LED_ADDR 0x31c
23 #define HW_ATL_FW2X_MPI_STATE_ADDR 0x370
24 #define HW_ATL_FW2X_MPI_STATE2_ADDR 0x374
26 #define HW_ATL_FW2X_CAP_SLEEP_PROXY BIT(CAPS_HI_SLEEP_PROXY)
27 #define HW_ATL_FW2X_CAP_WOL BIT(CAPS_HI_WOL)
29 #define HW_ATL_FW2X_CAP_EEE_1G_MASK BIT(CAPS_HI_1000BASET_FD_EEE)
30 #define HW_ATL_FW2X_CAP_EEE_2G5_MASK BIT(CAPS_HI_2P5GBASET_FD_EEE)
31 #define HW_ATL_FW2X_CAP_EEE_5G_MASK BIT(CAPS_HI_5GBASET_FD_EEE)
32 #define HW_ATL_FW2X_CAP_EEE_10G_MASK BIT(CAPS_HI_10GBASET_FD_EEE)
34 #define HAL_ATLANTIC_WOL_FILTERS_COUNT 8
35 #define HAL_ATLANTIC_UTILS_FW2X_MSG_WOL 0x0E
37 #define HW_ATL_FW_FEATURE_EEPROM 0x03010025
38 #define HW_ATL_FW_FEATURE_LED 0x03010026
40 struct fw2x_msg_wol_pattern {
43 } __attribute__((__packed__));
48 u8 magic_packet_enabled;
50 struct fw2x_msg_wol_pattern filter[HAL_ATLANTIC_WOL_FILTERS_COUNT];
55 u32 link_down_timeout;
56 } __attribute__((__packed__));
58 static int aq_fw2x_set_link_speed(struct aq_hw_s *self, u32 speed);
59 static int aq_fw2x_set_state(struct aq_hw_s *self,
60 enum hal_atl_utils_fw_state_e state);
62 static int aq_fw2x_init(struct aq_hw_s *self)
66 /* check 10 times by 1ms */
67 AQ_HW_WAIT_FOR(0U != (self->mbox_addr =
68 aq_hw_read_reg(self, HW_ATL_FW2X_MPI_MBOX_ADDR)),
70 AQ_HW_WAIT_FOR(0U != (self->rpc_addr =
71 aq_hw_read_reg(self, HW_ATL_FW2X_MPI_RPC_ADDR)),
76 static int aq_fw2x_deinit(struct aq_hw_s *self)
78 int err = aq_fw2x_set_link_speed(self, 0);
81 err = aq_fw2x_set_state(self, MPI_DEINIT);
86 static enum hw_atl_fw2x_rate link_speed_mask_2fw2x_ratemask(u32 speed)
88 enum hw_atl_fw2x_rate rate = 0;
90 if (speed & AQ_NIC_RATE_10G)
91 rate |= FW2X_RATE_10G;
93 if (speed & AQ_NIC_RATE_5G)
96 if (speed & AQ_NIC_RATE_5G5R)
99 if (speed & AQ_NIC_RATE_2G5)
100 rate |= FW2X_RATE_2G5;
102 if (speed & AQ_NIC_RATE_1G)
103 rate |= FW2X_RATE_1G;
105 if (speed & AQ_NIC_RATE_100M)
106 rate |= FW2X_RATE_100M;
111 static u32 fw2x_to_eee_mask(u32 speed)
115 if (speed & HW_ATL_FW2X_CAP_EEE_10G_MASK)
116 rate |= AQ_NIC_RATE_EEE_10G;
118 if (speed & HW_ATL_FW2X_CAP_EEE_5G_MASK)
119 rate |= AQ_NIC_RATE_EEE_5G;
121 if (speed & HW_ATL_FW2X_CAP_EEE_2G5_MASK)
122 rate |= AQ_NIC_RATE_EEE_2G5;
124 if (speed & HW_ATL_FW2X_CAP_EEE_1G_MASK)
125 rate |= AQ_NIC_RATE_EEE_1G;
130 static int aq_fw2x_set_link_speed(struct aq_hw_s *self, u32 speed)
132 u32 val = link_speed_mask_2fw2x_ratemask(speed);
134 aq_hw_write_reg(self, HW_ATL_FW2X_MPI_CONTROL_ADDR, val);
139 static void aq_fw2x_set_mpi_flow_control(struct aq_hw_s *self, u32 *mpi_state)
141 if (self->aq_nic_cfg->flow_control & AQ_NIC_FC_RX)
142 *mpi_state |= BIT(CAPS_HI_PAUSE);
144 *mpi_state &= ~BIT(CAPS_HI_PAUSE);
146 if (self->aq_nic_cfg->flow_control & AQ_NIC_FC_TX)
147 *mpi_state |= BIT(CAPS_HI_ASYMMETRIC_PAUSE);
149 *mpi_state &= ~BIT(CAPS_HI_ASYMMETRIC_PAUSE);
152 static int aq_fw2x_set_state(struct aq_hw_s *self,
153 enum hal_atl_utils_fw_state_e state)
155 u32 mpi_state = aq_hw_read_reg(self, HW_ATL_FW2X_MPI_CONTROL2_ADDR);
159 mpi_state &= ~BIT(CAPS_HI_LINK_DROP);
160 aq_fw2x_set_mpi_flow_control(self, &mpi_state);
163 mpi_state |= BIT(CAPS_HI_LINK_DROP);
170 aq_hw_write_reg(self, HW_ATL_FW2X_MPI_CONTROL2_ADDR, mpi_state);
174 static int aq_fw2x_update_link_status(struct aq_hw_s *self)
176 u32 mpi_state = aq_hw_read_reg(self, HW_ATL_FW2X_MPI_STATE_ADDR);
177 u32 speed = mpi_state & (FW2X_RATE_100M | FW2X_RATE_1G |
178 FW2X_RATE_2G5 | FW2X_RATE_5G | FW2X_RATE_10G);
179 struct aq_hw_link_status_s *link_status = &self->aq_link_status;
182 if (speed & FW2X_RATE_10G)
183 link_status->mbps = 10000;
184 else if (speed & FW2X_RATE_5G)
185 link_status->mbps = 5000;
186 else if (speed & FW2X_RATE_2G5)
187 link_status->mbps = 2500;
188 else if (speed & FW2X_RATE_1G)
189 link_status->mbps = 1000;
190 else if (speed & FW2X_RATE_100M)
191 link_status->mbps = 100;
193 link_status->mbps = 10000;
195 link_status->mbps = 0;
202 int aq_fw2x_get_mac_permanent(struct aq_hw_s *self, u8 *mac)
207 u32 mac_addr[2] = { 0 };
208 u32 efuse_addr = aq_hw_read_reg(self, HW_ATL_FW2X_MPI_EFUSE_ADDR);
210 if (efuse_addr != 0) {
211 err = hw_atl_utils_fw_downld_dwords(self,
212 efuse_addr + (40U * 4U),
214 ARRAY_SIZE(mac_addr));
217 mac_addr[0] = rte_constant_bswap32(mac_addr[0]);
218 mac_addr[1] = rte_constant_bswap32(mac_addr[1]);
221 ether_addr_copy((struct ether_addr *)mac_addr,
222 (struct ether_addr *)mac);
224 if ((mac[0] & 0x01U) || ((mac[0] | mac[1] | mac[2]) == 0x00U)) {
225 unsigned int rnd = (uint32_t)rte_rand();
227 //get_random_bytes(&rnd, sizeof(unsigned int));
234 mac[5] = (u8)(0xFFU & l);
236 mac[4] = (u8)(0xFFU & l);
238 mac[3] = (u8)(0xFFU & l);
240 mac[2] = (u8)(0xFFU & l);
241 mac[1] = (u8)(0xFFU & h);
243 mac[0] = (u8)(0xFFU & h);
248 static int aq_fw2x_update_stats(struct aq_hw_s *self)
251 u32 mpi_opts = aq_hw_read_reg(self, HW_ATL_FW2X_MPI_CONTROL2_ADDR);
252 u32 orig_stats_val = mpi_opts & BIT(CAPS_HI_STATISTICS);
254 /* Toggle statistics bit for FW to update */
255 mpi_opts = mpi_opts ^ BIT(CAPS_HI_STATISTICS);
256 aq_hw_write_reg(self, HW_ATL_FW2X_MPI_CONTROL2_ADDR, mpi_opts);
258 /* Wait FW to report back */
259 AQ_HW_WAIT_FOR(orig_stats_val !=
260 (aq_hw_read_reg(self, HW_ATL_FW2X_MPI_STATE2_ADDR) &
261 BIT(CAPS_HI_STATISTICS)),
266 return hw_atl_utils_update_stats(self);
269 static int aq_fw2x_get_temp(struct aq_hw_s *self, int *temp)
272 u32 mpi_opts = aq_hw_read_reg(self, HW_ATL_FW2X_MPI_CONTROL2_ADDR);
273 u32 temp_val = mpi_opts & BIT(CAPS_HI_TEMPERATURE);
276 /* Toggle statistics bit for FW to 0x36C.18 (CAPS_HI_TEMPERATURE) */
277 mpi_opts = mpi_opts ^ BIT(CAPS_HI_TEMPERATURE);
278 aq_hw_write_reg(self, HW_ATL_FW2X_MPI_CONTROL2_ADDR, mpi_opts);
280 /* Wait FW to report back */
281 AQ_HW_WAIT_FOR(temp_val !=
282 (aq_hw_read_reg(self, HW_ATL_FW2X_MPI_STATE2_ADDR) &
283 BIT(CAPS_HI_TEMPERATURE)), 1U, 10000U);
284 err = hw_atl_utils_fw_downld_dwords(self,
286 offsetof(struct hw_aq_atl_utils_mbox, info) +
287 offsetof(struct hw_aq_info, phy_temperature),
289 sizeof(temp_res) / sizeof(u32));
294 *temp = temp_res * 100 / 256;
298 static int aq_fw2x_get_cable_len(struct aq_hw_s *self, int *cable_len)
303 err = hw_atl_utils_fw_downld_dwords(self,
305 offsetof(struct hw_aq_atl_utils_mbox, info) +
306 offsetof(struct hw_aq_info, phy_temperature),
308 sizeof(cable_len_res) / sizeof(u32));
313 *cable_len = (cable_len_res >> 16) & 0xFF;
321 static int aq_fw2x_set_sleep_proxy(struct aq_hw_s *self, u8 *mac)
324 struct hw_aq_atl_utils_fw_rpc *rpc = NULL;
325 struct offload_info *cfg = NULL;
326 unsigned int rpc_size = 0U;
329 rpc_size = sizeof(rpc->msg_id) + sizeof(*cfg);
331 err = hw_atl_utils_fw_rpc_wait(self, &rpc);
335 memset(rpc, 0, rpc_size);
336 cfg = (struct offload_info *)(&rpc->msg_id + 1);
338 memcpy(cfg->mac_addr, mac, ETH_ALEN);
339 cfg->len = sizeof(*cfg);
341 /* Clear bit 0x36C.23 */
342 mpi_opts = aq_hw_read_reg(self, HW_ATL_FW2X_MPI_CONTROL2_ADDR);
343 mpi_opts &= ~HW_ATL_FW2X_CAP_SLEEP_PROXY;
345 aq_hw_write_reg(self, HW_ATL_FW2X_MPI_CONTROL2_ADDR, mpi_opts);
347 err = hw_atl_utils_fw_rpc_call(self, rpc_size);
351 /* Set bit 0x36C.23 */
352 mpi_opts |= HW_ATL_FW2X_CAP_SLEEP_PROXY;
353 aq_hw_write_reg(self, HW_ATL_FW2X_MPI_CONTROL2_ADDR, mpi_opts);
355 AQ_HW_WAIT_FOR((aq_hw_read_reg(self, HW_ATL_FW2X_MPI_STATE2_ADDR) &
356 HW_ATL_FW2X_CAP_SLEEP_PROXY), 1U, 10000U);
361 static int aq_fw2x_set_wol_params(struct aq_hw_s *self, u8 *mac)
364 struct fw2x_msg_wol *msg = NULL;
367 struct hw_aq_atl_utils_fw_rpc *rpc = NULL;
369 err = hw_atl_utils_fw_rpc_wait(self, &rpc);
373 msg = (struct fw2x_msg_wol *)rpc;
375 msg->msg_id = HAL_ATLANTIC_UTILS_FW2X_MSG_WOL;
376 msg->magic_packet_enabled = true;
377 memcpy(msg->hw_addr, mac, ETH_ALEN);
379 mpi_opts = aq_hw_read_reg(self, HW_ATL_FW2X_MPI_CONTROL2_ADDR);
380 mpi_opts &= ~(HW_ATL_FW2X_CAP_SLEEP_PROXY | HW_ATL_FW2X_CAP_WOL);
382 aq_hw_write_reg(self, HW_ATL_FW2X_MPI_CONTROL2_ADDR, mpi_opts);
384 err = hw_atl_utils_fw_rpc_call(self, sizeof(*msg));
388 /* Set bit 0x36C.24 */
389 mpi_opts |= HW_ATL_FW2X_CAP_WOL;
390 aq_hw_write_reg(self, HW_ATL_FW2X_MPI_CONTROL2_ADDR, mpi_opts);
392 AQ_HW_WAIT_FOR((aq_hw_read_reg(self, HW_ATL_FW2X_MPI_STATE2_ADDR) &
393 HW_ATL_FW2X_CAP_WOL), 1U, 10000U);
398 static int aq_fw2x_set_power(struct aq_hw_s *self,
399 unsigned int power_state __rte_unused,
404 if (self->aq_nic_cfg->wol & AQ_NIC_WOL_ENABLED) {
405 err = aq_fw2x_set_sleep_proxy(self, mac);
408 err = aq_fw2x_set_wol_params(self, mac);
416 static int aq_fw2x_set_eee_rate(struct aq_hw_s *self, u32 speed)
418 u32 mpi_opts = aq_hw_read_reg(self, HW_ATL_FW2X_MPI_CONTROL2_ADDR);
419 mpi_opts &= ~(HW_ATL_FW2X_CAP_EEE_1G_MASK |
420 HW_ATL_FW2X_CAP_EEE_2G5_MASK | HW_ATL_FW2X_CAP_EEE_5G_MASK |
421 HW_ATL_FW2X_CAP_EEE_10G_MASK);
423 if (speed & AQ_NIC_RATE_EEE_10G)
424 mpi_opts |= HW_ATL_FW2X_CAP_EEE_10G_MASK;
426 if (speed & AQ_NIC_RATE_EEE_5G)
427 mpi_opts |= HW_ATL_FW2X_CAP_EEE_5G_MASK;
429 if (speed & AQ_NIC_RATE_EEE_2G5)
430 mpi_opts |= HW_ATL_FW2X_CAP_EEE_2G5_MASK;
432 if (speed & AQ_NIC_RATE_EEE_1G)
433 mpi_opts |= HW_ATL_FW2X_CAP_EEE_1G_MASK;
435 aq_hw_write_reg(self, HW_ATL_FW2X_MPI_CONTROL2_ADDR, mpi_opts);
440 static int aq_fw2x_get_eee_rate(struct aq_hw_s *self, u32 *rate,
441 u32 *supported_rates)
447 err = hw_atl_utils_fw_downld_dwords(self,
449 offsetof(struct hw_aq_atl_utils_mbox, info) +
450 offsetof(struct hw_aq_info, caps_hi),
452 sizeof(caps_hi) / sizeof(u32));
457 *supported_rates = fw2x_to_eee_mask(caps_hi);
459 mpi_state = aq_hw_read_reg(self, HW_ATL_FW2X_MPI_STATE2_ADDR);
460 *rate = fw2x_to_eee_mask(mpi_state);
467 static int aq_fw2x_set_flow_control(struct aq_hw_s *self)
469 u32 mpi_state = aq_hw_read_reg(self, HW_ATL_FW2X_MPI_CONTROL2_ADDR);
471 aq_fw2x_set_mpi_flow_control(self, &mpi_state);
473 aq_hw_write_reg(self, HW_ATL_FW2X_MPI_CONTROL2_ADDR, mpi_state);
478 static int aq_fw2x_led_control(struct aq_hw_s *self, u32 mode)
480 if (self->fw_ver_actual < HW_ATL_FW_FEATURE_LED)
483 aq_hw_write_reg(self, HW_ATL_FW2X_MPI_LED_ADDR, mode);
487 static int aq_fw2x_get_eeprom(struct aq_hw_s *self, u32 *data, u32 len)
490 struct smbus_read_request request;
494 if (self->fw_ver_actual < HW_ATL_FW_FEATURE_EEPROM)
497 request.device_id = SMBUS_DEVICE_ID;
499 request.length = len;
501 /* Write SMBUS request to cfg memory */
502 err = hw_atl_utils_fw_upload_dwords(self, self->rpc_addr,
503 (u32 *)(void *)&request,
504 RTE_ALIGN(sizeof(request), sizeof(u32)));
509 /* Toggle 0x368.SMBUS_READ_REQUEST bit */
510 mpi_opts = aq_hw_read_reg(self, HW_ATL_FW2X_MPI_CONTROL_ADDR);
511 mpi_opts ^= SMBUS_READ_REQUEST;
513 aq_hw_write_reg(self, HW_ATL_FW2X_MPI_CONTROL_ADDR, mpi_opts);
515 /* Wait until REQUEST_BIT matched in 0x370 */
517 AQ_HW_WAIT_FOR((aq_hw_read_reg(self, HW_ATL_FW2X_MPI_STATE_ADDR) &
518 SMBUS_READ_REQUEST) == (mpi_opts & SMBUS_READ_REQUEST),
524 err = hw_atl_utils_fw_downld_dwords(self, self->rpc_addr + sizeof(u32),
526 RTE_ALIGN(sizeof(result), sizeof(u32)));
532 err = hw_atl_utils_fw_downld_dwords(self,
533 self->rpc_addr + sizeof(u32) * 2,
535 RTE_ALIGN(len, sizeof(u32)));
545 static int aq_fw2x_set_eeprom(struct aq_hw_s *self, u32 *data, u32 len)
547 struct smbus_write_request request;
548 u32 mpi_opts, result = 0;
551 if (self->fw_ver_actual < HW_ATL_FW_FEATURE_EEPROM)
554 request.device_id = SMBUS_DEVICE_ID;
556 request.length = len;
558 /* Write SMBUS request to cfg memory */
559 err = hw_atl_utils_fw_upload_dwords(self, self->rpc_addr,
560 (u32 *)(void *)&request,
561 RTE_ALIGN(sizeof(request), sizeof(u32)));
566 /* Write SMBUS data to cfg memory */
567 err = hw_atl_utils_fw_upload_dwords(self,
568 self->rpc_addr + sizeof(request),
570 RTE_ALIGN(len, sizeof(u32)));
575 /* Toggle 0x368.SMBUS_WRITE_REQUEST bit */
576 mpi_opts = aq_hw_read_reg(self, HW_ATL_FW2X_MPI_CONTROL_ADDR);
577 mpi_opts ^= SMBUS_WRITE_REQUEST;
579 aq_hw_write_reg(self, HW_ATL_FW2X_MPI_CONTROL_ADDR, mpi_opts);
581 /* Wait until REQUEST_BIT matched in 0x370 */
582 AQ_HW_WAIT_FOR((aq_hw_read_reg(self, HW_ATL_FW2X_MPI_STATE_ADDR) &
583 SMBUS_WRITE_REQUEST) == (mpi_opts & SMBUS_WRITE_REQUEST),
589 /* Read status of write operation */
590 err = hw_atl_utils_fw_downld_dwords(self, self->rpc_addr + sizeof(u32),
592 RTE_ALIGN(sizeof(result), sizeof(u32)));
600 const struct aq_fw_ops aq_fw_2x_ops = {
601 .init = aq_fw2x_init,
602 .deinit = aq_fw2x_deinit,
604 .get_mac_permanent = aq_fw2x_get_mac_permanent,
605 .set_link_speed = aq_fw2x_set_link_speed,
606 .set_state = aq_fw2x_set_state,
607 .update_link_status = aq_fw2x_update_link_status,
608 .update_stats = aq_fw2x_update_stats,
609 .set_power = aq_fw2x_set_power,
610 .get_temp = aq_fw2x_get_temp,
611 .get_cable_len = aq_fw2x_get_cable_len,
612 .set_eee_rate = aq_fw2x_set_eee_rate,
613 .get_eee_rate = aq_fw2x_get_eee_rate,
614 .set_flow_control = aq_fw2x_set_flow_control,
615 .led_control = aq_fw2x_led_control,
616 .get_eeprom = aq_fw2x_get_eeprom,
617 .set_eeprom = aq_fw2x_set_eeprom,