drivers/net/avf/avf_rxtx.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2017 Intel Corporation
   3  */
   4
   5 #include <stdio.h>
   6 #include <stdlib.h>
   7 #include <string.h>
   8 #include <errno.h>
   9 #include <stdint.h>
  10 #include <stdarg.h>
  11 #include <unistd.h>
  12 #include <inttypes.h>
  13 #include <sys/queue.h>
  14
  15 #include <rte_string_fns.h>
  16 #include <rte_memzone.h>
  17 #include <rte_mbuf.h>
  18 #include <rte_malloc.h>
  19 #include <rte_ether.h>
  20 #include <rte_ethdev_driver.h>
  21 #include <rte_tcp.h>
  22 #include <rte_sctp.h>
  23 #include <rte_udp.h>
  24 #include <rte_ip.h>
  25 #include <rte_net.h>
  26
  27 #include "avf_log.h"
  28 #include "base/avf_prototype.h"
  29 #include "base/avf_type.h"
  30 #include "avf.h"
  31 #include "avf_rxtx.h"
  32
  33 static inline int
  34 check_rx_thresh(uint16_t nb_desc, uint16_t thresh)
  35 {
  36         /* The following constraints must be satisfied:
  37          *   thresh < rxq->nb_rx_desc
  38          */
  39         if (thresh >= nb_desc) {
  40                 PMD_INIT_LOG(ERR, "rx_free_thresh (%u) must be less than %u",
  41                              thresh, nb_desc);
  42                 return -EINVAL;
  43         }
  44         return 0;
  45 }
  46
  47 static inline int
  48 check_tx_thresh(uint16_t nb_desc, uint16_t tx_rs_thresh,
  49                 uint16_t tx_free_thresh)
  50 {
  51         /* TX descriptors will have their RS bit set after tx_rs_thresh
  52          * descriptors have been used. The TX descriptor ring will be cleaned
  53          * after tx_free_thresh descriptors are used or if the number of
  54          * descriptors required to transmit a packet is greater than the
  55          * number of free TX descriptors.
  56          *
  57          * The following constraints must be satisfied:
  58          *  - tx_rs_thresh must be less than the size of the ring minus 2.
  59          *  - tx_free_thresh must be less than the size of the ring minus 3.
  60          *  - tx_rs_thresh must be less than or equal to tx_free_thresh.
  61          *  - tx_rs_thresh must be a divisor of the ring size.
  62          *
  63          * One descriptor in the TX ring is used as a sentinel to avoid a H/W
  64          * race condition, hence the maximum threshold constraints. When set
  65          * to zero use default values.
  66          */
  67         if (tx_rs_thresh >= (nb_desc - 2)) {
  68                 PMD_INIT_LOG(ERR, "tx_rs_thresh (%u) must be less than the "
  69                              "number of TX descriptors (%u) minus 2",
  70                              tx_rs_thresh, nb_desc);
  71                 return -EINVAL;
  72         }
  73         if (tx_free_thresh >= (nb_desc - 3)) {
  74                 PMD_INIT_LOG(ERR, "tx_free_thresh (%u) must be less than the "
  75                              "number of TX descriptors (%u) minus 3.",
  76                              tx_free_thresh, nb_desc);
  77                 return -EINVAL;
  78         }
  79         if (tx_rs_thresh > tx_free_thresh) {
  80                 PMD_INIT_LOG(ERR, "tx_rs_thresh (%u) must be less than or "
  81                              "equal to tx_free_thresh (%u).",
  82                              tx_rs_thresh, tx_free_thresh);
  83                 return -EINVAL;
  84         }
  85         if ((nb_desc % tx_rs_thresh) != 0) {
  86                 PMD_INIT_LOG(ERR, "tx_rs_thresh (%u) must be a divisor of the "
  87                              "number of TX descriptors (%u).",
  88                              tx_rs_thresh, nb_desc);
  89                 return -EINVAL;
  90         }
  91
  92         return 0;
  93 }
  94
  95 #ifdef RTE_LIBRTE_AVF_INC_VECTOR
  96 static inline bool
  97 check_rx_vec_allow(struct avf_rx_queue *rxq)
  98 {
  99         if (rxq->rx_free_thresh >= AVF_VPMD_RX_MAX_BURST &&
 100             rxq->nb_rx_desc % rxq->rx_free_thresh == 0) {
 101                 PMD_INIT_LOG(DEBUG, "Vector Rx can be enabled on this rxq.");
 102                 return TRUE;
 103         }
 104
 105         PMD_INIT_LOG(DEBUG, "Vector Rx cannot be enabled on this rxq.");
 106         return FALSE;
 107 }
 108
 109 static inline bool
 110 check_tx_vec_allow(struct avf_tx_queue *txq)
 111 {
 112         if ((txq->txq_flags & AVF_SIMPLE_FLAGS) == AVF_SIMPLE_FLAGS &&
 113             txq->rs_thresh >= AVF_VPMD_TX_MAX_BURST &&
 114             txq->rs_thresh <= AVF_VPMD_TX_MAX_FREE_BUF) {
 115                 PMD_INIT_LOG(DEBUG, "Vector tx can be enabled on this txq.");
 116                 return TRUE;
 117         }
 118         PMD_INIT_LOG(DEBUG, "Vector Tx cannot be enabled on this txq.");
 119         return FALSE;
 120 }
 121 #endif
 122
 123 static inline bool
 124 check_rx_bulk_allow(struct avf_rx_queue *rxq)
 125 {
 126         int ret = TRUE;
 127
 128         if (!(rxq->rx_free_thresh >= AVF_RX_MAX_BURST)) {
 129                 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions: "
 130                              "rxq->rx_free_thresh=%d, "
 131                              "AVF_RX_MAX_BURST=%d",
 132                              rxq->rx_free_thresh, AVF_RX_MAX_BURST);
 133                 ret = FALSE;
 134         } else if (rxq->nb_rx_desc % rxq->rx_free_thresh != 0) {
 135                 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions: "
 136                              "rxq->nb_rx_desc=%d, "
 137                              "rxq->rx_free_thresh=%d",
 138                              rxq->nb_rx_desc, rxq->rx_free_thresh);
 139                 ret = FALSE;
 140         }
 141         return ret;
 142 }
 143
 144 static inline void
 145 reset_rx_queue(struct avf_rx_queue *rxq)
 146 {
 147         uint16_t len, i;
 148
 149         if (!rxq)
 150                 return;
 151
 152         len = rxq->nb_rx_desc + AVF_RX_MAX_BURST;
 153
 154         for (i = 0; i < len * sizeof(union avf_rx_desc); i++)
 155                 ((volatile char *)rxq->rx_ring)[i] = 0;
 156
 157         memset(&rxq->fake_mbuf, 0x0, sizeof(rxq->fake_mbuf));
 158
 159         for (i = 0; i < AVF_RX_MAX_BURST; i++)
 160                 rxq->sw_ring[rxq->nb_rx_desc + i] = &rxq->fake_mbuf;
 161
 162         /* for rx bulk */
 163         rxq->rx_nb_avail = 0;
 164         rxq->rx_next_avail = 0;
 165         rxq->rx_free_trigger = (uint16_t)(rxq->rx_free_thresh - 1);
 166
 167         rxq->rx_tail = 0;
 168         rxq->nb_rx_hold = 0;
 169         rxq->pkt_first_seg = NULL;
 170         rxq->pkt_last_seg = NULL;
 171 }
 172
 173 static inline void
 174 reset_tx_queue(struct avf_tx_queue *txq)
 175 {
 176         struct avf_tx_entry *txe;
 177         uint16_t i, prev, size;
 178
 179         if (!txq) {
 180                 PMD_DRV_LOG(DEBUG, "Pointer to txq is NULL");
 181                 return;
 182         }
 183
 184         txe = txq->sw_ring;
 185         size = sizeof(struct avf_tx_desc) * txq->nb_tx_desc;
 186         for (i = 0; i < size; i++)
 187                 ((volatile char *)txq->tx_ring)[i] = 0;
 188
 189         prev = (uint16_t)(txq->nb_tx_desc - 1);
 190         for (i = 0; i < txq->nb_tx_desc; i++) {
 191                 txq->tx_ring[i].cmd_type_offset_bsz =
 192                         rte_cpu_to_le_64(AVF_TX_DESC_DTYPE_DESC_DONE);
 193                 txe[i].mbuf =  NULL;
 194                 txe[i].last_id = i;
 195                 txe[prev].next_id = i;
 196                 prev = i;
 197         }
 198
 199         txq->tx_tail = 0;
 200         txq->nb_used = 0;
 201
 202         txq->last_desc_cleaned = txq->nb_tx_desc - 1;
 203         txq->nb_free = txq->nb_tx_desc - 1;
 204
 205         txq->next_dd = txq->rs_thresh - 1;
 206         txq->next_rs = txq->rs_thresh - 1;
 207 }
 208
 209 static int
 210 alloc_rxq_mbufs(struct avf_rx_queue *rxq)
 211 {
 212         volatile union avf_rx_desc *rxd;
 213         struct rte_mbuf *mbuf = NULL;
 214         uint64_t dma_addr;
 215         uint16_t i;
 216
 217         for (i = 0; i < rxq->nb_rx_desc; i++) {
 218                 mbuf = rte_mbuf_raw_alloc(rxq->mp);
 219                 if (unlikely(!mbuf)) {
 220                         PMD_DRV_LOG(ERR, "Failed to allocate mbuf for RX");
 221                         return -ENOMEM;
 222                 }
 223
 224                 rte_mbuf_refcnt_set(mbuf, 1);
 225                 mbuf->next = NULL;
 226                 mbuf->data_off = RTE_PKTMBUF_HEADROOM;
 227                 mbuf->nb_segs = 1;
 228                 mbuf->port = rxq->port_id;
 229
 230                 dma_addr =
 231                         rte_cpu_to_le_64(rte_mbuf_data_iova_default(mbuf));
 232
 233                 rxd = &rxq->rx_ring[i];
 234                 rxd->read.pkt_addr = dma_addr;
 235                 rxd->read.hdr_addr = 0;
 236 #ifndef RTE_LIBRTE_AVF_16BYTE_RX_DESC
 237                 rxd->read.rsvd1 = 0;
 238                 rxd->read.rsvd2 = 0;
 239 #endif
 240
 241                 rxq->sw_ring[i] = mbuf;
 242         }
 243
 244         return 0;
 245 }
 246
 247 static inline void
 248 release_rxq_mbufs(struct avf_rx_queue *rxq)
 249 {
 250         struct rte_mbuf *mbuf;
 251         uint16_t i;
 252
 253         if (!rxq->sw_ring)
 254                 return;
 255
 256         for (i = 0; i < rxq->nb_rx_desc; i++) {
 257                 if (rxq->sw_ring[i]) {
 258                         rte_pktmbuf_free_seg(rxq->sw_ring[i]);
 259                         rxq->sw_ring[i] = NULL;
 260                 }
 261         }
 262
 263         /* for rx bulk */
 264         if (rxq->rx_nb_avail == 0)
 265                 return;
 266         for (i = 0; i < rxq->rx_nb_avail; i++) {
 267                 struct rte_mbuf *mbuf;
 268
 269                 mbuf = rxq->rx_stage[rxq->rx_next_avail + i];
 270                 rte_pktmbuf_free_seg(mbuf);
 271         }
 272         rxq->rx_nb_avail = 0;
 273 }
 274
 275 static inline void
 276 release_txq_mbufs(struct avf_tx_queue *txq)
 277 {
 278         uint16_t i;
 279
 280         if (!txq || !txq->sw_ring) {
 281                 PMD_DRV_LOG(DEBUG, "Pointer to rxq or sw_ring is NULL");
 282                 return;
 283         }
 284
 285         for (i = 0; i < txq->nb_tx_desc; i++) {
 286                 if (txq->sw_ring[i].mbuf) {
 287                         rte_pktmbuf_free_seg(txq->sw_ring[i].mbuf);
 288                         txq->sw_ring[i].mbuf = NULL;
 289                 }
 290         }
 291 }
 292
 293 static const struct avf_rxq_ops def_rxq_ops = {
 294         .release_mbufs = release_rxq_mbufs,
 295 };
 296
 297 static const struct avf_txq_ops def_txq_ops = {
 298         .release_mbufs = release_txq_mbufs,
 299 };
 300
 301 int
 302 avf_dev_rx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,
 303                        uint16_t nb_desc, unsigned int socket_id,
 304                        const struct rte_eth_rxconf *rx_conf,
 305                        struct rte_mempool *mp)
 306 {
 307         struct avf_hw *hw = AVF_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 308         struct avf_adapter *ad =
 309                 AVF_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
 310         struct avf_rx_queue *rxq;
 311         const struct rte_memzone *mz;
 312         uint32_t ring_size;
 313         uint16_t len, i;
 314         uint16_t rx_free_thresh;
 315         uint16_t base, bsf, tc_mapping;
 316
 317         PMD_INIT_FUNC_TRACE();
 318
 319         if (nb_desc % AVF_ALIGN_RING_DESC != 0 ||
 320             nb_desc > AVF_MAX_RING_DESC ||
 321             nb_desc < AVF_MIN_RING_DESC) {
 322                 PMD_INIT_LOG(ERR, "Number (%u) of receive descriptors is "
 323                              "invalid", nb_desc);
 324                 return -EINVAL;
 325         }
 326
 327         /* Check free threshold */
 328         rx_free_thresh = (rx_conf->rx_free_thresh == 0) ?
 329                          AVF_DEFAULT_RX_FREE_THRESH :
 330                          rx_conf->rx_free_thresh;
 331         if (check_rx_thresh(nb_desc, rx_free_thresh) != 0)
 332                 return -EINVAL;
 333
 334         /* Free memory if needed */
 335         if (dev->data->rx_queues[queue_idx]) {
 336                 avf_dev_rx_queue_release(dev->data->rx_queues[queue_idx]);
 337                 dev->data->rx_queues[queue_idx] = NULL;
 338         }
 339
 340         /* Allocate the rx queue data structure */
 341         rxq = rte_zmalloc_socket("avf rxq",
 342                                  sizeof(struct avf_rx_queue),
 343                                  RTE_CACHE_LINE_SIZE,
 344                                  socket_id);
 345         if (!rxq) {
 346                 PMD_INIT_LOG(ERR, "Failed to allocate memory for "
 347                              "rx queue data structure");
 348                 return -ENOMEM;
 349         }
 350
 351         rxq->mp = mp;
 352         rxq->nb_rx_desc = nb_desc;
 353         rxq->rx_free_thresh = rx_free_thresh;
 354         rxq->queue_id = queue_idx;
 355         rxq->port_id = dev->data->port_id;
 356         rxq->crc_len = 0; /* crc stripping by default */
 357         rxq->rx_deferred_start = rx_conf->rx_deferred_start;
 358         rxq->rx_hdr_len = 0;
 359
 360         len = rte_pktmbuf_data_room_size(rxq->mp) - RTE_PKTMBUF_HEADROOM;
 361         rxq->rx_buf_len = RTE_ALIGN(len, (1 << AVF_RXQ_CTX_DBUFF_SHIFT));
 362
 363         /* Allocate the software ring. */
 364         len = nb_desc + AVF_RX_MAX_BURST;
 365         rxq->sw_ring =
 366                 rte_zmalloc_socket("avf rx sw ring",
 367                                    sizeof(struct rte_mbuf *) * len,
 368                                    RTE_CACHE_LINE_SIZE,
 369                                    socket_id);
 370         if (!rxq->sw_ring) {
 371                 PMD_INIT_LOG(ERR, "Failed to allocate memory for SW ring");
 372                 rte_free(rxq);
 373                 return -ENOMEM;
 374         }
 375
 376         /* Allocate the maximun number of RX ring hardware descriptor with
 377          * a liitle more to support bulk allocate.
 378          */
 379         len = AVF_MAX_RING_DESC + AVF_RX_MAX_BURST;
 380         ring_size = RTE_ALIGN(len * sizeof(union avf_rx_desc),
 381                               AVF_DMA_MEM_ALIGN);
 382         mz = rte_eth_dma_zone_reserve(dev, "rx_ring", queue_idx,
 383                                       ring_size, AVF_RING_BASE_ALIGN,
 384                                       socket_id);
 385         if (!mz) {
 386                 PMD_INIT_LOG(ERR, "Failed to reserve DMA memory for RX");
 387                 rte_free(rxq->sw_ring);
 388                 rte_free(rxq);
 389                 return -ENOMEM;
 390         }
 391         /* Zero all the descriptors in the ring. */
 392         memset(mz->addr, 0, ring_size);
 393         rxq->rx_ring_phys_addr = mz->iova;
 394         rxq->rx_ring = (union avf_rx_desc *)mz->addr;
 395
 396         rxq->mz = mz;
 397         reset_rx_queue(rxq);
 398         rxq->q_set = TRUE;
 399         dev->data->rx_queues[queue_idx] = rxq;
 400         rxq->qrx_tail = hw->hw_addr + AVF_QRX_TAIL1(rxq->queue_id);
 401         rxq->ops = &def_rxq_ops;
 402
 403         if (check_rx_bulk_allow(rxq) == TRUE) {
 404                 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions are "
 405                              "satisfied. Rx Burst Bulk Alloc function will be "
 406                              "used on port=%d, queue=%d.",
 407                              rxq->port_id, rxq->queue_id);
 408         } else {
 409                 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions are "
 410                              "not satisfied, Scattered Rx is requested "
 411                              "on port=%d, queue=%d.",
 412                              rxq->port_id, rxq->queue_id);
 413                 ad->rx_bulk_alloc_allowed = false;
 414         }
 415
 416 #ifdef RTE_LIBRTE_AVF_INC_VECTOR
 417         if (check_rx_vec_allow(rxq) == FALSE)
 418                 ad->rx_vec_allowed = false;
 419 #endif
 420         return 0;
 421 }
 422
 423 int
 424 avf_dev_tx_queue_setup(struct rte_eth_dev *dev,
 425                        uint16_t queue_idx,
 426                        uint16_t nb_desc,
 427                        unsigned int socket_id,
 428                        const struct rte_eth_txconf *tx_conf)
 429 {
 430         struct avf_hw *hw = AVF_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 431         struct avf_adapter *ad =
 432                 AVF_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
 433         struct avf_tx_queue *txq;
 434         const struct rte_memzone *mz;
 435         uint32_t ring_size;
 436         uint16_t tx_rs_thresh, tx_free_thresh;
 437         uint16_t i, base, bsf, tc_mapping;
 438
 439         PMD_INIT_FUNC_TRACE();
 440
 441         if (nb_desc % AVF_ALIGN_RING_DESC != 0 ||
 442             nb_desc > AVF_MAX_RING_DESC ||
 443             nb_desc < AVF_MIN_RING_DESC) {
 444                 PMD_INIT_LOG(ERR, "Number (%u) of transmit descriptors is "
 445                             "invalid", nb_desc);
 446                 return -EINVAL;
 447         }
 448
 449         tx_rs_thresh = (uint16_t)((tx_conf->tx_rs_thresh) ?
 450                 tx_conf->tx_rs_thresh : DEFAULT_TX_RS_THRESH);
 451         tx_free_thresh = (uint16_t)((tx_conf->tx_free_thresh) ?
 452                 tx_conf->tx_free_thresh : DEFAULT_TX_FREE_THRESH);
 453         check_tx_thresh(nb_desc, tx_rs_thresh, tx_rs_thresh);
 454
 455         /* Free memory if needed. */
 456         if (dev->data->tx_queues[queue_idx]) {
 457                 avf_dev_tx_queue_release(dev->data->tx_queues[queue_idx]);
 458                 dev->data->tx_queues[queue_idx] = NULL;
 459         }
 460
 461         /* Allocate the TX queue data structure. */
 462         txq = rte_zmalloc_socket("avf txq",
 463                                  sizeof(struct avf_tx_queue),
 464                                  RTE_CACHE_LINE_SIZE,
 465                                  socket_id);
 466         if (!txq) {
 467                 PMD_INIT_LOG(ERR, "Failed to allocate memory for "
 468                              "tx queue structure");
 469                 return -ENOMEM;
 470         }
 471
 472         txq->nb_tx_desc = nb_desc;
 473         txq->rs_thresh = tx_rs_thresh;
 474         txq->free_thresh = tx_free_thresh;
 475         txq->queue_id = queue_idx;
 476         txq->port_id = dev->data->port_id;
 477         txq->txq_flags = tx_conf->txq_flags;
 478         txq->tx_deferred_start = tx_conf->tx_deferred_start;
 479
 480         /* Allocate software ring */
 481         txq->sw_ring =
 482                 rte_zmalloc_socket("avf tx sw ring",
 483                                    sizeof(struct avf_tx_entry) * nb_desc,
 484                                    RTE_CACHE_LINE_SIZE,
 485                                    socket_id);
 486         if (!txq->sw_ring) {
 487                 PMD_INIT_LOG(ERR, "Failed to allocate memory for SW TX ring");
 488                 rte_free(txq);
 489                 return -ENOMEM;
 490         }
 491
 492         /* Allocate TX hardware ring descriptors. */
 493         ring_size = sizeof(struct avf_tx_desc) * AVF_MAX_RING_DESC;
 494         ring_size = RTE_ALIGN(ring_size, AVF_DMA_MEM_ALIGN);
 495         mz = rte_eth_dma_zone_reserve(dev, "tx_ring", queue_idx,
 496                                       ring_size, AVF_RING_BASE_ALIGN,
 497                                       socket_id);
 498         if (!mz) {
 499                 PMD_INIT_LOG(ERR, "Failed to reserve DMA memory for TX");
 500                 rte_free(txq->sw_ring);
 501                 rte_free(txq);
 502                 return -ENOMEM;
 503         }
 504         txq->tx_ring_phys_addr = mz->iova;
 505         txq->tx_ring = (struct avf_tx_desc *)mz->addr;
 506
 507         txq->mz = mz;
 508         reset_tx_queue(txq);
 509         txq->q_set = TRUE;
 510         dev->data->tx_queues[queue_idx] = txq;
 511         txq->qtx_tail = hw->hw_addr + AVF_QTX_TAIL1(queue_idx);
 512         txq->ops = &def_txq_ops;
 513
 514 #ifdef RTE_LIBRTE_AVF_INC_VECTOR
 515         if (check_tx_vec_allow(txq) == FALSE)
 516                 ad->tx_vec_allowed = false;
 517 #endif
 518
 519         return 0;
 520 }
 521
 522 int
 523 avf_dev_rx_queue_start(struct rte_eth_dev *dev, uint16_t rx_queue_id)
 524 {
 525         struct avf_adapter *adapter =
 526                 AVF_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
 527         struct avf_hw *hw = AVF_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 528         struct avf_rx_queue *rxq;
 529         int err = 0;
 530
 531         PMD_DRV_FUNC_TRACE();
 532
 533         if (rx_queue_id >= dev->data->nb_rx_queues)
 534                 return -EINVAL;
 535
 536         rxq = dev->data->rx_queues[rx_queue_id];
 537
 538         err = alloc_rxq_mbufs(rxq);
 539         if (err) {
 540                 PMD_DRV_LOG(ERR, "Failed to allocate RX queue mbuf");
 541                 return err;
 542         }
 543
 544         rte_wmb();
 545
 546         /* Init the RX tail register. */
 547         AVF_PCI_REG_WRITE(rxq->qrx_tail, rxq->nb_rx_desc - 1);
 548         AVF_WRITE_FLUSH(hw);
 549
 550         /* Ready to switch the queue on */
 551         err = avf_switch_queue(adapter, rx_queue_id, TRUE, TRUE);
 552         if (err)
 553                 PMD_DRV_LOG(ERR, "Failed to switch RX queue %u on",
 554                             rx_queue_id);
 555         else
 556                 dev->data->rx_queue_state[rx_queue_id] =
 557                         RTE_ETH_QUEUE_STATE_STARTED;
 558
 559         return err;
 560 }
 561
 562 int
 563 avf_dev_tx_queue_start(struct rte_eth_dev *dev, uint16_t tx_queue_id)
 564 {
 565         struct avf_adapter *adapter =
 566                 AVF_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
 567         struct avf_hw *hw = AVF_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 568         struct avf_tx_queue *txq;
 569         int err = 0;
 570
 571         PMD_DRV_FUNC_TRACE();
 572
 573         if (tx_queue_id >= dev->data->nb_tx_queues)
 574                 return -EINVAL;
 575
 576         txq = dev->data->tx_queues[tx_queue_id];
 577
 578         /* Init the RX tail register. */
 579         AVF_PCI_REG_WRITE(txq->qtx_tail, 0);
 580         AVF_WRITE_FLUSH(hw);
 581
 582         /* Ready to switch the queue on */
 583         err = avf_switch_queue(adapter, tx_queue_id, FALSE, TRUE);
 584
 585         if (err)
 586                 PMD_DRV_LOG(ERR, "Failed to switch TX queue %u on",
 587                             tx_queue_id);
 588         else
 589                 dev->data->tx_queue_state[tx_queue_id] =
 590                         RTE_ETH_QUEUE_STATE_STARTED;
 591
 592         return err;
 593 }
 594
 595 int
 596 avf_dev_rx_queue_stop(struct rte_eth_dev *dev, uint16_t rx_queue_id)
 597 {
 598         struct avf_adapter *adapter =
 599                 AVF_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
 600         struct avf_rx_queue *rxq;
 601         int err;
 602
 603         PMD_DRV_FUNC_TRACE();
 604
 605         if (rx_queue_id >= dev->data->nb_rx_queues)
 606                 return -EINVAL;
 607
 608         err = avf_switch_queue(adapter, rx_queue_id, TRUE, FALSE);
 609         if (err) {
 610                 PMD_DRV_LOG(ERR, "Failed to switch RX queue %u off",
 611                             rx_queue_id);
 612                 return err;
 613         }
 614
 615         rxq = dev->data->rx_queues[rx_queue_id];
 616         rxq->ops->release_mbufs(rxq);
 617         reset_rx_queue(rxq);
 618         dev->data->rx_queue_state[rx_queue_id] = RTE_ETH_QUEUE_STATE_STOPPED;
 619
 620         return 0;
 621 }
 622
 623 int
 624 avf_dev_tx_queue_stop(struct rte_eth_dev *dev, uint16_t tx_queue_id)
 625 {
 626         struct avf_adapter *adapter =
 627                 AVF_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
 628         struct avf_tx_queue *txq;
 629         int err;
 630
 631         PMD_DRV_FUNC_TRACE();
 632
 633         if (tx_queue_id >= dev->data->nb_tx_queues)
 634                 return -EINVAL;
 635
 636         err = avf_switch_queue(adapter, tx_queue_id, FALSE, FALSE);
 637         if (err) {
 638                 PMD_DRV_LOG(ERR, "Failed to switch TX queue %u off",
 639                             tx_queue_id);
 640                 return err;
 641         }
 642
 643         txq = dev->data->tx_queues[tx_queue_id];
 644         txq->ops->release_mbufs(txq);
 645         reset_tx_queue(txq);
 646         dev->data->tx_queue_state[tx_queue_id] = RTE_ETH_QUEUE_STATE_STOPPED;
 647
 648         return 0;
 649 }
 650
 651 void
 652 avf_dev_rx_queue_release(void *rxq)
 653 {
 654         struct avf_rx_queue *q = (struct avf_rx_queue *)rxq;
 655
 656         if (!q)
 657                 return;
 658
 659         q->ops->release_mbufs(q);
 660         rte_free(q->sw_ring);
 661         rte_memzone_free(q->mz);
 662         rte_free(q);
 663 }
 664
 665 void
 666 avf_dev_tx_queue_release(void *txq)
 667 {
 668         struct avf_tx_queue *q = (struct avf_tx_queue *)txq;
 669
 670         if (!q)
 671                 return;
 672
 673         q->ops->release_mbufs(q);
 674         rte_free(q->sw_ring);
 675         rte_memzone_free(q->mz);
 676         rte_free(q);
 677 }
 678
 679 void
 680 avf_stop_queues(struct rte_eth_dev *dev)
 681 {
 682         struct avf_adapter *adapter =
 683                 AVF_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
 684         struct avf_rx_queue *rxq;
 685         struct avf_tx_queue *txq;
 686         int ret, i;
 687
 688         /* Stop All queues */
 689         ret = avf_disable_queues(adapter);
 690         if (ret)
 691                 PMD_DRV_LOG(WARNING, "Fail to stop queues");
 692
 693         for (i = 0; i < dev->data->nb_tx_queues; i++) {
 694                 txq = dev->data->tx_queues[i];
 695                 if (!txq)
 696                         continue;
 697                 txq->ops->release_mbufs(txq);
 698                 reset_tx_queue(txq);
 699                 dev->data->tx_queue_state[i] = RTE_ETH_QUEUE_STATE_STOPPED;
 700         }
 701         for (i = 0; i < dev->data->nb_rx_queues; i++) {
 702                 rxq = dev->data->rx_queues[i];
 703                 if (!rxq)
 704                         continue;
 705                 rxq->ops->release_mbufs(rxq);
 706                 reset_rx_queue(rxq);
 707                 dev->data->rx_queue_state[i] = RTE_ETH_QUEUE_STATE_STOPPED;
 708         }
 709 }
 710
 711 static inline void
 712 avf_rxd_to_vlan_tci(struct rte_mbuf *mb, volatile union avf_rx_desc *rxdp)
 713 {
 714         if (rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len) &
 715                 (1 << AVF_RX_DESC_STATUS_L2TAG1P_SHIFT)) {
 716                 mb->ol_flags |= PKT_RX_VLAN | PKT_RX_VLAN_STRIPPED;
 717                 mb->vlan_tci =
 718                         rte_le_to_cpu_16(rxdp->wb.qword0.lo_dword.l2tag1);
 719         } else {
 720                 mb->vlan_tci = 0;
 721         }
 722 }
 723
 724 /* Translate the rx descriptor status and error fields to pkt flags */
 725 static inline uint64_t
 726 avf_rxd_to_pkt_flags(uint64_t qword)
 727 {
 728         uint64_t flags;
 729         uint64_t error_bits = (qword >> AVF_RXD_QW1_ERROR_SHIFT);
 730
 731 #define AVF_RX_ERR_BITS 0x3f
 732
 733         /* Check if RSS_HASH */
 734         flags = (((qword >> AVF_RX_DESC_STATUS_FLTSTAT_SHIFT) &
 735                                         AVF_RX_DESC_FLTSTAT_RSS_HASH) ==
 736                         AVF_RX_DESC_FLTSTAT_RSS_HASH) ? PKT_RX_RSS_HASH : 0;
 737
 738         if (likely((error_bits & AVF_RX_ERR_BITS) == 0)) {
 739                 flags |= (PKT_RX_IP_CKSUM_GOOD | PKT_RX_L4_CKSUM_GOOD);
 740                 return flags;
 741         }
 742
 743         if (unlikely(error_bits & (1 << AVF_RX_DESC_ERROR_IPE_SHIFT)))
 744                 flags |= PKT_RX_IP_CKSUM_BAD;
 745         else
 746                 flags |= PKT_RX_IP_CKSUM_GOOD;
 747
 748         if (unlikely(error_bits & (1 << AVF_RX_DESC_ERROR_L4E_SHIFT)))
 749                 flags |= PKT_RX_L4_CKSUM_BAD;
 750         else
 751                 flags |= PKT_RX_L4_CKSUM_GOOD;
 752
 753         /* TODO: Oversize error bit is not processed here */
 754
 755         return flags;
 756 }
 757
 758 /* implement recv_pkts */
 759 uint16_t
 760 avf_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t nb_pkts)
 761 {
 762         volatile union avf_rx_desc *rx_ring;
 763         volatile union avf_rx_desc *rxdp;
 764         struct avf_rx_queue *rxq;
 765         union avf_rx_desc rxd;
 766         struct rte_mbuf *rxe;
 767         struct rte_eth_dev *dev;
 768         struct rte_mbuf *rxm;
 769         struct rte_mbuf *nmb;
 770         uint16_t nb_rx;
 771         uint32_t rx_status;
 772         uint64_t qword1;
 773         uint16_t rx_packet_len;
 774         uint16_t rx_id, nb_hold;
 775         uint64_t dma_addr;
 776         uint64_t pkt_flags;
 777         static const uint32_t ptype_tbl[UINT8_MAX + 1] __rte_cache_aligned = {
 778                 /* [0] reserved */
 779                 [1] = RTE_PTYPE_L2_ETHER,
 780                 /* [2] - [21] reserved */
 781                 [22] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 782                         RTE_PTYPE_L4_FRAG,
 783                 [23] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 784                         RTE_PTYPE_L4_NONFRAG,
 785                 [24] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 786                         RTE_PTYPE_L4_UDP,
 787                 /* [25] reserved */
 788                 [26] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 789                         RTE_PTYPE_L4_TCP,
 790                 [27] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 791                         RTE_PTYPE_L4_SCTP,
 792                 [28] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 793                         RTE_PTYPE_L4_ICMP,
 794                 /* All others reserved */
 795         };
 796
 797         nb_rx = 0;
 798         nb_hold = 0;
 799         rxq = rx_queue;
 800         rx_id = rxq->rx_tail;
 801         rx_ring = rxq->rx_ring;
 802
 803         while (nb_rx < nb_pkts) {
 804                 rxdp = &rx_ring[rx_id];
 805                 qword1 = rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len);
 806                 rx_status = (qword1 & AVF_RXD_QW1_STATUS_MASK) >>
 807                             AVF_RXD_QW1_STATUS_SHIFT;
 808
 809                 /* Check the DD bit first */
 810                 if (!(rx_status & (1 << AVF_RX_DESC_STATUS_DD_SHIFT)))
 811                         break;
 812                 AVF_DUMP_RX_DESC(rxq, rxdp, rx_id);
 813
 814                 nmb = rte_mbuf_raw_alloc(rxq->mp);
 815                 if (unlikely(!nmb)) {
 816                         dev = &rte_eth_devices[rxq->port_id];
 817                         dev->data->rx_mbuf_alloc_failed++;
 818                         PMD_RX_LOG(DEBUG, "RX mbuf alloc failed port_id=%u "
 819                                    "queue_id=%u", rxq->port_id, rxq->queue_id);
 820                         break;
 821                 }
 822
 823                 rxd = *rxdp;
 824                 nb_hold++;
 825                 rxe = rxq->sw_ring[rx_id];
 826                 rx_id++;
 827                 if (unlikely(rx_id == rxq->nb_rx_desc))
 828                         rx_id = 0;
 829
 830                 /* Prefetch next mbuf */
 831                 rte_prefetch0(rxq->sw_ring[rx_id]);
 832
 833                 /* When next RX descriptor is on a cache line boundary,
 834                  * prefetch the next 4 RX descriptors and next 8 pointers
 835                  * to mbufs.
 836                  */
 837                 if ((rx_id & 0x3) == 0) {
 838                         rte_prefetch0(&rx_ring[rx_id]);
 839                         rte_prefetch0(rxq->sw_ring[rx_id]);
 840                 }
 841                 rxm = rxe;
 842                 rxe = nmb;
 843                 dma_addr =
 844                         rte_cpu_to_le_64(rte_mbuf_data_iova_default(nmb));
 845                 rxdp->read.hdr_addr = 0;
 846                 rxdp->read.pkt_addr = dma_addr;
 847
 848                 rx_packet_len = ((qword1 & AVF_RXD_QW1_LENGTH_PBUF_MASK) >>
 849                                 AVF_RXD_QW1_LENGTH_PBUF_SHIFT) - rxq->crc_len;
 850
 851                 rxm->data_off = RTE_PKTMBUF_HEADROOM;
 852                 rte_prefetch0(RTE_PTR_ADD(rxm->buf_addr, RTE_PKTMBUF_HEADROOM));
 853                 rxm->nb_segs = 1;
 854                 rxm->next = NULL;
 855                 rxm->pkt_len = rx_packet_len;
 856                 rxm->data_len = rx_packet_len;
 857                 rxm->port = rxq->port_id;
 858                 rxm->ol_flags = 0;
 859                 avf_rxd_to_vlan_tci(rxm, &rxd);
 860                 pkt_flags = avf_rxd_to_pkt_flags(qword1);
 861                 rxm->packet_type =
 862                         ptype_tbl[(uint8_t)((qword1 &
 863                         AVF_RXD_QW1_PTYPE_MASK) >> AVF_RXD_QW1_PTYPE_SHIFT)];
 864
 865                 if (pkt_flags & PKT_RX_RSS_HASH)
 866                         rxm->hash.rss =
 867                                 rte_le_to_cpu_32(rxd.wb.qword0.hi_dword.rss);
 868
 869                 rxm->ol_flags |= pkt_flags;
 870
 871                 rx_pkts[nb_rx++] = rxm;
 872         }
 873         rxq->rx_tail = rx_id;
 874
 875         /* If the number of free RX descriptors is greater than the RX free
 876          * threshold of the queue, advance the receive tail register of queue.
 877          * Update that register with the value of the last processed RX
 878          * descriptor minus 1.
 879          */
 880         nb_hold = (uint16_t)(nb_hold + rxq->nb_rx_hold);
 881         if (nb_hold > rxq->rx_free_thresh) {
 882                 PMD_RX_LOG(DEBUG, "port_id=%u queue_id=%u rx_tail=%u "
 883                            "nb_hold=%u nb_rx=%u",
 884                            rxq->port_id, rxq->queue_id,
 885                            rx_id, nb_hold, nb_rx);
 886                 rx_id = (uint16_t)((rx_id == 0) ?
 887                         (rxq->nb_rx_desc - 1) : (rx_id - 1));
 888                 AVF_PCI_REG_WRITE(rxq->qrx_tail, rx_id);
 889                 nb_hold = 0;
 890         }
 891         rxq->nb_rx_hold = nb_hold;
 892
 893         return nb_rx;
 894 }
 895
 896 /* implement recv_scattered_pkts  */
 897 uint16_t
 898 avf_recv_scattered_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,
 899                         uint16_t nb_pkts)
 900 {
 901         struct avf_rx_queue *rxq = rx_queue;
 902         union avf_rx_desc rxd;
 903         struct rte_mbuf *rxe;
 904         struct rte_mbuf *first_seg = rxq->pkt_first_seg;
 905         struct rte_mbuf *last_seg = rxq->pkt_last_seg;
 906         struct rte_mbuf *nmb, *rxm;
 907         uint16_t rx_id = rxq->rx_tail;
 908         uint16_t nb_rx = 0, nb_hold = 0, rx_packet_len;
 909         struct rte_eth_dev *dev;
 910         uint32_t rx_status;
 911         uint64_t qword1;
 912         uint64_t dma_addr;
 913         uint64_t pkt_flags;
 914
 915         volatile union avf_rx_desc *rx_ring = rxq->rx_ring;
 916         volatile union avf_rx_desc *rxdp;
 917         static const uint32_t ptype_tbl[UINT8_MAX + 1] __rte_cache_aligned = {
 918                 /* [0] reserved */
 919                 [1] = RTE_PTYPE_L2_ETHER,
 920                 /* [2] - [21] reserved */
 921                 [22] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 922                         RTE_PTYPE_L4_FRAG,
 923                 [23] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 924                         RTE_PTYPE_L4_NONFRAG,
 925                 [24] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 926                         RTE_PTYPE_L4_UDP,
 927                 /* [25] reserved */
 928                 [26] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 929                         RTE_PTYPE_L4_TCP,
 930                 [27] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 931                         RTE_PTYPE_L4_SCTP,
 932                 [28] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 933                         RTE_PTYPE_L4_ICMP,
 934                 /* All others reserved */
 935         };
 936
 937         while (nb_rx < nb_pkts) {
 938                 rxdp = &rx_ring[rx_id];
 939                 qword1 = rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len);
 940                 rx_status = (qword1 & AVF_RXD_QW1_STATUS_MASK) >>
 941                             AVF_RXD_QW1_STATUS_SHIFT;
 942
 943                 /* Check the DD bit */
 944                 if (!(rx_status & (1 << AVF_RX_DESC_STATUS_DD_SHIFT)))
 945                         break;
 946                 AVF_DUMP_RX_DESC(rxq, rxdp, rx_id);
 947
 948                 nmb = rte_mbuf_raw_alloc(rxq->mp);
 949                 if (unlikely(!nmb)) {
 950                         PMD_RX_LOG(DEBUG, "RX mbuf alloc failed port_id=%u "
 951                                    "queue_id=%u", rxq->port_id, rxq->queue_id);
 952                         dev = &rte_eth_devices[rxq->port_id];
 953                         dev->data->rx_mbuf_alloc_failed++;
 954                         break;
 955                 }
 956
 957                 rxd = *rxdp;
 958                 nb_hold++;
 959                 rxe = rxq->sw_ring[rx_id];
 960                 rx_id++;
 961                 if (rx_id == rxq->nb_rx_desc)
 962                         rx_id = 0;
 963
 964                 /* Prefetch next mbuf */
 965                 rte_prefetch0(rxq->sw_ring[rx_id]);
 966
 967                 /* When next RX descriptor is on a cache line boundary,
 968                  * prefetch the next 4 RX descriptors and next 8 pointers
 969                  * to mbufs.
 970                  */
 971                 if ((rx_id & 0x3) == 0) {
 972                         rte_prefetch0(&rx_ring[rx_id]);
 973                         rte_prefetch0(rxq->sw_ring[rx_id]);
 974                 }
 975
 976                 rxm = rxe;
 977                 rxe = nmb;
 978                 dma_addr =
 979                         rte_cpu_to_le_64(rte_mbuf_data_iova_default(nmb));
 980
 981                 /* Set data buffer address and data length of the mbuf */
 982                 rxdp->read.hdr_addr = 0;
 983                 rxdp->read.pkt_addr = dma_addr;
 984                 rx_packet_len = (qword1 & AVF_RXD_QW1_LENGTH_PBUF_MASK) >>
 985                                  AVF_RXD_QW1_LENGTH_PBUF_SHIFT;
 986                 rxm->data_len = rx_packet_len;
 987                 rxm->data_off = RTE_PKTMBUF_HEADROOM;
 988
 989                 /* If this is the first buffer of the received packet, set the
 990                  * pointer to the first mbuf of the packet and initialize its
 991                  * context. Otherwise, update the total length and the number
 992                  * of segments of the current scattered packet, and update the
 993                  * pointer to the last mbuf of the current packet.
 994                  */
 995                 if (!first_seg) {
 996                         first_seg = rxm;
 997                         first_seg->nb_segs = 1;
 998                         first_seg->pkt_len = rx_packet_len;
 999                 } else {
1000                         first_seg->pkt_len =
1001                                 (uint16_t)(first_seg->pkt_len +
1002                                                 rx_packet_len);
1003                         first_seg->nb_segs++;
1004                         last_seg->next = rxm;
1005                 }
1006
1007                 /* If this is not the last buffer of the received packet,
1008                  * update the pointer to the last mbuf of the current scattered
1009                  * packet and continue to parse the RX ring.
1010                  */
1011                 if (!(rx_status & (1 << AVF_RX_DESC_STATUS_EOF_SHIFT))) {
1012                         last_seg = rxm;
1013                         continue;
1014                 }
1015
1016                 /* This is the last buffer of the received packet. If the CRC
1017                  * is not stripped by the hardware:
1018                  *  - Subtract the CRC length from the total packet length.
1019                  *  - If the last buffer only contains the whole CRC or a part
1020                  *  of it, free the mbuf associated to the last buffer. If part
1021                  *  of the CRC is also contained in the previous mbuf, subtract
1022                  *  the length of that CRC part from the data length of the
1023                  *  previous mbuf.
1024                  */
1025                 rxm->next = NULL;
1026                 if (unlikely(rxq->crc_len > 0)) {
1027                         first_seg->pkt_len -= ETHER_CRC_LEN;
1028                         if (rx_packet_len <= ETHER_CRC_LEN) {
1029                                 rte_pktmbuf_free_seg(rxm);
1030                                 first_seg->nb_segs--;
1031                                 last_seg->data_len =
1032                                         (uint16_t)(last_seg->data_len -
1033                                         (ETHER_CRC_LEN - rx_packet_len));
1034                                 last_seg->next = NULL;
1035                         } else
1036                                 rxm->data_len = (uint16_t)(rx_packet_len -
1037                                                                 ETHER_CRC_LEN);
1038                 }
1039
1040                 first_seg->port = rxq->port_id;
1041                 first_seg->ol_flags = 0;
1042                 avf_rxd_to_vlan_tci(first_seg, &rxd);
1043                 pkt_flags = avf_rxd_to_pkt_flags(qword1);
1044                 first_seg->packet_type =
1045                         ptype_tbl[(uint8_t)((qword1 &
1046                         AVF_RXD_QW1_PTYPE_MASK) >> AVF_RXD_QW1_PTYPE_SHIFT)];
1047
1048                 if (pkt_flags & PKT_RX_RSS_HASH)
1049                         first_seg->hash.rss =
1050                                 rte_le_to_cpu_32(rxd.wb.qword0.hi_dword.rss);
1051
1052                 first_seg->ol_flags |= pkt_flags;
1053
1054                 /* Prefetch data of first segment, if configured to do so. */
1055                 rte_prefetch0(RTE_PTR_ADD(first_seg->buf_addr,
1056                                           first_seg->data_off));
1057                 rx_pkts[nb_rx++] = first_seg;
1058                 first_seg = NULL;
1059         }
1060
1061         /* Record index of the next RX descriptor to probe. */
1062         rxq->rx_tail = rx_id;
1063         rxq->pkt_first_seg = first_seg;
1064         rxq->pkt_last_seg = last_seg;
1065
1066         /* If the number of free RX descriptors is greater than the RX free
1067          * threshold of the queue, advance the Receive Descriptor Tail (RDT)
1068          * register. Update the RDT with the value of the last processed RX
1069          * descriptor minus 1, to guarantee that the RDT register is never
1070          * equal to the RDH register, which creates a "full" ring situtation
1071          * from the hardware point of view.
1072          */
1073         nb_hold = (uint16_t)(nb_hold + rxq->nb_rx_hold);
1074         if (nb_hold > rxq->rx_free_thresh) {
1075                 PMD_RX_LOG(DEBUG, "port_id=%u queue_id=%u rx_tail=%u "
1076                            "nb_hold=%u nb_rx=%u",
1077                            rxq->port_id, rxq->queue_id,
1078                            rx_id, nb_hold, nb_rx);
1079                 rx_id = (uint16_t)(rx_id == 0 ?
1080                         (rxq->nb_rx_desc - 1) : (rx_id - 1));
1081                 AVF_PCI_REG_WRITE(rxq->qrx_tail, rx_id);
1082                 nb_hold = 0;
1083         }
1084         rxq->nb_rx_hold = nb_hold;
1085
1086         return nb_rx;
1087 }
1088
1089 #define AVF_LOOK_AHEAD 8
1090 static inline int
1091 avf_rx_scan_hw_ring(struct avf_rx_queue *rxq)
1092 {
1093         volatile union avf_rx_desc *rxdp;
1094         struct rte_mbuf **rxep;
1095         struct rte_mbuf *mb;
1096         uint16_t pkt_len;
1097         uint64_t qword1;
1098         uint32_t rx_status;
1099         int32_t s[AVF_LOOK_AHEAD], nb_dd;
1100         int32_t i, j, nb_rx = 0;
1101         uint64_t pkt_flags;
1102         static const uint32_t ptype_tbl[UINT8_MAX + 1] __rte_cache_aligned = {
1103                 /* [0] reserved */
1104                 [1] = RTE_PTYPE_L2_ETHER,
1105                 /* [2] - [21] reserved */
1106                 [22] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
1107                         RTE_PTYPE_L4_FRAG,
1108                 [23] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
1109                         RTE_PTYPE_L4_NONFRAG,
1110                 [24] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
1111                         RTE_PTYPE_L4_UDP,
1112                 /* [25] reserved */
1113                 [26] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
1114                         RTE_PTYPE_L4_TCP,
1115                 [27] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
1116                         RTE_PTYPE_L4_SCTP,
1117                 [28] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
1118                         RTE_PTYPE_L4_ICMP,
1119                 /* All others reserved */
1120         };
1121
1122         rxdp = &rxq->rx_ring[rxq->rx_tail];
1123         rxep = &rxq->sw_ring[rxq->rx_tail];
1124
1125         qword1 = rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len);
1126         rx_status = (qword1 & AVF_RXD_QW1_STATUS_MASK) >>
1127                     AVF_RXD_QW1_STATUS_SHIFT;
1128
1129         /* Make sure there is at least 1 packet to receive */
1130         if (!(rx_status & (1 << AVF_RX_DESC_STATUS_DD_SHIFT)))
1131                 return 0;
1132
1133         /* Scan LOOK_AHEAD descriptors at a time to determine which
1134          * descriptors reference packets that are ready to be received.
1135          */
1136         for (i = 0; i < AVF_RX_MAX_BURST; i += AVF_LOOK_AHEAD,
1137              rxdp += AVF_LOOK_AHEAD, rxep += AVF_LOOK_AHEAD) {
1138                 /* Read desc statuses backwards to avoid race condition */
1139                 for (j = AVF_LOOK_AHEAD - 1; j >= 0; j--) {
1140                         qword1 = rte_le_to_cpu_64(
1141                                 rxdp[j].wb.qword1.status_error_len);
1142                         s[j] = (qword1 & AVF_RXD_QW1_STATUS_MASK) >>
1143                                AVF_RXD_QW1_STATUS_SHIFT;
1144                 }
1145
1146                 rte_smp_rmb();
1147
1148                 /* Compute how many status bits were set */
1149                 for (j = 0, nb_dd = 0; j < AVF_LOOK_AHEAD; j++)
1150                         nb_dd += s[j] & (1 << AVF_RX_DESC_STATUS_DD_SHIFT);
1151
1152                 nb_rx += nb_dd;
1153
1154                 /* Translate descriptor info to mbuf parameters */
1155                 for (j = 0; j < nb_dd; j++) {
1156                         AVF_DUMP_RX_DESC(rxq, &rxdp[j],
1157                                          rxq->rx_tail + i * AVF_LOOK_AHEAD + j);
1158
1159                         mb = rxep[j];
1160                         qword1 = rte_le_to_cpu_64
1161                                         (rxdp[j].wb.qword1.status_error_len);
1162                         pkt_len = ((qword1 & AVF_RXD_QW1_LENGTH_PBUF_MASK) >>
1163                                   AVF_RXD_QW1_LENGTH_PBUF_SHIFT) - rxq->crc_len;
1164                         mb->data_len = pkt_len;
1165                         mb->pkt_len = pkt_len;
1166                         mb->ol_flags = 0;
1167                         avf_rxd_to_vlan_tci(mb, &rxdp[j]);
1168                         pkt_flags = avf_rxd_to_pkt_flags(qword1);
1169                         mb->packet_type =
1170                                 ptype_tbl[(uint8_t)((qword1 &
1171                                 AVF_RXD_QW1_PTYPE_MASK) >>
1172                                 AVF_RXD_QW1_PTYPE_SHIFT)];
1173
1174                         if (pkt_flags & PKT_RX_RSS_HASH)
1175                                 mb->hash.rss = rte_le_to_cpu_32(
1176                                         rxdp[j].wb.qword0.hi_dword.rss);
1177
1178                         mb->ol_flags |= pkt_flags;
1179                 }
1180
1181                 for (j = 0; j < AVF_LOOK_AHEAD; j++)
1182                         rxq->rx_stage[i + j] = rxep[j];
1183
1184                 if (nb_dd != AVF_LOOK_AHEAD)
1185                         break;
1186         }
1187
1188         /* Clear software ring entries */
1189         for (i = 0; i < nb_rx; i++)
1190                 rxq->sw_ring[rxq->rx_tail + i] = NULL;
1191
1192         return nb_rx;
1193 }
1194
1195 static inline uint16_t
1196 avf_rx_fill_from_stage(struct avf_rx_queue *rxq,
1197                        struct rte_mbuf **rx_pkts,
1198                        uint16_t nb_pkts)
1199 {
1200         uint16_t i;
1201         struct rte_mbuf **stage = &rxq->rx_stage[rxq->rx_next_avail];
1202
1203         nb_pkts = (uint16_t)RTE_MIN(nb_pkts, rxq->rx_nb_avail);
1204
1205         for (i = 0; i < nb_pkts; i++)
1206                 rx_pkts[i] = stage[i];
1207
1208         rxq->rx_nb_avail = (uint16_t)(rxq->rx_nb_avail - nb_pkts);
1209         rxq->rx_next_avail = (uint16_t)(rxq->rx_next_avail + nb_pkts);
1210
1211         return nb_pkts;
1212 }
1213
1214 static inline int
1215 avf_rx_alloc_bufs(struct avf_rx_queue *rxq)
1216 {
1217         volatile union avf_rx_desc *rxdp;
1218         struct rte_mbuf **rxep;
1219         struct rte_mbuf *mb;
1220         uint16_t alloc_idx, i;
1221         uint64_t dma_addr;
1222         int diag;
1223
1224         /* Allocate buffers in bulk */
1225         alloc_idx = (uint16_t)(rxq->rx_free_trigger -
1226                                 (rxq->rx_free_thresh - 1));
1227         rxep = &rxq->sw_ring[alloc_idx];
1228         diag = rte_mempool_get_bulk(rxq->mp, (void *)rxep,
1229                                     rxq->rx_free_thresh);
1230         if (unlikely(diag != 0)) {
1231                 PMD_RX_LOG(ERR, "Failed to get mbufs in bulk");
1232                 return -ENOMEM;
1233         }
1234
1235         rxdp = &rxq->rx_ring[alloc_idx];
1236         for (i = 0; i < rxq->rx_free_thresh; i++) {
1237                 if (likely(i < (rxq->rx_free_thresh - 1)))
1238                         /* Prefetch next mbuf */
1239                         rte_prefetch0(rxep[i + 1]);
1240
1241                 mb = rxep[i];
1242                 rte_mbuf_refcnt_set(mb, 1);
1243                 mb->next = NULL;
1244                 mb->data_off = RTE_PKTMBUF_HEADROOM;
1245                 mb->nb_segs = 1;
1246                 mb->port = rxq->port_id;
1247                 dma_addr = rte_cpu_to_le_64(rte_mbuf_data_iova_default(mb));
1248                 rxdp[i].read.hdr_addr = 0;
1249                 rxdp[i].read.pkt_addr = dma_addr;
1250         }
1251
1252         /* Update rx tail register */
1253         rte_wmb();
1254         AVF_PCI_REG_WRITE_RELAXED(rxq->qrx_tail, rxq->rx_free_trigger);
1255
1256         rxq->rx_free_trigger =
1257                 (uint16_t)(rxq->rx_free_trigger + rxq->rx_free_thresh);
1258         if (rxq->rx_free_trigger >= rxq->nb_rx_desc)
1259                 rxq->rx_free_trigger = (uint16_t)(rxq->rx_free_thresh - 1);
1260
1261         return 0;
1262 }
1263
1264 static inline uint16_t
1265 rx_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t nb_pkts)
1266 {
1267         struct avf_rx_queue *rxq = (struct avf_rx_queue *)rx_queue;
1268         struct rte_eth_dev *dev;
1269         uint16_t nb_rx = 0;
1270
1271         if (!nb_pkts)
1272                 return 0;
1273
1274         if (rxq->rx_nb_avail)
1275                 return avf_rx_fill_from_stage(rxq, rx_pkts, nb_pkts);
1276
1277         nb_rx = (uint16_t)avf_rx_scan_hw_ring(rxq);
1278         rxq->rx_next_avail = 0;
1279         rxq->rx_nb_avail = nb_rx;
1280         rxq->rx_tail = (uint16_t)(rxq->rx_tail + nb_rx);
1281
1282         if (rxq->rx_tail > rxq->rx_free_trigger) {
1283                 if (avf_rx_alloc_bufs(rxq) != 0) {
1284                         uint16_t i, j;
1285
1286                         /* TODO: count rx_mbuf_alloc_failed here */
1287
1288                         rxq->rx_nb_avail = 0;
1289                         rxq->rx_tail = (uint16_t)(rxq->rx_tail - nb_rx);
1290                         for (i = 0, j = rxq->rx_tail; i < nb_rx; i++, j++)
1291                                 rxq->sw_ring[j] = rxq->rx_stage[i];
1292
1293                         return 0;
1294                 }
1295         }
1296
1297         if (rxq->rx_tail >= rxq->nb_rx_desc)
1298                 rxq->rx_tail = 0;
1299
1300         PMD_RX_LOG(DEBUG, "port_id=%u queue_id=%u rx_tail=%u, nb_rx=%u",
1301                    rxq->port_id, rxq->queue_id,
1302                    rxq->rx_tail, nb_rx);
1303
1304         if (rxq->rx_nb_avail)
1305                 return avf_rx_fill_from_stage(rxq, rx_pkts, nb_pkts);
1306
1307         return 0;
1308 }
1309
1310 static uint16_t
1311 avf_recv_pkts_bulk_alloc(void *rx_queue,
1312                          struct rte_mbuf **rx_pkts,
1313                          uint16_t nb_pkts)
1314 {
1315         uint16_t nb_rx = 0, n, count;
1316
1317         if (unlikely(nb_pkts == 0))
1318                 return 0;
1319
1320         if (likely(nb_pkts <= AVF_RX_MAX_BURST))
1321                 return rx_recv_pkts(rx_queue, rx_pkts, nb_pkts);
1322
1323         while (nb_pkts) {
1324                 n = RTE_MIN(nb_pkts, AVF_RX_MAX_BURST);
1325                 count = rx_recv_pkts(rx_queue, &rx_pkts[nb_rx], n);
1326                 nb_rx = (uint16_t)(nb_rx + count);
1327                 nb_pkts = (uint16_t)(nb_pkts - count);
1328                 if (count < n)
1329                         break;
1330         }
1331
1332         return nb_rx;
1333 }
1334
1335 static inline int
1336 avf_xmit_cleanup(struct avf_tx_queue *txq)
1337 {
1338         struct avf_tx_entry *sw_ring = txq->sw_ring;
1339         uint16_t last_desc_cleaned = txq->last_desc_cleaned;
1340         uint16_t nb_tx_desc = txq->nb_tx_desc;
1341         uint16_t desc_to_clean_to;
1342         uint16_t nb_tx_to_clean;
1343
1344         volatile struct avf_tx_desc *txd = txq->tx_ring;
1345
1346         desc_to_clean_to = (uint16_t)(last_desc_cleaned + txq->rs_thresh);
1347         if (desc_to_clean_to >= nb_tx_desc)
1348                 desc_to_clean_to = (uint16_t)(desc_to_clean_to - nb_tx_desc);
1349
1350         desc_to_clean_to = sw_ring[desc_to_clean_to].last_id;
1351         if ((txd[desc_to_clean_to].cmd_type_offset_bsz &
1352                         rte_cpu_to_le_64(AVF_TXD_QW1_DTYPE_MASK)) !=
1353                         rte_cpu_to_le_64(AVF_TX_DESC_DTYPE_DESC_DONE)) {
1354                 PMD_TX_FREE_LOG(DEBUG, "TX descriptor %4u is not done "
1355                                 "(port=%d queue=%d)", desc_to_clean_to,
1356                                 txq->port_id, txq->queue_id);
1357                 return -1;
1358         }
1359
1360         if (last_desc_cleaned > desc_to_clean_to)
1361                 nb_tx_to_clean = (uint16_t)((nb_tx_desc - last_desc_cleaned) +
1362                                                         desc_to_clean_to);
1363         else
1364                 nb_tx_to_clean = (uint16_t)(desc_to_clean_to -
1365                                         last_desc_cleaned);
1366
1367         txd[desc_to_clean_to].cmd_type_offset_bsz = 0;
1368
1369         txq->last_desc_cleaned = desc_to_clean_to;
1370         txq->nb_free = (uint16_t)(txq->nb_free + nb_tx_to_clean);
1371
1372         return 0;
1373 }
1374
1375 /* Check if the context descriptor is needed for TX offloading */
1376 static inline uint16_t
1377 avf_calc_context_desc(uint64_t flags)
1378 {
1379         static uint64_t mask = PKT_TX_TCP_SEG;
1380
1381         return (flags & mask) ? 1 : 0;
1382 }
1383
1384 static inline void
1385 avf_txd_enable_checksum(uint64_t ol_flags,
1386                         uint32_t *td_cmd,
1387                         uint32_t *td_offset,
1388                         union avf_tx_offload tx_offload)
1389 {
1390         /* Set MACLEN */
1391         *td_offset |= (tx_offload.l2_len >> 1) <<
1392                       AVF_TX_DESC_LENGTH_MACLEN_SHIFT;
1393
1394         /* Enable L3 checksum offloads */
1395         if (ol_flags & PKT_TX_IP_CKSUM) {
1396                 *td_cmd |= AVF_TX_DESC_CMD_IIPT_IPV4_CSUM;
1397                 *td_offset |= (tx_offload.l3_len >> 2) <<
1398                               AVF_TX_DESC_LENGTH_IPLEN_SHIFT;
1399         } else if (ol_flags & PKT_TX_IPV4) {
1400                 *td_cmd |= AVF_TX_DESC_CMD_IIPT_IPV4;
1401                 *td_offset |= (tx_offload.l3_len >> 2) <<
1402                               AVF_TX_DESC_LENGTH_IPLEN_SHIFT;
1403         } else if (ol_flags & PKT_TX_IPV6) {
1404                 *td_cmd |= AVF_TX_DESC_CMD_IIPT_IPV6;
1405                 *td_offset |= (tx_offload.l3_len >> 2) <<
1406                               AVF_TX_DESC_LENGTH_IPLEN_SHIFT;
1407         }
1408
1409         if (ol_flags & PKT_TX_TCP_SEG) {
1410                 *td_cmd |= AVF_TX_DESC_CMD_L4T_EOFT_TCP;
1411                 *td_offset |= (tx_offload.l4_len >> 2) <<
1412                               AVF_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
1413                 return;
1414         }
1415
1416         /* Enable L4 checksum offloads */
1417         switch (ol_flags & PKT_TX_L4_MASK) {
1418         case PKT_TX_TCP_CKSUM:
1419                 *td_cmd |= AVF_TX_DESC_CMD_L4T_EOFT_TCP;
1420                 *td_offset |= (sizeof(struct tcp_hdr) >> 2) <<
1421                               AVF_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
1422                 break;
1423         case PKT_TX_SCTP_CKSUM:
1424                 *td_cmd |= AVF_TX_DESC_CMD_L4T_EOFT_SCTP;
1425                 *td_offset |= (sizeof(struct sctp_hdr) >> 2) <<
1426                               AVF_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
1427                 break;
1428         case PKT_TX_UDP_CKSUM:
1429                 *td_cmd |= AVF_TX_DESC_CMD_L4T_EOFT_UDP;
1430                 *td_offset |= (sizeof(struct udp_hdr) >> 2) <<
1431                               AVF_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
1432                 break;
1433         default:
1434                 break;
1435         }
1436 }
1437
1438 /* set TSO context descriptor
1439  * support IP -> L4 and IP -> IP -> L4
1440  */
1441 static inline uint64_t
1442 avf_set_tso_ctx(struct rte_mbuf *mbuf, union avf_tx_offload tx_offload)
1443 {
1444         uint64_t ctx_desc = 0;
1445         uint32_t cd_cmd, hdr_len, cd_tso_len;
1446
1447         if (!tx_offload.l4_len) {
1448                 PMD_TX_LOG(DEBUG, "L4 length set to 0");
1449                 return ctx_desc;
1450         }
1451
1452         /* in case of non tunneling packet, the outer_l2_len and
1453          * outer_l3_len must be 0.
1454          */
1455         hdr_len = tx_offload.l2_len +
1456                   tx_offload.l3_len +
1457                   tx_offload.l4_len;
1458
1459         cd_cmd = AVF_TX_CTX_DESC_TSO;
1460         cd_tso_len = mbuf->pkt_len - hdr_len;
1461         ctx_desc |= ((uint64_t)cd_cmd << AVF_TXD_CTX_QW1_CMD_SHIFT) |
1462                      ((uint64_t)cd_tso_len << AVF_TXD_CTX_QW1_TSO_LEN_SHIFT) |
1463                      ((uint64_t)mbuf->tso_segsz << AVF_TXD_CTX_QW1_MSS_SHIFT);
1464
1465         return ctx_desc;
1466 }
1467
1468 /* Construct the tx flags */
1469 static inline uint64_t
1470 avf_build_ctob(uint32_t td_cmd, uint32_t td_offset, unsigned int size,
1471                uint32_t td_tag)
1472 {
1473         return rte_cpu_to_le_64(AVF_TX_DESC_DTYPE_DATA |
1474                                 ((uint64_t)td_cmd  << AVF_TXD_QW1_CMD_SHIFT) |
1475                                 ((uint64_t)td_offset <<
1476                                  AVF_TXD_QW1_OFFSET_SHIFT) |
1477                                 ((uint64_t)size  <<
1478                                  AVF_TXD_QW1_TX_BUF_SZ_SHIFT) |
1479                                 ((uint64_t)td_tag  <<
1480                                  AVF_TXD_QW1_L2TAG1_SHIFT));
1481 }
1482
1483 /* TX function */
1484 uint16_t
1485 avf_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts, uint16_t nb_pkts)
1486 {
1487         volatile struct avf_tx_desc *txd;
1488         volatile struct avf_tx_desc *txr;
1489         struct avf_tx_queue *txq;
1490         struct avf_tx_entry *sw_ring;
1491         struct avf_tx_entry *txe, *txn;
1492         struct rte_mbuf *tx_pkt;
1493         struct rte_mbuf *m_seg;
1494         uint16_t tx_id;
1495         uint16_t nb_tx;
1496         uint32_t td_cmd;
1497         uint32_t td_offset;
1498         uint32_t td_tag;
1499         uint64_t ol_flags;
1500         uint16_t nb_used;
1501         uint16_t nb_ctx;
1502         uint16_t tx_last;
1503         uint16_t slen;
1504         uint64_t buf_dma_addr;
1505         union avf_tx_offload tx_offload = {0};
1506
1507         txq = tx_queue;
1508         sw_ring = txq->sw_ring;
1509         txr = txq->tx_ring;
1510         tx_id = txq->tx_tail;
1511         txe = &sw_ring[tx_id];
1512
1513         /* Check if the descriptor ring needs to be cleaned. */
1514         if (txq->nb_free < txq->free_thresh)
1515                 avf_xmit_cleanup(txq);
1516
1517         for (nb_tx = 0; nb_tx < nb_pkts; nb_tx++) {
1518                 td_cmd = 0;
1519                 td_tag = 0;
1520                 td_offset = 0;
1521
1522                 tx_pkt = *tx_pkts++;
1523                 RTE_MBUF_PREFETCH_TO_FREE(txe->mbuf);
1524
1525                 ol_flags = tx_pkt->ol_flags;
1526                 tx_offload.l2_len = tx_pkt->l2_len;
1527                 tx_offload.l3_len = tx_pkt->l3_len;
1528                 tx_offload.l4_len = tx_pkt->l4_len;
1529                 tx_offload.tso_segsz = tx_pkt->tso_segsz;
1530
1531                 /* Calculate the number of context descriptors needed. */
1532                 nb_ctx = avf_calc_context_desc(ol_flags);
1533
1534                 /* The number of descriptors that must be allocated for
1535                  * a packet equals to the number of the segments of that
1536                  * packet plus 1 context descriptor if needed.
1537                  */
1538                 nb_used = (uint16_t)(tx_pkt->nb_segs + nb_ctx);
1539                 tx_last = (uint16_t)(tx_id + nb_used - 1);
1540
1541                 /* Circular ring */
1542                 if (tx_last >= txq->nb_tx_desc)
1543                         tx_last = (uint16_t)(tx_last - txq->nb_tx_desc);
1544
1545                 PMD_TX_LOG(DEBUG, "port_id=%u queue_id=%u"
1546                            " tx_first=%u tx_last=%u",
1547                            txq->port_id, txq->queue_id, tx_id, tx_last);
1548
1549                 if (nb_used > txq->nb_free) {
1550                         if (avf_xmit_cleanup(txq)) {
1551                                 if (nb_tx == 0)
1552                                         return 0;
1553                                 goto end_of_tx;
1554                         }
1555                         if (unlikely(nb_used > txq->rs_thresh)) {
1556                                 while (nb_used > txq->nb_free) {
1557                                         if (avf_xmit_cleanup(txq)) {
1558                                                 if (nb_tx == 0)
1559                                                         return 0;
1560                                                 goto end_of_tx;
1561                                         }
1562                                 }
1563                         }
1564                 }
1565
1566                 /* Descriptor based VLAN insertion */
1567                 if (ol_flags & PKT_TX_VLAN_PKT) {
1568                         td_cmd |= AVF_TX_DESC_CMD_IL2TAG1;
1569                         td_tag = tx_pkt->vlan_tci;
1570                 }
1571
1572                 /* According to datasheet, the bit2 is reserved and must be
1573                  * set to 1.
1574                  */
1575                 td_cmd |= 0x04;
1576
1577                 /* Enable checksum offloading */
1578                 if (ol_flags & AVF_TX_CKSUM_OFFLOAD_MASK)
1579                         avf_txd_enable_checksum(ol_flags, &td_cmd,
1580                                                 &td_offset, tx_offload);
1581
1582                 if (nb_ctx) {
1583                         /* Setup TX context descriptor if required */
1584                         volatile struct avf_tx_context_desc *ctx_txd =
1585                                 (volatile struct avf_tx_context_desc *)
1586                                         &txr[tx_id];
1587                         uint16_t cd_l2tag2 = 0;
1588                         uint64_t cd_type_cmd_tso_mss =
1589                                 AVF_TX_DESC_DTYPE_CONTEXT;
1590
1591                         txn = &sw_ring[txe->next_id];
1592                         RTE_MBUF_PREFETCH_TO_FREE(txn->mbuf);
1593                         if (txe->mbuf) {
1594                                 rte_pktmbuf_free_seg(txe->mbuf);
1595                                 txe->mbuf = NULL;
1596                         }
1597
1598                         /* TSO enabled */
1599                         if (ol_flags & PKT_TX_TCP_SEG)
1600                                 cd_type_cmd_tso_mss |=
1601                                         avf_set_tso_ctx(tx_pkt, tx_offload);
1602
1603                         AVF_DUMP_TX_DESC(txq, ctx_txd, tx_id);
1604                         txe->last_id = tx_last;
1605                         tx_id = txe->next_id;
1606                         txe = txn;
1607                 }
1608
1609                 m_seg = tx_pkt;
1610                 do {
1611                         txd = &txr[tx_id];
1612                         txn = &sw_ring[txe->next_id];
1613
1614                         if (txe->mbuf)
1615                                 rte_pktmbuf_free_seg(txe->mbuf);
1616                         txe->mbuf = m_seg;
1617
1618                         /* Setup TX Descriptor */
1619                         slen = m_seg->data_len;
1620                         buf_dma_addr = rte_mbuf_data_iova(m_seg);
1621                         txd->buffer_addr = rte_cpu_to_le_64(buf_dma_addr);
1622                         txd->cmd_type_offset_bsz = avf_build_ctob(td_cmd,
1623                                                                   td_offset,
1624                                                                   slen,
1625                                                                   td_tag);
1626
1627                         AVF_DUMP_TX_DESC(txq, txd, tx_id);
1628                         txe->last_id = tx_last;
1629                         tx_id = txe->next_id;
1630                         txe = txn;
1631                         m_seg = m_seg->next;
1632                 } while (m_seg);
1633
1634                 /* The last packet data descriptor needs End Of Packet (EOP) */
1635                 td_cmd |= AVF_TX_DESC_CMD_EOP;
1636                 txq->nb_used = (uint16_t)(txq->nb_used + nb_used);
1637                 txq->nb_free = (uint16_t)(txq->nb_free - nb_used);
1638
1639                 if (txq->nb_used >= txq->rs_thresh) {
1640                         PMD_TX_LOG(DEBUG, "Setting RS bit on TXD id="
1641                                    "%4u (port=%d queue=%d)",
1642                                    tx_last, txq->port_id, txq->queue_id);
1643
1644                         td_cmd |= AVF_TX_DESC_CMD_RS;
1645
1646                         /* Update txq RS bit counters */
1647                         txq->nb_used = 0;
1648                 }
1649
1650                 txd->cmd_type_offset_bsz |=
1651                         rte_cpu_to_le_64(((uint64_t)td_cmd) <<
1652                                          AVF_TXD_QW1_CMD_SHIFT);
1653                 AVF_DUMP_TX_DESC(txq, txd, tx_id);
1654         }
1655
1656 end_of_tx:
1657         rte_wmb();
1658
1659         PMD_TX_LOG(DEBUG, "port_id=%u queue_id=%u tx_tail=%u nb_tx=%u",
1660                    txq->port_id, txq->queue_id, tx_id, nb_tx);
1661
1662         AVF_PCI_REG_WRITE_RELAXED(txq->qtx_tail, tx_id);
1663         txq->tx_tail = tx_id;
1664
1665         return nb_tx;
1666 }
1667
1668 static uint16_t
1669 avf_xmit_pkts_vec(void *tx_queue, struct rte_mbuf **tx_pkts,
1670                   uint16_t nb_pkts)
1671 {
1672         uint16_t nb_tx = 0;
1673         struct avf_tx_queue *txq = (struct avf_tx_queue *)tx_queue;
1674
1675         while (nb_pkts) {
1676                 uint16_t ret, num;
1677
1678                 num = (uint16_t)RTE_MIN(nb_pkts, txq->rs_thresh);
1679                 ret = avf_xmit_fixed_burst_vec(tx_queue, &tx_pkts[nb_tx], num);
1680                 nb_tx += ret;
1681                 nb_pkts -= ret;
1682                 if (ret < num)
1683                         break;
1684         }
1685
1686         return nb_tx;
1687 }
1688
1689 /* TX prep functions */
1690 uint16_t
1691 avf_prep_pkts(__rte_unused void *tx_queue, struct rte_mbuf **tx_pkts,
1692               uint16_t nb_pkts)
1693 {
1694         int i, ret;
1695         uint64_t ol_flags;
1696         struct rte_mbuf *m;
1697
1698         for (i = 0; i < nb_pkts; i++) {
1699                 m = tx_pkts[i];
1700                 ol_flags = m->ol_flags;
1701
1702                 /* Check condition for nb_segs > AVF_TX_MAX_MTU_SEG. */
1703                 if (!(ol_flags & PKT_TX_TCP_SEG)) {
1704                         if (m->nb_segs > AVF_TX_MAX_MTU_SEG) {
1705                                 rte_errno = -EINVAL;
1706                                 return i;
1707                         }
1708                 } else if ((m->tso_segsz < AVF_MIN_TSO_MSS) ||
1709                            (m->tso_segsz > AVF_MAX_TSO_MSS)) {
1710                         /* MSS outside the range are considered malicious */
1711                         rte_errno = -EINVAL;
1712                         return i;
1713                 }
1714
1715                 if (ol_flags & AVF_TX_OFFLOAD_NOTSUP_MASK) {
1716                         rte_errno = -ENOTSUP;
1717                         return i;
1718                 }
1719
1720 #ifdef RTE_LIBRTE_ETHDEV_DEBUG
1721                 ret = rte_validate_tx_offload(m);
1722                 if (ret != 0) {
1723                         rte_errno = ret;
1724                         return i;
1725                 }
1726 #endif
1727                 ret = rte_net_intel_cksum_prepare(m);
1728                 if (ret != 0) {
1729                         rte_errno = ret;
1730                         return i;
1731                 }
1732         }
1733
1734         return i;
1735 }
1736
1737 /* choose rx function*/
1738 void
1739 avf_set_rx_function(struct rte_eth_dev *dev)
1740 {
1741         struct avf_adapter *adapter =
1742                 AVF_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1743         struct avf_rx_queue *rxq;
1744         int i;
1745
1746         if (adapter->rx_vec_allowed) {
1747                 if (dev->data->scattered_rx) {
1748                         PMD_DRV_LOG(DEBUG, "Using Vector Scattered Rx callback"
1749                                     " (port=%d).", dev->data->port_id);
1750                         dev->rx_pkt_burst = avf_recv_scattered_pkts_vec;
1751                 } else {
1752                         PMD_DRV_LOG(DEBUG, "Using Vector Rx callback"
1753                                     " (port=%d).", dev->data->port_id);
1754                         dev->rx_pkt_burst = avf_recv_pkts_vec;
1755                 }
1756                 for (i = 0; i < dev->data->nb_rx_queues; i++) {
1757                         rxq = dev->data->rx_queues[i];
1758                         if (!rxq)
1759                                 continue;
1760                         avf_rxq_vec_setup(rxq);
1761                 }
1762         } else if (dev->data->scattered_rx) {
1763                 PMD_DRV_LOG(DEBUG, "Using a Scattered Rx callback (port=%d).",
1764                             dev->data->port_id);
1765                 dev->rx_pkt_burst = avf_recv_scattered_pkts;
1766         } else if (adapter->rx_bulk_alloc_allowed) {
1767                 PMD_DRV_LOG(DEBUG, "Using bulk Rx callback (port=%d).",
1768                             dev->data->port_id);
1769                 dev->rx_pkt_burst = avf_recv_pkts_bulk_alloc;
1770         } else {
1771                 PMD_DRV_LOG(DEBUG, "Using Basic Rx callback (port=%d).",
1772                             dev->data->port_id);
1773                 dev->rx_pkt_burst = avf_recv_pkts;
1774         }
1775 }
1776
1777 /* choose tx function*/
1778 void
1779 avf_set_tx_function(struct rte_eth_dev *dev)
1780 {
1781         struct avf_adapter *adapter =
1782                 AVF_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1783         struct avf_tx_queue *txq;
1784         int i;
1785
1786         if (adapter->tx_vec_allowed) {
1787                 PMD_DRV_LOG(DEBUG, "Using Vector Tx callback (port=%d).",
1788                             dev->data->port_id);
1789                 dev->tx_pkt_burst = avf_xmit_pkts_vec;
1790                 dev->tx_pkt_prepare = NULL;
1791                 for (i = 0; i < dev->data->nb_tx_queues; i++) {
1792                         txq = dev->data->tx_queues[i];
1793                         if (!txq)
1794                                 continue;
1795                         avf_txq_vec_setup(txq);
1796                 }
1797         } else {
1798                 PMD_DRV_LOG(DEBUG, "Using Basic Tx callback (port=%d).",
1799                             dev->data->port_id);
1800                 dev->tx_pkt_burst = avf_xmit_pkts;
1801                 dev->tx_pkt_prepare = avf_prep_pkts;
1802         }
1803 }
1804
1805 void
1806 avf_dev_rxq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
1807                      struct rte_eth_rxq_info *qinfo)
1808 {
1809         struct avf_rx_queue *rxq;
1810
1811         rxq = dev->data->rx_queues[queue_id];
1812
1813         qinfo->mp = rxq->mp;
1814         qinfo->scattered_rx = dev->data->scattered_rx;
1815         qinfo->nb_desc = rxq->nb_rx_desc;
1816
1817         qinfo->conf.rx_free_thresh = rxq->rx_free_thresh;
1818         qinfo->conf.rx_drop_en = TRUE;
1819         qinfo->conf.rx_deferred_start = rxq->rx_deferred_start;
1820 }
1821
1822 void
1823 avf_dev_txq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
1824                      struct rte_eth_txq_info *qinfo)
1825 {
1826         struct avf_tx_queue *txq;
1827
1828         txq = dev->data->tx_queues[queue_id];
1829
1830         qinfo->nb_desc = txq->nb_tx_desc;
1831
1832         qinfo->conf.tx_free_thresh = txq->free_thresh;
1833         qinfo->conf.tx_rs_thresh = txq->rs_thresh;
1834         qinfo->conf.txq_flags = txq->txq_flags;
1835         qinfo->conf.tx_deferred_start = txq->tx_deferred_start;
1836 }
1837
1838 /* Get the number of used descriptors of a rx queue */
1839 uint32_t
1840 avf_dev_rxq_count(struct rte_eth_dev *dev, uint16_t queue_id)
1841 {
1842 #define AVF_RXQ_SCAN_INTERVAL 4
1843         volatile union avf_rx_desc *rxdp;
1844         struct avf_rx_queue *rxq;
1845         uint16_t desc = 0;
1846
1847         rxq = dev->data->rx_queues[queue_id];
1848         rxdp = &rxq->rx_ring[rxq->rx_tail];
1849         while ((desc < rxq->nb_rx_desc) &&
1850                ((rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len) &
1851                  AVF_RXD_QW1_STATUS_MASK) >> AVF_RXD_QW1_STATUS_SHIFT) &
1852                (1 << AVF_RX_DESC_STATUS_DD_SHIFT)) {
1853                 /* Check the DD bit of a rx descriptor of each 4 in a group,
1854                  * to avoid checking too frequently and downgrading performance
1855                  * too much.
1856                  */
1857                 desc += AVF_RXQ_SCAN_INTERVAL;
1858                 rxdp += AVF_RXQ_SCAN_INTERVAL;
1859                 if (rxq->rx_tail + desc >= rxq->nb_rx_desc)
1860                         rxdp = &(rxq->rx_ring[rxq->rx_tail +
1861                                         desc - rxq->nb_rx_desc]);
1862         }
1863
1864         return desc;
1865 }
1866
1867 int
1868 avf_dev_rx_desc_status(void *rx_queue, uint16_t offset)
1869 {
1870         struct avf_rx_queue *rxq = rx_queue;
1871         volatile uint64_t *status;
1872         uint64_t mask;
1873         uint32_t desc;
1874
1875         if (unlikely(offset >= rxq->nb_rx_desc))
1876                 return -EINVAL;
1877
1878         if (offset >= rxq->nb_rx_desc - rxq->nb_rx_hold)
1879                 return RTE_ETH_RX_DESC_UNAVAIL;
1880
1881         desc = rxq->rx_tail + offset;
1882         if (desc >= rxq->nb_rx_desc)
1883                 desc -= rxq->nb_rx_desc;
1884
1885         status = &rxq->rx_ring[desc].wb.qword1.status_error_len;
1886         mask = rte_le_to_cpu_64((1ULL << AVF_RX_DESC_STATUS_DD_SHIFT)
1887                 << AVF_RXD_QW1_STATUS_SHIFT);
1888         if (*status & mask)
1889                 return RTE_ETH_RX_DESC_DONE;
1890
1891         return RTE_ETH_RX_DESC_AVAIL;
1892 }
1893
1894 int
1895 avf_dev_tx_desc_status(void *tx_queue, uint16_t offset)
1896 {
1897         struct avf_tx_queue *txq = tx_queue;
1898         volatile uint64_t *status;
1899         uint64_t mask, expect;
1900         uint32_t desc;
1901
1902         if (unlikely(offset >= txq->nb_tx_desc))
1903                 return -EINVAL;
1904
1905         desc = txq->tx_tail + offset;
1906         /* go to next desc that has the RS bit */
1907         desc = ((desc + txq->rs_thresh - 1) / txq->rs_thresh) *
1908                 txq->rs_thresh;
1909         if (desc >= txq->nb_tx_desc) {
1910                 desc -= txq->nb_tx_desc;
1911                 if (desc >= txq->nb_tx_desc)
1912                         desc -= txq->nb_tx_desc;
1913         }
1914
1915         status = &txq->tx_ring[desc].cmd_type_offset_bsz;
1916         mask = rte_le_to_cpu_64(AVF_TXD_QW1_DTYPE_MASK);
1917         expect = rte_cpu_to_le_64(
1918                  AVF_TX_DESC_DTYPE_DESC_DONE << AVF_TXD_QW1_DTYPE_SHIFT);
1919         if ((*status & mask) == expect)
1920                 return RTE_ETH_TX_DESC_DONE;
1921
1922         return RTE_ETH_TX_DESC_FULL;
1923 }
1924
1925 uint16_t __attribute__((weak))
1926 avf_recv_pkts_vec(__rte_unused void *rx_queue,
1927                   __rte_unused struct rte_mbuf **rx_pkts,
1928                   __rte_unused uint16_t nb_pkts)
1929 {
1930         return 0;
1931 }
1932
1933 uint16_t __attribute__((weak))
1934 avf_recv_scattered_pkts_vec(__rte_unused void *rx_queue,
1935                             __rte_unused struct rte_mbuf **rx_pkts,
1936                             __rte_unused uint16_t nb_pkts)
1937 {
1938         return 0;
1939 }
1940
1941 uint16_t __attribute__((weak))
1942 avf_xmit_fixed_burst_vec(__rte_unused void *tx_queue,
1943                          __rte_unused struct rte_mbuf **tx_pkts,
1944                          __rte_unused uint16_t nb_pkts)
1945 {
1946         return 0;
1947 }
1948
1949 int __attribute__((weak))
1950 avf_rxq_vec_setup(__rte_unused struct avf_rx_queue *rxq)
1951 {
1952         return -1;
1953 }
1954
1955 int __attribute__((weak))
1956 avf_txq_vec_setup(__rte_unused struct avf_tx_queue *txq)
1957 {
1958         return -1;
1959 }