drivers/net/avf/avf_rxtx.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2017 Intel Corporation
   3  */
   4
   5 #include <stdio.h>
   6 #include <stdlib.h>
   7 #include <string.h>
   8 #include <errno.h>
   9 #include <stdint.h>
  10 #include <stdarg.h>
  11 #include <unistd.h>
  12 #include <inttypes.h>
  13 #include <sys/queue.h>
  14
  15 #include <rte_string_fns.h>
  16 #include <rte_memzone.h>
  17 #include <rte_mbuf.h>
  18 #include <rte_malloc.h>
  19 #include <rte_ether.h>
  20 #include <rte_ethdev_driver.h>
  21 #include <rte_tcp.h>
  22 #include <rte_sctp.h>
  23 #include <rte_udp.h>
  24 #include <rte_ip.h>
  25 #include <rte_net.h>
  26
  27 #include "avf_log.h"
  28 #include "base/avf_prototype.h"
  29 #include "base/avf_type.h"
  30 #include "avf.h"
  31 #include "avf_rxtx.h"
  32
  33 static inline int
  34 check_rx_thresh(uint16_t nb_desc, uint16_t thresh)
  35 {
  36         /* The following constraints must be satisfied:
  37          *   thresh < rxq->nb_rx_desc
  38          */
  39         if (thresh >= nb_desc) {
  40                 PMD_INIT_LOG(ERR, "rx_free_thresh (%u) must be less than %u",
  41                              thresh, nb_desc);
  42                 return -EINVAL;
  43         }
  44         return 0;
  45 }
  46
  47 static inline int
  48 check_tx_thresh(uint16_t nb_desc, uint16_t tx_rs_thresh,
  49                 uint16_t tx_free_thresh)
  50 {
  51         /* TX descriptors will have their RS bit set after tx_rs_thresh
  52          * descriptors have been used. The TX descriptor ring will be cleaned
  53          * after tx_free_thresh descriptors are used or if the number of
  54          * descriptors required to transmit a packet is greater than the
  55          * number of free TX descriptors.
  56          *
  57          * The following constraints must be satisfied:
  58          *  - tx_rs_thresh must be less than the size of the ring minus 2.
  59          *  - tx_free_thresh must be less than the size of the ring minus 3.
  60          *  - tx_rs_thresh must be less than or equal to tx_free_thresh.
  61          *  - tx_rs_thresh must be a divisor of the ring size.
  62          *
  63          * One descriptor in the TX ring is used as a sentinel to avoid a H/W
  64          * race condition, hence the maximum threshold constraints. When set
  65          * to zero use default values.
  66          */
  67         if (tx_rs_thresh >= (nb_desc - 2)) {
  68                 PMD_INIT_LOG(ERR, "tx_rs_thresh (%u) must be less than the "
  69                              "number of TX descriptors (%u) minus 2",
  70                              tx_rs_thresh, nb_desc);
  71                 return -EINVAL;
  72         }
  73         if (tx_free_thresh >= (nb_desc - 3)) {
  74                 PMD_INIT_LOG(ERR, "tx_free_thresh (%u) must be less than the "
  75                              "number of TX descriptors (%u) minus 3.",
  76                              tx_free_thresh, nb_desc);
  77                 return -EINVAL;
  78         }
  79         if (tx_rs_thresh > tx_free_thresh) {
  80                 PMD_INIT_LOG(ERR, "tx_rs_thresh (%u) must be less than or "
  81                              "equal to tx_free_thresh (%u).",
  82                              tx_rs_thresh, tx_free_thresh);
  83                 return -EINVAL;
  84         }
  85         if ((nb_desc % tx_rs_thresh) != 0) {
  86                 PMD_INIT_LOG(ERR, "tx_rs_thresh (%u) must be a divisor of the "
  87                              "number of TX descriptors (%u).",
  88                              tx_rs_thresh, nb_desc);
  89                 return -EINVAL;
  90         }
  91
  92         return 0;
  93 }
  94
  95 #ifdef RTE_LIBRTE_AVF_INC_VECTOR
  96 static inline bool
  97 check_rx_vec_allow(struct avf_rx_queue *rxq)
  98 {
  99         if (rxq->rx_free_thresh >= AVF_VPMD_RX_MAX_BURST &&
 100             rxq->nb_rx_desc % rxq->rx_free_thresh == 0) {
 101                 PMD_INIT_LOG(DEBUG, "Vector Rx can be enabled on this rxq.");
 102                 return TRUE;
 103         }
 104
 105         PMD_INIT_LOG(DEBUG, "Vector Rx cannot be enabled on this rxq.");
 106         return FALSE;
 107 }
 108
 109 static inline bool
 110 check_tx_vec_allow(struct avf_tx_queue *txq)
 111 {
 112         if (!(txq->offloads & AVF_NO_VECTOR_FLAGS) &&
 113             txq->rs_thresh >= AVF_VPMD_TX_MAX_BURST &&
 114             txq->rs_thresh <= AVF_VPMD_TX_MAX_FREE_BUF) {
 115                 PMD_INIT_LOG(DEBUG, "Vector tx can be enabled on this txq.");
 116                 return TRUE;
 117         }
 118         PMD_INIT_LOG(DEBUG, "Vector Tx cannot be enabled on this txq.");
 119         return FALSE;
 120 }
 121 #endif
 122
 123 static inline bool
 124 check_rx_bulk_allow(struct avf_rx_queue *rxq)
 125 {
 126         int ret = TRUE;
 127
 128         if (!(rxq->rx_free_thresh >= AVF_RX_MAX_BURST)) {
 129                 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions: "
 130                              "rxq->rx_free_thresh=%d, "
 131                              "AVF_RX_MAX_BURST=%d",
 132                              rxq->rx_free_thresh, AVF_RX_MAX_BURST);
 133                 ret = FALSE;
 134         } else if (rxq->nb_rx_desc % rxq->rx_free_thresh != 0) {
 135                 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions: "
 136                              "rxq->nb_rx_desc=%d, "
 137                              "rxq->rx_free_thresh=%d",
 138                              rxq->nb_rx_desc, rxq->rx_free_thresh);
 139                 ret = FALSE;
 140         }
 141         return ret;
 142 }
 143
 144 static inline void
 145 reset_rx_queue(struct avf_rx_queue *rxq)
 146 {
 147         uint16_t len, i;
 148
 149         if (!rxq)
 150                 return;
 151
 152         len = rxq->nb_rx_desc + AVF_RX_MAX_BURST;
 153
 154         for (i = 0; i < len * sizeof(union avf_rx_desc); i++)
 155                 ((volatile char *)rxq->rx_ring)[i] = 0;
 156
 157         memset(&rxq->fake_mbuf, 0x0, sizeof(rxq->fake_mbuf));
 158
 159         for (i = 0; i < AVF_RX_MAX_BURST; i++)
 160                 rxq->sw_ring[rxq->nb_rx_desc + i] = &rxq->fake_mbuf;
 161
 162         /* for rx bulk */
 163         rxq->rx_nb_avail = 0;
 164         rxq->rx_next_avail = 0;
 165         rxq->rx_free_trigger = (uint16_t)(rxq->rx_free_thresh - 1);
 166
 167         rxq->rx_tail = 0;
 168         rxq->nb_rx_hold = 0;
 169         rxq->pkt_first_seg = NULL;
 170         rxq->pkt_last_seg = NULL;
 171 }
 172
 173 static inline void
 174 reset_tx_queue(struct avf_tx_queue *txq)
 175 {
 176         struct avf_tx_entry *txe;
 177         uint16_t i, prev, size;
 178
 179         if (!txq) {
 180                 PMD_DRV_LOG(DEBUG, "Pointer to txq is NULL");
 181                 return;
 182         }
 183
 184         txe = txq->sw_ring;
 185         size = sizeof(struct avf_tx_desc) * txq->nb_tx_desc;
 186         for (i = 0; i < size; i++)
 187                 ((volatile char *)txq->tx_ring)[i] = 0;
 188
 189         prev = (uint16_t)(txq->nb_tx_desc - 1);
 190         for (i = 0; i < txq->nb_tx_desc; i++) {
 191                 txq->tx_ring[i].cmd_type_offset_bsz =
 192                         rte_cpu_to_le_64(AVF_TX_DESC_DTYPE_DESC_DONE);
 193                 txe[i].mbuf =  NULL;
 194                 txe[i].last_id = i;
 195                 txe[prev].next_id = i;
 196                 prev = i;
 197         }
 198
 199         txq->tx_tail = 0;
 200         txq->nb_used = 0;
 201
 202         txq->last_desc_cleaned = txq->nb_tx_desc - 1;
 203         txq->nb_free = txq->nb_tx_desc - 1;
 204
 205         txq->next_dd = txq->rs_thresh - 1;
 206         txq->next_rs = txq->rs_thresh - 1;
 207 }
 208
 209 static int
 210 alloc_rxq_mbufs(struct avf_rx_queue *rxq)
 211 {
 212         volatile union avf_rx_desc *rxd;
 213         struct rte_mbuf *mbuf = NULL;
 214         uint64_t dma_addr;
 215         uint16_t i;
 216
 217         for (i = 0; i < rxq->nb_rx_desc; i++) {
 218                 mbuf = rte_mbuf_raw_alloc(rxq->mp);
 219                 if (unlikely(!mbuf)) {
 220                         PMD_DRV_LOG(ERR, "Failed to allocate mbuf for RX");
 221                         return -ENOMEM;
 222                 }
 223
 224                 rte_mbuf_refcnt_set(mbuf, 1);
 225                 mbuf->next = NULL;
 226                 mbuf->data_off = RTE_PKTMBUF_HEADROOM;
 227                 mbuf->nb_segs = 1;
 228                 mbuf->port = rxq->port_id;
 229
 230                 dma_addr =
 231                         rte_cpu_to_le_64(rte_mbuf_data_iova_default(mbuf));
 232
 233                 rxd = &rxq->rx_ring[i];
 234                 rxd->read.pkt_addr = dma_addr;
 235                 rxd->read.hdr_addr = 0;
 236 #ifndef RTE_LIBRTE_AVF_16BYTE_RX_DESC
 237                 rxd->read.rsvd1 = 0;
 238                 rxd->read.rsvd2 = 0;
 239 #endif
 240
 241                 rxq->sw_ring[i] = mbuf;
 242         }
 243
 244         return 0;
 245 }
 246
 247 static inline void
 248 release_rxq_mbufs(struct avf_rx_queue *rxq)
 249 {
 250         struct rte_mbuf *mbuf;
 251         uint16_t i;
 252
 253         if (!rxq->sw_ring)
 254                 return;
 255
 256         for (i = 0; i < rxq->nb_rx_desc; i++) {
 257                 if (rxq->sw_ring[i]) {
 258                         rte_pktmbuf_free_seg(rxq->sw_ring[i]);
 259                         rxq->sw_ring[i] = NULL;
 260                 }
 261         }
 262
 263         /* for rx bulk */
 264         if (rxq->rx_nb_avail == 0)
 265                 return;
 266         for (i = 0; i < rxq->rx_nb_avail; i++) {
 267                 struct rte_mbuf *mbuf;
 268
 269                 mbuf = rxq->rx_stage[rxq->rx_next_avail + i];
 270                 rte_pktmbuf_free_seg(mbuf);
 271         }
 272         rxq->rx_nb_avail = 0;
 273 }
 274
 275 static inline void
 276 release_txq_mbufs(struct avf_tx_queue *txq)
 277 {
 278         uint16_t i;
 279
 280         if (!txq || !txq->sw_ring) {
 281                 PMD_DRV_LOG(DEBUG, "Pointer to rxq or sw_ring is NULL");
 282                 return;
 283         }
 284
 285         for (i = 0; i < txq->nb_tx_desc; i++) {
 286                 if (txq->sw_ring[i].mbuf) {
 287                         rte_pktmbuf_free_seg(txq->sw_ring[i].mbuf);
 288                         txq->sw_ring[i].mbuf = NULL;
 289                 }
 290         }
 291 }
 292
 293 static const struct avf_rxq_ops def_rxq_ops = {
 294         .release_mbufs = release_rxq_mbufs,
 295 };
 296
 297 static const struct avf_txq_ops def_txq_ops = {
 298         .release_mbufs = release_txq_mbufs,
 299 };
 300
 301 int
 302 avf_dev_rx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,
 303                        uint16_t nb_desc, unsigned int socket_id,
 304                        const struct rte_eth_rxconf *rx_conf,
 305                        struct rte_mempool *mp)
 306 {
 307         struct avf_hw *hw = AVF_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 308         struct avf_adapter *ad =
 309                 AVF_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
 310         struct avf_rx_queue *rxq;
 311         const struct rte_memzone *mz;
 312         uint32_t ring_size;
 313         uint16_t len, i;
 314         uint16_t rx_free_thresh;
 315         uint16_t base, bsf, tc_mapping;
 316
 317         PMD_INIT_FUNC_TRACE();
 318
 319         if (nb_desc % AVF_ALIGN_RING_DESC != 0 ||
 320             nb_desc > AVF_MAX_RING_DESC ||
 321             nb_desc < AVF_MIN_RING_DESC) {
 322                 PMD_INIT_LOG(ERR, "Number (%u) of receive descriptors is "
 323                              "invalid", nb_desc);
 324                 return -EINVAL;
 325         }
 326
 327         /* Check free threshold */
 328         rx_free_thresh = (rx_conf->rx_free_thresh == 0) ?
 329                          AVF_DEFAULT_RX_FREE_THRESH :
 330                          rx_conf->rx_free_thresh;
 331         if (check_rx_thresh(nb_desc, rx_free_thresh) != 0)
 332                 return -EINVAL;
 333
 334         /* Free memory if needed */
 335         if (dev->data->rx_queues[queue_idx]) {
 336                 avf_dev_rx_queue_release(dev->data->rx_queues[queue_idx]);
 337                 dev->data->rx_queues[queue_idx] = NULL;
 338         }
 339
 340         /* Allocate the rx queue data structure */
 341         rxq = rte_zmalloc_socket("avf rxq",
 342                                  sizeof(struct avf_rx_queue),
 343                                  RTE_CACHE_LINE_SIZE,
 344                                  socket_id);
 345         if (!rxq) {
 346                 PMD_INIT_LOG(ERR, "Failed to allocate memory for "
 347                              "rx queue data structure");
 348                 return -ENOMEM;
 349         }
 350
 351         rxq->mp = mp;
 352         rxq->nb_rx_desc = nb_desc;
 353         rxq->rx_free_thresh = rx_free_thresh;
 354         rxq->queue_id = queue_idx;
 355         rxq->port_id = dev->data->port_id;
 356         rxq->crc_len = 0; /* crc stripping by default */
 357         rxq->rx_deferred_start = rx_conf->rx_deferred_start;
 358         rxq->rx_hdr_len = 0;
 359
 360         len = rte_pktmbuf_data_room_size(rxq->mp) - RTE_PKTMBUF_HEADROOM;
 361         rxq->rx_buf_len = RTE_ALIGN(len, (1 << AVF_RXQ_CTX_DBUFF_SHIFT));
 362
 363         /* Allocate the software ring. */
 364         len = nb_desc + AVF_RX_MAX_BURST;
 365         rxq->sw_ring =
 366                 rte_zmalloc_socket("avf rx sw ring",
 367                                    sizeof(struct rte_mbuf *) * len,
 368                                    RTE_CACHE_LINE_SIZE,
 369                                    socket_id);
 370         if (!rxq->sw_ring) {
 371                 PMD_INIT_LOG(ERR, "Failed to allocate memory for SW ring");
 372                 rte_free(rxq);
 373                 return -ENOMEM;
 374         }
 375
 376         /* Allocate the maximun number of RX ring hardware descriptor with
 377          * a liitle more to support bulk allocate.
 378          */
 379         len = AVF_MAX_RING_DESC + AVF_RX_MAX_BURST;
 380         ring_size = RTE_ALIGN(len * sizeof(union avf_rx_desc),
 381                               AVF_DMA_MEM_ALIGN);
 382         mz = rte_eth_dma_zone_reserve(dev, "rx_ring", queue_idx,
 383                                       ring_size, AVF_RING_BASE_ALIGN,
 384                                       socket_id);
 385         if (!mz) {
 386                 PMD_INIT_LOG(ERR, "Failed to reserve DMA memory for RX");
 387                 rte_free(rxq->sw_ring);
 388                 rte_free(rxq);
 389                 return -ENOMEM;
 390         }
 391         /* Zero all the descriptors in the ring. */
 392         memset(mz->addr, 0, ring_size);
 393         rxq->rx_ring_phys_addr = mz->iova;
 394         rxq->rx_ring = (union avf_rx_desc *)mz->addr;
 395
 396         rxq->mz = mz;
 397         reset_rx_queue(rxq);
 398         rxq->q_set = TRUE;
 399         dev->data->rx_queues[queue_idx] = rxq;
 400         rxq->qrx_tail = hw->hw_addr + AVF_QRX_TAIL1(rxq->queue_id);
 401         rxq->ops = &def_rxq_ops;
 402
 403         if (check_rx_bulk_allow(rxq) == TRUE) {
 404                 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions are "
 405                              "satisfied. Rx Burst Bulk Alloc function will be "
 406                              "used on port=%d, queue=%d.",
 407                              rxq->port_id, rxq->queue_id);
 408         } else {
 409                 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions are "
 410                              "not satisfied, Scattered Rx is requested "
 411                              "on port=%d, queue=%d.",
 412                              rxq->port_id, rxq->queue_id);
 413                 ad->rx_bulk_alloc_allowed = false;
 414         }
 415
 416 #ifdef RTE_LIBRTE_AVF_INC_VECTOR
 417         if (check_rx_vec_allow(rxq) == FALSE)
 418                 ad->rx_vec_allowed = false;
 419 #endif
 420         return 0;
 421 }
 422
 423 int
 424 avf_dev_tx_queue_setup(struct rte_eth_dev *dev,
 425                        uint16_t queue_idx,
 426                        uint16_t nb_desc,
 427                        unsigned int socket_id,
 428                        const struct rte_eth_txconf *tx_conf)
 429 {
 430         struct avf_hw *hw = AVF_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 431         struct avf_adapter *ad =
 432                 AVF_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
 433         struct avf_tx_queue *txq;
 434         const struct rte_memzone *mz;
 435         uint32_t ring_size;
 436         uint16_t tx_rs_thresh, tx_free_thresh;
 437         uint16_t i, base, bsf, tc_mapping;
 438         uint64_t offloads;
 439
 440         PMD_INIT_FUNC_TRACE();
 441
 442         offloads = tx_conf->offloads | dev->data->dev_conf.txmode.offloads;
 443
 444         if (nb_desc % AVF_ALIGN_RING_DESC != 0 ||
 445             nb_desc > AVF_MAX_RING_DESC ||
 446             nb_desc < AVF_MIN_RING_DESC) {
 447                 PMD_INIT_LOG(ERR, "Number (%u) of transmit descriptors is "
 448                             "invalid", nb_desc);
 449                 return -EINVAL;
 450         }
 451
 452         tx_rs_thresh = (uint16_t)((tx_conf->tx_rs_thresh) ?
 453                 tx_conf->tx_rs_thresh : DEFAULT_TX_RS_THRESH);
 454         tx_free_thresh = (uint16_t)((tx_conf->tx_free_thresh) ?
 455                 tx_conf->tx_free_thresh : DEFAULT_TX_FREE_THRESH);
 456         check_tx_thresh(nb_desc, tx_rs_thresh, tx_rs_thresh);
 457
 458         /* Free memory if needed. */
 459         if (dev->data->tx_queues[queue_idx]) {
 460                 avf_dev_tx_queue_release(dev->data->tx_queues[queue_idx]);
 461                 dev->data->tx_queues[queue_idx] = NULL;
 462         }
 463
 464         /* Allocate the TX queue data structure. */
 465         txq = rte_zmalloc_socket("avf txq",
 466                                  sizeof(struct avf_tx_queue),
 467                                  RTE_CACHE_LINE_SIZE,
 468                                  socket_id);
 469         if (!txq) {
 470                 PMD_INIT_LOG(ERR, "Failed to allocate memory for "
 471                              "tx queue structure");
 472                 return -ENOMEM;
 473         }
 474
 475         txq->nb_tx_desc = nb_desc;
 476         txq->rs_thresh = tx_rs_thresh;
 477         txq->free_thresh = tx_free_thresh;
 478         txq->queue_id = queue_idx;
 479         txq->port_id = dev->data->port_id;
 480         txq->offloads = offloads;
 481         txq->tx_deferred_start = tx_conf->tx_deferred_start;
 482
 483         /* Allocate software ring */
 484         txq->sw_ring =
 485                 rte_zmalloc_socket("avf tx sw ring",
 486                                    sizeof(struct avf_tx_entry) * nb_desc,
 487                                    RTE_CACHE_LINE_SIZE,
 488                                    socket_id);
 489         if (!txq->sw_ring) {
 490                 PMD_INIT_LOG(ERR, "Failed to allocate memory for SW TX ring");
 491                 rte_free(txq);
 492                 return -ENOMEM;
 493         }
 494
 495         /* Allocate TX hardware ring descriptors. */
 496         ring_size = sizeof(struct avf_tx_desc) * AVF_MAX_RING_DESC;
 497         ring_size = RTE_ALIGN(ring_size, AVF_DMA_MEM_ALIGN);
 498         mz = rte_eth_dma_zone_reserve(dev, "tx_ring", queue_idx,
 499                                       ring_size, AVF_RING_BASE_ALIGN,
 500                                       socket_id);
 501         if (!mz) {
 502                 PMD_INIT_LOG(ERR, "Failed to reserve DMA memory for TX");
 503                 rte_free(txq->sw_ring);
 504                 rte_free(txq);
 505                 return -ENOMEM;
 506         }
 507         txq->tx_ring_phys_addr = mz->iova;
 508         txq->tx_ring = (struct avf_tx_desc *)mz->addr;
 509
 510         txq->mz = mz;
 511         reset_tx_queue(txq);
 512         txq->q_set = TRUE;
 513         dev->data->tx_queues[queue_idx] = txq;
 514         txq->qtx_tail = hw->hw_addr + AVF_QTX_TAIL1(queue_idx);
 515         txq->ops = &def_txq_ops;
 516
 517 #ifdef RTE_LIBRTE_AVF_INC_VECTOR
 518         if (check_tx_vec_allow(txq) == FALSE)
 519                 ad->tx_vec_allowed = false;
 520 #endif
 521
 522         return 0;
 523 }
 524
 525 int
 526 avf_dev_rx_queue_start(struct rte_eth_dev *dev, uint16_t rx_queue_id)
 527 {
 528         struct avf_adapter *adapter =
 529                 AVF_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
 530         struct avf_hw *hw = AVF_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 531         struct avf_rx_queue *rxq;
 532         int err = 0;
 533
 534         PMD_DRV_FUNC_TRACE();
 535
 536         if (rx_queue_id >= dev->data->nb_rx_queues)
 537                 return -EINVAL;
 538
 539         rxq = dev->data->rx_queues[rx_queue_id];
 540
 541         err = alloc_rxq_mbufs(rxq);
 542         if (err) {
 543                 PMD_DRV_LOG(ERR, "Failed to allocate RX queue mbuf");
 544                 return err;
 545         }
 546
 547         rte_wmb();
 548
 549         /* Init the RX tail register. */
 550         AVF_PCI_REG_WRITE(rxq->qrx_tail, rxq->nb_rx_desc - 1);
 551         AVF_WRITE_FLUSH(hw);
 552
 553         /* Ready to switch the queue on */
 554         err = avf_switch_queue(adapter, rx_queue_id, TRUE, TRUE);
 555         if (err)
 556                 PMD_DRV_LOG(ERR, "Failed to switch RX queue %u on",
 557                             rx_queue_id);
 558         else
 559                 dev->data->rx_queue_state[rx_queue_id] =
 560                         RTE_ETH_QUEUE_STATE_STARTED;
 561
 562         return err;
 563 }
 564
 565 int
 566 avf_dev_tx_queue_start(struct rte_eth_dev *dev, uint16_t tx_queue_id)
 567 {
 568         struct avf_adapter *adapter =
 569                 AVF_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
 570         struct avf_hw *hw = AVF_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 571         struct avf_tx_queue *txq;
 572         int err = 0;
 573
 574         PMD_DRV_FUNC_TRACE();
 575
 576         if (tx_queue_id >= dev->data->nb_tx_queues)
 577                 return -EINVAL;
 578
 579         txq = dev->data->tx_queues[tx_queue_id];
 580
 581         /* Init the RX tail register. */
 582         AVF_PCI_REG_WRITE(txq->qtx_tail, 0);
 583         AVF_WRITE_FLUSH(hw);
 584
 585         /* Ready to switch the queue on */
 586         err = avf_switch_queue(adapter, tx_queue_id, FALSE, TRUE);
 587
 588         if (err)
 589                 PMD_DRV_LOG(ERR, "Failed to switch TX queue %u on",
 590                             tx_queue_id);
 591         else
 592                 dev->data->tx_queue_state[tx_queue_id] =
 593                         RTE_ETH_QUEUE_STATE_STARTED;
 594
 595         return err;
 596 }
 597
 598 int
 599 avf_dev_rx_queue_stop(struct rte_eth_dev *dev, uint16_t rx_queue_id)
 600 {
 601         struct avf_adapter *adapter =
 602                 AVF_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
 603         struct avf_rx_queue *rxq;
 604         int err;
 605
 606         PMD_DRV_FUNC_TRACE();
 607
 608         if (rx_queue_id >= dev->data->nb_rx_queues)
 609                 return -EINVAL;
 610
 611         err = avf_switch_queue(adapter, rx_queue_id, TRUE, FALSE);
 612         if (err) {
 613                 PMD_DRV_LOG(ERR, "Failed to switch RX queue %u off",
 614                             rx_queue_id);
 615                 return err;
 616         }
 617
 618         rxq = dev->data->rx_queues[rx_queue_id];
 619         rxq->ops->release_mbufs(rxq);
 620         reset_rx_queue(rxq);
 621         dev->data->rx_queue_state[rx_queue_id] = RTE_ETH_QUEUE_STATE_STOPPED;
 622
 623         return 0;
 624 }
 625
 626 int
 627 avf_dev_tx_queue_stop(struct rte_eth_dev *dev, uint16_t tx_queue_id)
 628 {
 629         struct avf_adapter *adapter =
 630                 AVF_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
 631         struct avf_tx_queue *txq;
 632         int err;
 633
 634         PMD_DRV_FUNC_TRACE();
 635
 636         if (tx_queue_id >= dev->data->nb_tx_queues)
 637                 return -EINVAL;
 638
 639         err = avf_switch_queue(adapter, tx_queue_id, FALSE, FALSE);
 640         if (err) {
 641                 PMD_DRV_LOG(ERR, "Failed to switch TX queue %u off",
 642                             tx_queue_id);
 643                 return err;
 644         }
 645
 646         txq = dev->data->tx_queues[tx_queue_id];
 647         txq->ops->release_mbufs(txq);
 648         reset_tx_queue(txq);
 649         dev->data->tx_queue_state[tx_queue_id] = RTE_ETH_QUEUE_STATE_STOPPED;
 650
 651         return 0;
 652 }
 653
 654 void
 655 avf_dev_rx_queue_release(void *rxq)
 656 {
 657         struct avf_rx_queue *q = (struct avf_rx_queue *)rxq;
 658
 659         if (!q)
 660                 return;
 661
 662         q->ops->release_mbufs(q);
 663         rte_free(q->sw_ring);
 664         rte_memzone_free(q->mz);
 665         rte_free(q);
 666 }
 667
 668 void
 669 avf_dev_tx_queue_release(void *txq)
 670 {
 671         struct avf_tx_queue *q = (struct avf_tx_queue *)txq;
 672
 673         if (!q)
 674                 return;
 675
 676         q->ops->release_mbufs(q);
 677         rte_free(q->sw_ring);
 678         rte_memzone_free(q->mz);
 679         rte_free(q);
 680 }
 681
 682 void
 683 avf_stop_queues(struct rte_eth_dev *dev)
 684 {
 685         struct avf_adapter *adapter =
 686                 AVF_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
 687         struct avf_rx_queue *rxq;
 688         struct avf_tx_queue *txq;
 689         int ret, i;
 690
 691         /* Stop All queues */
 692         ret = avf_disable_queues(adapter);
 693         if (ret)
 694                 PMD_DRV_LOG(WARNING, "Fail to stop queues");
 695
 696         for (i = 0; i < dev->data->nb_tx_queues; i++) {
 697                 txq = dev->data->tx_queues[i];
 698                 if (!txq)
 699                         continue;
 700                 txq->ops->release_mbufs(txq);
 701                 reset_tx_queue(txq);
 702                 dev->data->tx_queue_state[i] = RTE_ETH_QUEUE_STATE_STOPPED;
 703         }
 704         for (i = 0; i < dev->data->nb_rx_queues; i++) {
 705                 rxq = dev->data->rx_queues[i];
 706                 if (!rxq)
 707                         continue;
 708                 rxq->ops->release_mbufs(rxq);
 709                 reset_rx_queue(rxq);
 710                 dev->data->rx_queue_state[i] = RTE_ETH_QUEUE_STATE_STOPPED;
 711         }
 712 }
 713
 714 static inline void
 715 avf_rxd_to_vlan_tci(struct rte_mbuf *mb, volatile union avf_rx_desc *rxdp)
 716 {
 717         if (rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len) &
 718                 (1 << AVF_RX_DESC_STATUS_L2TAG1P_SHIFT)) {
 719                 mb->ol_flags |= PKT_RX_VLAN | PKT_RX_VLAN_STRIPPED;
 720                 mb->vlan_tci =
 721                         rte_le_to_cpu_16(rxdp->wb.qword0.lo_dword.l2tag1);
 722         } else {
 723                 mb->vlan_tci = 0;
 724         }
 725 }
 726
 727 /* Translate the rx descriptor status and error fields to pkt flags */
 728 static inline uint64_t
 729 avf_rxd_to_pkt_flags(uint64_t qword)
 730 {
 731         uint64_t flags;
 732         uint64_t error_bits = (qword >> AVF_RXD_QW1_ERROR_SHIFT);
 733
 734 #define AVF_RX_ERR_BITS 0x3f
 735
 736         /* Check if RSS_HASH */
 737         flags = (((qword >> AVF_RX_DESC_STATUS_FLTSTAT_SHIFT) &
 738                                         AVF_RX_DESC_FLTSTAT_RSS_HASH) ==
 739                         AVF_RX_DESC_FLTSTAT_RSS_HASH) ? PKT_RX_RSS_HASH : 0;
 740
 741         if (likely((error_bits & AVF_RX_ERR_BITS) == 0)) {
 742                 flags |= (PKT_RX_IP_CKSUM_GOOD | PKT_RX_L4_CKSUM_GOOD);
 743                 return flags;
 744         }
 745
 746         if (unlikely(error_bits & (1 << AVF_RX_DESC_ERROR_IPE_SHIFT)))
 747                 flags |= PKT_RX_IP_CKSUM_BAD;
 748         else
 749                 flags |= PKT_RX_IP_CKSUM_GOOD;
 750
 751         if (unlikely(error_bits & (1 << AVF_RX_DESC_ERROR_L4E_SHIFT)))
 752                 flags |= PKT_RX_L4_CKSUM_BAD;
 753         else
 754                 flags |= PKT_RX_L4_CKSUM_GOOD;
 755
 756         /* TODO: Oversize error bit is not processed here */
 757
 758         return flags;
 759 }
 760
 761 /* implement recv_pkts */
 762 uint16_t
 763 avf_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t nb_pkts)
 764 {
 765         volatile union avf_rx_desc *rx_ring;
 766         volatile union avf_rx_desc *rxdp;
 767         struct avf_rx_queue *rxq;
 768         union avf_rx_desc rxd;
 769         struct rte_mbuf *rxe;
 770         struct rte_eth_dev *dev;
 771         struct rte_mbuf *rxm;
 772         struct rte_mbuf *nmb;
 773         uint16_t nb_rx;
 774         uint32_t rx_status;
 775         uint64_t qword1;
 776         uint16_t rx_packet_len;
 777         uint16_t rx_id, nb_hold;
 778         uint64_t dma_addr;
 779         uint64_t pkt_flags;
 780         static const uint32_t ptype_tbl[UINT8_MAX + 1] __rte_cache_aligned = {
 781                 /* [0] reserved */
 782                 [1] = RTE_PTYPE_L2_ETHER,
 783                 /* [2] - [21] reserved */
 784                 [22] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 785                         RTE_PTYPE_L4_FRAG,
 786                 [23] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 787                         RTE_PTYPE_L4_NONFRAG,
 788                 [24] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 789                         RTE_PTYPE_L4_UDP,
 790                 /* [25] reserved */
 791                 [26] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 792                         RTE_PTYPE_L4_TCP,
 793                 [27] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 794                         RTE_PTYPE_L4_SCTP,
 795                 [28] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 796                         RTE_PTYPE_L4_ICMP,
 797                 /* All others reserved */
 798         };
 799
 800         nb_rx = 0;
 801         nb_hold = 0;
 802         rxq = rx_queue;
 803         rx_id = rxq->rx_tail;
 804         rx_ring = rxq->rx_ring;
 805
 806         while (nb_rx < nb_pkts) {
 807                 rxdp = &rx_ring[rx_id];
 808                 qword1 = rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len);
 809                 rx_status = (qword1 & AVF_RXD_QW1_STATUS_MASK) >>
 810                             AVF_RXD_QW1_STATUS_SHIFT;
 811
 812                 /* Check the DD bit first */
 813                 if (!(rx_status & (1 << AVF_RX_DESC_STATUS_DD_SHIFT)))
 814                         break;
 815                 AVF_DUMP_RX_DESC(rxq, rxdp, rx_id);
 816
 817                 nmb = rte_mbuf_raw_alloc(rxq->mp);
 818                 if (unlikely(!nmb)) {
 819                         dev = &rte_eth_devices[rxq->port_id];
 820                         dev->data->rx_mbuf_alloc_failed++;
 821                         PMD_RX_LOG(DEBUG, "RX mbuf alloc failed port_id=%u "
 822                                    "queue_id=%u", rxq->port_id, rxq->queue_id);
 823                         break;
 824                 }
 825
 826                 rxd = *rxdp;
 827                 nb_hold++;
 828                 rxe = rxq->sw_ring[rx_id];
 829                 rx_id++;
 830                 if (unlikely(rx_id == rxq->nb_rx_desc))
 831                         rx_id = 0;
 832
 833                 /* Prefetch next mbuf */
 834                 rte_prefetch0(rxq->sw_ring[rx_id]);
 835
 836                 /* When next RX descriptor is on a cache line boundary,
 837                  * prefetch the next 4 RX descriptors and next 8 pointers
 838                  * to mbufs.
 839                  */
 840                 if ((rx_id & 0x3) == 0) {
 841                         rte_prefetch0(&rx_ring[rx_id]);
 842                         rte_prefetch0(rxq->sw_ring[rx_id]);
 843                 }
 844                 rxm = rxe;
 845                 rxe = nmb;
 846                 dma_addr =
 847                         rte_cpu_to_le_64(rte_mbuf_data_iova_default(nmb));
 848                 rxdp->read.hdr_addr = 0;
 849                 rxdp->read.pkt_addr = dma_addr;
 850
 851                 rx_packet_len = ((qword1 & AVF_RXD_QW1_LENGTH_PBUF_MASK) >>
 852                                 AVF_RXD_QW1_LENGTH_PBUF_SHIFT) - rxq->crc_len;
 853
 854                 rxm->data_off = RTE_PKTMBUF_HEADROOM;
 855                 rte_prefetch0(RTE_PTR_ADD(rxm->buf_addr, RTE_PKTMBUF_HEADROOM));
 856                 rxm->nb_segs = 1;
 857                 rxm->next = NULL;
 858                 rxm->pkt_len = rx_packet_len;
 859                 rxm->data_len = rx_packet_len;
 860                 rxm->port = rxq->port_id;
 861                 rxm->ol_flags = 0;
 862                 avf_rxd_to_vlan_tci(rxm, &rxd);
 863                 pkt_flags = avf_rxd_to_pkt_flags(qword1);
 864                 rxm->packet_type =
 865                         ptype_tbl[(uint8_t)((qword1 &
 866                         AVF_RXD_QW1_PTYPE_MASK) >> AVF_RXD_QW1_PTYPE_SHIFT)];
 867
 868                 if (pkt_flags & PKT_RX_RSS_HASH)
 869                         rxm->hash.rss =
 870                                 rte_le_to_cpu_32(rxd.wb.qword0.hi_dword.rss);
 871
 872                 rxm->ol_flags |= pkt_flags;
 873
 874                 rx_pkts[nb_rx++] = rxm;
 875         }
 876         rxq->rx_tail = rx_id;
 877
 878         /* If the number of free RX descriptors is greater than the RX free
 879          * threshold of the queue, advance the receive tail register of queue.
 880          * Update that register with the value of the last processed RX
 881          * descriptor minus 1.
 882          */
 883         nb_hold = (uint16_t)(nb_hold + rxq->nb_rx_hold);
 884         if (nb_hold > rxq->rx_free_thresh) {
 885                 PMD_RX_LOG(DEBUG, "port_id=%u queue_id=%u rx_tail=%u "
 886                            "nb_hold=%u nb_rx=%u",
 887                            rxq->port_id, rxq->queue_id,
 888                            rx_id, nb_hold, nb_rx);
 889                 rx_id = (uint16_t)((rx_id == 0) ?
 890                         (rxq->nb_rx_desc - 1) : (rx_id - 1));
 891                 AVF_PCI_REG_WRITE(rxq->qrx_tail, rx_id);
 892                 nb_hold = 0;
 893         }
 894         rxq->nb_rx_hold = nb_hold;
 895
 896         return nb_rx;
 897 }
 898
 899 /* implement recv_scattered_pkts  */
 900 uint16_t
 901 avf_recv_scattered_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,
 902                         uint16_t nb_pkts)
 903 {
 904         struct avf_rx_queue *rxq = rx_queue;
 905         union avf_rx_desc rxd;
 906         struct rte_mbuf *rxe;
 907         struct rte_mbuf *first_seg = rxq->pkt_first_seg;
 908         struct rte_mbuf *last_seg = rxq->pkt_last_seg;
 909         struct rte_mbuf *nmb, *rxm;
 910         uint16_t rx_id = rxq->rx_tail;
 911         uint16_t nb_rx = 0, nb_hold = 0, rx_packet_len;
 912         struct rte_eth_dev *dev;
 913         uint32_t rx_status;
 914         uint64_t qword1;
 915         uint64_t dma_addr;
 916         uint64_t pkt_flags;
 917
 918         volatile union avf_rx_desc *rx_ring = rxq->rx_ring;
 919         volatile union avf_rx_desc *rxdp;
 920         static const uint32_t ptype_tbl[UINT8_MAX + 1] __rte_cache_aligned = {
 921                 /* [0] reserved */
 922                 [1] = RTE_PTYPE_L2_ETHER,
 923                 /* [2] - [21] reserved */
 924                 [22] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 925                         RTE_PTYPE_L4_FRAG,
 926                 [23] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 927                         RTE_PTYPE_L4_NONFRAG,
 928                 [24] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 929                         RTE_PTYPE_L4_UDP,
 930                 /* [25] reserved */
 931                 [26] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 932                         RTE_PTYPE_L4_TCP,
 933                 [27] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 934                         RTE_PTYPE_L4_SCTP,
 935                 [28] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 936                         RTE_PTYPE_L4_ICMP,
 937                 /* All others reserved */
 938         };
 939
 940         while (nb_rx < nb_pkts) {
 941                 rxdp = &rx_ring[rx_id];
 942                 qword1 = rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len);
 943                 rx_status = (qword1 & AVF_RXD_QW1_STATUS_MASK) >>
 944                             AVF_RXD_QW1_STATUS_SHIFT;
 945
 946                 /* Check the DD bit */
 947                 if (!(rx_status & (1 << AVF_RX_DESC_STATUS_DD_SHIFT)))
 948                         break;
 949                 AVF_DUMP_RX_DESC(rxq, rxdp, rx_id);
 950
 951                 nmb = rte_mbuf_raw_alloc(rxq->mp);
 952                 if (unlikely(!nmb)) {
 953                         PMD_RX_LOG(DEBUG, "RX mbuf alloc failed port_id=%u "
 954                                    "queue_id=%u", rxq->port_id, rxq->queue_id);
 955                         dev = &rte_eth_devices[rxq->port_id];
 956                         dev->data->rx_mbuf_alloc_failed++;
 957                         break;
 958                 }
 959
 960                 rxd = *rxdp;
 961                 nb_hold++;
 962                 rxe = rxq->sw_ring[rx_id];
 963                 rx_id++;
 964                 if (rx_id == rxq->nb_rx_desc)
 965                         rx_id = 0;
 966
 967                 /* Prefetch next mbuf */
 968                 rte_prefetch0(rxq->sw_ring[rx_id]);
 969
 970                 /* When next RX descriptor is on a cache line boundary,
 971                  * prefetch the next 4 RX descriptors and next 8 pointers
 972                  * to mbufs.
 973                  */
 974                 if ((rx_id & 0x3) == 0) {
 975                         rte_prefetch0(&rx_ring[rx_id]);
 976                         rte_prefetch0(rxq->sw_ring[rx_id]);
 977                 }
 978
 979                 rxm = rxe;
 980                 rxe = nmb;
 981                 dma_addr =
 982                         rte_cpu_to_le_64(rte_mbuf_data_iova_default(nmb));
 983
 984                 /* Set data buffer address and data length of the mbuf */
 985                 rxdp->read.hdr_addr = 0;
 986                 rxdp->read.pkt_addr = dma_addr;
 987                 rx_packet_len = (qword1 & AVF_RXD_QW1_LENGTH_PBUF_MASK) >>
 988                                  AVF_RXD_QW1_LENGTH_PBUF_SHIFT;
 989                 rxm->data_len = rx_packet_len;
 990                 rxm->data_off = RTE_PKTMBUF_HEADROOM;
 991
 992                 /* If this is the first buffer of the received packet, set the
 993                  * pointer to the first mbuf of the packet and initialize its
 994                  * context. Otherwise, update the total length and the number
 995                  * of segments of the current scattered packet, and update the
 996                  * pointer to the last mbuf of the current packet.
 997                  */
 998                 if (!first_seg) {
 999                         first_seg = rxm;
1000                         first_seg->nb_segs = 1;
1001                         first_seg->pkt_len = rx_packet_len;
1002                 } else {
1003                         first_seg->pkt_len =
1004                                 (uint16_t)(first_seg->pkt_len +
1005                                                 rx_packet_len);
1006                         first_seg->nb_segs++;
1007                         last_seg->next = rxm;
1008                 }
1009
1010                 /* If this is not the last buffer of the received packet,
1011                  * update the pointer to the last mbuf of the current scattered
1012                  * packet and continue to parse the RX ring.
1013                  */
1014                 if (!(rx_status & (1 << AVF_RX_DESC_STATUS_EOF_SHIFT))) {
1015                         last_seg = rxm;
1016                         continue;
1017                 }
1018
1019                 /* This is the last buffer of the received packet. If the CRC
1020                  * is not stripped by the hardware:
1021                  *  - Subtract the CRC length from the total packet length.
1022                  *  - If the last buffer only contains the whole CRC or a part
1023                  *  of it, free the mbuf associated to the last buffer. If part
1024                  *  of the CRC is also contained in the previous mbuf, subtract
1025                  *  the length of that CRC part from the data length of the
1026                  *  previous mbuf.
1027                  */
1028                 rxm->next = NULL;
1029                 if (unlikely(rxq->crc_len > 0)) {
1030                         first_seg->pkt_len -= ETHER_CRC_LEN;
1031                         if (rx_packet_len <= ETHER_CRC_LEN) {
1032                                 rte_pktmbuf_free_seg(rxm);
1033                                 first_seg->nb_segs--;
1034                                 last_seg->data_len =
1035                                         (uint16_t)(last_seg->data_len -
1036                                         (ETHER_CRC_LEN - rx_packet_len));
1037                                 last_seg->next = NULL;
1038                         } else
1039                                 rxm->data_len = (uint16_t)(rx_packet_len -
1040                                                                 ETHER_CRC_LEN);
1041                 }
1042
1043                 first_seg->port = rxq->port_id;
1044                 first_seg->ol_flags = 0;
1045                 avf_rxd_to_vlan_tci(first_seg, &rxd);
1046                 pkt_flags = avf_rxd_to_pkt_flags(qword1);
1047                 first_seg->packet_type =
1048                         ptype_tbl[(uint8_t)((qword1 &
1049                         AVF_RXD_QW1_PTYPE_MASK) >> AVF_RXD_QW1_PTYPE_SHIFT)];
1050
1051                 if (pkt_flags & PKT_RX_RSS_HASH)
1052                         first_seg->hash.rss =
1053                                 rte_le_to_cpu_32(rxd.wb.qword0.hi_dword.rss);
1054
1055                 first_seg->ol_flags |= pkt_flags;
1056
1057                 /* Prefetch data of first segment, if configured to do so. */
1058                 rte_prefetch0(RTE_PTR_ADD(first_seg->buf_addr,
1059                                           first_seg->data_off));
1060                 rx_pkts[nb_rx++] = first_seg;
1061                 first_seg = NULL;
1062         }
1063
1064         /* Record index of the next RX descriptor to probe. */
1065         rxq->rx_tail = rx_id;
1066         rxq->pkt_first_seg = first_seg;
1067         rxq->pkt_last_seg = last_seg;
1068
1069         /* If the number of free RX descriptors is greater than the RX free
1070          * threshold of the queue, advance the Receive Descriptor Tail (RDT)
1071          * register. Update the RDT with the value of the last processed RX
1072          * descriptor minus 1, to guarantee that the RDT register is never
1073          * equal to the RDH register, which creates a "full" ring situtation
1074          * from the hardware point of view.
1075          */
1076         nb_hold = (uint16_t)(nb_hold + rxq->nb_rx_hold);
1077         if (nb_hold > rxq->rx_free_thresh) {
1078                 PMD_RX_LOG(DEBUG, "port_id=%u queue_id=%u rx_tail=%u "
1079                            "nb_hold=%u nb_rx=%u",
1080                            rxq->port_id, rxq->queue_id,
1081                            rx_id, nb_hold, nb_rx);
1082                 rx_id = (uint16_t)(rx_id == 0 ?
1083                         (rxq->nb_rx_desc - 1) : (rx_id - 1));
1084                 AVF_PCI_REG_WRITE(rxq->qrx_tail, rx_id);
1085                 nb_hold = 0;
1086         }
1087         rxq->nb_rx_hold = nb_hold;
1088
1089         return nb_rx;
1090 }
1091
1092 #define AVF_LOOK_AHEAD 8
1093 static inline int
1094 avf_rx_scan_hw_ring(struct avf_rx_queue *rxq)
1095 {
1096         volatile union avf_rx_desc *rxdp;
1097         struct rte_mbuf **rxep;
1098         struct rte_mbuf *mb;
1099         uint16_t pkt_len;
1100         uint64_t qword1;
1101         uint32_t rx_status;
1102         int32_t s[AVF_LOOK_AHEAD], nb_dd;
1103         int32_t i, j, nb_rx = 0;
1104         uint64_t pkt_flags;
1105         static const uint32_t ptype_tbl[UINT8_MAX + 1] __rte_cache_aligned = {
1106                 /* [0] reserved */
1107                 [1] = RTE_PTYPE_L2_ETHER,
1108                 /* [2] - [21] reserved */
1109                 [22] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
1110                         RTE_PTYPE_L4_FRAG,
1111                 [23] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
1112                         RTE_PTYPE_L4_NONFRAG,
1113                 [24] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
1114                         RTE_PTYPE_L4_UDP,
1115                 /* [25] reserved */
1116                 [26] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
1117                         RTE_PTYPE_L4_TCP,
1118                 [27] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
1119                         RTE_PTYPE_L4_SCTP,
1120                 [28] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
1121                         RTE_PTYPE_L4_ICMP,
1122                 /* All others reserved */
1123         };
1124
1125         rxdp = &rxq->rx_ring[rxq->rx_tail];
1126         rxep = &rxq->sw_ring[rxq->rx_tail];
1127
1128         qword1 = rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len);
1129         rx_status = (qword1 & AVF_RXD_QW1_STATUS_MASK) >>
1130                     AVF_RXD_QW1_STATUS_SHIFT;
1131
1132         /* Make sure there is at least 1 packet to receive */
1133         if (!(rx_status & (1 << AVF_RX_DESC_STATUS_DD_SHIFT)))
1134                 return 0;
1135
1136         /* Scan LOOK_AHEAD descriptors at a time to determine which
1137          * descriptors reference packets that are ready to be received.
1138          */
1139         for (i = 0; i < AVF_RX_MAX_BURST; i += AVF_LOOK_AHEAD,
1140              rxdp += AVF_LOOK_AHEAD, rxep += AVF_LOOK_AHEAD) {
1141                 /* Read desc statuses backwards to avoid race condition */
1142                 for (j = AVF_LOOK_AHEAD - 1; j >= 0; j--) {
1143                         qword1 = rte_le_to_cpu_64(
1144                                 rxdp[j].wb.qword1.status_error_len);
1145                         s[j] = (qword1 & AVF_RXD_QW1_STATUS_MASK) >>
1146                                AVF_RXD_QW1_STATUS_SHIFT;
1147                 }
1148
1149                 rte_smp_rmb();
1150
1151                 /* Compute how many status bits were set */
1152                 for (j = 0, nb_dd = 0; j < AVF_LOOK_AHEAD; j++)
1153                         nb_dd += s[j] & (1 << AVF_RX_DESC_STATUS_DD_SHIFT);
1154
1155                 nb_rx += nb_dd;
1156
1157                 /* Translate descriptor info to mbuf parameters */
1158                 for (j = 0; j < nb_dd; j++) {
1159                         AVF_DUMP_RX_DESC(rxq, &rxdp[j],
1160                                          rxq->rx_tail + i * AVF_LOOK_AHEAD + j);
1161
1162                         mb = rxep[j];
1163                         qword1 = rte_le_to_cpu_64
1164                                         (rxdp[j].wb.qword1.status_error_len);
1165                         pkt_len = ((qword1 & AVF_RXD_QW1_LENGTH_PBUF_MASK) >>
1166                                   AVF_RXD_QW1_LENGTH_PBUF_SHIFT) - rxq->crc_len;
1167                         mb->data_len = pkt_len;
1168                         mb->pkt_len = pkt_len;
1169                         mb->ol_flags = 0;
1170                         avf_rxd_to_vlan_tci(mb, &rxdp[j]);
1171                         pkt_flags = avf_rxd_to_pkt_flags(qword1);
1172                         mb->packet_type =
1173                                 ptype_tbl[(uint8_t)((qword1 &
1174                                 AVF_RXD_QW1_PTYPE_MASK) >>
1175                                 AVF_RXD_QW1_PTYPE_SHIFT)];
1176
1177                         if (pkt_flags & PKT_RX_RSS_HASH)
1178                                 mb->hash.rss = rte_le_to_cpu_32(
1179                                         rxdp[j].wb.qword0.hi_dword.rss);
1180
1181                         mb->ol_flags |= pkt_flags;
1182                 }
1183
1184                 for (j = 0; j < AVF_LOOK_AHEAD; j++)
1185                         rxq->rx_stage[i + j] = rxep[j];
1186
1187                 if (nb_dd != AVF_LOOK_AHEAD)
1188                         break;
1189         }
1190
1191         /* Clear software ring entries */
1192         for (i = 0; i < nb_rx; i++)
1193                 rxq->sw_ring[rxq->rx_tail + i] = NULL;
1194
1195         return nb_rx;
1196 }
1197
1198 static inline uint16_t
1199 avf_rx_fill_from_stage(struct avf_rx_queue *rxq,
1200                        struct rte_mbuf **rx_pkts,
1201                        uint16_t nb_pkts)
1202 {
1203         uint16_t i;
1204         struct rte_mbuf **stage = &rxq->rx_stage[rxq->rx_next_avail];
1205
1206         nb_pkts = (uint16_t)RTE_MIN(nb_pkts, rxq->rx_nb_avail);
1207
1208         for (i = 0; i < nb_pkts; i++)
1209                 rx_pkts[i] = stage[i];
1210
1211         rxq->rx_nb_avail = (uint16_t)(rxq->rx_nb_avail - nb_pkts);
1212         rxq->rx_next_avail = (uint16_t)(rxq->rx_next_avail + nb_pkts);
1213
1214         return nb_pkts;
1215 }
1216
1217 static inline int
1218 avf_rx_alloc_bufs(struct avf_rx_queue *rxq)
1219 {
1220         volatile union avf_rx_desc *rxdp;
1221         struct rte_mbuf **rxep;
1222         struct rte_mbuf *mb;
1223         uint16_t alloc_idx, i;
1224         uint64_t dma_addr;
1225         int diag;
1226
1227         /* Allocate buffers in bulk */
1228         alloc_idx = (uint16_t)(rxq->rx_free_trigger -
1229                                 (rxq->rx_free_thresh - 1));
1230         rxep = &rxq->sw_ring[alloc_idx];
1231         diag = rte_mempool_get_bulk(rxq->mp, (void *)rxep,
1232                                     rxq->rx_free_thresh);
1233         if (unlikely(diag != 0)) {
1234                 PMD_RX_LOG(ERR, "Failed to get mbufs in bulk");
1235                 return -ENOMEM;
1236         }
1237
1238         rxdp = &rxq->rx_ring[alloc_idx];
1239         for (i = 0; i < rxq->rx_free_thresh; i++) {
1240                 if (likely(i < (rxq->rx_free_thresh - 1)))
1241                         /* Prefetch next mbuf */
1242                         rte_prefetch0(rxep[i + 1]);
1243
1244                 mb = rxep[i];
1245                 rte_mbuf_refcnt_set(mb, 1);
1246                 mb->next = NULL;
1247                 mb->data_off = RTE_PKTMBUF_HEADROOM;
1248                 mb->nb_segs = 1;
1249                 mb->port = rxq->port_id;
1250                 dma_addr = rte_cpu_to_le_64(rte_mbuf_data_iova_default(mb));
1251                 rxdp[i].read.hdr_addr = 0;
1252                 rxdp[i].read.pkt_addr = dma_addr;
1253         }
1254
1255         /* Update rx tail register */
1256         rte_wmb();
1257         AVF_PCI_REG_WRITE_RELAXED(rxq->qrx_tail, rxq->rx_free_trigger);
1258
1259         rxq->rx_free_trigger =
1260                 (uint16_t)(rxq->rx_free_trigger + rxq->rx_free_thresh);
1261         if (rxq->rx_free_trigger >= rxq->nb_rx_desc)
1262                 rxq->rx_free_trigger = (uint16_t)(rxq->rx_free_thresh - 1);
1263
1264         return 0;
1265 }
1266
1267 static inline uint16_t
1268 rx_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t nb_pkts)
1269 {
1270         struct avf_rx_queue *rxq = (struct avf_rx_queue *)rx_queue;
1271         struct rte_eth_dev *dev;
1272         uint16_t nb_rx = 0;
1273
1274         if (!nb_pkts)
1275                 return 0;
1276
1277         if (rxq->rx_nb_avail)
1278                 return avf_rx_fill_from_stage(rxq, rx_pkts, nb_pkts);
1279
1280         nb_rx = (uint16_t)avf_rx_scan_hw_ring(rxq);
1281         rxq->rx_next_avail = 0;
1282         rxq->rx_nb_avail = nb_rx;
1283         rxq->rx_tail = (uint16_t)(rxq->rx_tail + nb_rx);
1284
1285         if (rxq->rx_tail > rxq->rx_free_trigger) {
1286                 if (avf_rx_alloc_bufs(rxq) != 0) {
1287                         uint16_t i, j;
1288
1289                         /* TODO: count rx_mbuf_alloc_failed here */
1290
1291                         rxq->rx_nb_avail = 0;
1292                         rxq->rx_tail = (uint16_t)(rxq->rx_tail - nb_rx);
1293                         for (i = 0, j = rxq->rx_tail; i < nb_rx; i++, j++)
1294                                 rxq->sw_ring[j] = rxq->rx_stage[i];
1295
1296                         return 0;
1297                 }
1298         }
1299
1300         if (rxq->rx_tail >= rxq->nb_rx_desc)
1301                 rxq->rx_tail = 0;
1302
1303         PMD_RX_LOG(DEBUG, "port_id=%u queue_id=%u rx_tail=%u, nb_rx=%u",
1304                    rxq->port_id, rxq->queue_id,
1305                    rxq->rx_tail, nb_rx);
1306
1307         if (rxq->rx_nb_avail)
1308                 return avf_rx_fill_from_stage(rxq, rx_pkts, nb_pkts);
1309
1310         return 0;
1311 }
1312
1313 static uint16_t
1314 avf_recv_pkts_bulk_alloc(void *rx_queue,
1315                          struct rte_mbuf **rx_pkts,
1316                          uint16_t nb_pkts)
1317 {
1318         uint16_t nb_rx = 0, n, count;
1319
1320         if (unlikely(nb_pkts == 0))
1321                 return 0;
1322
1323         if (likely(nb_pkts <= AVF_RX_MAX_BURST))
1324                 return rx_recv_pkts(rx_queue, rx_pkts, nb_pkts);
1325
1326         while (nb_pkts) {
1327                 n = RTE_MIN(nb_pkts, AVF_RX_MAX_BURST);
1328                 count = rx_recv_pkts(rx_queue, &rx_pkts[nb_rx], n);
1329                 nb_rx = (uint16_t)(nb_rx + count);
1330                 nb_pkts = (uint16_t)(nb_pkts - count);
1331                 if (count < n)
1332                         break;
1333         }
1334
1335         return nb_rx;
1336 }
1337
1338 static inline int
1339 avf_xmit_cleanup(struct avf_tx_queue *txq)
1340 {
1341         struct avf_tx_entry *sw_ring = txq->sw_ring;
1342         uint16_t last_desc_cleaned = txq->last_desc_cleaned;
1343         uint16_t nb_tx_desc = txq->nb_tx_desc;
1344         uint16_t desc_to_clean_to;
1345         uint16_t nb_tx_to_clean;
1346
1347         volatile struct avf_tx_desc *txd = txq->tx_ring;
1348
1349         desc_to_clean_to = (uint16_t)(last_desc_cleaned + txq->rs_thresh);
1350         if (desc_to_clean_to >= nb_tx_desc)
1351                 desc_to_clean_to = (uint16_t)(desc_to_clean_to - nb_tx_desc);
1352
1353         desc_to_clean_to = sw_ring[desc_to_clean_to].last_id;
1354         if ((txd[desc_to_clean_to].cmd_type_offset_bsz &
1355                         rte_cpu_to_le_64(AVF_TXD_QW1_DTYPE_MASK)) !=
1356                         rte_cpu_to_le_64(AVF_TX_DESC_DTYPE_DESC_DONE)) {
1357                 PMD_TX_FREE_LOG(DEBUG, "TX descriptor %4u is not done "
1358                                 "(port=%d queue=%d)", desc_to_clean_to,
1359                                 txq->port_id, txq->queue_id);
1360                 return -1;
1361         }
1362
1363         if (last_desc_cleaned > desc_to_clean_to)
1364                 nb_tx_to_clean = (uint16_t)((nb_tx_desc - last_desc_cleaned) +
1365                                                         desc_to_clean_to);
1366         else
1367                 nb_tx_to_clean = (uint16_t)(desc_to_clean_to -
1368                                         last_desc_cleaned);
1369
1370         txd[desc_to_clean_to].cmd_type_offset_bsz = 0;
1371
1372         txq->last_desc_cleaned = desc_to_clean_to;
1373         txq->nb_free = (uint16_t)(txq->nb_free + nb_tx_to_clean);
1374
1375         return 0;
1376 }
1377
1378 /* Check if the context descriptor is needed for TX offloading */
1379 static inline uint16_t
1380 avf_calc_context_desc(uint64_t flags)
1381 {
1382         static uint64_t mask = PKT_TX_TCP_SEG;
1383
1384         return (flags & mask) ? 1 : 0;
1385 }
1386
1387 static inline void
1388 avf_txd_enable_checksum(uint64_t ol_flags,
1389                         uint32_t *td_cmd,
1390                         uint32_t *td_offset,
1391                         union avf_tx_offload tx_offload)
1392 {
1393         /* Set MACLEN */
1394         *td_offset |= (tx_offload.l2_len >> 1) <<
1395                       AVF_TX_DESC_LENGTH_MACLEN_SHIFT;
1396
1397         /* Enable L3 checksum offloads */
1398         if (ol_flags & PKT_TX_IP_CKSUM) {
1399                 *td_cmd |= AVF_TX_DESC_CMD_IIPT_IPV4_CSUM;
1400                 *td_offset |= (tx_offload.l3_len >> 2) <<
1401                               AVF_TX_DESC_LENGTH_IPLEN_SHIFT;
1402         } else if (ol_flags & PKT_TX_IPV4) {
1403                 *td_cmd |= AVF_TX_DESC_CMD_IIPT_IPV4;
1404                 *td_offset |= (tx_offload.l3_len >> 2) <<
1405                               AVF_TX_DESC_LENGTH_IPLEN_SHIFT;
1406         } else if (ol_flags & PKT_TX_IPV6) {
1407                 *td_cmd |= AVF_TX_DESC_CMD_IIPT_IPV6;
1408                 *td_offset |= (tx_offload.l3_len >> 2) <<
1409                               AVF_TX_DESC_LENGTH_IPLEN_SHIFT;
1410         }
1411
1412         if (ol_flags & PKT_TX_TCP_SEG) {
1413                 *td_cmd |= AVF_TX_DESC_CMD_L4T_EOFT_TCP;
1414                 *td_offset |= (tx_offload.l4_len >> 2) <<
1415                               AVF_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
1416                 return;
1417         }
1418
1419         /* Enable L4 checksum offloads */
1420         switch (ol_flags & PKT_TX_L4_MASK) {
1421         case PKT_TX_TCP_CKSUM:
1422                 *td_cmd |= AVF_TX_DESC_CMD_L4T_EOFT_TCP;
1423                 *td_offset |= (sizeof(struct tcp_hdr) >> 2) <<
1424                               AVF_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
1425                 break;
1426         case PKT_TX_SCTP_CKSUM:
1427                 *td_cmd |= AVF_TX_DESC_CMD_L4T_EOFT_SCTP;
1428                 *td_offset |= (sizeof(struct sctp_hdr) >> 2) <<
1429                               AVF_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
1430                 break;
1431         case PKT_TX_UDP_CKSUM:
1432                 *td_cmd |= AVF_TX_DESC_CMD_L4T_EOFT_UDP;
1433                 *td_offset |= (sizeof(struct udp_hdr) >> 2) <<
1434                               AVF_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
1435                 break;
1436         default:
1437                 break;
1438         }
1439 }
1440
1441 /* set TSO context descriptor
1442  * support IP -> L4 and IP -> IP -> L4
1443  */
1444 static inline uint64_t
1445 avf_set_tso_ctx(struct rte_mbuf *mbuf, union avf_tx_offload tx_offload)
1446 {
1447         uint64_t ctx_desc = 0;
1448         uint32_t cd_cmd, hdr_len, cd_tso_len;
1449
1450         if (!tx_offload.l4_len) {
1451                 PMD_TX_LOG(DEBUG, "L4 length set to 0");
1452                 return ctx_desc;
1453         }
1454
1455         /* in case of non tunneling packet, the outer_l2_len and
1456          * outer_l3_len must be 0.
1457          */
1458         hdr_len = tx_offload.l2_len +
1459                   tx_offload.l3_len +
1460                   tx_offload.l4_len;
1461
1462         cd_cmd = AVF_TX_CTX_DESC_TSO;
1463         cd_tso_len = mbuf->pkt_len - hdr_len;
1464         ctx_desc |= ((uint64_t)cd_cmd << AVF_TXD_CTX_QW1_CMD_SHIFT) |
1465                      ((uint64_t)cd_tso_len << AVF_TXD_CTX_QW1_TSO_LEN_SHIFT) |
1466                      ((uint64_t)mbuf->tso_segsz << AVF_TXD_CTX_QW1_MSS_SHIFT);
1467
1468         return ctx_desc;
1469 }
1470
1471 /* Construct the tx flags */
1472 static inline uint64_t
1473 avf_build_ctob(uint32_t td_cmd, uint32_t td_offset, unsigned int size,
1474                uint32_t td_tag)
1475 {
1476         return rte_cpu_to_le_64(AVF_TX_DESC_DTYPE_DATA |
1477                                 ((uint64_t)td_cmd  << AVF_TXD_QW1_CMD_SHIFT) |
1478                                 ((uint64_t)td_offset <<
1479                                  AVF_TXD_QW1_OFFSET_SHIFT) |
1480                                 ((uint64_t)size  <<
1481                                  AVF_TXD_QW1_TX_BUF_SZ_SHIFT) |
1482                                 ((uint64_t)td_tag  <<
1483                                  AVF_TXD_QW1_L2TAG1_SHIFT));
1484 }
1485
1486 /* TX function */
1487 uint16_t
1488 avf_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts, uint16_t nb_pkts)
1489 {
1490         volatile struct avf_tx_desc *txd;
1491         volatile struct avf_tx_desc *txr;
1492         struct avf_tx_queue *txq;
1493         struct avf_tx_entry *sw_ring;
1494         struct avf_tx_entry *txe, *txn;
1495         struct rte_mbuf *tx_pkt;
1496         struct rte_mbuf *m_seg;
1497         uint16_t tx_id;
1498         uint16_t nb_tx;
1499         uint32_t td_cmd;
1500         uint32_t td_offset;
1501         uint32_t td_tag;
1502         uint64_t ol_flags;
1503         uint16_t nb_used;
1504         uint16_t nb_ctx;
1505         uint16_t tx_last;
1506         uint16_t slen;
1507         uint64_t buf_dma_addr;
1508         union avf_tx_offload tx_offload = {0};
1509
1510         txq = tx_queue;
1511         sw_ring = txq->sw_ring;
1512         txr = txq->tx_ring;
1513         tx_id = txq->tx_tail;
1514         txe = &sw_ring[tx_id];
1515
1516         /* Check if the descriptor ring needs to be cleaned. */
1517         if (txq->nb_free < txq->free_thresh)
1518                 avf_xmit_cleanup(txq);
1519
1520         for (nb_tx = 0; nb_tx < nb_pkts; nb_tx++) {
1521                 td_cmd = 0;
1522                 td_tag = 0;
1523                 td_offset = 0;
1524
1525                 tx_pkt = *tx_pkts++;
1526                 RTE_MBUF_PREFETCH_TO_FREE(txe->mbuf);
1527
1528                 ol_flags = tx_pkt->ol_flags;
1529                 tx_offload.l2_len = tx_pkt->l2_len;
1530                 tx_offload.l3_len = tx_pkt->l3_len;
1531                 tx_offload.l4_len = tx_pkt->l4_len;
1532                 tx_offload.tso_segsz = tx_pkt->tso_segsz;
1533
1534                 /* Calculate the number of context descriptors needed. */
1535                 nb_ctx = avf_calc_context_desc(ol_flags);
1536
1537                 /* The number of descriptors that must be allocated for
1538                  * a packet equals to the number of the segments of that
1539                  * packet plus 1 context descriptor if needed.
1540                  */
1541                 nb_used = (uint16_t)(tx_pkt->nb_segs + nb_ctx);
1542                 tx_last = (uint16_t)(tx_id + nb_used - 1);
1543
1544                 /* Circular ring */
1545                 if (tx_last >= txq->nb_tx_desc)
1546                         tx_last = (uint16_t)(tx_last - txq->nb_tx_desc);
1547
1548                 PMD_TX_LOG(DEBUG, "port_id=%u queue_id=%u"
1549                            " tx_first=%u tx_last=%u",
1550                            txq->port_id, txq->queue_id, tx_id, tx_last);
1551
1552                 if (nb_used > txq->nb_free) {
1553                         if (avf_xmit_cleanup(txq)) {
1554                                 if (nb_tx == 0)
1555                                         return 0;
1556                                 goto end_of_tx;
1557                         }
1558                         if (unlikely(nb_used > txq->rs_thresh)) {
1559                                 while (nb_used > txq->nb_free) {
1560                                         if (avf_xmit_cleanup(txq)) {
1561                                                 if (nb_tx == 0)
1562                                                         return 0;
1563                                                 goto end_of_tx;
1564                                         }
1565                                 }
1566                         }
1567                 }
1568
1569                 /* Descriptor based VLAN insertion */
1570                 if (ol_flags & PKT_TX_VLAN_PKT) {
1571                         td_cmd |= AVF_TX_DESC_CMD_IL2TAG1;
1572                         td_tag = tx_pkt->vlan_tci;
1573                 }
1574
1575                 /* According to datasheet, the bit2 is reserved and must be
1576                  * set to 1.
1577                  */
1578                 td_cmd |= 0x04;
1579
1580                 /* Enable checksum offloading */
1581                 if (ol_flags & AVF_TX_CKSUM_OFFLOAD_MASK)
1582                         avf_txd_enable_checksum(ol_flags, &td_cmd,
1583                                                 &td_offset, tx_offload);
1584
1585                 if (nb_ctx) {
1586                         /* Setup TX context descriptor if required */
1587                         volatile struct avf_tx_context_desc *ctx_txd =
1588                                 (volatile struct avf_tx_context_desc *)
1589                                         &txr[tx_id];
1590                         uint16_t cd_l2tag2 = 0;
1591                         uint64_t cd_type_cmd_tso_mss =
1592                                 AVF_TX_DESC_DTYPE_CONTEXT;
1593
1594                         txn = &sw_ring[txe->next_id];
1595                         RTE_MBUF_PREFETCH_TO_FREE(txn->mbuf);
1596                         if (txe->mbuf) {
1597                                 rte_pktmbuf_free_seg(txe->mbuf);
1598                                 txe->mbuf = NULL;
1599                         }
1600
1601                         /* TSO enabled */
1602                         if (ol_flags & PKT_TX_TCP_SEG)
1603                                 cd_type_cmd_tso_mss |=
1604                                         avf_set_tso_ctx(tx_pkt, tx_offload);
1605
1606                         AVF_DUMP_TX_DESC(txq, ctx_txd, tx_id);
1607                         txe->last_id = tx_last;
1608                         tx_id = txe->next_id;
1609                         txe = txn;
1610                 }
1611
1612                 m_seg = tx_pkt;
1613                 do {
1614                         txd = &txr[tx_id];
1615                         txn = &sw_ring[txe->next_id];
1616
1617                         if (txe->mbuf)
1618                                 rte_pktmbuf_free_seg(txe->mbuf);
1619                         txe->mbuf = m_seg;
1620
1621                         /* Setup TX Descriptor */
1622                         slen = m_seg->data_len;
1623                         buf_dma_addr = rte_mbuf_data_iova(m_seg);
1624                         txd->buffer_addr = rte_cpu_to_le_64(buf_dma_addr);
1625                         txd->cmd_type_offset_bsz = avf_build_ctob(td_cmd,
1626                                                                   td_offset,
1627                                                                   slen,
1628                                                                   td_tag);
1629
1630                         AVF_DUMP_TX_DESC(txq, txd, tx_id);
1631                         txe->last_id = tx_last;
1632                         tx_id = txe->next_id;
1633                         txe = txn;
1634                         m_seg = m_seg->next;
1635                 } while (m_seg);
1636
1637                 /* The last packet data descriptor needs End Of Packet (EOP) */
1638                 td_cmd |= AVF_TX_DESC_CMD_EOP;
1639                 txq->nb_used = (uint16_t)(txq->nb_used + nb_used);
1640                 txq->nb_free = (uint16_t)(txq->nb_free - nb_used);
1641
1642                 if (txq->nb_used >= txq->rs_thresh) {
1643                         PMD_TX_LOG(DEBUG, "Setting RS bit on TXD id="
1644                                    "%4u (port=%d queue=%d)",
1645                                    tx_last, txq->port_id, txq->queue_id);
1646
1647                         td_cmd |= AVF_TX_DESC_CMD_RS;
1648
1649                         /* Update txq RS bit counters */
1650                         txq->nb_used = 0;
1651                 }
1652
1653                 txd->cmd_type_offset_bsz |=
1654                         rte_cpu_to_le_64(((uint64_t)td_cmd) <<
1655                                          AVF_TXD_QW1_CMD_SHIFT);
1656                 AVF_DUMP_TX_DESC(txq, txd, tx_id);
1657         }
1658
1659 end_of_tx:
1660         rte_wmb();
1661
1662         PMD_TX_LOG(DEBUG, "port_id=%u queue_id=%u tx_tail=%u nb_tx=%u",
1663                    txq->port_id, txq->queue_id, tx_id, nb_tx);
1664
1665         AVF_PCI_REG_WRITE_RELAXED(txq->qtx_tail, tx_id);
1666         txq->tx_tail = tx_id;
1667
1668         return nb_tx;
1669 }
1670
1671 static uint16_t
1672 avf_xmit_pkts_vec(void *tx_queue, struct rte_mbuf **tx_pkts,
1673                   uint16_t nb_pkts)
1674 {
1675         uint16_t nb_tx = 0;
1676         struct avf_tx_queue *txq = (struct avf_tx_queue *)tx_queue;
1677
1678         while (nb_pkts) {
1679                 uint16_t ret, num;
1680
1681                 num = (uint16_t)RTE_MIN(nb_pkts, txq->rs_thresh);
1682                 ret = avf_xmit_fixed_burst_vec(tx_queue, &tx_pkts[nb_tx], num);
1683                 nb_tx += ret;
1684                 nb_pkts -= ret;
1685                 if (ret < num)
1686                         break;
1687         }
1688
1689         return nb_tx;
1690 }
1691
1692 /* TX prep functions */
1693 uint16_t
1694 avf_prep_pkts(__rte_unused void *tx_queue, struct rte_mbuf **tx_pkts,
1695               uint16_t nb_pkts)
1696 {
1697         int i, ret;
1698         uint64_t ol_flags;
1699         struct rte_mbuf *m;
1700
1701         for (i = 0; i < nb_pkts; i++) {
1702                 m = tx_pkts[i];
1703                 ol_flags = m->ol_flags;
1704
1705                 /* Check condition for nb_segs > AVF_TX_MAX_MTU_SEG. */
1706                 if (!(ol_flags & PKT_TX_TCP_SEG)) {
1707                         if (m->nb_segs > AVF_TX_MAX_MTU_SEG) {
1708                                 rte_errno = -EINVAL;
1709                                 return i;
1710                         }
1711                 } else if ((m->tso_segsz < AVF_MIN_TSO_MSS) ||
1712                            (m->tso_segsz > AVF_MAX_TSO_MSS)) {
1713                         /* MSS outside the range are considered malicious */
1714                         rte_errno = -EINVAL;
1715                         return i;
1716                 }
1717
1718                 if (ol_flags & AVF_TX_OFFLOAD_NOTSUP_MASK) {
1719                         rte_errno = -ENOTSUP;
1720                         return i;
1721                 }
1722
1723 #ifdef RTE_LIBRTE_ETHDEV_DEBUG
1724                 ret = rte_validate_tx_offload(m);
1725                 if (ret != 0) {
1726                         rte_errno = ret;
1727                         return i;
1728                 }
1729 #endif
1730                 ret = rte_net_intel_cksum_prepare(m);
1731                 if (ret != 0) {
1732                         rte_errno = ret;
1733                         return i;
1734                 }
1735         }
1736
1737         return i;
1738 }
1739
1740 /* choose rx function*/
1741 void
1742 avf_set_rx_function(struct rte_eth_dev *dev)
1743 {
1744         struct avf_adapter *adapter =
1745                 AVF_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1746         struct avf_rx_queue *rxq;
1747         int i;
1748
1749         if (adapter->rx_vec_allowed) {
1750                 if (dev->data->scattered_rx) {
1751                         PMD_DRV_LOG(DEBUG, "Using Vector Scattered Rx callback"
1752                                     " (port=%d).", dev->data->port_id);
1753                         dev->rx_pkt_burst = avf_recv_scattered_pkts_vec;
1754                 } else {
1755                         PMD_DRV_LOG(DEBUG, "Using Vector Rx callback"
1756                                     " (port=%d).", dev->data->port_id);
1757                         dev->rx_pkt_burst = avf_recv_pkts_vec;
1758                 }
1759                 for (i = 0; i < dev->data->nb_rx_queues; i++) {
1760                         rxq = dev->data->rx_queues[i];
1761                         if (!rxq)
1762                                 continue;
1763                         avf_rxq_vec_setup(rxq);
1764                 }
1765         } else if (dev->data->scattered_rx) {
1766                 PMD_DRV_LOG(DEBUG, "Using a Scattered Rx callback (port=%d).",
1767                             dev->data->port_id);
1768                 dev->rx_pkt_burst = avf_recv_scattered_pkts;
1769         } else if (adapter->rx_bulk_alloc_allowed) {
1770                 PMD_DRV_LOG(DEBUG, "Using bulk Rx callback (port=%d).",
1771                             dev->data->port_id);
1772                 dev->rx_pkt_burst = avf_recv_pkts_bulk_alloc;
1773         } else {
1774                 PMD_DRV_LOG(DEBUG, "Using Basic Rx callback (port=%d).",
1775                             dev->data->port_id);
1776                 dev->rx_pkt_burst = avf_recv_pkts;
1777         }
1778 }
1779
1780 /* choose tx function*/
1781 void
1782 avf_set_tx_function(struct rte_eth_dev *dev)
1783 {
1784         struct avf_adapter *adapter =
1785                 AVF_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1786         struct avf_tx_queue *txq;
1787         int i;
1788
1789         if (adapter->tx_vec_allowed) {
1790                 PMD_DRV_LOG(DEBUG, "Using Vector Tx callback (port=%d).",
1791                             dev->data->port_id);
1792                 dev->tx_pkt_burst = avf_xmit_pkts_vec;
1793                 dev->tx_pkt_prepare = NULL;
1794                 for (i = 0; i < dev->data->nb_tx_queues; i++) {
1795                         txq = dev->data->tx_queues[i];
1796                         if (!txq)
1797                                 continue;
1798                         avf_txq_vec_setup(txq);
1799                 }
1800         } else {
1801                 PMD_DRV_LOG(DEBUG, "Using Basic Tx callback (port=%d).",
1802                             dev->data->port_id);
1803                 dev->tx_pkt_burst = avf_xmit_pkts;
1804                 dev->tx_pkt_prepare = avf_prep_pkts;
1805         }
1806 }
1807
1808 void
1809 avf_dev_rxq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
1810                      struct rte_eth_rxq_info *qinfo)
1811 {
1812         struct avf_rx_queue *rxq;
1813
1814         rxq = dev->data->rx_queues[queue_id];
1815
1816         qinfo->mp = rxq->mp;
1817         qinfo->scattered_rx = dev->data->scattered_rx;
1818         qinfo->nb_desc = rxq->nb_rx_desc;
1819
1820         qinfo->conf.rx_free_thresh = rxq->rx_free_thresh;
1821         qinfo->conf.rx_drop_en = TRUE;
1822         qinfo->conf.rx_deferred_start = rxq->rx_deferred_start;
1823 }
1824
1825 void
1826 avf_dev_txq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
1827                      struct rte_eth_txq_info *qinfo)
1828 {
1829         struct avf_tx_queue *txq;
1830
1831         txq = dev->data->tx_queues[queue_id];
1832
1833         qinfo->nb_desc = txq->nb_tx_desc;
1834
1835         qinfo->conf.tx_free_thresh = txq->free_thresh;
1836         qinfo->conf.tx_rs_thresh = txq->rs_thresh;
1837         qinfo->conf.offloads = txq->offloads;
1838         qinfo->conf.tx_deferred_start = txq->tx_deferred_start;
1839 }
1840
1841 /* Get the number of used descriptors of a rx queue */
1842 uint32_t
1843 avf_dev_rxq_count(struct rte_eth_dev *dev, uint16_t queue_id)
1844 {
1845 #define AVF_RXQ_SCAN_INTERVAL 4
1846         volatile union avf_rx_desc *rxdp;
1847         struct avf_rx_queue *rxq;
1848         uint16_t desc = 0;
1849
1850         rxq = dev->data->rx_queues[queue_id];
1851         rxdp = &rxq->rx_ring[rxq->rx_tail];
1852         while ((desc < rxq->nb_rx_desc) &&
1853                ((rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len) &
1854                  AVF_RXD_QW1_STATUS_MASK) >> AVF_RXD_QW1_STATUS_SHIFT) &
1855                (1 << AVF_RX_DESC_STATUS_DD_SHIFT)) {
1856                 /* Check the DD bit of a rx descriptor of each 4 in a group,
1857                  * to avoid checking too frequently and downgrading performance
1858                  * too much.
1859                  */
1860                 desc += AVF_RXQ_SCAN_INTERVAL;
1861                 rxdp += AVF_RXQ_SCAN_INTERVAL;
1862                 if (rxq->rx_tail + desc >= rxq->nb_rx_desc)
1863                         rxdp = &(rxq->rx_ring[rxq->rx_tail +
1864                                         desc - rxq->nb_rx_desc]);
1865         }
1866
1867         return desc;
1868 }
1869
1870 int
1871 avf_dev_rx_desc_status(void *rx_queue, uint16_t offset)
1872 {
1873         struct avf_rx_queue *rxq = rx_queue;
1874         volatile uint64_t *status;
1875         uint64_t mask;
1876         uint32_t desc;
1877
1878         if (unlikely(offset >= rxq->nb_rx_desc))
1879                 return -EINVAL;
1880
1881         if (offset >= rxq->nb_rx_desc - rxq->nb_rx_hold)
1882                 return RTE_ETH_RX_DESC_UNAVAIL;
1883
1884         desc = rxq->rx_tail + offset;
1885         if (desc >= rxq->nb_rx_desc)
1886                 desc -= rxq->nb_rx_desc;
1887
1888         status = &rxq->rx_ring[desc].wb.qword1.status_error_len;
1889         mask = rte_le_to_cpu_64((1ULL << AVF_RX_DESC_STATUS_DD_SHIFT)
1890                 << AVF_RXD_QW1_STATUS_SHIFT);
1891         if (*status & mask)
1892                 return RTE_ETH_RX_DESC_DONE;
1893
1894         return RTE_ETH_RX_DESC_AVAIL;
1895 }
1896
1897 int
1898 avf_dev_tx_desc_status(void *tx_queue, uint16_t offset)
1899 {
1900         struct avf_tx_queue *txq = tx_queue;
1901         volatile uint64_t *status;
1902         uint64_t mask, expect;
1903         uint32_t desc;
1904
1905         if (unlikely(offset >= txq->nb_tx_desc))
1906                 return -EINVAL;
1907
1908         desc = txq->tx_tail + offset;
1909         /* go to next desc that has the RS bit */
1910         desc = ((desc + txq->rs_thresh - 1) / txq->rs_thresh) *
1911                 txq->rs_thresh;
1912         if (desc >= txq->nb_tx_desc) {
1913                 desc -= txq->nb_tx_desc;
1914                 if (desc >= txq->nb_tx_desc)
1915                         desc -= txq->nb_tx_desc;
1916         }
1917
1918         status = &txq->tx_ring[desc].cmd_type_offset_bsz;
1919         mask = rte_le_to_cpu_64(AVF_TXD_QW1_DTYPE_MASK);
1920         expect = rte_cpu_to_le_64(
1921                  AVF_TX_DESC_DTYPE_DESC_DONE << AVF_TXD_QW1_DTYPE_SHIFT);
1922         if ((*status & mask) == expect)
1923                 return RTE_ETH_TX_DESC_DONE;
1924
1925         return RTE_ETH_TX_DESC_FULL;
1926 }
1927
1928 uint16_t __attribute__((weak))
1929 avf_recv_pkts_vec(__rte_unused void *rx_queue,
1930                   __rte_unused struct rte_mbuf **rx_pkts,
1931                   __rte_unused uint16_t nb_pkts)
1932 {
1933         return 0;
1934 }
1935
1936 uint16_t __attribute__((weak))
1937 avf_recv_scattered_pkts_vec(__rte_unused void *rx_queue,
1938                             __rte_unused struct rte_mbuf **rx_pkts,
1939                             __rte_unused uint16_t nb_pkts)
1940 {
1941         return 0;
1942 }
1943
1944 uint16_t __attribute__((weak))
1945 avf_xmit_fixed_burst_vec(__rte_unused void *tx_queue,
1946                          __rte_unused struct rte_mbuf **tx_pkts,
1947                          __rte_unused uint16_t nb_pkts)
1948 {
1949         return 0;
1950 }
1951
1952 int __attribute__((weak))
1953 avf_rxq_vec_setup(__rte_unused struct avf_rx_queue *rxq)
1954 {
1955         return -1;
1956 }
1957
1958 int __attribute__((weak))
1959 avf_txq_vec_setup(__rte_unused struct avf_tx_queue *txq)
1960 {
1961         return -1;
1962 }