2 * Copyright (c) 2007-2013 Broadcom Corporation.
4 * Eric Davis <edavis@broadcom.com>
5 * David Christensen <davidch@broadcom.com>
6 * Gary Zambrano <zambrano@broadcom.com>
8 * Copyright (c) 2013-2015 Brocade Communications Systems, Inc.
9 * Copyright (c) 2015 QLogic Corporation.
10 * All rights reserved.
13 * See LICENSE.bnx2x_pmd for copyright and licensing details.
16 #define BNX2X_DRIVER_VERSION "1.78.18"
19 #include "bnx2x_vfpf.h"
21 #include "ecore_init.h"
22 #include "ecore_init_ops.h"
24 #include "rte_version.h"
26 #include <sys/types.h>
31 #define BNX2X_PMD_VER_PREFIX "BNX2X PMD"
32 #define BNX2X_PMD_VERSION_MAJOR 1
33 #define BNX2X_PMD_VERSION_MINOR 0
34 #define BNX2X_PMD_VERSION_REVISION 1
35 #define BNX2X_PMD_VERSION_PATCH 1
37 static inline const char *
38 bnx2x_pmd_version(void)
40 static char version[32];
42 snprintf(version, sizeof(version), "%s %s_%d.%d.%d.%d",
45 BNX2X_PMD_VERSION_MAJOR,
46 BNX2X_PMD_VERSION_MINOR,
47 BNX2X_PMD_VERSION_REVISION,
48 BNX2X_PMD_VERSION_PATCH);
53 static z_stream zlib_stream;
55 #define EVL_VLID_MASK 0x0FFF
57 #define BNX2X_DEF_SB_ATT_IDX 0x0001
58 #define BNX2X_DEF_SB_IDX 0x0002
61 * FLR Support - bnx2x_pf_flr_clnup() is called during nic_load in the per
62 * function HW initialization.
64 #define FLR_WAIT_USEC 10000 /* 10 msecs */
65 #define FLR_WAIT_INTERVAL 50 /* usecs */
66 #define FLR_POLL_CNT (FLR_WAIT_USEC / FLR_WAIT_INTERVAL) /* 200 */
68 struct pbf_pN_buf_regs {
75 struct pbf_pN_cmd_regs {
81 /* resources needed for unloading a previously loaded device */
83 #define BNX2X_PREV_WAIT_NEEDED 1
84 rte_spinlock_t bnx2x_prev_mtx;
85 struct bnx2x_prev_list_node {
86 LIST_ENTRY(bnx2x_prev_list_node) node;
94 static LIST_HEAD(, bnx2x_prev_list_node) bnx2x_prev_list
95 = LIST_HEAD_INITIALIZER(bnx2x_prev_list);
97 static int load_count[2][3] = { { 0 } };
98 /* per-path: 0-common, 1-port0, 2-port1 */
100 static void bnx2x_cmng_fns_init(struct bnx2x_softc *sc, uint8_t read_cfg,
102 static int bnx2x_get_cmng_fns_mode(struct bnx2x_softc *sc);
103 static void storm_memset_cmng(struct bnx2x_softc *sc, struct cmng_init *cmng,
105 static void bnx2x_set_reset_global(struct bnx2x_softc *sc);
106 static void bnx2x_set_reset_in_progress(struct bnx2x_softc *sc);
107 static uint8_t bnx2x_reset_is_done(struct bnx2x_softc *sc, int engine);
108 static uint8_t bnx2x_clear_pf_load(struct bnx2x_softc *sc);
109 static uint8_t bnx2x_chk_parity_attn(struct bnx2x_softc *sc, uint8_t * global,
111 static void bnx2x_int_disable(struct bnx2x_softc *sc);
112 static int bnx2x_release_leader_lock(struct bnx2x_softc *sc);
113 static void bnx2x_pf_disable(struct bnx2x_softc *sc);
114 static void bnx2x_update_rx_prod(struct bnx2x_softc *sc,
115 struct bnx2x_fastpath *fp,
116 uint16_t rx_bd_prod, uint16_t rx_cq_prod);
117 static void bnx2x_link_report_locked(struct bnx2x_softc *sc);
118 static void bnx2x_link_report(struct bnx2x_softc *sc);
119 void bnx2x_link_status_update(struct bnx2x_softc *sc);
120 static int bnx2x_alloc_mem(struct bnx2x_softc *sc);
121 static void bnx2x_free_mem(struct bnx2x_softc *sc);
122 static int bnx2x_alloc_fw_stats_mem(struct bnx2x_softc *sc);
123 static void bnx2x_free_fw_stats_mem(struct bnx2x_softc *sc);
124 static __attribute__ ((noinline))
125 int bnx2x_nic_load(struct bnx2x_softc *sc);
127 static int bnx2x_handle_sp_tq(struct bnx2x_softc *sc);
128 static void bnx2x_handle_fp_tq(struct bnx2x_fastpath *fp, int scan_fp);
129 static void bnx2x_periodic_stop(struct bnx2x_softc *sc);
130 static void bnx2x_ack_sb(struct bnx2x_softc *sc, uint8_t igu_sb_id,
131 uint8_t storm, uint16_t index, uint8_t op,
134 int bnx2x_test_bit(int nr, volatile unsigned long *addr)
139 res = ((*addr) & (1UL << nr)) != 0;
144 void bnx2x_set_bit(unsigned int nr, volatile unsigned long *addr)
146 __sync_fetch_and_or(addr, (1UL << nr));
149 void bnx2x_clear_bit(int nr, volatile unsigned long *addr)
151 __sync_fetch_and_and(addr, ~(1UL << nr));
154 int bnx2x_test_and_clear_bit(int nr, volatile unsigned long *addr)
156 unsigned long mask = (1UL << nr);
157 return __sync_fetch_and_and(addr, ~mask) & mask;
160 int bnx2x_cmpxchg(volatile int *addr, int old, int new)
162 return __sync_val_compare_and_swap(addr, old, new);
166 bnx2x_dma_alloc(struct bnx2x_softc *sc, size_t size, struct bnx2x_dma *dma,
167 const char *msg, uint32_t align)
169 char mz_name[RTE_MEMZONE_NAMESIZE];
170 const struct rte_memzone *z;
174 snprintf(mz_name, sizeof(mz_name), "bnx2x%d_%s_%" PRIx64, SC_ABS_FUNC(sc), msg,
175 rte_get_timer_cycles());
177 snprintf(mz_name, sizeof(mz_name), "bnx2x%d_%s_%" PRIx64, sc->pcie_device, msg,
178 rte_get_timer_cycles());
180 /* Caller must take care that strlen(mz_name) < RTE_MEMZONE_NAMESIZE */
181 z = rte_memzone_reserve_aligned(mz_name, (uint64_t) (size),
185 PMD_DRV_LOG(ERR, sc, "DMA alloc failed for %s", msg);
188 dma->paddr = (uint64_t) z->phys_addr;
189 dma->vaddr = z->addr;
191 PMD_DRV_LOG(DEBUG, sc,
192 "%s: virt=%p phys=%" PRIx64, msg, dma->vaddr, dma->paddr);
197 static int bnx2x_acquire_hw_lock(struct bnx2x_softc *sc, uint32_t resource)
199 uint32_t lock_status;
200 uint32_t resource_bit = (1 << resource);
201 int func = SC_FUNC(sc);
202 uint32_t hw_lock_control_reg;
205 #ifndef RTE_LIBRTE_BNX2X_DEBUG_PERIODIC
207 PMD_INIT_FUNC_TRACE(sc);
209 PMD_INIT_FUNC_TRACE(sc);
212 /* validate the resource is within range */
213 if (resource > HW_LOCK_MAX_RESOURCE_VALUE) {
214 PMD_DRV_LOG(NOTICE, sc,
215 "resource 0x%x > HW_LOCK_MAX_RESOURCE_VALUE",
221 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + (func * 8));
223 hw_lock_control_reg =
224 (MISC_REG_DRIVER_CONTROL_7 + ((func - 6) * 8));
227 /* validate the resource is not already taken */
228 lock_status = REG_RD(sc, hw_lock_control_reg);
229 if (lock_status & resource_bit) {
230 PMD_DRV_LOG(NOTICE, sc,
231 "resource in use (status 0x%x bit 0x%x)",
232 lock_status, resource_bit);
236 /* try every 5ms for 5 seconds */
237 for (cnt = 0; cnt < 1000; cnt++) {
238 REG_WR(sc, (hw_lock_control_reg + 4), resource_bit);
239 lock_status = REG_RD(sc, hw_lock_control_reg);
240 if (lock_status & resource_bit) {
246 PMD_DRV_LOG(NOTICE, sc, "Resource 0x%x resource_bit 0x%x lock timeout!",
247 resource, resource_bit);
251 static int bnx2x_release_hw_lock(struct bnx2x_softc *sc, uint32_t resource)
253 uint32_t lock_status;
254 uint32_t resource_bit = (1 << resource);
255 int func = SC_FUNC(sc);
256 uint32_t hw_lock_control_reg;
258 #ifndef RTE_LIBRTE_BNX2X_DEBUG_PERIODIC
260 PMD_INIT_FUNC_TRACE(sc);
262 PMD_INIT_FUNC_TRACE(sc);
265 /* validate the resource is within range */
266 if (resource > HW_LOCK_MAX_RESOURCE_VALUE) {
267 PMD_DRV_LOG(NOTICE, sc,
268 "(resource 0x%x > HW_LOCK_MAX_RESOURCE_VALUE)"
269 " resource_bit 0x%x", resource, resource_bit);
274 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + (func * 8));
276 hw_lock_control_reg =
277 (MISC_REG_DRIVER_CONTROL_7 + ((func - 6) * 8));
280 /* validate the resource is currently taken */
281 lock_status = REG_RD(sc, hw_lock_control_reg);
282 if (!(lock_status & resource_bit)) {
283 PMD_DRV_LOG(NOTICE, sc,
284 "resource not in use (status 0x%x bit 0x%x)",
285 lock_status, resource_bit);
289 REG_WR(sc, hw_lock_control_reg, resource_bit);
293 static void bnx2x_acquire_phy_lock(struct bnx2x_softc *sc)
296 bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_MDIO);
299 static void bnx2x_release_phy_lock(struct bnx2x_softc *sc)
301 bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_MDIO);
302 BNX2X_PHY_UNLOCK(sc);
305 /* copy command into DMAE command memory and set DMAE command Go */
306 void bnx2x_post_dmae(struct bnx2x_softc *sc, struct dmae_command *dmae, int idx)
311 cmd_offset = (DMAE_REG_CMD_MEM + (sizeof(struct dmae_command) * idx));
312 for (i = 0; i < ((sizeof(struct dmae_command) / 4)); i++) {
313 REG_WR(sc, (cmd_offset + (i * 4)), *(((uint32_t *) dmae) + i));
316 REG_WR(sc, dmae_reg_go_c[idx], 1);
319 uint32_t bnx2x_dmae_opcode_add_comp(uint32_t opcode, uint8_t comp_type)
321 return opcode | ((comp_type << DMAE_COMMAND_C_DST_SHIFT) |
322 DMAE_COMMAND_C_TYPE_ENABLE);
325 uint32_t bnx2x_dmae_opcode_clr_src_reset(uint32_t opcode)
327 return opcode & ~DMAE_COMMAND_SRC_RESET;
331 bnx2x_dmae_opcode(struct bnx2x_softc * sc, uint8_t src_type, uint8_t dst_type,
332 uint8_t with_comp, uint8_t comp_type)
336 opcode |= ((src_type << DMAE_COMMAND_SRC_SHIFT) |
337 (dst_type << DMAE_COMMAND_DST_SHIFT));
339 opcode |= (DMAE_COMMAND_SRC_RESET | DMAE_COMMAND_DST_RESET);
341 opcode |= (SC_PORT(sc) ? DMAE_CMD_PORT_1 : DMAE_CMD_PORT_0);
343 opcode |= ((SC_VN(sc) << DMAE_COMMAND_E1HVN_SHIFT) |
344 (SC_VN(sc) << DMAE_COMMAND_DST_VN_SHIFT));
346 opcode |= (DMAE_COM_SET_ERR << DMAE_COMMAND_ERR_POLICY_SHIFT);
349 opcode |= DMAE_CMD_ENDIANITY_B_DW_SWAP;
351 opcode |= DMAE_CMD_ENDIANITY_DW_SWAP;
355 opcode = bnx2x_dmae_opcode_add_comp(opcode, comp_type);
362 bnx2x_prep_dmae_with_comp(struct bnx2x_softc *sc, struct dmae_command *dmae,
363 uint8_t src_type, uint8_t dst_type)
365 memset(dmae, 0, sizeof(struct dmae_command));
368 dmae->opcode = bnx2x_dmae_opcode(sc, src_type, dst_type,
369 TRUE, DMAE_COMP_PCI);
371 /* fill in the completion parameters */
372 dmae->comp_addr_lo = U64_LO(BNX2X_SP_MAPPING(sc, wb_comp));
373 dmae->comp_addr_hi = U64_HI(BNX2X_SP_MAPPING(sc, wb_comp));
374 dmae->comp_val = DMAE_COMP_VAL;
377 /* issue a DMAE command over the init channel and wait for completion */
379 bnx2x_issue_dmae_with_comp(struct bnx2x_softc *sc, struct dmae_command *dmae)
381 uint32_t *wb_comp = BNX2X_SP(sc, wb_comp);
382 int timeout = CHIP_REV_IS_SLOW(sc) ? 400000 : 4000;
384 /* reset completion */
387 /* post the command on the channel used for initializations */
388 bnx2x_post_dmae(sc, dmae, INIT_DMAE_C(sc));
390 /* wait for completion */
393 while ((*wb_comp & ~DMAE_PCI_ERR_FLAG) != DMAE_COMP_VAL) {
395 (sc->recovery_state != BNX2X_RECOVERY_DONE &&
396 sc->recovery_state != BNX2X_RECOVERY_NIC_LOADING)) {
397 PMD_DRV_LOG(INFO, sc, "DMAE timeout!");
405 if (*wb_comp & DMAE_PCI_ERR_FLAG) {
406 PMD_DRV_LOG(INFO, sc, "DMAE PCI error!");
407 return DMAE_PCI_ERROR;
413 void bnx2x_read_dmae(struct bnx2x_softc *sc, uint32_t src_addr, uint32_t len32)
415 struct dmae_command dmae;
420 if (!sc->dmae_ready) {
421 data = BNX2X_SP(sc, wb_data[0]);
423 for (i = 0; i < len32; i++) {
424 data[i] = REG_RD(sc, (src_addr + (i * 4)));
430 /* set opcode and fixed command fields */
431 bnx2x_prep_dmae_with_comp(sc, &dmae, DMAE_SRC_GRC, DMAE_DST_PCI);
433 /* fill in addresses and len */
434 dmae.src_addr_lo = (src_addr >> 2); /* GRC addr has dword resolution */
435 dmae.src_addr_hi = 0;
436 dmae.dst_addr_lo = U64_LO(BNX2X_SP_MAPPING(sc, wb_data));
437 dmae.dst_addr_hi = U64_HI(BNX2X_SP_MAPPING(sc, wb_data));
440 /* issue the command and wait for completion */
441 if ((rc = bnx2x_issue_dmae_with_comp(sc, &dmae)) != 0) {
442 rte_panic("DMAE failed (%d)", rc);
447 bnx2x_write_dmae(struct bnx2x_softc *sc, phys_addr_t dma_addr, uint32_t dst_addr,
450 struct dmae_command dmae;
453 if (!sc->dmae_ready) {
454 ecore_init_str_wr(sc, dst_addr, BNX2X_SP(sc, wb_data[0]), len32);
458 /* set opcode and fixed command fields */
459 bnx2x_prep_dmae_with_comp(sc, &dmae, DMAE_SRC_PCI, DMAE_DST_GRC);
461 /* fill in addresses and len */
462 dmae.src_addr_lo = U64_LO(dma_addr);
463 dmae.src_addr_hi = U64_HI(dma_addr);
464 dmae.dst_addr_lo = (dst_addr >> 2); /* GRC addr has dword resolution */
465 dmae.dst_addr_hi = 0;
468 /* issue the command and wait for completion */
469 if ((rc = bnx2x_issue_dmae_with_comp(sc, &dmae)) != 0) {
470 rte_panic("DMAE failed (%d)", rc);
475 bnx2x_write_dmae_phys_len(struct bnx2x_softc *sc, phys_addr_t phys_addr,
476 uint32_t addr, uint32_t len)
478 uint32_t dmae_wr_max = DMAE_LEN32_WR_MAX(sc);
481 while (len > dmae_wr_max) {
482 bnx2x_write_dmae(sc, (phys_addr + offset), /* src DMA address */
483 (addr + offset), /* dst GRC address */
485 offset += (dmae_wr_max * 4);
489 bnx2x_write_dmae(sc, (phys_addr + offset), /* src DMA address */
490 (addr + offset), /* dst GRC address */
495 bnx2x_set_ctx_validation(struct bnx2x_softc *sc, struct eth_context *cxt,
498 /* ustorm cxt validation */
499 cxt->ustorm_ag_context.cdu_usage =
500 CDU_RSRVD_VALUE_TYPE_A(HW_CID(sc, cid),
501 CDU_REGION_NUMBER_UCM_AG,
502 ETH_CONNECTION_TYPE);
503 /* xcontext validation */
504 cxt->xstorm_ag_context.cdu_reserved =
505 CDU_RSRVD_VALUE_TYPE_A(HW_CID(sc, cid),
506 CDU_REGION_NUMBER_XCM_AG,
507 ETH_CONNECTION_TYPE);
511 bnx2x_storm_memset_hc_timeout(struct bnx2x_softc *sc, uint8_t fw_sb_id,
512 uint8_t sb_index, uint8_t ticks)
515 (BAR_CSTRORM_INTMEM +
516 CSTORM_STATUS_BLOCK_DATA_TIMEOUT_OFFSET(fw_sb_id, sb_index));
518 REG_WR8(sc, addr, ticks);
522 bnx2x_storm_memset_hc_disable(struct bnx2x_softc *sc, uint16_t fw_sb_id,
523 uint8_t sb_index, uint8_t disable)
525 uint32_t enable_flag =
526 (disable) ? 0 : (1 << HC_INDEX_DATA_HC_ENABLED_SHIFT);
528 (BAR_CSTRORM_INTMEM +
529 CSTORM_STATUS_BLOCK_DATA_FLAGS_OFFSET(fw_sb_id, sb_index));
533 flags = REG_RD8(sc, addr);
534 flags &= ~HC_INDEX_DATA_HC_ENABLED;
535 flags |= enable_flag;
536 REG_WR8(sc, addr, flags);
540 bnx2x_update_coalesce_sb_index(struct bnx2x_softc *sc, uint8_t fw_sb_id,
541 uint8_t sb_index, uint8_t disable, uint16_t usec)
543 uint8_t ticks = (usec / 4);
545 bnx2x_storm_memset_hc_timeout(sc, fw_sb_id, sb_index, ticks);
547 disable = (disable) ? 1 : ((usec) ? 0 : 1);
548 bnx2x_storm_memset_hc_disable(sc, fw_sb_id, sb_index, disable);
551 uint32_t elink_cb_reg_read(struct bnx2x_softc *sc, uint32_t reg_addr)
553 return REG_RD(sc, reg_addr);
556 void elink_cb_reg_write(struct bnx2x_softc *sc, uint32_t reg_addr, uint32_t val)
558 REG_WR(sc, reg_addr, val);
562 elink_cb_event_log(__rte_unused struct bnx2x_softc *sc,
563 __rte_unused const elink_log_id_t elink_log_id, ...)
565 PMD_DRV_LOG(DEBUG, sc, "ELINK EVENT LOG (%d)", elink_log_id);
568 static int bnx2x_set_spio(struct bnx2x_softc *sc, int spio, uint32_t mode)
572 /* Only 2 SPIOs are configurable */
573 if ((spio != MISC_SPIO_SPIO4) && (spio != MISC_SPIO_SPIO5)) {
574 PMD_DRV_LOG(NOTICE, sc, "Invalid SPIO 0x%x", spio);
578 bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_SPIO);
580 /* read SPIO and mask except the float bits */
581 spio_reg = (REG_RD(sc, MISC_REG_SPIO) & MISC_SPIO_FLOAT);
584 case MISC_SPIO_OUTPUT_LOW:
585 /* clear FLOAT and set CLR */
586 spio_reg &= ~(spio << MISC_SPIO_FLOAT_POS);
587 spio_reg |= (spio << MISC_SPIO_CLR_POS);
590 case MISC_SPIO_OUTPUT_HIGH:
591 /* clear FLOAT and set SET */
592 spio_reg &= ~(spio << MISC_SPIO_FLOAT_POS);
593 spio_reg |= (spio << MISC_SPIO_SET_POS);
596 case MISC_SPIO_INPUT_HI_Z:
598 spio_reg |= (spio << MISC_SPIO_FLOAT_POS);
605 REG_WR(sc, MISC_REG_SPIO, spio_reg);
606 bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_SPIO);
611 static int bnx2x_gpio_read(struct bnx2x_softc *sc, int gpio_num, uint8_t port)
613 /* The GPIO should be swapped if swap register is set and active */
614 int gpio_port = ((REG_RD(sc, NIG_REG_PORT_SWAP) &&
615 REG_RD(sc, NIG_REG_STRAP_OVERRIDE)) ^ port);
616 int gpio_shift = gpio_num;
618 gpio_shift += MISC_REGISTERS_GPIO_PORT_SHIFT;
620 uint32_t gpio_mask = (1 << gpio_shift);
623 if (gpio_num > MISC_REGISTERS_GPIO_3) {
624 PMD_DRV_LOG(NOTICE, sc, "Invalid GPIO %d", gpio_num);
628 /* read GPIO value */
629 gpio_reg = REG_RD(sc, MISC_REG_GPIO);
631 /* get the requested pin value */
632 return ((gpio_reg & gpio_mask) == gpio_mask) ? 1 : 0;
636 bnx2x_gpio_write(struct bnx2x_softc *sc, int gpio_num, uint32_t mode, uint8_t port)
638 /* The GPIO should be swapped if swap register is set and active */
639 int gpio_port = ((REG_RD(sc, NIG_REG_PORT_SWAP) &&
640 REG_RD(sc, NIG_REG_STRAP_OVERRIDE)) ^ port);
641 int gpio_shift = gpio_num;
643 gpio_shift += MISC_REGISTERS_GPIO_PORT_SHIFT;
645 uint32_t gpio_mask = (1 << gpio_shift);
648 if (gpio_num > MISC_REGISTERS_GPIO_3) {
649 PMD_DRV_LOG(NOTICE, sc, "Invalid GPIO %d", gpio_num);
653 bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_GPIO);
655 /* read GPIO and mask except the float bits */
656 gpio_reg = (REG_RD(sc, MISC_REG_GPIO) & MISC_REGISTERS_GPIO_FLOAT);
659 case MISC_REGISTERS_GPIO_OUTPUT_LOW:
660 /* clear FLOAT and set CLR */
661 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS);
662 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_CLR_POS);
665 case MISC_REGISTERS_GPIO_OUTPUT_HIGH:
666 /* clear FLOAT and set SET */
667 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS);
668 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_SET_POS);
671 case MISC_REGISTERS_GPIO_INPUT_HI_Z:
673 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS);
680 REG_WR(sc, MISC_REG_GPIO, gpio_reg);
681 bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_GPIO);
687 bnx2x_gpio_mult_write(struct bnx2x_softc *sc, uint8_t pins, uint32_t mode)
691 /* any port swapping should be handled by caller */
693 bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_GPIO);
695 /* read GPIO and mask except the float bits */
696 gpio_reg = REG_RD(sc, MISC_REG_GPIO);
697 gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_FLOAT_POS);
698 gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_CLR_POS);
699 gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_SET_POS);
702 case MISC_REGISTERS_GPIO_OUTPUT_LOW:
704 gpio_reg |= (pins << MISC_REGISTERS_GPIO_CLR_POS);
707 case MISC_REGISTERS_GPIO_OUTPUT_HIGH:
709 gpio_reg |= (pins << MISC_REGISTERS_GPIO_SET_POS);
712 case MISC_REGISTERS_GPIO_INPUT_HI_Z:
714 gpio_reg |= (pins << MISC_REGISTERS_GPIO_FLOAT_POS);
718 PMD_DRV_LOG(NOTICE, sc,
719 "Invalid GPIO mode assignment %d", mode);
720 bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_GPIO);
724 REG_WR(sc, MISC_REG_GPIO, gpio_reg);
725 bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_GPIO);
731 bnx2x_gpio_int_write(struct bnx2x_softc *sc, int gpio_num, uint32_t mode,
734 /* The GPIO should be swapped if swap register is set and active */
735 int gpio_port = ((REG_RD(sc, NIG_REG_PORT_SWAP) &&
736 REG_RD(sc, NIG_REG_STRAP_OVERRIDE)) ^ port);
737 int gpio_shift = gpio_num;
739 gpio_shift += MISC_REGISTERS_GPIO_PORT_SHIFT;
741 uint32_t gpio_mask = (1 << gpio_shift);
744 if (gpio_num > MISC_REGISTERS_GPIO_3) {
745 PMD_DRV_LOG(NOTICE, sc, "Invalid GPIO %d", gpio_num);
749 bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_GPIO);
752 gpio_reg = REG_RD(sc, MISC_REG_GPIO_INT);
755 case MISC_REGISTERS_GPIO_INT_OUTPUT_CLR:
756 /* clear SET and set CLR */
757 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_INT_SET_POS);
758 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_INT_CLR_POS);
761 case MISC_REGISTERS_GPIO_INT_OUTPUT_SET:
762 /* clear CLR and set SET */
763 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_INT_CLR_POS);
764 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_INT_SET_POS);
771 REG_WR(sc, MISC_REG_GPIO_INT, gpio_reg);
772 bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_GPIO);
778 elink_cb_gpio_read(struct bnx2x_softc * sc, uint16_t gpio_num, uint8_t port)
780 return bnx2x_gpio_read(sc, gpio_num, port);
783 uint8_t elink_cb_gpio_write(struct bnx2x_softc * sc, uint16_t gpio_num, uint8_t mode, /* 0=low 1=high */
786 return bnx2x_gpio_write(sc, gpio_num, mode, port);
790 elink_cb_gpio_mult_write(struct bnx2x_softc * sc, uint8_t pins,
791 uint8_t mode /* 0=low 1=high */ )
793 return bnx2x_gpio_mult_write(sc, pins, mode);
796 uint8_t elink_cb_gpio_int_write(struct bnx2x_softc * sc, uint16_t gpio_num, uint8_t mode, /* 0=low 1=high */
799 return bnx2x_gpio_int_write(sc, gpio_num, mode, port);
802 void elink_cb_notify_link_changed(struct bnx2x_softc *sc)
804 REG_WR(sc, (MISC_REG_AEU_GENERAL_ATTN_12 +
805 (SC_FUNC(sc) * sizeof(uint32_t))), 1);
808 /* send the MCP a request, block until there is a reply */
810 elink_cb_fw_command(struct bnx2x_softc *sc, uint32_t command, uint32_t param)
812 int mb_idx = SC_FW_MB_IDX(sc);
816 uint8_t delay = CHIP_REV_IS_SLOW(sc) ? 100 : 10;
819 SHMEM_WR(sc, func_mb[mb_idx].drv_mb_param, param);
820 SHMEM_WR(sc, func_mb[mb_idx].drv_mb_header, (command | seq));
822 PMD_DRV_LOG(DEBUG, sc,
823 "wrote command 0x%08x to FW MB param 0x%08x",
824 (command | seq), param);
826 /* Let the FW do it's magic. GIve it up to 5 seconds... */
829 rc = SHMEM_RD(sc, func_mb[mb_idx].fw_mb_header);
830 } while ((seq != (rc & FW_MSG_SEQ_NUMBER_MASK)) && (cnt++ < 500));
832 /* is this a reply to our command? */
833 if (seq == (rc & FW_MSG_SEQ_NUMBER_MASK)) {
834 rc &= FW_MSG_CODE_MASK;
837 PMD_DRV_LOG(NOTICE, sc, "FW failed to respond!");
845 bnx2x_fw_command(struct bnx2x_softc *sc, uint32_t command, uint32_t param)
847 return elink_cb_fw_command(sc, command, param);
851 __storm_memset_dma_mapping(struct bnx2x_softc *sc, uint32_t addr,
854 REG_WR(sc, addr, U64_LO(mapping));
855 REG_WR(sc, (addr + 4), U64_HI(mapping));
859 storm_memset_spq_addr(struct bnx2x_softc *sc, phys_addr_t mapping,
862 uint32_t addr = (XSEM_REG_FAST_MEMORY +
863 XSTORM_SPQ_PAGE_BASE_OFFSET(abs_fid));
864 __storm_memset_dma_mapping(sc, addr, mapping);
868 storm_memset_vf_to_pf(struct bnx2x_softc *sc, uint16_t abs_fid, uint16_t pf_id)
870 REG_WR8(sc, (BAR_XSTRORM_INTMEM + XSTORM_VF_TO_PF_OFFSET(abs_fid)),
872 REG_WR8(sc, (BAR_CSTRORM_INTMEM + CSTORM_VF_TO_PF_OFFSET(abs_fid)),
874 REG_WR8(sc, (BAR_TSTRORM_INTMEM + TSTORM_VF_TO_PF_OFFSET(abs_fid)),
876 REG_WR8(sc, (BAR_USTRORM_INTMEM + USTORM_VF_TO_PF_OFFSET(abs_fid)),
881 storm_memset_func_en(struct bnx2x_softc *sc, uint16_t abs_fid, uint8_t enable)
883 REG_WR8(sc, (BAR_XSTRORM_INTMEM + XSTORM_FUNC_EN_OFFSET(abs_fid)),
885 REG_WR8(sc, (BAR_CSTRORM_INTMEM + CSTORM_FUNC_EN_OFFSET(abs_fid)),
887 REG_WR8(sc, (BAR_TSTRORM_INTMEM + TSTORM_FUNC_EN_OFFSET(abs_fid)),
889 REG_WR8(sc, (BAR_USTRORM_INTMEM + USTORM_FUNC_EN_OFFSET(abs_fid)),
894 storm_memset_eq_data(struct bnx2x_softc *sc, struct event_ring_data *eq_data,
900 addr = (BAR_CSTRORM_INTMEM + CSTORM_EVENT_RING_DATA_OFFSET(pfid));
901 size = sizeof(struct event_ring_data);
902 ecore_storm_memset_struct(sc, addr, size, (uint32_t *) eq_data);
906 storm_memset_eq_prod(struct bnx2x_softc *sc, uint16_t eq_prod, uint16_t pfid)
908 uint32_t addr = (BAR_CSTRORM_INTMEM +
909 CSTORM_EVENT_RING_PROD_OFFSET(pfid));
910 REG_WR16(sc, addr, eq_prod);
914 * Post a slowpath command.
916 * A slowpath command is used to propogate a configuration change through
917 * the controller in a controlled manner, allowing each STORM processor and
918 * other H/W blocks to phase in the change. The commands sent on the
919 * slowpath are referred to as ramrods. Depending on the ramrod used the
920 * completion of the ramrod will occur in different ways. Here's a
921 * breakdown of ramrods and how they complete:
923 * RAMROD_CMD_ID_ETH_PORT_SETUP
924 * Used to setup the leading connection on a port. Completes on the
925 * Receive Completion Queue (RCQ) of that port (typically fp[0]).
927 * RAMROD_CMD_ID_ETH_CLIENT_SETUP
928 * Used to setup an additional connection on a port. Completes on the
929 * RCQ of the multi-queue/RSS connection being initialized.
931 * RAMROD_CMD_ID_ETH_STAT_QUERY
932 * Used to force the storm processors to update the statistics database
933 * in host memory. This ramrod is send on the leading connection CID and
934 * completes as an index increment of the CSTORM on the default status
937 * RAMROD_CMD_ID_ETH_UPDATE
938 * Used to update the state of the leading connection, usually to udpate
939 * the RSS indirection table. Completes on the RCQ of the leading
940 * connection. (Not currently used under FreeBSD until OS support becomes
943 * RAMROD_CMD_ID_ETH_HALT
944 * Used when tearing down a connection prior to driver unload. Completes
945 * on the RCQ of the multi-queue/RSS connection being torn down. Don't
946 * use this on the leading connection.
948 * RAMROD_CMD_ID_ETH_SET_MAC
949 * Sets the Unicast/Broadcast/Multicast used by the port. Completes on
950 * the RCQ of the leading connection.
952 * RAMROD_CMD_ID_ETH_CFC_DEL
953 * Used when tearing down a conneciton prior to driver unload. Completes
954 * on the RCQ of the leading connection (since the current connection
955 * has been completely removed from controller memory).
957 * RAMROD_CMD_ID_ETH_PORT_DEL
958 * Used to tear down the leading connection prior to driver unload,
959 * typically fp[0]. Completes as an index increment of the CSTORM on the
960 * default status block.
962 * RAMROD_CMD_ID_ETH_FORWARD_SETUP
963 * Used for connection offload. Completes on the RCQ of the multi-queue
964 * RSS connection that is being offloaded. (Not currently used under
967 * There can only be one command pending per function.
970 * 0 = Success, !0 = Failure.
973 /* must be called under the spq lock */
974 static inline struct eth_spe *bnx2x_sp_get_next(struct bnx2x_softc *sc)
976 struct eth_spe *next_spe = sc->spq_prod_bd;
978 if (sc->spq_prod_bd == sc->spq_last_bd) {
979 /* wrap back to the first eth_spq */
980 sc->spq_prod_bd = sc->spq;
981 sc->spq_prod_idx = 0;
990 /* must be called under the spq lock */
991 static void bnx2x_sp_prod_update(struct bnx2x_softc *sc)
993 int func = SC_FUNC(sc);
996 * Make sure that BD data is updated before writing the producer.
997 * BD data is written to the memory, the producer is read from the
998 * memory, thus we need a full memory barrier to ensure the ordering.
1002 REG_WR16(sc, (BAR_XSTRORM_INTMEM + XSTORM_SPQ_PROD_OFFSET(func)),
1009 * bnx2x_is_contextless_ramrod - check if the current command ends on EQ
1011 * @cmd: command to check
1012 * @cmd_type: command type
1014 static int bnx2x_is_contextless_ramrod(int cmd, int cmd_type)
1016 if ((cmd_type == NONE_CONNECTION_TYPE) ||
1017 (cmd == RAMROD_CMD_ID_ETH_FORWARD_SETUP) ||
1018 (cmd == RAMROD_CMD_ID_ETH_CLASSIFICATION_RULES) ||
1019 (cmd == RAMROD_CMD_ID_ETH_FILTER_RULES) ||
1020 (cmd == RAMROD_CMD_ID_ETH_MULTICAST_RULES) ||
1021 (cmd == RAMROD_CMD_ID_ETH_SET_MAC) ||
1022 (cmd == RAMROD_CMD_ID_ETH_RSS_UPDATE)) {
1030 * bnx2x_sp_post - place a single command on an SP ring
1032 * @sc: driver handle
1033 * @command: command to place (e.g. SETUP, FILTER_RULES, etc.)
1034 * @cid: SW CID the command is related to
1035 * @data_hi: command private data address (high 32 bits)
1036 * @data_lo: command private data address (low 32 bits)
1037 * @cmd_type: command type (e.g. NONE, ETH)
1039 * SP data is handled as if it's always an address pair, thus data fields are
1040 * not swapped to little endian in upper functions. Instead this function swaps
1041 * data as if it's two uint32 fields.
1044 bnx2x_sp_post(struct bnx2x_softc *sc, int command, int cid, uint32_t data_hi,
1045 uint32_t data_lo, int cmd_type)
1047 struct eth_spe *spe;
1051 common = bnx2x_is_contextless_ramrod(command, cmd_type);
1054 if (!atomic_load_acq_long(&sc->eq_spq_left)) {
1055 PMD_DRV_LOG(INFO, sc, "EQ ring is full!");
1059 if (!atomic_load_acq_long(&sc->cq_spq_left)) {
1060 PMD_DRV_LOG(INFO, sc, "SPQ ring is full!");
1065 spe = bnx2x_sp_get_next(sc);
1067 /* CID needs port number to be encoded int it */
1068 spe->hdr.conn_and_cmd_data =
1069 htole32((command << SPE_HDR_CMD_ID_SHIFT) | HW_CID(sc, cid));
1071 type = (cmd_type << SPE_HDR_CONN_TYPE_SHIFT) & SPE_HDR_CONN_TYPE;
1073 /* TBD: Check if it works for VFs */
1074 type |= ((SC_FUNC(sc) << SPE_HDR_FUNCTION_ID_SHIFT) &
1075 SPE_HDR_FUNCTION_ID);
1077 spe->hdr.type = htole16(type);
1079 spe->data.update_data_addr.hi = htole32(data_hi);
1080 spe->data.update_data_addr.lo = htole32(data_lo);
1083 * It's ok if the actual decrement is issued towards the memory
1084 * somewhere between the lock and unlock. Thus no more explict
1085 * memory barrier is needed.
1088 atomic_subtract_acq_long(&sc->eq_spq_left, 1);
1090 atomic_subtract_acq_long(&sc->cq_spq_left, 1);
1093 PMD_DRV_LOG(DEBUG, sc,
1094 "SPQE[%x] (%x:%x) (cmd, common?) (%d,%d) hw_cid %x"
1095 "data (%x:%x) type(0x%x) left (CQ, EQ) (%lx,%lx)",
1097 (uint32_t) U64_HI(sc->spq_dma.paddr),
1098 (uint32_t) (U64_LO(sc->spq_dma.paddr) +
1099 (uint8_t *) sc->spq_prod_bd -
1100 (uint8_t *) sc->spq), command, common,
1101 HW_CID(sc, cid), data_hi, data_lo, type,
1102 atomic_load_acq_long(&sc->cq_spq_left),
1103 atomic_load_acq_long(&sc->eq_spq_left));
1105 bnx2x_sp_prod_update(sc);
1110 static void bnx2x_drv_pulse(struct bnx2x_softc *sc)
1112 SHMEM_WR(sc, func_mb[SC_FW_MB_IDX(sc)].drv_pulse_mb,
1113 sc->fw_drv_pulse_wr_seq);
1116 static int bnx2x_tx_queue_has_work(const struct bnx2x_fastpath *fp)
1119 struct bnx2x_tx_queue *txq = fp->sc->tx_queues[fp->index];
1121 if (unlikely(!txq)) {
1122 PMD_TX_LOG(ERR, "ERROR: TX queue is NULL");
1126 mb(); /* status block fields can change */
1127 hw_cons = le16toh(*fp->tx_cons_sb);
1128 return hw_cons != txq->tx_pkt_head;
1131 static uint8_t bnx2x_has_tx_work(struct bnx2x_fastpath *fp)
1133 /* expand this for multi-cos if ever supported */
1134 return bnx2x_tx_queue_has_work(fp);
1137 static int bnx2x_has_rx_work(struct bnx2x_fastpath *fp)
1139 uint16_t rx_cq_cons_sb;
1140 struct bnx2x_rx_queue *rxq;
1141 rxq = fp->sc->rx_queues[fp->index];
1142 if (unlikely(!rxq)) {
1143 PMD_RX_LOG(ERR, "ERROR: RX queue is NULL");
1147 mb(); /* status block fields can change */
1148 rx_cq_cons_sb = le16toh(*fp->rx_cq_cons_sb);
1149 if (unlikely((rx_cq_cons_sb & MAX_RCQ_ENTRIES(rxq)) ==
1150 MAX_RCQ_ENTRIES(rxq)))
1152 return rxq->rx_cq_head != rx_cq_cons_sb;
1156 bnx2x_sp_event(struct bnx2x_softc *sc, struct bnx2x_fastpath *fp,
1157 union eth_rx_cqe *rr_cqe)
1159 #ifdef RTE_LIBRTE_BNX2X_DEBUG
1160 int cid = SW_CID(rr_cqe->ramrod_cqe.conn_and_cmd_data);
1162 int command = CQE_CMD(rr_cqe->ramrod_cqe.conn_and_cmd_data);
1163 enum ecore_queue_cmd drv_cmd = ECORE_Q_CMD_MAX;
1164 struct ecore_queue_sp_obj *q_obj = &BNX2X_SP_OBJ(sc, fp).q_obj;
1166 PMD_DRV_LOG(DEBUG, sc,
1167 "fp=%d cid=%d got ramrod #%d state is %x type is %d",
1168 fp->index, cid, command, sc->state,
1169 rr_cqe->ramrod_cqe.ramrod_type);
1172 case (RAMROD_CMD_ID_ETH_CLIENT_UPDATE):
1173 PMD_DRV_LOG(DEBUG, sc, "got UPDATE ramrod. CID %d", cid);
1174 drv_cmd = ECORE_Q_CMD_UPDATE;
1177 case (RAMROD_CMD_ID_ETH_CLIENT_SETUP):
1178 PMD_DRV_LOG(DEBUG, sc, "got MULTI[%d] setup ramrod", cid);
1179 drv_cmd = ECORE_Q_CMD_SETUP;
1182 case (RAMROD_CMD_ID_ETH_TX_QUEUE_SETUP):
1183 PMD_DRV_LOG(DEBUG, sc,
1184 "got MULTI[%d] tx-only setup ramrod", cid);
1185 drv_cmd = ECORE_Q_CMD_SETUP_TX_ONLY;
1188 case (RAMROD_CMD_ID_ETH_HALT):
1189 PMD_DRV_LOG(DEBUG, sc, "got MULTI[%d] halt ramrod", cid);
1190 drv_cmd = ECORE_Q_CMD_HALT;
1193 case (RAMROD_CMD_ID_ETH_TERMINATE):
1194 PMD_DRV_LOG(DEBUG, sc, "got MULTI[%d] teminate ramrod", cid);
1195 drv_cmd = ECORE_Q_CMD_TERMINATE;
1198 case (RAMROD_CMD_ID_ETH_EMPTY):
1199 PMD_DRV_LOG(DEBUG, sc, "got MULTI[%d] empty ramrod", cid);
1200 drv_cmd = ECORE_Q_CMD_EMPTY;
1204 PMD_DRV_LOG(DEBUG, sc,
1205 "ERROR: unexpected MC reply (%d)"
1206 "on fp[%d]", command, fp->index);
1210 if ((drv_cmd != ECORE_Q_CMD_MAX) &&
1211 q_obj->complete_cmd(sc, q_obj, drv_cmd)) {
1213 * q_obj->complete_cmd() failure means that this was
1214 * an unexpected completion.
1216 * In this case we don't want to increase the sc->spq_left
1217 * because apparently we haven't sent this command the first
1220 // rte_panic("Unexpected SP completion");
1224 atomic_add_acq_long(&sc->cq_spq_left, 1);
1226 PMD_DRV_LOG(DEBUG, sc, "sc->cq_spq_left 0x%lx",
1227 atomic_load_acq_long(&sc->cq_spq_left));
1230 static uint8_t bnx2x_rxeof(struct bnx2x_softc *sc, struct bnx2x_fastpath *fp)
1232 struct bnx2x_rx_queue *rxq;
1233 uint16_t bd_cons, bd_prod, bd_prod_fw, comp_ring_cons;
1234 uint16_t hw_cq_cons, sw_cq_cons, sw_cq_prod;
1236 rxq = sc->rx_queues[fp->index];
1238 PMD_RX_LOG(ERR, "RX queue %d is NULL", fp->index);
1242 /* CQ "next element" is of the size of the regular element */
1243 hw_cq_cons = le16toh(*fp->rx_cq_cons_sb);
1244 if (unlikely((hw_cq_cons & USABLE_RCQ_ENTRIES_PER_PAGE) ==
1245 USABLE_RCQ_ENTRIES_PER_PAGE)) {
1249 bd_cons = rxq->rx_bd_head;
1250 bd_prod = rxq->rx_bd_tail;
1251 bd_prod_fw = bd_prod;
1252 sw_cq_cons = rxq->rx_cq_head;
1253 sw_cq_prod = rxq->rx_cq_tail;
1256 * Memory barrier necessary as speculative reads of the rx
1257 * buffer can be ahead of the index in the status block
1261 while (sw_cq_cons != hw_cq_cons) {
1262 union eth_rx_cqe *cqe;
1263 struct eth_fast_path_rx_cqe *cqe_fp;
1264 uint8_t cqe_fp_flags;
1265 enum eth_rx_cqe_type cqe_fp_type;
1267 comp_ring_cons = RCQ_ENTRY(sw_cq_cons, rxq);
1268 bd_prod = RX_BD(bd_prod, rxq);
1269 bd_cons = RX_BD(bd_cons, rxq);
1271 cqe = &rxq->cq_ring[comp_ring_cons];
1272 cqe_fp = &cqe->fast_path_cqe;
1273 cqe_fp_flags = cqe_fp->type_error_flags;
1274 cqe_fp_type = cqe_fp_flags & ETH_FAST_PATH_RX_CQE_TYPE;
1276 /* is this a slowpath msg? */
1277 if (CQE_TYPE_SLOW(cqe_fp_type)) {
1278 bnx2x_sp_event(sc, fp, cqe);
1282 /* is this an error packet? */
1283 if (unlikely(cqe_fp_flags &
1284 ETH_FAST_PATH_RX_CQE_PHY_DECODE_ERR_FLG)) {
1285 PMD_RX_LOG(DEBUG, "flags 0x%x rx packet %u",
1286 cqe_fp_flags, sw_cq_cons);
1290 PMD_RX_LOG(DEBUG, "Dropping fastpath called from attn poller!");
1293 bd_cons = NEXT_RX_BD(bd_cons);
1294 bd_prod = NEXT_RX_BD(bd_prod);
1295 bd_prod_fw = NEXT_RX_BD(bd_prod_fw);
1298 sw_cq_prod = NEXT_RCQ_IDX(sw_cq_prod);
1299 sw_cq_cons = NEXT_RCQ_IDX(sw_cq_cons);
1301 } /* while work to do */
1303 rxq->rx_bd_head = bd_cons;
1304 rxq->rx_bd_tail = bd_prod_fw;
1305 rxq->rx_cq_head = sw_cq_cons;
1306 rxq->rx_cq_tail = sw_cq_prod;
1308 /* Update producers */
1309 bnx2x_update_rx_prod(sc, fp, bd_prod_fw, sw_cq_prod);
1311 return sw_cq_cons != hw_cq_cons;
1315 bnx2x_free_tx_pkt(__rte_unused struct bnx2x_fastpath *fp, struct bnx2x_tx_queue *txq,
1316 uint16_t pkt_idx, uint16_t bd_idx)
1318 struct eth_tx_start_bd *tx_start_bd =
1319 &txq->tx_ring[TX_BD(bd_idx, txq)].start_bd;
1320 uint16_t nbd = rte_le_to_cpu_16(tx_start_bd->nbd);
1321 struct rte_mbuf *tx_mbuf = txq->sw_ring[TX_BD(pkt_idx, txq)];
1323 if (likely(tx_mbuf != NULL)) {
1324 rte_pktmbuf_free_seg(tx_mbuf);
1326 PMD_RX_LOG(ERR, "fp[%02d] lost mbuf %lu",
1327 fp->index, (unsigned long)TX_BD(pkt_idx, txq));
1330 txq->sw_ring[TX_BD(pkt_idx, txq)] = NULL;
1331 txq->nb_tx_avail += nbd;
1334 bd_idx = NEXT_TX_BD(bd_idx);
1339 /* processes transmit completions */
1340 uint8_t bnx2x_txeof(__rte_unused struct bnx2x_softc * sc, struct bnx2x_fastpath * fp)
1342 uint16_t bd_cons, hw_cons, sw_cons;
1343 __rte_unused uint16_t tx_bd_avail;
1345 struct bnx2x_tx_queue *txq = fp->sc->tx_queues[fp->index];
1347 if (unlikely(!txq)) {
1348 PMD_TX_LOG(ERR, "ERROR: TX queue is NULL");
1352 bd_cons = txq->tx_bd_head;
1353 hw_cons = rte_le_to_cpu_16(*fp->tx_cons_sb);
1354 sw_cons = txq->tx_pkt_head;
1356 while (sw_cons != hw_cons) {
1357 bd_cons = bnx2x_free_tx_pkt(fp, txq, sw_cons, bd_cons);
1361 txq->tx_pkt_head = sw_cons;
1362 txq->tx_bd_head = bd_cons;
1364 tx_bd_avail = txq->nb_tx_avail;
1366 PMD_TX_LOG(DEBUG, "fp[%02d] avail=%u cons_sb=%u, "
1367 "pkt_head=%u pkt_tail=%u bd_head=%u bd_tail=%u",
1368 fp->index, tx_bd_avail, hw_cons,
1369 txq->tx_pkt_head, txq->tx_pkt_tail,
1370 txq->tx_bd_head, txq->tx_bd_tail);
1374 static void bnx2x_drain_tx_queues(struct bnx2x_softc *sc)
1376 struct bnx2x_fastpath *fp;
1379 /* wait until all TX fastpath tasks have completed */
1380 for (i = 0; i < sc->num_queues; i++) {
1385 while (bnx2x_has_tx_work(fp)) {
1386 bnx2x_txeof(sc, fp);
1390 "Timeout waiting for fp[%d] "
1391 "transmits to complete!", i);
1392 rte_panic("tx drain failure");
1406 bnx2x_del_all_macs(struct bnx2x_softc *sc, struct ecore_vlan_mac_obj *mac_obj,
1407 int mac_type, uint8_t wait_for_comp)
1409 unsigned long ramrod_flags = 0, vlan_mac_flags = 0;
1412 /* wait for completion of requested */
1413 if (wait_for_comp) {
1414 bnx2x_set_bit(RAMROD_COMP_WAIT, &ramrod_flags);
1417 /* Set the mac type of addresses we want to clear */
1418 bnx2x_set_bit(mac_type, &vlan_mac_flags);
1420 rc = mac_obj->delete_all(sc, mac_obj, &vlan_mac_flags, &ramrod_flags);
1422 PMD_DRV_LOG(ERR, sc, "Failed to delete MACs (%d)", rc);
1428 bnx2x_fill_accept_flags(struct bnx2x_softc *sc, uint32_t rx_mode,
1429 unsigned long *rx_accept_flags,
1430 unsigned long *tx_accept_flags)
1432 /* Clear the flags first */
1433 *rx_accept_flags = 0;
1434 *tx_accept_flags = 0;
1437 case BNX2X_RX_MODE_NONE:
1439 * 'drop all' supersedes any accept flags that may have been
1440 * passed to the function.
1444 case BNX2X_RX_MODE_NORMAL:
1445 bnx2x_set_bit(ECORE_ACCEPT_UNICAST, rx_accept_flags);
1446 bnx2x_set_bit(ECORE_ACCEPT_MULTICAST, rx_accept_flags);
1447 bnx2x_set_bit(ECORE_ACCEPT_BROADCAST, rx_accept_flags);
1449 /* internal switching mode */
1450 bnx2x_set_bit(ECORE_ACCEPT_UNICAST, tx_accept_flags);
1451 bnx2x_set_bit(ECORE_ACCEPT_MULTICAST, tx_accept_flags);
1452 bnx2x_set_bit(ECORE_ACCEPT_BROADCAST, tx_accept_flags);
1456 case BNX2X_RX_MODE_ALLMULTI:
1457 bnx2x_set_bit(ECORE_ACCEPT_UNICAST, rx_accept_flags);
1458 bnx2x_set_bit(ECORE_ACCEPT_ALL_MULTICAST, rx_accept_flags);
1459 bnx2x_set_bit(ECORE_ACCEPT_BROADCAST, rx_accept_flags);
1461 /* internal switching mode */
1462 bnx2x_set_bit(ECORE_ACCEPT_UNICAST, tx_accept_flags);
1463 bnx2x_set_bit(ECORE_ACCEPT_ALL_MULTICAST, tx_accept_flags);
1464 bnx2x_set_bit(ECORE_ACCEPT_BROADCAST, tx_accept_flags);
1468 case BNX2X_RX_MODE_ALLMULTI_PROMISC:
1469 case BNX2X_RX_MODE_PROMISC:
1471 * According to deffinition of SI mode, iface in promisc mode
1472 * should receive matched and unmatched (in resolution of port)
1475 bnx2x_set_bit(ECORE_ACCEPT_UNMATCHED, rx_accept_flags);
1476 bnx2x_set_bit(ECORE_ACCEPT_UNICAST, rx_accept_flags);
1477 bnx2x_set_bit(ECORE_ACCEPT_ALL_MULTICAST, rx_accept_flags);
1478 bnx2x_set_bit(ECORE_ACCEPT_BROADCAST, rx_accept_flags);
1480 /* internal switching mode */
1481 bnx2x_set_bit(ECORE_ACCEPT_ALL_MULTICAST, tx_accept_flags);
1482 bnx2x_set_bit(ECORE_ACCEPT_BROADCAST, tx_accept_flags);
1485 bnx2x_set_bit(ECORE_ACCEPT_ALL_UNICAST, tx_accept_flags);
1487 bnx2x_set_bit(ECORE_ACCEPT_UNICAST, tx_accept_flags);
1493 PMD_RX_LOG(ERR, "Unknown rx_mode (%d)", rx_mode);
1497 /* Set ACCEPT_ANY_VLAN as we do not enable filtering by VLAN */
1498 if (rx_mode != BNX2X_RX_MODE_NONE) {
1499 bnx2x_set_bit(ECORE_ACCEPT_ANY_VLAN, rx_accept_flags);
1500 bnx2x_set_bit(ECORE_ACCEPT_ANY_VLAN, tx_accept_flags);
1507 bnx2x_set_q_rx_mode(struct bnx2x_softc *sc, uint8_t cl_id,
1508 unsigned long rx_mode_flags,
1509 unsigned long rx_accept_flags,
1510 unsigned long tx_accept_flags, unsigned long ramrod_flags)
1512 struct ecore_rx_mode_ramrod_params ramrod_param;
1515 memset(&ramrod_param, 0, sizeof(ramrod_param));
1517 /* Prepare ramrod parameters */
1518 ramrod_param.cid = 0;
1519 ramrod_param.cl_id = cl_id;
1520 ramrod_param.rx_mode_obj = &sc->rx_mode_obj;
1521 ramrod_param.func_id = SC_FUNC(sc);
1523 ramrod_param.pstate = &sc->sp_state;
1524 ramrod_param.state = ECORE_FILTER_RX_MODE_PENDING;
1526 ramrod_param.rdata = BNX2X_SP(sc, rx_mode_rdata);
1527 ramrod_param.rdata_mapping =
1528 (phys_addr_t)BNX2X_SP_MAPPING(sc, rx_mode_rdata),
1529 bnx2x_set_bit(ECORE_FILTER_RX_MODE_PENDING, &sc->sp_state);
1531 ramrod_param.ramrod_flags = ramrod_flags;
1532 ramrod_param.rx_mode_flags = rx_mode_flags;
1534 ramrod_param.rx_accept_flags = rx_accept_flags;
1535 ramrod_param.tx_accept_flags = tx_accept_flags;
1537 rc = ecore_config_rx_mode(sc, &ramrod_param);
1539 PMD_RX_LOG(ERR, "Set rx_mode %d failed", sc->rx_mode);
1546 int bnx2x_set_storm_rx_mode(struct bnx2x_softc *sc)
1548 unsigned long rx_mode_flags = 0, ramrod_flags = 0;
1549 unsigned long rx_accept_flags = 0, tx_accept_flags = 0;
1552 rc = bnx2x_fill_accept_flags(sc, sc->rx_mode, &rx_accept_flags,
1558 bnx2x_set_bit(RAMROD_RX, &ramrod_flags);
1559 bnx2x_set_bit(RAMROD_TX, &ramrod_flags);
1560 bnx2x_set_bit(RAMROD_COMP_WAIT, &ramrod_flags);
1562 return bnx2x_set_q_rx_mode(sc, sc->fp[0].cl_id, rx_mode_flags,
1563 rx_accept_flags, tx_accept_flags,
1567 /* returns the "mcp load_code" according to global load_count array */
1568 static int bnx2x_nic_load_no_mcp(struct bnx2x_softc *sc)
1570 int path = SC_PATH(sc);
1571 int port = SC_PORT(sc);
1573 PMD_DRV_LOG(INFO, sc, "NO MCP - load counts[%d] %d, %d, %d",
1574 path, load_count[path][0], load_count[path][1],
1575 load_count[path][2]);
1577 load_count[path][0]++;
1578 load_count[path][1 + port]++;
1579 PMD_DRV_LOG(INFO, sc, "NO MCP - new load counts[%d] %d, %d, %d",
1580 path, load_count[path][0], load_count[path][1],
1581 load_count[path][2]);
1582 if (load_count[path][0] == 1)
1583 return FW_MSG_CODE_DRV_LOAD_COMMON;
1584 else if (load_count[path][1 + port] == 1)
1585 return FW_MSG_CODE_DRV_LOAD_PORT;
1587 return FW_MSG_CODE_DRV_LOAD_FUNCTION;
1590 /* returns the "mcp load_code" according to global load_count array */
1591 static int bnx2x_nic_unload_no_mcp(struct bnx2x_softc *sc)
1593 int port = SC_PORT(sc);
1594 int path = SC_PATH(sc);
1596 PMD_DRV_LOG(INFO, sc, "NO MCP - load counts[%d] %d, %d, %d",
1597 path, load_count[path][0], load_count[path][1],
1598 load_count[path][2]);
1599 load_count[path][0]--;
1600 load_count[path][1 + port]--;
1601 PMD_DRV_LOG(INFO, sc, "NO MCP - new load counts[%d] %d, %d, %d",
1602 path, load_count[path][0], load_count[path][1],
1603 load_count[path][2]);
1604 if (load_count[path][0] == 0) {
1605 return FW_MSG_CODE_DRV_UNLOAD_COMMON;
1606 } else if (load_count[path][1 + port] == 0) {
1607 return FW_MSG_CODE_DRV_UNLOAD_PORT;
1609 return FW_MSG_CODE_DRV_UNLOAD_FUNCTION;
1613 /* request unload mode from the MCP: COMMON, PORT or FUNCTION */
1614 static uint32_t bnx2x_send_unload_req(struct bnx2x_softc *sc, int unload_mode)
1616 uint32_t reset_code = 0;
1618 /* Select the UNLOAD request mode */
1619 if (unload_mode == UNLOAD_NORMAL) {
1620 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS;
1622 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS;
1625 /* Send the request to the MCP */
1626 if (!BNX2X_NOMCP(sc)) {
1627 reset_code = bnx2x_fw_command(sc, reset_code, 0);
1629 reset_code = bnx2x_nic_unload_no_mcp(sc);
1635 /* send UNLOAD_DONE command to the MCP */
1636 static void bnx2x_send_unload_done(struct bnx2x_softc *sc, uint8_t keep_link)
1638 uint32_t reset_param =
1639 keep_link ? DRV_MSG_CODE_UNLOAD_SKIP_LINK_RESET : 0;
1641 /* Report UNLOAD_DONE to MCP */
1642 if (!BNX2X_NOMCP(sc)) {
1643 bnx2x_fw_command(sc, DRV_MSG_CODE_UNLOAD_DONE, reset_param);
1647 static int bnx2x_func_wait_started(struct bnx2x_softc *sc)
1651 if (!sc->port.pmf) {
1656 * (assumption: No Attention from MCP at this stage)
1657 * PMF probably in the middle of TX disable/enable transaction
1658 * 1. Sync IRS for default SB
1659 * 2. Sync SP queue - this guarantees us that attention handling started
1660 * 3. Wait, that TX disable/enable transaction completes
1662 * 1+2 guarantee that if DCBX attention was scheduled it already changed
1663 * pending bit of transaction from STARTED-->TX_STOPPED, if we already
1664 * received completion for the transaction the state is TX_STOPPED.
1665 * State will return to STARTED after completion of TX_STOPPED-->STARTED
1669 while (ecore_func_get_state(sc, &sc->func_obj) !=
1670 ECORE_F_STATE_STARTED && tout--) {
1674 if (ecore_func_get_state(sc, &sc->func_obj) != ECORE_F_STATE_STARTED) {
1676 * Failed to complete the transaction in a "good way"
1677 * Force both transactions with CLR bit.
1679 struct ecore_func_state_params func_params = { NULL };
1681 PMD_DRV_LOG(NOTICE, sc, "Unexpected function state! "
1682 "Forcing STARTED-->TX_STOPPED-->STARTED");
1684 func_params.f_obj = &sc->func_obj;
1685 bnx2x_set_bit(RAMROD_DRV_CLR_ONLY, &func_params.ramrod_flags);
1687 /* STARTED-->TX_STOPPED */
1688 func_params.cmd = ECORE_F_CMD_TX_STOP;
1689 ecore_func_state_change(sc, &func_params);
1691 /* TX_STOPPED-->STARTED */
1692 func_params.cmd = ECORE_F_CMD_TX_START;
1693 return ecore_func_state_change(sc, &func_params);
1699 static int bnx2x_stop_queue(struct bnx2x_softc *sc, int index)
1701 struct bnx2x_fastpath *fp = &sc->fp[index];
1702 struct ecore_queue_state_params q_params = { NULL };
1705 PMD_DRV_LOG(DEBUG, sc, "stopping queue %d cid %d", index, fp->index);
1707 q_params.q_obj = &sc->sp_objs[fp->index].q_obj;
1708 /* We want to wait for completion in this context */
1709 bnx2x_set_bit(RAMROD_COMP_WAIT, &q_params.ramrod_flags);
1711 /* Stop the primary connection: */
1713 /* ...halt the connection */
1714 q_params.cmd = ECORE_Q_CMD_HALT;
1715 rc = ecore_queue_state_change(sc, &q_params);
1720 /* ...terminate the connection */
1721 q_params.cmd = ECORE_Q_CMD_TERMINATE;
1722 memset(&q_params.params.terminate, 0,
1723 sizeof(q_params.params.terminate));
1724 q_params.params.terminate.cid_index = FIRST_TX_COS_INDEX;
1725 rc = ecore_queue_state_change(sc, &q_params);
1730 /* ...delete cfc entry */
1731 q_params.cmd = ECORE_Q_CMD_CFC_DEL;
1732 memset(&q_params.params.cfc_del, 0, sizeof(q_params.params.cfc_del));
1733 q_params.params.cfc_del.cid_index = FIRST_TX_COS_INDEX;
1734 return ecore_queue_state_change(sc, &q_params);
1737 /* wait for the outstanding SP commands */
1738 static uint8_t bnx2x_wait_sp_comp(struct bnx2x_softc *sc, unsigned long mask)
1741 int tout = 5000; /* wait for 5 secs tops */
1745 if (!(atomic_load_acq_long(&sc->sp_state) & mask)) {
1754 tmp = atomic_load_acq_long(&sc->sp_state);
1756 PMD_DRV_LOG(INFO, sc, "Filtering completion timed out: "
1757 "sp_state 0x%lx, mask 0x%lx", tmp, mask);
1764 static int bnx2x_func_stop(struct bnx2x_softc *sc)
1766 struct ecore_func_state_params func_params = { NULL };
1769 /* prepare parameters for function state transitions */
1770 bnx2x_set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags);
1771 func_params.f_obj = &sc->func_obj;
1772 func_params.cmd = ECORE_F_CMD_STOP;
1775 * Try to stop the function the 'good way'. If it fails (in case
1776 * of a parity error during bnx2x_chip_cleanup()) and we are
1777 * not in a debug mode, perform a state transaction in order to
1778 * enable further HW_RESET transaction.
1780 rc = ecore_func_state_change(sc, &func_params);
1782 PMD_DRV_LOG(NOTICE, sc, "FUNC_STOP ramrod failed. "
1783 "Running a dry transaction");
1784 bnx2x_set_bit(RAMROD_DRV_CLR_ONLY, &func_params.ramrod_flags);
1785 return ecore_func_state_change(sc, &func_params);
1791 static int bnx2x_reset_hw(struct bnx2x_softc *sc, uint32_t load_code)
1793 struct ecore_func_state_params func_params = { NULL };
1795 /* Prepare parameters for function state transitions */
1796 bnx2x_set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags);
1798 func_params.f_obj = &sc->func_obj;
1799 func_params.cmd = ECORE_F_CMD_HW_RESET;
1801 func_params.params.hw_init.load_phase = load_code;
1803 return ecore_func_state_change(sc, &func_params);
1806 static void bnx2x_int_disable_sync(struct bnx2x_softc *sc, int disable_hw)
1809 /* prevent the HW from sending interrupts */
1810 bnx2x_int_disable(sc);
1815 bnx2x_chip_cleanup(struct bnx2x_softc *sc, uint32_t unload_mode, uint8_t keep_link)
1817 int port = SC_PORT(sc);
1818 struct ecore_mcast_ramrod_params rparam = { NULL };
1819 uint32_t reset_code;
1822 bnx2x_drain_tx_queues(sc);
1824 /* give HW time to discard old tx messages */
1827 /* Clean all ETH MACs */
1828 rc = bnx2x_del_all_macs(sc, &sc->sp_objs[0].mac_obj, ECORE_ETH_MAC,
1831 PMD_DRV_LOG(NOTICE, sc,
1832 "Failed to delete all ETH MACs (%d)", rc);
1835 /* Clean up UC list */
1836 rc = bnx2x_del_all_macs(sc, &sc->sp_objs[0].mac_obj, ECORE_UC_LIST_MAC,
1839 PMD_DRV_LOG(NOTICE, sc,
1840 "Failed to delete UC MACs list (%d)", rc);
1844 REG_WR(sc, NIG_REG_LLH0_FUNC_EN + port * 8, 0);
1846 /* Set "drop all" to stop Rx */
1849 * We need to take the if_maddr_lock() here in order to prevent
1850 * a race between the completion code and this code.
1853 if (bnx2x_test_bit(ECORE_FILTER_RX_MODE_PENDING, &sc->sp_state)) {
1854 bnx2x_set_bit(ECORE_FILTER_RX_MODE_SCHED, &sc->sp_state);
1856 bnx2x_set_storm_rx_mode(sc);
1859 /* Clean up multicast configuration */
1860 rparam.mcast_obj = &sc->mcast_obj;
1861 rc = ecore_config_mcast(sc, &rparam, ECORE_MCAST_CMD_DEL);
1863 PMD_DRV_LOG(NOTICE, sc,
1864 "Failed to send DEL MCAST command (%d)", rc);
1868 * Send the UNLOAD_REQUEST to the MCP. This will return if
1869 * this function should perform FUNCTION, PORT, or COMMON HW
1872 reset_code = bnx2x_send_unload_req(sc, unload_mode);
1875 * (assumption: No Attention from MCP at this stage)
1876 * PMF probably in the middle of TX disable/enable transaction
1878 rc = bnx2x_func_wait_started(sc);
1880 PMD_DRV_LOG(NOTICE, sc, "bnx2x_func_wait_started failed");
1884 * Close multi and leading connections
1885 * Completions for ramrods are collected in a synchronous way
1887 for (i = 0; i < sc->num_queues; i++) {
1888 if (bnx2x_stop_queue(sc, i)) {
1894 * If SP settings didn't get completed so far - something
1895 * very wrong has happen.
1897 if (!bnx2x_wait_sp_comp(sc, ~0x0UL)) {
1898 PMD_DRV_LOG(NOTICE, sc, "Common slow path ramrods got stuck!");
1903 rc = bnx2x_func_stop(sc);
1905 PMD_DRV_LOG(NOTICE, sc, "Function stop failed!");
1908 /* disable HW interrupts */
1909 bnx2x_int_disable_sync(sc, TRUE);
1911 /* Reset the chip */
1912 rc = bnx2x_reset_hw(sc, reset_code);
1914 PMD_DRV_LOG(NOTICE, sc, "Hardware reset failed");
1917 /* Report UNLOAD_DONE to MCP */
1918 bnx2x_send_unload_done(sc, keep_link);
1921 static void bnx2x_disable_close_the_gate(struct bnx2x_softc *sc)
1925 PMD_DRV_LOG(DEBUG, sc, "Disabling 'close the gates'");
1927 val = REG_RD(sc, MISC_REG_AEU_GENERAL_MASK);
1928 val &= ~(MISC_AEU_GENERAL_MASK_REG_AEU_PXP_CLOSE_MASK |
1929 MISC_AEU_GENERAL_MASK_REG_AEU_NIG_CLOSE_MASK);
1930 REG_WR(sc, MISC_REG_AEU_GENERAL_MASK, val);
1934 * Cleans the object that have internal lists without sending
1935 * ramrods. Should be run when interrutps are disabled.
1937 static void bnx2x_squeeze_objects(struct bnx2x_softc *sc)
1939 unsigned long ramrod_flags = 0, vlan_mac_flags = 0;
1940 struct ecore_mcast_ramrod_params rparam = { NULL };
1941 struct ecore_vlan_mac_obj *mac_obj = &sc->sp_objs->mac_obj;
1944 /* Cleanup MACs' object first... */
1946 /* Wait for completion of requested */
1947 bnx2x_set_bit(RAMROD_COMP_WAIT, &ramrod_flags);
1948 /* Perform a dry cleanup */
1949 bnx2x_set_bit(RAMROD_DRV_CLR_ONLY, &ramrod_flags);
1951 /* Clean ETH primary MAC */
1952 bnx2x_set_bit(ECORE_ETH_MAC, &vlan_mac_flags);
1953 rc = mac_obj->delete_all(sc, &sc->sp_objs->mac_obj, &vlan_mac_flags,
1956 PMD_DRV_LOG(NOTICE, sc, "Failed to clean ETH MACs (%d)", rc);
1959 /* Cleanup UC list */
1961 bnx2x_set_bit(ECORE_UC_LIST_MAC, &vlan_mac_flags);
1962 rc = mac_obj->delete_all(sc, mac_obj, &vlan_mac_flags, &ramrod_flags);
1964 PMD_DRV_LOG(NOTICE, sc,
1965 "Failed to clean UC list MACs (%d)", rc);
1968 /* Now clean mcast object... */
1970 rparam.mcast_obj = &sc->mcast_obj;
1971 bnx2x_set_bit(RAMROD_DRV_CLR_ONLY, &rparam.ramrod_flags);
1973 /* Add a DEL command... */
1974 rc = ecore_config_mcast(sc, &rparam, ECORE_MCAST_CMD_DEL);
1976 PMD_DRV_LOG(NOTICE, sc,
1977 "Failed to send DEL MCAST command (%d)", rc);
1980 /* now wait until all pending commands are cleared */
1982 rc = ecore_config_mcast(sc, &rparam, ECORE_MCAST_CMD_CONT);
1985 PMD_DRV_LOG(NOTICE, sc,
1986 "Failed to clean MCAST object (%d)", rc);
1990 rc = ecore_config_mcast(sc, &rparam, ECORE_MCAST_CMD_CONT);
1994 /* stop the controller */
1995 __attribute__ ((noinline))
1997 bnx2x_nic_unload(struct bnx2x_softc *sc, uint32_t unload_mode, uint8_t keep_link)
1999 uint8_t global = FALSE;
2002 PMD_DRV_LOG(DEBUG, sc, "Starting NIC unload...");
2004 /* stop the periodic callout */
2005 bnx2x_periodic_stop(sc);
2007 /* mark driver as unloaded in shmem2 */
2008 if (IS_PF(sc) && SHMEM2_HAS(sc, drv_capabilities_flag)) {
2009 val = SHMEM2_RD(sc, drv_capabilities_flag[SC_FW_MB_IDX(sc)]);
2010 SHMEM2_WR(sc, drv_capabilities_flag[SC_FW_MB_IDX(sc)],
2011 val & ~DRV_FLAGS_CAPABILITIES_LOADED_L2);
2014 if (IS_PF(sc) && sc->recovery_state != BNX2X_RECOVERY_DONE &&
2015 (sc->state == BNX2X_STATE_CLOSED || sc->state == BNX2X_STATE_ERROR)) {
2017 * We can get here if the driver has been unloaded
2018 * during parity error recovery and is either waiting for a
2019 * leader to complete or for other functions to unload and
2020 * then ifconfig down has been issued. In this case we want to
2021 * unload and let other functions to complete a recovery
2024 sc->recovery_state = BNX2X_RECOVERY_DONE;
2026 bnx2x_release_leader_lock(sc);
2029 PMD_DRV_LOG(NOTICE, sc, "Can't unload in closed or error state");
2034 * Nothing to do during unload if previous bnx2x_nic_load()
2035 * did not completed succesfully - all resourses are released.
2037 if ((sc->state == BNX2X_STATE_CLOSED) || (sc->state == BNX2X_STATE_ERROR)) {
2041 sc->state = BNX2X_STATE_CLOSING_WAITING_HALT;
2044 sc->rx_mode = BNX2X_RX_MODE_NONE;
2045 bnx2x_set_rx_mode(sc);
2049 /* set ALWAYS_ALIVE bit in shmem */
2050 sc->fw_drv_pulse_wr_seq |= DRV_PULSE_ALWAYS_ALIVE;
2052 bnx2x_drv_pulse(sc);
2054 bnx2x_stats_handle(sc, STATS_EVENT_STOP);
2055 bnx2x_save_statistics(sc);
2058 /* wait till consumers catch up with producers in all queues */
2059 bnx2x_drain_tx_queues(sc);
2061 /* if VF indicate to PF this function is going down (PF will delete sp
2062 * elements and clear initializations
2065 bnx2x_vf_unload(sc);
2066 } else if (unload_mode != UNLOAD_RECOVERY) {
2067 /* if this is a normal/close unload need to clean up chip */
2068 bnx2x_chip_cleanup(sc, unload_mode, keep_link);
2070 /* Send the UNLOAD_REQUEST to the MCP */
2071 bnx2x_send_unload_req(sc, unload_mode);
2074 * Prevent transactions to host from the functions on the
2075 * engine that doesn't reset global blocks in case of global
2076 * attention once gloabl blocks are reset and gates are opened
2077 * (the engine which leader will perform the recovery
2080 if (!CHIP_IS_E1x(sc)) {
2081 bnx2x_pf_disable(sc);
2084 /* disable HW interrupts */
2085 bnx2x_int_disable_sync(sc, TRUE);
2087 /* Report UNLOAD_DONE to MCP */
2088 bnx2x_send_unload_done(sc, FALSE);
2092 * At this stage no more interrupts will arrive so we may safely clean
2093 * the queue'able objects here in case they failed to get cleaned so far.
2096 bnx2x_squeeze_objects(sc);
2099 /* There should be no more pending SP commands at this stage */
2108 bnx2x_free_fw_stats_mem(sc);
2110 sc->state = BNX2X_STATE_CLOSED;
2113 * Check if there are pending parity attentions. If there are - set
2114 * RECOVERY_IN_PROGRESS.
2116 if (IS_PF(sc) && bnx2x_chk_parity_attn(sc, &global, FALSE)) {
2117 bnx2x_set_reset_in_progress(sc);
2119 /* Set RESET_IS_GLOBAL if needed */
2121 bnx2x_set_reset_global(sc);
2126 * The last driver must disable a "close the gate" if there is no
2127 * parity attention or "process kill" pending.
2129 if (IS_PF(sc) && !bnx2x_clear_pf_load(sc) &&
2130 bnx2x_reset_is_done(sc, SC_PATH(sc))) {
2131 bnx2x_disable_close_the_gate(sc);
2134 PMD_DRV_LOG(DEBUG, sc, "Ended NIC unload");
2140 * Encapsulte an mbuf cluster into the tx bd chain and makes the memory
2141 * visible to the controller.
2143 * If an mbuf is submitted to this routine and cannot be given to the
2144 * controller (e.g. it has too many fragments) then the function may free
2145 * the mbuf and return to the caller.
2148 * int: Number of TX BDs used for the mbuf
2150 * Note the side effect that an mbuf may be freed if it causes a problem.
2152 int bnx2x_tx_encap(struct bnx2x_tx_queue *txq, struct rte_mbuf *m0)
2154 struct eth_tx_start_bd *tx_start_bd;
2155 uint16_t bd_prod, pkt_prod;
2156 struct bnx2x_softc *sc;
2160 bd_prod = txq->tx_bd_tail;
2161 pkt_prod = txq->tx_pkt_tail;
2163 txq->sw_ring[TX_BD(pkt_prod, txq)] = m0;
2165 tx_start_bd = &txq->tx_ring[TX_BD(bd_prod, txq)].start_bd;
2168 rte_cpu_to_le_64(rte_mbuf_data_dma_addr(m0));
2169 tx_start_bd->nbytes = rte_cpu_to_le_16(m0->data_len);
2170 tx_start_bd->bd_flags.as_bitfield = ETH_TX_BD_FLAGS_START_BD;
2171 tx_start_bd->general_data =
2172 (1 << ETH_TX_START_BD_HDR_NBDS_SHIFT);
2174 tx_start_bd->nbd = rte_cpu_to_le_16(2);
2176 if (m0->ol_flags & PKT_TX_VLAN_PKT) {
2177 tx_start_bd->vlan_or_ethertype =
2178 rte_cpu_to_le_16(m0->vlan_tci);
2179 tx_start_bd->bd_flags.as_bitfield |=
2180 (X_ETH_OUTBAND_VLAN <<
2181 ETH_TX_BD_FLAGS_VLAN_MODE_SHIFT);
2184 tx_start_bd->vlan_or_ethertype =
2185 rte_cpu_to_le_16(pkt_prod);
2187 struct ether_hdr *eh =
2188 rte_pktmbuf_mtod(m0, struct ether_hdr *);
2190 tx_start_bd->vlan_or_ethertype =
2191 rte_cpu_to_le_16(rte_be_to_cpu_16(eh->ether_type));
2195 bd_prod = NEXT_TX_BD(bd_prod);
2197 struct eth_tx_parse_bd_e2 *tx_parse_bd;
2198 const struct ether_hdr *eh =
2199 rte_pktmbuf_mtod(m0, struct ether_hdr *);
2200 uint8_t mac_type = UNICAST_ADDRESS;
2203 &txq->tx_ring[TX_BD(bd_prod, txq)].parse_bd_e2;
2204 if (is_multicast_ether_addr(&eh->d_addr)) {
2205 if (is_broadcast_ether_addr(&eh->d_addr))
2206 mac_type = BROADCAST_ADDRESS;
2208 mac_type = MULTICAST_ADDRESS;
2210 tx_parse_bd->parsing_data =
2211 (mac_type << ETH_TX_PARSE_BD_E2_ETH_ADDR_TYPE_SHIFT);
2213 rte_memcpy(&tx_parse_bd->data.mac_addr.dst_hi,
2214 &eh->d_addr.addr_bytes[0], 2);
2215 rte_memcpy(&tx_parse_bd->data.mac_addr.dst_mid,
2216 &eh->d_addr.addr_bytes[2], 2);
2217 rte_memcpy(&tx_parse_bd->data.mac_addr.dst_lo,
2218 &eh->d_addr.addr_bytes[4], 2);
2219 rte_memcpy(&tx_parse_bd->data.mac_addr.src_hi,
2220 &eh->s_addr.addr_bytes[0], 2);
2221 rte_memcpy(&tx_parse_bd->data.mac_addr.src_mid,
2222 &eh->s_addr.addr_bytes[2], 2);
2223 rte_memcpy(&tx_parse_bd->data.mac_addr.src_lo,
2224 &eh->s_addr.addr_bytes[4], 2);
2226 tx_parse_bd->data.mac_addr.dst_hi =
2227 rte_cpu_to_be_16(tx_parse_bd->data.mac_addr.dst_hi);
2228 tx_parse_bd->data.mac_addr.dst_mid =
2229 rte_cpu_to_be_16(tx_parse_bd->data.
2231 tx_parse_bd->data.mac_addr.dst_lo =
2232 rte_cpu_to_be_16(tx_parse_bd->data.mac_addr.dst_lo);
2233 tx_parse_bd->data.mac_addr.src_hi =
2234 rte_cpu_to_be_16(tx_parse_bd->data.mac_addr.src_hi);
2235 tx_parse_bd->data.mac_addr.src_mid =
2236 rte_cpu_to_be_16(tx_parse_bd->data.
2238 tx_parse_bd->data.mac_addr.src_lo =
2239 rte_cpu_to_be_16(tx_parse_bd->data.mac_addr.src_lo);
2242 "PBD dst %x %x %x src %x %x %x p_data %x",
2243 tx_parse_bd->data.mac_addr.dst_hi,
2244 tx_parse_bd->data.mac_addr.dst_mid,
2245 tx_parse_bd->data.mac_addr.dst_lo,
2246 tx_parse_bd->data.mac_addr.src_hi,
2247 tx_parse_bd->data.mac_addr.src_mid,
2248 tx_parse_bd->data.mac_addr.src_lo,
2249 tx_parse_bd->parsing_data);
2253 "start bd: nbytes %d flags %x vlan %x\n",
2254 tx_start_bd->nbytes,
2255 tx_start_bd->bd_flags.as_bitfield,
2256 tx_start_bd->vlan_or_ethertype);
2258 bd_prod = NEXT_TX_BD(bd_prod);
2261 if (TX_IDX(bd_prod) < 2)
2264 txq->nb_tx_avail -= 2;
2265 txq->tx_bd_tail = bd_prod;
2266 txq->tx_pkt_tail = pkt_prod;
2271 static uint16_t bnx2x_cid_ilt_lines(struct bnx2x_softc *sc)
2273 return L2_ILT_LINES(sc);
2276 static void bnx2x_ilt_set_info(struct bnx2x_softc *sc)
2278 struct ilt_client_info *ilt_client;
2279 struct ecore_ilt *ilt = sc->ilt;
2282 PMD_INIT_FUNC_TRACE(sc);
2284 ilt->start_line = FUNC_ILT_BASE(SC_FUNC(sc));
2287 ilt_client = &ilt->clients[ILT_CLIENT_CDU];
2288 ilt_client->client_num = ILT_CLIENT_CDU;
2289 ilt_client->page_size = CDU_ILT_PAGE_SZ;
2290 ilt_client->flags = ILT_CLIENT_SKIP_MEM;
2291 ilt_client->start = line;
2292 line += bnx2x_cid_ilt_lines(sc);
2294 if (CNIC_SUPPORT(sc)) {
2295 line += CNIC_ILT_LINES;
2298 ilt_client->end = (line - 1);
2301 if (QM_INIT(sc->qm_cid_count)) {
2302 ilt_client = &ilt->clients[ILT_CLIENT_QM];
2303 ilt_client->client_num = ILT_CLIENT_QM;
2304 ilt_client->page_size = QM_ILT_PAGE_SZ;
2305 ilt_client->flags = 0;
2306 ilt_client->start = line;
2308 /* 4 bytes for each cid */
2309 line += DIV_ROUND_UP(sc->qm_cid_count * QM_QUEUES_PER_FUNC * 4,
2312 ilt_client->end = (line - 1);
2315 if (CNIC_SUPPORT(sc)) {
2317 ilt_client = &ilt->clients[ILT_CLIENT_SRC];
2318 ilt_client->client_num = ILT_CLIENT_SRC;
2319 ilt_client->page_size = SRC_ILT_PAGE_SZ;
2320 ilt_client->flags = 0;
2321 ilt_client->start = line;
2322 line += SRC_ILT_LINES;
2323 ilt_client->end = (line - 1);
2326 ilt_client = &ilt->clients[ILT_CLIENT_TM];
2327 ilt_client->client_num = ILT_CLIENT_TM;
2328 ilt_client->page_size = TM_ILT_PAGE_SZ;
2329 ilt_client->flags = 0;
2330 ilt_client->start = line;
2331 line += TM_ILT_LINES;
2332 ilt_client->end = (line - 1);
2335 assert((line <= ILT_MAX_LINES));
2338 static void bnx2x_set_fp_rx_buf_size(struct bnx2x_softc *sc)
2342 for (i = 0; i < sc->num_queues; i++) {
2343 /* get the Rx buffer size for RX frames */
2344 sc->fp[i].rx_buf_size =
2345 (IP_HEADER_ALIGNMENT_PADDING + ETH_OVERHEAD + sc->mtu);
2349 int bnx2x_alloc_ilt_mem(struct bnx2x_softc *sc)
2352 sc->ilt = rte_malloc("", sizeof(struct ecore_ilt), RTE_CACHE_LINE_SIZE);
2354 return sc->ilt == NULL;
2357 static int bnx2x_alloc_ilt_lines_mem(struct bnx2x_softc *sc)
2359 sc->ilt->lines = rte_calloc("",
2360 sizeof(struct ilt_line), ILT_MAX_LINES,
2361 RTE_CACHE_LINE_SIZE);
2362 return sc->ilt->lines == NULL;
2365 void bnx2x_free_ilt_mem(struct bnx2x_softc *sc)
2371 static void bnx2x_free_ilt_lines_mem(struct bnx2x_softc *sc)
2373 if (sc->ilt->lines != NULL) {
2374 rte_free(sc->ilt->lines);
2375 sc->ilt->lines = NULL;
2379 static void bnx2x_free_mem(struct bnx2x_softc *sc)
2383 for (i = 0; i < L2_ILT_LINES(sc); i++) {
2384 sc->context[i].vcxt = NULL;
2385 sc->context[i].size = 0;
2388 ecore_ilt_mem_op(sc, ILT_MEMOP_FREE);
2390 bnx2x_free_ilt_lines_mem(sc);
2393 static int bnx2x_alloc_mem(struct bnx2x_softc *sc)
2398 char cdu_name[RTE_MEMZONE_NAMESIZE];
2401 * Allocate memory for CDU context:
2402 * This memory is allocated separately and not in the generic ILT
2403 * functions because CDU differs in few aspects:
2404 * 1. There can be multiple entities allocating memory for context -
2405 * regular L2, CNIC, and SRIOV drivers. Each separately controls
2406 * its own ILT lines.
2407 * 2. Since CDU page-size is not a single 4KB page (which is the case
2408 * for the other ILT clients), to be efficient we want to support
2409 * allocation of sub-page-size in the last entry.
2410 * 3. Context pointers are used by the driver to pass to FW / update
2411 * the context (for the other ILT clients the pointers are used just to
2412 * free the memory during unload).
2414 context_size = (sizeof(union cdu_context) * BNX2X_L2_CID_COUNT(sc));
2415 for (i = 0, allocated = 0; allocated < context_size; i++) {
2416 sc->context[i].size = min(CDU_ILT_PAGE_SZ,
2417 (context_size - allocated));
2419 snprintf(cdu_name, sizeof(cdu_name), "cdu_%d", i);
2420 if (bnx2x_dma_alloc(sc, sc->context[i].size,
2421 &sc->context[i].vcxt_dma,
2422 cdu_name, BNX2X_PAGE_SIZE) != 0) {
2427 sc->context[i].vcxt =
2428 (union cdu_context *)sc->context[i].vcxt_dma.vaddr;
2430 allocated += sc->context[i].size;
2433 bnx2x_alloc_ilt_lines_mem(sc);
2435 if (ecore_ilt_mem_op(sc, ILT_MEMOP_ALLOC)) {
2436 PMD_DRV_LOG(NOTICE, sc, "ecore_ilt_mem_op ILT_MEMOP_ALLOC failed");
2444 static void bnx2x_free_fw_stats_mem(struct bnx2x_softc *sc)
2446 sc->fw_stats_num = 0;
2448 sc->fw_stats_req_size = 0;
2449 sc->fw_stats_req = NULL;
2450 sc->fw_stats_req_mapping = 0;
2452 sc->fw_stats_data_size = 0;
2453 sc->fw_stats_data = NULL;
2454 sc->fw_stats_data_mapping = 0;
2457 static int bnx2x_alloc_fw_stats_mem(struct bnx2x_softc *sc)
2459 uint8_t num_queue_stats;
2460 int num_groups, vf_headroom = 0;
2462 /* number of queues for statistics is number of eth queues */
2463 num_queue_stats = BNX2X_NUM_ETH_QUEUES(sc);
2466 * Total number of FW statistics requests =
2467 * 1 for port stats + 1 for PF stats + num of queues
2469 sc->fw_stats_num = (2 + num_queue_stats);
2472 * Request is built from stats_query_header and an array of
2473 * stats_query_cmd_group each of which contains STATS_QUERY_CMD_COUNT
2474 * rules. The real number or requests is configured in the
2475 * stats_query_header.
2477 num_groups = (sc->fw_stats_num + vf_headroom) / STATS_QUERY_CMD_COUNT;
2478 if ((sc->fw_stats_num + vf_headroom) % STATS_QUERY_CMD_COUNT)
2481 sc->fw_stats_req_size =
2482 (sizeof(struct stats_query_header) +
2483 (num_groups * sizeof(struct stats_query_cmd_group)));
2486 * Data for statistics requests + stats_counter.
2487 * stats_counter holds per-STORM counters that are incremented when
2488 * STORM has finished with the current request. Memory for FCoE
2489 * offloaded statistics are counted anyway, even if they will not be sent.
2490 * VF stats are not accounted for here as the data of VF stats is stored
2491 * in memory allocated by the VF, not here.
2493 sc->fw_stats_data_size =
2494 (sizeof(struct stats_counter) +
2495 sizeof(struct per_port_stats) + sizeof(struct per_pf_stats) +
2496 /* sizeof(struct fcoe_statistics_params) + */
2497 (sizeof(struct per_queue_stats) * num_queue_stats));
2499 if (bnx2x_dma_alloc(sc, (sc->fw_stats_req_size + sc->fw_stats_data_size),
2500 &sc->fw_stats_dma, "fw_stats",
2501 RTE_CACHE_LINE_SIZE) != 0) {
2502 bnx2x_free_fw_stats_mem(sc);
2506 /* set up the shortcuts */
2508 sc->fw_stats_req = (struct bnx2x_fw_stats_req *)sc->fw_stats_dma.vaddr;
2509 sc->fw_stats_req_mapping = sc->fw_stats_dma.paddr;
2512 (struct bnx2x_fw_stats_data *)((uint8_t *) sc->fw_stats_dma.vaddr +
2513 sc->fw_stats_req_size);
2514 sc->fw_stats_data_mapping = (sc->fw_stats_dma.paddr +
2515 sc->fw_stats_req_size);
2522 * 0-7 - Engine0 load counter.
2523 * 8-15 - Engine1 load counter.
2524 * 16 - Engine0 RESET_IN_PROGRESS bit.
2525 * 17 - Engine1 RESET_IN_PROGRESS bit.
2526 * 18 - Engine0 ONE_IS_LOADED. Set when there is at least one active
2527 * function on the engine
2528 * 19 - Engine1 ONE_IS_LOADED.
2529 * 20 - Chip reset flow bit. When set none-leader must wait for both engines
2530 * leader to complete (check for both RESET_IN_PROGRESS bits and not
2531 * for just the one belonging to its engine).
2533 #define BNX2X_RECOVERY_GLOB_REG MISC_REG_GENERIC_POR_1
2534 #define BNX2X_PATH0_LOAD_CNT_MASK 0x000000ff
2535 #define BNX2X_PATH0_LOAD_CNT_SHIFT 0
2536 #define BNX2X_PATH1_LOAD_CNT_MASK 0x0000ff00
2537 #define BNX2X_PATH1_LOAD_CNT_SHIFT 8
2538 #define BNX2X_PATH0_RST_IN_PROG_BIT 0x00010000
2539 #define BNX2X_PATH1_RST_IN_PROG_BIT 0x00020000
2540 #define BNX2X_GLOBAL_RESET_BIT 0x00040000
2542 /* set the GLOBAL_RESET bit, should be run under rtnl lock */
2543 static void bnx2x_set_reset_global(struct bnx2x_softc *sc)
2546 bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG);
2547 val = REG_RD(sc, BNX2X_RECOVERY_GLOB_REG);
2548 REG_WR(sc, BNX2X_RECOVERY_GLOB_REG, val | BNX2X_GLOBAL_RESET_BIT);
2549 bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG);
2552 /* clear the GLOBAL_RESET bit, should be run under rtnl lock */
2553 static void bnx2x_clear_reset_global(struct bnx2x_softc *sc)
2556 bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG);
2557 val = REG_RD(sc, BNX2X_RECOVERY_GLOB_REG);
2558 REG_WR(sc, BNX2X_RECOVERY_GLOB_REG, val & (~BNX2X_GLOBAL_RESET_BIT));
2559 bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG);
2562 /* checks the GLOBAL_RESET bit, should be run under rtnl lock */
2563 static uint8_t bnx2x_reset_is_global(struct bnx2x_softc *sc)
2565 return REG_RD(sc, BNX2X_RECOVERY_GLOB_REG) & BNX2X_GLOBAL_RESET_BIT;
2568 /* clear RESET_IN_PROGRESS bit for the engine, should be run under rtnl lock */
2569 static void bnx2x_set_reset_done(struct bnx2x_softc *sc)
2572 uint32_t bit = SC_PATH(sc) ? BNX2X_PATH1_RST_IN_PROG_BIT :
2573 BNX2X_PATH0_RST_IN_PROG_BIT;
2575 bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG);
2577 val = REG_RD(sc, BNX2X_RECOVERY_GLOB_REG);
2580 REG_WR(sc, BNX2X_RECOVERY_GLOB_REG, val);
2582 bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG);
2585 /* set RESET_IN_PROGRESS for the engine, should be run under rtnl lock */
2586 static void bnx2x_set_reset_in_progress(struct bnx2x_softc *sc)
2589 uint32_t bit = SC_PATH(sc) ? BNX2X_PATH1_RST_IN_PROG_BIT :
2590 BNX2X_PATH0_RST_IN_PROG_BIT;
2592 bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG);
2594 val = REG_RD(sc, BNX2X_RECOVERY_GLOB_REG);
2597 REG_WR(sc, BNX2X_RECOVERY_GLOB_REG, val);
2599 bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG);
2602 /* check RESET_IN_PROGRESS bit for an engine, should be run under rtnl lock */
2603 static uint8_t bnx2x_reset_is_done(struct bnx2x_softc *sc, int engine)
2605 uint32_t val = REG_RD(sc, BNX2X_RECOVERY_GLOB_REG);
2606 uint32_t bit = engine ? BNX2X_PATH1_RST_IN_PROG_BIT :
2607 BNX2X_PATH0_RST_IN_PROG_BIT;
2609 /* return false if bit is set */
2610 return (val & bit) ? FALSE : TRUE;
2613 /* get the load status for an engine, should be run under rtnl lock */
2614 static uint8_t bnx2x_get_load_status(struct bnx2x_softc *sc, int engine)
2616 uint32_t mask = engine ? BNX2X_PATH1_LOAD_CNT_MASK :
2617 BNX2X_PATH0_LOAD_CNT_MASK;
2618 uint32_t shift = engine ? BNX2X_PATH1_LOAD_CNT_SHIFT :
2619 BNX2X_PATH0_LOAD_CNT_SHIFT;
2620 uint32_t val = REG_RD(sc, BNX2X_RECOVERY_GLOB_REG);
2622 val = ((val & mask) >> shift);
2627 /* set pf load mark */
2628 static void bnx2x_set_pf_load(struct bnx2x_softc *sc)
2632 uint32_t mask = SC_PATH(sc) ? BNX2X_PATH1_LOAD_CNT_MASK :
2633 BNX2X_PATH0_LOAD_CNT_MASK;
2634 uint32_t shift = SC_PATH(sc) ? BNX2X_PATH1_LOAD_CNT_SHIFT :
2635 BNX2X_PATH0_LOAD_CNT_SHIFT;
2637 bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG);
2639 PMD_INIT_FUNC_TRACE(sc);
2641 val = REG_RD(sc, BNX2X_RECOVERY_GLOB_REG);
2643 /* get the current counter value */
2644 val1 = ((val & mask) >> shift);
2646 /* set bit of this PF */
2647 val1 |= (1 << SC_ABS_FUNC(sc));
2649 /* clear the old value */
2652 /* set the new one */
2653 val |= ((val1 << shift) & mask);
2655 REG_WR(sc, BNX2X_RECOVERY_GLOB_REG, val);
2657 bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG);
2660 /* clear pf load mark */
2661 static uint8_t bnx2x_clear_pf_load(struct bnx2x_softc *sc)
2664 uint32_t mask = SC_PATH(sc) ? BNX2X_PATH1_LOAD_CNT_MASK :
2665 BNX2X_PATH0_LOAD_CNT_MASK;
2666 uint32_t shift = SC_PATH(sc) ? BNX2X_PATH1_LOAD_CNT_SHIFT :
2667 BNX2X_PATH0_LOAD_CNT_SHIFT;
2669 bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG);
2670 val = REG_RD(sc, BNX2X_RECOVERY_GLOB_REG);
2672 /* get the current counter value */
2673 val1 = (val & mask) >> shift;
2675 /* clear bit of that PF */
2676 val1 &= ~(1 << SC_ABS_FUNC(sc));
2678 /* clear the old value */
2681 /* set the new one */
2682 val |= ((val1 << shift) & mask);
2684 REG_WR(sc, BNX2X_RECOVERY_GLOB_REG, val);
2685 bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG);
2689 /* send load requrest to mcp and analyze response */
2690 static int bnx2x_nic_load_request(struct bnx2x_softc *sc, uint32_t * load_code)
2692 PMD_INIT_FUNC_TRACE(sc);
2696 (SHMEM_RD(sc, func_mb[SC_FW_MB_IDX(sc)].drv_mb_header) &
2697 DRV_MSG_SEQ_NUMBER_MASK);
2699 PMD_DRV_LOG(DEBUG, sc, "initial fw_seq 0x%04x", sc->fw_seq);
2702 /* get the current FW pulse sequence */
2703 sc->fw_drv_pulse_wr_seq =
2704 (SHMEM_RD(sc, func_mb[SC_FW_MB_IDX(sc)].drv_pulse_mb) &
2705 DRV_PULSE_SEQ_MASK);
2707 /* set ALWAYS_ALIVE bit in shmem */
2708 sc->fw_drv_pulse_wr_seq |= DRV_PULSE_ALWAYS_ALIVE;
2709 bnx2x_drv_pulse(sc);
2713 (*load_code) = bnx2x_fw_command(sc, DRV_MSG_CODE_LOAD_REQ,
2714 DRV_MSG_CODE_LOAD_REQ_WITH_LFA);
2716 /* if the MCP fails to respond we must abort */
2717 if (!(*load_code)) {
2718 PMD_DRV_LOG(NOTICE, sc, "MCP response failure!");
2722 /* if MCP refused then must abort */
2723 if ((*load_code) == FW_MSG_CODE_DRV_LOAD_REFUSED) {
2724 PMD_DRV_LOG(NOTICE, sc, "MCP refused load request");
2732 * Check whether another PF has already loaded FW to chip. In virtualized
2733 * environments a pf from anoth VM may have already initialized the device
2734 * including loading FW.
2736 static int bnx2x_nic_load_analyze_req(struct bnx2x_softc *sc, uint32_t load_code)
2738 uint32_t my_fw, loaded_fw;
2740 /* is another pf loaded on this engine? */
2741 if ((load_code != FW_MSG_CODE_DRV_LOAD_COMMON_CHIP) &&
2742 (load_code != FW_MSG_CODE_DRV_LOAD_COMMON)) {
2743 /* build my FW version dword */
2744 my_fw = (BNX2X_5710_FW_MAJOR_VERSION +
2745 (BNX2X_5710_FW_MINOR_VERSION << 8) +
2746 (BNX2X_5710_FW_REVISION_VERSION << 16) +
2747 (BNX2X_5710_FW_ENGINEERING_VERSION << 24));
2749 /* read loaded FW from chip */
2750 loaded_fw = REG_RD(sc, XSEM_REG_PRAM);
2751 PMD_DRV_LOG(DEBUG, sc, "loaded FW 0x%08x / my FW 0x%08x",
2754 /* abort nic load if version mismatch */
2755 if (my_fw != loaded_fw) {
2756 PMD_DRV_LOG(NOTICE, sc,
2757 "FW 0x%08x already loaded (mine is 0x%08x)",
2766 /* mark PMF if applicable */
2767 static void bnx2x_nic_load_pmf(struct bnx2x_softc *sc, uint32_t load_code)
2769 uint32_t ncsi_oem_data_addr;
2771 PMD_INIT_FUNC_TRACE(sc);
2773 if ((load_code == FW_MSG_CODE_DRV_LOAD_COMMON) ||
2774 (load_code == FW_MSG_CODE_DRV_LOAD_COMMON_CHIP) ||
2775 (load_code == FW_MSG_CODE_DRV_LOAD_PORT)) {
2777 * Barrier here for ordering between the writing to sc->port.pmf here
2778 * and reading it from the periodic task.
2786 PMD_DRV_LOG(DEBUG, sc, "pmf %d", sc->port.pmf);
2788 if (load_code == FW_MSG_CODE_DRV_LOAD_COMMON_CHIP) {
2789 if (SHMEM2_HAS(sc, ncsi_oem_data_addr)) {
2790 ncsi_oem_data_addr = SHMEM2_RD(sc, ncsi_oem_data_addr);
2791 if (ncsi_oem_data_addr) {
2793 (ncsi_oem_data_addr +
2794 offsetof(struct glob_ncsi_oem_data,
2795 driver_version)), 0);
2801 static void bnx2x_read_mf_cfg(struct bnx2x_softc *sc)
2803 int n = (CHIP_IS_MODE_4_PORT(sc) ? 2 : 1);
2807 if (BNX2X_NOMCP(sc)) {
2808 return; /* what should be the default bvalue in this case */
2812 * The formula for computing the absolute function number is...
2813 * For 2 port configuration (4 functions per port):
2814 * abs_func = 2 * vn + SC_PORT + SC_PATH
2815 * For 4 port configuration (2 functions per port):
2816 * abs_func = 4 * vn + 2 * SC_PORT + SC_PATH
2818 for (vn = VN_0; vn < SC_MAX_VN_NUM(sc); vn++) {
2819 abs_func = (n * (2 * vn + SC_PORT(sc)) + SC_PATH(sc));
2820 if (abs_func >= E1H_FUNC_MAX) {
2823 sc->devinfo.mf_info.mf_config[vn] =
2824 MFCFG_RD(sc, func_mf_config[abs_func].config);
2827 if (sc->devinfo.mf_info.mf_config[SC_VN(sc)] &
2828 FUNC_MF_CFG_FUNC_DISABLED) {
2829 PMD_DRV_LOG(DEBUG, sc, "mf_cfg function disabled");
2830 sc->flags |= BNX2X_MF_FUNC_DIS;
2832 PMD_DRV_LOG(DEBUG, sc, "mf_cfg function enabled");
2833 sc->flags &= ~BNX2X_MF_FUNC_DIS;
2837 /* acquire split MCP access lock register */
2838 static int bnx2x_acquire_alr(struct bnx2x_softc *sc)
2842 for (j = 0; j < 1000; j++) {
2844 REG_WR(sc, GRCBASE_MCP + 0x9c, val);
2845 val = REG_RD(sc, GRCBASE_MCP + 0x9c);
2846 if (val & (1L << 31))
2852 if (!(val & (1L << 31))) {
2853 PMD_DRV_LOG(NOTICE, sc, "Cannot acquire MCP access lock register");
2860 /* release split MCP access lock register */
2861 static void bnx2x_release_alr(struct bnx2x_softc *sc)
2863 REG_WR(sc, GRCBASE_MCP + 0x9c, 0);
2866 static void bnx2x_fan_failure(struct bnx2x_softc *sc)
2868 int port = SC_PORT(sc);
2869 uint32_t ext_phy_config;
2871 /* mark the failure */
2873 SHMEM_RD(sc, dev_info.port_hw_config[port].external_phy_config);
2875 ext_phy_config &= ~PORT_HW_CFG_XGXS_EXT_PHY_TYPE_MASK;
2876 ext_phy_config |= PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE;
2877 SHMEM_WR(sc, dev_info.port_hw_config[port].external_phy_config,
2880 /* log the failure */
2881 PMD_DRV_LOG(INFO, sc,
2882 "Fan Failure has caused the driver to shutdown "
2883 "the card to prevent permanent damage. "
2884 "Please contact OEM Support for assistance");
2886 rte_panic("Schedule task to handle fan failure");
2889 /* this function is called upon a link interrupt */
2890 static void bnx2x_link_attn(struct bnx2x_softc *sc)
2892 uint32_t pause_enabled = 0;
2893 struct host_port_stats *pstats;
2896 /* Make sure that we are synced with the current statistics */
2897 bnx2x_stats_handle(sc, STATS_EVENT_STOP);
2899 elink_link_update(&sc->link_params, &sc->link_vars);
2901 if (sc->link_vars.link_up) {
2903 /* dropless flow control */
2904 if (sc->dropless_fc) {
2907 if (sc->link_vars.flow_ctrl & ELINK_FLOW_CTRL_TX) {
2912 (BAR_USTRORM_INTMEM +
2913 USTORM_ETH_PAUSE_ENABLED_OFFSET(SC_PORT(sc))),
2917 if (sc->link_vars.mac_type != ELINK_MAC_TYPE_EMAC) {
2918 pstats = BNX2X_SP(sc, port_stats);
2919 /* reset old mac stats */
2920 memset(&(pstats->mac_stx[0]), 0,
2921 sizeof(struct mac_stx));
2924 if (sc->state == BNX2X_STATE_OPEN) {
2925 bnx2x_stats_handle(sc, STATS_EVENT_LINK_UP);
2929 if (sc->link_vars.link_up && sc->link_vars.line_speed) {
2930 cmng_fns = bnx2x_get_cmng_fns_mode(sc);
2932 if (cmng_fns != CMNG_FNS_NONE) {
2933 bnx2x_cmng_fns_init(sc, FALSE, cmng_fns);
2934 storm_memset_cmng(sc, &sc->cmng, SC_PORT(sc));
2938 bnx2x_link_report_locked(sc);
2941 bnx2x_link_sync_notify(sc);
2945 static void bnx2x_attn_int_asserted(struct bnx2x_softc *sc, uint32_t asserted)
2947 int port = SC_PORT(sc);
2948 uint32_t aeu_addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 :
2949 MISC_REG_AEU_MASK_ATTN_FUNC_0;
2950 uint32_t nig_int_mask_addr = port ? NIG_REG_MASK_INTERRUPT_PORT1 :
2951 NIG_REG_MASK_INTERRUPT_PORT0;
2953 uint32_t nig_mask = 0;
2958 if (sc->attn_state & asserted) {
2959 PMD_DRV_LOG(ERR, sc, "IGU ERROR attn=0x%08x", asserted);
2962 bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
2964 aeu_mask = REG_RD(sc, aeu_addr);
2966 aeu_mask &= ~(asserted & 0x3ff);
2968 REG_WR(sc, aeu_addr, aeu_mask);
2970 bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
2972 sc->attn_state |= asserted;
2974 if (asserted & ATTN_HARD_WIRED_MASK) {
2975 if (asserted & ATTN_NIG_FOR_FUNC) {
2977 bnx2x_acquire_phy_lock(sc);
2978 /* save nig interrupt mask */
2979 nig_mask = REG_RD(sc, nig_int_mask_addr);
2981 /* If nig_mask is not set, no need to call the update function */
2983 REG_WR(sc, nig_int_mask_addr, 0);
2985 bnx2x_link_attn(sc);
2988 /* handle unicore attn? */
2991 if (asserted & ATTN_SW_TIMER_4_FUNC) {
2992 PMD_DRV_LOG(DEBUG, sc, "ATTN_SW_TIMER_4_FUNC!");
2995 if (asserted & GPIO_2_FUNC) {
2996 PMD_DRV_LOG(DEBUG, sc, "GPIO_2_FUNC!");
2999 if (asserted & GPIO_3_FUNC) {
3000 PMD_DRV_LOG(DEBUG, sc, "GPIO_3_FUNC!");
3003 if (asserted & GPIO_4_FUNC) {
3004 PMD_DRV_LOG(DEBUG, sc, "GPIO_4_FUNC!");
3008 if (asserted & ATTN_GENERAL_ATTN_1) {
3009 PMD_DRV_LOG(DEBUG, sc, "ATTN_GENERAL_ATTN_1!");
3010 REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_1, 0x0);
3012 if (asserted & ATTN_GENERAL_ATTN_2) {
3013 PMD_DRV_LOG(DEBUG, sc, "ATTN_GENERAL_ATTN_2!");
3014 REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_2, 0x0);
3016 if (asserted & ATTN_GENERAL_ATTN_3) {
3017 PMD_DRV_LOG(DEBUG, sc, "ATTN_GENERAL_ATTN_3!");
3018 REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_3, 0x0);
3021 if (asserted & ATTN_GENERAL_ATTN_4) {
3022 PMD_DRV_LOG(DEBUG, sc, "ATTN_GENERAL_ATTN_4!");
3023 REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_4, 0x0);
3025 if (asserted & ATTN_GENERAL_ATTN_5) {
3026 PMD_DRV_LOG(DEBUG, sc, "ATTN_GENERAL_ATTN_5!");
3027 REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_5, 0x0);
3029 if (asserted & ATTN_GENERAL_ATTN_6) {
3030 PMD_DRV_LOG(DEBUG, sc, "ATTN_GENERAL_ATTN_6!");
3031 REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_6, 0x0);
3036 if (sc->devinfo.int_block == INT_BLOCK_HC) {
3038 (HC_REG_COMMAND_REG + port * 32 +
3039 COMMAND_REG_ATTN_BITS_SET);
3041 reg_addr = (BAR_IGU_INTMEM + IGU_CMD_ATTN_BIT_SET_UPPER * 8);
3044 PMD_DRV_LOG(DEBUG, sc, "about to mask 0x%08x at %s addr 0x%08x",
3046 (sc->devinfo.int_block == INT_BLOCK_HC) ? "HC" : "IGU",
3048 REG_WR(sc, reg_addr, asserted);
3050 /* now set back the mask */
3051 if (asserted & ATTN_NIG_FOR_FUNC) {
3053 * Verify that IGU ack through BAR was written before restoring
3054 * NIG mask. This loop should exit after 2-3 iterations max.
3056 if (sc->devinfo.int_block != INT_BLOCK_HC) {
3061 REG_RD(sc, IGU_REG_ATTENTION_ACK_BITS);
3062 } while (((igu_acked & ATTN_NIG_FOR_FUNC) == 0)
3063 && (++cnt < MAX_IGU_ATTN_ACK_TO));
3066 PMD_DRV_LOG(ERR, sc,
3067 "Failed to verify IGU ack on time");
3073 REG_WR(sc, nig_int_mask_addr, nig_mask);
3075 bnx2x_release_phy_lock(sc);
3080 bnx2x_print_next_block(__rte_unused struct bnx2x_softc *sc, __rte_unused int idx,
3081 __rte_unused const char *blk)
3083 PMD_DRV_LOG(INFO, sc, "%s%s", idx ? ", " : "", blk);
3087 bnx2x_check_blocks_with_parity0(struct bnx2x_softc *sc, uint32_t sig, int par_num,
3090 uint32_t cur_bit = 0;
3093 for (i = 0; sig; i++) {
3094 cur_bit = ((uint32_t) 0x1 << i);
3095 if (sig & cur_bit) {
3097 case AEU_INPUTS_ATTN_BITS_BRB_PARITY_ERROR:
3099 bnx2x_print_next_block(sc, par_num++,
3102 case AEU_INPUTS_ATTN_BITS_PARSER_PARITY_ERROR:
3104 bnx2x_print_next_block(sc, par_num++,
3107 case AEU_INPUTS_ATTN_BITS_TSDM_PARITY_ERROR:
3109 bnx2x_print_next_block(sc, par_num++,
3112 case AEU_INPUTS_ATTN_BITS_SEARCHER_PARITY_ERROR:
3114 bnx2x_print_next_block(sc, par_num++,
3117 case AEU_INPUTS_ATTN_BITS_TCM_PARITY_ERROR:
3119 bnx2x_print_next_block(sc, par_num++,
3122 case AEU_INPUTS_ATTN_BITS_TSEMI_PARITY_ERROR:
3124 bnx2x_print_next_block(sc, par_num++,
3127 case AEU_INPUTS_ATTN_BITS_PBCLIENT_PARITY_ERROR:
3129 bnx2x_print_next_block(sc, par_num++,
3143 bnx2x_check_blocks_with_parity1(struct bnx2x_softc *sc, uint32_t sig, int par_num,
3144 uint8_t * global, uint8_t print)
3147 uint32_t cur_bit = 0;
3148 for (i = 0; sig; i++) {
3149 cur_bit = ((uint32_t) 0x1 << i);
3150 if (sig & cur_bit) {
3152 case AEU_INPUTS_ATTN_BITS_PBF_PARITY_ERROR:
3154 bnx2x_print_next_block(sc, par_num++,
3157 case AEU_INPUTS_ATTN_BITS_QM_PARITY_ERROR:
3159 bnx2x_print_next_block(sc, par_num++,
3162 case AEU_INPUTS_ATTN_BITS_TIMERS_PARITY_ERROR:
3164 bnx2x_print_next_block(sc, par_num++,
3167 case AEU_INPUTS_ATTN_BITS_XSDM_PARITY_ERROR:
3169 bnx2x_print_next_block(sc, par_num++,
3172 case AEU_INPUTS_ATTN_BITS_XCM_PARITY_ERROR:
3174 bnx2x_print_next_block(sc, par_num++,
3177 case AEU_INPUTS_ATTN_BITS_XSEMI_PARITY_ERROR:
3179 bnx2x_print_next_block(sc, par_num++,
3182 case AEU_INPUTS_ATTN_BITS_DOORBELLQ_PARITY_ERROR:
3184 bnx2x_print_next_block(sc, par_num++,
3187 case AEU_INPUTS_ATTN_BITS_NIG_PARITY_ERROR:
3189 bnx2x_print_next_block(sc, par_num++,
3192 case AEU_INPUTS_ATTN_BITS_VAUX_PCI_CORE_PARITY_ERROR:
3194 bnx2x_print_next_block(sc, par_num++,
3198 case AEU_INPUTS_ATTN_BITS_DEBUG_PARITY_ERROR:
3200 bnx2x_print_next_block(sc, par_num++,
3203 case AEU_INPUTS_ATTN_BITS_USDM_PARITY_ERROR:
3205 bnx2x_print_next_block(sc, par_num++,
3208 case AEU_INPUTS_ATTN_BITS_UCM_PARITY_ERROR:
3210 bnx2x_print_next_block(sc, par_num++,
3213 case AEU_INPUTS_ATTN_BITS_USEMI_PARITY_ERROR:
3215 bnx2x_print_next_block(sc, par_num++,
3218 case AEU_INPUTS_ATTN_BITS_UPB_PARITY_ERROR:
3220 bnx2x_print_next_block(sc, par_num++,
3223 case AEU_INPUTS_ATTN_BITS_CSDM_PARITY_ERROR:
3225 bnx2x_print_next_block(sc, par_num++,
3228 case AEU_INPUTS_ATTN_BITS_CCM_PARITY_ERROR:
3230 bnx2x_print_next_block(sc, par_num++,
3244 bnx2x_check_blocks_with_parity2(struct bnx2x_softc *sc, uint32_t sig, int par_num,
3247 uint32_t cur_bit = 0;
3250 for (i = 0; sig; i++) {
3251 cur_bit = ((uint32_t) 0x1 << i);
3252 if (sig & cur_bit) {
3254 case AEU_INPUTS_ATTN_BITS_CSEMI_PARITY_ERROR:
3256 bnx2x_print_next_block(sc, par_num++,
3259 case AEU_INPUTS_ATTN_BITS_PXP_PARITY_ERROR:
3261 bnx2x_print_next_block(sc, par_num++,
3264 case AEU_IN_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR:
3266 bnx2x_print_next_block(sc, par_num++,
3267 "PXPPCICLOCKCLIENT");
3269 case AEU_INPUTS_ATTN_BITS_CFC_PARITY_ERROR:
3271 bnx2x_print_next_block(sc, par_num++,
3274 case AEU_INPUTS_ATTN_BITS_CDU_PARITY_ERROR:
3276 bnx2x_print_next_block(sc, par_num++,
3279 case AEU_INPUTS_ATTN_BITS_DMAE_PARITY_ERROR:
3281 bnx2x_print_next_block(sc, par_num++,
3284 case AEU_INPUTS_ATTN_BITS_IGU_PARITY_ERROR:
3286 bnx2x_print_next_block(sc, par_num++,
3289 case AEU_INPUTS_ATTN_BITS_MISC_PARITY_ERROR:
3291 bnx2x_print_next_block(sc, par_num++,
3305 bnx2x_check_blocks_with_parity3(struct bnx2x_softc *sc, uint32_t sig, int par_num,
3306 uint8_t * global, uint8_t print)
3308 uint32_t cur_bit = 0;
3311 for (i = 0; sig; i++) {
3312 cur_bit = ((uint32_t) 0x1 << i);
3313 if (sig & cur_bit) {
3315 case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_ROM_PARITY:
3317 bnx2x_print_next_block(sc, par_num++,
3321 case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_RX_PARITY:
3323 bnx2x_print_next_block(sc, par_num++,
3327 case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_TX_PARITY:
3329 bnx2x_print_next_block(sc, par_num++,
3333 case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY:
3335 bnx2x_print_next_block(sc, par_num++,
3350 bnx2x_check_blocks_with_parity4(struct bnx2x_softc *sc, uint32_t sig, int par_num,
3353 uint32_t cur_bit = 0;
3356 for (i = 0; sig; i++) {
3357 cur_bit = ((uint32_t) 0x1 << i);
3358 if (sig & cur_bit) {
3360 case AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR:
3362 bnx2x_print_next_block(sc, par_num++,
3365 case AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR:
3367 bnx2x_print_next_block(sc, par_num++,
3381 bnx2x_parity_attn(struct bnx2x_softc *sc, uint8_t * global, uint8_t print,
3386 if ((sig[0] & HW_PRTY_ASSERT_SET_0) ||
3387 (sig[1] & HW_PRTY_ASSERT_SET_1) ||
3388 (sig[2] & HW_PRTY_ASSERT_SET_2) ||
3389 (sig[3] & HW_PRTY_ASSERT_SET_3) ||
3390 (sig[4] & HW_PRTY_ASSERT_SET_4)) {
3391 PMD_DRV_LOG(ERR, sc,
3392 "Parity error: HW block parity attention:"
3393 "[0]:0x%08x [1]:0x%08x [2]:0x%08x [3]:0x%08x [4]:0x%08x",
3394 (uint32_t) (sig[0] & HW_PRTY_ASSERT_SET_0),
3395 (uint32_t) (sig[1] & HW_PRTY_ASSERT_SET_1),
3396 (uint32_t) (sig[2] & HW_PRTY_ASSERT_SET_2),
3397 (uint32_t) (sig[3] & HW_PRTY_ASSERT_SET_3),
3398 (uint32_t) (sig[4] & HW_PRTY_ASSERT_SET_4));
3401 PMD_DRV_LOG(INFO, sc, "Parity errors detected in blocks: ");
3404 bnx2x_check_blocks_with_parity0(sc, sig[0] &
3405 HW_PRTY_ASSERT_SET_0,
3408 bnx2x_check_blocks_with_parity1(sc, sig[1] &
3409 HW_PRTY_ASSERT_SET_1,
3410 par_num, global, print);
3412 bnx2x_check_blocks_with_parity2(sc, sig[2] &
3413 HW_PRTY_ASSERT_SET_2,
3416 bnx2x_check_blocks_with_parity3(sc, sig[3] &
3417 HW_PRTY_ASSERT_SET_3,
3418 par_num, global, print);
3420 bnx2x_check_blocks_with_parity4(sc, sig[4] &
3421 HW_PRTY_ASSERT_SET_4,
3425 PMD_DRV_LOG(INFO, sc, "");
3434 bnx2x_chk_parity_attn(struct bnx2x_softc *sc, uint8_t * global, uint8_t print)
3436 struct attn_route attn = { {0} };
3437 int port = SC_PORT(sc);
3439 attn.sig[0] = REG_RD(sc, MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 + port * 4);
3440 attn.sig[1] = REG_RD(sc, MISC_REG_AEU_AFTER_INVERT_2_FUNC_0 + port * 4);
3441 attn.sig[2] = REG_RD(sc, MISC_REG_AEU_AFTER_INVERT_3_FUNC_0 + port * 4);
3442 attn.sig[3] = REG_RD(sc, MISC_REG_AEU_AFTER_INVERT_4_FUNC_0 + port * 4);
3444 if (!CHIP_IS_E1x(sc))
3446 REG_RD(sc, MISC_REG_AEU_AFTER_INVERT_5_FUNC_0 + port * 4);
3448 return bnx2x_parity_attn(sc, global, print, attn.sig);
3451 static void bnx2x_attn_int_deasserted4(struct bnx2x_softc *sc, uint32_t attn)
3455 if (attn & AEU_INPUTS_ATTN_BITS_PGLUE_HW_INTERRUPT) {
3456 val = REG_RD(sc, PGLUE_B_REG_PGLUE_B_INT_STS_CLR);
3457 PMD_DRV_LOG(INFO, sc, "ERROR: PGLUE hw attention 0x%08x", val);
3458 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_ADDRESS_ERROR)
3459 PMD_DRV_LOG(INFO, sc,
3460 "ERROR: PGLUE_B_PGLUE_B_INT_STS_REG_ADDRESS_ERROR");
3461 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_INCORRECT_RCV_BEHAVIOR)
3462 PMD_DRV_LOG(INFO, sc,
3463 "ERROR: PGLUE_B_PGLUE_B_INT_STS_REG_INCORRECT_RCV_BEHAVIOR");
3464 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_WAS_ERROR_ATTN)
3465 PMD_DRV_LOG(INFO, sc,
3466 "ERROR: PGLUE_B_PGLUE_B_INT_STS_REG_WAS_ERROR_ATTN");
3467 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_VF_LENGTH_VIOLATION_ATTN)
3468 PMD_DRV_LOG(INFO, sc,
3469 "ERROR: PGLUE_B_PGLUE_B_INT_STS_REG_VF_LENGTH_VIOLATION_ATTN");
3471 PGLUE_B_PGLUE_B_INT_STS_REG_VF_GRC_SPACE_VIOLATION_ATTN)
3472 PMD_DRV_LOG(INFO, sc,
3473 "ERROR: PGLUE_B_PGLUE_B_INT_STS_REG_VF_GRC_SPACE_VIOLATION_ATTN");
3475 PGLUE_B_PGLUE_B_INT_STS_REG_VF_MSIX_BAR_VIOLATION_ATTN)
3476 PMD_DRV_LOG(INFO, sc,
3477 "ERROR: PGLUE_B_PGLUE_B_INT_STS_REG_VF_MSIX_BAR_VIOLATION_ATTN");
3478 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_ERROR_ATTN)
3479 PMD_DRV_LOG(INFO, sc,
3480 "ERROR: PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_ERROR_ATTN");
3481 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_IN_TWO_RCBS_ATTN)
3482 PMD_DRV_LOG(INFO, sc,
3483 "ERROR: PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_IN_TWO_RCBS_ATTN");
3484 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_CSSNOOP_FIFO_OVERFLOW)
3485 PMD_DRV_LOG(INFO, sc,
3486 "ERROR: PGLUE_B_PGLUE_B_INT_STS_REG_CSSNOOP_FIFO_OVERFLOW");
3489 if (attn & AEU_INPUTS_ATTN_BITS_ATC_HW_INTERRUPT) {
3490 val = REG_RD(sc, ATC_REG_ATC_INT_STS_CLR);
3491 PMD_DRV_LOG(INFO, sc, "ERROR: ATC hw attention 0x%08x", val);
3492 if (val & ATC_ATC_INT_STS_REG_ADDRESS_ERROR)
3493 PMD_DRV_LOG(INFO, sc,
3494 "ERROR: ATC_ATC_INT_STS_REG_ADDRESS_ERROR");
3495 if (val & ATC_ATC_INT_STS_REG_ATC_TCPL_TO_NOT_PEND)
3496 PMD_DRV_LOG(INFO, sc,
3497 "ERROR: ATC_ATC_INT_STS_REG_ATC_TCPL_TO_NOT_PEND");
3498 if (val & ATC_ATC_INT_STS_REG_ATC_GPA_MULTIPLE_HITS)
3499 PMD_DRV_LOG(INFO, sc,
3500 "ERROR: ATC_ATC_INT_STS_REG_ATC_GPA_MULTIPLE_HITS");
3501 if (val & ATC_ATC_INT_STS_REG_ATC_RCPL_TO_EMPTY_CNT)
3502 PMD_DRV_LOG(INFO, sc,
3503 "ERROR: ATC_ATC_INT_STS_REG_ATC_RCPL_TO_EMPTY_CNT");
3504 if (val & ATC_ATC_INT_STS_REG_ATC_TCPL_ERROR)
3505 PMD_DRV_LOG(INFO, sc,
3506 "ERROR: ATC_ATC_INT_STS_REG_ATC_TCPL_ERROR");
3507 if (val & ATC_ATC_INT_STS_REG_ATC_IREQ_LESS_THAN_STU)
3508 PMD_DRV_LOG(INFO, sc,
3509 "ERROR: ATC_ATC_INT_STS_REG_ATC_IREQ_LESS_THAN_STU");
3512 if (attn & (AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR |
3513 AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR)) {
3514 PMD_DRV_LOG(INFO, sc,
3515 "ERROR: FATAL parity attention set4 0x%08x",
3517 (AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR
3519 AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR)));
3523 static void bnx2x_e1h_disable(struct bnx2x_softc *sc)
3525 int port = SC_PORT(sc);
3527 REG_WR(sc, NIG_REG_LLH0_FUNC_EN + port * 8, 0);
3530 static void bnx2x_e1h_enable(struct bnx2x_softc *sc)
3532 int port = SC_PORT(sc);
3534 REG_WR(sc, NIG_REG_LLH0_FUNC_EN + port * 8, 1);
3538 * called due to MCP event (on pmf):
3539 * reread new bandwidth configuration
3541 * notify others function about the change
3543 static void bnx2x_config_mf_bw(struct bnx2x_softc *sc)
3545 if (sc->link_vars.link_up) {
3546 bnx2x_cmng_fns_init(sc, TRUE, CMNG_FNS_MINMAX);
3547 bnx2x_link_sync_notify(sc);
3550 storm_memset_cmng(sc, &sc->cmng, SC_PORT(sc));
3553 static void bnx2x_set_mf_bw(struct bnx2x_softc *sc)
3555 bnx2x_config_mf_bw(sc);
3556 bnx2x_fw_command(sc, DRV_MSG_CODE_SET_MF_BW_ACK, 0);
3559 static void bnx2x_handle_eee_event(struct bnx2x_softc *sc)
3561 bnx2x_fw_command(sc, DRV_MSG_CODE_EEE_RESULTS_ACK, 0);
3564 #define DRV_INFO_ETH_STAT_NUM_MACS_REQUIRED 3
3566 static void bnx2x_drv_info_ether_stat(struct bnx2x_softc *sc)
3568 struct eth_stats_info *ether_stat = &sc->sp->drv_info_to_mcp.ether_stat;
3570 strncpy(ether_stat->version, BNX2X_DRIVER_VERSION,
3571 ETH_STAT_INFO_VERSION_LEN);
3573 sc->sp_objs[0].mac_obj.get_n_elements(sc, &sc->sp_objs[0].mac_obj,
3574 DRV_INFO_ETH_STAT_NUM_MACS_REQUIRED,
3575 ether_stat->mac_local + MAC_PAD,
3578 ether_stat->mtu_size = sc->mtu;
3580 ether_stat->feature_flags |= FEATURE_ETH_CHKSUM_OFFLOAD_MASK;
3581 ether_stat->promiscuous_mode = 0; // (flags & PROMISC) ? 1 : 0;
3583 ether_stat->txq_size = sc->tx_ring_size;
3584 ether_stat->rxq_size = sc->rx_ring_size;
3587 static void bnx2x_handle_drv_info_req(struct bnx2x_softc *sc)
3589 enum drv_info_opcode op_code;
3590 uint32_t drv_info_ctl = SHMEM2_RD(sc, drv_info_control);
3592 /* if drv_info version supported by MFW doesn't match - send NACK */
3593 if ((drv_info_ctl & DRV_INFO_CONTROL_VER_MASK) != DRV_INFO_CUR_VER) {
3594 bnx2x_fw_command(sc, DRV_MSG_CODE_DRV_INFO_NACK, 0);
3598 op_code = ((drv_info_ctl & DRV_INFO_CONTROL_OP_CODE_MASK) >>
3599 DRV_INFO_CONTROL_OP_CODE_SHIFT);
3601 memset(&sc->sp->drv_info_to_mcp, 0, sizeof(union drv_info_to_mcp));
3604 case ETH_STATS_OPCODE:
3605 bnx2x_drv_info_ether_stat(sc);
3607 case FCOE_STATS_OPCODE:
3608 case ISCSI_STATS_OPCODE:
3610 /* if op code isn't supported - send NACK */
3611 bnx2x_fw_command(sc, DRV_MSG_CODE_DRV_INFO_NACK, 0);
3616 * If we got drv_info attn from MFW then these fields are defined in
3619 SHMEM2_WR(sc, drv_info_host_addr_lo,
3620 U64_LO(BNX2X_SP_MAPPING(sc, drv_info_to_mcp)));
3621 SHMEM2_WR(sc, drv_info_host_addr_hi,
3622 U64_HI(BNX2X_SP_MAPPING(sc, drv_info_to_mcp)));
3624 bnx2x_fw_command(sc, DRV_MSG_CODE_DRV_INFO_ACK, 0);
3627 static void bnx2x_dcc_event(struct bnx2x_softc *sc, uint32_t dcc_event)
3629 if (dcc_event & DRV_STATUS_DCC_DISABLE_ENABLE_PF) {
3631 * This is the only place besides the function initialization
3632 * where the sc->flags can change so it is done without any
3636 mf_info.mf_config[SC_VN(sc)] & FUNC_MF_CFG_FUNC_DISABLED) {
3637 PMD_DRV_LOG(DEBUG, sc, "mf_cfg function disabled");
3638 sc->flags |= BNX2X_MF_FUNC_DIS;
3639 bnx2x_e1h_disable(sc);
3641 PMD_DRV_LOG(DEBUG, sc, "mf_cfg function enabled");
3642 sc->flags &= ~BNX2X_MF_FUNC_DIS;
3643 bnx2x_e1h_enable(sc);
3645 dcc_event &= ~DRV_STATUS_DCC_DISABLE_ENABLE_PF;
3648 if (dcc_event & DRV_STATUS_DCC_BANDWIDTH_ALLOCATION) {
3649 bnx2x_config_mf_bw(sc);
3650 dcc_event &= ~DRV_STATUS_DCC_BANDWIDTH_ALLOCATION;
3653 /* Report results to MCP */
3655 bnx2x_fw_command(sc, DRV_MSG_CODE_DCC_FAILURE, 0);
3657 bnx2x_fw_command(sc, DRV_MSG_CODE_DCC_OK, 0);
3660 static void bnx2x_pmf_update(struct bnx2x_softc *sc)
3662 int port = SC_PORT(sc);
3668 * We need the mb() to ensure the ordering between the writing to
3669 * sc->port.pmf here and reading it from the bnx2x_periodic_task().
3673 /* enable nig attention */
3674 val = (0xff0f | (1 << (SC_VN(sc) + 4)));
3675 if (sc->devinfo.int_block == INT_BLOCK_HC) {
3676 REG_WR(sc, HC_REG_TRAILING_EDGE_0 + port * 8, val);
3677 REG_WR(sc, HC_REG_LEADING_EDGE_0 + port * 8, val);
3678 } else if (!CHIP_IS_E1x(sc)) {
3679 REG_WR(sc, IGU_REG_TRAILING_EDGE_LATCH, val);
3680 REG_WR(sc, IGU_REG_LEADING_EDGE_LATCH, val);
3683 bnx2x_stats_handle(sc, STATS_EVENT_PMF);
3686 static int bnx2x_mc_assert(struct bnx2x_softc *sc)
3690 __rte_unused uint32_t row0, row1, row2, row3;
3694 REG_RD8(sc, BAR_XSTRORM_INTMEM + XSTORM_ASSERT_LIST_INDEX_OFFSET);
3696 PMD_DRV_LOG(ERR, sc, "XSTORM_ASSERT_LIST_INDEX 0x%x", last_idx);
3698 /* print the asserts */
3699 for (i = 0; i < STORM_ASSERT_ARRAY_SIZE; i++) {
3703 BAR_XSTRORM_INTMEM + XSTORM_ASSERT_LIST_OFFSET(i));
3706 BAR_XSTRORM_INTMEM + XSTORM_ASSERT_LIST_OFFSET(i) +
3710 BAR_XSTRORM_INTMEM + XSTORM_ASSERT_LIST_OFFSET(i) +
3714 BAR_XSTRORM_INTMEM + XSTORM_ASSERT_LIST_OFFSET(i) +
3717 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
3718 PMD_DRV_LOG(ERR, sc,
3719 "XSTORM_ASSERT_INDEX 0x%x = 0x%08x 0x%08x 0x%08x 0x%08x",
3720 i, row3, row2, row1, row0);
3729 REG_RD8(sc, BAR_TSTRORM_INTMEM + TSTORM_ASSERT_LIST_INDEX_OFFSET);
3731 PMD_DRV_LOG(ERR, sc, "TSTORM_ASSERT_LIST_INDEX 0x%x", last_idx);
3734 /* print the asserts */
3735 for (i = 0; i < STORM_ASSERT_ARRAY_SIZE; i++) {
3739 BAR_TSTRORM_INTMEM + TSTORM_ASSERT_LIST_OFFSET(i));
3742 BAR_TSTRORM_INTMEM + TSTORM_ASSERT_LIST_OFFSET(i) +
3746 BAR_TSTRORM_INTMEM + TSTORM_ASSERT_LIST_OFFSET(i) +
3750 BAR_TSTRORM_INTMEM + TSTORM_ASSERT_LIST_OFFSET(i) +
3753 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
3754 PMD_DRV_LOG(ERR, sc,
3755 "TSTORM_ASSERT_INDEX 0x%x = 0x%08x 0x%08x 0x%08x 0x%08x",
3756 i, row3, row2, row1, row0);
3765 REG_RD8(sc, BAR_CSTRORM_INTMEM + CSTORM_ASSERT_LIST_INDEX_OFFSET);
3767 PMD_DRV_LOG(ERR, sc, "CSTORM_ASSERT_LIST_INDEX 0x%x", last_idx);
3770 /* print the asserts */
3771 for (i = 0; i < STORM_ASSERT_ARRAY_SIZE; i++) {
3775 BAR_CSTRORM_INTMEM + CSTORM_ASSERT_LIST_OFFSET(i));
3778 BAR_CSTRORM_INTMEM + CSTORM_ASSERT_LIST_OFFSET(i) +
3782 BAR_CSTRORM_INTMEM + CSTORM_ASSERT_LIST_OFFSET(i) +
3786 BAR_CSTRORM_INTMEM + CSTORM_ASSERT_LIST_OFFSET(i) +
3789 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
3790 PMD_DRV_LOG(ERR, sc,
3791 "CSTORM_ASSERT_INDEX 0x%x = 0x%08x 0x%08x 0x%08x 0x%08x",
3792 i, row3, row2, row1, row0);
3801 REG_RD8(sc, BAR_USTRORM_INTMEM + USTORM_ASSERT_LIST_INDEX_OFFSET);
3803 PMD_DRV_LOG(ERR, sc, "USTORM_ASSERT_LIST_INDEX 0x%x", last_idx);
3806 /* print the asserts */
3807 for (i = 0; i < STORM_ASSERT_ARRAY_SIZE; i++) {
3811 BAR_USTRORM_INTMEM + USTORM_ASSERT_LIST_OFFSET(i));
3814 BAR_USTRORM_INTMEM + USTORM_ASSERT_LIST_OFFSET(i) +
3818 BAR_USTRORM_INTMEM + USTORM_ASSERT_LIST_OFFSET(i) +
3822 BAR_USTRORM_INTMEM + USTORM_ASSERT_LIST_OFFSET(i) +
3825 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
3826 PMD_DRV_LOG(ERR, sc,
3827 "USTORM_ASSERT_INDEX 0x%x = 0x%08x 0x%08x 0x%08x 0x%08x",
3828 i, row3, row2, row1, row0);
3838 static void bnx2x_attn_int_deasserted3(struct bnx2x_softc *sc, uint32_t attn)
3840 int func = SC_FUNC(sc);
3843 if (attn & EVEREST_GEN_ATTN_IN_USE_MASK) {
3845 if (attn & BNX2X_PMF_LINK_ASSERT(sc)) {
3847 REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_12 + func * 4, 0);
3848 bnx2x_read_mf_cfg(sc);
3849 sc->devinfo.mf_info.mf_config[SC_VN(sc)] =
3851 func_mf_config[SC_ABS_FUNC(sc)].config);
3853 SHMEM_RD(sc, func_mb[SC_FW_MB_IDX(sc)].drv_status);
3855 if (val & DRV_STATUS_DCC_EVENT_MASK)
3858 DRV_STATUS_DCC_EVENT_MASK));
3860 if (val & DRV_STATUS_SET_MF_BW)
3861 bnx2x_set_mf_bw(sc);
3863 if (val & DRV_STATUS_DRV_INFO_REQ)
3864 bnx2x_handle_drv_info_req(sc);
3866 if ((sc->port.pmf == 0) && (val & DRV_STATUS_PMF))
3867 bnx2x_pmf_update(sc);
3869 if (val & DRV_STATUS_EEE_NEGOTIATION_RESULTS)
3870 bnx2x_handle_eee_event(sc);
3872 if (sc->link_vars.periodic_flags &
3873 ELINK_PERIODIC_FLAGS_LINK_EVENT) {
3874 /* sync with link */
3875 bnx2x_acquire_phy_lock(sc);
3876 sc->link_vars.periodic_flags &=
3877 ~ELINK_PERIODIC_FLAGS_LINK_EVENT;
3878 bnx2x_release_phy_lock(sc);
3880 bnx2x_link_sync_notify(sc);
3882 bnx2x_link_report(sc);
3886 * Always call it here: bnx2x_link_report() will
3887 * prevent the link indication duplication.
3889 bnx2x_link_status_update(sc);
3891 } else if (attn & BNX2X_MC_ASSERT_BITS) {
3893 PMD_DRV_LOG(ERR, sc, "MC assert!");
3894 bnx2x_mc_assert(sc);
3895 REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_10, 0);
3896 REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_9, 0);
3897 REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_8, 0);
3898 REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_7, 0);
3899 rte_panic("MC assert!");
3901 } else if (attn & BNX2X_MCP_ASSERT) {
3903 PMD_DRV_LOG(ERR, sc, "MCP assert!");
3904 REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_11, 0);
3907 PMD_DRV_LOG(ERR, sc,
3908 "Unknown HW assert! (attn 0x%08x)", attn);
3912 if (attn & EVEREST_LATCHED_ATTN_IN_USE_MASK) {
3913 PMD_DRV_LOG(ERR, sc, "LATCHED attention 0x%08x (masked)", attn);
3914 if (attn & BNX2X_GRC_TIMEOUT) {
3915 val = REG_RD(sc, MISC_REG_GRC_TIMEOUT_ATTN);
3916 PMD_DRV_LOG(ERR, sc, "GRC time-out 0x%08x", val);
3918 if (attn & BNX2X_GRC_RSV) {
3919 val = REG_RD(sc, MISC_REG_GRC_RSV_ATTN);
3920 PMD_DRV_LOG(ERR, sc, "GRC reserved 0x%08x", val);
3922 REG_WR(sc, MISC_REG_AEU_CLR_LATCH_SIGNAL, 0x7ff);
3926 static void bnx2x_attn_int_deasserted2(struct bnx2x_softc *sc, uint32_t attn)
3928 int port = SC_PORT(sc);
3930 uint32_t val0, mask0, val1, mask1;
3933 if (attn & AEU_INPUTS_ATTN_BITS_CFC_HW_INTERRUPT) {
3934 val = REG_RD(sc, CFC_REG_CFC_INT_STS_CLR);
3935 PMD_DRV_LOG(ERR, sc, "CFC hw attention 0x%08x", val);
3936 /* CFC error attention */
3938 PMD_DRV_LOG(ERR, sc, "FATAL error from CFC");
3942 if (attn & AEU_INPUTS_ATTN_BITS_PXP_HW_INTERRUPT) {
3943 val = REG_RD(sc, PXP_REG_PXP_INT_STS_CLR_0);
3944 PMD_DRV_LOG(ERR, sc, "PXP hw attention-0 0x%08x", val);
3945 /* RQ_USDMDP_FIFO_OVERFLOW */
3946 if (val & 0x18000) {
3947 PMD_DRV_LOG(ERR, sc, "FATAL error from PXP");
3950 if (!CHIP_IS_E1x(sc)) {
3951 val = REG_RD(sc, PXP_REG_PXP_INT_STS_CLR_1);
3952 PMD_DRV_LOG(ERR, sc, "PXP hw attention-1 0x%08x", val);
3955 #define PXP2_EOP_ERROR_BIT PXP2_PXP2_INT_STS_CLR_0_REG_WR_PGLUE_EOP_ERROR
3956 #define AEU_PXP2_HW_INT_BIT AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_HW_INTERRUPT
3958 if (attn & AEU_PXP2_HW_INT_BIT) {
3959 /* CQ47854 workaround do not panic on
3960 * PXP2_PXP2_INT_STS_0_REG_WR_PGLUE_EOP_ERROR
3962 if (!CHIP_IS_E1x(sc)) {
3963 mask0 = REG_RD(sc, PXP2_REG_PXP2_INT_MASK_0);
3964 val1 = REG_RD(sc, PXP2_REG_PXP2_INT_STS_1);
3965 mask1 = REG_RD(sc, PXP2_REG_PXP2_INT_MASK_1);
3966 val0 = REG_RD(sc, PXP2_REG_PXP2_INT_STS_0);
3968 * If the olny PXP2_EOP_ERROR_BIT is set in
3969 * STS0 and STS1 - clear it
3971 * probably we lose additional attentions between
3972 * STS0 and STS_CLR0, in this case user will not
3973 * be notified about them
3975 if (val0 & mask0 & PXP2_EOP_ERROR_BIT &&
3977 val0 = REG_RD(sc, PXP2_REG_PXP2_INT_STS_CLR_0);
3979 /* print the register, since no one can restore it */
3980 PMD_DRV_LOG(ERR, sc,
3981 "PXP2_REG_PXP2_INT_STS_CLR_0 0x%08x", val0);
3984 * if PXP2_PXP2_INT_STS_0_REG_WR_PGLUE_EOP_ERROR
3987 if (val0 & PXP2_EOP_ERROR_BIT) {
3988 PMD_DRV_LOG(ERR, sc, "PXP2_WR_PGLUE_EOP_ERROR");
3991 * if only PXP2_PXP2_INT_STS_0_REG_WR_PGLUE_EOP_ERROR is
3992 * set then clear attention from PXP2 block without panic
3994 if (((val0 & mask0) == PXP2_EOP_ERROR_BIT) &&
3995 ((val1 & mask1) == 0))
3996 attn &= ~AEU_PXP2_HW_INT_BIT;
4001 if (attn & HW_INTERRUT_ASSERT_SET_2) {
4002 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_2 :
4003 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_2);
4005 val = REG_RD(sc, reg_offset);
4006 val &= ~(attn & HW_INTERRUT_ASSERT_SET_2);
4007 REG_WR(sc, reg_offset, val);
4009 PMD_DRV_LOG(ERR, sc,
4010 "FATAL HW block attention set2 0x%x",
4011 (uint32_t) (attn & HW_INTERRUT_ASSERT_SET_2));
4012 rte_panic("HW block attention set2");
4016 static void bnx2x_attn_int_deasserted1(struct bnx2x_softc *sc, uint32_t attn)
4018 int port = SC_PORT(sc);
4022 if (attn & AEU_INPUTS_ATTN_BITS_DOORBELLQ_HW_INTERRUPT) {
4023 val = REG_RD(sc, DORQ_REG_DORQ_INT_STS_CLR);
4024 PMD_DRV_LOG(ERR, sc, "DB hw attention 0x%08x", val);
4025 /* DORQ discard attention */
4027 PMD_DRV_LOG(ERR, sc, "FATAL error from DORQ");
4031 if (attn & HW_INTERRUT_ASSERT_SET_1) {
4032 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_1 :
4033 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_1);
4035 val = REG_RD(sc, reg_offset);
4036 val &= ~(attn & HW_INTERRUT_ASSERT_SET_1);
4037 REG_WR(sc, reg_offset, val);
4039 PMD_DRV_LOG(ERR, sc,
4040 "FATAL HW block attention set1 0x%08x",
4041 (uint32_t) (attn & HW_INTERRUT_ASSERT_SET_1));
4042 rte_panic("HW block attention set1");
4046 static void bnx2x_attn_int_deasserted0(struct bnx2x_softc *sc, uint32_t attn)
4048 int port = SC_PORT(sc);
4052 reg_offset = (port) ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 :
4053 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0;
4055 if (attn & AEU_INPUTS_ATTN_BITS_SPIO5) {
4056 val = REG_RD(sc, reg_offset);
4057 val &= ~AEU_INPUTS_ATTN_BITS_SPIO5;
4058 REG_WR(sc, reg_offset, val);
4060 PMD_DRV_LOG(WARNING, sc, "SPIO5 hw attention");
4062 /* Fan failure attention */
4063 elink_hw_reset_phy(&sc->link_params);
4064 bnx2x_fan_failure(sc);
4067 if ((attn & sc->link_vars.aeu_int_mask) && sc->port.pmf) {
4068 bnx2x_acquire_phy_lock(sc);
4069 elink_handle_module_detect_int(&sc->link_params);
4070 bnx2x_release_phy_lock(sc);
4073 if (attn & HW_INTERRUT_ASSERT_SET_0) {
4074 val = REG_RD(sc, reg_offset);
4075 val &= ~(attn & HW_INTERRUT_ASSERT_SET_0);
4076 REG_WR(sc, reg_offset, val);
4078 rte_panic("FATAL HW block attention set0 0x%lx",
4079 (attn & HW_INTERRUT_ASSERT_SET_0));
4083 static void bnx2x_attn_int_deasserted(struct bnx2x_softc *sc, uint32_t deasserted)
4085 struct attn_route attn;
4086 struct attn_route *group_mask;
4087 int port = SC_PORT(sc);
4092 uint8_t global = FALSE;
4095 * Need to take HW lock because MCP or other port might also
4096 * try to handle this event.
4098 bnx2x_acquire_alr(sc);
4100 if (bnx2x_chk_parity_attn(sc, &global, TRUE)) {
4101 sc->recovery_state = BNX2X_RECOVERY_INIT;
4103 /* disable HW interrupts */
4104 bnx2x_int_disable(sc);
4105 bnx2x_release_alr(sc);
4109 attn.sig[0] = REG_RD(sc, MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 + port * 4);
4110 attn.sig[1] = REG_RD(sc, MISC_REG_AEU_AFTER_INVERT_2_FUNC_0 + port * 4);
4111 attn.sig[2] = REG_RD(sc, MISC_REG_AEU_AFTER_INVERT_3_FUNC_0 + port * 4);
4112 attn.sig[3] = REG_RD(sc, MISC_REG_AEU_AFTER_INVERT_4_FUNC_0 + port * 4);
4113 if (!CHIP_IS_E1x(sc)) {
4115 REG_RD(sc, MISC_REG_AEU_AFTER_INVERT_5_FUNC_0 + port * 4);
4120 for (index = 0; index < MAX_DYNAMIC_ATTN_GRPS; index++) {
4121 if (deasserted & (1 << index)) {
4122 group_mask = &sc->attn_group[index];
4124 bnx2x_attn_int_deasserted4(sc,
4126 sig[4] & group_mask->sig[4]);
4127 bnx2x_attn_int_deasserted3(sc,
4129 sig[3] & group_mask->sig[3]);
4130 bnx2x_attn_int_deasserted1(sc,
4132 sig[1] & group_mask->sig[1]);
4133 bnx2x_attn_int_deasserted2(sc,
4135 sig[2] & group_mask->sig[2]);
4136 bnx2x_attn_int_deasserted0(sc,
4138 sig[0] & group_mask->sig[0]);
4142 bnx2x_release_alr(sc);
4144 if (sc->devinfo.int_block == INT_BLOCK_HC) {
4145 reg_addr = (HC_REG_COMMAND_REG + port * 32 +
4146 COMMAND_REG_ATTN_BITS_CLR);
4148 reg_addr = (BAR_IGU_INTMEM + IGU_CMD_ATTN_BIT_CLR_UPPER * 8);
4152 PMD_DRV_LOG(DEBUG, sc,
4153 "about to mask 0x%08x at %s addr 0x%08x", val,
4154 (sc->devinfo.int_block == INT_BLOCK_HC) ? "HC" : "IGU",
4156 REG_WR(sc, reg_addr, val);
4158 if (~sc->attn_state & deasserted) {
4159 PMD_DRV_LOG(ERR, sc, "IGU error");
4162 reg_addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 :
4163 MISC_REG_AEU_MASK_ATTN_FUNC_0;
4165 bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
4167 aeu_mask = REG_RD(sc, reg_addr);
4169 aeu_mask |= (deasserted & 0x3ff);
4171 REG_WR(sc, reg_addr, aeu_mask);
4172 bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
4174 sc->attn_state &= ~deasserted;
4177 static void bnx2x_attn_int(struct bnx2x_softc *sc)
4179 /* read local copy of bits */
4180 uint32_t attn_bits = le32toh(sc->def_sb->atten_status_block.attn_bits);
4182 le32toh(sc->def_sb->atten_status_block.attn_bits_ack);
4183 uint32_t attn_state = sc->attn_state;
4185 /* look for changed bits */
4186 uint32_t asserted = attn_bits & ~attn_ack & ~attn_state;
4187 uint32_t deasserted = ~attn_bits & attn_ack & attn_state;
4189 PMD_DRV_LOG(DEBUG, sc,
4190 "attn_bits 0x%08x attn_ack 0x%08x asserted 0x%08x deasserted 0x%08x",
4191 attn_bits, attn_ack, asserted, deasserted);
4193 if (~(attn_bits ^ attn_ack) & (attn_bits ^ attn_state)) {
4194 PMD_DRV_LOG(ERR, sc, "BAD attention state");
4197 /* handle bits that were raised */
4199 bnx2x_attn_int_asserted(sc, asserted);
4203 bnx2x_attn_int_deasserted(sc, deasserted);
4207 static uint16_t bnx2x_update_dsb_idx(struct bnx2x_softc *sc)
4209 struct host_sp_status_block *def_sb = sc->def_sb;
4212 mb(); /* status block is written to by the chip */
4214 if (sc->def_att_idx != def_sb->atten_status_block.attn_bits_index) {
4215 sc->def_att_idx = def_sb->atten_status_block.attn_bits_index;
4216 rc |= BNX2X_DEF_SB_ATT_IDX;
4219 if (sc->def_idx != def_sb->sp_sb.running_index) {
4220 sc->def_idx = def_sb->sp_sb.running_index;
4221 rc |= BNX2X_DEF_SB_IDX;
4229 static struct ecore_queue_sp_obj *bnx2x_cid_to_q_obj(struct bnx2x_softc *sc,
4232 return &sc->sp_objs[CID_TO_FP(cid, sc)].q_obj;
4235 static void bnx2x_handle_mcast_eqe(struct bnx2x_softc *sc)
4237 struct ecore_mcast_ramrod_params rparam;
4240 memset(&rparam, 0, sizeof(rparam));
4242 rparam.mcast_obj = &sc->mcast_obj;
4244 /* clear pending state for the last command */
4245 sc->mcast_obj.raw.clear_pending(&sc->mcast_obj.raw);
4247 /* if there are pending mcast commands - send them */
4248 if (sc->mcast_obj.check_pending(&sc->mcast_obj)) {
4249 rc = ecore_config_mcast(sc, &rparam, ECORE_MCAST_CMD_CONT);
4251 PMD_DRV_LOG(INFO, sc,
4252 "Failed to send pending mcast commands (%d)",
4259 bnx2x_handle_classification_eqe(struct bnx2x_softc *sc, union event_ring_elem *elem)
4261 unsigned long ramrod_flags = 0;
4263 uint32_t cid = elem->message.data.eth_event.echo & BNX2X_SWCID_MASK;
4264 struct ecore_vlan_mac_obj *vlan_mac_obj;
4266 /* always push next commands out, don't wait here */
4267 bnx2x_set_bit(RAMROD_CONT, &ramrod_flags);
4269 switch (le32toh(elem->message.data.eth_event.echo) >> BNX2X_SWCID_SHIFT) {
4270 case ECORE_FILTER_MAC_PENDING:
4271 PMD_DRV_LOG(DEBUG, sc, "Got SETUP_MAC completions");
4272 vlan_mac_obj = &sc->sp_objs[cid].mac_obj;
4275 case ECORE_FILTER_MCAST_PENDING:
4276 PMD_DRV_LOG(DEBUG, sc, "Got SETUP_MCAST completions");
4277 bnx2x_handle_mcast_eqe(sc);
4281 PMD_DRV_LOG(NOTICE, sc, "Unsupported classification command: %d",
4282 elem->message.data.eth_event.echo);
4286 rc = vlan_mac_obj->complete(sc, vlan_mac_obj, elem, &ramrod_flags);
4289 PMD_DRV_LOG(NOTICE, sc,
4290 "Failed to schedule new commands (%d)", rc);
4291 } else if (rc > 0) {
4292 PMD_DRV_LOG(DEBUG, sc, "Scheduled next pending commands...");
4296 static void bnx2x_handle_rx_mode_eqe(struct bnx2x_softc *sc)
4298 bnx2x_clear_bit(ECORE_FILTER_RX_MODE_PENDING, &sc->sp_state);
4300 /* send rx_mode command again if was requested */
4301 if (bnx2x_test_and_clear_bit(ECORE_FILTER_RX_MODE_SCHED, &sc->sp_state)) {
4302 bnx2x_set_storm_rx_mode(sc);
4306 static void bnx2x_update_eq_prod(struct bnx2x_softc *sc, uint16_t prod)
4308 storm_memset_eq_prod(sc, prod, SC_FUNC(sc));
4309 wmb(); /* keep prod updates ordered */
4312 static void bnx2x_eq_int(struct bnx2x_softc *sc)
4314 uint16_t hw_cons, sw_cons, sw_prod;
4315 union event_ring_elem *elem;
4320 struct ecore_queue_sp_obj *q_obj;
4321 struct ecore_func_sp_obj *f_obj = &sc->func_obj;
4322 struct ecore_raw_obj *rss_raw = &sc->rss_conf_obj.raw;
4324 hw_cons = le16toh(*sc->eq_cons_sb);
4327 * The hw_cons range is 1-255, 257 - the sw_cons range is 0-254, 256.
4328 * when we get to the next-page we need to adjust so the loop
4329 * condition below will be met. The next element is the size of a
4330 * regular element and hence incrementing by 1
4332 if ((hw_cons & EQ_DESC_MAX_PAGE) == EQ_DESC_MAX_PAGE) {
4337 * This function may never run in parallel with itself for a
4338 * specific sc and no need for a read memory barrier here.
4340 sw_cons = sc->eq_cons;
4341 sw_prod = sc->eq_prod;
4345 sw_prod = NEXT_EQ_IDX(sw_prod), sw_cons = NEXT_EQ_IDX(sw_cons)) {
4347 elem = &sc->eq[EQ_DESC(sw_cons)];
4349 /* elem CID originates from FW, actually LE */
4350 cid = SW_CID(elem->message.data.cfc_del_event.cid);
4351 opcode = elem->message.opcode;
4353 /* handle eq element */
4355 case EVENT_RING_OPCODE_STAT_QUERY:
4356 PMD_DEBUG_PERIODIC_LOG(DEBUG, sc, "got statistics completion event %d",
4358 /* nothing to do with stats comp */
4361 case EVENT_RING_OPCODE_CFC_DEL:
4362 /* handle according to cid range */
4363 /* we may want to verify here that the sc state is HALTING */
4364 PMD_DRV_LOG(DEBUG, sc, "got delete ramrod for MULTI[%d]",
4366 q_obj = bnx2x_cid_to_q_obj(sc, cid);
4367 if (q_obj->complete_cmd(sc, q_obj, ECORE_Q_CMD_CFC_DEL)) {
4372 case EVENT_RING_OPCODE_STOP_TRAFFIC:
4373 PMD_DRV_LOG(DEBUG, sc, "got STOP TRAFFIC");
4374 if (f_obj->complete_cmd(sc, f_obj, ECORE_F_CMD_TX_STOP)) {
4379 case EVENT_RING_OPCODE_START_TRAFFIC:
4380 PMD_DRV_LOG(DEBUG, sc, "got START TRAFFIC");
4381 if (f_obj->complete_cmd
4382 (sc, f_obj, ECORE_F_CMD_TX_START)) {
4387 case EVENT_RING_OPCODE_FUNCTION_UPDATE:
4388 echo = elem->message.data.function_update_event.echo;
4389 if (echo == SWITCH_UPDATE) {
4390 PMD_DRV_LOG(DEBUG, sc,
4391 "got FUNC_SWITCH_UPDATE ramrod");
4392 if (f_obj->complete_cmd(sc, f_obj,
4393 ECORE_F_CMD_SWITCH_UPDATE))
4398 PMD_DRV_LOG(DEBUG, sc,
4399 "AFEX: ramrod completed FUNCTION_UPDATE");
4400 f_obj->complete_cmd(sc, f_obj,
4401 ECORE_F_CMD_AFEX_UPDATE);
4405 case EVENT_RING_OPCODE_FORWARD_SETUP:
4406 q_obj = &bnx2x_fwd_sp_obj(sc, q_obj);
4407 if (q_obj->complete_cmd(sc, q_obj,
4408 ECORE_Q_CMD_SETUP_TX_ONLY)) {
4413 case EVENT_RING_OPCODE_FUNCTION_START:
4414 PMD_DRV_LOG(DEBUG, sc, "got FUNC_START ramrod");
4415 if (f_obj->complete_cmd(sc, f_obj, ECORE_F_CMD_START)) {
4420 case EVENT_RING_OPCODE_FUNCTION_STOP:
4421 PMD_DRV_LOG(DEBUG, sc, "got FUNC_STOP ramrod");
4422 if (f_obj->complete_cmd(sc, f_obj, ECORE_F_CMD_STOP)) {
4428 switch (opcode | sc->state) {
4429 case (EVENT_RING_OPCODE_RSS_UPDATE_RULES | BNX2X_STATE_OPEN):
4430 case (EVENT_RING_OPCODE_RSS_UPDATE_RULES | BNX2X_STATE_OPENING_WAITING_PORT):
4432 elem->message.data.eth_event.echo & BNX2X_SWCID_MASK;
4433 PMD_DRV_LOG(DEBUG, sc, "got RSS_UPDATE ramrod. CID %d",
4435 rss_raw->clear_pending(rss_raw);
4438 case (EVENT_RING_OPCODE_SET_MAC | BNX2X_STATE_OPEN):
4439 case (EVENT_RING_OPCODE_SET_MAC | BNX2X_STATE_DIAG):
4440 case (EVENT_RING_OPCODE_SET_MAC | BNX2X_STATE_CLOSING_WAITING_HALT):
4441 case (EVENT_RING_OPCODE_CLASSIFICATION_RULES | BNX2X_STATE_OPEN):
4442 case (EVENT_RING_OPCODE_CLASSIFICATION_RULES | BNX2X_STATE_DIAG):
4443 case (EVENT_RING_OPCODE_CLASSIFICATION_RULES | BNX2X_STATE_CLOSING_WAITING_HALT):
4444 PMD_DRV_LOG(DEBUG, sc,
4445 "got (un)set mac ramrod");
4446 bnx2x_handle_classification_eqe(sc, elem);
4449 case (EVENT_RING_OPCODE_MULTICAST_RULES | BNX2X_STATE_OPEN):
4450 case (EVENT_RING_OPCODE_MULTICAST_RULES | BNX2X_STATE_DIAG):
4451 case (EVENT_RING_OPCODE_MULTICAST_RULES | BNX2X_STATE_CLOSING_WAITING_HALT):
4452 PMD_DRV_LOG(DEBUG, sc,
4453 "got mcast ramrod");
4454 bnx2x_handle_mcast_eqe(sc);
4457 case (EVENT_RING_OPCODE_FILTERS_RULES | BNX2X_STATE_OPEN):
4458 case (EVENT_RING_OPCODE_FILTERS_RULES | BNX2X_STATE_DIAG):
4459 case (EVENT_RING_OPCODE_FILTERS_RULES | BNX2X_STATE_CLOSING_WAITING_HALT):
4460 PMD_DRV_LOG(DEBUG, sc,
4461 "got rx_mode ramrod");
4462 bnx2x_handle_rx_mode_eqe(sc);
4466 /* unknown event log error and continue */
4467 PMD_DRV_LOG(INFO, sc, "Unknown EQ event %d, sc->state 0x%x",
4468 elem->message.opcode, sc->state);
4476 atomic_add_acq_long(&sc->eq_spq_left, spqe_cnt);
4478 sc->eq_cons = sw_cons;
4479 sc->eq_prod = sw_prod;
4481 /* make sure that above mem writes were issued towards the memory */
4484 /* update producer */
4485 bnx2x_update_eq_prod(sc, sc->eq_prod);
4488 static int bnx2x_handle_sp_tq(struct bnx2x_softc *sc)
4493 PMD_DRV_LOG(DEBUG, sc, "---> SP TASK <---");
4495 /* what work needs to be performed? */
4496 status = bnx2x_update_dsb_idx(sc);
4498 PMD_DRV_LOG(DEBUG, sc, "dsb status 0x%04x", status);
4501 if (status & BNX2X_DEF_SB_ATT_IDX) {
4502 PMD_DRV_LOG(DEBUG, sc, "---> ATTN INTR <---");
4504 status &= ~BNX2X_DEF_SB_ATT_IDX;
4508 /* SP events: STAT_QUERY and others */
4509 if (status & BNX2X_DEF_SB_IDX) {
4510 /* handle EQ completions */
4511 PMD_DRV_LOG(DEBUG, sc, "---> EQ INTR <---");
4513 bnx2x_ack_sb(sc, sc->igu_dsb_id, USTORM_ID,
4514 le16toh(sc->def_idx), IGU_INT_NOP, 1);
4515 status &= ~BNX2X_DEF_SB_IDX;
4518 /* if status is non zero then something went wrong */
4519 if (unlikely(status)) {
4520 PMD_DRV_LOG(INFO, sc,
4521 "Got an unknown SP interrupt! (0x%04x)", status);
4524 /* ack status block only if something was actually handled */
4525 bnx2x_ack_sb(sc, sc->igu_dsb_id, ATTENTION_ID,
4526 le16toh(sc->def_att_idx), IGU_INT_ENABLE, 1);
4531 static void bnx2x_handle_fp_tq(struct bnx2x_fastpath *fp, int scan_fp)
4533 struct bnx2x_softc *sc = fp->sc;
4534 uint8_t more_rx = FALSE;
4536 PMD_DEBUG_PERIODIC_LOG(DEBUG, sc,
4537 "---> FP TASK QUEUE (%d) <--", fp->index);
4539 /* update the fastpath index */
4540 bnx2x_update_fp_sb_idx(fp);
4543 if (bnx2x_has_rx_work(fp)) {
4544 more_rx = bnx2x_rxeof(sc, fp);
4548 /* still more work to do */
4549 bnx2x_handle_fp_tq(fp, scan_fp);
4554 bnx2x_ack_sb(sc, fp->igu_sb_id, USTORM_ID,
4555 le16toh(fp->fp_hc_idx), IGU_INT_ENABLE, 1);
4559 * Legacy interrupt entry point.
4561 * Verifies that the controller generated the interrupt and
4562 * then calls a separate routine to handle the various
4563 * interrupt causes: link, RX, and TX.
4565 int bnx2x_intr_legacy(struct bnx2x_softc *sc, int scan_fp)
4567 struct bnx2x_fastpath *fp;
4568 uint32_t status, mask;
4572 * 0 for ustorm, 1 for cstorm
4573 * the bits returned from ack_int() are 0-15
4574 * bit 0 = attention status block
4575 * bit 1 = fast path status block
4576 * a mask of 0x2 or more = tx/rx event
4577 * a mask of 1 = slow path event
4580 status = bnx2x_ack_int(sc);
4582 /* the interrupt is not for us */
4583 if (unlikely(status == 0)) {
4587 PMD_DEBUG_PERIODIC_LOG(DEBUG, sc, "Interrupt status 0x%04x", status);
4588 //bnx2x_dump_status_block(sc);
4590 FOR_EACH_ETH_QUEUE(sc, i) {
4592 mask = (0x2 << (fp->index + CNIC_SUPPORT(sc)));
4593 if (status & mask) {
4594 /* acknowledge and disable further fastpath interrupts */
4595 bnx2x_ack_sb(sc, fp->igu_sb_id, USTORM_ID,
4596 0, IGU_INT_DISABLE, 0);
4597 bnx2x_handle_fp_tq(fp, scan_fp);
4602 if (unlikely(status & 0x1)) {
4603 /* acknowledge and disable further slowpath interrupts */
4604 bnx2x_ack_sb(sc, sc->igu_dsb_id, USTORM_ID,
4605 0, IGU_INT_DISABLE, 0);
4606 rc = bnx2x_handle_sp_tq(sc);
4610 if (unlikely(status)) {
4611 PMD_DRV_LOG(WARNING, sc,
4612 "Unexpected fastpath status (0x%08x)!", status);
4618 static int bnx2x_init_hw_common_chip(struct bnx2x_softc *sc);
4619 static int bnx2x_init_hw_common(struct bnx2x_softc *sc);
4620 static int bnx2x_init_hw_port(struct bnx2x_softc *sc);
4621 static int bnx2x_init_hw_func(struct bnx2x_softc *sc);
4622 static void bnx2x_reset_common(struct bnx2x_softc *sc);
4623 static void bnx2x_reset_port(struct bnx2x_softc *sc);
4624 static void bnx2x_reset_func(struct bnx2x_softc *sc);
4625 static int bnx2x_init_firmware(struct bnx2x_softc *sc);
4626 static void bnx2x_release_firmware(struct bnx2x_softc *sc);
4629 ecore_func_sp_drv_ops bnx2x_func_sp_drv = {
4630 .init_hw_cmn_chip = bnx2x_init_hw_common_chip,
4631 .init_hw_cmn = bnx2x_init_hw_common,
4632 .init_hw_port = bnx2x_init_hw_port,
4633 .init_hw_func = bnx2x_init_hw_func,
4635 .reset_hw_cmn = bnx2x_reset_common,
4636 .reset_hw_port = bnx2x_reset_port,
4637 .reset_hw_func = bnx2x_reset_func,
4639 .init_fw = bnx2x_init_firmware,
4640 .release_fw = bnx2x_release_firmware,
4643 static void bnx2x_init_func_obj(struct bnx2x_softc *sc)
4647 PMD_INIT_FUNC_TRACE(sc);
4649 ecore_init_func_obj(sc,
4651 BNX2X_SP(sc, func_rdata),
4652 (phys_addr_t)BNX2X_SP_MAPPING(sc, func_rdata),
4653 BNX2X_SP(sc, func_afex_rdata),
4654 (phys_addr_t)BNX2X_SP_MAPPING(sc, func_afex_rdata),
4655 &bnx2x_func_sp_drv);
4658 static int bnx2x_init_hw(struct bnx2x_softc *sc, uint32_t load_code)
4660 struct ecore_func_state_params func_params = { NULL };
4663 PMD_INIT_FUNC_TRACE(sc);
4665 /* prepare the parameters for function state transitions */
4666 bnx2x_set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags);
4668 func_params.f_obj = &sc->func_obj;
4669 func_params.cmd = ECORE_F_CMD_HW_INIT;
4671 func_params.params.hw_init.load_phase = load_code;
4674 * Via a plethora of function pointers, we will eventually reach
4675 * bnx2x_init_hw_common(), bnx2x_init_hw_port(), or bnx2x_init_hw_func().
4677 rc = ecore_func_state_change(sc, &func_params);
4683 bnx2x_fill(struct bnx2x_softc *sc, uint32_t addr, int fill, uint32_t len)
4687 if (!(len % 4) && !(addr % 4)) {
4688 for (i = 0; i < len; i += 4) {
4689 REG_WR(sc, (addr + i), fill);
4692 for (i = 0; i < len; i++) {
4693 REG_WR8(sc, (addr + i), fill);
4698 /* writes FP SP data to FW - data_size in dwords */
4700 bnx2x_wr_fp_sb_data(struct bnx2x_softc *sc, int fw_sb_id, uint32_t * sb_data_p,
4705 for (index = 0; index < data_size; index++) {
4707 (BAR_CSTRORM_INTMEM +
4708 CSTORM_STATUS_BLOCK_DATA_OFFSET(fw_sb_id) +
4709 (sizeof(uint32_t) * index)), *(sb_data_p + index));
4713 static void bnx2x_zero_fp_sb(struct bnx2x_softc *sc, int fw_sb_id)
4715 struct hc_status_block_data_e2 sb_data_e2;
4716 struct hc_status_block_data_e1x sb_data_e1x;
4717 uint32_t *sb_data_p;
4718 uint32_t data_size = 0;
4720 if (!CHIP_IS_E1x(sc)) {
4721 memset(&sb_data_e2, 0, sizeof(struct hc_status_block_data_e2));
4722 sb_data_e2.common.state = SB_DISABLED;
4723 sb_data_e2.common.p_func.vf_valid = FALSE;
4724 sb_data_p = (uint32_t *) & sb_data_e2;
4725 data_size = (sizeof(struct hc_status_block_data_e2) /
4728 memset(&sb_data_e1x, 0,
4729 sizeof(struct hc_status_block_data_e1x));
4730 sb_data_e1x.common.state = SB_DISABLED;
4731 sb_data_e1x.common.p_func.vf_valid = FALSE;
4732 sb_data_p = (uint32_t *) & sb_data_e1x;
4733 data_size = (sizeof(struct hc_status_block_data_e1x) /
4737 bnx2x_wr_fp_sb_data(sc, fw_sb_id, sb_data_p, data_size);
4740 (BAR_CSTRORM_INTMEM + CSTORM_STATUS_BLOCK_OFFSET(fw_sb_id)), 0,
4741 CSTORM_STATUS_BLOCK_SIZE);
4742 bnx2x_fill(sc, (BAR_CSTRORM_INTMEM + CSTORM_SYNC_BLOCK_OFFSET(fw_sb_id)),
4743 0, CSTORM_SYNC_BLOCK_SIZE);
4747 bnx2x_wr_sp_sb_data(struct bnx2x_softc *sc,
4748 struct hc_sp_status_block_data *sp_sb_data)
4753 i < (sizeof(struct hc_sp_status_block_data) / sizeof(uint32_t));
4756 (BAR_CSTRORM_INTMEM +
4757 CSTORM_SP_STATUS_BLOCK_DATA_OFFSET(SC_FUNC(sc)) +
4758 (i * sizeof(uint32_t))),
4759 *((uint32_t *) sp_sb_data + i));
4763 static void bnx2x_zero_sp_sb(struct bnx2x_softc *sc)
4765 struct hc_sp_status_block_data sp_sb_data;
4767 memset(&sp_sb_data, 0, sizeof(struct hc_sp_status_block_data));
4769 sp_sb_data.state = SB_DISABLED;
4770 sp_sb_data.p_func.vf_valid = FALSE;
4772 bnx2x_wr_sp_sb_data(sc, &sp_sb_data);
4775 (BAR_CSTRORM_INTMEM +
4776 CSTORM_SP_STATUS_BLOCK_OFFSET(SC_FUNC(sc))),
4777 0, CSTORM_SP_STATUS_BLOCK_SIZE);
4779 (BAR_CSTRORM_INTMEM +
4780 CSTORM_SP_SYNC_BLOCK_OFFSET(SC_FUNC(sc))),
4781 0, CSTORM_SP_SYNC_BLOCK_SIZE);
4785 bnx2x_setup_ndsb_state_machine(struct hc_status_block_sm *hc_sm, int igu_sb_id,
4788 hc_sm->igu_sb_id = igu_sb_id;
4789 hc_sm->igu_seg_id = igu_seg_id;
4790 hc_sm->timer_value = 0xFF;
4791 hc_sm->time_to_expire = 0xFFFFFFFF;
4794 static void bnx2x_map_sb_state_machines(struct hc_index_data *index_data)
4796 /* zero out state machine indices */
4799 index_data[HC_INDEX_ETH_RX_CQ_CONS].flags &= ~HC_INDEX_DATA_SM_ID;
4802 index_data[HC_INDEX_OOO_TX_CQ_CONS].flags &= ~HC_INDEX_DATA_SM_ID;
4803 index_data[HC_INDEX_ETH_TX_CQ_CONS_COS0].flags &= ~HC_INDEX_DATA_SM_ID;
4804 index_data[HC_INDEX_ETH_TX_CQ_CONS_COS1].flags &= ~HC_INDEX_DATA_SM_ID;
4805 index_data[HC_INDEX_ETH_TX_CQ_CONS_COS2].flags &= ~HC_INDEX_DATA_SM_ID;
4810 index_data[HC_INDEX_ETH_RX_CQ_CONS].flags |=
4811 (SM_RX_ID << HC_INDEX_DATA_SM_ID_SHIFT);
4814 index_data[HC_INDEX_OOO_TX_CQ_CONS].flags |=
4815 (SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT);
4816 index_data[HC_INDEX_ETH_TX_CQ_CONS_COS0].flags |=
4817 (SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT);
4818 index_data[HC_INDEX_ETH_TX_CQ_CONS_COS1].flags |=
4819 (SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT);
4820 index_data[HC_INDEX_ETH_TX_CQ_CONS_COS2].flags |=
4821 (SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT);
4825 bnx2x_init_sb(struct bnx2x_softc *sc, phys_addr_t busaddr, int vfid,
4826 uint8_t vf_valid, int fw_sb_id, int igu_sb_id)
4828 struct hc_status_block_data_e2 sb_data_e2;
4829 struct hc_status_block_data_e1x sb_data_e1x;
4830 struct hc_status_block_sm *hc_sm_p;
4831 uint32_t *sb_data_p;
4835 if (CHIP_INT_MODE_IS_BC(sc)) {
4836 igu_seg_id = HC_SEG_ACCESS_NORM;
4838 igu_seg_id = IGU_SEG_ACCESS_NORM;
4841 bnx2x_zero_fp_sb(sc, fw_sb_id);
4843 if (!CHIP_IS_E1x(sc)) {
4844 memset(&sb_data_e2, 0, sizeof(struct hc_status_block_data_e2));
4845 sb_data_e2.common.state = SB_ENABLED;
4846 sb_data_e2.common.p_func.pf_id = SC_FUNC(sc);
4847 sb_data_e2.common.p_func.vf_id = vfid;
4848 sb_data_e2.common.p_func.vf_valid = vf_valid;
4849 sb_data_e2.common.p_func.vnic_id = SC_VN(sc);
4850 sb_data_e2.common.same_igu_sb_1b = TRUE;
4851 sb_data_e2.common.host_sb_addr.hi = U64_HI(busaddr);
4852 sb_data_e2.common.host_sb_addr.lo = U64_LO(busaddr);
4853 hc_sm_p = sb_data_e2.common.state_machine;
4854 sb_data_p = (uint32_t *) & sb_data_e2;
4855 data_size = (sizeof(struct hc_status_block_data_e2) /
4857 bnx2x_map_sb_state_machines(sb_data_e2.index_data);
4859 memset(&sb_data_e1x, 0,
4860 sizeof(struct hc_status_block_data_e1x));
4861 sb_data_e1x.common.state = SB_ENABLED;
4862 sb_data_e1x.common.p_func.pf_id = SC_FUNC(sc);
4863 sb_data_e1x.common.p_func.vf_id = 0xff;
4864 sb_data_e1x.common.p_func.vf_valid = FALSE;
4865 sb_data_e1x.common.p_func.vnic_id = SC_VN(sc);
4866 sb_data_e1x.common.same_igu_sb_1b = TRUE;
4867 sb_data_e1x.common.host_sb_addr.hi = U64_HI(busaddr);
4868 sb_data_e1x.common.host_sb_addr.lo = U64_LO(busaddr);
4869 hc_sm_p = sb_data_e1x.common.state_machine;
4870 sb_data_p = (uint32_t *) & sb_data_e1x;
4871 data_size = (sizeof(struct hc_status_block_data_e1x) /
4873 bnx2x_map_sb_state_machines(sb_data_e1x.index_data);
4876 bnx2x_setup_ndsb_state_machine(&hc_sm_p[SM_RX_ID], igu_sb_id, igu_seg_id);
4877 bnx2x_setup_ndsb_state_machine(&hc_sm_p[SM_TX_ID], igu_sb_id, igu_seg_id);
4879 /* write indices to HW - PCI guarantees endianity of regpairs */
4880 bnx2x_wr_fp_sb_data(sc, fw_sb_id, sb_data_p, data_size);
4883 static uint8_t bnx2x_fp_qzone_id(struct bnx2x_fastpath *fp)
4885 if (CHIP_IS_E1x(fp->sc)) {
4886 return fp->cl_id + SC_PORT(fp->sc) * ETH_MAX_RX_CLIENTS_E1H;
4893 bnx2x_rx_ustorm_prods_offset(struct bnx2x_softc *sc, struct bnx2x_fastpath *fp)
4895 uint32_t offset = BAR_USTRORM_INTMEM;
4898 return PXP_VF_ADDR_USDM_QUEUES_START +
4899 (sc->acquire_resp.resc.hw_qid[fp->index] *
4900 sizeof(struct ustorm_queue_zone_data));
4901 } else if (!CHIP_IS_E1x(sc)) {
4902 offset += USTORM_RX_PRODS_E2_OFFSET(fp->cl_qzone_id);
4904 offset += USTORM_RX_PRODS_E1X_OFFSET(SC_PORT(sc), fp->cl_id);
4910 static void bnx2x_init_eth_fp(struct bnx2x_softc *sc, int idx)
4912 struct bnx2x_fastpath *fp = &sc->fp[idx];
4913 uint32_t cids[ECORE_MULTI_TX_COS] = { 0 };
4914 unsigned long q_type = 0;
4920 fp->igu_sb_id = (sc->igu_base_sb + idx + CNIC_SUPPORT(sc));
4921 fp->fw_sb_id = (sc->base_fw_ndsb + idx + CNIC_SUPPORT(sc));
4923 if (CHIP_IS_E1x(sc))
4924 fp->cl_id = SC_L_ID(sc) + idx;
4926 /* want client ID same as IGU SB ID for non-E1 */
4927 fp->cl_id = fp->igu_sb_id;
4928 fp->cl_qzone_id = bnx2x_fp_qzone_id(fp);
4930 /* setup sb indices */
4931 if (!CHIP_IS_E1x(sc)) {
4932 fp->sb_index_values = fp->status_block.e2_sb->sb.index_values;
4933 fp->sb_running_index = fp->status_block.e2_sb->sb.running_index;
4935 fp->sb_index_values = fp->status_block.e1x_sb->sb.index_values;
4936 fp->sb_running_index =
4937 fp->status_block.e1x_sb->sb.running_index;
4941 fp->ustorm_rx_prods_offset = bnx2x_rx_ustorm_prods_offset(sc, fp);
4943 fp->rx_cq_cons_sb = &fp->sb_index_values[HC_INDEX_ETH_RX_CQ_CONS];
4945 for (cos = 0; cos < sc->max_cos; cos++) {
4948 fp->tx_cons_sb = &fp->sb_index_values[HC_INDEX_ETH_TX_CQ_CONS_COS0];
4950 /* nothing more for a VF to do */
4955 bnx2x_init_sb(sc, fp->sb_dma.paddr, BNX2X_VF_ID_INVALID, FALSE,
4956 fp->fw_sb_id, fp->igu_sb_id);
4958 bnx2x_update_fp_sb_idx(fp);
4960 /* Configure Queue State object */
4961 bnx2x_set_bit(ECORE_Q_TYPE_HAS_RX, &q_type);
4962 bnx2x_set_bit(ECORE_Q_TYPE_HAS_TX, &q_type);
4964 ecore_init_queue_obj(sc,
4965 &sc->sp_objs[idx].q_obj,
4970 BNX2X_SP(sc, q_rdata),
4971 (phys_addr_t)BNX2X_SP_MAPPING(sc, q_rdata),
4974 /* configure classification DBs */
4975 ecore_init_mac_obj(sc,
4976 &sc->sp_objs[idx].mac_obj,
4980 BNX2X_SP(sc, mac_rdata),
4981 (phys_addr_t)BNX2X_SP_MAPPING(sc, mac_rdata),
4982 ECORE_FILTER_MAC_PENDING, &sc->sp_state,
4983 ECORE_OBJ_TYPE_RX_TX, &sc->macs_pool);
4987 bnx2x_update_rx_prod(struct bnx2x_softc *sc, struct bnx2x_fastpath *fp,
4988 uint16_t rx_bd_prod, uint16_t rx_cq_prod)
4990 union ustorm_eth_rx_producers rx_prods;
4993 /* update producers */
4994 rx_prods.prod.bd_prod = rx_bd_prod;
4995 rx_prods.prod.cqe_prod = rx_cq_prod;
4996 rx_prods.prod.reserved = 0;
4999 * Make sure that the BD and SGE data is updated before updating the
5000 * producers since FW might read the BD/SGE right after the producer
5002 * This is only applicable for weak-ordered memory model archs such
5003 * as IA-64. The following barrier is also mandatory since FW will
5004 * assumes BDs must have buffers.
5008 for (i = 0; i < (sizeof(rx_prods) / 4); i++) {
5010 (fp->ustorm_rx_prods_offset + (i * 4)),
5011 rx_prods.raw_data[i]);
5014 wmb(); /* keep prod updates ordered */
5017 static void bnx2x_init_rx_rings(struct bnx2x_softc *sc)
5019 struct bnx2x_fastpath *fp;
5021 struct bnx2x_rx_queue *rxq;
5023 for (i = 0; i < sc->num_queues; i++) {
5025 rxq = sc->rx_queues[fp->index];
5027 PMD_RX_LOG(ERR, "RX queue is NULL");
5031 rxq->rx_bd_head = 0;
5032 rxq->rx_bd_tail = rxq->nb_rx_desc;
5033 rxq->rx_cq_head = 0;
5034 rxq->rx_cq_tail = TOTAL_RCQ_ENTRIES(rxq);
5035 *fp->rx_cq_cons_sb = 0;
5038 * Activate the BD ring...
5039 * Warning, this will generate an interrupt (to the TSTORM)
5040 * so this can only be done after the chip is initialized
5042 bnx2x_update_rx_prod(sc, fp, rxq->rx_bd_tail, rxq->rx_cq_tail);
5050 static void bnx2x_init_tx_ring_one(struct bnx2x_fastpath *fp)
5052 struct bnx2x_tx_queue *txq = fp->sc->tx_queues[fp->index];
5054 fp->tx_db.data.header.header = 1 << DOORBELL_HDR_DB_TYPE_SHIFT;
5055 fp->tx_db.data.zero_fill1 = 0;
5056 fp->tx_db.data.prod = 0;
5059 PMD_TX_LOG(ERR, "ERROR: TX queue is NULL");
5063 txq->tx_pkt_tail = 0;
5064 txq->tx_pkt_head = 0;
5065 txq->tx_bd_tail = 0;
5066 txq->tx_bd_head = 0;
5069 static void bnx2x_init_tx_rings(struct bnx2x_softc *sc)
5073 for (i = 0; i < sc->num_queues; i++) {
5074 bnx2x_init_tx_ring_one(&sc->fp[i]);
5078 static void bnx2x_init_def_sb(struct bnx2x_softc *sc)
5080 struct host_sp_status_block *def_sb = sc->def_sb;
5081 phys_addr_t mapping = sc->def_sb_dma.paddr;
5082 int igu_sp_sb_index;
5084 int port = SC_PORT(sc);
5085 int func = SC_FUNC(sc);
5086 int reg_offset, reg_offset_en5;
5089 struct hc_sp_status_block_data sp_sb_data;
5091 memset(&sp_sb_data, 0, sizeof(struct hc_sp_status_block_data));
5093 if (CHIP_INT_MODE_IS_BC(sc)) {
5094 igu_sp_sb_index = DEF_SB_IGU_ID;
5095 igu_seg_id = HC_SEG_ACCESS_DEF;
5097 igu_sp_sb_index = sc->igu_dsb_id;
5098 igu_seg_id = IGU_SEG_ACCESS_DEF;
5102 section = ((uint64_t) mapping +
5103 offsetof(struct host_sp_status_block, atten_status_block));
5104 def_sb->atten_status_block.status_block_id = igu_sp_sb_index;
5107 reg_offset = (port) ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 :
5108 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0;
5110 reg_offset_en5 = (port) ? MISC_REG_AEU_ENABLE5_FUNC_1_OUT_0 :
5111 MISC_REG_AEU_ENABLE5_FUNC_0_OUT_0;
5113 for (index = 0; index < MAX_DYNAMIC_ATTN_GRPS; index++) {
5114 /* take care of sig[0]..sig[4] */
5115 for (sindex = 0; sindex < 4; sindex++) {
5116 sc->attn_group[index].sig[sindex] =
5118 (reg_offset + (sindex * 0x4) +
5122 if (!CHIP_IS_E1x(sc)) {
5124 * enable5 is separate from the rest of the registers,
5125 * and the address skip is 4 and not 16 between the
5128 sc->attn_group[index].sig[4] =
5129 REG_RD(sc, (reg_offset_en5 + (0x4 * index)));
5131 sc->attn_group[index].sig[4] = 0;
5135 if (sc->devinfo.int_block == INT_BLOCK_HC) {
5137 port ? HC_REG_ATTN_MSG1_ADDR_L : HC_REG_ATTN_MSG0_ADDR_L;
5138 REG_WR(sc, reg_offset, U64_LO(section));
5139 REG_WR(sc, (reg_offset + 4), U64_HI(section));
5140 } else if (!CHIP_IS_E1x(sc)) {
5141 REG_WR(sc, IGU_REG_ATTN_MSG_ADDR_L, U64_LO(section));
5142 REG_WR(sc, IGU_REG_ATTN_MSG_ADDR_H, U64_HI(section));
5145 section = ((uint64_t) mapping +
5146 offsetof(struct host_sp_status_block, sp_sb));
5148 bnx2x_zero_sp_sb(sc);
5150 /* PCI guarantees endianity of regpair */
5151 sp_sb_data.state = SB_ENABLED;
5152 sp_sb_data.host_sb_addr.lo = U64_LO(section);
5153 sp_sb_data.host_sb_addr.hi = U64_HI(section);
5154 sp_sb_data.igu_sb_id = igu_sp_sb_index;
5155 sp_sb_data.igu_seg_id = igu_seg_id;
5156 sp_sb_data.p_func.pf_id = func;
5157 sp_sb_data.p_func.vnic_id = SC_VN(sc);
5158 sp_sb_data.p_func.vf_id = 0xff;
5160 bnx2x_wr_sp_sb_data(sc, &sp_sb_data);
5162 bnx2x_ack_sb(sc, sc->igu_dsb_id, USTORM_ID, 0, IGU_INT_ENABLE, 0);
5165 static void bnx2x_init_sp_ring(struct bnx2x_softc *sc)
5167 atomic_store_rel_long(&sc->cq_spq_left, MAX_SPQ_PENDING);
5168 sc->spq_prod_idx = 0;
5170 &sc->def_sb->sp_sb.index_values[HC_SP_INDEX_ETH_DEF_CONS];
5171 sc->spq_prod_bd = sc->spq;
5172 sc->spq_last_bd = (sc->spq_prod_bd + MAX_SP_DESC_CNT);
5175 static void bnx2x_init_eq_ring(struct bnx2x_softc *sc)
5177 union event_ring_elem *elem;
5180 for (i = 1; i <= NUM_EQ_PAGES; i++) {
5181 elem = &sc->eq[EQ_DESC_CNT_PAGE * i - 1];
5183 elem->next_page.addr.hi = htole32(U64_HI(sc->eq_dma.paddr +
5185 (i % NUM_EQ_PAGES)));
5186 elem->next_page.addr.lo = htole32(U64_LO(sc->eq_dma.paddr +
5188 (i % NUM_EQ_PAGES)));
5192 sc->eq_prod = NUM_EQ_DESC;
5193 sc->eq_cons_sb = &sc->def_sb->sp_sb.index_values[HC_SP_INDEX_EQ_CONS];
5195 atomic_store_rel_long(&sc->eq_spq_left,
5196 (min((MAX_SP_DESC_CNT - MAX_SPQ_PENDING),
5200 static void bnx2x_init_internal_common(struct bnx2x_softc *sc)
5206 * In switch independent mode, the TSTORM needs to accept
5207 * packets that failed classification, since approximate match
5208 * mac addresses aren't written to NIG LLH.
5211 (BAR_TSTRORM_INTMEM +
5212 TSTORM_ACCEPT_CLASSIFY_FAILED_OFFSET), 2);
5215 (BAR_TSTRORM_INTMEM +
5216 TSTORM_ACCEPT_CLASSIFY_FAILED_OFFSET), 0);
5219 * Zero this manually as its initialization is currently missing
5222 for (i = 0; i < (USTORM_AGG_DATA_SIZE >> 2); i++) {
5224 (BAR_USTRORM_INTMEM + USTORM_AGG_DATA_OFFSET + (i * 4)),
5228 if (!CHIP_IS_E1x(sc)) {
5229 REG_WR8(sc, (BAR_CSTRORM_INTMEM + CSTORM_IGU_MODE_OFFSET),
5230 CHIP_INT_MODE_IS_BC(sc) ? HC_IGU_BC_MODE :
5235 static void bnx2x_init_internal(struct bnx2x_softc *sc, uint32_t load_code)
5237 switch (load_code) {
5238 case FW_MSG_CODE_DRV_LOAD_COMMON:
5239 case FW_MSG_CODE_DRV_LOAD_COMMON_CHIP:
5240 bnx2x_init_internal_common(sc);
5243 case FW_MSG_CODE_DRV_LOAD_PORT:
5247 case FW_MSG_CODE_DRV_LOAD_FUNCTION:
5248 /* internal memory per function is initialized inside bnx2x_pf_init */
5252 PMD_DRV_LOG(NOTICE, sc, "Unknown load_code (0x%x) from MCP",
5259 storm_memset_func_cfg(struct bnx2x_softc *sc,
5260 struct tstorm_eth_function_common_config *tcfg,
5266 addr = (BAR_TSTRORM_INTMEM +
5267 TSTORM_FUNCTION_COMMON_CONFIG_OFFSET(abs_fid));
5268 size = sizeof(struct tstorm_eth_function_common_config);
5269 ecore_storm_memset_struct(sc, addr, size, (uint32_t *) tcfg);
5272 static void bnx2x_func_init(struct bnx2x_softc *sc, struct bnx2x_func_init_params *p)
5274 struct tstorm_eth_function_common_config tcfg = { 0 };
5276 if (CHIP_IS_E1x(sc)) {
5277 storm_memset_func_cfg(sc, &tcfg, p->func_id);
5280 /* Enable the function in the FW */
5281 storm_memset_vf_to_pf(sc, p->func_id, p->pf_id);
5282 storm_memset_func_en(sc, p->func_id, 1);
5285 if (p->func_flgs & FUNC_FLG_SPQ) {
5286 storm_memset_spq_addr(sc, p->spq_map, p->func_id);
5288 (XSEM_REG_FAST_MEMORY +
5289 XSTORM_SPQ_PROD_OFFSET(p->func_id)), p->spq_prod);
5294 * Calculates the sum of vn_min_rates.
5295 * It's needed for further normalizing of the min_rates.
5297 * sum of vn_min_rates.
5299 * 0 - if all the min_rates are 0.
5300 * In the later case fainess algorithm should be deactivated.
5301 * If all min rates are not zero then those that are zeroes will be set to 1.
5303 static void bnx2x_calc_vn_min(struct bnx2x_softc *sc, struct cmng_init_input *input)
5306 uint32_t vn_min_rate;
5310 for (vn = VN_0; vn < SC_MAX_VN_NUM(sc); vn++) {
5311 vn_cfg = sc->devinfo.mf_info.mf_config[vn];
5312 vn_min_rate = (((vn_cfg & FUNC_MF_CFG_MIN_BW_MASK) >>
5313 FUNC_MF_CFG_MIN_BW_SHIFT) * 100);
5315 if (vn_cfg & FUNC_MF_CFG_FUNC_HIDE) {
5316 /* skip hidden VNs */
5318 } else if (!vn_min_rate) {
5319 /* If min rate is zero - set it to 100 */
5320 vn_min_rate = DEF_MIN_RATE;
5325 input->vnic_min_rate[vn] = vn_min_rate;
5328 /* if ETS or all min rates are zeros - disable fairness */
5330 input->flags.cmng_enables &= ~CMNG_FLAGS_PER_PORT_FAIRNESS_VN;
5332 input->flags.cmng_enables |= CMNG_FLAGS_PER_PORT_FAIRNESS_VN;
5337 bnx2x_extract_max_cfg(__rte_unused struct bnx2x_softc *sc, uint32_t mf_cfg)
5339 uint16_t max_cfg = ((mf_cfg & FUNC_MF_CFG_MAX_BW_MASK) >>
5340 FUNC_MF_CFG_MAX_BW_SHIFT);
5343 PMD_DRV_LOG(DEBUG, sc,
5344 "Max BW configured to 0 - using 100 instead");
5352 bnx2x_calc_vn_max(struct bnx2x_softc *sc, int vn, struct cmng_init_input *input)
5354 uint16_t vn_max_rate;
5355 uint32_t vn_cfg = sc->devinfo.mf_info.mf_config[vn];
5358 if (vn_cfg & FUNC_MF_CFG_FUNC_HIDE) {
5361 max_cfg = bnx2x_extract_max_cfg(sc, vn_cfg);
5364 /* max_cfg in percents of linkspeed */
5366 ((sc->link_vars.line_speed * max_cfg) / 100);
5367 } else { /* SD modes */
5368 /* max_cfg is absolute in 100Mb units */
5369 vn_max_rate = (max_cfg * 100);
5373 input->vnic_max_rate[vn] = vn_max_rate;
5377 bnx2x_cmng_fns_init(struct bnx2x_softc *sc, uint8_t read_cfg, uint8_t cmng_type)
5379 struct cmng_init_input input;
5382 memset(&input, 0, sizeof(struct cmng_init_input));
5384 input.port_rate = sc->link_vars.line_speed;
5386 if (cmng_type == CMNG_FNS_MINMAX) {
5387 /* read mf conf from shmem */
5389 bnx2x_read_mf_cfg(sc);
5392 /* get VN min rate and enable fairness if not 0 */
5393 bnx2x_calc_vn_min(sc, &input);
5395 /* get VN max rate */
5397 for (vn = VN_0; vn < SC_MAX_VN_NUM(sc); vn++) {
5398 bnx2x_calc_vn_max(sc, vn, &input);
5402 /* always enable rate shaping and fairness */
5403 input.flags.cmng_enables |= CMNG_FLAGS_PER_PORT_RATE_SHAPING_VN;
5405 ecore_init_cmng(&input, &sc->cmng);
5410 static int bnx2x_get_cmng_fns_mode(struct bnx2x_softc *sc)
5412 if (CHIP_REV_IS_SLOW(sc)) {
5413 return CMNG_FNS_NONE;
5417 return CMNG_FNS_MINMAX;
5420 return CMNG_FNS_NONE;
5424 storm_memset_cmng(struct bnx2x_softc *sc, struct cmng_init *cmng, uint8_t port)
5431 addr = (BAR_XSTRORM_INTMEM + XSTORM_CMNG_PER_PORT_VARS_OFFSET(port));
5432 size = sizeof(struct cmng_struct_per_port);
5433 ecore_storm_memset_struct(sc, addr, size, (uint32_t *) & cmng->port);
5435 for (vn = VN_0; vn < SC_MAX_VN_NUM(sc); vn++) {
5436 func = func_by_vn(sc, vn);
5438 addr = (BAR_XSTRORM_INTMEM +
5439 XSTORM_RATE_SHAPING_PER_VN_VARS_OFFSET(func));
5440 size = sizeof(struct rate_shaping_vars_per_vn);
5441 ecore_storm_memset_struct(sc, addr, size,
5442 (uint32_t *) & cmng->
5443 vnic.vnic_max_rate[vn]);
5445 addr = (BAR_XSTRORM_INTMEM +
5446 XSTORM_FAIRNESS_PER_VN_VARS_OFFSET(func));
5447 size = sizeof(struct fairness_vars_per_vn);
5448 ecore_storm_memset_struct(sc, addr, size,
5449 (uint32_t *) & cmng->
5450 vnic.vnic_min_rate[vn]);
5454 static void bnx2x_pf_init(struct bnx2x_softc *sc)
5456 struct bnx2x_func_init_params func_init;
5457 struct event_ring_data eq_data;
5460 memset(&eq_data, 0, sizeof(struct event_ring_data));
5461 memset(&func_init, 0, sizeof(struct bnx2x_func_init_params));
5463 if (!CHIP_IS_E1x(sc)) {
5464 /* reset IGU PF statistics: MSIX + ATTN */
5467 (IGU_REG_STATISTIC_NUM_MESSAGE_SENT +
5468 (BNX2X_IGU_STAS_MSG_VF_CNT * 4) +
5469 ((CHIP_IS_MODE_4_PORT(sc) ? SC_FUNC(sc) : SC_VN(sc)) *
5473 (IGU_REG_STATISTIC_NUM_MESSAGE_SENT +
5474 (BNX2X_IGU_STAS_MSG_VF_CNT * 4) +
5475 (BNX2X_IGU_STAS_MSG_PF_CNT * 4) +
5476 ((CHIP_IS_MODE_4_PORT(sc) ? SC_FUNC(sc) : SC_VN(sc)) *
5480 /* function setup flags */
5481 flags = (FUNC_FLG_STATS | FUNC_FLG_LEADING | FUNC_FLG_SPQ);
5483 func_init.func_flgs = flags;
5484 func_init.pf_id = SC_FUNC(sc);
5485 func_init.func_id = SC_FUNC(sc);
5486 func_init.spq_map = sc->spq_dma.paddr;
5487 func_init.spq_prod = sc->spq_prod_idx;
5489 bnx2x_func_init(sc, &func_init);
5491 memset(&sc->cmng, 0, sizeof(struct cmng_struct_per_port));
5494 * Congestion management values depend on the link rate.
5495 * There is no active link so initial link rate is set to 10Gbps.
5496 * When the link comes up the congestion management values are
5497 * re-calculated according to the actual link rate.
5499 sc->link_vars.line_speed = SPEED_10000;
5500 bnx2x_cmng_fns_init(sc, TRUE, bnx2x_get_cmng_fns_mode(sc));
5502 /* Only the PMF sets the HW */
5504 storm_memset_cmng(sc, &sc->cmng, SC_PORT(sc));
5507 /* init Event Queue - PCI bus guarantees correct endainity */
5508 eq_data.base_addr.hi = U64_HI(sc->eq_dma.paddr);
5509 eq_data.base_addr.lo = U64_LO(sc->eq_dma.paddr);
5510 eq_data.producer = sc->eq_prod;
5511 eq_data.index_id = HC_SP_INDEX_EQ_CONS;
5512 eq_data.sb_id = DEF_SB_ID;
5513 storm_memset_eq_data(sc, &eq_data, SC_FUNC(sc));
5516 static void bnx2x_hc_int_enable(struct bnx2x_softc *sc)
5518 int port = SC_PORT(sc);
5519 uint32_t addr = (port) ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0;
5520 uint32_t val = REG_RD(sc, addr);
5521 uint8_t msix = (sc->interrupt_mode == INTR_MODE_MSIX)
5522 || (sc->interrupt_mode == INTR_MODE_SINGLE_MSIX);
5523 uint8_t single_msix = (sc->interrupt_mode == INTR_MODE_SINGLE_MSIX);
5524 uint8_t msi = (sc->interrupt_mode == INTR_MODE_MSI);
5527 val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
5528 HC_CONFIG_0_REG_INT_LINE_EN_0);
5529 val |= (HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
5530 HC_CONFIG_0_REG_ATTN_BIT_EN_0);
5532 val |= HC_CONFIG_0_REG_SINGLE_ISR_EN_0;
5535 val &= ~HC_CONFIG_0_REG_INT_LINE_EN_0;
5536 val |= (HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
5537 HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
5538 HC_CONFIG_0_REG_ATTN_BIT_EN_0);
5540 val |= (HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
5541 HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
5542 HC_CONFIG_0_REG_INT_LINE_EN_0 |
5543 HC_CONFIG_0_REG_ATTN_BIT_EN_0);
5545 REG_WR(sc, addr, val);
5547 val &= ~HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0;
5550 REG_WR(sc, addr, val);
5552 /* ensure that HC_CONFIG is written before leading/trailing edge config */
5555 /* init leading/trailing edge */
5557 val = (0xee0f | (1 << (SC_VN(sc) + 4)));
5559 /* enable nig and gpio3 attention */
5566 REG_WR(sc, (HC_REG_TRAILING_EDGE_0 + port * 8), val);
5567 REG_WR(sc, (HC_REG_LEADING_EDGE_0 + port * 8), val);
5569 /* make sure that interrupts are indeed enabled from here on */
5573 static void bnx2x_igu_int_enable(struct bnx2x_softc *sc)
5576 uint8_t msix = (sc->interrupt_mode == INTR_MODE_MSIX)
5577 || (sc->interrupt_mode == INTR_MODE_SINGLE_MSIX);
5578 uint8_t single_msix = (sc->interrupt_mode == INTR_MODE_SINGLE_MSIX);
5579 uint8_t msi = (sc->interrupt_mode == INTR_MODE_MSI);
5581 val = REG_RD(sc, IGU_REG_PF_CONFIGURATION);
5584 val &= ~(IGU_PF_CONF_INT_LINE_EN | IGU_PF_CONF_SINGLE_ISR_EN);
5585 val |= (IGU_PF_CONF_MSI_MSIX_EN | IGU_PF_CONF_ATTN_BIT_EN);
5587 val |= IGU_PF_CONF_SINGLE_ISR_EN;
5590 val &= ~IGU_PF_CONF_INT_LINE_EN;
5591 val |= (IGU_PF_CONF_MSI_MSIX_EN |
5592 IGU_PF_CONF_ATTN_BIT_EN | IGU_PF_CONF_SINGLE_ISR_EN);
5594 val &= ~IGU_PF_CONF_MSI_MSIX_EN;
5595 val |= (IGU_PF_CONF_INT_LINE_EN |
5596 IGU_PF_CONF_ATTN_BIT_EN | IGU_PF_CONF_SINGLE_ISR_EN);
5599 /* clean previous status - need to configure igu prior to ack */
5600 if ((!msix) || single_msix) {
5601 REG_WR(sc, IGU_REG_PF_CONFIGURATION, val);
5605 val |= IGU_PF_CONF_FUNC_EN;
5607 PMD_DRV_LOG(DEBUG, sc, "write 0x%x to IGU mode %s",
5608 val, ((msix) ? "MSI-X" : ((msi) ? "MSI" : "INTx")));
5610 REG_WR(sc, IGU_REG_PF_CONFIGURATION, val);
5614 /* init leading/trailing edge */
5616 val = (0xee0f | (1 << (SC_VN(sc) + 4)));
5618 /* enable nig and gpio3 attention */
5625 REG_WR(sc, IGU_REG_TRAILING_EDGE_LATCH, val);
5626 REG_WR(sc, IGU_REG_LEADING_EDGE_LATCH, val);
5628 /* make sure that interrupts are indeed enabled from here on */
5632 static void bnx2x_int_enable(struct bnx2x_softc *sc)
5634 if (sc->devinfo.int_block == INT_BLOCK_HC) {
5635 bnx2x_hc_int_enable(sc);
5637 bnx2x_igu_int_enable(sc);
5641 static void bnx2x_hc_int_disable(struct bnx2x_softc *sc)
5643 int port = SC_PORT(sc);
5644 uint32_t addr = (port) ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0;
5645 uint32_t val = REG_RD(sc, addr);
5647 val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
5648 HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
5649 HC_CONFIG_0_REG_INT_LINE_EN_0 | HC_CONFIG_0_REG_ATTN_BIT_EN_0);
5650 /* flush all outstanding writes */
5653 REG_WR(sc, addr, val);
5654 if (REG_RD(sc, addr) != val) {
5655 PMD_DRV_LOG(ERR, sc, "proper val not read from HC IGU!");
5659 static void bnx2x_igu_int_disable(struct bnx2x_softc *sc)
5661 uint32_t val = REG_RD(sc, IGU_REG_PF_CONFIGURATION);
5663 val &= ~(IGU_PF_CONF_MSI_MSIX_EN |
5664 IGU_PF_CONF_INT_LINE_EN | IGU_PF_CONF_ATTN_BIT_EN);
5666 PMD_DRV_LOG(DEBUG, sc, "write %x to IGU", val);
5668 /* flush all outstanding writes */
5671 REG_WR(sc, IGU_REG_PF_CONFIGURATION, val);
5672 if (REG_RD(sc, IGU_REG_PF_CONFIGURATION) != val) {
5673 PMD_DRV_LOG(ERR, sc, "proper val not read from IGU!");
5677 static void bnx2x_int_disable(struct bnx2x_softc *sc)
5679 if (sc->devinfo.int_block == INT_BLOCK_HC) {
5680 bnx2x_hc_int_disable(sc);
5682 bnx2x_igu_int_disable(sc);
5686 static void bnx2x_nic_init(struct bnx2x_softc *sc, int load_code)
5690 PMD_INIT_FUNC_TRACE(sc);
5692 for (i = 0; i < sc->num_queues; i++) {
5693 bnx2x_init_eth_fp(sc, i);
5696 rmb(); /* ensure status block indices were read */
5698 bnx2x_init_rx_rings(sc);
5699 bnx2x_init_tx_rings(sc);
5702 bnx2x_memset_stats(sc);
5706 /* initialize MOD_ABS interrupts */
5707 elink_init_mod_abs_int(sc, &sc->link_vars,
5708 sc->devinfo.chip_id,
5709 sc->devinfo.shmem_base,
5710 sc->devinfo.shmem2_base, SC_PORT(sc));
5712 bnx2x_init_def_sb(sc);
5713 bnx2x_update_dsb_idx(sc);
5714 bnx2x_init_sp_ring(sc);
5715 bnx2x_init_eq_ring(sc);
5716 bnx2x_init_internal(sc, load_code);
5718 bnx2x_stats_init(sc);
5720 /* flush all before enabling interrupts */
5723 bnx2x_int_enable(sc);
5725 /* check for SPIO5 */
5726 bnx2x_attn_int_deasserted0(sc,
5728 (MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 +
5730 AEU_INPUTS_ATTN_BITS_SPIO5);
5733 static void bnx2x_init_objs(struct bnx2x_softc *sc)
5735 /* mcast rules must be added to tx if tx switching is enabled */
5736 ecore_obj_type o_type;
5737 if (sc->flags & BNX2X_TX_SWITCHING)
5738 o_type = ECORE_OBJ_TYPE_RX_TX;
5740 o_type = ECORE_OBJ_TYPE_RX;
5742 /* RX_MODE controlling object */
5743 ecore_init_rx_mode_obj(sc, &sc->rx_mode_obj);
5745 /* multicast configuration controlling object */
5746 ecore_init_mcast_obj(sc,
5752 BNX2X_SP(sc, mcast_rdata),
5753 (phys_addr_t)BNX2X_SP_MAPPING(sc, mcast_rdata),
5754 ECORE_FILTER_MCAST_PENDING,
5755 &sc->sp_state, o_type);
5757 /* Setup CAM credit pools */
5758 ecore_init_mac_credit_pool(sc,
5761 CHIP_IS_E1x(sc) ? VNICS_PER_PORT(sc) :
5762 VNICS_PER_PATH(sc));
5764 ecore_init_vlan_credit_pool(sc,
5766 SC_ABS_FUNC(sc) >> 1,
5767 CHIP_IS_E1x(sc) ? VNICS_PER_PORT(sc) :
5768 VNICS_PER_PATH(sc));
5770 /* RSS configuration object */
5771 ecore_init_rss_config_obj(&sc->rss_conf_obj,
5776 BNX2X_SP(sc, rss_rdata),
5777 (phys_addr_t)BNX2X_SP_MAPPING(sc, rss_rdata),
5778 ECORE_FILTER_RSS_CONF_PENDING,
5779 &sc->sp_state, ECORE_OBJ_TYPE_RX);
5783 * Initialize the function. This must be called before sending CLIENT_SETUP
5784 * for the first client.
5786 static int bnx2x_func_start(struct bnx2x_softc *sc)
5788 struct ecore_func_state_params func_params = { NULL };
5789 struct ecore_func_start_params *start_params =
5790 &func_params.params.start;
5792 /* Prepare parameters for function state transitions */
5793 bnx2x_set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags);
5795 func_params.f_obj = &sc->func_obj;
5796 func_params.cmd = ECORE_F_CMD_START;
5798 /* Function parameters */
5799 start_params->mf_mode = sc->devinfo.mf_info.mf_mode;
5800 start_params->sd_vlan_tag = OVLAN(sc);
5802 if (CHIP_IS_E2(sc) || CHIP_IS_E3(sc)) {
5803 start_params->network_cos_mode = STATIC_COS;
5804 } else { /* CHIP_IS_E1X */
5805 start_params->network_cos_mode = FW_WRR;
5808 start_params->gre_tunnel_mode = 0;
5809 start_params->gre_tunnel_rss = 0;
5811 return ecore_func_state_change(sc, &func_params);
5814 static int bnx2x_set_power_state(struct bnx2x_softc *sc, uint8_t state)
5818 /* If there is no power capability, silently succeed */
5819 if (!(sc->devinfo.pcie_cap_flags & BNX2X_PM_CAPABLE_FLAG)) {
5820 PMD_DRV_LOG(WARNING, sc, "No power capability");
5824 pci_read(sc, (sc->devinfo.pcie_pm_cap_reg + PCIR_POWER_STATUS), &pmcsr,
5830 (sc->devinfo.pcie_pm_cap_reg +
5832 ((pmcsr & ~PCIM_PSTAT_DMASK) | PCIM_PSTAT_PME));
5834 if (pmcsr & PCIM_PSTAT_DMASK) {
5835 /* delay required during transition out of D3hot */
5842 /* don't shut down the power for emulation and FPGA */
5843 if (CHIP_REV_IS_SLOW(sc)) {
5847 pmcsr &= ~PCIM_PSTAT_DMASK;
5848 pmcsr |= PCIM_PSTAT_D3;
5851 pmcsr |= PCIM_PSTAT_PMEENABLE;
5855 (sc->devinfo.pcie_pm_cap_reg +
5856 PCIR_POWER_STATUS), pmcsr);
5859 * No more memory access after this point until device is brought back
5865 PMD_DRV_LOG(NOTICE, sc, "Can't support PCI power state = %d",
5873 /* return true if succeeded to acquire the lock */
5874 static uint8_t bnx2x_trylock_hw_lock(struct bnx2x_softc *sc, uint32_t resource)
5876 uint32_t lock_status;
5877 uint32_t resource_bit = (1 << resource);
5878 int func = SC_FUNC(sc);
5879 uint32_t hw_lock_control_reg;
5881 /* Validating that the resource is within range */
5882 if (resource > HW_LOCK_MAX_RESOURCE_VALUE) {
5883 PMD_DRV_LOG(INFO, sc,
5884 "resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)",
5885 resource, HW_LOCK_MAX_RESOURCE_VALUE);
5890 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + func * 8);
5892 hw_lock_control_reg =
5893 (MISC_REG_DRIVER_CONTROL_7 + (func - 6) * 8);
5896 /* try to acquire the lock */
5897 REG_WR(sc, hw_lock_control_reg + 4, resource_bit);
5898 lock_status = REG_RD(sc, hw_lock_control_reg);
5899 if (lock_status & resource_bit) {
5903 PMD_DRV_LOG(NOTICE, sc, "Failed to get a resource lock 0x%x", resource);
5909 * Get the recovery leader resource id according to the engine this function
5910 * belongs to. Currently only only 2 engines is supported.
5912 static int bnx2x_get_leader_lock_resource(struct bnx2x_softc *sc)
5915 return HW_LOCK_RESOURCE_RECOVERY_LEADER_1;
5917 return HW_LOCK_RESOURCE_RECOVERY_LEADER_0;
5921 /* try to acquire a leader lock for current engine */
5922 static uint8_t bnx2x_trylock_leader_lock(struct bnx2x_softc *sc)
5924 return bnx2x_trylock_hw_lock(sc, bnx2x_get_leader_lock_resource(sc));
5927 static int bnx2x_release_leader_lock(struct bnx2x_softc *sc)
5929 return bnx2x_release_hw_lock(sc, bnx2x_get_leader_lock_resource(sc));
5932 /* close gates #2, #3 and #4 */
5933 static void bnx2x_set_234_gates(struct bnx2x_softc *sc, uint8_t close)
5937 /* gates #2 and #4a are closed/opened */
5939 REG_WR(sc, PXP_REG_HST_DISCARD_DOORBELLS, ! !close);
5941 REG_WR(sc, PXP_REG_HST_DISCARD_INTERNAL_WRITES, ! !close);
5944 if (CHIP_IS_E1x(sc)) {
5945 /* prevent interrupts from HC on both ports */
5946 val = REG_RD(sc, HC_REG_CONFIG_1);
5948 REG_WR(sc, HC_REG_CONFIG_1, (val & ~(uint32_t)
5949 HC_CONFIG_1_REG_BLOCK_DISABLE_1));
5951 REG_WR(sc, HC_REG_CONFIG_1,
5952 (val | HC_CONFIG_1_REG_BLOCK_DISABLE_1));
5954 val = REG_RD(sc, HC_REG_CONFIG_0);
5956 REG_WR(sc, HC_REG_CONFIG_0, (val & ~(uint32_t)
5957 HC_CONFIG_0_REG_BLOCK_DISABLE_0));
5959 REG_WR(sc, HC_REG_CONFIG_0,
5960 (val | HC_CONFIG_0_REG_BLOCK_DISABLE_0));
5963 /* Prevent incomming interrupts in IGU */
5964 val = REG_RD(sc, IGU_REG_BLOCK_CONFIGURATION);
5967 REG_WR(sc, IGU_REG_BLOCK_CONFIGURATION,
5969 IGU_BLOCK_CONFIGURATION_REG_BLOCK_ENABLE));
5971 REG_WR(sc, IGU_REG_BLOCK_CONFIGURATION,
5973 IGU_BLOCK_CONFIGURATION_REG_BLOCK_ENABLE));
5979 /* poll for pending writes bit, it should get cleared in no more than 1s */
5980 static int bnx2x_er_poll_igu_vq(struct bnx2x_softc *sc)
5982 uint32_t cnt = 1000;
5983 uint32_t pend_bits = 0;
5986 pend_bits = REG_RD(sc, IGU_REG_PENDING_BITS_STATUS);
5988 if (pend_bits == 0) {
5993 } while (cnt-- > 0);
5996 PMD_DRV_LOG(NOTICE, sc, "Still pending IGU requests bits=0x%08x!",
6004 #define SHARED_MF_CLP_MAGIC 0x80000000 /* 'magic' bit */
6006 static void bnx2x_clp_reset_prep(struct bnx2x_softc *sc, uint32_t * magic_val)
6008 /* Do some magic... */
6009 uint32_t val = MFCFG_RD(sc, shared_mf_config.clp_mb);
6010 *magic_val = val & SHARED_MF_CLP_MAGIC;
6011 MFCFG_WR(sc, shared_mf_config.clp_mb, val | SHARED_MF_CLP_MAGIC);
6014 /* restore the value of the 'magic' bit */
6015 static void bnx2x_clp_reset_done(struct bnx2x_softc *sc, uint32_t magic_val)
6017 /* Restore the 'magic' bit value... */
6018 uint32_t val = MFCFG_RD(sc, shared_mf_config.clp_mb);
6019 MFCFG_WR(sc, shared_mf_config.clp_mb,
6020 (val & (~SHARED_MF_CLP_MAGIC)) | magic_val);
6023 /* prepare for MCP reset, takes care of CLP configurations */
6024 static void bnx2x_reset_mcp_prep(struct bnx2x_softc *sc, uint32_t * magic_val)
6027 uint32_t validity_offset;
6029 /* set `magic' bit in order to save MF config */
6030 bnx2x_clp_reset_prep(sc, magic_val);
6032 /* get shmem offset */
6033 shmem = REG_RD(sc, MISC_REG_SHARED_MEM_ADDR);
6035 offsetof(struct shmem_region, validity_map[SC_PORT(sc)]);
6037 /* Clear validity map flags */
6039 REG_WR(sc, shmem + validity_offset, 0);
6043 #define MCP_TIMEOUT 5000 /* 5 seconds (in ms) */
6044 #define MCP_ONE_TIMEOUT 100 /* 100 ms */
6046 static void bnx2x_mcp_wait_one(struct bnx2x_softc *sc)
6048 /* special handling for emulation and FPGA (10 times longer) */
6049 if (CHIP_REV_IS_SLOW(sc)) {
6050 DELAY((MCP_ONE_TIMEOUT * 10) * 1000);
6052 DELAY((MCP_ONE_TIMEOUT) * 1000);
6056 /* initialize shmem_base and waits for validity signature to appear */
6057 static int bnx2x_init_shmem(struct bnx2x_softc *sc)
6063 sc->devinfo.shmem_base =
6064 sc->link_params.shmem_base =
6065 REG_RD(sc, MISC_REG_SHARED_MEM_ADDR);
6067 if (sc->devinfo.shmem_base) {
6068 val = SHMEM_RD(sc, validity_map[SC_PORT(sc)]);
6069 if (val & SHR_MEM_VALIDITY_MB)
6073 bnx2x_mcp_wait_one(sc);
6075 } while (cnt++ < (MCP_TIMEOUT / MCP_ONE_TIMEOUT));
6077 PMD_DRV_LOG(NOTICE, sc, "BAD MCP validity signature");
6082 static int bnx2x_reset_mcp_comp(struct bnx2x_softc *sc, uint32_t magic_val)
6084 int rc = bnx2x_init_shmem(sc);
6086 /* Restore the `magic' bit value */
6087 bnx2x_clp_reset_done(sc, magic_val);
6092 static void bnx2x_pxp_prep(struct bnx2x_softc *sc)
6094 REG_WR(sc, PXP2_REG_RD_START_INIT, 0);
6095 REG_WR(sc, PXP2_REG_RQ_RBC_DONE, 0);
6100 * Reset the whole chip except for:
6102 * - PCI Glue, PSWHST, PXP/PXP2 RF (all controlled by one reset bit)
6104 * - MISC (including AEU)
6108 static void bnx2x_process_kill_chip_reset(struct bnx2x_softc *sc, uint8_t global)
6110 uint32_t not_reset_mask1, reset_mask1, not_reset_mask2, reset_mask2;
6111 uint32_t global_bits2, stay_reset2;
6114 * Bits that have to be set in reset_mask2 if we want to reset 'global'
6115 * (per chip) blocks.
6118 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_CMN_CPU |
6119 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_CMN_CORE;
6122 * Don't reset the following blocks.
6123 * Important: per port blocks (such as EMAC, BMAC, UMAC) can't be
6124 * reset, as in 4 port device they might still be owned
6125 * by the MCP (there is only one leader per path).
6128 MISC_REGISTERS_RESET_REG_1_RST_HC |
6129 MISC_REGISTERS_RESET_REG_1_RST_PXPV |
6130 MISC_REGISTERS_RESET_REG_1_RST_PXP;
6133 MISC_REGISTERS_RESET_REG_2_RST_PCI_MDIO |
6134 MISC_REGISTERS_RESET_REG_2_RST_EMAC0_HARD_CORE |
6135 MISC_REGISTERS_RESET_REG_2_RST_EMAC1_HARD_CORE |
6136 MISC_REGISTERS_RESET_REG_2_RST_MISC_CORE |
6137 MISC_REGISTERS_RESET_REG_2_RST_RBCN |
6138 MISC_REGISTERS_RESET_REG_2_RST_GRC |
6139 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_REG_HARD_CORE |
6140 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_HARD_CORE_RST_B |
6141 MISC_REGISTERS_RESET_REG_2_RST_ATC |
6142 MISC_REGISTERS_RESET_REG_2_PGLC |
6143 MISC_REGISTERS_RESET_REG_2_RST_BMAC0 |
6144 MISC_REGISTERS_RESET_REG_2_RST_BMAC1 |
6145 MISC_REGISTERS_RESET_REG_2_RST_EMAC0 |
6146 MISC_REGISTERS_RESET_REG_2_RST_EMAC1 |
6147 MISC_REGISTERS_RESET_REG_2_UMAC0 | MISC_REGISTERS_RESET_REG_2_UMAC1;
6150 * Keep the following blocks in reset:
6151 * - all xxMACs are handled by the elink code.
6154 MISC_REGISTERS_RESET_REG_2_XMAC |
6155 MISC_REGISTERS_RESET_REG_2_XMAC_SOFT;
6157 /* Full reset masks according to the chip */
6158 reset_mask1 = 0xffffffff;
6160 if (CHIP_IS_E1H(sc))
6161 reset_mask2 = 0x1ffff;
6162 else if (CHIP_IS_E2(sc))
6163 reset_mask2 = 0xfffff;
6164 else /* CHIP_IS_E3 */
6165 reset_mask2 = 0x3ffffff;
6167 /* Don't reset global blocks unless we need to */
6169 reset_mask2 &= ~global_bits2;
6172 * In case of attention in the QM, we need to reset PXP
6173 * (MISC_REGISTERS_RESET_REG_2_RST_PXP_RQ_RD_WR) before QM
6174 * because otherwise QM reset would release 'close the gates' shortly
6175 * before resetting the PXP, then the PSWRQ would send a write
6176 * request to PGLUE. Then when PXP is reset, PGLUE would try to
6177 * read the payload data from PSWWR, but PSWWR would not
6178 * respond. The write queue in PGLUE would stuck, dmae commands
6179 * would not return. Therefore it's important to reset the second
6180 * reset register (containing the
6181 * MISC_REGISTERS_RESET_REG_2_RST_PXP_RQ_RD_WR bit) before the
6182 * first one (containing the MISC_REGISTERS_RESET_REG_1_RST_QM
6185 REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
6186 reset_mask2 & (~not_reset_mask2));
6188 REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR,
6189 reset_mask1 & (~not_reset_mask1));
6194 REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,
6195 reset_mask2 & (~stay_reset2));
6200 REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, reset_mask1);
6204 static int bnx2x_process_kill(struct bnx2x_softc *sc, uint8_t global)
6208 uint32_t sr_cnt, blk_cnt, port_is_idle_0, port_is_idle_1, pgl_exp_rom2;
6209 uint32_t tags_63_32 = 0;
6211 /* Empty the Tetris buffer, wait for 1s */
6213 sr_cnt = REG_RD(sc, PXP2_REG_RD_SR_CNT);
6214 blk_cnt = REG_RD(sc, PXP2_REG_RD_BLK_CNT);
6215 port_is_idle_0 = REG_RD(sc, PXP2_REG_RD_PORT_IS_IDLE_0);
6216 port_is_idle_1 = REG_RD(sc, PXP2_REG_RD_PORT_IS_IDLE_1);
6217 pgl_exp_rom2 = REG_RD(sc, PXP2_REG_PGL_EXP_ROM2);
6218 if (CHIP_IS_E3(sc)) {
6219 tags_63_32 = REG_RD(sc, PGLUE_B_REG_TAGS_63_32);
6222 if ((sr_cnt == 0x7e) && (blk_cnt == 0xa0) &&
6223 ((port_is_idle_0 & 0x1) == 0x1) &&
6224 ((port_is_idle_1 & 0x1) == 0x1) &&
6225 (pgl_exp_rom2 == 0xffffffff) &&
6226 (!CHIP_IS_E3(sc) || (tags_63_32 == 0xffffffff)))
6229 } while (cnt-- > 0);
6232 PMD_DRV_LOG(NOTICE, sc,
6233 "ERROR: Tetris buffer didn't get empty or there "
6234 "are still outstanding read requests after 1s! "
6235 "sr_cnt=0x%08x, blk_cnt=0x%08x, port_is_idle_0=0x%08x, "
6236 "port_is_idle_1=0x%08x, pgl_exp_rom2=0x%08x",
6237 sr_cnt, blk_cnt, port_is_idle_0, port_is_idle_1,
6244 /* Close gates #2, #3 and #4 */
6245 bnx2x_set_234_gates(sc, TRUE);
6247 /* Poll for IGU VQs for 57712 and newer chips */
6248 if (!CHIP_IS_E1x(sc) && bnx2x_er_poll_igu_vq(sc)) {
6252 /* clear "unprepared" bit */
6253 REG_WR(sc, MISC_REG_UNPREPARED, 0);
6256 /* Make sure all is written to the chip before the reset */
6260 * Wait for 1ms to empty GLUE and PCI-E core queues,
6261 * PSWHST, GRC and PSWRD Tetris buffer.
6265 /* Prepare to chip reset: */
6268 bnx2x_reset_mcp_prep(sc, &val);
6275 /* reset the chip */
6276 bnx2x_process_kill_chip_reset(sc, global);
6279 /* Recover after reset: */
6281 if (global && bnx2x_reset_mcp_comp(sc, val)) {
6285 /* Open the gates #2, #3 and #4 */
6286 bnx2x_set_234_gates(sc, FALSE);
6291 static int bnx2x_leader_reset(struct bnx2x_softc *sc)
6294 uint8_t global = bnx2x_reset_is_global(sc);
6298 * If not going to reset MCP, load "fake" driver to reset HW while
6299 * driver is owner of the HW.
6301 if (!global && !BNX2X_NOMCP(sc)) {
6302 load_code = bnx2x_fw_command(sc, DRV_MSG_CODE_LOAD_REQ,
6303 DRV_MSG_CODE_LOAD_REQ_WITH_LFA);
6305 PMD_DRV_LOG(NOTICE, sc, "MCP response failure, aborting");
6307 goto exit_leader_reset;
6310 if ((load_code != FW_MSG_CODE_DRV_LOAD_COMMON_CHIP) &&
6311 (load_code != FW_MSG_CODE_DRV_LOAD_COMMON)) {
6312 PMD_DRV_LOG(NOTICE, sc,
6313 "MCP unexpected response, aborting");
6315 goto exit_leader_reset2;
6318 load_code = bnx2x_fw_command(sc, DRV_MSG_CODE_LOAD_DONE, 0);
6320 PMD_DRV_LOG(NOTICE, sc, "MCP response failure, aborting");
6322 goto exit_leader_reset2;
6326 /* try to recover after the failure */
6327 if (bnx2x_process_kill(sc, global)) {
6328 PMD_DRV_LOG(NOTICE, sc, "Something bad occurred on engine %d!",
6331 goto exit_leader_reset2;
6335 * Clear the RESET_IN_PROGRESS and RESET_GLOBAL bits and update the driver
6338 bnx2x_set_reset_done(sc);
6340 bnx2x_clear_reset_global(sc);
6345 /* unload "fake driver" if it was loaded */
6346 if (!global &&!BNX2X_NOMCP(sc)) {
6347 bnx2x_fw_command(sc, DRV_MSG_CODE_UNLOAD_REQ_WOL_MCP, 0);
6348 bnx2x_fw_command(sc, DRV_MSG_CODE_UNLOAD_DONE, 0);
6354 bnx2x_release_leader_lock(sc);
6361 * prepare INIT transition, parameters configured:
6362 * - HC configuration
6363 * - Queue's CDU context
6366 bnx2x_pf_q_prep_init(struct bnx2x_softc *sc, struct bnx2x_fastpath *fp,
6367 struct ecore_queue_init_params *init_params)
6370 int cxt_index, cxt_offset;
6372 bnx2x_set_bit(ECORE_Q_FLG_HC, &init_params->rx.flags);
6373 bnx2x_set_bit(ECORE_Q_FLG_HC, &init_params->tx.flags);
6375 bnx2x_set_bit(ECORE_Q_FLG_HC_EN, &init_params->rx.flags);
6376 bnx2x_set_bit(ECORE_Q_FLG_HC_EN, &init_params->tx.flags);
6379 init_params->rx.hc_rate =
6380 sc->hc_rx_ticks ? (1000000 / sc->hc_rx_ticks) : 0;
6381 init_params->tx.hc_rate =
6382 sc->hc_tx_ticks ? (1000000 / sc->hc_tx_ticks) : 0;
6385 init_params->rx.fw_sb_id = init_params->tx.fw_sb_id = fp->fw_sb_id;
6387 /* CQ index among the SB indices */
6388 init_params->rx.sb_cq_index = HC_INDEX_ETH_RX_CQ_CONS;
6389 init_params->tx.sb_cq_index = HC_INDEX_ETH_FIRST_TX_CQ_CONS;
6391 /* set maximum number of COSs supported by this queue */
6392 init_params->max_cos = sc->max_cos;
6394 /* set the context pointers queue object */
6395 for (cos = FIRST_TX_COS_INDEX; cos < init_params->max_cos; cos++) {
6396 cxt_index = fp->index / ILT_PAGE_CIDS;
6397 cxt_offset = fp->index - (cxt_index * ILT_PAGE_CIDS);
6398 init_params->cxts[cos] =
6399 &sc->context[cxt_index].vcxt[cxt_offset].eth;
6403 /* set flags that are common for the Tx-only and not normal connections */
6404 static unsigned long
6405 bnx2x_get_common_flags(struct bnx2x_softc *sc, uint8_t zero_stats)
6407 unsigned long flags = 0;
6409 /* PF driver will always initialize the Queue to an ACTIVE state */
6410 bnx2x_set_bit(ECORE_Q_FLG_ACTIVE, &flags);
6413 * tx only connections collect statistics (on the same index as the
6414 * parent connection). The statistics are zeroed when the parent
6415 * connection is initialized.
6418 bnx2x_set_bit(ECORE_Q_FLG_STATS, &flags);
6420 bnx2x_set_bit(ECORE_Q_FLG_ZERO_STATS, &flags);
6424 * tx only connections can support tx-switching, though their
6425 * CoS-ness doesn't survive the loopback
6427 if (sc->flags & BNX2X_TX_SWITCHING) {
6428 bnx2x_set_bit(ECORE_Q_FLG_TX_SWITCH, &flags);
6431 bnx2x_set_bit(ECORE_Q_FLG_PCSUM_ON_PKT, &flags);
6436 static unsigned long bnx2x_get_q_flags(struct bnx2x_softc *sc, uint8_t leading)
6438 unsigned long flags = 0;
6441 bnx2x_set_bit(ECORE_Q_FLG_OV, &flags);
6445 bnx2x_set_bit(ECORE_Q_FLG_LEADING_RSS, &flags);
6446 bnx2x_set_bit(ECORE_Q_FLG_MCAST, &flags);
6449 bnx2x_set_bit(ECORE_Q_FLG_VLAN, &flags);
6451 /* merge with common flags */
6452 return flags | bnx2x_get_common_flags(sc, TRUE);
6456 bnx2x_pf_q_prep_general(struct bnx2x_softc *sc, struct bnx2x_fastpath *fp,
6457 struct ecore_general_setup_params *gen_init, uint8_t cos)
6459 gen_init->stat_id = bnx2x_stats_id(fp);
6460 gen_init->spcl_id = fp->cl_id;
6461 gen_init->mtu = sc->mtu;
6462 gen_init->cos = cos;
6466 bnx2x_pf_rx_q_prep(struct bnx2x_softc *sc, struct bnx2x_fastpath *fp,
6467 struct rxq_pause_params *pause,
6468 struct ecore_rxq_setup_params *rxq_init)
6470 struct bnx2x_rx_queue *rxq;
6472 rxq = sc->rx_queues[fp->index];
6474 PMD_RX_LOG(ERR, "RX queue is NULL");
6478 pause->bd_th_lo = BD_TH_LO(sc);
6479 pause->bd_th_hi = BD_TH_HI(sc);
6481 pause->rcq_th_lo = RCQ_TH_LO(sc);
6482 pause->rcq_th_hi = RCQ_TH_HI(sc);
6484 /* validate rings have enough entries to cross high thresholds */
6485 if (sc->dropless_fc &&
6486 pause->bd_th_hi + FW_PREFETCH_CNT > sc->rx_ring_size) {
6487 PMD_DRV_LOG(WARNING, sc, "rx bd ring threshold limit");
6490 if (sc->dropless_fc &&
6491 pause->rcq_th_hi + FW_PREFETCH_CNT > USABLE_RCQ_ENTRIES(rxq)) {
6492 PMD_DRV_LOG(WARNING, sc, "rcq ring threshold limit");
6498 rxq_init->dscr_map = (phys_addr_t)rxq->rx_ring_phys_addr;
6499 rxq_init->rcq_map = (phys_addr_t)rxq->cq_ring_phys_addr;
6500 rxq_init->rcq_np_map = (phys_addr_t)(rxq->cq_ring_phys_addr +
6504 * This should be a maximum number of data bytes that may be
6505 * placed on the BD (not including paddings).
6507 rxq_init->buf_sz = (fp->rx_buf_size - IP_HEADER_ALIGNMENT_PADDING);
6509 rxq_init->cl_qzone_id = fp->cl_qzone_id;
6510 rxq_init->rss_engine_id = SC_FUNC(sc);
6511 rxq_init->mcast_engine_id = SC_FUNC(sc);
6513 rxq_init->cache_line_log = BNX2X_RX_ALIGN_SHIFT;
6514 rxq_init->fw_sb_id = fp->fw_sb_id;
6516 rxq_init->sb_cq_index = HC_INDEX_ETH_RX_CQ_CONS;
6519 * configure silent vlan removal
6520 * if multi function mode is afex, then mask default vlan
6522 if (IS_MF_AFEX(sc)) {
6523 rxq_init->silent_removal_value =
6524 sc->devinfo.mf_info.afex_def_vlan_tag;
6525 rxq_init->silent_removal_mask = EVL_VLID_MASK;
6530 bnx2x_pf_tx_q_prep(struct bnx2x_softc *sc, struct bnx2x_fastpath *fp,
6531 struct ecore_txq_setup_params *txq_init, uint8_t cos)
6533 struct bnx2x_tx_queue *txq = fp->sc->tx_queues[fp->index];
6536 PMD_TX_LOG(ERR, "ERROR: TX queue is NULL");
6539 txq_init->dscr_map = (phys_addr_t)txq->tx_ring_phys_addr;
6540 txq_init->sb_cq_index = HC_INDEX_ETH_FIRST_TX_CQ_CONS + cos;
6541 txq_init->traffic_type = LLFC_TRAFFIC_TYPE_NW;
6542 txq_init->fw_sb_id = fp->fw_sb_id;
6545 * set the TSS leading client id for TX classfication to the
6546 * leading RSS client id
6548 txq_init->tss_leading_cl_id = BNX2X_FP(sc, 0, cl_id);
6552 * This function performs 2 steps in a queue state machine:
6557 bnx2x_setup_queue(struct bnx2x_softc *sc, struct bnx2x_fastpath *fp, uint8_t leading)
6559 struct ecore_queue_state_params q_params = { NULL };
6560 struct ecore_queue_setup_params *setup_params = &q_params.params.setup;
6563 PMD_DRV_LOG(DEBUG, sc, "setting up queue %d", fp->index);
6565 bnx2x_ack_sb(sc, fp->igu_sb_id, USTORM_ID, 0, IGU_INT_ENABLE, 0);
6567 q_params.q_obj = &BNX2X_SP_OBJ(sc, fp).q_obj;
6569 /* we want to wait for completion in this context */
6570 bnx2x_set_bit(RAMROD_COMP_WAIT, &q_params.ramrod_flags);
6572 /* prepare the INIT parameters */
6573 bnx2x_pf_q_prep_init(sc, fp, &q_params.params.init);
6575 /* Set the command */
6576 q_params.cmd = ECORE_Q_CMD_INIT;
6578 /* Change the state to INIT */
6579 rc = ecore_queue_state_change(sc, &q_params);
6581 PMD_DRV_LOG(NOTICE, sc, "Queue(%d) INIT failed", fp->index);
6585 PMD_DRV_LOG(DEBUG, sc, "init complete");
6587 /* now move the Queue to the SETUP state */
6588 memset(setup_params, 0, sizeof(*setup_params));
6590 /* set Queue flags */
6591 setup_params->flags = bnx2x_get_q_flags(sc, leading);
6593 /* set general SETUP parameters */
6594 bnx2x_pf_q_prep_general(sc, fp, &setup_params->gen_params,
6595 FIRST_TX_COS_INDEX);
6597 bnx2x_pf_rx_q_prep(sc, fp,
6598 &setup_params->pause_params,
6599 &setup_params->rxq_params);
6601 bnx2x_pf_tx_q_prep(sc, fp, &setup_params->txq_params, FIRST_TX_COS_INDEX);
6603 /* Set the command */
6604 q_params.cmd = ECORE_Q_CMD_SETUP;
6606 /* change the state to SETUP */
6607 rc = ecore_queue_state_change(sc, &q_params);
6609 PMD_DRV_LOG(NOTICE, sc, "Queue(%d) SETUP failed", fp->index);
6616 static int bnx2x_setup_leading(struct bnx2x_softc *sc)
6619 return bnx2x_setup_queue(sc, &sc->fp[0], TRUE);
6621 return bnx2x_vf_setup_queue(sc, &sc->fp[0], TRUE);
6625 bnx2x_config_rss_pf(struct bnx2x_softc *sc, struct ecore_rss_config_obj *rss_obj,
6626 uint8_t config_hash)
6628 struct ecore_config_rss_params params = { NULL };
6632 * Although RSS is meaningless when there is a single HW queue we
6633 * still need it enabled in order to have HW Rx hash generated.
6636 params.rss_obj = rss_obj;
6638 bnx2x_set_bit(RAMROD_COMP_WAIT, ¶ms.ramrod_flags);
6640 bnx2x_set_bit(ECORE_RSS_MODE_REGULAR, ¶ms.rss_flags);
6642 /* RSS configuration */
6643 bnx2x_set_bit(ECORE_RSS_IPV4, ¶ms.rss_flags);
6644 bnx2x_set_bit(ECORE_RSS_IPV4_TCP, ¶ms.rss_flags);
6645 bnx2x_set_bit(ECORE_RSS_IPV6, ¶ms.rss_flags);
6646 bnx2x_set_bit(ECORE_RSS_IPV6_TCP, ¶ms.rss_flags);
6647 if (rss_obj->udp_rss_v4) {
6648 bnx2x_set_bit(ECORE_RSS_IPV4_UDP, ¶ms.rss_flags);
6650 if (rss_obj->udp_rss_v6) {
6651 bnx2x_set_bit(ECORE_RSS_IPV6_UDP, ¶ms.rss_flags);
6655 params.rss_result_mask = MULTI_MASK;
6657 (void)rte_memcpy(params.ind_table, rss_obj->ind_table,
6658 sizeof(params.ind_table));
6662 for (i = 0; i < sizeof(params.rss_key) / 4; i++) {
6663 params.rss_key[i] = (uint32_t) rte_rand();
6666 bnx2x_set_bit(ECORE_RSS_SET_SRCH, ¶ms.rss_flags);
6670 return ecore_config_rss(sc, ¶ms);
6672 return bnx2x_vf_config_rss(sc, ¶ms);
6675 static int bnx2x_config_rss_eth(struct bnx2x_softc *sc, uint8_t config_hash)
6677 return bnx2x_config_rss_pf(sc, &sc->rss_conf_obj, config_hash);
6680 static int bnx2x_init_rss_pf(struct bnx2x_softc *sc)
6682 uint8_t num_eth_queues = BNX2X_NUM_ETH_QUEUES(sc);
6686 * Prepare the initial contents of the indirection table if
6689 for (i = 0; i < sizeof(sc->rss_conf_obj.ind_table); i++) {
6690 sc->rss_conf_obj.ind_table[i] =
6691 (sc->fp->cl_id + (i % num_eth_queues));
6695 sc->rss_conf_obj.udp_rss_v4 = sc->rss_conf_obj.udp_rss_v6 = 1;
6699 * For 57711 SEARCHER configuration (rss_keys) is
6700 * per-port, so if explicit configuration is needed, do it only
6703 * For 57712 and newer it's a per-function configuration.
6705 return bnx2x_config_rss_eth(sc, sc->port.pmf || !CHIP_IS_E1x(sc));
6709 bnx2x_set_mac_one(struct bnx2x_softc *sc, uint8_t * mac,
6710 struct ecore_vlan_mac_obj *obj, uint8_t set, int mac_type,
6711 unsigned long *ramrod_flags)
6713 struct ecore_vlan_mac_ramrod_params ramrod_param;
6716 memset(&ramrod_param, 0, sizeof(ramrod_param));
6718 /* fill in general parameters */
6719 ramrod_param.vlan_mac_obj = obj;
6720 ramrod_param.ramrod_flags = *ramrod_flags;
6722 /* fill a user request section if needed */
6723 if (!bnx2x_test_bit(RAMROD_CONT, ramrod_flags)) {
6724 (void)rte_memcpy(ramrod_param.user_req.u.mac.mac, mac,
6727 bnx2x_set_bit(mac_type, &ramrod_param.user_req.vlan_mac_flags);
6729 /* Set the command: ADD or DEL */
6730 ramrod_param.user_req.cmd = (set) ? ECORE_VLAN_MAC_ADD :
6734 rc = ecore_config_vlan_mac(sc, &ramrod_param);
6736 if (rc == ECORE_EXISTS) {
6737 PMD_DRV_LOG(INFO, sc, "Failed to schedule ADD operations (EEXIST)");
6738 /* do not treat adding same MAC as error */
6740 } else if (rc < 0) {
6741 PMD_DRV_LOG(ERR, sc,
6742 "%s MAC failed (%d)", (set ? "Set" : "Delete"), rc);
6748 static int bnx2x_set_eth_mac(struct bnx2x_softc *sc, uint8_t set)
6750 unsigned long ramrod_flags = 0;
6752 PMD_DRV_LOG(DEBUG, sc, "Adding Ethernet MAC");
6754 bnx2x_set_bit(RAMROD_COMP_WAIT, &ramrod_flags);
6756 /* Eth MAC is set on RSS leading client (fp[0]) */
6757 return bnx2x_set_mac_one(sc, sc->link_params.mac_addr,
6758 &sc->sp_objs->mac_obj,
6759 set, ECORE_ETH_MAC, &ramrod_flags);
6762 static int bnx2x_get_cur_phy_idx(struct bnx2x_softc *sc)
6764 uint32_t sel_phy_idx = 0;
6766 if (sc->link_params.num_phys <= 1) {
6767 return ELINK_INT_PHY;
6770 if (sc->link_vars.link_up) {
6771 sel_phy_idx = ELINK_EXT_PHY1;
6772 /* In case link is SERDES, check if the ELINK_EXT_PHY2 is the one */
6773 if ((sc->link_vars.link_status & LINK_STATUS_SERDES_LINK) &&
6774 (sc->link_params.phy[ELINK_EXT_PHY2].supported &
6775 ELINK_SUPPORTED_FIBRE))
6776 sel_phy_idx = ELINK_EXT_PHY2;
6778 switch (elink_phy_selection(&sc->link_params)) {
6779 case PORT_HW_CFG_PHY_SELECTION_HARDWARE_DEFAULT:
6780 case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY:
6781 case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY_PRIORITY:
6782 sel_phy_idx = ELINK_EXT_PHY1;
6784 case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY:
6785 case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY_PRIORITY:
6786 sel_phy_idx = ELINK_EXT_PHY2;
6794 static int bnx2x_get_link_cfg_idx(struct bnx2x_softc *sc)
6796 uint32_t sel_phy_idx = bnx2x_get_cur_phy_idx(sc);
6799 * The selected activated PHY is always after swapping (in case PHY
6800 * swapping is enabled). So when swapping is enabled, we need to reverse
6804 if (sc->link_params.multi_phy_config & PORT_HW_CFG_PHY_SWAPPED_ENABLED) {
6805 if (sel_phy_idx == ELINK_EXT_PHY1)
6806 sel_phy_idx = ELINK_EXT_PHY2;
6807 else if (sel_phy_idx == ELINK_EXT_PHY2)
6808 sel_phy_idx = ELINK_EXT_PHY1;
6811 return ELINK_LINK_CONFIG_IDX(sel_phy_idx);
6814 static void bnx2x_set_requested_fc(struct bnx2x_softc *sc)
6817 * Initialize link parameters structure variables
6818 * It is recommended to turn off RX FC for jumbo frames
6819 * for better performance
6821 if (CHIP_IS_E1x(sc) && (sc->mtu > 5000)) {
6822 sc->link_params.req_fc_auto_adv = ELINK_FLOW_CTRL_TX;
6824 sc->link_params.req_fc_auto_adv = ELINK_FLOW_CTRL_BOTH;
6828 static void bnx2x_calc_fc_adv(struct bnx2x_softc *sc)
6830 uint8_t cfg_idx = bnx2x_get_link_cfg_idx(sc);
6831 switch (sc->link_vars.ieee_fc &
6832 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK) {
6833 case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_NONE:
6835 sc->port.advertising[cfg_idx] &= ~(ADVERTISED_Asym_Pause |
6839 case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH:
6840 sc->port.advertising[cfg_idx] |= (ADVERTISED_Asym_Pause |
6844 case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC:
6845 sc->port.advertising[cfg_idx] |= ADVERTISED_Asym_Pause;
6850 static uint16_t bnx2x_get_mf_speed(struct bnx2x_softc *sc)
6852 uint16_t line_speed = sc->link_vars.line_speed;
6854 uint16_t maxCfg = bnx2x_extract_max_cfg(sc,
6856 mf_info.mf_config[SC_VN
6859 /* calculate the current MAX line speed limit for the MF devices */
6861 line_speed = (line_speed * maxCfg) / 100;
6862 } else { /* SD mode */
6863 uint16_t vn_max_rate = maxCfg * 100;
6865 if (vn_max_rate < line_speed) {
6866 line_speed = vn_max_rate;
6875 bnx2x_fill_report_data(struct bnx2x_softc *sc, struct bnx2x_link_report_data *data)
6877 uint16_t line_speed = bnx2x_get_mf_speed(sc);
6879 memset(data, 0, sizeof(*data));
6881 /* fill the report data with the effective line speed */
6882 data->line_speed = line_speed;
6885 if (!sc->link_vars.link_up || (sc->flags & BNX2X_MF_FUNC_DIS)) {
6886 bnx2x_set_bit(BNX2X_LINK_REPORT_LINK_DOWN,
6887 &data->link_report_flags);
6891 if (sc->link_vars.duplex == DUPLEX_FULL) {
6892 bnx2x_set_bit(BNX2X_LINK_REPORT_FULL_DUPLEX,
6893 &data->link_report_flags);
6896 /* Rx Flow Control is ON */
6897 if (sc->link_vars.flow_ctrl & ELINK_FLOW_CTRL_RX) {
6898 bnx2x_set_bit(BNX2X_LINK_REPORT_RX_FC_ON, &data->link_report_flags);
6901 /* Tx Flow Control is ON */
6902 if (sc->link_vars.flow_ctrl & ELINK_FLOW_CTRL_TX) {
6903 bnx2x_set_bit(BNX2X_LINK_REPORT_TX_FC_ON, &data->link_report_flags);
6907 /* report link status to OS, should be called under phy_lock */
6908 static void bnx2x_link_report_locked(struct bnx2x_softc *sc)
6910 struct bnx2x_link_report_data cur_data;
6914 bnx2x_read_mf_cfg(sc);
6917 /* Read the current link report info */
6918 bnx2x_fill_report_data(sc, &cur_data);
6920 /* Don't report link down or exactly the same link status twice */
6921 if (!memcmp(&cur_data, &sc->last_reported_link, sizeof(cur_data)) ||
6922 (bnx2x_test_bit(BNX2X_LINK_REPORT_LINK_DOWN,
6923 &sc->last_reported_link.link_report_flags) &&
6924 bnx2x_test_bit(BNX2X_LINK_REPORT_LINK_DOWN,
6925 &cur_data.link_report_flags))) {
6929 PMD_DRV_LOG(INFO, sc, "Change in link status : cur_data = %lx, last_reported_link = %lx\n",
6930 cur_data.link_report_flags,
6931 sc->last_reported_link.link_report_flags);
6935 PMD_DRV_LOG(INFO, sc, "link status change count = %x\n", sc->link_cnt);
6936 /* report new link params and remember the state for the next time */
6937 (void)rte_memcpy(&sc->last_reported_link, &cur_data, sizeof(cur_data));
6939 if (bnx2x_test_bit(BNX2X_LINK_REPORT_LINK_DOWN,
6940 &cur_data.link_report_flags)) {
6941 PMD_DRV_LOG(INFO, sc, "NIC Link is Down");
6943 __rte_unused const char *duplex;
6944 __rte_unused const char *flow;
6946 if (bnx2x_test_and_clear_bit(BNX2X_LINK_REPORT_FULL_DUPLEX,
6947 &cur_data.link_report_flags)) {
6954 * Handle the FC at the end so that only these flags would be
6955 * possibly set. This way we may easily check if there is no FC
6958 if (cur_data.link_report_flags) {
6959 if (bnx2x_test_bit(BNX2X_LINK_REPORT_RX_FC_ON,
6960 &cur_data.link_report_flags) &&
6961 bnx2x_test_bit(BNX2X_LINK_REPORT_TX_FC_ON,
6962 &cur_data.link_report_flags)) {
6963 flow = "ON - receive & transmit";
6964 } else if (bnx2x_test_bit(BNX2X_LINK_REPORT_RX_FC_ON,
6965 &cur_data.link_report_flags) &&
6966 !bnx2x_test_bit(BNX2X_LINK_REPORT_TX_FC_ON,
6967 &cur_data.link_report_flags)) {
6968 flow = "ON - receive";
6969 } else if (!bnx2x_test_bit(BNX2X_LINK_REPORT_RX_FC_ON,
6970 &cur_data.link_report_flags) &&
6971 bnx2x_test_bit(BNX2X_LINK_REPORT_TX_FC_ON,
6972 &cur_data.link_report_flags)) {
6973 flow = "ON - transmit";
6975 flow = "none"; /* possible? */
6981 PMD_DRV_LOG(INFO, sc,
6982 "NIC Link is Up, %d Mbps %s duplex, Flow control: %s",
6983 cur_data.line_speed, duplex, flow);
6988 bnx2x_link_report(struct bnx2x_softc *sc)
6990 bnx2x_acquire_phy_lock(sc);
6991 bnx2x_link_report_locked(sc);
6992 bnx2x_release_phy_lock(sc);
6995 void bnx2x_link_status_update(struct bnx2x_softc *sc)
6997 if (sc->state != BNX2X_STATE_OPEN) {
7001 if (IS_PF(sc) && !CHIP_REV_IS_SLOW(sc)) {
7002 elink_link_status_update(&sc->link_params, &sc->link_vars);
7004 sc->port.supported[0] |= (ELINK_SUPPORTED_10baseT_Half |
7005 ELINK_SUPPORTED_10baseT_Full |
7006 ELINK_SUPPORTED_100baseT_Half |
7007 ELINK_SUPPORTED_100baseT_Full |
7008 ELINK_SUPPORTED_1000baseT_Full |
7009 ELINK_SUPPORTED_2500baseX_Full |
7010 ELINK_SUPPORTED_10000baseT_Full |
7011 ELINK_SUPPORTED_TP |
7012 ELINK_SUPPORTED_FIBRE |
7013 ELINK_SUPPORTED_Autoneg |
7014 ELINK_SUPPORTED_Pause |
7015 ELINK_SUPPORTED_Asym_Pause);
7016 sc->port.advertising[0] = sc->port.supported[0];
7018 sc->link_params.sc = sc;
7019 sc->link_params.port = SC_PORT(sc);
7020 sc->link_params.req_duplex[0] = DUPLEX_FULL;
7021 sc->link_params.req_flow_ctrl[0] = ELINK_FLOW_CTRL_NONE;
7022 sc->link_params.req_line_speed[0] = SPEED_10000;
7023 sc->link_params.speed_cap_mask[0] = 0x7f0000;
7024 sc->link_params.switch_cfg = ELINK_SWITCH_CFG_10G;
7026 if (CHIP_REV_IS_FPGA(sc)) {
7027 sc->link_vars.mac_type = ELINK_MAC_TYPE_EMAC;
7028 sc->link_vars.line_speed = ELINK_SPEED_1000;
7029 sc->link_vars.link_status = (LINK_STATUS_LINK_UP |
7030 LINK_STATUS_SPEED_AND_DUPLEX_1000TFD);
7032 sc->link_vars.mac_type = ELINK_MAC_TYPE_BMAC;
7033 sc->link_vars.line_speed = ELINK_SPEED_10000;
7034 sc->link_vars.link_status = (LINK_STATUS_LINK_UP |
7035 LINK_STATUS_SPEED_AND_DUPLEX_10GTFD);
7038 sc->link_vars.link_up = 1;
7040 sc->link_vars.duplex = DUPLEX_FULL;
7041 sc->link_vars.flow_ctrl = ELINK_FLOW_CTRL_NONE;
7045 NIG_REG_EGRESS_DRAIN0_MODE +
7046 sc->link_params.port * 4, 0);
7047 bnx2x_stats_handle(sc, STATS_EVENT_LINK_UP);
7048 bnx2x_link_report(sc);
7053 if (sc->link_vars.link_up) {
7054 bnx2x_stats_handle(sc, STATS_EVENT_LINK_UP);
7056 bnx2x_stats_handle(sc, STATS_EVENT_STOP);
7058 bnx2x_link_report(sc);
7060 bnx2x_link_report_locked(sc);
7061 bnx2x_stats_handle(sc, STATS_EVENT_LINK_UP);
7065 static void bnx2x_periodic_start(struct bnx2x_softc *sc)
7067 atomic_store_rel_long(&sc->periodic_flags, PERIODIC_GO);
7070 static void bnx2x_periodic_stop(struct bnx2x_softc *sc)
7072 atomic_store_rel_long(&sc->periodic_flags, PERIODIC_STOP);
7075 static int bnx2x_initial_phy_init(struct bnx2x_softc *sc, int load_mode)
7077 int rc, cfg_idx = bnx2x_get_link_cfg_idx(sc);
7078 uint16_t req_line_speed = sc->link_params.req_line_speed[cfg_idx];
7079 struct elink_params *lp = &sc->link_params;
7081 bnx2x_set_requested_fc(sc);
7083 bnx2x_acquire_phy_lock(sc);
7085 if (load_mode == LOAD_DIAG) {
7086 lp->loopback_mode = ELINK_LOOPBACK_XGXS;
7087 /* Prefer doing PHY loopback at 10G speed, if possible */
7088 if (lp->req_line_speed[cfg_idx] < ELINK_SPEED_10000) {
7089 if (lp->speed_cap_mask[cfg_idx] &
7090 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G) {
7091 lp->req_line_speed[cfg_idx] = ELINK_SPEED_10000;
7093 lp->req_line_speed[cfg_idx] = ELINK_SPEED_1000;
7098 if (load_mode == LOAD_LOOPBACK_EXT) {
7099 lp->loopback_mode = ELINK_LOOPBACK_EXT;
7102 rc = elink_phy_init(&sc->link_params, &sc->link_vars);
7104 bnx2x_release_phy_lock(sc);
7106 bnx2x_calc_fc_adv(sc);
7108 if (sc->link_vars.link_up) {
7109 bnx2x_stats_handle(sc, STATS_EVENT_LINK_UP);
7110 bnx2x_link_report(sc);
7113 if (!CHIP_REV_IS_SLOW(sc)) {
7114 bnx2x_periodic_start(sc);
7117 sc->link_params.req_line_speed[cfg_idx] = req_line_speed;
7121 /* update flags in shmem */
7123 bnx2x_update_drv_flags(struct bnx2x_softc *sc, uint32_t flags, uint32_t set)
7127 if (SHMEM2_HAS(sc, drv_flags)) {
7128 bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_DRV_FLAGS);
7129 drv_flags = SHMEM2_RD(sc, drv_flags);
7134 drv_flags &= ~flags;
7137 SHMEM2_WR(sc, drv_flags, drv_flags);
7139 bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_DRV_FLAGS);
7143 /* periodic timer callout routine, only runs when the interface is up */
7144 void bnx2x_periodic_callout(struct bnx2x_softc *sc)
7146 if ((sc->state != BNX2X_STATE_OPEN) ||
7147 (atomic_load_acq_long(&sc->periodic_flags) == PERIODIC_STOP)) {
7148 PMD_DRV_LOG(INFO, sc, "periodic callout exit (state=0x%x)",
7152 if (!CHIP_REV_IS_SLOW(sc)) {
7154 * This barrier is needed to ensure the ordering between the writing
7155 * to the sc->port.pmf in the bnx2x_nic_load() or bnx2x_pmf_update() and
7160 bnx2x_acquire_phy_lock(sc);
7161 elink_period_func(&sc->link_params, &sc->link_vars);
7162 bnx2x_release_phy_lock(sc);
7166 if (IS_PF(sc) && !BNX2X_NOMCP(sc)) {
7167 int mb_idx = SC_FW_MB_IDX(sc);
7171 ++sc->fw_drv_pulse_wr_seq;
7172 sc->fw_drv_pulse_wr_seq &= DRV_PULSE_SEQ_MASK;
7174 drv_pulse = sc->fw_drv_pulse_wr_seq;
7175 bnx2x_drv_pulse(sc);
7177 mcp_pulse = (SHMEM_RD(sc, func_mb[mb_idx].mcp_pulse_mb) &
7178 MCP_PULSE_SEQ_MASK);
7181 * The delta between driver pulse and mcp response should
7182 * be 1 (before mcp response) or 0 (after mcp response).
7184 if ((drv_pulse != mcp_pulse) &&
7185 (drv_pulse != ((mcp_pulse + 1) & MCP_PULSE_SEQ_MASK))) {
7186 /* someone lost a heartbeat... */
7187 PMD_DRV_LOG(ERR, sc,
7188 "drv_pulse (0x%x) != mcp_pulse (0x%x)",
7189 drv_pulse, mcp_pulse);
7195 /* start the controller */
7196 static __attribute__ ((noinline))
7197 int bnx2x_nic_load(struct bnx2x_softc *sc)
7200 uint32_t load_code = 0;
7203 PMD_INIT_FUNC_TRACE(sc);
7205 sc->state = BNX2X_STATE_OPENING_WAITING_LOAD;
7208 /* must be called before memory allocation and HW init */
7209 bnx2x_ilt_set_info(sc);
7212 bnx2x_set_fp_rx_buf_size(sc);
7215 if (bnx2x_alloc_mem(sc) != 0) {
7216 sc->state = BNX2X_STATE_CLOSED;
7218 goto bnx2x_nic_load_error0;
7222 if (bnx2x_alloc_fw_stats_mem(sc) != 0) {
7223 sc->state = BNX2X_STATE_CLOSED;
7225 goto bnx2x_nic_load_error0;
7229 rc = bnx2x_vf_init(sc);
7231 sc->state = BNX2X_STATE_ERROR;
7232 goto bnx2x_nic_load_error0;
7237 /* set pf load just before approaching the MCP */
7238 bnx2x_set_pf_load(sc);
7240 /* if MCP exists send load request and analyze response */
7241 if (!BNX2X_NOMCP(sc)) {
7242 /* attempt to load pf */
7243 if (bnx2x_nic_load_request(sc, &load_code) != 0) {
7244 sc->state = BNX2X_STATE_CLOSED;
7246 goto bnx2x_nic_load_error1;
7249 /* what did the MCP say? */
7250 if (bnx2x_nic_load_analyze_req(sc, load_code) != 0) {
7251 bnx2x_fw_command(sc, DRV_MSG_CODE_LOAD_DONE, 0);
7252 sc->state = BNX2X_STATE_CLOSED;
7254 goto bnx2x_nic_load_error2;
7257 PMD_DRV_LOG(INFO, sc, "Device has no MCP!");
7258 load_code = bnx2x_nic_load_no_mcp(sc);
7261 /* mark PMF if applicable */
7262 bnx2x_nic_load_pmf(sc, load_code);
7264 /* Init Function state controlling object */
7265 bnx2x_init_func_obj(sc);
7268 if (bnx2x_init_hw(sc, load_code) != 0) {
7269 PMD_DRV_LOG(NOTICE, sc, "HW init failed");
7270 bnx2x_fw_command(sc, DRV_MSG_CODE_LOAD_DONE, 0);
7271 sc->state = BNX2X_STATE_CLOSED;
7273 goto bnx2x_nic_load_error2;
7277 bnx2x_nic_init(sc, load_code);
7279 /* Init per-function objects */
7281 bnx2x_init_objs(sc);
7283 /* set AFEX default VLAN tag to an invalid value */
7284 sc->devinfo.mf_info.afex_def_vlan_tag = -1;
7286 sc->state = BNX2X_STATE_OPENING_WAITING_PORT;
7287 rc = bnx2x_func_start(sc);
7289 PMD_DRV_LOG(NOTICE, sc, "Function start failed!");
7290 bnx2x_fw_command(sc, DRV_MSG_CODE_LOAD_DONE, 0);
7291 sc->state = BNX2X_STATE_ERROR;
7292 goto bnx2x_nic_load_error3;
7295 /* send LOAD_DONE command to MCP */
7296 if (!BNX2X_NOMCP(sc)) {
7298 bnx2x_fw_command(sc, DRV_MSG_CODE_LOAD_DONE, 0);
7300 PMD_DRV_LOG(NOTICE, sc,
7301 "MCP response failure, aborting");
7302 sc->state = BNX2X_STATE_ERROR;
7304 goto bnx2x_nic_load_error3;
7309 rc = bnx2x_setup_leading(sc);
7311 PMD_DRV_LOG(NOTICE, sc, "Setup leading failed!");
7312 sc->state = BNX2X_STATE_ERROR;
7313 goto bnx2x_nic_load_error3;
7316 FOR_EACH_NONDEFAULT_ETH_QUEUE(sc, i) {
7318 rc = bnx2x_setup_queue(sc, &sc->fp[i], FALSE);
7319 else /* IS_VF(sc) */
7320 rc = bnx2x_vf_setup_queue(sc, &sc->fp[i], FALSE);
7323 PMD_DRV_LOG(NOTICE, sc, "Queue(%d) setup failed", i);
7324 sc->state = BNX2X_STATE_ERROR;
7325 goto bnx2x_nic_load_error3;
7329 rc = bnx2x_init_rss_pf(sc);
7331 PMD_DRV_LOG(NOTICE, sc, "PF RSS init failed");
7332 sc->state = BNX2X_STATE_ERROR;
7333 goto bnx2x_nic_load_error3;
7336 /* now when Clients are configured we are ready to work */
7337 sc->state = BNX2X_STATE_OPEN;
7339 /* Configure a ucast MAC */
7341 rc = bnx2x_set_eth_mac(sc, TRUE);
7342 } else { /* IS_VF(sc) */
7343 rc = bnx2x_vf_set_mac(sc, TRUE);
7347 PMD_DRV_LOG(NOTICE, sc, "Setting Ethernet MAC failed");
7348 sc->state = BNX2X_STATE_ERROR;
7349 goto bnx2x_nic_load_error3;
7353 rc = bnx2x_initial_phy_init(sc, LOAD_OPEN);
7355 sc->state = BNX2X_STATE_ERROR;
7356 goto bnx2x_nic_load_error3;
7360 sc->link_params.feature_config_flags &=
7361 ~ELINK_FEATURE_CONFIG_BOOT_FROM_SAN;
7364 switch (LOAD_OPEN) {
7370 case LOAD_LOOPBACK_EXT:
7371 sc->state = BNX2X_STATE_DIAG;
7379 bnx2x_update_drv_flags(sc, 1 << DRV_FLAGS_PORT_MASK, 0);
7381 bnx2x_link_status_update(sc);
7384 if (IS_PF(sc) && SHMEM2_HAS(sc, drv_capabilities_flag)) {
7385 /* mark driver is loaded in shmem2 */
7386 val = SHMEM2_RD(sc, drv_capabilities_flag[SC_FW_MB_IDX(sc)]);
7387 SHMEM2_WR(sc, drv_capabilities_flag[SC_FW_MB_IDX(sc)],
7389 DRV_FLAGS_CAPABILITIES_LOADED_SUPPORTED |
7390 DRV_FLAGS_CAPABILITIES_LOADED_L2));
7393 /* start fast path */
7394 /* Initialize Rx filter */
7395 bnx2x_set_rx_mode(sc);
7397 /* wait for all pending SP commands to complete */
7398 if (IS_PF(sc) && !bnx2x_wait_sp_comp(sc, ~0x0UL)) {
7399 PMD_DRV_LOG(NOTICE, sc, "Timeout waiting for all SPs to complete!");
7400 bnx2x_periodic_stop(sc);
7401 bnx2x_nic_unload(sc, UNLOAD_CLOSE, FALSE);
7405 PMD_DRV_LOG(DEBUG, sc, "NIC successfully loaded");
7409 bnx2x_nic_load_error3:
7412 bnx2x_int_disable_sync(sc, 1);
7414 /* clean out queued objects */
7415 bnx2x_squeeze_objects(sc);
7418 bnx2x_nic_load_error2:
7420 if (IS_PF(sc) && !BNX2X_NOMCP(sc)) {
7421 bnx2x_fw_command(sc, DRV_MSG_CODE_UNLOAD_REQ_WOL_MCP, 0);
7422 bnx2x_fw_command(sc, DRV_MSG_CODE_UNLOAD_DONE, 0);
7427 bnx2x_nic_load_error1:
7429 /* clear pf_load status, as it was already set */
7431 bnx2x_clear_pf_load(sc);
7434 bnx2x_nic_load_error0:
7436 bnx2x_free_fw_stats_mem(sc);
7443 * Handles controller initialization.
7445 int bnx2x_init(struct bnx2x_softc *sc)
7447 int other_engine = SC_PATH(sc) ? 0 : 1;
7448 uint8_t other_load_status, load_status;
7449 uint8_t global = FALSE;
7452 /* Check if the driver is still running and bail out if it is. */
7453 if (sc->state != BNX2X_STATE_CLOSED) {
7454 PMD_DRV_LOG(DEBUG, sc, "Init called while driver is running!");
7456 goto bnx2x_init_done;
7459 bnx2x_set_power_state(sc, PCI_PM_D0);
7462 * If parity occurred during the unload, then attentions and/or
7463 * RECOVERY_IN_PROGRESS may still be set. If so we want the first function
7464 * loaded on the current engine to complete the recovery. Parity recovery
7465 * is only relevant for PF driver.
7468 other_load_status = bnx2x_get_load_status(sc, other_engine);
7469 load_status = bnx2x_get_load_status(sc, SC_PATH(sc));
7471 if (!bnx2x_reset_is_done(sc, SC_PATH(sc)) ||
7472 bnx2x_chk_parity_attn(sc, &global, TRUE)) {
7475 * If there are attentions and they are in global blocks, set
7476 * the GLOBAL_RESET bit regardless whether it will be this
7477 * function that will complete the recovery or not.
7480 bnx2x_set_reset_global(sc);
7484 * Only the first function on the current engine should try
7485 * to recover in open. In case of attentions in global blocks
7486 * only the first in the chip should try to recover.
7489 && (!global ||!other_load_status))
7490 && bnx2x_trylock_leader_lock(sc)
7491 && !bnx2x_leader_reset(sc)) {
7492 PMD_DRV_LOG(INFO, sc,
7493 "Recovered during init");
7497 /* recovery has failed... */
7498 bnx2x_set_power_state(sc, PCI_PM_D3hot);
7500 sc->recovery_state = BNX2X_RECOVERY_FAILED;
7502 PMD_DRV_LOG(NOTICE, sc,
7503 "Recovery flow hasn't properly "
7504 "completed yet, try again later. "
7505 "If you still see this message after a "
7506 "few retries then power cycle is required.");
7509 goto bnx2x_init_done;
7514 sc->recovery_state = BNX2X_RECOVERY_DONE;
7516 rc = bnx2x_nic_load(sc);
7521 PMD_DRV_LOG(NOTICE, sc, "Initialization failed, "
7522 "stack notified driver is NOT running!");
7528 static void bnx2x_get_function_num(struct bnx2x_softc *sc)
7533 * Read the ME register to get the function number. The ME register
7534 * holds the relative-function number and absolute-function number. The
7535 * absolute-function number appears only in E2 and above. Before that
7536 * these bits always contained zero, therefore we cannot blindly use them.
7539 val = REG_RD(sc, BAR_ME_REGISTER);
7542 (uint8_t) ((val & ME_REG_PF_NUM) >> ME_REG_PF_NUM_SHIFT);
7544 (uint8_t) ((val & ME_REG_ABS_PF_NUM) >> ME_REG_ABS_PF_NUM_SHIFT) &
7547 if (CHIP_PORT_MODE(sc) == CHIP_4_PORT_MODE) {
7548 sc->pfunc_abs = ((sc->pfunc_rel << 1) | sc->path_id);
7550 sc->pfunc_abs = (sc->pfunc_rel | sc->path_id);
7553 PMD_DRV_LOG(DEBUG, sc,
7554 "Relative function %d, Absolute function %d, Path %d",
7555 sc->pfunc_rel, sc->pfunc_abs, sc->path_id);
7558 static uint32_t bnx2x_get_shmem_mf_cfg_base(struct bnx2x_softc *sc)
7560 uint32_t shmem2_size;
7562 uint32_t mf_cfg_offset_value;
7565 offset = (SHMEM_ADDR(sc, func_mb) +
7566 (MAX_FUNC_NUM * sizeof(struct drv_func_mb)));
7569 if (sc->devinfo.shmem2_base != 0) {
7570 shmem2_size = SHMEM2_RD(sc, size);
7571 if (shmem2_size > offsetof(struct shmem2_region, mf_cfg_addr)) {
7572 mf_cfg_offset_value = SHMEM2_RD(sc, mf_cfg_addr);
7573 if (SHMEM_MF_CFG_ADDR_NONE != mf_cfg_offset_value) {
7574 offset = mf_cfg_offset_value;
7582 static uint32_t bnx2x_pcie_capability_read(struct bnx2x_softc *sc, int reg)
7585 struct bnx2x_pci_cap *caps;
7587 /* ensure PCIe capability is enabled */
7588 caps = pci_find_cap(sc, PCIY_EXPRESS, BNX2X_PCI_CAP);
7590 PMD_DRV_LOG(DEBUG, sc, "Found PCIe capability: "
7591 "id=0x%04X type=0x%04X addr=0x%08X",
7592 caps->id, caps->type, caps->addr);
7593 pci_read(sc, (caps->addr + reg), &ret, 2);
7597 PMD_DRV_LOG(WARNING, sc, "PCIe capability NOT FOUND!!!");
7602 static uint8_t bnx2x_is_pcie_pending(struct bnx2x_softc *sc)
7604 return bnx2x_pcie_capability_read(sc, PCIR_EXPRESS_DEVICE_STA) &
7605 PCIM_EXP_STA_TRANSACTION_PND;
7609 * Walk the PCI capabiites list for the device to find what features are
7610 * supported. These capabilites may be enabled/disabled by firmware so it's
7611 * best to walk the list rather than make assumptions.
7613 static void bnx2x_probe_pci_caps(struct bnx2x_softc *sc)
7615 PMD_INIT_FUNC_TRACE(sc);
7617 struct bnx2x_pci_cap *caps;
7618 uint16_t link_status;
7619 #ifdef RTE_LIBRTE_BNX2X_DEBUG
7623 /* check if PCI Power Management is enabled */
7624 caps = pci_find_cap(sc, PCIY_PMG, BNX2X_PCI_CAP);
7626 PMD_DRV_LOG(DEBUG, sc, "Found PM capability: "
7627 "id=0x%04X type=0x%04X addr=0x%08X",
7628 caps->id, caps->type, caps->addr);
7630 sc->devinfo.pcie_cap_flags |= BNX2X_PM_CAPABLE_FLAG;
7631 sc->devinfo.pcie_pm_cap_reg = caps->addr;
7634 link_status = bnx2x_pcie_capability_read(sc, PCIR_EXPRESS_LINK_STA);
7636 sc->devinfo.pcie_link_speed = (link_status & PCIM_LINK_STA_SPEED);
7637 sc->devinfo.pcie_link_width =
7638 ((link_status & PCIM_LINK_STA_WIDTH) >> 4);
7640 PMD_DRV_LOG(DEBUG, sc, "PCIe link speed=%d width=%d",
7641 sc->devinfo.pcie_link_speed, sc->devinfo.pcie_link_width);
7643 sc->devinfo.pcie_cap_flags |= BNX2X_PCIE_CAPABLE_FLAG;
7645 /* check if MSI capability is enabled */
7646 caps = pci_find_cap(sc, PCIY_MSI, BNX2X_PCI_CAP);
7648 PMD_DRV_LOG(DEBUG, sc, "Found MSI capability at 0x%04x", reg);
7650 sc->devinfo.pcie_cap_flags |= BNX2X_MSI_CAPABLE_FLAG;
7651 sc->devinfo.pcie_msi_cap_reg = caps->addr;
7654 /* check if MSI-X capability is enabled */
7655 caps = pci_find_cap(sc, PCIY_MSIX, BNX2X_PCI_CAP);
7657 PMD_DRV_LOG(DEBUG, sc, "Found MSI-X capability at 0x%04x", reg);
7659 sc->devinfo.pcie_cap_flags |= BNX2X_MSIX_CAPABLE_FLAG;
7660 sc->devinfo.pcie_msix_cap_reg = caps->addr;
7664 static int bnx2x_get_shmem_mf_cfg_info_sd(struct bnx2x_softc *sc)
7666 struct bnx2x_mf_info *mf_info = &sc->devinfo.mf_info;
7669 /* get the outer vlan if we're in switch-dependent mode */
7671 val = MFCFG_RD(sc, func_mf_config[SC_ABS_FUNC(sc)].e1hov_tag);
7672 mf_info->ext_id = (uint16_t) val;
7674 mf_info->multi_vnics_mode = 1;
7676 if (!VALID_OVLAN(mf_info->ext_id)) {
7677 PMD_DRV_LOG(NOTICE, sc, "Invalid VLAN (%d)", mf_info->ext_id);
7681 /* get the capabilities */
7682 if ((mf_info->mf_config[SC_VN(sc)] & FUNC_MF_CFG_PROTOCOL_MASK) ==
7683 FUNC_MF_CFG_PROTOCOL_ISCSI) {
7684 mf_info->mf_protos_supported |= MF_PROTO_SUPPORT_ISCSI;
7685 } else if ((mf_info->mf_config[SC_VN(sc)] & FUNC_MF_CFG_PROTOCOL_MASK)
7686 == FUNC_MF_CFG_PROTOCOL_FCOE) {
7687 mf_info->mf_protos_supported |= MF_PROTO_SUPPORT_FCOE;
7689 mf_info->mf_protos_supported |= MF_PROTO_SUPPORT_ETHERNET;
7692 mf_info->vnics_per_port =
7693 (CHIP_PORT_MODE(sc) == CHIP_4_PORT_MODE) ? 2 : 4;
7698 static uint32_t bnx2x_get_shmem_ext_proto_support_flags(struct bnx2x_softc *sc)
7700 uint32_t retval = 0;
7703 val = MFCFG_RD(sc, func_ext_config[SC_ABS_FUNC(sc)].func_cfg);
7705 if (val & MACP_FUNC_CFG_FLAGS_ENABLED) {
7706 if (val & MACP_FUNC_CFG_FLAGS_ETHERNET) {
7707 retval |= MF_PROTO_SUPPORT_ETHERNET;
7709 if (val & MACP_FUNC_CFG_FLAGS_ISCSI_OFFLOAD) {
7710 retval |= MF_PROTO_SUPPORT_ISCSI;
7712 if (val & MACP_FUNC_CFG_FLAGS_FCOE_OFFLOAD) {
7713 retval |= MF_PROTO_SUPPORT_FCOE;
7720 static int bnx2x_get_shmem_mf_cfg_info_si(struct bnx2x_softc *sc)
7722 struct bnx2x_mf_info *mf_info = &sc->devinfo.mf_info;
7726 * There is no outer vlan if we're in switch-independent mode.
7727 * If the mac is valid then assume multi-function.
7730 val = MFCFG_RD(sc, func_ext_config[SC_ABS_FUNC(sc)].func_cfg);
7732 mf_info->multi_vnics_mode = ((val & MACP_FUNC_CFG_FLAGS_MASK) != 0);
7734 mf_info->mf_protos_supported =
7735 bnx2x_get_shmem_ext_proto_support_flags(sc);
7737 mf_info->vnics_per_port =
7738 (CHIP_PORT_MODE(sc) == CHIP_4_PORT_MODE) ? 2 : 4;
7743 static int bnx2x_get_shmem_mf_cfg_info_niv(struct bnx2x_softc *sc)
7745 struct bnx2x_mf_info *mf_info = &sc->devinfo.mf_info;
7747 uint32_t func_config;
7748 uint32_t niv_config;
7750 mf_info->multi_vnics_mode = 1;
7752 e1hov_tag = MFCFG_RD(sc, func_mf_config[SC_ABS_FUNC(sc)].e1hov_tag);
7753 func_config = MFCFG_RD(sc, func_mf_config[SC_ABS_FUNC(sc)].config);
7754 niv_config = MFCFG_RD(sc, func_mf_config[SC_ABS_FUNC(sc)].afex_config);
7757 (uint16_t) ((e1hov_tag & FUNC_MF_CFG_E1HOV_TAG_MASK) >>
7758 FUNC_MF_CFG_E1HOV_TAG_SHIFT);
7760 mf_info->default_vlan =
7761 (uint16_t) ((e1hov_tag & FUNC_MF_CFG_AFEX_VLAN_MASK) >>
7762 FUNC_MF_CFG_AFEX_VLAN_SHIFT);
7764 mf_info->niv_allowed_priorities =
7765 (uint8_t) ((niv_config & FUNC_MF_CFG_AFEX_COS_FILTER_MASK) >>
7766 FUNC_MF_CFG_AFEX_COS_FILTER_SHIFT);
7768 mf_info->niv_default_cos =
7769 (uint8_t) ((func_config & FUNC_MF_CFG_TRANSMIT_PRIORITY_MASK) >>
7770 FUNC_MF_CFG_TRANSMIT_PRIORITY_SHIFT);
7772 mf_info->afex_vlan_mode =
7773 ((niv_config & FUNC_MF_CFG_AFEX_VLAN_MODE_MASK) >>
7774 FUNC_MF_CFG_AFEX_VLAN_MODE_SHIFT);
7776 mf_info->niv_mba_enabled =
7777 ((niv_config & FUNC_MF_CFG_AFEX_MBA_ENABLED_MASK) >>
7778 FUNC_MF_CFG_AFEX_MBA_ENABLED_SHIFT);
7780 mf_info->mf_protos_supported =
7781 bnx2x_get_shmem_ext_proto_support_flags(sc);
7783 mf_info->vnics_per_port =
7784 (CHIP_PORT_MODE(sc) == CHIP_4_PORT_MODE) ? 2 : 4;
7789 static int bnx2x_check_valid_mf_cfg(struct bnx2x_softc *sc)
7791 struct bnx2x_mf_info *mf_info = &sc->devinfo.mf_info;
7798 /* various MF mode sanity checks... */
7800 if (mf_info->mf_config[SC_VN(sc)] & FUNC_MF_CFG_FUNC_HIDE) {
7801 PMD_DRV_LOG(NOTICE, sc,
7802 "Enumerated function %d is marked as hidden",
7807 if ((mf_info->vnics_per_port > 1) && !mf_info->multi_vnics_mode) {
7808 PMD_DRV_LOG(NOTICE, sc, "vnics_per_port=%d multi_vnics_mode=%d",
7809 mf_info->vnics_per_port, mf_info->multi_vnics_mode);
7813 if (mf_info->mf_mode == MULTI_FUNCTION_SD) {
7814 /* vnic id > 0 must have valid ovlan in switch-dependent mode */
7815 if ((SC_VN(sc) > 0) && !VALID_OVLAN(OVLAN(sc))) {
7816 PMD_DRV_LOG(NOTICE, sc, "mf_mode=SD vnic_id=%d ovlan=%d",
7817 SC_VN(sc), OVLAN(sc));
7821 if (!VALID_OVLAN(OVLAN(sc)) && mf_info->multi_vnics_mode) {
7822 PMD_DRV_LOG(NOTICE, sc,
7823 "mf_mode=SD multi_vnics_mode=%d ovlan=%d",
7824 mf_info->multi_vnics_mode, OVLAN(sc));
7829 * Verify all functions are either MF or SF mode. If MF, make sure
7830 * sure that all non-hidden functions have a valid ovlan. If SF,
7831 * make sure that all non-hidden functions have an invalid ovlan.
7833 FOREACH_ABS_FUNC_IN_PORT(sc, i) {
7834 mf_cfg1 = MFCFG_RD(sc, func_mf_config[i].config);
7835 ovlan1 = MFCFG_RD(sc, func_mf_config[i].e1hov_tag);
7836 if (!(mf_cfg1 & FUNC_MF_CFG_FUNC_HIDE) &&
7837 (((mf_info->multi_vnics_mode)
7838 && !VALID_OVLAN(ovlan1))
7839 || ((!mf_info->multi_vnics_mode)
7840 && VALID_OVLAN(ovlan1)))) {
7841 PMD_DRV_LOG(NOTICE, sc,
7842 "mf_mode=SD function %d MF config "
7843 "mismatch, multi_vnics_mode=%d ovlan=%d",
7844 i, mf_info->multi_vnics_mode,
7850 /* Verify all funcs on the same port each have a different ovlan. */
7851 FOREACH_ABS_FUNC_IN_PORT(sc, i) {
7852 mf_cfg1 = MFCFG_RD(sc, func_mf_config[i].config);
7853 ovlan1 = MFCFG_RD(sc, func_mf_config[i].e1hov_tag);
7854 /* iterate from the next function on the port to the max func */
7855 for (j = i + 2; j < MAX_FUNC_NUM; j += 2) {
7857 MFCFG_RD(sc, func_mf_config[j].config);
7859 MFCFG_RD(sc, func_mf_config[j].e1hov_tag);
7860 if (!(mf_cfg1 & FUNC_MF_CFG_FUNC_HIDE)
7861 && VALID_OVLAN(ovlan1)
7862 && !(mf_cfg2 & FUNC_MF_CFG_FUNC_HIDE)
7863 && VALID_OVLAN(ovlan2)
7864 && (ovlan1 == ovlan2)) {
7865 PMD_DRV_LOG(NOTICE, sc,
7866 "mf_mode=SD functions %d and %d "
7867 "have the same ovlan (%d)",
7874 /* MULTI_FUNCTION_SD */
7878 static int bnx2x_get_mf_cfg_info(struct bnx2x_softc *sc)
7880 struct bnx2x_mf_info *mf_info = &sc->devinfo.mf_info;
7881 uint32_t val, mac_upper;
7884 /* initialize mf_info defaults */
7885 mf_info->vnics_per_port = 1;
7886 mf_info->multi_vnics_mode = FALSE;
7887 mf_info->path_has_ovlan = FALSE;
7888 mf_info->mf_mode = SINGLE_FUNCTION;
7890 if (!CHIP_IS_MF_CAP(sc)) {
7894 if (sc->devinfo.mf_cfg_base == SHMEM_MF_CFG_ADDR_NONE) {
7895 PMD_DRV_LOG(NOTICE, sc, "Invalid mf_cfg_base!");
7899 /* get the MF mode (switch dependent / independent / single-function) */
7901 val = SHMEM_RD(sc, dev_info.shared_feature_config.config);
7903 switch (val & SHARED_FEAT_CFG_FORCE_SF_MODE_MASK) {
7904 case SHARED_FEAT_CFG_FORCE_SF_MODE_SWITCH_INDEPT:
7907 MFCFG_RD(sc, func_mf_config[SC_ABS_FUNC(sc)].mac_upper);
7909 /* check for legal upper mac bytes */
7910 if (mac_upper != FUNC_MF_CFG_UPPERMAC_DEFAULT) {
7911 mf_info->mf_mode = MULTI_FUNCTION_SI;
7913 PMD_DRV_LOG(NOTICE, sc,
7914 "Invalid config for Switch Independent mode");
7919 case SHARED_FEAT_CFG_FORCE_SF_MODE_MF_ALLOWED:
7920 case SHARED_FEAT_CFG_FORCE_SF_MODE_SPIO4:
7922 /* get outer vlan configuration */
7923 val = MFCFG_RD(sc, func_mf_config[SC_ABS_FUNC(sc)].e1hov_tag);
7925 if ((val & FUNC_MF_CFG_E1HOV_TAG_MASK) !=
7926 FUNC_MF_CFG_E1HOV_TAG_DEFAULT) {
7927 mf_info->mf_mode = MULTI_FUNCTION_SD;
7929 PMD_DRV_LOG(NOTICE, sc,
7930 "Invalid config for Switch Dependent mode");
7935 case SHARED_FEAT_CFG_FORCE_SF_MODE_FORCED_SF:
7937 /* not in MF mode, vnics_per_port=1 and multi_vnics_mode=FALSE */
7940 case SHARED_FEAT_CFG_FORCE_SF_MODE_AFEX_MODE:
7943 * Mark MF mode as NIV if MCP version includes NPAR-SD support
7944 * and the MAC address is valid.
7947 MFCFG_RD(sc, func_mf_config[SC_ABS_FUNC(sc)].mac_upper);
7949 if ((SHMEM2_HAS(sc, afex_driver_support)) &&
7950 (mac_upper != FUNC_MF_CFG_UPPERMAC_DEFAULT)) {
7951 mf_info->mf_mode = MULTI_FUNCTION_AFEX;
7953 PMD_DRV_LOG(NOTICE, sc, "Invalid config for AFEX mode");
7960 PMD_DRV_LOG(NOTICE, sc, "Unknown MF mode (0x%08x)",
7961 (val & SHARED_FEAT_CFG_FORCE_SF_MODE_MASK));
7966 /* set path mf_mode (which could be different than function mf_mode) */
7967 if (mf_info->mf_mode == MULTI_FUNCTION_SD) {
7968 mf_info->path_has_ovlan = TRUE;
7969 } else if (mf_info->mf_mode == SINGLE_FUNCTION) {
7971 * Decide on path multi vnics mode. If we're not in MF mode and in
7972 * 4-port mode, this is good enough to check vnic-0 of the other port
7975 if (CHIP_PORT_MODE(sc) == CHIP_4_PORT_MODE) {
7976 uint8_t other_port = !(PORT_ID(sc) & 1);
7977 uint8_t abs_func_other_port =
7978 (SC_PATH(sc) + (2 * other_port));
7983 [abs_func_other_port].e1hov_tag);
7985 mf_info->path_has_ovlan = VALID_OVLAN((uint16_t) val);
7989 if (mf_info->mf_mode == SINGLE_FUNCTION) {
7990 /* invalid MF config */
7991 if (SC_VN(sc) >= 1) {
7992 PMD_DRV_LOG(NOTICE, sc, "VNIC ID >= 1 in SF mode");
7999 /* get the MF configuration */
8000 mf_info->mf_config[SC_VN(sc)] =
8001 MFCFG_RD(sc, func_mf_config[SC_ABS_FUNC(sc)].config);
8003 switch (mf_info->mf_mode) {
8004 case MULTI_FUNCTION_SD:
8006 bnx2x_get_shmem_mf_cfg_info_sd(sc);
8009 case MULTI_FUNCTION_SI:
8011 bnx2x_get_shmem_mf_cfg_info_si(sc);
8014 case MULTI_FUNCTION_AFEX:
8016 bnx2x_get_shmem_mf_cfg_info_niv(sc);
8021 PMD_DRV_LOG(NOTICE, sc, "Get MF config failed (mf_mode=0x%08x)",
8026 /* get the congestion management parameters */
8029 FOREACH_ABS_FUNC_IN_PORT(sc, i) {
8030 /* get min/max bw */
8031 val = MFCFG_RD(sc, func_mf_config[i].config);
8032 mf_info->min_bw[vnic] =
8033 ((val & FUNC_MF_CFG_MIN_BW_MASK) >>
8034 FUNC_MF_CFG_MIN_BW_SHIFT);
8035 mf_info->max_bw[vnic] =
8036 ((val & FUNC_MF_CFG_MAX_BW_MASK) >>
8037 FUNC_MF_CFG_MAX_BW_SHIFT);
8041 return bnx2x_check_valid_mf_cfg(sc);
8044 static int bnx2x_get_shmem_info(struct bnx2x_softc *sc)
8047 uint32_t mac_hi, mac_lo, val;
8049 PMD_INIT_FUNC_TRACE(sc);
8052 mac_hi = mac_lo = 0;
8054 sc->link_params.sc = sc;
8055 sc->link_params.port = port;
8057 /* get the hardware config info */
8058 sc->devinfo.hw_config = SHMEM_RD(sc, dev_info.shared_hw_config.config);
8059 sc->devinfo.hw_config2 =
8060 SHMEM_RD(sc, dev_info.shared_hw_config.config2);
8062 sc->link_params.hw_led_mode =
8063 ((sc->devinfo.hw_config & SHARED_HW_CFG_LED_MODE_MASK) >>
8064 SHARED_HW_CFG_LED_MODE_SHIFT);
8066 /* get the port feature config */
8068 SHMEM_RD(sc, dev_info.port_feature_config[port].config);
8070 /* get the link params */
8071 sc->link_params.speed_cap_mask[ELINK_INT_PHY] =
8072 SHMEM_RD(sc, dev_info.port_hw_config[port].speed_capability_mask)
8073 & PORT_HW_CFG_SPEED_CAPABILITY_D0_MASK;
8074 sc->link_params.speed_cap_mask[ELINK_EXT_PHY1] =
8075 SHMEM_RD(sc, dev_info.port_hw_config[port].speed_capability_mask2)
8076 & PORT_HW_CFG_SPEED_CAPABILITY_D0_MASK;
8078 /* get the lane config */
8079 sc->link_params.lane_config =
8080 SHMEM_RD(sc, dev_info.port_hw_config[port].lane_config);
8082 /* get the link config */
8083 val = SHMEM_RD(sc, dev_info.port_feature_config[port].link_config);
8084 sc->port.link_config[ELINK_INT_PHY] = val;
8085 sc->link_params.switch_cfg = (val & PORT_FEATURE_CONNECTED_SWITCH_MASK);
8086 sc->port.link_config[ELINK_EXT_PHY1] =
8087 SHMEM_RD(sc, dev_info.port_feature_config[port].link_config2);
8089 /* get the override preemphasis flag and enable it or turn it off */
8090 val = SHMEM_RD(sc, dev_info.shared_feature_config.config);
8091 if (val & SHARED_FEAT_CFG_OVERRIDE_PREEMPHASIS_CFG_ENABLED) {
8092 sc->link_params.feature_config_flags |=
8093 ELINK_FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED;
8095 sc->link_params.feature_config_flags &=
8096 ~ELINK_FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED;
8099 /* get the initial value of the link params */
8100 sc->link_params.multi_phy_config =
8101 SHMEM_RD(sc, dev_info.port_hw_config[port].multi_phy_config);
8103 /* get external phy info */
8104 sc->port.ext_phy_config =
8105 SHMEM_RD(sc, dev_info.port_hw_config[port].external_phy_config);
8107 /* get the multifunction configuration */
8108 bnx2x_get_mf_cfg_info(sc);
8110 /* get the mac address */
8113 MFCFG_RD(sc, func_mf_config[SC_ABS_FUNC(sc)].mac_upper);
8115 MFCFG_RD(sc, func_mf_config[SC_ABS_FUNC(sc)].mac_lower);
8117 mac_hi = SHMEM_RD(sc, dev_info.port_hw_config[port].mac_upper);
8118 mac_lo = SHMEM_RD(sc, dev_info.port_hw_config[port].mac_lower);
8121 if ((mac_lo == 0) && (mac_hi == 0)) {
8122 *sc->mac_addr_str = 0;
8123 PMD_DRV_LOG(NOTICE, sc, "No Ethernet address programmed!");
8125 sc->link_params.mac_addr[0] = (uint8_t) (mac_hi >> 8);
8126 sc->link_params.mac_addr[1] = (uint8_t) (mac_hi);
8127 sc->link_params.mac_addr[2] = (uint8_t) (mac_lo >> 24);
8128 sc->link_params.mac_addr[3] = (uint8_t) (mac_lo >> 16);
8129 sc->link_params.mac_addr[4] = (uint8_t) (mac_lo >> 8);
8130 sc->link_params.mac_addr[5] = (uint8_t) (mac_lo);
8131 snprintf(sc->mac_addr_str, sizeof(sc->mac_addr_str),
8132 "%02x:%02x:%02x:%02x:%02x:%02x",
8133 sc->link_params.mac_addr[0],
8134 sc->link_params.mac_addr[1],
8135 sc->link_params.mac_addr[2],
8136 sc->link_params.mac_addr[3],
8137 sc->link_params.mac_addr[4],
8138 sc->link_params.mac_addr[5]);
8139 PMD_DRV_LOG(DEBUG, sc,
8140 "Ethernet address: %s", sc->mac_addr_str);
8146 static void bnx2x_media_detect(struct bnx2x_softc *sc)
8148 uint32_t phy_idx = bnx2x_get_cur_phy_idx(sc);
8149 switch (sc->link_params.phy[phy_idx].media_type) {
8150 case ELINK_ETH_PHY_SFPP_10G_FIBER:
8151 case ELINK_ETH_PHY_SFP_1G_FIBER:
8152 case ELINK_ETH_PHY_XFP_FIBER:
8153 case ELINK_ETH_PHY_KR:
8154 case ELINK_ETH_PHY_CX4:
8155 PMD_DRV_LOG(INFO, sc, "Found 10GBase-CX4 media.");
8156 sc->media = IFM_10G_CX4;
8158 case ELINK_ETH_PHY_DA_TWINAX:
8159 PMD_DRV_LOG(INFO, sc, "Found 10Gb Twinax media.");
8160 sc->media = IFM_10G_TWINAX;
8162 case ELINK_ETH_PHY_BASE_T:
8163 PMD_DRV_LOG(INFO, sc, "Found 10GBase-T media.");
8164 sc->media = IFM_10G_T;
8166 case ELINK_ETH_PHY_NOT_PRESENT:
8167 PMD_DRV_LOG(INFO, sc, "Media not present.");
8170 case ELINK_ETH_PHY_UNSPECIFIED:
8172 PMD_DRV_LOG(INFO, sc, "Unknown media!");
8178 #define GET_FIELD(value, fname) \
8179 (((value) & (fname##_MASK)) >> (fname##_SHIFT))
8180 #define IGU_FID(val) GET_FIELD((val), IGU_REG_MAPPING_MEMORY_FID)
8181 #define IGU_VEC(val) GET_FIELD((val), IGU_REG_MAPPING_MEMORY_VECTOR)
8183 static int bnx2x_get_igu_cam_info(struct bnx2x_softc *sc)
8185 int pfid = SC_FUNC(sc);
8188 uint8_t fid, igu_sb_cnt = 0;
8190 sc->igu_base_sb = 0xff;
8192 if (CHIP_INT_MODE_IS_BC(sc)) {
8194 igu_sb_cnt = sc->igu_sb_cnt;
8195 sc->igu_base_sb = ((CHIP_IS_MODE_4_PORT(sc) ? pfid : vn) *
8197 sc->igu_dsb_id = (E1HVN_MAX * FP_SB_MAX_E1x +
8198 (CHIP_IS_MODE_4_PORT(sc) ? pfid : vn));
8202 /* IGU in normal mode - read CAM */
8204 igu_sb_id < IGU_REG_MAPPING_MEMORY_SIZE; igu_sb_id++) {
8205 val = REG_RD(sc, IGU_REG_MAPPING_MEMORY + igu_sb_id * 4);
8206 if (!(val & IGU_REG_MAPPING_MEMORY_VALID)) {
8210 if ((fid & IGU_FID_ENCODE_IS_PF)) {
8211 if ((fid & IGU_FID_PF_NUM_MASK) != pfid) {
8214 if (IGU_VEC(val) == 0) {
8215 /* default status block */
8216 sc->igu_dsb_id = igu_sb_id;
8218 if (sc->igu_base_sb == 0xff) {
8219 sc->igu_base_sb = igu_sb_id;
8227 * Due to new PF resource allocation by MFW T7.4 and above, it's optional
8228 * that number of CAM entries will not be equal to the value advertised in
8229 * PCI. Driver should use the minimal value of both as the actual status
8232 sc->igu_sb_cnt = min(sc->igu_sb_cnt, igu_sb_cnt);
8234 if (igu_sb_cnt == 0) {
8235 PMD_DRV_LOG(ERR, sc, "CAM configuration error");
8243 * Gather various information from the device config space, the device itself,
8244 * shmem, and the user input.
8246 static int bnx2x_get_device_info(struct bnx2x_softc *sc)
8251 /* get the chip revision (chip metal comes from pci config space) */
8252 sc->devinfo.chip_id = sc->link_params.chip_id =
8253 (((REG_RD(sc, MISC_REG_CHIP_NUM) & 0xffff) << 16) |
8254 ((REG_RD(sc, MISC_REG_CHIP_REV) & 0xf) << 12) |
8255 (((REG_RD(sc, PCICFG_OFFSET + PCI_ID_VAL3) >> 24) & 0xf) << 4) |
8256 ((REG_RD(sc, MISC_REG_BOND_ID) & 0xf) << 0));
8258 /* force 57811 according to MISC register */
8259 if (REG_RD(sc, MISC_REG_CHIP_TYPE) & MISC_REG_CHIP_TYPE_57811_MASK) {
8260 if (CHIP_IS_57810(sc)) {
8261 sc->devinfo.chip_id = ((CHIP_NUM_57811 << 16) |
8263 devinfo.chip_id & 0x0000ffff));
8264 } else if (CHIP_IS_57810_MF(sc)) {
8265 sc->devinfo.chip_id = ((CHIP_NUM_57811_MF << 16) |
8267 devinfo.chip_id & 0x0000ffff));
8269 sc->devinfo.chip_id |= 0x1;
8272 PMD_DRV_LOG(DEBUG, sc,
8273 "chip_id=0x%08x (num=0x%04x rev=0x%01x metal=0x%02x bond=0x%01x)",
8274 sc->devinfo.chip_id,
8275 ((sc->devinfo.chip_id >> 16) & 0xffff),
8276 ((sc->devinfo.chip_id >> 12) & 0xf),
8277 ((sc->devinfo.chip_id >> 4) & 0xff),
8278 ((sc->devinfo.chip_id >> 0) & 0xf));
8280 val = (REG_RD(sc, 0x2874) & 0x55);
8281 if ((sc->devinfo.chip_id & 0x1) || (CHIP_IS_E1H(sc) && (val == 0x55))) {
8282 sc->flags |= BNX2X_ONE_PORT_FLAG;
8283 PMD_DRV_LOG(DEBUG, sc, "single port device");
8286 /* set the doorbell size */
8287 sc->doorbell_size = (1 << BNX2X_DB_SHIFT);
8289 /* determine whether the device is in 2 port or 4 port mode */
8290 sc->devinfo.chip_port_mode = CHIP_PORT_MODE_NONE; /* E1h */
8291 if (CHIP_IS_E2E3(sc)) {
8293 * Read port4mode_en_ovwr[0]:
8294 * If 1, four port mode is in port4mode_en_ovwr[1].
8295 * If 0, four port mode is in port4mode_en[0].
8297 val = REG_RD(sc, MISC_REG_PORT4MODE_EN_OVWR);
8299 val = ((val >> 1) & 1);
8301 val = REG_RD(sc, MISC_REG_PORT4MODE_EN);
8304 sc->devinfo.chip_port_mode =
8305 (val) ? CHIP_4_PORT_MODE : CHIP_2_PORT_MODE;
8307 PMD_DRV_LOG(DEBUG, sc, "Port mode = %s", (val) ? "4" : "2");
8310 /* get the function and path info for the device */
8311 bnx2x_get_function_num(sc);
8313 /* get the shared memory base address */
8314 sc->devinfo.shmem_base =
8315 sc->link_params.shmem_base = REG_RD(sc, MISC_REG_SHARED_MEM_ADDR);
8316 sc->devinfo.shmem2_base =
8317 REG_RD(sc, (SC_PATH(sc) ? MISC_REG_GENERIC_CR_1 :
8318 MISC_REG_GENERIC_CR_0));
8320 if (!sc->devinfo.shmem_base) {
8321 /* this should ONLY prevent upcoming shmem reads */
8322 PMD_DRV_LOG(INFO, sc, "MCP not active");
8323 sc->flags |= BNX2X_NO_MCP_FLAG;
8327 /* make sure the shared memory contents are valid */
8328 val = SHMEM_RD(sc, validity_map[SC_PORT(sc)]);
8329 if ((val & (SHR_MEM_VALIDITY_DEV_INFO | SHR_MEM_VALIDITY_MB)) !=
8330 (SHR_MEM_VALIDITY_DEV_INFO | SHR_MEM_VALIDITY_MB)) {
8331 PMD_DRV_LOG(NOTICE, sc, "Invalid SHMEM validity signature: 0x%08x",
8336 /* get the bootcode version */
8337 sc->devinfo.bc_ver = SHMEM_RD(sc, dev_info.bc_rev);
8338 snprintf(sc->devinfo.bc_ver_str,
8339 sizeof(sc->devinfo.bc_ver_str),
8341 ((sc->devinfo.bc_ver >> 24) & 0xff),
8342 ((sc->devinfo.bc_ver >> 16) & 0xff),
8343 ((sc->devinfo.bc_ver >> 8) & 0xff));
8344 PMD_DRV_LOG(INFO, sc, "Bootcode version: %s", sc->devinfo.bc_ver_str);
8346 /* get the bootcode shmem address */
8347 sc->devinfo.mf_cfg_base = bnx2x_get_shmem_mf_cfg_base(sc);
8349 /* clean indirect addresses as they're not used */
8350 pci_write_long(sc, PCICFG_GRC_ADDRESS, 0);
8352 REG_WR(sc, PXP2_REG_PGL_ADDR_88_F0, 0);
8353 REG_WR(sc, PXP2_REG_PGL_ADDR_8C_F0, 0);
8354 REG_WR(sc, PXP2_REG_PGL_ADDR_90_F0, 0);
8355 REG_WR(sc, PXP2_REG_PGL_ADDR_94_F0, 0);
8356 if (CHIP_IS_E1x(sc)) {
8357 REG_WR(sc, PXP2_REG_PGL_ADDR_88_F1, 0);
8358 REG_WR(sc, PXP2_REG_PGL_ADDR_8C_F1, 0);
8359 REG_WR(sc, PXP2_REG_PGL_ADDR_90_F1, 0);
8360 REG_WR(sc, PXP2_REG_PGL_ADDR_94_F1, 0);
8364 /* get the nvram size */
8365 val = REG_RD(sc, MCP_REG_MCPR_NVM_CFG4);
8366 sc->devinfo.flash_size =
8367 (NVRAM_1MB_SIZE << (val & MCPR_NVM_CFG4_FLASH_SIZE));
8369 bnx2x_set_power_state(sc, PCI_PM_D0);
8370 /* get various configuration parameters from shmem */
8371 bnx2x_get_shmem_info(sc);
8373 /* initialize IGU parameters */
8374 if (CHIP_IS_E1x(sc)) {
8375 sc->devinfo.int_block = INT_BLOCK_HC;
8376 sc->igu_dsb_id = DEF_SB_IGU_ID;
8377 sc->igu_base_sb = 0;
8379 sc->devinfo.int_block = INT_BLOCK_IGU;
8381 /* do not allow device reset during IGU info preocessing */
8382 bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_RESET);
8384 val = REG_RD(sc, IGU_REG_BLOCK_CONFIGURATION);
8386 if (val & IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN) {
8389 val &= ~(IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN);
8390 REG_WR(sc, IGU_REG_BLOCK_CONFIGURATION, val);
8391 REG_WR(sc, IGU_REG_RESET_MEMORIES, 0x7f);
8393 while (tout && REG_RD(sc, IGU_REG_RESET_MEMORIES)) {
8398 if (REG_RD(sc, IGU_REG_RESET_MEMORIES)) {
8399 PMD_DRV_LOG(NOTICE, sc,
8400 "FORCING IGU Normal Mode failed!!!");
8401 bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_RESET);
8406 if (val & IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN) {
8407 PMD_DRV_LOG(DEBUG, sc, "IGU Backward Compatible Mode");
8408 sc->devinfo.int_block |= INT_BLOCK_MODE_BW_COMP;
8410 PMD_DRV_LOG(DEBUG, sc, "IGU Normal Mode");
8413 rc = bnx2x_get_igu_cam_info(sc);
8415 bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_RESET);
8423 * Get base FW non-default (fast path) status block ID. This value is
8424 * used to initialize the fw_sb_id saved on the fp/queue structure to
8425 * determine the id used by the FW.
8427 if (CHIP_IS_E1x(sc)) {
8429 ((SC_PORT(sc) * FP_SB_MAX_E1x) + SC_L_ID(sc));
8432 * 57712+ - We currently use one FW SB per IGU SB (Rx and Tx of
8433 * the same queue are indicated on the same IGU SB). So we prefer
8434 * FW and IGU SBs to be the same value.
8436 sc->base_fw_ndsb = sc->igu_base_sb;
8439 elink_phy_probe(&sc->link_params);
8445 bnx2x_link_settings_supported(struct bnx2x_softc *sc, uint32_t switch_cfg)
8447 uint32_t cfg_size = 0;
8449 uint8_t port = SC_PORT(sc);
8451 /* aggregation of supported attributes of all external phys */
8452 sc->port.supported[0] = 0;
8453 sc->port.supported[1] = 0;
8455 switch (sc->link_params.num_phys) {
8457 sc->port.supported[0] =
8458 sc->link_params.phy[ELINK_INT_PHY].supported;
8462 sc->port.supported[0] =
8463 sc->link_params.phy[ELINK_EXT_PHY1].supported;
8467 if (sc->link_params.multi_phy_config &
8468 PORT_HW_CFG_PHY_SWAPPED_ENABLED) {
8469 sc->port.supported[1] =
8470 sc->link_params.phy[ELINK_EXT_PHY1].supported;
8471 sc->port.supported[0] =
8472 sc->link_params.phy[ELINK_EXT_PHY2].supported;
8474 sc->port.supported[0] =
8475 sc->link_params.phy[ELINK_EXT_PHY1].supported;
8476 sc->port.supported[1] =
8477 sc->link_params.phy[ELINK_EXT_PHY2].supported;
8483 if (!(sc->port.supported[0] || sc->port.supported[1])) {
8484 PMD_DRV_LOG(ERR, sc,
8485 "Invalid phy config in NVRAM (PHY1=0x%08x PHY2=0x%08x)",
8487 dev_info.port_hw_config
8488 [port].external_phy_config),
8490 dev_info.port_hw_config
8491 [port].external_phy_config2));
8496 sc->port.phy_addr = REG_RD(sc, MISC_REG_WC0_CTRL_PHY_ADDR);
8498 switch (switch_cfg) {
8499 case ELINK_SWITCH_CFG_1G:
8502 NIG_REG_SERDES0_CTRL_PHY_ADDR + port * 0x10);
8504 case ELINK_SWITCH_CFG_10G:
8507 NIG_REG_XGXS0_CTRL_PHY_ADDR + port * 0x18);
8510 PMD_DRV_LOG(ERR, sc,
8511 "Invalid switch config in"
8512 "link_config=0x%08x",
8513 sc->port.link_config[0]);
8518 PMD_DRV_LOG(INFO, sc, "PHY addr 0x%08x", sc->port.phy_addr);
8520 /* mask what we support according to speed_cap_mask per configuration */
8521 for (idx = 0; idx < cfg_size; idx++) {
8522 if (!(sc->link_params.speed_cap_mask[idx] &
8523 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF)) {
8524 sc->port.supported[idx] &=
8525 ~ELINK_SUPPORTED_10baseT_Half;
8528 if (!(sc->link_params.speed_cap_mask[idx] &
8529 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL)) {
8530 sc->port.supported[idx] &=
8531 ~ELINK_SUPPORTED_10baseT_Full;
8534 if (!(sc->link_params.speed_cap_mask[idx] &
8535 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF)) {
8536 sc->port.supported[idx] &=
8537 ~ELINK_SUPPORTED_100baseT_Half;
8540 if (!(sc->link_params.speed_cap_mask[idx] &
8541 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL)) {
8542 sc->port.supported[idx] &=
8543 ~ELINK_SUPPORTED_100baseT_Full;
8546 if (!(sc->link_params.speed_cap_mask[idx] &
8547 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) {
8548 sc->port.supported[idx] &=
8549 ~ELINK_SUPPORTED_1000baseT_Full;
8552 if (!(sc->link_params.speed_cap_mask[idx] &
8553 PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G)) {
8554 sc->port.supported[idx] &=
8555 ~ELINK_SUPPORTED_2500baseX_Full;
8558 if (!(sc->link_params.speed_cap_mask[idx] &
8559 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) {
8560 sc->port.supported[idx] &=
8561 ~ELINK_SUPPORTED_10000baseT_Full;
8564 if (!(sc->link_params.speed_cap_mask[idx] &
8565 PORT_HW_CFG_SPEED_CAPABILITY_D0_20G)) {
8566 sc->port.supported[idx] &=
8567 ~ELINK_SUPPORTED_20000baseKR2_Full;
8571 PMD_DRV_LOG(INFO, sc, "PHY supported 0=0x%08x 1=0x%08x",
8572 sc->port.supported[0], sc->port.supported[1]);
8575 static void bnx2x_link_settings_requested(struct bnx2x_softc *sc)
8577 uint32_t link_config;
8579 uint32_t cfg_size = 0;
8581 sc->port.advertising[0] = 0;
8582 sc->port.advertising[1] = 0;
8584 switch (sc->link_params.num_phys) {
8594 for (idx = 0; idx < cfg_size; idx++) {
8595 sc->link_params.req_duplex[idx] = DUPLEX_FULL;
8596 link_config = sc->port.link_config[idx];
8598 switch (link_config & PORT_FEATURE_LINK_SPEED_MASK) {
8599 case PORT_FEATURE_LINK_SPEED_AUTO:
8600 if (sc->port.supported[idx] & ELINK_SUPPORTED_Autoneg) {
8601 sc->link_params.req_line_speed[idx] =
8602 ELINK_SPEED_AUTO_NEG;
8603 sc->port.advertising[idx] |=
8604 sc->port.supported[idx];
8605 if (sc->link_params.phy[ELINK_EXT_PHY1].type ==
8606 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84833)
8607 sc->port.advertising[idx] |=
8608 (ELINK_SUPPORTED_100baseT_Half |
8609 ELINK_SUPPORTED_100baseT_Full);
8611 /* force 10G, no AN */
8612 sc->link_params.req_line_speed[idx] =
8614 sc->port.advertising[idx] |=
8615 (ADVERTISED_10000baseT_Full |
8621 case PORT_FEATURE_LINK_SPEED_10M_FULL:
8623 port.supported[idx] & ELINK_SUPPORTED_10baseT_Full)
8625 sc->link_params.req_line_speed[idx] =
8627 sc->port.advertising[idx] |=
8628 (ADVERTISED_10baseT_Full | ADVERTISED_TP);
8630 PMD_DRV_LOG(ERR, sc,
8631 "Invalid NVRAM config link_config=0x%08x "
8632 "speed_cap_mask=0x%08x",
8635 link_params.speed_cap_mask[idx]);
8640 case PORT_FEATURE_LINK_SPEED_10M_HALF:
8642 port.supported[idx] & ELINK_SUPPORTED_10baseT_Half)
8644 sc->link_params.req_line_speed[idx] =
8646 sc->link_params.req_duplex[idx] = DUPLEX_HALF;
8647 sc->port.advertising[idx] |=
8648 (ADVERTISED_10baseT_Half | ADVERTISED_TP);
8650 PMD_DRV_LOG(ERR, sc,
8651 "Invalid NVRAM config link_config=0x%08x "
8652 "speed_cap_mask=0x%08x",
8655 link_params.speed_cap_mask[idx]);
8660 case PORT_FEATURE_LINK_SPEED_100M_FULL:
8662 port.supported[idx] & ELINK_SUPPORTED_100baseT_Full)
8664 sc->link_params.req_line_speed[idx] =
8666 sc->port.advertising[idx] |=
8667 (ADVERTISED_100baseT_Full | ADVERTISED_TP);
8669 PMD_DRV_LOG(ERR, sc,
8670 "Invalid NVRAM config link_config=0x%08x "
8671 "speed_cap_mask=0x%08x",
8674 link_params.speed_cap_mask[idx]);
8679 case PORT_FEATURE_LINK_SPEED_100M_HALF:
8681 port.supported[idx] & ELINK_SUPPORTED_100baseT_Half)
8683 sc->link_params.req_line_speed[idx] =
8685 sc->link_params.req_duplex[idx] = DUPLEX_HALF;
8686 sc->port.advertising[idx] |=
8687 (ADVERTISED_100baseT_Half | ADVERTISED_TP);
8689 PMD_DRV_LOG(ERR, sc,
8690 "Invalid NVRAM config link_config=0x%08x "
8691 "speed_cap_mask=0x%08x",
8694 link_params.speed_cap_mask[idx]);
8699 case PORT_FEATURE_LINK_SPEED_1G:
8700 if (sc->port.supported[idx] &
8701 ELINK_SUPPORTED_1000baseT_Full) {
8702 sc->link_params.req_line_speed[idx] =
8704 sc->port.advertising[idx] |=
8705 (ADVERTISED_1000baseT_Full | ADVERTISED_TP);
8707 PMD_DRV_LOG(ERR, sc,
8708 "Invalid NVRAM config link_config=0x%08x "
8709 "speed_cap_mask=0x%08x",
8712 link_params.speed_cap_mask[idx]);
8717 case PORT_FEATURE_LINK_SPEED_2_5G:
8718 if (sc->port.supported[idx] &
8719 ELINK_SUPPORTED_2500baseX_Full) {
8720 sc->link_params.req_line_speed[idx] =
8722 sc->port.advertising[idx] |=
8723 (ADVERTISED_2500baseX_Full | ADVERTISED_TP);
8725 PMD_DRV_LOG(ERR, sc,
8726 "Invalid NVRAM config link_config=0x%08x "
8727 "speed_cap_mask=0x%08x",
8730 link_params.speed_cap_mask[idx]);
8735 case PORT_FEATURE_LINK_SPEED_10G_CX4:
8736 if (sc->port.supported[idx] &
8737 ELINK_SUPPORTED_10000baseT_Full) {
8738 sc->link_params.req_line_speed[idx] =
8740 sc->port.advertising[idx] |=
8741 (ADVERTISED_10000baseT_Full |
8744 PMD_DRV_LOG(ERR, sc,
8745 "Invalid NVRAM config link_config=0x%08x "
8746 "speed_cap_mask=0x%08x",
8749 link_params.speed_cap_mask[idx]);
8754 case PORT_FEATURE_LINK_SPEED_20G:
8755 sc->link_params.req_line_speed[idx] = ELINK_SPEED_20000;
8759 PMD_DRV_LOG(ERR, sc,
8760 "Invalid NVRAM config link_config=0x%08x "
8761 "speed_cap_mask=0x%08x", link_config,
8762 sc->link_params.speed_cap_mask[idx]);
8763 sc->link_params.req_line_speed[idx] =
8764 ELINK_SPEED_AUTO_NEG;
8765 sc->port.advertising[idx] = sc->port.supported[idx];
8769 sc->link_params.req_flow_ctrl[idx] =
8770 (link_config & PORT_FEATURE_FLOW_CONTROL_MASK);
8772 if (sc->link_params.req_flow_ctrl[idx] == ELINK_FLOW_CTRL_AUTO) {
8775 port.supported[idx] & ELINK_SUPPORTED_Autoneg)) {
8776 sc->link_params.req_flow_ctrl[idx] =
8777 ELINK_FLOW_CTRL_NONE;
8779 bnx2x_set_requested_fc(sc);
8785 static void bnx2x_get_phy_info(struct bnx2x_softc *sc)
8787 uint8_t port = SC_PORT(sc);
8790 PMD_INIT_FUNC_TRACE(sc);
8792 /* shmem data already read in bnx2x_get_shmem_info() */
8794 bnx2x_link_settings_supported(sc, sc->link_params.switch_cfg);
8795 bnx2x_link_settings_requested(sc);
8797 /* configure link feature according to nvram value */
8799 (((SHMEM_RD(sc, dev_info.port_feature_config[port].eee_power_mode))
8800 & PORT_FEAT_CFG_EEE_POWER_MODE_MASK) >>
8801 PORT_FEAT_CFG_EEE_POWER_MODE_SHIFT);
8802 if (eee_mode != PORT_FEAT_CFG_EEE_POWER_MODE_DISABLED) {
8803 sc->link_params.eee_mode = (ELINK_EEE_MODE_ADV_LPI |
8804 ELINK_EEE_MODE_ENABLE_LPI |
8805 ELINK_EEE_MODE_OUTPUT_TIME);
8807 sc->link_params.eee_mode = 0;
8810 /* get the media type */
8811 bnx2x_media_detect(sc);
8814 static void bnx2x_set_modes_bitmap(struct bnx2x_softc *sc)
8816 uint32_t flags = MODE_ASIC | MODE_PORT2;
8818 if (CHIP_IS_E2(sc)) {
8820 } else if (CHIP_IS_E3(sc)) {
8822 if (CHIP_REV(sc) == CHIP_REV_Ax) {
8823 flags |= MODE_E3_A0;
8824 } else { /*if (CHIP_REV(sc) == CHIP_REV_Bx) */
8826 flags |= MODE_E3_B0 | MODE_COS3;
8832 switch (sc->devinfo.mf_info.mf_mode) {
8833 case MULTI_FUNCTION_SD:
8834 flags |= MODE_MF_SD;
8836 case MULTI_FUNCTION_SI:
8837 flags |= MODE_MF_SI;
8839 case MULTI_FUNCTION_AFEX:
8840 flags |= MODE_MF_AFEX;
8847 #if defined(__LITTLE_ENDIAN)
8848 flags |= MODE_LITTLE_ENDIAN;
8849 #else /* __BIG_ENDIAN */
8850 flags |= MODE_BIG_ENDIAN;
8853 INIT_MODE_FLAGS(sc) = flags;
8856 int bnx2x_alloc_hsi_mem(struct bnx2x_softc *sc)
8858 struct bnx2x_fastpath *fp;
8863 /************************/
8864 /* DEFAULT STATUS BLOCK */
8865 /************************/
8867 if (bnx2x_dma_alloc(sc, sizeof(struct host_sp_status_block),
8868 &sc->def_sb_dma, "def_sb",
8869 RTE_CACHE_LINE_SIZE) != 0) {
8874 (struct host_sp_status_block *)sc->def_sb_dma.vaddr;
8879 if (bnx2x_dma_alloc(sc, BNX2X_PAGE_SIZE,
8880 &sc->eq_dma, "ev_queue",
8881 RTE_CACHE_LINE_SIZE) != 0) {
8886 sc->eq = (union event_ring_elem *)sc->eq_dma.vaddr;
8892 if (bnx2x_dma_alloc(sc, sizeof(struct bnx2x_slowpath),
8894 RTE_CACHE_LINE_SIZE) != 0) {
8900 sc->sp = (struct bnx2x_slowpath *)sc->sp_dma.vaddr;
8902 /*******************/
8903 /* SLOW PATH QUEUE */
8904 /*******************/
8906 if (bnx2x_dma_alloc(sc, BNX2X_PAGE_SIZE,
8907 &sc->spq_dma, "sp_queue",
8908 RTE_CACHE_LINE_SIZE) != 0) {
8915 sc->spq = (struct eth_spe *)sc->spq_dma.vaddr;
8917 /***************************/
8918 /* FW DECOMPRESSION BUFFER */
8919 /***************************/
8921 if (bnx2x_dma_alloc(sc, FW_BUF_SIZE, &sc->gz_buf_dma,
8922 "fw_buf", RTE_CACHE_LINE_SIZE) != 0) {
8930 sc->gz_buf = (void *)sc->gz_buf_dma.vaddr;
8937 /* allocate DMA memory for each fastpath structure */
8938 for (i = 0; i < sc->num_queues; i++) {
8943 /*******************/
8944 /* FP STATUS BLOCK */
8945 /*******************/
8947 snprintf(buf, sizeof(buf), "fp_%d_sb", i);
8948 if (bnx2x_dma_alloc(sc, sizeof(union bnx2x_host_hc_status_block),
8949 &fp->sb_dma, buf, RTE_CACHE_LINE_SIZE) != 0) {
8950 PMD_DRV_LOG(NOTICE, sc, "Failed to alloc %s", buf);
8953 if (CHIP_IS_E2E3(sc)) {
8954 fp->status_block.e2_sb =
8955 (struct host_hc_status_block_e2 *)
8958 fp->status_block.e1x_sb =
8959 (struct host_hc_status_block_e1x *)
8968 void bnx2x_free_hsi_mem(struct bnx2x_softc *sc)
8970 struct bnx2x_fastpath *fp;
8973 for (i = 0; i < sc->num_queues; i++) {
8976 /*******************/
8977 /* FP STATUS BLOCK */
8978 /*******************/
8980 memset(&fp->status_block, 0, sizeof(fp->status_block));
8983 /***************************/
8984 /* FW DECOMPRESSION BUFFER */
8985 /***************************/
8989 /*******************/
8990 /* SLOW PATH QUEUE */
8991 /*******************/
9007 /************************/
9008 /* DEFAULT STATUS BLOCK */
9009 /************************/
9016 * Previous driver DMAE transaction may have occurred when pre-boot stage
9017 * ended and boot began. This would invalidate the addresses of the
9018 * transaction, resulting in was-error bit set in the PCI causing all
9019 * hw-to-host PCIe transactions to timeout. If this happened we want to clear
9020 * the interrupt which detected this from the pglueb and the was-done bit
9022 static void bnx2x_prev_interrupted_dmae(struct bnx2x_softc *sc)
9026 if (!CHIP_IS_E1x(sc)) {
9027 val = REG_RD(sc, PGLUE_B_REG_PGLUE_B_INT_STS);
9028 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_WAS_ERROR_ATTN) {
9029 REG_WR(sc, PGLUE_B_REG_WAS_ERROR_PF_7_0_CLR,
9035 static int bnx2x_prev_mcp_done(struct bnx2x_softc *sc)
9037 uint32_t rc = bnx2x_fw_command(sc, DRV_MSG_CODE_UNLOAD_DONE,
9038 DRV_MSG_CODE_UNLOAD_SKIP_LINK_RESET);
9040 PMD_DRV_LOG(NOTICE, sc, "MCP response failure, aborting");
9047 static struct bnx2x_prev_list_node *bnx2x_prev_path_get_entry(struct bnx2x_softc *sc)
9049 struct bnx2x_prev_list_node *tmp;
9051 LIST_FOREACH(tmp, &bnx2x_prev_list, node) {
9052 if ((sc->pcie_bus == tmp->bus) &&
9053 (sc->pcie_device == tmp->slot) &&
9054 (SC_PATH(sc) == tmp->path)) {
9062 static uint8_t bnx2x_prev_is_path_marked(struct bnx2x_softc *sc)
9064 struct bnx2x_prev_list_node *tmp;
9067 rte_spinlock_lock(&bnx2x_prev_mtx);
9069 tmp = bnx2x_prev_path_get_entry(sc);
9072 PMD_DRV_LOG(DEBUG, sc,
9073 "Path %d/%d/%d was marked by AER",
9074 sc->pcie_bus, sc->pcie_device, SC_PATH(sc));
9077 PMD_DRV_LOG(DEBUG, sc,
9078 "Path %d/%d/%d was already cleaned from previous drivers",
9079 sc->pcie_bus, sc->pcie_device, SC_PATH(sc));
9083 rte_spinlock_unlock(&bnx2x_prev_mtx);
9088 static int bnx2x_prev_mark_path(struct bnx2x_softc *sc, uint8_t after_undi)
9090 struct bnx2x_prev_list_node *tmp;
9092 rte_spinlock_lock(&bnx2x_prev_mtx);
9094 /* Check whether the entry for this path already exists */
9095 tmp = bnx2x_prev_path_get_entry(sc);
9098 PMD_DRV_LOG(DEBUG, sc,
9099 "Re-marking AER in path %d/%d/%d",
9100 sc->pcie_bus, sc->pcie_device, SC_PATH(sc));
9102 PMD_DRV_LOG(DEBUG, sc,
9103 "Removing AER indication from path %d/%d/%d",
9104 sc->pcie_bus, sc->pcie_device, SC_PATH(sc));
9108 rte_spinlock_unlock(&bnx2x_prev_mtx);
9112 rte_spinlock_unlock(&bnx2x_prev_mtx);
9114 /* Create an entry for this path and add it */
9115 tmp = rte_malloc("", sizeof(struct bnx2x_prev_list_node),
9116 RTE_CACHE_LINE_SIZE);
9118 PMD_DRV_LOG(NOTICE, sc, "Failed to allocate 'bnx2x_prev_list_node'");
9122 tmp->bus = sc->pcie_bus;
9123 tmp->slot = sc->pcie_device;
9124 tmp->path = SC_PATH(sc);
9126 tmp->undi = after_undi ? (1 << SC_PORT(sc)) : 0;
9128 rte_spinlock_lock(&bnx2x_prev_mtx);
9130 LIST_INSERT_HEAD(&bnx2x_prev_list, tmp, node);
9132 rte_spinlock_unlock(&bnx2x_prev_mtx);
9137 static int bnx2x_do_flr(struct bnx2x_softc *sc)
9141 /* only E2 and onwards support FLR */
9142 if (CHIP_IS_E1x(sc)) {
9143 PMD_DRV_LOG(WARNING, sc, "FLR not supported in E1H");
9147 /* only bootcode REQ_BC_VER_4_INITIATE_FLR and onwards support flr */
9148 if (sc->devinfo.bc_ver < REQ_BC_VER_4_INITIATE_FLR) {
9149 PMD_DRV_LOG(WARNING, sc,
9150 "FLR not supported by BC_VER: 0x%08x",
9151 sc->devinfo.bc_ver);
9155 /* Wait for Transaction Pending bit clean */
9156 for (i = 0; i < 4; i++) {
9158 DELAY(((1 << (i - 1)) * 100) * 1000);
9161 if (!bnx2x_is_pcie_pending(sc)) {
9166 PMD_DRV_LOG(NOTICE, sc, "PCIE transaction is not cleared, "
9167 "proceeding with reset anyway");
9170 bnx2x_fw_command(sc, DRV_MSG_CODE_INITIATE_FLR, 0);
9175 struct bnx2x_mac_vals {
9183 uint32_t bmac_val[2];
9187 bnx2x_prev_unload_close_mac(struct bnx2x_softc *sc, struct bnx2x_mac_vals *vals)
9189 uint32_t val, base_addr, offset, mask, reset_reg;
9190 uint8_t mac_stopped = FALSE;
9191 uint8_t port = SC_PORT(sc);
9192 uint32_t wb_data[2];
9194 /* reset addresses as they also mark which values were changed */
9195 vals->bmac_addr = 0;
9196 vals->umac_addr = 0;
9197 vals->xmac_addr = 0;
9198 vals->emac_addr = 0;
9200 reset_reg = REG_RD(sc, MISC_REG_RESET_REG_2);
9202 if (!CHIP_IS_E3(sc)) {
9203 val = REG_RD(sc, NIG_REG_BMAC0_REGS_OUT_EN + port * 4);
9204 mask = MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port;
9205 if ((mask & reset_reg) && val) {
9206 base_addr = SC_PORT(sc) ? NIG_REG_INGRESS_BMAC1_MEM
9207 : NIG_REG_INGRESS_BMAC0_MEM;
9208 offset = CHIP_IS_E2(sc) ? BIGMAC2_REGISTER_BMAC_CONTROL
9209 : BIGMAC_REGISTER_BMAC_CONTROL;
9212 * use rd/wr since we cannot use dmae. This is safe
9213 * since MCP won't access the bus due to the request
9214 * to unload, and no function on the path can be
9215 * loaded at this time.
9217 wb_data[0] = REG_RD(sc, base_addr + offset);
9218 wb_data[1] = REG_RD(sc, base_addr + offset + 0x4);
9219 vals->bmac_addr = base_addr + offset;
9220 vals->bmac_val[0] = wb_data[0];
9221 vals->bmac_val[1] = wb_data[1];
9222 wb_data[0] &= ~ELINK_BMAC_CONTROL_RX_ENABLE;
9223 REG_WR(sc, vals->bmac_addr, wb_data[0]);
9224 REG_WR(sc, vals->bmac_addr + 0x4, wb_data[1]);
9227 vals->emac_addr = NIG_REG_NIG_EMAC0_EN + SC_PORT(sc) * 4;
9228 vals->emac_val = REG_RD(sc, vals->emac_addr);
9229 REG_WR(sc, vals->emac_addr, 0);
9232 if (reset_reg & MISC_REGISTERS_RESET_REG_2_XMAC) {
9233 base_addr = SC_PORT(sc) ? GRCBASE_XMAC1 : GRCBASE_XMAC0;
9234 val = REG_RD(sc, base_addr + XMAC_REG_PFC_CTRL_HI);
9235 REG_WR(sc, base_addr + XMAC_REG_PFC_CTRL_HI,
9237 REG_WR(sc, base_addr + XMAC_REG_PFC_CTRL_HI,
9239 vals->xmac_addr = base_addr + XMAC_REG_CTRL;
9240 vals->xmac_val = REG_RD(sc, vals->xmac_addr);
9241 REG_WR(sc, vals->xmac_addr, 0);
9245 mask = MISC_REGISTERS_RESET_REG_2_UMAC0 << port;
9246 if (mask & reset_reg) {
9247 base_addr = SC_PORT(sc) ? GRCBASE_UMAC1 : GRCBASE_UMAC0;
9248 vals->umac_addr = base_addr + UMAC_REG_COMMAND_CONFIG;
9249 vals->umac_val = REG_RD(sc, vals->umac_addr);
9250 REG_WR(sc, vals->umac_addr, 0);
9260 #define BNX2X_PREV_UNDI_PROD_ADDR(p) (BAR_TSTRORM_INTMEM + 0x1508 + ((p) << 4))
9261 #define BNX2X_PREV_UNDI_RCQ(val) ((val) & 0xffff)
9262 #define BNX2X_PREV_UNDI_BD(val) ((val) >> 16 & 0xffff)
9263 #define BNX2X_PREV_UNDI_PROD(rcq, bd) ((bd) << 16 | (rcq))
9266 bnx2x_prev_unload_undi_inc(struct bnx2x_softc *sc, uint8_t port, uint8_t inc)
9269 uint32_t tmp_reg = REG_RD(sc, BNX2X_PREV_UNDI_PROD_ADDR(port));
9271 rcq = BNX2X_PREV_UNDI_RCQ(tmp_reg) + inc;
9272 bd = BNX2X_PREV_UNDI_BD(tmp_reg) + inc;
9274 tmp_reg = BNX2X_PREV_UNDI_PROD(rcq, bd);
9275 REG_WR(sc, BNX2X_PREV_UNDI_PROD_ADDR(port), tmp_reg);
9278 static int bnx2x_prev_unload_common(struct bnx2x_softc *sc)
9280 uint32_t reset_reg, tmp_reg = 0, rc;
9281 uint8_t prev_undi = FALSE;
9282 struct bnx2x_mac_vals mac_vals;
9283 uint32_t timer_count = 1000;
9287 * It is possible a previous function received 'common' answer,
9288 * but hasn't loaded yet, therefore creating a scenario of
9289 * multiple functions receiving 'common' on the same path.
9291 memset(&mac_vals, 0, sizeof(mac_vals));
9293 if (bnx2x_prev_is_path_marked(sc)) {
9294 return bnx2x_prev_mcp_done(sc);
9297 reset_reg = REG_RD(sc, MISC_REG_RESET_REG_1);
9299 /* Reset should be performed after BRB is emptied */
9300 if (reset_reg & MISC_REGISTERS_RESET_REG_1_RST_BRB1) {
9301 /* Close the MAC Rx to prevent BRB from filling up */
9302 bnx2x_prev_unload_close_mac(sc, &mac_vals);
9304 /* close LLH filters towards the BRB */
9305 elink_set_rx_filter(&sc->link_params, 0);
9308 * Check if the UNDI driver was previously loaded.
9309 * UNDI driver initializes CID offset for normal bell to 0x7
9311 if (reset_reg & MISC_REGISTERS_RESET_REG_1_RST_DORQ) {
9312 tmp_reg = REG_RD(sc, DORQ_REG_NORM_CID_OFST);
9313 if (tmp_reg == 0x7) {
9314 PMD_DRV_LOG(DEBUG, sc, "UNDI previously loaded");
9316 /* clear the UNDI indication */
9317 REG_WR(sc, DORQ_REG_NORM_CID_OFST, 0);
9318 /* clear possible idle check errors */
9319 REG_RD(sc, NIG_REG_NIG_INT_STS_CLR_0);
9323 /* wait until BRB is empty */
9324 tmp_reg = REG_RD(sc, BRB1_REG_NUM_OF_FULL_BLOCKS);
9325 while (timer_count) {
9328 tmp_reg = REG_RD(sc, BRB1_REG_NUM_OF_FULL_BLOCKS);
9333 PMD_DRV_LOG(DEBUG, sc, "BRB still has 0x%08x", tmp_reg);
9335 /* reset timer as long as BRB actually gets emptied */
9336 if (prev_brb > tmp_reg) {
9342 /* If UNDI resides in memory, manually increment it */
9344 bnx2x_prev_unload_undi_inc(sc, SC_PORT(sc), 1);
9351 PMD_DRV_LOG(NOTICE, sc, "Failed to empty BRB");
9355 /* No packets are in the pipeline, path is ready for reset */
9356 bnx2x_reset_common(sc);
9358 if (mac_vals.xmac_addr) {
9359 REG_WR(sc, mac_vals.xmac_addr, mac_vals.xmac_val);
9361 if (mac_vals.umac_addr) {
9362 REG_WR(sc, mac_vals.umac_addr, mac_vals.umac_val);
9364 if (mac_vals.emac_addr) {
9365 REG_WR(sc, mac_vals.emac_addr, mac_vals.emac_val);
9367 if (mac_vals.bmac_addr) {
9368 REG_WR(sc, mac_vals.bmac_addr, mac_vals.bmac_val[0]);
9369 REG_WR(sc, mac_vals.bmac_addr + 4, mac_vals.bmac_val[1]);
9372 rc = bnx2x_prev_mark_path(sc, prev_undi);
9374 bnx2x_prev_mcp_done(sc);
9378 return bnx2x_prev_mcp_done(sc);
9381 static int bnx2x_prev_unload_uncommon(struct bnx2x_softc *sc)
9385 /* Test if previous unload process was already finished for this path */
9386 if (bnx2x_prev_is_path_marked(sc)) {
9387 return bnx2x_prev_mcp_done(sc);
9391 * If function has FLR capabilities, and existing FW version matches
9392 * the one required, then FLR will be sufficient to clean any residue
9393 * left by previous driver
9395 rc = bnx2x_nic_load_analyze_req(sc, FW_MSG_CODE_DRV_LOAD_FUNCTION);
9397 /* fw version is good */
9398 rc = bnx2x_do_flr(sc);
9402 /* FLR was performed */
9406 PMD_DRV_LOG(INFO, sc, "Could not FLR");
9408 /* Close the MCP request, return failure */
9409 rc = bnx2x_prev_mcp_done(sc);
9411 rc = BNX2X_PREV_WAIT_NEEDED;
9417 static int bnx2x_prev_unload(struct bnx2x_softc *sc)
9419 int time_counter = 10;
9420 uint32_t fw, hw_lock_reg, hw_lock_val;
9423 PMD_INIT_FUNC_TRACE(sc);
9426 * Clear HW from errors which may have resulted from an interrupted
9429 bnx2x_prev_interrupted_dmae(sc);
9431 /* Release previously held locks */
9432 hw_lock_reg = (SC_FUNC(sc) <= 5) ?
9433 (MISC_REG_DRIVER_CONTROL_1 + SC_FUNC(sc) * 8) :
9434 (MISC_REG_DRIVER_CONTROL_7 + (SC_FUNC(sc) - 6) * 8);
9436 hw_lock_val = (REG_RD(sc, hw_lock_reg));
9438 if (hw_lock_val & HW_LOCK_RESOURCE_NVRAM) {
9439 PMD_DRV_LOG(DEBUG, sc, "Releasing previously held NVRAM lock\n");
9440 REG_WR(sc, MCP_REG_MCPR_NVM_SW_ARB,
9441 (MCPR_NVM_SW_ARB_ARB_REQ_CLR1 << SC_PORT(sc)));
9443 PMD_DRV_LOG(DEBUG, sc, "Releasing previously held HW lock\n");
9444 REG_WR(sc, hw_lock_reg, 0xffffffff);
9447 if (MCPR_ACCESS_LOCK_LOCK & REG_RD(sc, MCP_REG_MCPR_ACCESS_LOCK)) {
9448 PMD_DRV_LOG(DEBUG, sc, "Releasing previously held ALR\n");
9449 REG_WR(sc, MCP_REG_MCPR_ACCESS_LOCK, 0);
9453 /* Lock MCP using an unload request */
9454 fw = bnx2x_fw_command(sc, DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS, 0);
9456 PMD_DRV_LOG(NOTICE, sc, "MCP response failure, aborting");
9461 if (fw == FW_MSG_CODE_DRV_UNLOAD_COMMON) {
9462 rc = bnx2x_prev_unload_common(sc);
9466 /* non-common reply from MCP might require looping */
9467 rc = bnx2x_prev_unload_uncommon(sc);
9468 if (rc != BNX2X_PREV_WAIT_NEEDED) {
9473 } while (--time_counter);
9475 if (!time_counter || rc) {
9476 PMD_DRV_LOG(NOTICE, sc, "Failed to unload previous driver!");
9484 bnx2x_dcbx_set_state(struct bnx2x_softc *sc, uint8_t dcb_on, uint32_t dcbx_enabled)
9486 if (!CHIP_IS_E1x(sc)) {
9487 sc->dcb_state = dcb_on;
9488 sc->dcbx_enabled = dcbx_enabled;
9490 sc->dcb_state = FALSE;
9491 sc->dcbx_enabled = BNX2X_DCBX_ENABLED_INVALID;
9493 PMD_DRV_LOG(DEBUG, sc,
9494 "DCB state [%s:%s]",
9495 dcb_on ? "ON" : "OFF",
9496 (dcbx_enabled == BNX2X_DCBX_ENABLED_OFF) ? "user-mode" :
9498 BNX2X_DCBX_ENABLED_ON_NEG_OFF) ? "on-chip static"
9500 BNX2X_DCBX_ENABLED_ON_NEG_ON) ?
9501 "on-chip with negotiation" : "invalid");
9504 static int bnx2x_set_qm_cid_count(struct bnx2x_softc *sc)
9506 int cid_count = BNX2X_L2_MAX_CID(sc);
9508 if (CNIC_SUPPORT(sc)) {
9509 cid_count += CNIC_CID_MAX;
9512 return roundup(cid_count, QM_CID_ROUND);
9515 static void bnx2x_init_multi_cos(struct bnx2x_softc *sc)
9519 uint32_t pri_map = 0;
9521 for (pri = 0; pri < BNX2X_MAX_PRIORITY; pri++) {
9522 cos = ((pri_map & (0xf << (pri * 4))) >> (pri * 4));
9523 if (cos < sc->max_cos) {
9524 sc->prio_to_cos[pri] = cos;
9526 PMD_DRV_LOG(WARNING, sc,
9527 "Invalid COS %d for priority %d "
9528 "(max COS is %d), setting to 0", cos, pri,
9530 sc->prio_to_cos[pri] = 0;
9535 static int bnx2x_pci_get_caps(struct bnx2x_softc *sc)
9542 struct bnx2x_pci_cap *cap;
9544 cap = sc->pci_caps = rte_zmalloc("caps", sizeof(struct bnx2x_pci_cap),
9545 RTE_CACHE_LINE_SIZE);
9547 PMD_DRV_LOG(NOTICE, sc, "Failed to allocate memory");
9552 pci_read(sc, PCI_STATUS, &status, 2);
9553 if (!(status & PCI_STATUS_CAP_LIST)) {
9555 pci_read(sc, PCIR_STATUS, &status, 2);
9556 if (!(status & PCIM_STATUS_CAPPRESENT)) {
9558 PMD_DRV_LOG(NOTICE, sc, "PCIe capability reading failed");
9563 pci_read(sc, PCI_CAPABILITY_LIST, &pci_cap.next, 1);
9565 pci_read(sc, PCIR_CAP_PTR, &pci_cap.next, 1);
9567 while (pci_cap.next) {
9568 cap->addr = pci_cap.next & ~3;
9569 pci_read(sc, pci_cap.next & ~3, &pci_cap, 2);
9570 if (pci_cap.id == 0xff)
9572 cap->id = pci_cap.id;
9573 cap->type = BNX2X_PCI_CAP;
9574 cap->next = rte_zmalloc("pci_cap",
9575 sizeof(struct bnx2x_pci_cap),
9576 RTE_CACHE_LINE_SIZE);
9578 PMD_DRV_LOG(NOTICE, sc, "Failed to allocate memory");
9587 static void bnx2x_init_rte(struct bnx2x_softc *sc)
9590 sc->max_tx_queues = min(BNX2X_VF_MAX_QUEUES_PER_VF,
9592 sc->max_rx_queues = min(BNX2X_VF_MAX_QUEUES_PER_VF,
9595 sc->max_rx_queues = BNX2X_MAX_RSS_COUNT(sc);
9596 sc->max_tx_queues = sc->max_rx_queues;
9600 #define FW_HEADER_LEN 104
9601 #define FW_NAME_57711 "/lib/firmware/bnx2x/bnx2x-e1h-7.2.51.0.fw"
9602 #define FW_NAME_57810 "/lib/firmware/bnx2x/bnx2x-e2-7.2.51.0.fw"
9604 void bnx2x_load_firmware(struct bnx2x_softc *sc)
9610 fwname = sc->devinfo.device_id == CHIP_NUM_57711
9611 ? FW_NAME_57711 : FW_NAME_57810;
9612 f = open(fwname, O_RDONLY);
9614 PMD_DRV_LOG(NOTICE, sc, "Can't open firmware file");
9618 if (fstat(f, &st) < 0) {
9619 PMD_DRV_LOG(NOTICE, sc, "Can't stat firmware file");
9624 sc->firmware = rte_zmalloc("bnx2x_fw", st.st_size, RTE_CACHE_LINE_SIZE);
9625 if (!sc->firmware) {
9626 PMD_DRV_LOG(NOTICE, sc, "Can't allocate memory for firmware");
9631 if (read(f, sc->firmware, st.st_size) != st.st_size) {
9632 PMD_DRV_LOG(NOTICE, sc, "Can't read firmware data");
9638 sc->fw_len = st.st_size;
9639 if (sc->fw_len < FW_HEADER_LEN) {
9640 PMD_DRV_LOG(NOTICE, sc,
9641 "Invalid fw size: %" PRIu64, sc->fw_len);
9644 PMD_DRV_LOG(DEBUG, sc, "fw_len = %" PRIu64, sc->fw_len);
9648 bnx2x_data_to_init_ops(uint8_t * data, struct raw_op *dst, uint32_t len)
9650 uint32_t *src = (uint32_t *) data;
9653 for (i = 0, j = 0; i < len / 8; ++i, j += 2) {
9654 tmp = rte_be_to_cpu_32(src[j]);
9655 dst[i].op = (tmp >> 24) & 0xFF;
9656 dst[i].offset = tmp & 0xFFFFFF;
9657 dst[i].raw_data = rte_be_to_cpu_32(src[j + 1]);
9662 bnx2x_data_to_init_offsets(uint8_t * data, uint16_t * dst, uint32_t len)
9664 uint16_t *src = (uint16_t *) data;
9667 for (i = 0; i < len / 2; ++i)
9668 dst[i] = rte_be_to_cpu_16(src[i]);
9671 static void bnx2x_data_to_init_data(uint8_t * data, uint32_t * dst, uint32_t len)
9673 uint32_t *src = (uint32_t *) data;
9676 for (i = 0; i < len / 4; ++i)
9677 dst[i] = rte_be_to_cpu_32(src[i]);
9680 static void bnx2x_data_to_iro_array(uint8_t * data, struct iro *dst, uint32_t len)
9682 uint32_t *src = (uint32_t *) data;
9685 for (i = 0, j = 0; i < len / sizeof(struct iro); ++i, ++j) {
9686 dst[i].base = rte_be_to_cpu_32(src[j++]);
9687 tmp = rte_be_to_cpu_32(src[j]);
9688 dst[i].m1 = (tmp >> 16) & 0xFFFF;
9689 dst[i].m2 = tmp & 0xFFFF;
9691 tmp = rte_be_to_cpu_32(src[j]);
9692 dst[i].m3 = (tmp >> 16) & 0xFFFF;
9693 dst[i].size = tmp & 0xFFFF;
9698 * Device attach function.
9700 * Allocates device resources, performs secondary chip identification, and
9701 * initializes driver instance variables. This function is called from driver
9702 * load after a successful probe.
9705 * 0 = Success, >0 = Failure
9707 int bnx2x_attach(struct bnx2x_softc *sc)
9711 PMD_DRV_LOG(DEBUG, sc, "Starting attach...");
9713 rc = bnx2x_pci_get_caps(sc);
9715 PMD_DRV_LOG(NOTICE, sc, "PCIe caps reading was failed");
9719 sc->state = BNX2X_STATE_CLOSED;
9721 pci_write_long(sc, PCICFG_GRC_ADDRESS, PCICFG_VENDOR_ID_OFFSET);
9723 sc->igu_base_addr = IS_VF(sc) ? PXP_VF_ADDR_IGU_START : BAR_IGU_INTMEM;
9725 /* get PCI capabilites */
9726 bnx2x_probe_pci_caps(sc);
9728 if (sc->devinfo.pcie_msix_cap_reg != 0) {
9731 (sc->devinfo.pcie_msix_cap_reg + PCIR_MSIX_CTRL), &val,
9733 sc->igu_sb_cnt = (val & PCIM_MSIXCTRL_TABLE_SIZE) + 1;
9738 /* Init RTE stuff */
9742 /* Enable internal target-read (in case we are probed after PF
9743 * FLR). Must be done prior to any BAR read access. Only for
9746 if (!CHIP_IS_E1x(sc)) {
9747 REG_WR(sc, PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ,
9752 /* get device info and set params */
9753 if (bnx2x_get_device_info(sc) != 0) {
9754 PMD_DRV_LOG(NOTICE, sc, "getting device info");
9758 /* get phy settings from shmem and 'and' against admin settings */
9759 bnx2x_get_phy_info(sc);
9761 /* Left mac of VF unfilled, PF should set it for VF */
9762 memset(sc->link_params.mac_addr, 0, ETHER_ADDR_LEN);
9767 /* set the default MTU (changed via ifconfig) */
9768 sc->mtu = ETHER_MTU;
9770 bnx2x_set_modes_bitmap(sc);
9772 /* need to reset chip if UNDI was active */
9773 if (IS_PF(sc) && !BNX2X_NOMCP(sc)) {
9776 (SHMEM_RD(sc, func_mb[SC_FW_MB_IDX(sc)].drv_mb_header) &
9777 DRV_MSG_SEQ_NUMBER_MASK);
9778 PMD_DRV_LOG(DEBUG, sc, "prev unload fw_seq 0x%04x",
9780 bnx2x_prev_unload(sc);
9783 bnx2x_dcbx_set_state(sc, FALSE, BNX2X_DCBX_ENABLED_OFF);
9785 /* calculate qm_cid_count */
9786 sc->qm_cid_count = bnx2x_set_qm_cid_count(sc);
9789 bnx2x_init_multi_cos(sc);
9795 bnx2x_igu_ack_sb(struct bnx2x_softc *sc, uint8_t igu_sb_id, uint8_t segment,
9796 uint16_t index, uint8_t op, uint8_t update)
9798 uint32_t igu_addr = sc->igu_base_addr;
9799 igu_addr += (IGU_CMD_INT_ACK_BASE + igu_sb_id) * 8;
9800 bnx2x_igu_ack_sb_gen(sc, segment, index, op, update, igu_addr);
9804 bnx2x_ack_sb(struct bnx2x_softc *sc, uint8_t igu_sb_id, uint8_t storm,
9805 uint16_t index, uint8_t op, uint8_t update)
9807 if (unlikely(sc->devinfo.int_block == INT_BLOCK_HC))
9808 bnx2x_hc_ack_sb(sc, igu_sb_id, storm, index, op, update);
9811 if (CHIP_INT_MODE_IS_BC(sc)) {
9813 } else if (igu_sb_id != sc->igu_dsb_id) {
9814 segment = IGU_SEG_ACCESS_DEF;
9815 } else if (storm == ATTENTION_ID) {
9816 segment = IGU_SEG_ACCESS_ATTN;
9818 segment = IGU_SEG_ACCESS_DEF;
9820 bnx2x_igu_ack_sb(sc, igu_sb_id, segment, index, op, update);
9825 bnx2x_igu_clear_sb_gen(struct bnx2x_softc *sc, uint8_t func, uint8_t idu_sb_id,
9828 uint32_t data, ctl, cnt = 100;
9829 uint32_t igu_addr_data = IGU_REG_COMMAND_REG_32LSB_DATA;
9830 uint32_t igu_addr_ctl = IGU_REG_COMMAND_REG_CTRL;
9831 uint32_t igu_addr_ack = IGU_REG_CSTORM_TYPE_0_SB_CLEANUP +
9832 (idu_sb_id / 32) * 4;
9833 uint32_t sb_bit = 1 << (idu_sb_id % 32);
9834 uint32_t func_encode = func |
9835 (is_pf ? 1 : 0) << IGU_FID_ENCODE_IS_PF_SHIFT;
9836 uint32_t addr_encode = IGU_CMD_E2_PROD_UPD_BASE + idu_sb_id;
9838 /* Not supported in BC mode */
9839 if (CHIP_INT_MODE_IS_BC(sc)) {
9843 data = ((IGU_USE_REGISTER_cstorm_type_0_sb_cleanup <<
9844 IGU_REGULAR_CLEANUP_TYPE_SHIFT) |
9845 IGU_REGULAR_CLEANUP_SET | IGU_REGULAR_BCLEANUP);
9847 ctl = ((addr_encode << IGU_CTRL_REG_ADDRESS_SHIFT) |
9848 (func_encode << IGU_CTRL_REG_FID_SHIFT) |
9849 (IGU_CTRL_CMD_TYPE_WR << IGU_CTRL_REG_TYPE_SHIFT));
9851 REG_WR(sc, igu_addr_data, data);
9855 PMD_DRV_LOG(DEBUG, sc, "write 0x%08x to IGU(via GRC) addr 0x%x",
9857 REG_WR(sc, igu_addr_ctl, ctl);
9861 /* wait for clean up to finish */
9862 while (!(REG_RD(sc, igu_addr_ack) & sb_bit) && --cnt) {
9866 if (!(REG_RD(sc, igu_addr_ack) & sb_bit)) {
9867 PMD_DRV_LOG(DEBUG, sc,
9868 "Unable to finish IGU cleanup: "
9869 "idu_sb_id %d offset %d bit %d (cnt %d)",
9870 idu_sb_id, idu_sb_id / 32, idu_sb_id % 32, cnt);
9874 static void bnx2x_igu_clear_sb(struct bnx2x_softc *sc, uint8_t idu_sb_id)
9876 bnx2x_igu_clear_sb_gen(sc, SC_FUNC(sc), idu_sb_id, TRUE /*PF*/);
9879 /*******************/
9880 /* ECORE CALLBACKS */
9881 /*******************/
9883 static void bnx2x_reset_common(struct bnx2x_softc *sc)
9885 uint32_t val = 0x1400;
9887 PMD_INIT_FUNC_TRACE(sc);
9890 REG_WR(sc, (GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR),
9893 if (CHIP_IS_E3(sc)) {
9894 val |= MISC_REGISTERS_RESET_REG_2_MSTAT0;
9895 val |= MISC_REGISTERS_RESET_REG_2_MSTAT1;
9898 REG_WR(sc, (GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR), val);
9901 static void bnx2x_common_init_phy(struct bnx2x_softc *sc)
9903 uint32_t shmem_base[2];
9904 uint32_t shmem2_base[2];
9906 /* Avoid common init in case MFW supports LFA */
9907 if (SHMEM2_RD(sc, size) >
9908 (uint32_t) offsetof(struct shmem2_region,
9909 lfa_host_addr[SC_PORT(sc)])) {
9913 shmem_base[0] = sc->devinfo.shmem_base;
9914 shmem2_base[0] = sc->devinfo.shmem2_base;
9916 if (!CHIP_IS_E1x(sc)) {
9917 shmem_base[1] = SHMEM2_RD(sc, other_shmem_base_addr);
9918 shmem2_base[1] = SHMEM2_RD(sc, other_shmem2_base_addr);
9921 bnx2x_acquire_phy_lock(sc);
9922 elink_common_init_phy(sc, shmem_base, shmem2_base,
9923 sc->devinfo.chip_id, 0);
9924 bnx2x_release_phy_lock(sc);
9927 static void bnx2x_pf_disable(struct bnx2x_softc *sc)
9929 uint32_t val = REG_RD(sc, IGU_REG_PF_CONFIGURATION);
9931 val &= ~IGU_PF_CONF_FUNC_EN;
9933 REG_WR(sc, IGU_REG_PF_CONFIGURATION, val);
9934 REG_WR(sc, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 0);
9935 REG_WR(sc, CFC_REG_WEAK_ENABLE_PF, 0);
9938 static void bnx2x_init_pxp(struct bnx2x_softc *sc)
9941 int r_order, w_order;
9943 devctl = bnx2x_pcie_capability_read(sc, PCIR_EXPRESS_DEVICE_CTL);
9945 w_order = ((devctl & PCIM_EXP_CTL_MAX_PAYLOAD) >> 5);
9946 r_order = ((devctl & PCIM_EXP_CTL_MAX_READ_REQUEST) >> 12);
9948 ecore_init_pxp_arb(sc, r_order, w_order);
9951 static uint32_t bnx2x_get_pretend_reg(struct bnx2x_softc *sc)
9953 uint32_t base = PXP2_REG_PGL_PRETEND_FUNC_F0;
9954 uint32_t stride = (PXP2_REG_PGL_PRETEND_FUNC_F1 - base);
9955 return base + (SC_ABS_FUNC(sc)) * stride;
9959 * Called only on E1H or E2.
9960 * When pretending to be PF, the pretend value is the function number 0..7.
9961 * When pretending to be VF, the pretend val is the PF-num:VF-valid:ABS-VFID
9964 static int bnx2x_pretend_func(struct bnx2x_softc *sc, uint16_t pretend_func_val)
9966 uint32_t pretend_reg;
9968 if (CHIP_IS_E1H(sc) && (pretend_func_val > E1H_FUNC_MAX))
9971 /* get my own pretend register */
9972 pretend_reg = bnx2x_get_pretend_reg(sc);
9973 REG_WR(sc, pretend_reg, pretend_func_val);
9974 REG_RD(sc, pretend_reg);
9978 static void bnx2x_setup_fan_failure_detection(struct bnx2x_softc *sc)
9985 val = (SHMEM_RD(sc, dev_info.shared_hw_config.config2) &
9986 SHARED_HW_CFG_FAN_FAILURE_MASK);
9988 if (val == SHARED_HW_CFG_FAN_FAILURE_ENABLED) {
9992 * The fan failure mechanism is usually related to the PHY type since
9993 * the power consumption of the board is affected by the PHY. Currently,
9994 * fan is required for most designs with SFX7101, BNX2X8727 and BNX2X8481.
9996 else if (val == SHARED_HW_CFG_FAN_FAILURE_PHY_TYPE) {
9997 for (port = PORT_0; port < PORT_MAX; port++) {
9998 is_required |= elink_fan_failure_det_req(sc,
10000 devinfo.shmem_base,
10002 devinfo.shmem2_base,
10007 if (is_required == 0) {
10011 /* Fan failure is indicated by SPIO 5 */
10012 bnx2x_set_spio(sc, MISC_SPIO_SPIO5, MISC_SPIO_INPUT_HI_Z);
10014 /* set to active low mode */
10015 val = REG_RD(sc, MISC_REG_SPIO_INT);
10016 val |= (MISC_SPIO_SPIO5 << MISC_SPIO_INT_OLD_SET_POS);
10017 REG_WR(sc, MISC_REG_SPIO_INT, val);
10019 /* enable interrupt to signal the IGU */
10020 val = REG_RD(sc, MISC_REG_SPIO_EVENT_EN);
10021 val |= MISC_SPIO_SPIO5;
10022 REG_WR(sc, MISC_REG_SPIO_EVENT_EN, val);
10025 static void bnx2x_enable_blocks_attention(struct bnx2x_softc *sc)
10029 REG_WR(sc, PXP_REG_PXP_INT_MASK_0, 0);
10030 if (!CHIP_IS_E1x(sc)) {
10031 REG_WR(sc, PXP_REG_PXP_INT_MASK_1, 0x40);
10033 REG_WR(sc, PXP_REG_PXP_INT_MASK_1, 0);
10035 REG_WR(sc, DORQ_REG_DORQ_INT_MASK, 0);
10036 REG_WR(sc, CFC_REG_CFC_INT_MASK, 0);
10038 * mask read length error interrupts in brb for parser
10039 * (parsing unit and 'checksum and crc' unit)
10040 * these errors are legal (PU reads fixed length and CAC can cause
10041 * read length error on truncated packets)
10043 REG_WR(sc, BRB1_REG_BRB1_INT_MASK, 0xFC00);
10044 REG_WR(sc, QM_REG_QM_INT_MASK, 0);
10045 REG_WR(sc, TM_REG_TM_INT_MASK, 0);
10046 REG_WR(sc, XSDM_REG_XSDM_INT_MASK_0, 0);
10047 REG_WR(sc, XSDM_REG_XSDM_INT_MASK_1, 0);
10048 REG_WR(sc, XCM_REG_XCM_INT_MASK, 0);
10049 /* REG_WR(sc, XSEM_REG_XSEM_INT_MASK_0, 0); */
10050 /* REG_WR(sc, XSEM_REG_XSEM_INT_MASK_1, 0); */
10051 REG_WR(sc, USDM_REG_USDM_INT_MASK_0, 0);
10052 REG_WR(sc, USDM_REG_USDM_INT_MASK_1, 0);
10053 REG_WR(sc, UCM_REG_UCM_INT_MASK, 0);
10054 /* REG_WR(sc, USEM_REG_USEM_INT_MASK_0, 0); */
10055 /* REG_WR(sc, USEM_REG_USEM_INT_MASK_1, 0); */
10056 REG_WR(sc, GRCBASE_UPB + PB_REG_PB_INT_MASK, 0);
10057 REG_WR(sc, CSDM_REG_CSDM_INT_MASK_0, 0);
10058 REG_WR(sc, CSDM_REG_CSDM_INT_MASK_1, 0);
10059 REG_WR(sc, CCM_REG_CCM_INT_MASK, 0);
10060 /* REG_WR(sc, CSEM_REG_CSEM_INT_MASK_0, 0); */
10061 /* REG_WR(sc, CSEM_REG_CSEM_INT_MASK_1, 0); */
10063 val = (PXP2_PXP2_INT_MASK_0_REG_PGL_CPL_AFT |
10064 PXP2_PXP2_INT_MASK_0_REG_PGL_CPL_OF |
10065 PXP2_PXP2_INT_MASK_0_REG_PGL_PCIE_ATTN);
10066 if (!CHIP_IS_E1x(sc)) {
10067 val |= (PXP2_PXP2_INT_MASK_0_REG_PGL_READ_BLOCKED |
10068 PXP2_PXP2_INT_MASK_0_REG_PGL_WRITE_BLOCKED);
10070 REG_WR(sc, PXP2_REG_PXP2_INT_MASK_0, val);
10072 REG_WR(sc, TSDM_REG_TSDM_INT_MASK_0, 0);
10073 REG_WR(sc, TSDM_REG_TSDM_INT_MASK_1, 0);
10074 REG_WR(sc, TCM_REG_TCM_INT_MASK, 0);
10075 /* REG_WR(sc, TSEM_REG_TSEM_INT_MASK_0, 0); */
10077 if (!CHIP_IS_E1x(sc)) {
10078 /* enable VFC attentions: bits 11 and 12, bits 31:13 reserved */
10079 REG_WR(sc, TSEM_REG_TSEM_INT_MASK_1, 0x07ff);
10082 REG_WR(sc, CDU_REG_CDU_INT_MASK, 0);
10083 REG_WR(sc, DMAE_REG_DMAE_INT_MASK, 0);
10084 /* REG_WR(sc, MISC_REG_MISC_INT_MASK, 0); */
10085 REG_WR(sc, PBF_REG_PBF_INT_MASK, 0x18); /* bit 3,4 masked */
10089 * bnx2x_init_hw_common - initialize the HW at the COMMON phase.
10091 * @sc: driver handle
10093 static int bnx2x_init_hw_common(struct bnx2x_softc *sc)
10095 uint8_t abs_func_id;
10098 PMD_DRV_LOG(DEBUG, sc,
10099 "starting common init for func %d", SC_ABS_FUNC(sc));
10102 * take the RESET lock to protect undi_unload flow from accessing
10103 * registers while we are resetting the chip
10105 bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_RESET);
10107 bnx2x_reset_common(sc);
10109 REG_WR(sc, (GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET), 0xffffffff);
10112 if (CHIP_IS_E3(sc)) {
10113 val |= MISC_REGISTERS_RESET_REG_2_MSTAT0;
10114 val |= MISC_REGISTERS_RESET_REG_2_MSTAT1;
10117 REG_WR(sc, (GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET), val);
10119 bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_RESET);
10121 ecore_init_block(sc, BLOCK_MISC, PHASE_COMMON);
10123 if (!CHIP_IS_E1x(sc)) {
10125 * 4-port mode or 2-port mode we need to turn off master-enable for
10126 * everyone. After that we turn it back on for self. So, we disregard
10127 * multi-function, and always disable all functions on the given path,
10128 * this means 0,2,4,6 for path 0 and 1,3,5,7 for path 1
10130 for (abs_func_id = SC_PATH(sc);
10131 abs_func_id < (E2_FUNC_MAX * 2); abs_func_id += 2) {
10132 if (abs_func_id == SC_ABS_FUNC(sc)) {
10134 PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER,
10139 bnx2x_pretend_func(sc, abs_func_id);
10141 /* clear pf enable */
10142 bnx2x_pf_disable(sc);
10144 bnx2x_pretend_func(sc, SC_ABS_FUNC(sc));
10148 ecore_init_block(sc, BLOCK_PXP, PHASE_COMMON);
10150 ecore_init_block(sc, BLOCK_PXP2, PHASE_COMMON);
10151 bnx2x_init_pxp(sc);
10153 #ifdef __BIG_ENDIAN
10154 REG_WR(sc, PXP2_REG_RQ_QM_ENDIAN_M, 1);
10155 REG_WR(sc, PXP2_REG_RQ_TM_ENDIAN_M, 1);
10156 REG_WR(sc, PXP2_REG_RQ_SRC_ENDIAN_M, 1);
10157 REG_WR(sc, PXP2_REG_RQ_CDU_ENDIAN_M, 1);
10158 REG_WR(sc, PXP2_REG_RQ_DBG_ENDIAN_M, 1);
10159 /* make sure this value is 0 */
10160 REG_WR(sc, PXP2_REG_RQ_HC_ENDIAN_M, 0);
10162 //REG_WR(sc, PXP2_REG_RD_PBF_SWAP_MODE, 1);
10163 REG_WR(sc, PXP2_REG_RD_QM_SWAP_MODE, 1);
10164 REG_WR(sc, PXP2_REG_RD_TM_SWAP_MODE, 1);
10165 REG_WR(sc, PXP2_REG_RD_SRC_SWAP_MODE, 1);
10166 REG_WR(sc, PXP2_REG_RD_CDURD_SWAP_MODE, 1);
10169 ecore_ilt_init_page_size(sc, INITOP_SET);
10171 if (CHIP_REV_IS_FPGA(sc) && CHIP_IS_E1H(sc)) {
10172 REG_WR(sc, PXP2_REG_PGL_TAGS_LIMIT, 0x1);
10175 /* let the HW do it's magic... */
10178 /* finish PXP init */
10180 val = REG_RD(sc, PXP2_REG_RQ_CFG_DONE);
10182 PMD_DRV_LOG(NOTICE, sc, "PXP2 CFG failed");
10185 val = REG_RD(sc, PXP2_REG_RD_INIT_DONE);
10187 PMD_DRV_LOG(NOTICE, sc, "PXP2 RD_INIT failed");
10192 * Timer bug workaround for E2 only. We need to set the entire ILT to have
10193 * entries with value "0" and valid bit on. This needs to be done by the
10194 * first PF that is loaded in a path (i.e. common phase)
10196 if (!CHIP_IS_E1x(sc)) {
10198 * In E2 there is a bug in the timers block that can cause function 6 / 7
10199 * (i.e. vnic3) to start even if it is marked as "scan-off".
10200 * This occurs when a different function (func2,3) is being marked
10201 * as "scan-off". Real-life scenario for example: if a driver is being
10202 * load-unloaded while func6,7 are down. This will cause the timer to access
10203 * the ilt, translate to a logical address and send a request to read/write.
10204 * Since the ilt for the function that is down is not valid, this will cause
10205 * a translation error which is unrecoverable.
10206 * The Workaround is intended to make sure that when this happens nothing
10207 * fatal will occur. The workaround:
10208 * 1. First PF driver which loads on a path will:
10209 * a. After taking the chip out of reset, by using pretend,
10210 * it will write "0" to the following registers of
10212 * REG_WR(pdev, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 0);
10213 * REG_WR(pdev, CFC_REG_WEAK_ENABLE_PF,0);
10214 * REG_WR(pdev, CFC_REG_STRONG_ENABLE_PF,0);
10215 * And for itself it will write '1' to
10216 * PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER to enable
10217 * dmae-operations (writing to pram for example.)
10218 * note: can be done for only function 6,7 but cleaner this
10220 * b. Write zero+valid to the entire ILT.
10221 * c. Init the first_timers_ilt_entry, last_timers_ilt_entry of
10222 * VNIC3 (of that port). The range allocated will be the
10223 * entire ILT. This is needed to prevent ILT range error.
10224 * 2. Any PF driver load flow:
10225 * a. ILT update with the physical addresses of the allocated
10227 * b. Wait 20msec. - note that this timeout is needed to make
10228 * sure there are no requests in one of the PXP internal
10229 * queues with "old" ILT addresses.
10230 * c. PF enable in the PGLC.
10231 * d. Clear the was_error of the PF in the PGLC. (could have
10232 * occurred while driver was down)
10233 * e. PF enable in the CFC (WEAK + STRONG)
10234 * f. Timers scan enable
10235 * 3. PF driver unload flow:
10236 * a. Clear the Timers scan_en.
10237 * b. Polling for scan_on=0 for that PF.
10238 * c. Clear the PF enable bit in the PXP.
10239 * d. Clear the PF enable in the CFC (WEAK + STRONG)
10240 * e. Write zero+valid to all ILT entries (The valid bit must
10242 * f. If this is VNIC 3 of a port then also init
10243 * first_timers_ilt_entry to zero and last_timers_ilt_entry
10244 * to the last enrty in the ILT.
10247 * Currently the PF error in the PGLC is non recoverable.
10248 * In the future the there will be a recovery routine for this error.
10249 * Currently attention is masked.
10250 * Having an MCP lock on the load/unload process does not guarantee that
10251 * there is no Timer disable during Func6/7 enable. This is because the
10252 * Timers scan is currently being cleared by the MCP on FLR.
10253 * Step 2.d can be done only for PF6/7 and the driver can also check if
10254 * there is error before clearing it. But the flow above is simpler and
10256 * All ILT entries are written by zero+valid and not just PF6/7
10257 * ILT entries since in the future the ILT entries allocation for
10258 * PF-s might be dynamic.
10260 struct ilt_client_info ilt_cli;
10261 struct ecore_ilt ilt;
10263 memset(&ilt_cli, 0, sizeof(struct ilt_client_info));
10264 memset(&ilt, 0, sizeof(struct ecore_ilt));
10266 /* initialize dummy TM client */
10268 ilt_cli.end = ILT_NUM_PAGE_ENTRIES - 1;
10269 ilt_cli.client_num = ILT_CLIENT_TM;
10272 * Step 1: set zeroes to all ilt page entries with valid bit on
10273 * Step 2: set the timers first/last ilt entry to point
10274 * to the entire range to prevent ILT range error for 3rd/4th
10275 * vnic (this code assumes existence of the vnic)
10277 * both steps performed by call to ecore_ilt_client_init_op()
10278 * with dummy TM client
10280 * we must use pretend since PXP2_REG_RQ_##blk##_FIRST_ILT
10281 * and his brother are split registers
10284 bnx2x_pretend_func(sc, (SC_PATH(sc) + 6));
10285 ecore_ilt_client_init_op_ilt(sc, &ilt, &ilt_cli, INITOP_CLEAR);
10286 bnx2x_pretend_func(sc, SC_ABS_FUNC(sc));
10288 REG_WR(sc, PXP2_REG_RQ_DRAM_ALIGN, BNX2X_PXP_DRAM_ALIGN);
10289 REG_WR(sc, PXP2_REG_RQ_DRAM_ALIGN_RD, BNX2X_PXP_DRAM_ALIGN);
10290 REG_WR(sc, PXP2_REG_RQ_DRAM_ALIGN_SEL, 1);
10293 REG_WR(sc, PXP2_REG_RQ_DISABLE_INPUTS, 0);
10294 REG_WR(sc, PXP2_REG_RD_DISABLE_INPUTS, 0);
10296 if (!CHIP_IS_E1x(sc)) {
10299 ecore_init_block(sc, BLOCK_PGLUE_B, PHASE_COMMON);
10300 ecore_init_block(sc, BLOCK_ATC, PHASE_COMMON);
10302 /* let the HW do it's magic... */
10305 val = REG_RD(sc, ATC_REG_ATC_INIT_DONE);
10306 } while (factor-- && (val != 1));
10309 PMD_DRV_LOG(NOTICE, sc, "ATC_INIT failed");
10314 ecore_init_block(sc, BLOCK_DMAE, PHASE_COMMON);
10316 /* clean the DMAE memory */
10317 sc->dmae_ready = 1;
10318 ecore_init_fill(sc, TSEM_REG_PRAM, 0, 8);
10320 ecore_init_block(sc, BLOCK_TCM, PHASE_COMMON);
10322 ecore_init_block(sc, BLOCK_UCM, PHASE_COMMON);
10324 ecore_init_block(sc, BLOCK_CCM, PHASE_COMMON);
10326 ecore_init_block(sc, BLOCK_XCM, PHASE_COMMON);
10328 bnx2x_read_dmae(sc, XSEM_REG_PASSIVE_BUFFER, 3);
10329 bnx2x_read_dmae(sc, CSEM_REG_PASSIVE_BUFFER, 3);
10330 bnx2x_read_dmae(sc, TSEM_REG_PASSIVE_BUFFER, 3);
10331 bnx2x_read_dmae(sc, USEM_REG_PASSIVE_BUFFER, 3);
10333 ecore_init_block(sc, BLOCK_QM, PHASE_COMMON);
10335 /* QM queues pointers table */
10336 ecore_qm_init_ptr_table(sc, sc->qm_cid_count, INITOP_SET);
10338 /* soft reset pulse */
10339 REG_WR(sc, QM_REG_SOFT_RESET, 1);
10340 REG_WR(sc, QM_REG_SOFT_RESET, 0);
10342 if (CNIC_SUPPORT(sc))
10343 ecore_init_block(sc, BLOCK_TM, PHASE_COMMON);
10345 ecore_init_block(sc, BLOCK_DORQ, PHASE_COMMON);
10346 REG_WR(sc, DORQ_REG_DPM_CID_OFST, BNX2X_DB_SHIFT);
10348 if (!CHIP_REV_IS_SLOW(sc)) {
10349 /* enable hw interrupt from doorbell Q */
10350 REG_WR(sc, DORQ_REG_DORQ_INT_MASK, 0);
10353 ecore_init_block(sc, BLOCK_BRB1, PHASE_COMMON);
10355 ecore_init_block(sc, BLOCK_PRS, PHASE_COMMON);
10356 REG_WR(sc, PRS_REG_A_PRSU_20, 0xf);
10357 REG_WR(sc, PRS_REG_E1HOV_MODE, sc->devinfo.mf_info.path_has_ovlan);
10359 if (!CHIP_IS_E1x(sc) && !CHIP_IS_E3B0(sc)) {
10360 if (IS_MF_AFEX(sc)) {
10362 * configure that AFEX and VLAN headers must be
10363 * received in AFEX mode
10365 REG_WR(sc, PRS_REG_HDRS_AFTER_BASIC, 0xE);
10366 REG_WR(sc, PRS_REG_MUST_HAVE_HDRS, 0xA);
10367 REG_WR(sc, PRS_REG_HDRS_AFTER_TAG_0, 0x6);
10368 REG_WR(sc, PRS_REG_TAG_ETHERTYPE_0, 0x8926);
10369 REG_WR(sc, PRS_REG_TAG_LEN_0, 0x4);
10372 * Bit-map indicating which L2 hdrs may appear
10373 * after the basic Ethernet header
10375 REG_WR(sc, PRS_REG_HDRS_AFTER_BASIC,
10376 sc->devinfo.mf_info.path_has_ovlan ? 7 : 6);
10380 ecore_init_block(sc, BLOCK_TSDM, PHASE_COMMON);
10381 ecore_init_block(sc, BLOCK_CSDM, PHASE_COMMON);
10382 ecore_init_block(sc, BLOCK_USDM, PHASE_COMMON);
10383 ecore_init_block(sc, BLOCK_XSDM, PHASE_COMMON);
10385 if (!CHIP_IS_E1x(sc)) {
10386 /* reset VFC memories */
10387 REG_WR(sc, TSEM_REG_FAST_MEMORY + VFC_REG_MEMORIES_RST,
10388 VFC_MEMORIES_RST_REG_CAM_RST |
10389 VFC_MEMORIES_RST_REG_RAM_RST);
10390 REG_WR(sc, XSEM_REG_FAST_MEMORY + VFC_REG_MEMORIES_RST,
10391 VFC_MEMORIES_RST_REG_CAM_RST |
10392 VFC_MEMORIES_RST_REG_RAM_RST);
10397 ecore_init_block(sc, BLOCK_TSEM, PHASE_COMMON);
10398 ecore_init_block(sc, BLOCK_USEM, PHASE_COMMON);
10399 ecore_init_block(sc, BLOCK_CSEM, PHASE_COMMON);
10400 ecore_init_block(sc, BLOCK_XSEM, PHASE_COMMON);
10402 /* sync semi rtc */
10403 REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, 0x80000000);
10404 REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0x80000000);
10406 ecore_init_block(sc, BLOCK_UPB, PHASE_COMMON);
10407 ecore_init_block(sc, BLOCK_XPB, PHASE_COMMON);
10408 ecore_init_block(sc, BLOCK_PBF, PHASE_COMMON);
10410 if (!CHIP_IS_E1x(sc)) {
10411 if (IS_MF_AFEX(sc)) {
10413 * configure that AFEX and VLAN headers must be
10414 * sent in AFEX mode
10416 REG_WR(sc, PBF_REG_HDRS_AFTER_BASIC, 0xE);
10417 REG_WR(sc, PBF_REG_MUST_HAVE_HDRS, 0xA);
10418 REG_WR(sc, PBF_REG_HDRS_AFTER_TAG_0, 0x6);
10419 REG_WR(sc, PBF_REG_TAG_ETHERTYPE_0, 0x8926);
10420 REG_WR(sc, PBF_REG_TAG_LEN_0, 0x4);
10422 REG_WR(sc, PBF_REG_HDRS_AFTER_BASIC,
10423 sc->devinfo.mf_info.path_has_ovlan ? 7 : 6);
10427 REG_WR(sc, SRC_REG_SOFT_RST, 1);
10429 ecore_init_block(sc, BLOCK_SRC, PHASE_COMMON);
10431 if (CNIC_SUPPORT(sc)) {
10432 REG_WR(sc, SRC_REG_KEYSEARCH_0, 0x63285672);
10433 REG_WR(sc, SRC_REG_KEYSEARCH_1, 0x24b8f2cc);
10434 REG_WR(sc, SRC_REG_KEYSEARCH_2, 0x223aef9b);
10435 REG_WR(sc, SRC_REG_KEYSEARCH_3, 0x26001e3a);
10436 REG_WR(sc, SRC_REG_KEYSEARCH_4, 0x7ae91116);
10437 REG_WR(sc, SRC_REG_KEYSEARCH_5, 0x5ce5230b);
10438 REG_WR(sc, SRC_REG_KEYSEARCH_6, 0x298d8adf);
10439 REG_WR(sc, SRC_REG_KEYSEARCH_7, 0x6eb0ff09);
10440 REG_WR(sc, SRC_REG_KEYSEARCH_8, 0x1830f82f);
10441 REG_WR(sc, SRC_REG_KEYSEARCH_9, 0x01e46be7);
10443 REG_WR(sc, SRC_REG_SOFT_RST, 0);
10445 if (sizeof(union cdu_context) != 1024) {
10446 /* we currently assume that a context is 1024 bytes */
10447 PMD_DRV_LOG(NOTICE, sc,
10448 "please adjust the size of cdu_context(%ld)",
10449 (long)sizeof(union cdu_context));
10452 ecore_init_block(sc, BLOCK_CDU, PHASE_COMMON);
10453 val = (4 << 24) + (0 << 12) + 1024;
10454 REG_WR(sc, CDU_REG_CDU_GLOBAL_PARAMS, val);
10456 ecore_init_block(sc, BLOCK_CFC, PHASE_COMMON);
10458 REG_WR(sc, CFC_REG_INIT_REG, 0x7FF);
10459 /* enable context validation interrupt from CFC */
10460 REG_WR(sc, CFC_REG_CFC_INT_MASK, 0);
10462 /* set the thresholds to prevent CFC/CDU race */
10463 REG_WR(sc, CFC_REG_DEBUG0, 0x20020000);
10464 ecore_init_block(sc, BLOCK_HC, PHASE_COMMON);
10466 if (!CHIP_IS_E1x(sc) && BNX2X_NOMCP(sc)) {
10467 REG_WR(sc, IGU_REG_RESET_MEMORIES, 0x36);
10470 ecore_init_block(sc, BLOCK_IGU, PHASE_COMMON);
10471 ecore_init_block(sc, BLOCK_MISC_AEU, PHASE_COMMON);
10473 /* Reset PCIE errors for debug */
10474 REG_WR(sc, 0x2814, 0xffffffff);
10475 REG_WR(sc, 0x3820, 0xffffffff);
10477 if (!CHIP_IS_E1x(sc)) {
10478 REG_WR(sc, PCICFG_OFFSET + PXPCS_TL_CONTROL_5,
10479 (PXPCS_TL_CONTROL_5_ERR_UNSPPORT1 |
10480 PXPCS_TL_CONTROL_5_ERR_UNSPPORT));
10481 REG_WR(sc, PCICFG_OFFSET + PXPCS_TL_FUNC345_STAT,
10482 (PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT4 |
10483 PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT3 |
10484 PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT2));
10485 REG_WR(sc, PCICFG_OFFSET + PXPCS_TL_FUNC678_STAT,
10486 (PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT7 |
10487 PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT6 |
10488 PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT5));
10491 ecore_init_block(sc, BLOCK_NIG, PHASE_COMMON);
10493 /* in E3 this done in per-port section */
10494 if (!CHIP_IS_E3(sc))
10495 REG_WR(sc, NIG_REG_LLH_MF_MODE, IS_MF(sc));
10497 if (CHIP_IS_E1H(sc)) {
10498 /* not applicable for E2 (and above ...) */
10499 REG_WR(sc, NIG_REG_LLH_E1HOV_MODE, IS_MF_SD(sc));
10502 if (CHIP_REV_IS_SLOW(sc)) {
10506 /* finish CFC init */
10507 val = reg_poll(sc, CFC_REG_LL_INIT_DONE, 1, 100, 10);
10509 PMD_DRV_LOG(NOTICE, sc, "CFC LL_INIT failed");
10512 val = reg_poll(sc, CFC_REG_AC_INIT_DONE, 1, 100, 10);
10514 PMD_DRV_LOG(NOTICE, sc, "CFC AC_INIT failed");
10517 val = reg_poll(sc, CFC_REG_CAM_INIT_DONE, 1, 100, 10);
10519 PMD_DRV_LOG(NOTICE, sc, "CFC CAM_INIT failed");
10522 REG_WR(sc, CFC_REG_DEBUG0, 0);
10524 bnx2x_setup_fan_failure_detection(sc);
10526 /* clear PXP2 attentions */
10527 REG_RD(sc, PXP2_REG_PXP2_INT_STS_CLR_0);
10529 bnx2x_enable_blocks_attention(sc);
10531 if (!CHIP_REV_IS_SLOW(sc)) {
10532 ecore_enable_blocks_parity(sc);
10535 if (!BNX2X_NOMCP(sc)) {
10536 if (CHIP_IS_E1x(sc)) {
10537 bnx2x_common_init_phy(sc);
10545 * bnx2x_init_hw_common_chip - init HW at the COMMON_CHIP phase.
10547 * @sc: driver handle
10549 static int bnx2x_init_hw_common_chip(struct bnx2x_softc *sc)
10551 int rc = bnx2x_init_hw_common(sc);
10557 /* In E2 2-PORT mode, same ext phy is used for the two paths */
10558 if (!BNX2X_NOMCP(sc)) {
10559 bnx2x_common_init_phy(sc);
10565 static int bnx2x_init_hw_port(struct bnx2x_softc *sc)
10567 int port = SC_PORT(sc);
10568 int init_phase = port ? PHASE_PORT1 : PHASE_PORT0;
10569 uint32_t low, high;
10572 PMD_DRV_LOG(DEBUG, sc, "starting port init for port %d", port);
10574 REG_WR(sc, NIG_REG_MASK_INTERRUPT_PORT0 + port * 4, 0);
10576 ecore_init_block(sc, BLOCK_MISC, init_phase);
10577 ecore_init_block(sc, BLOCK_PXP, init_phase);
10578 ecore_init_block(sc, BLOCK_PXP2, init_phase);
10581 * Timers bug workaround: disables the pf_master bit in pglue at
10582 * common phase, we need to enable it here before any dmae access are
10583 * attempted. Therefore we manually added the enable-master to the
10584 * port phase (it also happens in the function phase)
10586 if (!CHIP_IS_E1x(sc)) {
10587 REG_WR(sc, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1);
10590 ecore_init_block(sc, BLOCK_ATC, init_phase);
10591 ecore_init_block(sc, BLOCK_DMAE, init_phase);
10592 ecore_init_block(sc, BLOCK_PGLUE_B, init_phase);
10593 ecore_init_block(sc, BLOCK_QM, init_phase);
10595 ecore_init_block(sc, BLOCK_TCM, init_phase);
10596 ecore_init_block(sc, BLOCK_UCM, init_phase);
10597 ecore_init_block(sc, BLOCK_CCM, init_phase);
10598 ecore_init_block(sc, BLOCK_XCM, init_phase);
10600 /* QM cid (connection) count */
10601 ecore_qm_init_cid_count(sc, sc->qm_cid_count, INITOP_SET);
10603 if (CNIC_SUPPORT(sc)) {
10604 ecore_init_block(sc, BLOCK_TM, init_phase);
10605 REG_WR(sc, TM_REG_LIN0_SCAN_TIME + port * 4, 20);
10606 REG_WR(sc, TM_REG_LIN0_MAX_ACTIVE_CID + port * 4, 31);
10609 ecore_init_block(sc, BLOCK_DORQ, init_phase);
10611 ecore_init_block(sc, BLOCK_BRB1, init_phase);
10613 if (CHIP_IS_E1H(sc)) {
10615 low = (BNX2X_ONE_PORT(sc) ? 160 : 246);
10616 } else if (sc->mtu > 4096) {
10617 if (BNX2X_ONE_PORT(sc)) {
10621 /* (24*1024 + val*4)/256 */
10622 low = (96 + (val / 64) + ((val % 64) ? 1 : 0));
10625 low = (BNX2X_ONE_PORT(sc) ? 80 : 160);
10627 high = (low + 56); /* 14*1024/256 */
10628 REG_WR(sc, BRB1_REG_PAUSE_LOW_THRESHOLD_0 + port * 4, low);
10629 REG_WR(sc, BRB1_REG_PAUSE_HIGH_THRESHOLD_0 + port * 4, high);
10632 if (CHIP_IS_MODE_4_PORT(sc)) {
10633 REG_WR(sc, SC_PORT(sc) ?
10634 BRB1_REG_MAC_GUARANTIED_1 :
10635 BRB1_REG_MAC_GUARANTIED_0, 40);
10638 ecore_init_block(sc, BLOCK_PRS, init_phase);
10639 if (CHIP_IS_E3B0(sc)) {
10640 if (IS_MF_AFEX(sc)) {
10641 /* configure headers for AFEX mode */
10643 REG_WR(sc, PRS_REG_HDRS_AFTER_BASIC_PORT_1,
10645 REG_WR(sc, PRS_REG_HDRS_AFTER_TAG_0_PORT_1,
10647 REG_WR(sc, PRS_REG_MUST_HAVE_HDRS_PORT_1, 0xA);
10649 REG_WR(sc, PRS_REG_HDRS_AFTER_BASIC_PORT_0,
10651 REG_WR(sc, PRS_REG_HDRS_AFTER_TAG_0_PORT_0,
10653 REG_WR(sc, PRS_REG_MUST_HAVE_HDRS_PORT_0, 0xA);
10656 /* Ovlan exists only if we are in multi-function +
10657 * switch-dependent mode, in switch-independent there
10658 * is no ovlan headers
10660 REG_WR(sc, SC_PORT(sc) ?
10661 PRS_REG_HDRS_AFTER_BASIC_PORT_1 :
10662 PRS_REG_HDRS_AFTER_BASIC_PORT_0,
10663 (sc->devinfo.mf_info.path_has_ovlan ? 7 : 6));
10667 ecore_init_block(sc, BLOCK_TSDM, init_phase);
10668 ecore_init_block(sc, BLOCK_CSDM, init_phase);
10669 ecore_init_block(sc, BLOCK_USDM, init_phase);
10670 ecore_init_block(sc, BLOCK_XSDM, init_phase);
10672 ecore_init_block(sc, BLOCK_TSEM, init_phase);
10673 ecore_init_block(sc, BLOCK_USEM, init_phase);
10674 ecore_init_block(sc, BLOCK_CSEM, init_phase);
10675 ecore_init_block(sc, BLOCK_XSEM, init_phase);
10677 ecore_init_block(sc, BLOCK_UPB, init_phase);
10678 ecore_init_block(sc, BLOCK_XPB, init_phase);
10680 ecore_init_block(sc, BLOCK_PBF, init_phase);
10682 if (CHIP_IS_E1x(sc)) {
10683 /* configure PBF to work without PAUSE mtu 9000 */
10684 REG_WR(sc, PBF_REG_P0_PAUSE_ENABLE + port * 4, 0);
10686 /* update threshold */
10687 REG_WR(sc, PBF_REG_P0_ARB_THRSH + port * 4, (9040 / 16));
10688 /* update init credit */
10689 REG_WR(sc, PBF_REG_P0_INIT_CRD + port * 4,
10690 (9040 / 16) + 553 - 22);
10692 /* probe changes */
10693 REG_WR(sc, PBF_REG_INIT_P0 + port * 4, 1);
10695 REG_WR(sc, PBF_REG_INIT_P0 + port * 4, 0);
10698 if (CNIC_SUPPORT(sc)) {
10699 ecore_init_block(sc, BLOCK_SRC, init_phase);
10702 ecore_init_block(sc, BLOCK_CDU, init_phase);
10703 ecore_init_block(sc, BLOCK_CFC, init_phase);
10704 ecore_init_block(sc, BLOCK_HC, init_phase);
10705 ecore_init_block(sc, BLOCK_IGU, init_phase);
10706 ecore_init_block(sc, BLOCK_MISC_AEU, init_phase);
10707 /* init aeu_mask_attn_func_0/1:
10708 * - SF mode: bits 3-7 are masked. only bits 0-2 are in use
10709 * - MF mode: bit 3 is masked. bits 0-2 are in use as in SF
10710 * bits 4-7 are used for "per vn group attention" */
10711 val = IS_MF(sc) ? 0xF7 : 0x7;
10713 REG_WR(sc, MISC_REG_AEU_MASK_ATTN_FUNC_0 + port * 4, val);
10715 ecore_init_block(sc, BLOCK_NIG, init_phase);
10717 if (!CHIP_IS_E1x(sc)) {
10718 /* Bit-map indicating which L2 hdrs may appear after the
10719 * basic Ethernet header
10721 if (IS_MF_AFEX(sc)) {
10722 REG_WR(sc, SC_PORT(sc) ?
10723 NIG_REG_P1_HDRS_AFTER_BASIC :
10724 NIG_REG_P0_HDRS_AFTER_BASIC, 0xE);
10726 REG_WR(sc, SC_PORT(sc) ?
10727 NIG_REG_P1_HDRS_AFTER_BASIC :
10728 NIG_REG_P0_HDRS_AFTER_BASIC,
10729 IS_MF_SD(sc) ? 7 : 6);
10732 if (CHIP_IS_E3(sc)) {
10733 REG_WR(sc, SC_PORT(sc) ?
10734 NIG_REG_LLH1_MF_MODE :
10735 NIG_REG_LLH_MF_MODE, IS_MF(sc));
10738 if (!CHIP_IS_E3(sc)) {
10739 REG_WR(sc, NIG_REG_XGXS_SERDES0_MODE_SEL + port * 4, 1);
10742 /* 0x2 disable mf_ov, 0x1 enable */
10743 REG_WR(sc, NIG_REG_LLH0_BRB1_DRV_MASK_MF + port * 4,
10744 (IS_MF_SD(sc) ? 0x1 : 0x2));
10746 if (!CHIP_IS_E1x(sc)) {
10748 switch (sc->devinfo.mf_info.mf_mode) {
10749 case MULTI_FUNCTION_SD:
10752 case MULTI_FUNCTION_SI:
10753 case MULTI_FUNCTION_AFEX:
10758 REG_WR(sc, (SC_PORT(sc) ? NIG_REG_LLH1_CLS_TYPE :
10759 NIG_REG_LLH0_CLS_TYPE), val);
10761 REG_WR(sc, NIG_REG_LLFC_ENABLE_0 + port * 4, 0);
10762 REG_WR(sc, NIG_REG_LLFC_OUT_EN_0 + port * 4, 0);
10763 REG_WR(sc, NIG_REG_PAUSE_ENABLE_0 + port * 4, 1);
10765 /* If SPIO5 is set to generate interrupts, enable it for this port */
10766 val = REG_RD(sc, MISC_REG_SPIO_EVENT_EN);
10767 if (val & MISC_SPIO_SPIO5) {
10768 uint32_t reg_addr = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 :
10769 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0);
10770 val = REG_RD(sc, reg_addr);
10771 val |= AEU_INPUTS_ATTN_BITS_SPIO5;
10772 REG_WR(sc, reg_addr, val);
10779 bnx2x_flr_clnup_reg_poll(struct bnx2x_softc *sc, uint32_t reg,
10780 uint32_t expected, uint32_t poll_count)
10782 uint32_t cur_cnt = poll_count;
10785 while ((val = REG_RD(sc, reg)) != expected && cur_cnt--) {
10786 DELAY(FLR_WAIT_INTERVAL);
10793 bnx2x_flr_clnup_poll_hw_counter(struct bnx2x_softc *sc, uint32_t reg,
10794 __rte_unused const char *msg, uint32_t poll_cnt)
10796 uint32_t val = bnx2x_flr_clnup_reg_poll(sc, reg, 0, poll_cnt);
10799 PMD_DRV_LOG(NOTICE, sc, "%s usage count=%d", msg, val);
10806 /* Common routines with VF FLR cleanup */
10807 static uint32_t bnx2x_flr_clnup_poll_count(struct bnx2x_softc *sc)
10809 /* adjust polling timeout */
10810 if (CHIP_REV_IS_EMUL(sc)) {
10811 return FLR_POLL_CNT * 2000;
10814 if (CHIP_REV_IS_FPGA(sc)) {
10815 return FLR_POLL_CNT * 120;
10818 return FLR_POLL_CNT;
10821 static int bnx2x_poll_hw_usage_counters(struct bnx2x_softc *sc, uint32_t poll_cnt)
10823 /* wait for CFC PF usage-counter to zero (includes all the VFs) */
10824 if (bnx2x_flr_clnup_poll_hw_counter(sc,
10825 CFC_REG_NUM_LCIDS_INSIDE_PF,
10826 "CFC PF usage counter timed out",
10831 /* Wait for DQ PF usage-counter to zero (until DQ cleanup) */
10832 if (bnx2x_flr_clnup_poll_hw_counter(sc,
10833 DORQ_REG_PF_USAGE_CNT,
10834 "DQ PF usage counter timed out",
10839 /* Wait for QM PF usage-counter to zero (until DQ cleanup) */
10840 if (bnx2x_flr_clnup_poll_hw_counter(sc,
10841 QM_REG_PF_USG_CNT_0 + 4 * SC_FUNC(sc),
10842 "QM PF usage counter timed out",
10847 /* Wait for Timer PF usage-counters to zero (until DQ cleanup) */
10848 if (bnx2x_flr_clnup_poll_hw_counter(sc,
10849 TM_REG_LIN0_VNIC_UC + 4 * SC_PORT(sc),
10850 "Timers VNIC usage counter timed out",
10855 if (bnx2x_flr_clnup_poll_hw_counter(sc,
10856 TM_REG_LIN0_NUM_SCANS +
10858 "Timers NUM_SCANS usage counter timed out",
10863 /* Wait DMAE PF usage counter to zero */
10864 if (bnx2x_flr_clnup_poll_hw_counter(sc,
10865 dmae_reg_go_c[INIT_DMAE_C(sc)],
10866 "DMAE dommand register timed out",
10874 #define OP_GEN_PARAM(param) \
10875 (((param) << SDM_OP_GEN_COMP_PARAM_SHIFT) & SDM_OP_GEN_COMP_PARAM)
10876 #define OP_GEN_TYPE(type) \
10877 (((type) << SDM_OP_GEN_COMP_TYPE_SHIFT) & SDM_OP_GEN_COMP_TYPE)
10878 #define OP_GEN_AGG_VECT(index) \
10879 (((index) << SDM_OP_GEN_AGG_VECT_IDX_SHIFT) & SDM_OP_GEN_AGG_VECT_IDX)
10882 bnx2x_send_final_clnup(struct bnx2x_softc *sc, uint8_t clnup_func,
10885 uint32_t op_gen_command = 0;
10886 uint32_t comp_addr = (BAR_CSTRORM_INTMEM +
10887 CSTORM_FINAL_CLEANUP_COMPLETE_OFFSET(clnup_func));
10890 if (REG_RD(sc, comp_addr)) {
10891 PMD_DRV_LOG(NOTICE, sc,
10892 "Cleanup complete was not 0 before sending");
10896 op_gen_command |= OP_GEN_PARAM(XSTORM_AGG_INT_FINAL_CLEANUP_INDEX);
10897 op_gen_command |= OP_GEN_TYPE(XSTORM_AGG_INT_FINAL_CLEANUP_COMP_TYPE);
10898 op_gen_command |= OP_GEN_AGG_VECT(clnup_func);
10899 op_gen_command |= 1 << SDM_OP_GEN_AGG_VECT_IDX_VALID_SHIFT;
10901 REG_WR(sc, XSDM_REG_OPERATION_GEN, op_gen_command);
10903 if (bnx2x_flr_clnup_reg_poll(sc, comp_addr, 1, poll_cnt) != 1) {
10904 PMD_DRV_LOG(NOTICE, sc, "FW final cleanup did not succeed");
10905 PMD_DRV_LOG(DEBUG, sc, "At timeout completion address contained %x",
10906 (REG_RD(sc, comp_addr)));
10907 rte_panic("FLR cleanup failed");
10911 /* Zero completion for nxt FLR */
10912 REG_WR(sc, comp_addr, 0);
10918 bnx2x_pbf_pN_buf_flushed(struct bnx2x_softc *sc, struct pbf_pN_buf_regs *regs,
10919 uint32_t poll_count)
10921 uint32_t init_crd, crd, crd_start, crd_freed, crd_freed_start;
10922 uint32_t cur_cnt = poll_count;
10924 crd_freed = crd_freed_start = REG_RD(sc, regs->crd_freed);
10925 crd = crd_start = REG_RD(sc, regs->crd);
10926 init_crd = REG_RD(sc, regs->init_crd);
10928 while ((crd != init_crd) &&
10929 ((uint32_t) ((int32_t) crd_freed - (int32_t) crd_freed_start) <
10930 (init_crd - crd_start))) {
10932 DELAY(FLR_WAIT_INTERVAL);
10933 crd = REG_RD(sc, regs->crd);
10934 crd_freed = REG_RD(sc, regs->crd_freed);
10942 bnx2x_pbf_pN_cmd_flushed(struct bnx2x_softc *sc, struct pbf_pN_cmd_regs *regs,
10943 uint32_t poll_count)
10945 uint32_t occup, to_free, freed, freed_start;
10946 uint32_t cur_cnt = poll_count;
10948 occup = to_free = REG_RD(sc, regs->lines_occup);
10949 freed = freed_start = REG_RD(sc, regs->lines_freed);
10952 ((uint32_t) ((int32_t) freed - (int32_t) freed_start) <
10955 DELAY(FLR_WAIT_INTERVAL);
10956 occup = REG_RD(sc, regs->lines_occup);
10957 freed = REG_RD(sc, regs->lines_freed);
10964 static void bnx2x_tx_hw_flushed(struct bnx2x_softc *sc, uint32_t poll_count)
10966 struct pbf_pN_cmd_regs cmd_regs[] = {
10967 {0, (CHIP_IS_E3B0(sc)) ?
10968 PBF_REG_TQ_OCCUPANCY_Q0 : PBF_REG_P0_TQ_OCCUPANCY,
10969 (CHIP_IS_E3B0(sc)) ?
10970 PBF_REG_TQ_LINES_FREED_CNT_Q0 : PBF_REG_P0_TQ_LINES_FREED_CNT},
10971 {1, (CHIP_IS_E3B0(sc)) ?
10972 PBF_REG_TQ_OCCUPANCY_Q1 : PBF_REG_P1_TQ_OCCUPANCY,
10973 (CHIP_IS_E3B0(sc)) ?
10974 PBF_REG_TQ_LINES_FREED_CNT_Q1 : PBF_REG_P1_TQ_LINES_FREED_CNT},
10975 {4, (CHIP_IS_E3B0(sc)) ?
10976 PBF_REG_TQ_OCCUPANCY_LB_Q : PBF_REG_P4_TQ_OCCUPANCY,
10977 (CHIP_IS_E3B0(sc)) ?
10978 PBF_REG_TQ_LINES_FREED_CNT_LB_Q :
10979 PBF_REG_P4_TQ_LINES_FREED_CNT}
10982 struct pbf_pN_buf_regs buf_regs[] = {
10983 {0, (CHIP_IS_E3B0(sc)) ?
10984 PBF_REG_INIT_CRD_Q0 : PBF_REG_P0_INIT_CRD,
10985 (CHIP_IS_E3B0(sc)) ? PBF_REG_CREDIT_Q0 : PBF_REG_P0_CREDIT,
10986 (CHIP_IS_E3B0(sc)) ?
10987 PBF_REG_INTERNAL_CRD_FREED_CNT_Q0 :
10988 PBF_REG_P0_INTERNAL_CRD_FREED_CNT},
10989 {1, (CHIP_IS_E3B0(sc)) ?
10990 PBF_REG_INIT_CRD_Q1 : PBF_REG_P1_INIT_CRD,
10991 (CHIP_IS_E3B0(sc)) ? PBF_REG_CREDIT_Q1 : PBF_REG_P1_CREDIT,
10992 (CHIP_IS_E3B0(sc)) ?
10993 PBF_REG_INTERNAL_CRD_FREED_CNT_Q1 :
10994 PBF_REG_P1_INTERNAL_CRD_FREED_CNT},
10995 {4, (CHIP_IS_E3B0(sc)) ?
10996 PBF_REG_INIT_CRD_LB_Q : PBF_REG_P4_INIT_CRD,
10997 (CHIP_IS_E3B0(sc)) ? PBF_REG_CREDIT_LB_Q : PBF_REG_P4_CREDIT,
10998 (CHIP_IS_E3B0(sc)) ?
10999 PBF_REG_INTERNAL_CRD_FREED_CNT_LB_Q :
11000 PBF_REG_P4_INTERNAL_CRD_FREED_CNT},
11005 /* Verify the command queues are flushed P0, P1, P4 */
11006 for (i = 0; i < ARRAY_SIZE(cmd_regs); i++) {
11007 bnx2x_pbf_pN_cmd_flushed(sc, &cmd_regs[i], poll_count);
11010 /* Verify the transmission buffers are flushed P0, P1, P4 */
11011 for (i = 0; i < ARRAY_SIZE(buf_regs); i++) {
11012 bnx2x_pbf_pN_buf_flushed(sc, &buf_regs[i], poll_count);
11016 static void bnx2x_hw_enable_status(struct bnx2x_softc *sc)
11018 __rte_unused uint32_t val;
11020 val = REG_RD(sc, CFC_REG_WEAK_ENABLE_PF);
11021 PMD_DRV_LOG(DEBUG, sc, "CFC_REG_WEAK_ENABLE_PF is 0x%x", val);
11023 val = REG_RD(sc, PBF_REG_DISABLE_PF);
11024 PMD_DRV_LOG(DEBUG, sc, "PBF_REG_DISABLE_PF is 0x%x", val);
11026 val = REG_RD(sc, IGU_REG_PCI_PF_MSI_EN);
11027 PMD_DRV_LOG(DEBUG, sc, "IGU_REG_PCI_PF_MSI_EN is 0x%x", val);
11029 val = REG_RD(sc, IGU_REG_PCI_PF_MSIX_EN);
11030 PMD_DRV_LOG(DEBUG, sc, "IGU_REG_PCI_PF_MSIX_EN is 0x%x", val);
11032 val = REG_RD(sc, IGU_REG_PCI_PF_MSIX_FUNC_MASK);
11033 PMD_DRV_LOG(DEBUG, sc, "IGU_REG_PCI_PF_MSIX_FUNC_MASK is 0x%x", val);
11035 val = REG_RD(sc, PGLUE_B_REG_SHADOW_BME_PF_7_0_CLR);
11036 PMD_DRV_LOG(DEBUG, sc,
11037 "PGLUE_B_REG_SHADOW_BME_PF_7_0_CLR is 0x%x", val);
11039 val = REG_RD(sc, PGLUE_B_REG_FLR_REQUEST_PF_7_0_CLR);
11040 PMD_DRV_LOG(DEBUG, sc,
11041 "PGLUE_B_REG_FLR_REQUEST_PF_7_0_CLR is 0x%x", val);
11043 val = REG_RD(sc, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER);
11044 PMD_DRV_LOG(DEBUG, sc, "PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER is 0x%x",
11049 * bnx2x_pf_flr_clnup
11050 * a. re-enable target read on the PF
11051 * b. poll cfc per function usgae counter
11052 * c. poll the qm perfunction usage counter
11053 * d. poll the tm per function usage counter
11054 * e. poll the tm per function scan-done indication
11055 * f. clear the dmae channel associated wit hthe PF
11056 * g. zero the igu 'trailing edge' and 'leading edge' regs (attentions)
11057 * h. call the common flr cleanup code with -1 (pf indication)
11059 static int bnx2x_pf_flr_clnup(struct bnx2x_softc *sc)
11061 uint32_t poll_cnt = bnx2x_flr_clnup_poll_count(sc);
11063 /* Re-enable PF target read access */
11064 REG_WR(sc, PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ, 1);
11066 /* Poll HW usage counters */
11067 if (bnx2x_poll_hw_usage_counters(sc, poll_cnt)) {
11071 /* Zero the igu 'trailing edge' and 'leading edge' */
11073 /* Send the FW cleanup command */
11074 if (bnx2x_send_final_clnup(sc, (uint8_t) SC_FUNC(sc), poll_cnt)) {
11080 /* Verify TX hw is flushed */
11081 bnx2x_tx_hw_flushed(sc, poll_cnt);
11083 /* Wait 100ms (not adjusted according to platform) */
11086 /* Verify no pending pci transactions */
11087 if (bnx2x_is_pcie_pending(sc)) {
11088 PMD_DRV_LOG(NOTICE, sc, "PCIE Transactions still pending");
11092 bnx2x_hw_enable_status(sc);
11095 * Master enable - Due to WB DMAE writes performed before this
11096 * register is re-initialized as part of the regular function init
11098 REG_WR(sc, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1);
11103 static int bnx2x_init_hw_func(struct bnx2x_softc *sc)
11105 int port = SC_PORT(sc);
11106 int func = SC_FUNC(sc);
11107 int init_phase = PHASE_PF0 + func;
11108 struct ecore_ilt *ilt = sc->ilt;
11109 uint16_t cdu_ilt_start;
11110 uint32_t addr, val;
11111 uint32_t main_mem_base, main_mem_size, main_mem_prty_clr;
11112 int main_mem_width, rc;
11115 PMD_DRV_LOG(DEBUG, sc, "starting func init for func %d", func);
11118 if (!CHIP_IS_E1x(sc)) {
11119 rc = bnx2x_pf_flr_clnup(sc);
11121 PMD_DRV_LOG(NOTICE, sc, "FLR cleanup failed!");
11126 /* set MSI reconfigure capability */
11127 if (sc->devinfo.int_block == INT_BLOCK_HC) {
11128 addr = (port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0);
11129 val = REG_RD(sc, addr);
11130 val |= HC_CONFIG_0_REG_MSI_ATTN_EN_0;
11131 REG_WR(sc, addr, val);
11134 ecore_init_block(sc, BLOCK_PXP, init_phase);
11135 ecore_init_block(sc, BLOCK_PXP2, init_phase);
11138 cdu_ilt_start = ilt->clients[ILT_CLIENT_CDU].start;
11140 for (i = 0; i < L2_ILT_LINES(sc); i++) {
11141 ilt->lines[cdu_ilt_start + i].page = sc->context[i].vcxt;
11142 ilt->lines[cdu_ilt_start + i].page_mapping =
11143 (phys_addr_t)sc->context[i].vcxt_dma.paddr;
11144 ilt->lines[cdu_ilt_start + i].size = sc->context[i].size;
11146 ecore_ilt_init_op(sc, INITOP_SET);
11148 REG_WR(sc, PRS_REG_NIC_MODE, 1);
11150 if (!CHIP_IS_E1x(sc)) {
11151 uint32_t pf_conf = IGU_PF_CONF_FUNC_EN;
11153 /* Turn on a single ISR mode in IGU if driver is going to use
11156 if ((sc->interrupt_mode != INTR_MODE_MSIX)
11157 || (sc->interrupt_mode != INTR_MODE_SINGLE_MSIX)) {
11158 pf_conf |= IGU_PF_CONF_SINGLE_ISR_EN;
11162 * Timers workaround bug: function init part.
11163 * Need to wait 20msec after initializing ILT,
11164 * needed to make sure there are no requests in
11165 * one of the PXP internal queues with "old" ILT addresses
11170 * Master enable - Due to WB DMAE writes performed before this
11171 * register is re-initialized as part of the regular function
11174 REG_WR(sc, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1);
11175 /* Enable the function in IGU */
11176 REG_WR(sc, IGU_REG_PF_CONFIGURATION, pf_conf);
11179 sc->dmae_ready = 1;
11181 ecore_init_block(sc, BLOCK_PGLUE_B, init_phase);
11183 if (!CHIP_IS_E1x(sc))
11184 REG_WR(sc, PGLUE_B_REG_WAS_ERROR_PF_7_0_CLR, func);
11186 ecore_init_block(sc, BLOCK_ATC, init_phase);
11187 ecore_init_block(sc, BLOCK_DMAE, init_phase);
11188 ecore_init_block(sc, BLOCK_NIG, init_phase);
11189 ecore_init_block(sc, BLOCK_SRC, init_phase);
11190 ecore_init_block(sc, BLOCK_MISC, init_phase);
11191 ecore_init_block(sc, BLOCK_TCM, init_phase);
11192 ecore_init_block(sc, BLOCK_UCM, init_phase);
11193 ecore_init_block(sc, BLOCK_CCM, init_phase);
11194 ecore_init_block(sc, BLOCK_XCM, init_phase);
11195 ecore_init_block(sc, BLOCK_TSEM, init_phase);
11196 ecore_init_block(sc, BLOCK_USEM, init_phase);
11197 ecore_init_block(sc, BLOCK_CSEM, init_phase);
11198 ecore_init_block(sc, BLOCK_XSEM, init_phase);
11200 if (!CHIP_IS_E1x(sc))
11201 REG_WR(sc, QM_REG_PF_EN, 1);
11203 if (!CHIP_IS_E1x(sc)) {
11204 REG_WR(sc, TSEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func);
11205 REG_WR(sc, USEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func);
11206 REG_WR(sc, CSEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func);
11207 REG_WR(sc, XSEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func);
11209 ecore_init_block(sc, BLOCK_QM, init_phase);
11211 ecore_init_block(sc, BLOCK_TM, init_phase);
11212 ecore_init_block(sc, BLOCK_DORQ, init_phase);
11214 ecore_init_block(sc, BLOCK_BRB1, init_phase);
11215 ecore_init_block(sc, BLOCK_PRS, init_phase);
11216 ecore_init_block(sc, BLOCK_TSDM, init_phase);
11217 ecore_init_block(sc, BLOCK_CSDM, init_phase);
11218 ecore_init_block(sc, BLOCK_USDM, init_phase);
11219 ecore_init_block(sc, BLOCK_XSDM, init_phase);
11220 ecore_init_block(sc, BLOCK_UPB, init_phase);
11221 ecore_init_block(sc, BLOCK_XPB, init_phase);
11222 ecore_init_block(sc, BLOCK_PBF, init_phase);
11223 if (!CHIP_IS_E1x(sc))
11224 REG_WR(sc, PBF_REG_DISABLE_PF, 0);
11226 ecore_init_block(sc, BLOCK_CDU, init_phase);
11228 ecore_init_block(sc, BLOCK_CFC, init_phase);
11230 if (!CHIP_IS_E1x(sc))
11231 REG_WR(sc, CFC_REG_WEAK_ENABLE_PF, 1);
11234 REG_WR(sc, NIG_REG_LLH0_FUNC_EN + port * 8, 1);
11235 REG_WR(sc, NIG_REG_LLH0_FUNC_VLAN_ID + port * 8, OVLAN(sc));
11238 ecore_init_block(sc, BLOCK_MISC_AEU, init_phase);
11240 /* HC init per function */
11241 if (sc->devinfo.int_block == INT_BLOCK_HC) {
11242 if (CHIP_IS_E1H(sc)) {
11243 REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_12 + func * 4, 0);
11245 REG_WR(sc, HC_REG_LEADING_EDGE_0 + port * 8, 0);
11246 REG_WR(sc, HC_REG_TRAILING_EDGE_0 + port * 8, 0);
11248 ecore_init_block(sc, BLOCK_HC, init_phase);
11251 uint32_t num_segs, sb_idx, prod_offset;
11253 REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_12 + func * 4, 0);
11255 if (!CHIP_IS_E1x(sc)) {
11256 REG_WR(sc, IGU_REG_LEADING_EDGE_LATCH, 0);
11257 REG_WR(sc, IGU_REG_TRAILING_EDGE_LATCH, 0);
11260 ecore_init_block(sc, BLOCK_IGU, init_phase);
11262 if (!CHIP_IS_E1x(sc)) {
11266 * E2 mode: address 0-135 match to the mapping memory;
11267 * 136 - PF0 default prod; 137 - PF1 default prod;
11268 * 138 - PF2 default prod; 139 - PF3 default prod;
11269 * 140 - PF0 attn prod; 141 - PF1 attn prod;
11270 * 142 - PF2 attn prod; 143 - PF3 attn prod;
11271 * 144-147 reserved.
11273 * E1.5 mode - In backward compatible mode;
11274 * for non default SB; each even line in the memory
11275 * holds the U producer and each odd line hold
11276 * the C producer. The first 128 producers are for
11277 * NDSB (PF0 - 0-31; PF1 - 32-63 and so on). The last 20
11278 * producers are for the DSB for each PF.
11279 * Each PF has five segments: (the order inside each
11280 * segment is PF0; PF1; PF2; PF3) - 128-131 U prods;
11281 * 132-135 C prods; 136-139 X prods; 140-143 T prods;
11282 * 144-147 attn prods;
11284 /* non-default-status-blocks */
11285 num_segs = CHIP_INT_MODE_IS_BC(sc) ?
11286 IGU_BC_NDSB_NUM_SEGS : IGU_NORM_NDSB_NUM_SEGS;
11287 for (sb_idx = 0; sb_idx < sc->igu_sb_cnt; sb_idx++) {
11288 prod_offset = (sc->igu_base_sb + sb_idx) *
11291 for (i = 0; i < num_segs; i++) {
11292 addr = IGU_REG_PROD_CONS_MEMORY +
11293 (prod_offset + i) * 4;
11294 REG_WR(sc, addr, 0);
11296 /* send consumer update with value 0 */
11297 bnx2x_ack_sb(sc, sc->igu_base_sb + sb_idx,
11298 USTORM_ID, 0, IGU_INT_NOP, 1);
11299 bnx2x_igu_clear_sb(sc, sc->igu_base_sb + sb_idx);
11302 /* default-status-blocks */
11303 num_segs = CHIP_INT_MODE_IS_BC(sc) ?
11304 IGU_BC_DSB_NUM_SEGS : IGU_NORM_DSB_NUM_SEGS;
11306 if (CHIP_IS_MODE_4_PORT(sc))
11307 dsb_idx = SC_FUNC(sc);
11309 dsb_idx = SC_VN(sc);
11311 prod_offset = (CHIP_INT_MODE_IS_BC(sc) ?
11312 IGU_BC_BASE_DSB_PROD + dsb_idx :
11313 IGU_NORM_BASE_DSB_PROD + dsb_idx);
11316 * igu prods come in chunks of E1HVN_MAX (4) -
11317 * does not matters what is the current chip mode
11319 for (i = 0; i < (num_segs * E1HVN_MAX); i += E1HVN_MAX) {
11320 addr = IGU_REG_PROD_CONS_MEMORY +
11321 (prod_offset + i) * 4;
11322 REG_WR(sc, addr, 0);
11324 /* send consumer update with 0 */
11325 if (CHIP_INT_MODE_IS_BC(sc)) {
11326 bnx2x_ack_sb(sc, sc->igu_dsb_id,
11327 USTORM_ID, 0, IGU_INT_NOP, 1);
11328 bnx2x_ack_sb(sc, sc->igu_dsb_id,
11329 CSTORM_ID, 0, IGU_INT_NOP, 1);
11330 bnx2x_ack_sb(sc, sc->igu_dsb_id,
11331 XSTORM_ID, 0, IGU_INT_NOP, 1);
11332 bnx2x_ack_sb(sc, sc->igu_dsb_id,
11333 TSTORM_ID, 0, IGU_INT_NOP, 1);
11334 bnx2x_ack_sb(sc, sc->igu_dsb_id,
11335 ATTENTION_ID, 0, IGU_INT_NOP, 1);
11337 bnx2x_ack_sb(sc, sc->igu_dsb_id,
11338 USTORM_ID, 0, IGU_INT_NOP, 1);
11339 bnx2x_ack_sb(sc, sc->igu_dsb_id,
11340 ATTENTION_ID, 0, IGU_INT_NOP, 1);
11342 bnx2x_igu_clear_sb(sc, sc->igu_dsb_id);
11344 /* !!! these should become driver const once
11345 rf-tool supports split-68 const */
11346 REG_WR(sc, IGU_REG_SB_INT_BEFORE_MASK_LSB, 0);
11347 REG_WR(sc, IGU_REG_SB_INT_BEFORE_MASK_MSB, 0);
11348 REG_WR(sc, IGU_REG_SB_MASK_LSB, 0);
11349 REG_WR(sc, IGU_REG_SB_MASK_MSB, 0);
11350 REG_WR(sc, IGU_REG_PBA_STATUS_LSB, 0);
11351 REG_WR(sc, IGU_REG_PBA_STATUS_MSB, 0);
11355 /* Reset PCIE errors for debug */
11356 REG_WR(sc, 0x2114, 0xffffffff);
11357 REG_WR(sc, 0x2120, 0xffffffff);
11359 if (CHIP_IS_E1x(sc)) {
11360 main_mem_size = HC_REG_MAIN_MEMORY_SIZE / 2; /*dwords */
11361 main_mem_base = HC_REG_MAIN_MEMORY +
11362 SC_PORT(sc) * (main_mem_size * 4);
11363 main_mem_prty_clr = HC_REG_HC_PRTY_STS_CLR;
11364 main_mem_width = 8;
11366 val = REG_RD(sc, main_mem_prty_clr);
11368 PMD_DRV_LOG(DEBUG, sc,
11369 "Parity errors in HC block during function init (0x%x)!",
11373 /* Clear "false" parity errors in MSI-X table */
11374 for (i = main_mem_base;
11375 i < main_mem_base + main_mem_size * 4;
11376 i += main_mem_width) {
11377 bnx2x_read_dmae(sc, i, main_mem_width / 4);
11378 bnx2x_write_dmae(sc, BNX2X_SP_MAPPING(sc, wb_data),
11379 i, main_mem_width / 4);
11381 /* Clear HC parity attention */
11382 REG_RD(sc, main_mem_prty_clr);
11385 /* Enable STORMs SP logging */
11386 REG_WR8(sc, BAR_USTRORM_INTMEM +
11387 USTORM_RECORD_SLOW_PATH_OFFSET(SC_FUNC(sc)), 1);
11388 REG_WR8(sc, BAR_TSTRORM_INTMEM +
11389 TSTORM_RECORD_SLOW_PATH_OFFSET(SC_FUNC(sc)), 1);
11390 REG_WR8(sc, BAR_CSTRORM_INTMEM +
11391 CSTORM_RECORD_SLOW_PATH_OFFSET(SC_FUNC(sc)), 1);
11392 REG_WR8(sc, BAR_XSTRORM_INTMEM +
11393 XSTORM_RECORD_SLOW_PATH_OFFSET(SC_FUNC(sc)), 1);
11395 elink_phy_probe(&sc->link_params);
11400 static void bnx2x_link_reset(struct bnx2x_softc *sc)
11402 if (!BNX2X_NOMCP(sc)) {
11403 bnx2x_acquire_phy_lock(sc);
11404 elink_lfa_reset(&sc->link_params, &sc->link_vars);
11405 bnx2x_release_phy_lock(sc);
11407 if (!CHIP_REV_IS_SLOW(sc)) {
11408 PMD_DRV_LOG(WARNING, sc,
11409 "Bootcode is missing - cannot reset link");
11414 static void bnx2x_reset_port(struct bnx2x_softc *sc)
11416 int port = SC_PORT(sc);
11419 /* reset physical Link */
11420 bnx2x_link_reset(sc);
11422 REG_WR(sc, NIG_REG_MASK_INTERRUPT_PORT0 + port * 4, 0);
11424 /* Do not rcv packets to BRB */
11425 REG_WR(sc, NIG_REG_LLH0_BRB1_DRV_MASK + port * 4, 0x0);
11426 /* Do not direct rcv packets that are not for MCP to the BRB */
11427 REG_WR(sc, (port ? NIG_REG_LLH1_BRB1_NOT_MCP :
11428 NIG_REG_LLH0_BRB1_NOT_MCP), 0x0);
11430 /* Configure AEU */
11431 REG_WR(sc, MISC_REG_AEU_MASK_ATTN_FUNC_0 + port * 4, 0);
11435 /* Check for BRB port occupancy */
11436 val = REG_RD(sc, BRB1_REG_PORT_NUM_OCC_BLOCKS_0 + port * 4);
11438 PMD_DRV_LOG(DEBUG, sc,
11439 "BRB1 is not empty, %d blocks are occupied", val);
11443 static void bnx2x_ilt_wr(struct bnx2x_softc *sc, uint32_t index, phys_addr_t addr)
11446 uint32_t wb_write[2];
11448 reg = PXP2_REG_RQ_ONCHIP_AT_B0 + index * 8;
11450 wb_write[0] = ONCHIP_ADDR1(addr);
11451 wb_write[1] = ONCHIP_ADDR2(addr);
11452 REG_WR_DMAE(sc, reg, wb_write, 2);
11455 static void bnx2x_clear_func_ilt(struct bnx2x_softc *sc, uint32_t func)
11457 uint32_t i, base = FUNC_ILT_BASE(func);
11458 for (i = base; i < base + ILT_PER_FUNC; i++) {
11459 bnx2x_ilt_wr(sc, i, 0);
11463 static void bnx2x_reset_func(struct bnx2x_softc *sc)
11465 struct bnx2x_fastpath *fp;
11466 int port = SC_PORT(sc);
11467 int func = SC_FUNC(sc);
11470 /* Disable the function in the FW */
11471 REG_WR8(sc, BAR_XSTRORM_INTMEM + XSTORM_FUNC_EN_OFFSET(func), 0);
11472 REG_WR8(sc, BAR_CSTRORM_INTMEM + CSTORM_FUNC_EN_OFFSET(func), 0);
11473 REG_WR8(sc, BAR_TSTRORM_INTMEM + TSTORM_FUNC_EN_OFFSET(func), 0);
11474 REG_WR8(sc, BAR_USTRORM_INTMEM + USTORM_FUNC_EN_OFFSET(func), 0);
11477 FOR_EACH_ETH_QUEUE(sc, i) {
11479 REG_WR8(sc, BAR_CSTRORM_INTMEM +
11480 CSTORM_STATUS_BLOCK_DATA_STATE_OFFSET(fp->fw_sb_id),
11485 REG_WR8(sc, BAR_CSTRORM_INTMEM +
11486 CSTORM_SP_STATUS_BLOCK_DATA_STATE_OFFSET(func), SB_DISABLED);
11488 for (i = 0; i < XSTORM_SPQ_DATA_SIZE / 4; i++) {
11489 REG_WR(sc, BAR_XSTRORM_INTMEM + XSTORM_SPQ_DATA_OFFSET(func),
11493 /* Configure IGU */
11494 if (sc->devinfo.int_block == INT_BLOCK_HC) {
11495 REG_WR(sc, HC_REG_LEADING_EDGE_0 + port * 8, 0);
11496 REG_WR(sc, HC_REG_TRAILING_EDGE_0 + port * 8, 0);
11498 REG_WR(sc, IGU_REG_LEADING_EDGE_LATCH, 0);
11499 REG_WR(sc, IGU_REG_TRAILING_EDGE_LATCH, 0);
11502 if (CNIC_LOADED(sc)) {
11503 /* Disable Timer scan */
11504 REG_WR(sc, TM_REG_EN_LINEAR0_TIMER + port * 4, 0);
11506 * Wait for at least 10ms and up to 2 second for the timers
11509 for (i = 0; i < 200; i++) {
11511 if (!REG_RD(sc, TM_REG_LIN0_SCAN_ON + port * 4))
11517 bnx2x_clear_func_ilt(sc, func);
11520 * Timers workaround bug for E2: if this is vnic-3,
11521 * we need to set the entire ilt range for this timers.
11523 if (!CHIP_IS_E1x(sc) && SC_VN(sc) == 3) {
11524 struct ilt_client_info ilt_cli;
11525 /* use dummy TM client */
11526 memset(&ilt_cli, 0, sizeof(struct ilt_client_info));
11528 ilt_cli.end = ILT_NUM_PAGE_ENTRIES - 1;
11529 ilt_cli.client_num = ILT_CLIENT_TM;
11531 ecore_ilt_boundry_init_op(sc, &ilt_cli, 0);
11534 /* this assumes that reset_port() called before reset_func() */
11535 if (!CHIP_IS_E1x(sc)) {
11536 bnx2x_pf_disable(sc);
11539 sc->dmae_ready = 0;
11542 static void bnx2x_release_firmware(struct bnx2x_softc *sc)
11544 rte_free(sc->init_ops);
11545 rte_free(sc->init_ops_offsets);
11546 rte_free(sc->init_data);
11547 rte_free(sc->iro_array);
11550 static int bnx2x_init_firmware(struct bnx2x_softc *sc)
11553 uint8_t *p = sc->firmware;
11556 for (i = 0; i < 24; ++i)
11557 off[i] = rte_be_to_cpu_32(*((uint32_t *) sc->firmware + i));
11560 sc->init_ops = rte_zmalloc("", len, RTE_CACHE_LINE_SIZE);
11563 bnx2x_data_to_init_ops(p + off[1], sc->init_ops, len);
11566 sc->init_ops_offsets = rte_zmalloc("", len, RTE_CACHE_LINE_SIZE);
11567 if (!sc->init_ops_offsets)
11569 bnx2x_data_to_init_offsets(p + off[3], sc->init_ops_offsets, len);
11572 sc->init_data = rte_zmalloc("", len, RTE_CACHE_LINE_SIZE);
11573 if (!sc->init_data)
11575 bnx2x_data_to_init_data(p + off[5], sc->init_data, len);
11577 sc->tsem_int_table_data = p + off[7];
11578 sc->tsem_pram_data = p + off[9];
11579 sc->usem_int_table_data = p + off[11];
11580 sc->usem_pram_data = p + off[13];
11581 sc->csem_int_table_data = p + off[15];
11582 sc->csem_pram_data = p + off[17];
11583 sc->xsem_int_table_data = p + off[19];
11584 sc->xsem_pram_data = p + off[21];
11587 sc->iro_array = rte_zmalloc("", len, RTE_CACHE_LINE_SIZE);
11588 if (!sc->iro_array)
11590 bnx2x_data_to_iro_array(p + off[23], sc->iro_array, len);
11595 bnx2x_release_firmware(sc);
11599 static int cut_gzip_prefix(const uint8_t * zbuf, int len)
11601 #define MIN_PREFIX_SIZE (10)
11603 int n = MIN_PREFIX_SIZE;
11606 if (!(zbuf[0] == 0x1f && zbuf[1] == 0x8b && zbuf[2] == Z_DEFLATED) ||
11607 len <= MIN_PREFIX_SIZE) {
11611 /* optional extra fields are present */
11612 if (zbuf[3] & 0x4) {
11619 /* file name is present */
11620 if (zbuf[3] & 0x8) {
11621 while ((zbuf[n++] != 0) && (n < len)) ;
11627 static int ecore_gunzip(struct bnx2x_softc *sc, const uint8_t * zbuf, int len)
11630 int data_begin = cut_gzip_prefix(zbuf, len);
11632 PMD_DRV_LOG(DEBUG, sc, "ecore_gunzip %d", len);
11634 if (data_begin <= 0) {
11635 PMD_DRV_LOG(NOTICE, sc, "bad gzip prefix");
11639 memset(&zlib_stream, 0, sizeof(zlib_stream));
11640 zlib_stream.next_in = zbuf + data_begin;
11641 zlib_stream.avail_in = len - data_begin;
11642 zlib_stream.next_out = sc->gz_buf;
11643 zlib_stream.avail_out = FW_BUF_SIZE;
11645 ret = inflateInit2(&zlib_stream, -MAX_WBITS);
11647 PMD_DRV_LOG(NOTICE, sc, "zlib inflateInit2 error");
11651 ret = inflate(&zlib_stream, Z_FINISH);
11652 if ((ret != Z_STREAM_END) && (ret != Z_OK)) {
11653 PMD_DRV_LOG(NOTICE, sc, "zlib inflate error: %d %s", ret,
11657 sc->gz_outlen = zlib_stream.total_out;
11658 if (sc->gz_outlen & 0x3) {
11659 PMD_DRV_LOG(NOTICE, sc, "firmware is not aligned. gz_outlen == %d",
11662 sc->gz_outlen >>= 2;
11664 inflateEnd(&zlib_stream);
11666 if (ret == Z_STREAM_END)
11673 ecore_write_dmae_phys_len(struct bnx2x_softc *sc, phys_addr_t phys_addr,
11674 uint32_t addr, uint32_t len)
11676 bnx2x_write_dmae_phys_len(sc, phys_addr, addr, len);
11680 ecore_storm_memset_struct(struct bnx2x_softc *sc, uint32_t addr, size_t size,
11684 for (i = 0; i < size / 4; i++) {
11685 REG_WR(sc, addr + (i * 4), data[i]);
11689 __rte_unused static const char *get_ext_phy_type(uint32_t ext_phy_type)
11691 uint32_t phy_type_idx = ext_phy_type >> 8;
11692 static const char *types[] =
11693 { "DIRECT", "BNX2X-8071", "BNX2X-8072", "BNX2X-8073",
11694 "BNX2X-8705", "BNX2X-8706", "BNX2X-8726", "BNX2X-8481", "SFX-7101",
11696 "BNX2X-8727-NOC", "BNX2X-84823", "NOT_CONN", "FAILURE"
11699 if (phy_type_idx < 12)
11700 return types[phy_type_idx];
11701 else if (PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN == ext_phy_type)
11707 __rte_unused static const char *get_state(uint32_t state)
11709 uint32_t state_idx = state >> 12;
11710 static const char *states[] = { "CLOSED", "OPENING_WAIT4_LOAD",
11711 "OPENING_WAIT4_PORT", "OPEN", "CLOSING_WAIT4_HALT",
11712 "CLOSING_WAIT4_DELETE", "CLOSING_WAIT4_UNLOAD",
11713 "UNKNOWN", "UNKNOWN", "UNKNOWN", "UNKNOWN", "UNKNOWN",
11714 "UNKNOWN", "DISABLED", "DIAG", "ERROR", "UNDEFINED"
11717 if (state_idx <= 0xF)
11718 return states[state_idx];
11720 return states[0x10];
11723 __rte_unused static const char *get_recovery_state(uint32_t state)
11725 static const char *states[] = { "NONE", "DONE", "INIT",
11726 "WAIT", "FAILED", "NIC_LOADING"
11728 return states[state];
11731 __rte_unused static const char *get_rx_mode(uint32_t mode)
11733 static const char *modes[] = { "NONE", "NORMAL", "ALLMULTI",
11734 "PROMISC", "MAX_MULTICAST", "ERROR"
11738 return modes[mode];
11739 else if (BNX2X_MAX_MULTICAST == mode)
11745 #define BNX2X_INFO_STR_MAX 256
11746 __rte_unused static const char *get_bnx2x_flags(uint32_t flags)
11749 static const char *flag[] = { "ONE_PORT ", "NO_ISCSI ",
11750 "NO_FCOE ", "NO_WOL ", "USING_DAC ", "USING_MSIX ",
11751 "USING_MSI ", "DISABLE_MSI ", "UNKNOWN ", "NO_MCP ",
11752 "SAFC_TX_FLAG ", "MF_FUNC_DIS ", "TX_SWITCHING "
11754 static char flag_str[BNX2X_INFO_STR_MAX];
11755 memset(flag_str, 0, BNX2X_INFO_STR_MAX);
11757 for (i = 0; i < 5; i++)
11758 if (flags & (1 << i)) {
11759 strcat(flag_str, flag[i]);
11763 static char unknown[BNX2X_INFO_STR_MAX];
11764 snprintf(unknown, 32, "Unknown flag mask %x", flags);
11765 strcat(flag_str, unknown);
11771 * Prints useful adapter info.
11773 void bnx2x_print_adapter_info(struct bnx2x_softc *sc)
11776 __rte_unused uint32_t ext_phy_type;
11778 PMD_INIT_FUNC_TRACE(sc);
11779 if (sc->link_vars.phy_flags & PHY_XGXS_FLAG)
11780 ext_phy_type = ELINK_XGXS_EXT_PHY_TYPE(REG_RD(sc,
11785 dev_info.port_hw_config
11786 [0].external_phy_config)));
11788 ext_phy_type = ELINK_SERDES_EXT_PHY_TYPE(REG_RD(sc,
11794 dev_info.port_hw_config
11795 [0].external_phy_config)));
11797 PMD_DRV_LOG(INFO, sc, "\n\n===================================\n");
11798 /* Hardware chip info. */
11799 PMD_DRV_LOG(INFO, sc, "%12s : %#08x", "ASIC", sc->devinfo.chip_id);
11800 PMD_DRV_LOG(INFO, sc, "%12s : %c%d", "Rev", (CHIP_REV(sc) >> 12) + 'A',
11801 (CHIP_METAL(sc) >> 4));
11804 PMD_DRV_LOG(INFO, sc,
11805 "%12s : %d, ", "Bus PCIe", sc->devinfo.pcie_link_width);
11806 switch (sc->devinfo.pcie_link_speed) {
11808 PMD_DRV_LOG(INFO, sc, "%23s", "2.5 Gbps");
11811 PMD_DRV_LOG(INFO, sc, "%21s", "5 Gbps");
11814 PMD_DRV_LOG(INFO, sc, "%21s", "8 Gbps");
11817 PMD_DRV_LOG(INFO, sc, "%33s", "Unknown link speed");
11820 /* Device features. */
11821 PMD_DRV_LOG(INFO, sc, "%12s : ", "Flags");
11823 /* Miscellaneous flags. */
11824 if (sc->devinfo.pcie_cap_flags & BNX2X_MSI_CAPABLE_FLAG) {
11825 PMD_DRV_LOG(INFO, sc, "%18s", "MSI");
11829 if (sc->devinfo.pcie_cap_flags & BNX2X_MSIX_CAPABLE_FLAG) {
11831 PMD_DRV_LOG(INFO, sc, "|");
11832 PMD_DRV_LOG(INFO, sc, "%20s", "MSI-X");
11837 PMD_DRV_LOG(INFO, sc, "%12s : ", "Queues");
11838 switch (sc->sp->rss_rdata.rss_mode) {
11839 case ETH_RSS_MODE_DISABLED:
11840 PMD_DRV_LOG(INFO, sc, "%19s", "None");
11842 case ETH_RSS_MODE_REGULAR:
11843 PMD_DRV_LOG(INFO, sc,
11844 "%18s : %d", "RSS", sc->num_queues);
11847 PMD_DRV_LOG(INFO, sc, "%22s", "Unknown");
11852 /* RTE and Driver versions */
11853 PMD_DRV_LOG(INFO, sc, "%12s : %s", "DPDK",
11855 PMD_DRV_LOG(INFO, sc, "%12s : %s", "Driver",
11856 bnx2x_pmd_version());
11858 /* Firmware versions and device features. */
11859 PMD_DRV_LOG(INFO, sc, "%12s : %d.%d.%d",
11861 BNX2X_5710_FW_MAJOR_VERSION,
11862 BNX2X_5710_FW_MINOR_VERSION,
11863 BNX2X_5710_FW_REVISION_VERSION);
11864 PMD_DRV_LOG(INFO, sc, "%12s : %s",
11865 "Bootcode", sc->devinfo.bc_ver_str);
11867 PMD_DRV_LOG(INFO, sc, "\n\n===================================\n");
11868 PMD_DRV_LOG(INFO, sc, "%12s : %u", "Bnx2x Func", sc->pcie_func);
11869 PMD_DRV_LOG(INFO, sc,
11870 "%12s : %s", "Bnx2x Flags", get_bnx2x_flags(sc->flags));
11871 PMD_DRV_LOG(INFO, sc, "%12s : %s", "DMAE Is",
11872 (sc->dmae_ready ? "Ready" : "Not Ready"));
11873 PMD_DRV_LOG(INFO, sc, "%12s : %s", "OVLAN", (OVLAN(sc) ? "YES" : "NO"));
11874 PMD_DRV_LOG(INFO, sc, "%12s : %s", "MF", (IS_MF(sc) ? "YES" : "NO"));
11875 PMD_DRV_LOG(INFO, sc, "%12s : %u", "MTU", sc->mtu);
11876 PMD_DRV_LOG(INFO, sc,
11877 "%12s : %s", "PHY Type", get_ext_phy_type(ext_phy_type));
11878 PMD_DRV_LOG(INFO, sc, "%12s : %x:%x:%x:%x:%x:%x", "MAC Addr",
11879 sc->link_params.mac_addr[0],
11880 sc->link_params.mac_addr[1],
11881 sc->link_params.mac_addr[2],
11882 sc->link_params.mac_addr[3],
11883 sc->link_params.mac_addr[4],
11884 sc->link_params.mac_addr[5]);
11885 PMD_DRV_LOG(INFO, sc, "%12s : %s", "RX Mode", get_rx_mode(sc->rx_mode));
11886 PMD_DRV_LOG(INFO, sc, "%12s : %s", "State", get_state(sc->state));
11887 if (sc->recovery_state)
11888 PMD_DRV_LOG(INFO, sc, "%12s : %s", "Recovery",
11889 get_recovery_state(sc->recovery_state));
11890 PMD_DRV_LOG(INFO, sc, "%12s : CQ = %lx, EQ = %lx", "SPQ Left",
11891 sc->cq_spq_left, sc->eq_spq_left);
11892 PMD_DRV_LOG(INFO, sc,
11893 "%12s : %x", "Switch", sc->link_params.switch_cfg);
11894 PMD_DRV_LOG(INFO, sc, "\n\n===================================\n");