2 * Copyright (c) 2007-2013 Broadcom Corporation.
4 * Eric Davis <edavis@broadcom.com>
5 * David Christensen <davidch@broadcom.com>
6 * Gary Zambrano <zambrano@broadcom.com>
8 * Copyright (c) 2013-2015 Brocade Communications Systems, Inc.
9 * Copyright (c) 2015 QLogic Corporation.
10 * All rights reserved.
13 * See LICENSE.bnx2x_pmd for copyright and licensing details.
19 #include <rte_byteorder.h>
20 #include <rte_spinlock.h>
21 #include <rte_bus_pci.h>
24 #if RTE_BYTE_ORDER == RTE_LITTLE_ENDIAN
25 #ifndef __LITTLE_ENDIAN
26 #define __LITTLE_ENDIAN RTE_LITTLE_ENDIAN
29 #elif RTE_BYTE_ORDER == RTE_BIG_ENDIAN
31 #define __BIG_ENDIAN RTE_BIG_ENDIAN
33 #undef __LITTLE_ENDIAN
36 #include "bnx2x_ethdev.h"
37 #include "ecore_mfw_req.h"
38 #include "ecore_fw_defs.h"
39 #include "ecore_hsi.h"
40 #include "ecore_reg.h"
41 #include "bnx2x_stats.h"
42 #include "bnx2x_vfpf.h"
47 #include <linux/pci_regs.h>
49 #define PCIY_PMG PCI_CAP_ID_PM
50 #define PCIY_MSI PCI_CAP_ID_MSI
51 #define PCIY_EXPRESS PCI_CAP_ID_EXP
52 #define PCIY_MSIX PCI_CAP_ID_MSIX
53 #define PCIR_EXPRESS_DEVICE_STA PCI_EXP_TYPE_RC_EC
54 #define PCIM_EXP_STA_TRANSACTION_PND PCI_EXP_DEVSTA_TRPND
55 #define PCIR_EXPRESS_LINK_STA PCI_EXP_LNKSTA
56 #define PCIM_LINK_STA_WIDTH PCI_EXP_LNKSTA_NLW
57 #define PCIM_LINK_STA_SPEED PCI_EXP_LNKSTA_CLS
58 #define PCIR_EXPRESS_DEVICE_CTL PCI_EXP_DEVCTL
59 #define PCIM_EXP_CTL_MAX_PAYLOAD PCI_EXP_DEVCTL_PAYLOAD
60 #define PCIM_EXP_CTL_MAX_READ_REQUEST PCI_EXP_DEVCTL_READRQ
61 #define PCIR_POWER_STATUS PCI_PM_CTRL
62 #define PCIM_PSTAT_DMASK PCI_PM_CTRL_STATE_MASK
63 #define PCIM_PSTAT_PME PCI_PM_CTRL_PME_STATUS
64 #define PCIM_PSTAT_D3 0x3
65 #define PCIM_PSTAT_PMEENABLE PCI_PM_CTRL_PME_ENABLE
66 #define PCIR_MSIX_CTRL PCI_MSIX_FLAGS
67 #define PCIM_MSIXCTRL_TABLE_SIZE PCI_MSIX_FLAGS_QSIZE
69 #include <dev/pci/pcireg.h>
72 #define IFM_10G_CX4 20 /* 10GBase CX4 copper */
73 #define IFM_10G_TWINAX 22 /* 10GBase Twinax copper */
74 #define IFM_10G_T 26 /* 10GBase-T - RJ45 */
77 #define PCIR_EXPRESS_DEVICE_STA PCI_EXP_TYPE_RC_EC
78 #define PCIM_EXP_STA_TRANSACTION_PND PCI_EXP_DEVSTA_TRPND
79 #define PCIR_EXPRESS_LINK_STA PCI_EXP_LNKSTA
80 #define PCIM_LINK_STA_WIDTH PCI_EXP_LNKSTA_NLW
81 #define PCIM_LINK_STA_SPEED PCI_EXP_LNKSTA_CLS
82 #define PCIR_EXPRESS_DEVICE_CTL PCI_EXP_DEVCTL
83 #define PCIM_EXP_CTL_MAX_PAYLOAD PCI_EXP_DEVCTL_PAYLOAD
84 #define PCIM_EXP_CTL_MAX_READ_REQUEST PCI_EXP_DEVCTL_READRQ
86 #define PCIR_EXPRESS_DEVICE_STA PCIER_DEVICE_STA
87 #define PCIM_EXP_STA_TRANSACTION_PND PCIEM_STA_TRANSACTION_PND
88 #define PCIR_EXPRESS_LINK_STA PCIER_LINK_STA
89 #define PCIM_LINK_STA_WIDTH PCIEM_LINK_STA_WIDTH
90 #define PCIM_LINK_STA_SPEED PCIEM_LINK_STA_SPEED
91 #define PCIR_EXPRESS_DEVICE_CTL PCIER_DEVICE_CTL
92 #define PCIM_EXP_CTL_MAX_PAYLOAD PCIEM_CTL_MAX_PAYLOAD
93 #define PCIM_EXP_CTL_MAX_READ_REQUEST PCIEM_CTL_MAX_READ_REQUEST
97 #define ARRAY_SIZE(arr) (sizeof(arr) / sizeof((arr)[0]))
100 #define ARRSIZE(arr) (sizeof(arr) / sizeof((arr)[0]))
103 #define DIV_ROUND_UP(n, d) (((n) + (d) - 1) / (d))
106 #define roundup(x, y) ((((x) + ((y) - 1)) / (y)) * (y))
110 int bnx2x_ilog2(int x)
121 #define ilog2(x) bnx2x_ilog2(x)
124 #include "ecore_sp.h"
126 struct bnx2x_device_type {
134 #define BNX2X_PAGE_SHIFT 12
135 #define BNX2X_PAGE_SIZE (1 << BNX2X_PAGE_SHIFT)
136 #define BNX2X_PAGE_MASK (~(BNX2X_PAGE_SIZE - 1))
137 #define BNX2X_PAGE_ALIGN(addr) ((addr + BNX2X_PAGE_SIZE - 1) & BNX2X_PAGE_MASK)
139 #if BNX2X_PAGE_SIZE != 4096
140 #error Page sizes other than 4KB are unsupported!
143 #define U64_LO(addr) ((uint32_t)(((uint64_t)(addr)) & 0xFFFFFFFF))
144 #define U64_HI(addr) ((uint32_t)(((uint64_t)(addr)) >> 32))
145 #define HILO_U64(hi, lo) ((((uint64_t)(hi)) << 32) + (lo))
147 /* dropless fc FW/HW related params */
148 #define BRB_SIZE(sc) (CHIP_IS_E3(sc) ? 1024 : 512)
149 #define MAX_AGG_QS(sc) ETH_MAX_AGGREGATION_QUEUES_E1H_E2
150 #define FW_DROP_LEVEL(sc) (3 + MAX_SPQ_PENDING + MAX_AGG_QS(sc))
151 #define FW_PREFETCH_CNT 16U
152 #define DROPLESS_FC_HEADROOM 100
155 * Transmit Buffer Descriptor (tx_bd) definitions*
157 /* NUM_TX_PAGES must be a power of 2. */
158 #define TOTAL_TX_BD_PER_PAGE (BNX2X_PAGE_SIZE / sizeof(union eth_tx_bd_types)) /* 256 */
159 #define USABLE_TX_BD_PER_PAGE (TOTAL_TX_BD_PER_PAGE - 1) /* 255 */
161 #define TOTAL_TX_BD(q) (TOTAL_TX_BD_PER_PAGE * q->nb_tx_pages) /* 512 */
162 #define USABLE_TX_BD(q) (USABLE_TX_BD_PER_PAGE * q->nb_tx_pages) /* 510 */
163 #define MAX_TX_BD(q) (TOTAL_TX_BD(q) - 1) /* 511 */
165 #define NEXT_TX_BD(x) \
166 ((((x) & USABLE_TX_BD_PER_PAGE) == \
167 (USABLE_TX_BD_PER_PAGE - 1)) ? (x) + 2 : (x) + 1)
169 #define TX_BD(x, q) ((x) & MAX_TX_BD(q))
170 #define TX_PAGE(x) (((x) & ~USABLE_TX_BD_PER_PAGE) >> 8)
171 #define TX_IDX(x) ((x) & USABLE_TX_BD_PER_PAGE)
173 #define BDS_PER_TX_PKT (3)
176 * Trigger pending transmits when the number of available BDs is greater
177 * than 1/8 of the total number of usable BDs.
179 #define BNX2X_TX_CLEANUP_THRESHOLD(q) (USABLE_TX_BD(q) / 8)
180 #define BNX2X_TX_TIMEOUT 5
183 * Receive Buffer Descriptor (rx_bd) definitions*
185 //#define NUM_RX_PAGES 1
186 #define TOTAL_RX_BD_PER_PAGE (BNX2X_PAGE_SIZE / sizeof(struct eth_rx_bd)) /* 512 */
187 #define USABLE_RX_BD_PER_PAGE (TOTAL_RX_BD_PER_PAGE - 2) /* 510 */
188 #define RX_BD_PER_PAGE_MASK (TOTAL_RX_BD_PER_PAGE - 1) /* 511 */
189 #define TOTAL_RX_BD(q) (TOTAL_RX_BD_PER_PAGE * q->nb_rx_pages) /* 512 */
190 #define USABLE_RX_BD(q) (USABLE_RX_BD_PER_PAGE * q->nb_rx_pages) /* 510 */
191 #define MAX_RX_BD(q) (TOTAL_RX_BD(q) - 1) /* 511 */
192 #define RX_BD_NEXT_PAGE_DESC_CNT 2
194 #define NEXT_RX_BD(x) \
195 ((((x) & RX_BD_PER_PAGE_MASK) == \
196 (USABLE_RX_BD_PER_PAGE - 1)) ? (x) + 3 : (x) + 1)
199 #define RX_BD(x, q) ((x) & MAX_RX_BD(q))
200 #define RX_PAGE(x) (((x) & ~RX_BD_PER_PAGE_MASK) >> 9)
201 #define RX_IDX(x) ((x) & RX_BD_PER_PAGE_MASK)
204 * Receive Completion Queue definitions*
206 //#define NUM_RCQ_PAGES (NUM_RX_PAGES * 4)
207 #define TOTAL_RCQ_ENTRIES_PER_PAGE (BNX2X_PAGE_SIZE / sizeof(union eth_rx_cqe)) /* 128 */
208 #define USABLE_RCQ_ENTRIES_PER_PAGE (TOTAL_RCQ_ENTRIES_PER_PAGE - 1) /* 127 */
209 #define TOTAL_RCQ_ENTRIES(q) (TOTAL_RCQ_ENTRIES_PER_PAGE * q->nb_cq_pages) /* 512 */
210 #define USABLE_RCQ_ENTRIES(q) (USABLE_RCQ_ENTRIES_PER_PAGE * q->nb_cq_pages) /* 508 */
211 #define MAX_RCQ_ENTRIES(q) (TOTAL_RCQ_ENTRIES(q) - 1) /* 511 */
212 #define RCQ_NEXT_PAGE_DESC_CNT 1
214 #define NEXT_RCQ_IDX(x) \
215 ((((x) & USABLE_RCQ_ENTRIES_PER_PAGE) == \
216 (USABLE_RCQ_ENTRIES_PER_PAGE - 1)) ? (x) + 2 : (x) + 1)
219 (sizeof(union eth_rx_cqe) / sizeof(struct eth_rx_bd))
221 #define RCQ_BD_PAGES(q) \
222 (q->nb_rx_pages * CQE_BD_REL)
224 #define RCQ_ENTRY(x, q) ((x) & MAX_RCQ_ENTRIES(q))
225 #define RCQ_PAGE(x) (((x) & ~USABLE_RCQ_ENTRIES_PER_PAGE) >> 7)
226 #define RCQ_IDX(x) ((x) & USABLE_RCQ_ENTRIES_PER_PAGE)
229 * dropless fc calculations for BDs
230 * Number of BDs should be as number of buffers in BRB:
231 * Low threshold takes into account RX_BD_NEXT_PAGE_DESC_CNT
232 * "next" elements on each page
234 #define NUM_BD_REQ(sc) \
236 #define NUM_BD_PG_REQ(sc) \
237 ((NUM_BD_REQ(sc) + USABLE_RX_BD_PER_PAGE - 1) / USABLE_RX_BD_PER_PAGE)
238 #define BD_TH_LO(sc) \
240 NUM_BD_PG_REQ(sc) * RX_BD_NEXT_PAGE_DESC_CNT + \
242 #define BD_TH_HI(sc) \
243 (BD_TH_LO(sc) + DROPLESS_FC_HEADROOM)
244 #define MIN_RX_AVAIL(sc) \
245 ((sc)->dropless_fc ? BD_TH_HI(sc) + 128 : 128)
248 * dropless fc calculations for RCQs
249 * Number of RCQs should be as number of buffers in BRB:
250 * Low threshold takes into account RCQ_NEXT_PAGE_DESC_CNT
251 * "next" elements on each page
253 #define NUM_RCQ_REQ(sc) \
255 #define NUM_RCQ_PG_REQ(sc) \
256 ((NUM_RCQ_REQ(sc) + USABLE_RCQ_ENTRIES_PER_PAGE - 1) / USABLE_RCQ_ENTRIES_PER_PAGE)
257 #define RCQ_TH_LO(sc) \
259 NUM_RCQ_PG_REQ(sc) * RCQ_NEXT_PAGE_DESC_CNT + \
261 #define RCQ_TH_HI(sc) \
262 (RCQ_TH_LO(sc) + DROPLESS_FC_HEADROOM)
264 /* Load / Unload modes */
265 #define LOAD_NORMAL 0
268 #define LOAD_LOOPBACK_EXT 3
269 #define UNLOAD_NORMAL 0
270 #define UNLOAD_CLOSE 1
271 #define UNLOAD_RECOVERY 2
273 /* Some constants... */
274 //#define MAX_PATH_NUM 2
275 //#define E2_MAX_NUM_OF_VFS 64
276 //#define E1H_FUNC_MAX 8
277 //#define E2_FUNC_MAX 4 /* per path */
278 #define MAX_VNIC_NUM 4
279 #define MAX_FUNC_NUM 8 /* common to all chips */
280 //#define MAX_NDSB HC_SB_MAX_SB_E2 /* max non-default status block */
281 #define MAX_RSS_CHAINS 16 /* a constant for HW limit */
282 #define MAX_MSI_VECTOR 8 /* a constant for HW limit */
284 #define ILT_NUM_PAGE_ENTRIES 3072
286 * 57711 we use whole table since we have 8 functions.
287 * 57712 we have only 4 functions, but use same size per func, so only half
288 * of the table is used.
290 #define ILT_PER_FUNC (ILT_NUM_PAGE_ENTRIES / 8)
291 #define FUNC_ILT_BASE(func) (func * ILT_PER_FUNC)
293 * the phys address is shifted right 12 bits and has an added
294 * 1=valid bit added to the 53rd bit
295 * then since this is a wide register(TM)
296 * we split it into two 32 bit writes
298 #define ONCHIP_ADDR1(x) ((uint32_t)(((uint64_t)x >> 12) & 0xFFFFFFFF))
299 #define ONCHIP_ADDR2(x) ((uint32_t)((1 << 20) | ((uint64_t)x >> 44)))
301 /* L2 header size + 2*VLANs (8 bytes) + LLC SNAP (8 bytes) */
303 #define ETH_OVERHEAD (ETH_HLEN + 8 + 8)
304 #define ETH_MIN_PACKET_SIZE 60
305 #define ETH_MAX_PACKET_SIZE ETHERMTU /* 1500 */
306 #define ETH_MAX_JUMBO_PACKET_SIZE 9600
307 /* TCP with Timestamp Option (32) + IPv6 (40) */
309 /* max supported alignment is 256 (8 shift) */
310 #define BNX2X_RX_ALIGN_SHIFT RTE_MAX(6, min(8, RTE_CACHE_LINE_SIZE_LOG2))
312 #define BNX2X_PXP_DRAM_ALIGN (BNX2X_RX_ALIGN_SHIFT - 5)
318 /* Used to manage DMA allocations. */
320 struct bnx2x_softc *sc;
324 char msg[RTE_MEMZONE_NAMESIZE - 6];
327 /* attn group wiring */
328 #define MAX_DYNAMIC_ATTN_GRPS 8
342 union bnx2x_host_hc_status_block {
343 /* pointer to fp status block e2 */
344 struct host_hc_status_block_e2 *e2_sb;
345 /* pointer to fp status block e1x */
346 struct host_hc_status_block_e1x *e1x_sb;
349 union bnx2x_db_prod {
350 struct doorbell_set_prod data;
354 struct bnx2x_sw_tx_bd {
358 /* set on the first BD descriptor when there is a split BD */
359 #define BNX2X_TSO_SPLIT_BD (1 << 0)
363 * This is the HSI fastpath data structure. There can be up to MAX_RSS_CHAIN
364 * instances of the fastpath structure when using multiple queues.
366 struct bnx2x_fastpath {
367 /* pointer back to parent structure */
368 struct bnx2x_softc *sc;
371 struct bnx2x_dma sb_dma;
372 union bnx2x_host_hc_status_block status_block;
374 rte_iova_t tx_desc_mapping;
376 rte_iova_t rx_desc_mapping;
377 rte_iova_t rx_comp_mapping;
379 uint16_t *sb_index_values;
380 uint16_t *sb_running_index;
381 uint32_t ustorm_rx_prods_offset;
383 uint8_t igu_sb_id; /* status block number in HW */
384 uint8_t fw_sb_id; /* status block number in FW */
386 uint32_t rx_buf_size;
389 #define BNX2X_FP_STATE_CLOSED 0x01
390 #define BNX2X_FP_STATE_IRQ 0x02
391 #define BNX2X_FP_STATE_OPENING 0x04
392 #define BNX2X_FP_STATE_OPEN 0x08
393 #define BNX2X_FP_STATE_HALTING 0x10
394 #define BNX2X_FP_STATE_HALTED 0x20
396 /* reference back to this fastpath queue number */
397 uint8_t index; /* this is also the 'cid' */
398 #define FP_IDX(fp) (fp->index)
400 /* ethernet client ID (each fastpath set of RX/TX/CQE is a client) */
402 #define FP_CL_ID(fp) (fp->cl_id)
407 union bnx2x_db_prod tx_db;
409 struct tstorm_per_queue_stats old_tclient;
410 struct ustorm_per_queue_stats old_uclient;
411 struct xstorm_per_queue_stats old_xclient;
412 struct bnx2x_eth_q_stats eth_q_stats;
413 struct bnx2x_eth_q_stats_old eth_q_stats_old;
415 /* Pointer to the receive consumer in the status block */
416 uint16_t *rx_cq_cons_sb;
418 /* Pointer to the transmit consumer in the status block */
419 uint16_t *tx_cons_sb;
421 /* transmit timeout until chip reset */
424 }; /* struct bnx2x_fastpath */
426 #define BNX2X_MAX_NUM_OF_VFS 64
427 #define BNX2X_VF_ID_INVALID 0xFF
429 /* maximum number of fast-path interrupt contexts */
430 #define FP_SB_MAX_E1x 16
431 #define FP_SB_MAX_E2 HC_SB_MAX_SB_E2
434 struct eth_context eth;
438 /* CDU host DB constants */
439 #define CDU_ILT_PAGE_SZ_HW 2
440 #define CDU_ILT_PAGE_SZ (8192 << CDU_ILT_PAGE_SZ_HW) /* 32K */
441 #define ILT_PAGE_CIDS (CDU_ILT_PAGE_SZ / sizeof(union cdu_context))
443 #define CNIC_ISCSI_CID_MAX 256
444 #define CNIC_FCOE_CID_MAX 2048
445 #define CNIC_CID_MAX (CNIC_ISCSI_CID_MAX + CNIC_FCOE_CID_MAX)
446 #define CNIC_ILT_LINES DIV_ROUND_UP(CNIC_CID_MAX, ILT_PAGE_CIDS)
448 #define QM_ILT_PAGE_SZ_HW 0
449 #define QM_ILT_PAGE_SZ (4096 << QM_ILT_PAGE_SZ_HW) /* 4K */
450 #define QM_CID_ROUND 1024
452 /* TM (timers) host DB constants */
453 #define TM_ILT_PAGE_SZ_HW 0
454 #define TM_ILT_PAGE_SZ (4096 << TM_ILT_PAGE_SZ_HW) /* 4K */
455 /*#define TM_CONN_NUM (CNIC_STARTING_CID+CNIC_ISCSI_CXT_MAX) */
456 #define TM_CONN_NUM 1024
457 #define TM_ILT_SZ (8 * TM_CONN_NUM)
458 #define TM_ILT_LINES DIV_ROUND_UP(TM_ILT_SZ, TM_ILT_PAGE_SZ)
460 /* SRC (Searcher) host DB constants */
461 #define SRC_ILT_PAGE_SZ_HW 0
462 #define SRC_ILT_PAGE_SZ (4096 << SRC_ILT_PAGE_SZ_HW) /* 4K */
463 #define SRC_HASH_BITS 10
464 #define SRC_CONN_NUM (1 << SRC_HASH_BITS) /* 1024 */
465 #define SRC_ILT_SZ (sizeof(struct src_ent) * SRC_CONN_NUM)
466 #define SRC_T2_SZ SRC_ILT_SZ
467 #define SRC_ILT_LINES DIV_ROUND_UP(SRC_ILT_SZ, SRC_ILT_PAGE_SZ)
470 struct bnx2x_dma vcxt_dma;
471 union cdu_context *vcxt;
472 //rte_iova_t cxt_mapping;
479 /* defines for multiple tx priority indices */
480 #define FIRST_TX_ONLY_COS_INDEX 1
481 #define FIRST_TX_COS_INDEX 0
483 #define CID_TO_FP(cid, sc) ((cid) % BNX2X_NUM_NON_CNIC_QUEUES(sc))
485 #define HC_INDEX_ETH_RX_CQ_CONS 1
486 #define HC_INDEX_OOO_TX_CQ_CONS 4
487 #define HC_INDEX_ETH_TX_CQ_CONS_COS0 5
488 #define HC_INDEX_ETH_TX_CQ_CONS_COS1 6
489 #define HC_INDEX_ETH_TX_CQ_CONS_COS2 7
490 #define HC_INDEX_ETH_FIRST_TX_CQ_CONS HC_INDEX_ETH_TX_CQ_CONS_COS0
492 /* congestion management fairness mode */
493 #define CMNG_FNS_NONE 0
494 #define CMNG_FNS_MINMAX 1
496 /* CMNG constants, as derived from system spec calculations */
497 /* default MIN rate in case VNIC min rate is configured to zero - 100Mbps */
498 #define DEF_MIN_RATE 100
499 /* resolution of the rate shaping timer - 400 usec */
500 #define RS_PERIODIC_TIMEOUT_USEC 400
501 /* number of bytes in single QM arbitration cycle -
502 * coefficient for calculating the fairness timer */
503 #define QM_ARB_BYTES 160000
504 /* resolution of Min algorithm 1:100 */
506 /* how many bytes above threshold for the minimal credit of Min algorithm*/
507 #define MIN_ABOVE_THRESH 32768
508 /* fairness algorithm integration time coefficient -
509 * for calculating the actual Tfair */
510 #define T_FAIR_COEF ((MIN_ABOVE_THRESH + QM_ARB_BYTES) * 8 * MIN_RES)
511 /* memory of fairness algorithm - 2 cycles */
514 #define HC_SEG_ACCESS_DEF 0 /* Driver decision 0-3 */
515 #define HC_SEG_ACCESS_ATTN 4
516 #define HC_SEG_ACCESS_NORM 0 /* Driver decision 0-1 */
519 * The total number of L2 queues, MSIX vectors and HW contexts (CIDs) is
520 * control by the number of fast-path status blocks supported by the
521 * device (HW/FW). Each fast-path status block (FP-SB) aka non-default
522 * status block represents an independent interrupts context that can
523 * serve a regular L2 networking queue. However special L2 queues such
524 * as the FCoE queue do not require a FP-SB and other components like
525 * the CNIC may consume FP-SB reducing the number of possible L2 queues
527 * If the maximum number of FP-SB available is X then:
528 * a. If CNIC is supported it consumes 1 FP-SB thus the max number of
529 * regular L2 queues is Y=X-1
530 * b. in MF mode the actual number of L2 queues is Y= (X-1/MF_factor)
531 * c. If the FCoE L2 queue is supported the actual number of L2 queues
533 * d. The number of irqs (MSIX vectors) is either Y+1 (one extra for
534 * slow-path interrupts) or Y+2 if CNIC is supported (one additional
535 * FP interrupt context for the CNIC).
536 * e. The number of HW context (CID count) is always X or X+1 if FCoE
537 * L2 queue is supported. the cid for the FCoE L2 queue is always X.
539 * So this is quite simple for now as no ULPs are supported yet. :-)
541 #define BNX2X_NUM_QUEUES(sc) ((sc)->num_queues)
542 #define BNX2X_NUM_ETH_QUEUES(sc) BNX2X_NUM_QUEUES(sc)
543 #define BNX2X_NUM_NON_CNIC_QUEUES(sc) BNX2X_NUM_QUEUES(sc)
544 #define BNX2X_NUM_RX_QUEUES(sc) BNX2X_NUM_QUEUES(sc)
546 #define FOR_EACH_QUEUE(sc, var) \
547 for ((var) = 0; (var) < BNX2X_NUM_QUEUES(sc); (var)++)
549 #define FOR_EACH_NONDEFAULT_QUEUE(sc, var) \
550 for ((var) = 1; (var) < BNX2X_NUM_QUEUES(sc); (var)++)
552 #define FOR_EACH_ETH_QUEUE(sc, var) \
553 for ((var) = 0; (var) < BNX2X_NUM_ETH_QUEUES(sc); (var)++)
555 #define FOR_EACH_NONDEFAULT_ETH_QUEUE(sc, var) \
556 for ((var) = 1; (var) < BNX2X_NUM_ETH_QUEUES(sc); (var)++)
558 #define FOR_EACH_COS_IN_TX_QUEUE(sc, var) \
559 for ((var) = 0; (var) < (sc)->max_cos; (var)++)
561 #define FOR_EACH_CNIC_QUEUE(sc, var) \
562 for ((var) = BNX2X_NUM_ETH_QUEUES(sc); \
563 (var) < BNX2X_NUM_QUEUES(sc); \
572 #define FCOE_IDX(sc) (BNX2X_NUM_NON_CNIC_QUEUES(sc) + FCOE_IDX_OFFSET)
573 #define bnx2x_fcoe_fp(sc) (&sc->fp[FCOE_IDX(sc)])
574 #define bnx2x_fcoe(sc, var) (bnx2x_fcoe_fp(sc)->var)
575 #define bnx2x_fcoe_inner_sp_obj(sc) (&sc->sp_objs[FCOE_IDX(sc)])
576 #define bnx2x_fcoe_sp_obj(sc, var) (bnx2x_fcoe_inner_sp_obj(sc)->var)
577 #define bnx2x_fcoe_tx(sc, var) (bnx2x_fcoe_fp(sc)->txdata_ptr[FIRST_TX_COS_INDEX]->var)
579 #define OOO_IDX(sc) (BNX2X_NUM_NON_CNIC_QUEUES(sc) + OOO_IDX_OFFSET)
580 #define bnx2x_ooo_fp(sc) (&sc->fp[OOO_IDX(sc)])
581 #define bnx2x_ooo(sc, var) (bnx2x_ooo_fp(sc)->var)
582 #define bnx2x_ooo_inner_sp_obj(sc) (&sc->sp_objs[OOO_IDX(sc)])
583 #define bnx2x_ooo_sp_obj(sc, var) (bnx2x_ooo_inner_sp_obj(sc)->var)
585 #define FWD_IDX(sc) (BNX2X_NUM_NON_CNIC_QUEUES(sc) + FWD_IDX_OFFSET)
586 #define bnx2x_fwd_fp(sc) (&sc->fp[FWD_IDX(sc)])
587 #define bnx2x_fwd(sc, var) (bnx2x_fwd_fp(sc)->var)
588 #define bnx2x_fwd_inner_sp_obj(sc) (&sc->sp_objs[FWD_IDX(sc)])
589 #define bnx2x_fwd_sp_obj(sc, var) (bnx2x_fwd_inner_sp_obj(sc)->var)
590 #define bnx2x_fwd_txdata(fp) (fp->txdata_ptr[FIRST_TX_COS_INDEX])
592 #define IS_ETH_FP(fp) ((fp)->index < BNX2X_NUM_ETH_QUEUES((fp)->sc))
593 #define IS_FCOE_FP(fp) ((fp)->index == FCOE_IDX((fp)->sc))
594 #define IS_FCOE_IDX(idx) ((idx) == FCOE_IDX(sc))
595 #define IS_FWD_FP(fp) ((fp)->index == FWD_IDX((fp)->sc))
596 #define IS_FWD_IDX(idx) ((idx) == FWD_IDX(sc))
597 #define IS_OOO_FP(fp) ((fp)->index == OOO_IDX((fp)->sc))
598 #define IS_OOO_IDX(idx) ((idx) == OOO_IDX(sc))
601 BNX2X_PORT_QUERY_IDX,
603 BNX2X_FCOE_QUERY_IDX,
604 BNX2X_FIRST_QUEUE_QUERY_IDX,
607 struct bnx2x_fw_stats_req {
608 struct stats_query_header hdr;
609 struct stats_query_entry query[FP_SB_MAX_E1x +
610 BNX2X_FIRST_QUEUE_QUERY_IDX];
613 struct bnx2x_fw_stats_data {
614 struct stats_counter storm_counters;
615 struct per_port_stats port;
616 struct per_pf_stats pf;
617 struct per_queue_stats queue_stats[1];
620 /* IGU MSIX STATISTICS on 57712: 64 for VFs; 4 for PFs; 4 for Attentions */
621 #define BNX2X_IGU_STAS_MSG_VF_CNT 64
622 #define BNX2X_IGU_STAS_MSG_PF_CNT 4
627 * This is the slowpath data structure. It is mapped into non-paged memory
628 * so that the hardware can access it's contents directly and must be page
631 struct bnx2x_slowpath {
633 /* used by the DMAE command executer */
634 struct dmae_command dmae[MAX_DMAE_C];
636 /* statistics completion */
639 /* firmware defined statistics blocks */
640 union mac_stats mac_stats;
641 struct nig_stats nig_stats;
642 struct host_port_stats port_stats;
643 struct host_func_stats func_stats;
645 /* DMAE completion value and data source/sink */
650 struct mac_configuration_cmd e1x;
651 struct eth_classify_rules_ramrod_data e2;
655 struct tstorm_eth_mac_filter_config e1x;
656 struct eth_filter_rules_ramrod_data e2;
659 struct eth_rss_update_ramrod_data rss_rdata;
662 struct mac_configuration_cmd e1;
663 struct eth_multicast_rules_ramrod_data e2;
667 struct function_start_data func_start;
668 struct flow_control_configuration pfc_config; /* for DCBX ramrod */
671 /* Queue State related ramrods */
673 struct client_init_ramrod_data init_data;
674 struct client_update_ramrod_data update_data;
678 * AFEX ramrod can not be a part of func_rdata union because these
679 * events might arrive in parallel to other events from func_rdata.
680 * If they were defined in the same union the data can get corrupted.
682 struct afex_vif_list_ramrod_data func_afex_rdata;
684 union drv_info_to_mcp drv_info_to_mcp;
685 }; /* struct bnx2x_slowpath */
688 * Port specifc data structure.
692 * Port Management Function (for 57711E only).
693 * When this field is set the driver instance is
694 * responsible for managing port specifc
695 * configurations such as handling link attentions.
699 /* Ethernet maximum transmission unit. */
702 uint32_t link_config[ELINK_LINK_CONFIG_SIZE];
704 uint32_t ext_phy_config;
706 /* Port feature config.*/
709 /* Defines the features supported by the PHY. */
710 uint32_t supported[ELINK_LINK_CONFIG_SIZE];
712 /* Defines the features advertised by the PHY. */
713 uint32_t advertising[ELINK_LINK_CONFIG_SIZE];
714 #define ADVERTISED_10baseT_Half (1 << 1)
715 #define ADVERTISED_10baseT_Full (1 << 2)
716 #define ADVERTISED_100baseT_Half (1 << 3)
717 #define ADVERTISED_100baseT_Full (1 << 4)
718 #define ADVERTISED_1000baseT_Half (1 << 5)
719 #define ADVERTISED_1000baseT_Full (1 << 6)
720 #define ADVERTISED_TP (1 << 7)
721 #define ADVERTISED_FIBRE (1 << 8)
722 #define ADVERTISED_Autoneg (1 << 9)
723 #define ADVERTISED_Asym_Pause (1 << 10)
724 #define ADVERTISED_Pause (1 << 11)
725 #define ADVERTISED_2500baseX_Full (1 << 15)
726 #define ADVERTISED_10000baseT_Full (1 << 16)
730 /* Used to synchronize phy accesses. */
731 rte_spinlock_t phy_mtx;
732 char phy_mtx_name[32];
734 #define BNX2X_PHY_LOCK(sc) rte_spinlock_lock(&sc->port.phy_mtx)
735 #define BNX2X_PHY_UNLOCK(sc) rte_spinlock_unlock(&sc->port.phy_mtx)
738 * MCP scratchpad address for port specific statistics.
739 * The device is responsible for writing statistcss
740 * back to the MCP for use with management firmware such
745 struct nig_stats old_nig_stats;
746 }; /* struct bnx2x_port */
748 struct bnx2x_mf_info {
749 uint32_t mf_config[E1HVN_MAX];
751 uint32_t vnics_per_port; /* 1, 2 or 4 */
752 uint32_t multi_vnics_mode; /* can be set even if vnics_per_port = 1 */
753 uint32_t path_has_ovlan; /* MF mode in the path (can be different than the MF mode of the function */
755 #define IS_MULTI_VNIC(sc) ((sc)->devinfo.mf_info.multi_vnics_mode)
756 #define VNICS_PER_PORT(sc) ((sc)->devinfo.mf_info.vnics_per_port)
757 #define VNICS_PER_PATH(sc) \
758 ((sc)->devinfo.mf_info.vnics_per_port * \
759 ((CHIP_PORT_MODE(sc) == CHIP_4_PORT_MODE) ? 2 : 1 ))
761 uint8_t min_bw[MAX_VNIC_NUM];
762 uint8_t max_bw[MAX_VNIC_NUM];
764 uint16_t ext_id; /* vnic outer vlan or VIF ID */
765 #define VALID_OVLAN(ovlan) ((ovlan) <= 4096)
766 #define INVALID_VIF_ID 0xFFFF
767 #define OVLAN(sc) ((sc)->devinfo.mf_info.ext_id)
768 #define VIF_ID(sc) ((sc)->devinfo.mf_info.ext_id)
770 uint16_t default_vlan;
771 #define NIV_DEFAULT_VLAN(sc) ((sc)->devinfo.mf_info.default_vlan)
773 uint8_t niv_allowed_priorities;
774 #define NIV_ALLOWED_PRIORITIES(sc) ((sc)->devinfo.mf_info.niv_allowed_priorities)
776 uint8_t niv_default_cos;
777 #define NIV_DEFAULT_COS(sc) ((sc)->devinfo.mf_info.niv_default_cos)
779 uint8_t niv_mba_enabled;
781 enum mf_cfg_afex_vlan_mode afex_vlan_mode;
782 #define AFEX_VLAN_MODE(sc) ((sc)->devinfo.mf_info.afex_vlan_mode)
783 int afex_def_vlan_tag;
784 uint32_t pending_max;
787 #define MF_INFO_VALID_MAC 0x0001
790 uint8_t mf_mode; /* Switch-Dependent or Switch-Independent */
792 (IS_MULTI_VNIC(sc) && \
793 ((sc)->devinfo.mf_info.mf_mode != 0))
794 #define IS_MF_SD(sc) \
795 (IS_MULTI_VNIC(sc) && \
796 ((sc)->devinfo.mf_info.mf_mode == MULTI_FUNCTION_SD))
797 #define IS_MF_SI(sc) \
798 (IS_MULTI_VNIC(sc) && \
799 ((sc)->devinfo.mf_info.mf_mode == MULTI_FUNCTION_SI))
800 #define IS_MF_AFEX(sc) \
801 (IS_MULTI_VNIC(sc) && \
802 ((sc)->devinfo.mf_info.mf_mode == MULTI_FUNCTION_AFEX))
803 #define IS_MF_SD_MODE(sc) IS_MF_SD(sc)
804 #define IS_MF_SI_MODE(sc) IS_MF_SI(sc)
805 #define IS_MF_AFEX_MODE(sc) IS_MF_AFEX(sc)
807 uint32_t mf_protos_supported;
808 #define MF_PROTO_SUPPORT_ETHERNET 0x1
809 #define MF_PROTO_SUPPORT_ISCSI 0x2
810 #define MF_PROTO_SUPPORT_FCOE 0x4
811 }; /* struct bnx2x_mf_info */
813 /* Device information data structure. */
814 struct bnx2x_devinfo {
816 #define NAME_SIZE 128
817 char name[NAME_SIZE];
822 uint16_t subvendor_id;
823 uint16_t subdevice_id;
826 * chip_id = 0b'CCCCCCCCCCCCCCCCRRRRMMMMMMMMBBBB'
827 * C = Chip Number (bits 16-31)
828 * R = Chip Revision (bits 12-15)
829 * M = Chip Metal (bits 4-11)
830 * B = Chip Bond ID (bits 0-3)
833 #define CHIP_ID(sc) ((sc)->devinfo.chip_id & 0xffff0000)
834 #define CHIP_NUM(sc) ((sc)->devinfo.chip_id >> 16)
836 #define CHIP_NUM_57711 0x164f
837 #define CHIP_NUM_57711E 0x1650
838 #define CHIP_NUM_57712 0x1662
839 #define CHIP_NUM_57712_MF 0x1663
840 #define CHIP_NUM_57712_VF 0x166f
841 #define CHIP_NUM_57800 0x168a
842 #define CHIP_NUM_57800_MF 0x16a5
843 #define CHIP_NUM_57800_VF 0x16a9
844 #define CHIP_NUM_57810 0x168e
845 #define CHIP_NUM_57810_MF 0x16ae
846 #define CHIP_NUM_57810_VF 0x16af
847 #define CHIP_NUM_57811 0x163d
848 #define CHIP_NUM_57811_MF 0x163e
849 #define CHIP_NUM_57811_VF 0x163f
850 #define CHIP_NUM_57840_OBS 0x168d
851 #define CHIP_NUM_57840_OBS_MF 0x16ab
852 #define CHIP_NUM_57840_4_10 0x16a1
853 #define CHIP_NUM_57840_2_20 0x16a2
854 #define CHIP_NUM_57840_MF 0x16a4
855 #define CHIP_NUM_57840_VF 0x16ad
857 #define CHIP_REV_SHIFT 12
858 #define CHIP_REV_MASK (0xF << CHIP_REV_SHIFT)
859 #define CHIP_REV(sc) ((sc)->devinfo.chip_id & CHIP_REV_MASK)
861 #define CHIP_REV_Ax (0x0 << CHIP_REV_SHIFT)
862 #define CHIP_REV_Bx (0x1 << CHIP_REV_SHIFT)
863 #define CHIP_REV_Cx (0x2 << CHIP_REV_SHIFT)
865 #define CHIP_REV_IS_SLOW(sc) \
866 (CHIP_REV(sc) > 0x00005000)
867 #define CHIP_REV_IS_FPGA(sc) \
868 (CHIP_REV_IS_SLOW(sc) && (CHIP_REV(sc) & 0x00001000))
869 #define CHIP_REV_IS_EMUL(sc) \
870 (CHIP_REV_IS_SLOW(sc) && !(CHIP_REV(sc) & 0x00001000))
871 #define CHIP_REV_IS_ASIC(sc) \
872 (!CHIP_REV_IS_SLOW(sc))
874 #define CHIP_METAL(sc) ((sc->devinfo.chip_id) & 0x00000ff0)
875 #define CHIP_BOND_ID(sc) ((sc->devinfo.chip_id) & 0x0000000f)
877 #define CHIP_IS_57711(sc) (CHIP_NUM(sc) == CHIP_NUM_57711)
878 #define CHIP_IS_57711E(sc) (CHIP_NUM(sc) == CHIP_NUM_57711E)
879 #define CHIP_IS_E1H(sc) ((CHIP_IS_57711(sc)) || \
880 (CHIP_IS_57711E(sc)))
881 #define CHIP_IS_E1x(sc) CHIP_IS_E1H(sc)
883 #define CHIP_IS_57712(sc) (CHIP_NUM(sc) == CHIP_NUM_57712)
884 #define CHIP_IS_57712_MF(sc) (CHIP_NUM(sc) == CHIP_NUM_57712_MF)
885 #define CHIP_IS_57712_VF(sc) (CHIP_NUM(sc) == CHIP_NUM_57712_VF)
886 #define CHIP_IS_E2(sc) (CHIP_IS_57712(sc) || \
887 CHIP_IS_57712_MF(sc))
889 #define CHIP_IS_57800(sc) (CHIP_NUM(sc) == CHIP_NUM_57800)
890 #define CHIP_IS_57800_MF(sc) (CHIP_NUM(sc) == CHIP_NUM_57800_MF)
891 #define CHIP_IS_57800_VF(sc) (CHIP_NUM(sc) == CHIP_NUM_57800_VF)
892 #define CHIP_IS_57810(sc) (CHIP_NUM(sc) == CHIP_NUM_57810)
893 #define CHIP_IS_57810_MF(sc) (CHIP_NUM(sc) == CHIP_NUM_57810_MF)
894 #define CHIP_IS_57810_VF(sc) (CHIP_NUM(sc) == CHIP_NUM_57810_VF)
895 #define CHIP_IS_57811(sc) (CHIP_NUM(sc) == CHIP_NUM_57811)
896 #define CHIP_IS_57811_MF(sc) (CHIP_NUM(sc) == CHIP_NUM_57811_MF)
897 #define CHIP_IS_57811_VF(sc) (CHIP_NUM(sc) == CHIP_NUM_57811_VF)
898 #define CHIP_IS_57840(sc) ((CHIP_NUM(sc) == CHIP_NUM_57840_OBS) || \
899 (CHIP_NUM(sc) == CHIP_NUM_57840_4_10) || \
900 (CHIP_NUM(sc) == CHIP_NUM_57840_2_20))
901 #define CHIP_IS_57840_MF(sc) ((CHIP_NUM(sc) == CHIP_NUM_57840_OBS_MF) || \
902 (CHIP_NUM(sc) == CHIP_NUM_57840_MF))
903 #define CHIP_IS_57840_VF(sc) (CHIP_NUM(sc) == CHIP_NUM_57840_VF)
905 #define CHIP_IS_E3(sc) (CHIP_IS_57800(sc) || \
906 CHIP_IS_57800_MF(sc) || \
907 CHIP_IS_57800_VF(sc) || \
908 CHIP_IS_57810(sc) || \
909 CHIP_IS_57810_MF(sc) || \
910 CHIP_IS_57810_VF(sc) || \
911 CHIP_IS_57811(sc) || \
912 CHIP_IS_57811_MF(sc) || \
913 CHIP_IS_57811_VF(sc) || \
914 CHIP_IS_57840(sc) || \
915 CHIP_IS_57840_MF(sc) || \
916 CHIP_IS_57840_VF(sc))
917 #define CHIP_IS_E3A0(sc) (CHIP_IS_E3(sc) && \
918 (CHIP_REV(sc) == CHIP_REV_Ax))
919 #define CHIP_IS_E3B0(sc) (CHIP_IS_E3(sc) && \
920 (CHIP_REV(sc) == CHIP_REV_Bx))
922 #define USES_WARPCORE(sc) (CHIP_IS_E3(sc))
923 #define CHIP_IS_E2E3(sc) (CHIP_IS_E2(sc) || \
926 #define CHIP_IS_MF_CAP(sc) (CHIP_IS_57711E(sc) || \
927 CHIP_IS_57712_MF(sc) || \
930 #define IS_VF(sc) ((sc)->flags & BNX2X_IS_VF_FLAG)
931 #define IS_PF(sc) (!IS_VF(sc))
934 * This define is used in two main places:
935 * 1. In the early stages of nic_load, to know if to configure Parser/Searcher
936 * to nic-only mode or to offload mode. Offload mode is configured if either
937 * the chip is E1x (where NIC_MODE register is not applicable), or if cnic
938 * already registered for this port (which means that the user wants storage
940 * 2. During cnic-related load, to know if offload mode is already configured
941 * in the HW or needs to be configrued. Since the transition from nic-mode to
942 * offload-mode in HW causes traffic coruption, nic-mode is configured only
943 * in ports on which storage services where never requested.
945 #define CONFIGURE_NIC_MODE(sc) (!CHIP_IS_E1x(sc) && !CNIC_ENABLED(sc))
947 uint8_t chip_port_mode;
948 #define CHIP_4_PORT_MODE 0x0
949 #define CHIP_2_PORT_MODE 0x1
950 #define CHIP_PORT_MODE_NONE 0x2
951 #define CHIP_PORT_MODE(sc) ((sc)->devinfo.chip_port_mode)
952 #define CHIP_IS_MODE_4_PORT(sc) (CHIP_PORT_MODE(sc) == CHIP_4_PORT_MODE)
955 #define INT_BLOCK_HC 0
956 #define INT_BLOCK_IGU 1
957 #define INT_BLOCK_MODE_NORMAL 0
958 #define INT_BLOCK_MODE_BW_COMP 2
959 #define CHIP_INT_MODE_IS_NBC(sc) \
960 (!CHIP_IS_E1x(sc) && \
961 !((sc)->devinfo.int_block & INT_BLOCK_MODE_BW_COMP))
962 #define CHIP_INT_MODE_IS_BC(sc) (!CHIP_INT_MODE_IS_NBC(sc))
965 uint32_t shmem2_base;
968 uint32_t mf_cfg_base; /* bootcode shmem address in BAR memory */
969 struct bnx2x_mf_info mf_info;
972 #define NVRAM_1MB_SIZE 0x20000
973 #define NVRAM_TIMEOUT_COUNT 30000
974 #define NVRAM_PAGE_SIZE 256
976 /* PCIe capability information */
977 uint32_t pcie_cap_flags;
978 #define BNX2X_PM_CAPABLE_FLAG 0x00000001
979 #define BNX2X_PCIE_CAPABLE_FLAG 0x00000002
980 #define BNX2X_MSI_CAPABLE_FLAG 0x00000004
981 #define BNX2X_MSIX_CAPABLE_FLAG 0x00000008
982 uint16_t pcie_pm_cap_reg;
983 uint16_t pcie_link_width;
984 uint16_t pcie_link_speed;
985 uint16_t pcie_msi_cap_reg;
986 uint16_t pcie_msix_cap_reg;
988 /* device configuration read from bootcode shared memory */
991 }; /* struct bnx2x_devinfo */
993 struct bnx2x_sp_objs {
994 struct ecore_vlan_mac_obj mac_obj; /* MACs object */
995 struct ecore_queue_sp_obj q_obj; /* Queue State object */
996 }; /* struct bnx2x_sp_objs */
999 * Data that will be used to create a link report message. We will keep the
1000 * data used for the last link report in order to prevent reporting the same
1001 * link parameters twice.
1003 struct bnx2x_link_report_data {
1004 uint16_t line_speed; /* Effective line speed */
1005 unsigned long link_report_flags; /* BNX2X_LINK_REPORT_XXX flags */
1009 BNX2X_LINK_REPORT_FULL_DUPLEX,
1010 BNX2X_LINK_REPORT_LINK_DOWN,
1011 BNX2X_LINK_REPORT_RX_FC_ON,
1012 BNX2X_LINK_REPORT_TX_FC_ON
1015 #define BNX2X_RX_CHAIN_PAGE_SZ BNX2X_PAGE_SIZE
1017 struct bnx2x_pci_cap {
1018 struct bnx2x_pci_cap *next;
1026 /* Top level device private data structure. */
1027 struct bnx2x_softc {
1031 uint32_t max_tx_queues;
1032 uint32_t max_rx_queues;
1033 const struct rte_pci_device *pci_dev;
1035 struct bnx2x_pci_cap *pci_caps;
1036 #define BNX2X_INTRS_POLL_PERIOD 1
1041 /* MAC address operations */
1042 struct bnx2x_mac_ops mac_ops;
1044 /* structures for VF mbox/response/bulletin */
1045 struct bnx2x_vf_mbx_msg *vf2pf_mbox;
1046 struct bnx2x_dma vf2pf_mbox_mapping;
1047 struct vf_acquire_resp_tlv acquire_resp;
1048 struct bnx2x_vf_bulletin *pf2vf_bulletin;
1049 struct bnx2x_dma pf2vf_bulletin_mapping;
1050 struct bnx2x_vf_bulletin old_bulletin;
1051 rte_spinlock_t vf2pf_lock;
1055 int state; /* device state */
1056 #define BNX2X_STATE_CLOSED 0x0000
1057 #define BNX2X_STATE_OPENING_WAITING_LOAD 0x1000
1058 #define BNX2X_STATE_OPENING_WAITING_PORT 0x2000
1059 #define BNX2X_STATE_OPEN 0x3000
1060 #define BNX2X_STATE_CLOSING_WAITING_HALT 0x4000
1061 #define BNX2X_STATE_CLOSING_WAITING_DELETE 0x5000
1062 #define BNX2X_STATE_CLOSING_WAITING_UNLOAD 0x6000
1063 #define BNX2X_STATE_DISABLED 0xD000
1064 #define BNX2X_STATE_DIAG 0xE000
1065 #define BNX2X_STATE_ERROR 0xF000
1068 #define BNX2X_ONE_PORT_FLAG 0x1
1069 #define BNX2X_NO_FCOE_FLAG 0x2
1070 #define BNX2X_NO_WOL_FLAG 0x4
1071 #define BNX2X_NO_MCP_FLAG 0x8
1072 #define BNX2X_NO_ISCSI_OOO_FLAG 0x10
1073 #define BNX2X_NO_ISCSI_FLAG 0x20
1074 #define BNX2X_MF_FUNC_DIS 0x40
1075 #define BNX2X_TX_SWITCHING 0x80
1076 #define BNX2X_IS_VF_FLAG 0x100
1078 #define BNX2X_ONE_PORT(sc) (sc->flags & BNX2X_ONE_PORT_FLAG)
1079 #define BNX2X_NOFCOE(sc) (sc->flags & BNX2X_NO_FCOE_FLAG)
1080 #define BNX2X_NOMCP(sc) (sc->flags & BNX2X_NO_MCP_FLAG)
1083 struct bnx2x_bar bar[MAX_BARS]; /* map BARs 0, 2, 4 */
1085 uint16_t doorbell_size;
1087 /* periodic timer callout */
1088 #define PERIODIC_STOP 0
1089 #define PERIODIC_GO 1
1090 volatile unsigned long periodic_flags;
1092 struct bnx2x_fastpath fp[MAX_RSS_CHAINS];
1093 struct bnx2x_sp_objs sp_objs[MAX_RSS_CHAINS];
1095 uint8_t unit; /* driver instance number */
1097 int pcie_bus; /* PCIe bus number */
1098 int pcie_device; /* PCIe device/slot number */
1099 int pcie_func; /* PCIe function number */
1101 uint8_t pfunc_rel; /* function relative */
1102 uint8_t pfunc_abs; /* function absolute */
1103 uint8_t path_id; /* function absolute */
1104 #define SC_PATH(sc) (sc->path_id)
1105 #define SC_PORT(sc) (sc->pfunc_rel & 1)
1106 #define SC_FUNC(sc) (sc->pfunc_rel)
1107 #define SC_ABS_FUNC(sc) (sc->pfunc_abs)
1108 #define SC_VN(sc) (sc->pfunc_rel >> 1)
1109 #define SC_L_ID(sc) (SC_VN(sc) << 2)
1110 #define PORT_ID(sc) SC_PORT(sc)
1111 #define PATH_ID(sc) SC_PATH(sc)
1112 #define VNIC_ID(sc) SC_VN(sc)
1113 #define FUNC_ID(sc) SC_FUNC(sc)
1114 #define ABS_FUNC_ID(sc) SC_ABS_FUNC(sc)
1115 #define SC_FW_MB_IDX_VN(sc, vn) \
1116 (SC_PORT(sc) + (vn) * \
1117 ((CHIP_IS_E1x(sc) || (CHIP_IS_MODE_4_PORT(sc))) ? 2 : 1))
1118 #define SC_FW_MB_IDX(sc) SC_FW_MB_IDX_VN(sc, SC_VN(sc))
1120 int if_capen; /* enabled interface capabilities */
1122 struct bnx2x_devinfo devinfo;
1123 char fw_ver_str[32];
1124 char mf_mode_str[32];
1125 char pci_link_str[32];
1127 struct iro *iro_array;
1130 #define DMAE_READY(sc) (sc->dmae_ready)
1132 struct ecore_credit_pool_obj vlans_pool;
1133 struct ecore_credit_pool_obj macs_pool;
1134 struct ecore_rx_mode_obj rx_mode_obj;
1135 struct ecore_mcast_obj mcast_obj;
1136 struct ecore_rss_config_obj rss_conf_obj;
1137 struct ecore_func_sp_obj func_obj;
1140 uint16_t fw_drv_pulse_wr_seq;
1143 struct elink_params link_params;
1144 struct elink_vars link_vars;
1146 struct bnx2x_link_report_data last_reported_link;
1147 char mac_addr_str[32];
1149 uint32_t tx_ring_size;
1150 uint32_t rx_ring_size;
1155 #define BNX2X_RECOVERY_DONE 1
1156 #define BNX2X_RECOVERY_INIT 2
1157 #define BNX2X_RECOVERY_WAIT 3
1158 #define BNX2X_RECOVERY_FAILED 4
1159 #define BNX2X_RECOVERY_NIC_LOADING 5
1162 #define BNX2X_RX_MODE_NONE 0
1163 #define BNX2X_RX_MODE_NORMAL 1
1164 #define BNX2X_RX_MODE_ALLMULTI 2
1165 #define BNX2X_RX_MODE_ALLMULTI_PROMISC 3
1166 #define BNX2X_RX_MODE_PROMISC 4
1167 #define BNX2X_MAX_MULTICAST 64
1169 struct bnx2x_port port;
1171 struct cmng_init cmng;
1179 #define INTR_MODE_INTX 0
1180 #define INTR_MODE_MSI 1
1181 #define INTR_MODE_MSIX 2
1182 #define INTR_MODE_SINGLE_MSIX 3
1186 uint8_t igu_base_sb;
1188 uint32_t igu_base_addr;
1189 uint8_t base_fw_ndsb;
1190 #define DEF_SB_IGU_ID 16
1191 #define DEF_SB_ID HC_SP_SB_ID
1193 /* default status block */
1194 struct bnx2x_dma def_sb_dma;
1195 struct host_sp_status_block *def_sb;
1197 uint16_t def_att_idx;
1198 uint32_t attn_state;
1199 struct attn_route attn_group[MAX_DYNAMIC_ATTN_GRPS];
1201 /* general SP events - stats query, cfc delete, etc */
1202 #define HC_SP_INDEX_ETH_DEF_CONS 3
1203 /* EQ completions */
1204 #define HC_SP_INDEX_EQ_CONS 7
1205 /* FCoE L2 connection completions */
1206 #define HC_SP_INDEX_ETH_FCOE_TX_CQ_CONS 6
1207 #define HC_SP_INDEX_ETH_FCOE_RX_CQ_CONS 4
1209 #define HC_SP_INDEX_ETH_ISCSI_CQ_CONS 5
1210 #define HC_SP_INDEX_ETH_ISCSI_RX_CQ_CONS 1
1213 struct bnx2x_dma eq_dma;
1214 union event_ring_elem *eq;
1217 uint16_t *eq_cons_sb;
1218 #define NUM_EQ_PAGES 1 /* must be a power of 2 */
1219 #define EQ_DESC_CNT_PAGE (BNX2X_PAGE_SIZE / sizeof(union event_ring_elem))
1220 #define EQ_DESC_MAX_PAGE (EQ_DESC_CNT_PAGE - 1)
1221 #define NUM_EQ_DESC (EQ_DESC_CNT_PAGE * NUM_EQ_PAGES)
1222 #define EQ_DESC_MASK (NUM_EQ_DESC - 1)
1223 #define MAX_EQ_AVAIL (EQ_DESC_MAX_PAGE * NUM_EQ_PAGES - 2)
1224 /* depends on EQ_DESC_CNT_PAGE being a power of 2 */
1225 #define NEXT_EQ_IDX(x) \
1226 ((((x) & EQ_DESC_MAX_PAGE) == (EQ_DESC_MAX_PAGE - 1)) ? \
1227 ((x) + 2) : ((x) + 1))
1228 /* depends on the above and on NUM_EQ_PAGES being a power of 2 */
1229 #define EQ_DESC(x) ((x) & EQ_DESC_MASK)
1232 struct bnx2x_dma sp_dma;
1233 struct bnx2x_slowpath *sp;
1234 unsigned long sp_state;
1236 /* slow path queue */
1237 struct bnx2x_dma spq_dma;
1238 struct eth_spe *spq;
1239 #define SP_DESC_CNT (BNX2X_PAGE_SIZE / sizeof(struct eth_spe))
1240 #define MAX_SP_DESC_CNT (SP_DESC_CNT - 1)
1241 #define MAX_SPQ_PENDING 8
1243 uint16_t spq_prod_idx;
1244 struct eth_spe *spq_prod_bd;
1245 struct eth_spe *spq_last_bd;
1246 uint16_t *dsb_sp_prod;
1248 volatile unsigned long eq_spq_left; /* COMMON_xxx ramrod credit */
1249 volatile unsigned long cq_spq_left; /* ETH_xxx ramrod credit */
1251 /* fw decompression buffer */
1252 struct bnx2x_dma gz_buf_dma;
1255 #define GUNZIP_BUF(sc) (sc->gz_buf)
1256 #define GUNZIP_OUTLEN(sc) (sc->gz_outlen)
1257 #define GUNZIP_PHYS(sc) (rte_iova_t)(sc->gz_buf_dma.paddr)
1258 #define FW_BUF_SIZE 0x40000
1260 struct raw_op *init_ops;
1261 uint16_t *init_ops_offsets; /* init block offsets inside init_ops */
1262 uint32_t *init_data; /* data blob, 32 bit granularity */
1263 uint32_t init_mode_flags;
1264 #define INIT_MODE_FLAGS(sc) (sc->init_mode_flags)
1265 /* PRAM blobs - raw data */
1266 const uint8_t *tsem_int_table_data;
1267 const uint8_t *tsem_pram_data;
1268 const uint8_t *usem_int_table_data;
1269 const uint8_t *usem_pram_data;
1270 const uint8_t *xsem_int_table_data;
1271 const uint8_t *xsem_pram_data;
1272 const uint8_t *csem_int_table_data;
1273 const uint8_t *csem_pram_data;
1274 #define INIT_OPS(sc) (sc->init_ops)
1275 #define INIT_OPS_OFFSETS(sc) (sc->init_ops_offsets)
1276 #define INIT_DATA(sc) (sc->init_data)
1277 #define INIT_TSEM_INT_TABLE_DATA(sc) (sc->tsem_int_table_data)
1278 #define INIT_TSEM_PRAM_DATA(sc) (sc->tsem_pram_data)
1279 #define INIT_USEM_INT_TABLE_DATA(sc) (sc->usem_int_table_data)
1280 #define INIT_USEM_PRAM_DATA(sc) (sc->usem_pram_data)
1281 #define INIT_XSEM_INT_TABLE_DATA(sc) (sc->xsem_int_table_data)
1282 #define INIT_XSEM_PRAM_DATA(sc) (sc->xsem_pram_data)
1283 #define INIT_CSEM_INT_TABLE_DATA(sc) (sc->csem_int_table_data)
1284 #define INIT_CSEM_PRAM_DATA(sc) (sc->csem_pram_data)
1286 #define PHY_FW_VER_LEN 20
1290 * For max 196 cids (64*3 + non-eth), 32KB ILT page size and 1KB
1291 * context size we need 8 ILT entries.
1293 #define ILT_MAX_L2_LINES 8
1294 struct hw_context context[ILT_MAX_L2_LINES];
1295 struct ecore_ilt *ilt;
1296 #define ILT_MAX_LINES 256
1298 /* max supported number of RSS queues: IGU SBs minus one for CNIC */
1299 #define BNX2X_MAX_RSS_COUNT(sc) ((sc)->igu_sb_cnt - CNIC_SUPPORT(sc))
1300 /* max CID count: Max RSS * Max_Tx_Multi_Cos + FCoE + iSCSI */
1301 #define BNX2X_L2_MAX_CID(sc) \
1302 (BNX2X_MAX_RSS_COUNT(sc) * ECORE_MULTI_TX_COS + 2 * CNIC_SUPPORT(sc))
1303 #define BNX2X_L2_CID_COUNT(sc) \
1304 (BNX2X_NUM_ETH_QUEUES(sc) * ECORE_MULTI_TX_COS + 2 * CNIC_SUPPORT(sc))
1305 #define L2_ILT_LINES(sc) \
1306 (DIV_ROUND_UP(BNX2X_L2_CID_COUNT(sc), ILT_PAGE_CIDS))
1310 uint8_t dropless_fc;
1312 /* total number of FW statistics requests */
1313 uint8_t fw_stats_num;
1315 * This is a memory buffer that will contain both statistics ramrod
1318 struct bnx2x_dma fw_stats_dma;
1320 * FW statistics request shortcut (points at the beginning of fw_stats
1323 int fw_stats_req_size;
1324 struct bnx2x_fw_stats_req *fw_stats_req;
1325 rte_iova_t fw_stats_req_mapping;
1327 * FW statistics data shortcut (points at the beginning of fw_stats
1328 * buffer + fw_stats_req_size).
1330 int fw_stats_data_size;
1331 struct bnx2x_fw_stats_data *fw_stats_data;
1332 rte_iova_t fw_stats_data_mapping;
1334 /* tracking a pending STAT_QUERY ramrod */
1335 uint16_t stats_pending;
1336 /* number of completed statistics ramrods */
1337 uint16_t stats_comp;
1338 uint16_t stats_counter;
1342 struct bnx2x_eth_stats eth_stats;
1343 struct host_func_stats func_stats;
1344 struct bnx2x_eth_stats_old eth_stats_old;
1345 struct bnx2x_net_stats_old net_stats_old;
1346 struct bnx2x_fw_port_stats_old fw_stats_old;
1348 struct dmae_command stats_dmae; /* used by dmae command loader */
1353 /* DCB support on/off */
1355 #define BNX2X_DCB_STATE_OFF 0
1356 #define BNX2X_DCB_STATE_ON 1
1357 /* DCBX engine mode */
1359 #define BNX2X_DCBX_ENABLED_OFF 0
1360 #define BNX2X_DCBX_ENABLED_ON_NEG_OFF 1
1361 #define BNX2X_DCBX_ENABLED_ON_NEG_ON 2
1362 #define BNX2X_DCBX_ENABLED_INVALID -1
1364 uint8_t cnic_support;
1365 uint8_t cnic_enabled;
1366 uint8_t cnic_loaded;
1367 #define CNIC_SUPPORT(sc) 0 /* ((sc)->cnic_support) */
1368 #define CNIC_ENABLED(sc) 0 /* ((sc)->cnic_enabled) */
1369 #define CNIC_LOADED(sc) 0 /* ((sc)->cnic_loaded) */
1371 /* multiple tx classes of service */
1373 #define BNX2X_MAX_PRIORITY 8
1374 /* priority to cos mapping */
1375 uint8_t prio_to_cos[BNX2X_MAX_PRIORITY];
1378 }; /* struct bnx2x_softc */
1380 /* IOCTL sub-commands for edebug and firmware upgrade */
1381 #define BNX2X_IOC_RD_NVRAM 1
1382 #define BNX2X_IOC_WR_NVRAM 2
1383 #define BNX2X_IOC_STATS_SHOW_NUM 3
1384 #define BNX2X_IOC_STATS_SHOW_STR 4
1385 #define BNX2X_IOC_STATS_SHOW_CNT 5
1387 struct bnx2x_nvram_data {
1388 uint32_t op; /* ioctl sub-command */
1391 uint32_t value[1]; /* variable */
1394 union bnx2x_stats_show_data {
1395 uint32_t op; /* ioctl sub-command */
1398 uint32_t num; /* return number of stats */
1399 uint32_t len; /* length of each string item */
1402 /* variable length... */
1403 char str[1]; /* holds names of desc.num stats, each desc.len in length */
1405 /* variable length... */
1406 uint64_t stats[1]; /* holds all stats */
1409 /* function init flags */
1410 #define FUNC_FLG_RSS 0x0001
1411 #define FUNC_FLG_STATS 0x0002
1412 /* FUNC_FLG_UNMATCHED 0x0004 */
1413 #define FUNC_FLG_SPQ 0x0010
1414 #define FUNC_FLG_LEADING 0x0020 /* PF only */
1416 struct bnx2x_func_init_params {
1417 rte_iova_t fw_stat_map; /* (dma) valid if FUNC_FLG_STATS */
1418 rte_iova_t spq_map; /* (dma) valid if FUNC_FLG_SPQ */
1420 uint16_t func_id; /* abs function id */
1422 uint16_t spq_prod; /* valid if FUNC_FLG_SPQ */
1425 /* memory resources reside at BARs 0, 2, 4 */
1426 /* Run `pciconf -lb` to see mappings */
1432 bnx2x_reg_write8(struct bnx2x_softc *sc, size_t offset, uint8_t val)
1434 PMD_DEBUG_PERIODIC_LOG(DEBUG, sc, "offset=0x%08lx val=0x%02x",
1435 (unsigned long)offset, val);
1436 rte_write8(val, ((uint8_t *)sc->bar[BAR0].base_addr + offset));
1440 bnx2x_reg_write16(struct bnx2x_softc *sc, size_t offset, uint16_t val)
1442 #ifdef RTE_LIBRTE_BNX2X_DEBUG_PERIODIC
1443 if ((offset % 2) != 0)
1444 PMD_DRV_LOG(NOTICE, sc, "Unaligned 16-bit write to 0x%08lx",
1445 (unsigned long)offset);
1447 PMD_DEBUG_PERIODIC_LOG(DEBUG, sc, "offset=0x%08lx val=0x%04x",
1448 (unsigned long)offset, val);
1449 rte_write16(val, ((uint8_t *)sc->bar[BAR0].base_addr + offset));
1454 bnx2x_reg_write32(struct bnx2x_softc *sc, size_t offset, uint32_t val)
1456 #ifdef RTE_LIBRTE_BNX2X_DEBUG_PERIODIC
1457 if ((offset % 4) != 0)
1458 PMD_DRV_LOG(NOTICE, sc, "Unaligned 32-bit write to 0x%08lx",
1459 (unsigned long)offset);
1462 PMD_DEBUG_PERIODIC_LOG(DEBUG, sc, "offset=0x%08lx val=0x%08x",
1463 (unsigned long)offset, val);
1464 rte_write32(val, ((uint8_t *)sc->bar[BAR0].base_addr + offset));
1467 static inline uint8_t
1468 bnx2x_reg_read8(struct bnx2x_softc *sc, size_t offset)
1472 val = rte_read8((uint8_t *)sc->bar[BAR0].base_addr + offset);
1473 PMD_DEBUG_PERIODIC_LOG(DEBUG, sc, "offset=0x%08lx val=0x%02x",
1474 (unsigned long)offset, val);
1479 static inline uint16_t
1480 bnx2x_reg_read16(struct bnx2x_softc *sc, size_t offset)
1484 #ifdef RTE_LIBRTE_BNX2X_DEBUG_PERIODIC
1485 if ((offset % 2) != 0)
1486 PMD_DRV_LOG(NOTICE, sc, "Unaligned 16-bit read from 0x%08lx",
1487 (unsigned long)offset);
1490 val = rte_read16(((uint8_t *)sc->bar[BAR0].base_addr + offset));
1491 PMD_DEBUG_PERIODIC_LOG(DEBUG, sc, "offset=0x%08lx val=0x%08x",
1492 (unsigned long)offset, val);
1497 static inline uint32_t
1498 bnx2x_reg_read32(struct bnx2x_softc *sc, size_t offset)
1502 #ifdef RTE_LIBRTE_BNX2X_DEBUG_PERIODIC
1503 if ((offset % 4) != 0)
1504 PMD_DRV_LOG(NOTICE, sc, "Unaligned 32-bit read from 0x%08lx",
1505 (unsigned long)offset);
1508 val = rte_read32(((uint8_t *)sc->bar[BAR0].base_addr + offset));
1509 PMD_DEBUG_PERIODIC_LOG(DEBUG, sc, "offset=0x%08lx val=0x%08x",
1510 (unsigned long)offset, val);
1515 #define REG_ADDR(sc, offset) (((uint64_t)sc->bar[BAR0].base_addr) + (offset))
1517 #define REG_RD8(sc, offset) bnx2x_reg_read8(sc, (offset))
1518 #define REG_RD16(sc, offset) bnx2x_reg_read16(sc, (offset))
1519 #define REG_RD32(sc, offset) bnx2x_reg_read32(sc, (offset))
1521 #define REG_WR8(sc, offset, val) bnx2x_reg_write8(sc, (offset), val)
1522 #define REG_WR16(sc, offset, val) bnx2x_reg_write16(sc, (offset), val)
1523 #define REG_WR32(sc, offset, val) bnx2x_reg_write32(sc, (offset), val)
1525 #define REG_RD(sc, offset) REG_RD32(sc, offset)
1526 #define REG_WR(sc, offset, val) REG_WR32(sc, offset, val)
1528 #define BNX2X_SP(sc, var) (&(sc)->sp->var)
1529 #define BNX2X_SP_MAPPING(sc, var) \
1530 (sc->sp_dma.paddr + offsetof(struct bnx2x_slowpath, var))
1532 #define BNX2X_FP(sc, nr, var) ((sc)->fp[(nr)].var)
1533 #define BNX2X_SP_OBJ(sc, fp) ((sc)->sp_objs[(fp)->index])
1535 #define bnx2x_fp(sc, nr, var) ((sc)->fp[nr].var)
1537 #define REG_RD_DMAE(sc, offset, valp, len32) \
1539 (void)bnx2x_read_dmae(sc, offset, len32); \
1540 rte_memcpy(valp, BNX2X_SP(sc, wb_data[0]), (len32) * 4); \
1543 #define REG_WR_DMAE(sc, offset, valp, len32) \
1545 rte_memcpy(BNX2X_SP(sc, wb_data[0]), valp, (len32) * 4); \
1546 (void)bnx2x_write_dmae(sc, BNX2X_SP_MAPPING(sc, wb_data), offset, len32); \
1549 #define REG_WR_DMAE_LEN(sc, offset, valp, len32) \
1550 REG_WR_DMAE(sc, offset, valp, len32)
1552 #define REG_RD_DMAE_LEN(sc, offset, valp, len32) \
1553 REG_RD_DMAE(sc, offset, valp, len32)
1555 #define VIRT_WR_DMAE_LEN(sc, data, addr, len32, le32_swap) \
1557 /* if (le32_swap) { */ \
1558 /* PMD_PWARN_LOG(sc, "VIRT_WR_DMAE_LEN with le32_swap=1"); */ \
1560 rte_memcpy(GUNZIP_BUF(sc), data, len32 * 4); \
1561 ecore_write_big_buf_wb(sc, addr, len32); \
1564 #define BNX2X_DB_MIN_SHIFT 3 /* 8 bytes */
1565 #define BNX2X_DB_SHIFT 7 /* 128 bytes */
1566 #if (BNX2X_DB_SHIFT < BNX2X_DB_MIN_SHIFT)
1567 #error "Minimum DB doorbell stride is 8"
1569 #define DPM_TRIGGER_TYPE 0x40
1571 /* Doorbell macro */
1572 #define BNX2X_DB_WRITE(db_bar, val) rte_write32_relaxed((val), (db_bar))
1574 #define BNX2X_DB_READ(db_bar) rte_read32_relaxed(db_bar)
1576 #define DOORBELL_ADDR(sc, offset) \
1577 (volatile uint32_t *)(((char *)(sc)->bar[BAR1].base_addr + (offset)))
1579 #define DOORBELL(sc, cid, val) \
1581 BNX2X_DB_WRITE((DOORBELL_ADDR(sc, sc->doorbell_size * (cid) + DPM_TRIGGER_TYPE)), (val)); \
1583 BNX2X_DB_WRITE((DOORBELL_ADDR(sc, sc->doorbell_size * (cid))), (val)) \
1585 #define SHMEM_ADDR(sc, field) \
1586 (sc->devinfo.shmem_base + offsetof(struct shmem_region, field))
1587 #define SHMEM_RD(sc, field) REG_RD(sc, SHMEM_ADDR(sc, field))
1588 #define SHMEM_RD16(sc, field) REG_RD16(sc, SHMEM_ADDR(sc, field))
1589 #define SHMEM_WR(sc, field, val) REG_WR(sc, SHMEM_ADDR(sc, field), val)
1591 #define SHMEM2_ADDR(sc, field) \
1592 (sc->devinfo.shmem2_base + offsetof(struct shmem2_region, field))
1593 #define SHMEM2_HAS(sc, field) \
1594 (sc->devinfo.shmem2_base && (REG_RD(sc, SHMEM2_ADDR(sc, size)) > \
1595 offsetof(struct shmem2_region, field)))
1596 #define SHMEM2_RD(sc, field) REG_RD(sc, SHMEM2_ADDR(sc, field))
1597 #define SHMEM2_WR(sc, field, val) REG_WR(sc, SHMEM2_ADDR(sc, field), val)
1599 #define MFCFG_ADDR(sc, field) \
1600 (sc->devinfo.mf_cfg_base + offsetof(struct mf_cfg, field))
1601 #define MFCFG_RD(sc, field) REG_RD(sc, MFCFG_ADDR(sc, field))
1602 #define MFCFG_RD16(sc, field) REG_RD16(sc, MFCFG_ADDR(sc, field))
1603 #define MFCFG_WR(sc, field, val) REG_WR(sc, MFCFG_ADDR(sc, field), val)
1605 /* DMAE command defines */
1607 #define DMAE_TIMEOUT -1
1608 #define DMAE_PCI_ERROR -2 /* E2 and onward */
1609 #define DMAE_NOT_RDY -3
1610 #define DMAE_PCI_ERR_FLAG 0x80000000
1612 #define DMAE_SRC_PCI 0
1613 #define DMAE_SRC_GRC 1
1615 #define DMAE_DST_NONE 0
1616 #define DMAE_DST_PCI 1
1617 #define DMAE_DST_GRC 2
1619 #define DMAE_COMP_PCI 0
1620 #define DMAE_COMP_GRC 1
1622 #define DMAE_COMP_REGULAR 0
1623 #define DMAE_COM_SET_ERR 1
1625 #define DMAE_CMD_SRC_PCI (DMAE_SRC_PCI << DMAE_COMMAND_SRC_SHIFT)
1626 #define DMAE_CMD_SRC_GRC (DMAE_SRC_GRC << DMAE_COMMAND_SRC_SHIFT)
1627 #define DMAE_CMD_DST_PCI (DMAE_DST_PCI << DMAE_COMMAND_DST_SHIFT)
1628 #define DMAE_CMD_DST_GRC (DMAE_DST_GRC << DMAE_COMMAND_DST_SHIFT)
1630 #define DMAE_CMD_C_DST_PCI (DMAE_COMP_PCI << DMAE_COMMAND_C_DST_SHIFT)
1631 #define DMAE_CMD_C_DST_GRC (DMAE_COMP_GRC << DMAE_COMMAND_C_DST_SHIFT)
1633 #define DMAE_CMD_ENDIANITY_NO_SWAP (0 << DMAE_COMMAND_ENDIANITY_SHIFT)
1634 #define DMAE_CMD_ENDIANITY_B_SWAP (1 << DMAE_COMMAND_ENDIANITY_SHIFT)
1635 #define DMAE_CMD_ENDIANITY_DW_SWAP (2 << DMAE_COMMAND_ENDIANITY_SHIFT)
1636 #define DMAE_CMD_ENDIANITY_B_DW_SWAP (3 << DMAE_COMMAND_ENDIANITY_SHIFT)
1638 #define DMAE_CMD_PORT_0 0
1639 #define DMAE_CMD_PORT_1 DMAE_COMMAND_PORT
1641 #define DMAE_SRC_PF 0
1642 #define DMAE_SRC_VF 1
1644 #define DMAE_DST_PF 0
1645 #define DMAE_DST_VF 1
1647 #define DMAE_C_SRC 0
1648 #define DMAE_C_DST 1
1650 #define DMAE_LEN32_RD_MAX 0x80
1651 #define DMAE_LEN32_WR_MAX(sc) 0x2000
1653 #define DMAE_COMP_VAL 0x60d0d0ae /* E2 and beyond, upper bit indicates error */
1655 #define MAX_DMAE_C_PER_PORT 8
1656 #define INIT_DMAE_C(sc) ((SC_PORT(sc) * MAX_DMAE_C_PER_PORT) + SC_VN(sc))
1657 #define PMF_DMAE_C(sc) ((SC_PORT(sc) * MAX_DMAE_C_PER_PORT) + E1HVN_MAX)
1659 static const uint32_t dmae_reg_go_c[] = {
1660 DMAE_REG_GO_C0, DMAE_REG_GO_C1, DMAE_REG_GO_C2, DMAE_REG_GO_C3,
1661 DMAE_REG_GO_C4, DMAE_REG_GO_C5, DMAE_REG_GO_C6, DMAE_REG_GO_C7,
1662 DMAE_REG_GO_C8, DMAE_REG_GO_C9, DMAE_REG_GO_C10, DMAE_REG_GO_C11,
1663 DMAE_REG_GO_C12, DMAE_REG_GO_C13, DMAE_REG_GO_C14, DMAE_REG_GO_C15
1666 #define ATTN_NIG_FOR_FUNC (1L << 8)
1667 #define ATTN_SW_TIMER_4_FUNC (1L << 9)
1668 #define GPIO_2_FUNC (1L << 10)
1669 #define GPIO_3_FUNC (1L << 11)
1670 #define GPIO_4_FUNC (1L << 12)
1671 #define ATTN_GENERAL_ATTN_1 (1L << 13)
1672 #define ATTN_GENERAL_ATTN_2 (1L << 14)
1673 #define ATTN_GENERAL_ATTN_3 (1L << 15)
1674 #define ATTN_GENERAL_ATTN_4 (1L << 13)
1675 #define ATTN_GENERAL_ATTN_5 (1L << 14)
1676 #define ATTN_GENERAL_ATTN_6 (1L << 15)
1677 #define ATTN_HARD_WIRED_MASK 0xff00
1678 #define ATTENTION_ID 4
1680 #define AEU_IN_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR \
1681 AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR
1683 #define MAX_IGU_ATTN_ACK_TO 100
1685 #define STORM_ASSERT_ARRAY_SIZE 50
1687 #define BNX2X_PMF_LINK_ASSERT(sc) \
1688 GENERAL_ATTEN_OFFSET(LINK_SYNC_ATTENTION_BIT_FUNC_0 + SC_FUNC(sc))
1690 #define BNX2X_MC_ASSERT_BITS \
1691 (GENERAL_ATTEN_OFFSET(TSTORM_FATAL_ASSERT_ATTENTION_BIT) | \
1692 GENERAL_ATTEN_OFFSET(USTORM_FATAL_ASSERT_ATTENTION_BIT) | \
1693 GENERAL_ATTEN_OFFSET(CSTORM_FATAL_ASSERT_ATTENTION_BIT) | \
1694 GENERAL_ATTEN_OFFSET(XSTORM_FATAL_ASSERT_ATTENTION_BIT))
1696 #define BNX2X_MCP_ASSERT \
1697 GENERAL_ATTEN_OFFSET(MCP_FATAL_ASSERT_ATTENTION_BIT)
1699 #define BNX2X_GRC_TIMEOUT GENERAL_ATTEN_OFFSET(LATCHED_ATTN_TIMEOUT_GRC)
1700 #define BNX2X_GRC_RSV (GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCR) | \
1701 GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCT) | \
1702 GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCN) | \
1703 GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCU) | \
1704 GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCP) | \
1705 GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RSVD_GRC))
1707 #define MULTI_MASK 0x7f
1709 #define PFS_PER_PORT(sc) \
1710 ((CHIP_PORT_MODE(sc) == CHIP_4_PORT_MODE) ? 2 : 4)
1711 #define SC_MAX_VN_NUM(sc) PFS_PER_PORT(sc)
1713 #define FIRST_ABS_FUNC_IN_PORT(sc) \
1714 ((CHIP_PORT_MODE(sc) == CHIP_PORT_MODE_NONE) ? \
1715 PORT_ID(sc) : (PATH_ID(sc) + (2 * PORT_ID(sc))))
1717 #define FOREACH_ABS_FUNC_IN_PORT(sc, i) \
1718 for ((i) = FIRST_ABS_FUNC_IN_PORT(sc); \
1719 (i) < MAX_FUNC_NUM; \
1720 (i) += (MAX_FUNC_NUM / PFS_PER_PORT(sc)))
1722 #define BNX2X_SWCID_SHIFT 17
1723 #define BNX2X_SWCID_MASK ((0x1 << BNX2X_SWCID_SHIFT) - 1)
1725 #define SW_CID(x) (le32toh(x) & BNX2X_SWCID_MASK)
1726 #define CQE_CMD(x) (le32toh(x) >> COMMON_RAMROD_ETH_RX_CQE_CMD_ID_SHIFT)
1728 #define CQE_TYPE(cqe_fp_flags) ((cqe_fp_flags) & ETH_FAST_PATH_RX_CQE_TYPE)
1729 #define CQE_TYPE_START(cqe_type) ((cqe_type) == RX_ETH_CQE_TYPE_ETH_START_AGG)
1730 #define CQE_TYPE_STOP(cqe_type) ((cqe_type) == RX_ETH_CQE_TYPE_ETH_STOP_AGG)
1731 #define CQE_TYPE_SLOW(cqe_type) ((cqe_type) == RX_ETH_CQE_TYPE_ETH_RAMROD)
1732 #define CQE_TYPE_FAST(cqe_type) ((cqe_type) == RX_ETH_CQE_TYPE_ETH_FASTPATH)
1734 /* must be used on a CID before placing it on a HW ring */
1735 #define HW_CID(sc, x) \
1736 ((SC_PORT(sc) << 23) | (SC_VN(sc) << BNX2X_SWCID_SHIFT) | (x))
1739 #define SPEED_100 100
1740 #define SPEED_1000 1000
1741 #define SPEED_2500 2500
1742 #define SPEED_10000 10000
1745 #define PCI_PM_D3hot 2
1747 int bnx2x_test_bit(int nr, volatile unsigned long * addr);
1748 void bnx2x_set_bit(unsigned int nr, volatile unsigned long * addr);
1749 void bnx2x_clear_bit(int nr, volatile unsigned long * addr);
1750 int bnx2x_test_and_clear_bit(int nr, volatile unsigned long * addr);
1751 int bnx2x_cmpxchg(volatile int *addr, int old, int new);
1753 int bnx2x_dma_alloc(struct bnx2x_softc *sc, size_t size,
1754 struct bnx2x_dma *dma, const char *msg, uint32_t align);
1756 uint32_t bnx2x_dmae_opcode_add_comp(uint32_t opcode, uint8_t comp_type);
1757 uint32_t bnx2x_dmae_opcode_clr_src_reset(uint32_t opcode);
1758 uint32_t bnx2x_dmae_opcode(struct bnx2x_softc *sc, uint8_t src_type,
1759 uint8_t dst_type, uint8_t with_comp,
1761 void bnx2x_post_dmae(struct bnx2x_softc *sc, struct dmae_command *dmae, int idx);
1762 void bnx2x_read_dmae(struct bnx2x_softc *sc, uint32_t src_addr, uint32_t len32);
1763 void bnx2x_write_dmae(struct bnx2x_softc *sc, rte_iova_t dma_addr,
1764 uint32_t dst_addr, uint32_t len32);
1765 void bnx2x_set_ctx_validation(struct bnx2x_softc *sc, struct eth_context *cxt,
1767 void bnx2x_update_coalesce_sb_index(struct bnx2x_softc *sc, uint8_t fw_sb_id,
1768 uint8_t sb_index, uint8_t disable,
1771 int bnx2x_sp_post(struct bnx2x_softc *sc, int command, int cid,
1772 uint32_t data_hi, uint32_t data_lo, int cmd_type);
1774 void ecore_init_e1h_firmware(struct bnx2x_softc *sc);
1775 void ecore_init_e2_firmware(struct bnx2x_softc *sc);
1777 void ecore_storm_memset_struct(struct bnx2x_softc *sc, uint32_t addr,
1778 size_t size, uint32_t *data);
1780 #define CATC_TRIGGER(sc, data) REG_WR((sc), 0x2000, (data));
1781 #define CATC_TRIGGER_START(sc) CATC_TRIGGER((sc), 0xcafecafe)
1783 #define BNX2X_MAC_FMT "%pM"
1784 #define BNX2X_MAC_PRN_LIST(mac) (mac)
1790 static inline uint32_t
1791 reg_poll(struct bnx2x_softc *sc, uint32_t reg, uint32_t expected, int ms, int wait)
1795 val = REG_RD(sc, reg);
1796 if (val == expected) {
1807 bnx2x_update_fp_sb_idx(struct bnx2x_fastpath *fp)
1809 mb(); /* status block is written to by the chip */
1810 fp->fp_hc_idx = fp->sb_running_index[SM_RX_ID];
1814 bnx2x_igu_ack_sb_gen(struct bnx2x_softc *sc, uint8_t segment,
1815 uint16_t index, uint8_t op, uint8_t update, uint32_t igu_addr)
1817 struct igu_regular cmd_data = {0};
1819 cmd_data.sb_id_and_flags =
1820 ((index << IGU_REGULAR_SB_INDEX_SHIFT) |
1821 (segment << IGU_REGULAR_SEGMENT_ACCESS_SHIFT) |
1822 (update << IGU_REGULAR_BUPDATE_SHIFT) |
1823 (op << IGU_REGULAR_ENABLE_INT_SHIFT));
1825 REG_WR(sc, igu_addr, cmd_data.sb_id_and_flags);
1827 /* Make sure that ACK is written */
1832 bnx2x_hc_ack_sb(struct bnx2x_softc *sc, uint8_t sb_id, uint8_t storm,
1833 uint16_t index, uint8_t op, uint8_t update)
1835 uint32_t hc_addr = (HC_REG_COMMAND_REG + SC_PORT(sc) * 32 +
1836 COMMAND_REG_INT_ACK);
1837 union igu_ack_register igu_ack;
1839 igu_ack.sb.status_block_index = index;
1840 igu_ack.sb.sb_id_and_flags =
1841 ((sb_id << IGU_ACK_REGISTER_STATUS_BLOCK_ID_SHIFT) |
1842 (storm << IGU_ACK_REGISTER_STORM_ID_SHIFT) |
1843 (update << IGU_ACK_REGISTER_UPDATE_INDEX_SHIFT) |
1844 (op << IGU_ACK_REGISTER_INTERRUPT_MODE_SHIFT));
1846 REG_WR(sc, hc_addr, igu_ack.raw_data);
1848 /* Make sure that ACK is written */
1852 static inline uint32_t
1853 bnx2x_hc_ack_int(struct bnx2x_softc *sc)
1855 uint32_t hc_addr = (HC_REG_COMMAND_REG + SC_PORT(sc) * 32 +
1856 COMMAND_REG_SIMD_MASK);
1857 uint32_t result = REG_RD(sc, hc_addr);
1863 static inline uint32_t
1864 bnx2x_igu_ack_int(struct bnx2x_softc *sc)
1866 uint32_t igu_addr = (BAR_IGU_INTMEM + IGU_REG_SISR_MDPC_WMASK_LSB_UPPER * 8);
1867 uint32_t result = REG_RD(sc, igu_addr);
1869 /* PMD_PDEBUG_LOG(sc, DBG_INTR, "read 0x%08x from IGU addr 0x%x",
1870 result, igu_addr); */
1876 static inline uint32_t
1877 bnx2x_ack_int(struct bnx2x_softc *sc)
1880 if (sc->devinfo.int_block == INT_BLOCK_HC) {
1881 return bnx2x_hc_ack_int(sc);
1883 return bnx2x_igu_ack_int(sc);
1888 func_by_vn(struct bnx2x_softc *sc, int vn)
1890 return 2 * vn + SC_PORT(sc);
1894 * send notification to other functions.
1897 bnx2x_link_sync_notify(struct bnx2x_softc *sc)
1901 /* Set the attention towards other drivers on the same port */
1902 for (vn = VN_0; vn < SC_MAX_VN_NUM(sc); vn++) {
1903 if (vn == SC_VN(sc))
1906 func = func_by_vn(sc, vn);
1907 REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_0 +
1908 (LINK_SYNC_ATTENTION_BIT_FUNC_0 + func) * 4, 1);
1913 * Statistics ID are global per chip/path, while Client IDs for E1x
1916 static inline uint8_t
1917 bnx2x_stats_id(struct bnx2x_fastpath *fp)
1919 struct bnx2x_softc *sc = fp->sc;
1921 if (!CHIP_IS_E1x(sc)) {
1925 return fp->cl_id + SC_PORT(sc) * FP_SB_MAX_E1x;
1928 int bnx2x_init(struct bnx2x_softc *sc);
1929 void bnx2x_load_firmware(struct bnx2x_softc *sc);
1930 int bnx2x_attach(struct bnx2x_softc *sc);
1931 int bnx2x_nic_unload(struct bnx2x_softc *sc, uint32_t unload_mode, uint8_t keep_link);
1932 int bnx2x_alloc_hsi_mem(struct bnx2x_softc *sc);
1933 int bnx2x_alloc_ilt_mem(struct bnx2x_softc *sc);
1934 void bnx2x_free_ilt_mem(struct bnx2x_softc *sc);
1935 void bnx2x_dump_tx_chain(struct bnx2x_fastpath * fp, int bd_prod, int count);
1936 int bnx2x_tx_encap(struct bnx2x_tx_queue *txq, struct rte_mbuf *m0);
1937 uint8_t bnx2x_txeof(struct bnx2x_softc *sc, struct bnx2x_fastpath *fp);
1938 void bnx2x_print_adapter_info(struct bnx2x_softc *sc);
1939 int bnx2x_intr_legacy(struct bnx2x_softc *sc, int scan_fp);
1940 void bnx2x_link_status_update(struct bnx2x_softc *sc);
1941 int bnx2x_complete_sp(struct bnx2x_softc *sc);
1942 int bnx2x_set_storm_rx_mode(struct bnx2x_softc *sc);
1943 void bnx2x_periodic_callout(struct bnx2x_softc *sc);
1944 void bnx2x_periodic_stop(void *param);
1946 int bnx2x_vf_get_resources(struct bnx2x_softc *sc, uint8_t tx_count, uint8_t rx_count);
1947 void bnx2x_vf_close(struct bnx2x_softc *sc);
1948 int bnx2x_vf_init(struct bnx2x_softc *sc);
1949 void bnx2x_vf_unload(struct bnx2x_softc *sc);
1950 int bnx2x_vf_setup_queue(struct bnx2x_softc *sc, struct bnx2x_fastpath *fp,
1952 void bnx2x_free_hsi_mem(struct bnx2x_softc *sc);
1953 int bnx2x_vf_set_rx_mode(struct bnx2x_softc *sc);
1954 int bnx2x_check_bull(struct bnx2x_softc *sc);
1956 //#define BNX2X_PULSE
1958 #define BNX2X_PCI_CAP 1
1959 #define BNX2X_PCI_ECAP 2
1961 static inline struct bnx2x_pci_cap*
1962 pci_find_cap(struct bnx2x_softc *sc, uint8_t id, uint8_t type)
1964 struct bnx2x_pci_cap *cap = sc->pci_caps;
1967 if (cap->id == id && cap->type == type)
1976 bnx2x_set_rx_mode(struct bnx2x_softc *sc)
1978 if (sc->state == BNX2X_STATE_OPEN) {
1980 bnx2x_set_storm_rx_mode(sc);
1982 sc->rx_mode = BNX2X_RX_MODE_PROMISC;
1983 bnx2x_vf_set_rx_mode(sc);
1986 PMD_DRV_LOG(NOTICE, sc, "Card is not ready to change mode");
1990 static inline int pci_read(struct bnx2x_softc *sc, size_t addr,
1991 void *val, uint8_t size)
1993 if (rte_pci_read_config(sc->pci_dev, val, size, addr) <= 0) {
1994 PMD_DRV_LOG(ERR, sc, "Can't read from PCI config space");
2001 static inline int pci_write_word(struct bnx2x_softc *sc, size_t addr, off_t val)
2003 uint16_t val16 = val;
2005 if (rte_pci_write_config(sc->pci_dev, &val16,
2006 sizeof(val16), addr) <= 0) {
2007 PMD_DRV_LOG(ERR, sc, "Can't write to PCI config space");
2014 static inline int pci_write_long(struct bnx2x_softc *sc, size_t addr, off_t val)
2016 uint32_t val32 = val;
2017 if (rte_pci_write_config(sc->pci_dev, &val32,
2018 sizeof(val32), addr) <= 0) {
2019 PMD_DRV_LOG(ERR, sc, "Can't write to PCI config space");
2026 #endif /* __BNX2X_H__ */