2 * Copyright (c) 2007-2013 QLogic Corporation. All rights reserved.
4 * Eric Davis <edavis@broadcom.com>
5 * David Christensen <davidch@broadcom.com>
6 * Gary Zambrano <zambrano@broadcom.com>
8 * Copyright (c) 2013-2015 Brocade Communications Systems, Inc.
9 * Copyright (c) 2015 QLogic Corporation.
10 * All rights reserved.
13 * See LICENSE.bnx2x_pmd for copyright and licensing details.
18 #include "ecore_mfw_req.h"
19 #include "ecore_fw_defs.h"
20 #include "ecore_hsi.h"
21 #include "ecore_reg.h"
23 static elink_status_t elink_link_reset(struct elink_params *params,
24 struct elink_vars *vars,
25 uint8_t reset_ext_phy);
26 static elink_status_t elink_check_half_open_conn(struct elink_params *params,
27 struct elink_vars *vars,
29 static elink_status_t elink_sfp_module_detection(struct elink_phy *phy,
30 struct elink_params *params);
32 #define MDIO_REG_BANK_CL73_IEEEB0 0x0
33 #define MDIO_CL73_IEEEB0_CL73_AN_CONTROL 0x0
34 #define MDIO_CL73_IEEEB0_CL73_AN_CONTROL_RESTART_AN 0x0200
35 #define MDIO_CL73_IEEEB0_CL73_AN_CONTROL_AN_EN 0x1000
36 #define MDIO_CL73_IEEEB0_CL73_AN_CONTROL_MAIN_RST 0x8000
38 #define MDIO_REG_BANK_CL73_IEEEB1 0x10
39 #define MDIO_CL73_IEEEB1_AN_ADV1 0x00
40 #define MDIO_CL73_IEEEB1_AN_ADV1_PAUSE 0x0400
41 #define MDIO_CL73_IEEEB1_AN_ADV1_ASYMMETRIC 0x0800
42 #define MDIO_CL73_IEEEB1_AN_ADV1_PAUSE_BOTH 0x0C00
43 #define MDIO_CL73_IEEEB1_AN_ADV1_PAUSE_MASK 0x0C00
44 #define MDIO_CL73_IEEEB1_AN_ADV2 0x01
45 #define MDIO_CL73_IEEEB1_AN_ADV2_ADVR_1000M 0x0000
46 #define MDIO_CL73_IEEEB1_AN_ADV2_ADVR_1000M_KX 0x0020
47 #define MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KX4 0x0040
48 #define MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KR 0x0080
49 #define MDIO_CL73_IEEEB1_AN_LP_ADV1 0x03
50 #define MDIO_CL73_IEEEB1_AN_LP_ADV1_PAUSE 0x0400
51 #define MDIO_CL73_IEEEB1_AN_LP_ADV1_ASYMMETRIC 0x0800
52 #define MDIO_CL73_IEEEB1_AN_LP_ADV1_PAUSE_BOTH 0x0C00
53 #define MDIO_CL73_IEEEB1_AN_LP_ADV1_PAUSE_MASK 0x0C00
54 #define MDIO_CL73_IEEEB1_AN_LP_ADV2 0x04
56 #define MDIO_REG_BANK_RX0 0x80b0
57 #define MDIO_RX0_RX_STATUS 0x10
58 #define MDIO_RX0_RX_STATUS_SIGDET 0x8000
59 #define MDIO_RX0_RX_STATUS_RX_SEQ_DONE 0x1000
60 #define MDIO_RX0_RX_EQ_BOOST 0x1c
61 #define MDIO_RX0_RX_EQ_BOOST_EQUALIZER_CTRL_MASK 0x7
62 #define MDIO_RX0_RX_EQ_BOOST_OFFSET_CTRL 0x10
64 #define MDIO_REG_BANK_RX1 0x80c0
65 #define MDIO_RX1_RX_EQ_BOOST 0x1c
66 #define MDIO_RX1_RX_EQ_BOOST_EQUALIZER_CTRL_MASK 0x7
67 #define MDIO_RX1_RX_EQ_BOOST_OFFSET_CTRL 0x10
69 #define MDIO_REG_BANK_RX2 0x80d0
70 #define MDIO_RX2_RX_EQ_BOOST 0x1c
71 #define MDIO_RX2_RX_EQ_BOOST_EQUALIZER_CTRL_MASK 0x7
72 #define MDIO_RX2_RX_EQ_BOOST_OFFSET_CTRL 0x10
74 #define MDIO_REG_BANK_RX3 0x80e0
75 #define MDIO_RX3_RX_EQ_BOOST 0x1c
76 #define MDIO_RX3_RX_EQ_BOOST_EQUALIZER_CTRL_MASK 0x7
77 #define MDIO_RX3_RX_EQ_BOOST_OFFSET_CTRL 0x10
79 #define MDIO_REG_BANK_RX_ALL 0x80f0
80 #define MDIO_RX_ALL_RX_EQ_BOOST 0x1c
81 #define MDIO_RX_ALL_RX_EQ_BOOST_EQUALIZER_CTRL_MASK 0x7
82 #define MDIO_RX_ALL_RX_EQ_BOOST_OFFSET_CTRL 0x10
84 #define MDIO_REG_BANK_TX0 0x8060
85 #define MDIO_TX0_TX_DRIVER 0x17
86 #define MDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK 0xf000
87 #define MDIO_TX0_TX_DRIVER_PREEMPHASIS_SHIFT 12
88 #define MDIO_TX0_TX_DRIVER_IDRIVER_MASK 0x0f00
89 #define MDIO_TX0_TX_DRIVER_IDRIVER_SHIFT 8
90 #define MDIO_TX0_TX_DRIVER_IPREDRIVER_MASK 0x00f0
91 #define MDIO_TX0_TX_DRIVER_IPREDRIVER_SHIFT 4
92 #define MDIO_TX0_TX_DRIVER_IFULLSPD_MASK 0x000e
93 #define MDIO_TX0_TX_DRIVER_IFULLSPD_SHIFT 1
94 #define MDIO_TX0_TX_DRIVER_ICBUF1T 1
96 #define MDIO_REG_BANK_TX1 0x8070
97 #define MDIO_TX1_TX_DRIVER 0x17
98 #define MDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK 0xf000
99 #define MDIO_TX0_TX_DRIVER_PREEMPHASIS_SHIFT 12
100 #define MDIO_TX0_TX_DRIVER_IDRIVER_MASK 0x0f00
101 #define MDIO_TX0_TX_DRIVER_IDRIVER_SHIFT 8
102 #define MDIO_TX0_TX_DRIVER_IPREDRIVER_MASK 0x00f0
103 #define MDIO_TX0_TX_DRIVER_IPREDRIVER_SHIFT 4
104 #define MDIO_TX0_TX_DRIVER_IFULLSPD_MASK 0x000e
105 #define MDIO_TX0_TX_DRIVER_IFULLSPD_SHIFT 1
106 #define MDIO_TX0_TX_DRIVER_ICBUF1T 1
108 #define MDIO_REG_BANK_TX2 0x8080
109 #define MDIO_TX2_TX_DRIVER 0x17
110 #define MDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK 0xf000
111 #define MDIO_TX0_TX_DRIVER_PREEMPHASIS_SHIFT 12
112 #define MDIO_TX0_TX_DRIVER_IDRIVER_MASK 0x0f00
113 #define MDIO_TX0_TX_DRIVER_IDRIVER_SHIFT 8
114 #define MDIO_TX0_TX_DRIVER_IPREDRIVER_MASK 0x00f0
115 #define MDIO_TX0_TX_DRIVER_IPREDRIVER_SHIFT 4
116 #define MDIO_TX0_TX_DRIVER_IFULLSPD_MASK 0x000e
117 #define MDIO_TX0_TX_DRIVER_IFULLSPD_SHIFT 1
118 #define MDIO_TX0_TX_DRIVER_ICBUF1T 1
120 #define MDIO_REG_BANK_TX3 0x8090
121 #define MDIO_TX3_TX_DRIVER 0x17
122 #define MDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK 0xf000
123 #define MDIO_TX0_TX_DRIVER_PREEMPHASIS_SHIFT 12
124 #define MDIO_TX0_TX_DRIVER_IDRIVER_MASK 0x0f00
125 #define MDIO_TX0_TX_DRIVER_IDRIVER_SHIFT 8
126 #define MDIO_TX0_TX_DRIVER_IPREDRIVER_MASK 0x00f0
127 #define MDIO_TX0_TX_DRIVER_IPREDRIVER_SHIFT 4
128 #define MDIO_TX0_TX_DRIVER_IFULLSPD_MASK 0x000e
129 #define MDIO_TX0_TX_DRIVER_IFULLSPD_SHIFT 1
130 #define MDIO_TX0_TX_DRIVER_ICBUF1T 1
132 #define MDIO_REG_BANK_XGXS_BLOCK0 0x8000
133 #define MDIO_BLOCK0_XGXS_CONTROL 0x10
135 #define MDIO_REG_BANK_XGXS_BLOCK1 0x8010
136 #define MDIO_BLOCK1_LANE_CTRL0 0x15
137 #define MDIO_BLOCK1_LANE_CTRL1 0x16
138 #define MDIO_BLOCK1_LANE_CTRL2 0x17
139 #define MDIO_BLOCK1_LANE_PRBS 0x19
141 #define MDIO_REG_BANK_XGXS_BLOCK2 0x8100
142 #define MDIO_XGXS_BLOCK2_RX_LN_SWAP 0x10
143 #define MDIO_XGXS_BLOCK2_RX_LN_SWAP_ENABLE 0x8000
144 #define MDIO_XGXS_BLOCK2_RX_LN_SWAP_FORCE_ENABLE 0x4000
145 #define MDIO_XGXS_BLOCK2_TX_LN_SWAP 0x11
146 #define MDIO_XGXS_BLOCK2_TX_LN_SWAP_ENABLE 0x8000
147 #define MDIO_XGXS_BLOCK2_UNICORE_MODE_10G 0x14
148 #define MDIO_XGXS_BLOCK2_UNICORE_MODE_10G_CX4_XGXS 0x0001
149 #define MDIO_XGXS_BLOCK2_UNICORE_MODE_10G_HIGIG_XGXS 0x0010
150 #define MDIO_XGXS_BLOCK2_TEST_MODE_LANE 0x15
152 #define MDIO_REG_BANK_GP_STATUS 0x8120
153 #define MDIO_GP_STATUS_TOP_AN_STATUS1 0x1B
154 #define MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_AUTONEG_COMPLETE 0x0001
155 #define MDIO_GP_STATUS_TOP_AN_STATUS1_CL37_AUTONEG_COMPLETE 0x0002
156 #define MDIO_GP_STATUS_TOP_AN_STATUS1_LINK_STATUS 0x0004
157 #define MDIO_GP_STATUS_TOP_AN_STATUS1_DUPLEX_STATUS 0x0008
158 #define MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_MR_LP_NP_AN_ABLE 0x0010
159 #define MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_LP_NP_BAM_ABLE 0x0020
160 #define MDIO_GP_STATUS_TOP_AN_STATUS1_PAUSE_RSOLUTION_TXSIDE 0x0040
161 #define MDIO_GP_STATUS_TOP_AN_STATUS1_PAUSE_RSOLUTION_RXSIDE 0x0080
162 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_MASK 0x3f00
163 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10M 0x0000
164 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_100M 0x0100
165 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_1G 0x0200
166 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_2_5G 0x0300
167 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_5G 0x0400
168 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_6G 0x0500
169 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_HIG 0x0600
170 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_CX4 0x0700
171 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_12G_HIG 0x0800
172 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_12_5G 0x0900
173 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_13G 0x0A00
174 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_15G 0x0B00
175 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_16G 0x0C00
176 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_1G_KX 0x0D00
177 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_KX4 0x0E00
178 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_KR 0x0F00
179 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_XFI 0x1B00
180 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_20G_DXGXS 0x1E00
181 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_SFI 0x1F00
182 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_20G_KR2 0x3900
184 #define MDIO_REG_BANK_10G_PARALLEL_DETECT 0x8130
185 #define MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_STATUS 0x10
186 #define MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_STATUS_PD_LINK 0x8000
187 #define MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL 0x11
188 #define MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL_PARDET10G_EN 0x1
189 #define MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_LINK 0x13
190 #define MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_LINK_CNT (0xb71<<1)
192 #define MDIO_REG_BANK_SERDES_DIGITAL 0x8300
193 #define MDIO_SERDES_DIGITAL_A_1000X_CONTROL1 0x10
194 #define MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_FIBER_MODE 0x0001
195 #define MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_TBI_IF 0x0002
196 #define MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_SIGNAL_DETECT_EN 0x0004
197 #define MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_INVERT_SIGNAL_DETECT 0x0008
198 #define MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_AUTODET 0x0010
199 #define MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_MSTR_MODE 0x0020
200 #define MDIO_SERDES_DIGITAL_A_1000X_CONTROL2 0x11
201 #define MDIO_SERDES_DIGITAL_A_1000X_CONTROL2_PRL_DT_EN 0x0001
202 #define MDIO_SERDES_DIGITAL_A_1000X_CONTROL2_AN_FST_TMR 0x0040
203 #define MDIO_SERDES_DIGITAL_A_1000X_STATUS1 0x14
204 #define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_SGMII 0x0001
205 #define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_LINK 0x0002
206 #define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_DUPLEX 0x0004
207 #define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_SPEED_MASK 0x0018
208 #define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_SPEED_SHIFT 3
209 #define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_SPEED_2_5G 0x0018
210 #define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_SPEED_1G 0x0010
211 #define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_SPEED_100M 0x0008
212 #define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_SPEED_10M 0x0000
213 #define MDIO_SERDES_DIGITAL_A_1000X_STATUS2 0x15
214 #define MDIO_SERDES_DIGITAL_A_1000X_STATUS2_AN_DISABLED 0x0002
215 #define MDIO_SERDES_DIGITAL_MISC1 0x18
216 #define MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_MASK 0xE000
217 #define MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_25M 0x0000
218 #define MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_100M 0x2000
219 #define MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_125M 0x4000
220 #define MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_156_25M 0x6000
221 #define MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_187_5M 0x8000
222 #define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_SEL 0x0010
223 #define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_MASK 0x000f
224 #define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_2_5G 0x0000
225 #define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_5G 0x0001
226 #define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_6G 0x0002
227 #define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_10G_HIG 0x0003
228 #define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_10G_CX4 0x0004
229 #define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_12G 0x0005
230 #define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_12_5G 0x0006
231 #define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_13G 0x0007
232 #define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_15G 0x0008
233 #define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_16G 0x0009
235 #define MDIO_REG_BANK_OVER_1G 0x8320
236 #define MDIO_OVER_1G_DIGCTL_3_4 0x14
237 #define MDIO_OVER_1G_DIGCTL_3_4_MP_ID_MASK 0xffe0
238 #define MDIO_OVER_1G_DIGCTL_3_4_MP_ID_SHIFT 5
239 #define MDIO_OVER_1G_UP1 0x19
240 #define MDIO_OVER_1G_UP1_2_5G 0x0001
241 #define MDIO_OVER_1G_UP1_5G 0x0002
242 #define MDIO_OVER_1G_UP1_6G 0x0004
243 #define MDIO_OVER_1G_UP1_10G 0x0010
244 #define MDIO_OVER_1G_UP1_10GH 0x0008
245 #define MDIO_OVER_1G_UP1_12G 0x0020
246 #define MDIO_OVER_1G_UP1_12_5G 0x0040
247 #define MDIO_OVER_1G_UP1_13G 0x0080
248 #define MDIO_OVER_1G_UP1_15G 0x0100
249 #define MDIO_OVER_1G_UP1_16G 0x0200
250 #define MDIO_OVER_1G_UP2 0x1A
251 #define MDIO_OVER_1G_UP2_IPREDRIVER_MASK 0x0007
252 #define MDIO_OVER_1G_UP2_IDRIVER_MASK 0x0038
253 #define MDIO_OVER_1G_UP2_PREEMPHASIS_MASK 0x03C0
254 #define MDIO_OVER_1G_UP3 0x1B
255 #define MDIO_OVER_1G_UP3_HIGIG2 0x0001
256 #define MDIO_OVER_1G_LP_UP1 0x1C
257 #define MDIO_OVER_1G_LP_UP2 0x1D
258 #define MDIO_OVER_1G_LP_UP2_MR_ADV_OVER_1G_MASK 0x03ff
259 #define MDIO_OVER_1G_LP_UP2_PREEMPHASIS_MASK 0x0780
260 #define MDIO_OVER_1G_LP_UP2_PREEMPHASIS_SHIFT 7
261 #define MDIO_OVER_1G_LP_UP3 0x1E
263 #define MDIO_REG_BANK_REMOTE_PHY 0x8330
264 #define MDIO_REMOTE_PHY_MISC_RX_STATUS 0x10
265 #define MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_OVER1G_MSG 0x0010
266 #define MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_BRCM_OUI_MSG 0x0600
268 #define MDIO_REG_BANK_BAM_NEXT_PAGE 0x8350
269 #define MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL 0x10
270 #define MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_BAM_MODE 0x0001
271 #define MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_TETON_AN 0x0002
273 #define MDIO_REG_BANK_CL73_USERB0 0x8370
274 #define MDIO_CL73_USERB0_CL73_UCTRL 0x10
275 #define MDIO_CL73_USERB0_CL73_UCTRL_USTAT1_MUXSEL 0x0002
276 #define MDIO_CL73_USERB0_CL73_USTAT1 0x11
277 #define MDIO_CL73_USERB0_CL73_USTAT1_LINK_STATUS_CHECK 0x0100
278 #define MDIO_CL73_USERB0_CL73_USTAT1_AN_GOOD_CHECK_BAM37 0x0400
279 #define MDIO_CL73_USERB0_CL73_BAM_CTRL1 0x12
280 #define MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_EN 0x8000
281 #define MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_STATION_MNGR_EN 0x4000
282 #define MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_NP_AFTER_BP_EN 0x2000
283 #define MDIO_CL73_USERB0_CL73_BAM_CTRL3 0x14
284 #define MDIO_CL73_USERB0_CL73_BAM_CTRL3_USE_CL73_HCD_MR 0x0001
286 #define MDIO_REG_BANK_AER_BLOCK 0xFFD0
287 #define MDIO_AER_BLOCK_AER_REG 0x1E
289 #define MDIO_REG_BANK_COMBO_IEEE0 0xFFE0
290 #define MDIO_COMBO_IEEE0_MII_CONTROL 0x10
291 #define MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_MASK 0x2040
292 #define MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_10 0x0000
293 #define MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_100 0x2000
294 #define MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_1000 0x0040
295 #define MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX 0x0100
296 #define MDIO_COMBO_IEEO_MII_CONTROL_RESTART_AN 0x0200
297 #define MDIO_COMBO_IEEO_MII_CONTROL_AN_EN 0x1000
298 #define MDIO_COMBO_IEEO_MII_CONTROL_LOOPBACK 0x4000
299 #define MDIO_COMBO_IEEO_MII_CONTROL_RESET 0x8000
300 #define MDIO_COMBO_IEEE0_MII_STATUS 0x11
301 #define MDIO_COMBO_IEEE0_MII_STATUS_LINK_PASS 0x0004
302 #define MDIO_COMBO_IEEE0_MII_STATUS_AUTONEG_COMPLETE 0x0020
303 #define MDIO_COMBO_IEEE0_AUTO_NEG_ADV 0x14
304 #define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_FULL_DUPLEX 0x0020
305 #define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_HALF_DUPLEX 0x0040
306 #define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK 0x0180
307 #define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_NONE 0x0000
308 #define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_SYMMETRIC 0x0080
309 #define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC 0x0100
310 #define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH 0x0180
311 #define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_NEXT_PAGE 0x8000
312 #define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1 0x15
313 #define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_NEXT_PAGE 0x8000
314 #define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_ACK 0x4000
315 #define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_PAUSE_MASK 0x0180
316 #define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_PAUSE_NONE 0x0000
317 #define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_PAUSE_BOTH 0x0180
318 #define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_HALF_DUP_CAP 0x0040
319 #define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_FULL_DUP_CAP 0x0020
320 /*WhenthelinkpartnerisinSGMIImode(bit0=1),then
321 bit15=link,bit12=duplex,bits11:10=speed,bit14=acknowledge.
322 Theotherbitsarereservedandshouldbezero*/
323 #define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_SGMII_MODE 0x0001
325 #define MDIO_PMA_DEVAD 0x1
327 #define MDIO_PMA_REG_CTRL 0x0
328 #define MDIO_PMA_REG_STATUS 0x1
329 #define MDIO_PMA_REG_10G_CTRL2 0x7
330 #define MDIO_PMA_REG_TX_DISABLE 0x0009
331 #define MDIO_PMA_REG_RX_SD 0xa
333 #define MDIO_PMA_REG_BNX2X_CTRL 0x0096
334 #define MDIO_PMA_REG_FEC_CTRL 0x00ab
335 #define MDIO_PMA_LASI_RXCTRL 0x9000
336 #define MDIO_PMA_LASI_TXCTRL 0x9001
337 #define MDIO_PMA_LASI_CTRL 0x9002
338 #define MDIO_PMA_LASI_RXSTAT 0x9003
339 #define MDIO_PMA_LASI_TXSTAT 0x9004
340 #define MDIO_PMA_LASI_STAT 0x9005
341 #define MDIO_PMA_REG_PHY_IDENTIFIER 0xc800
342 #define MDIO_PMA_REG_DIGITAL_CTRL 0xc808
343 #define MDIO_PMA_REG_DIGITAL_STATUS 0xc809
344 #define MDIO_PMA_REG_TX_POWER_DOWN 0xca02
345 #define MDIO_PMA_REG_CMU_PLL_BYPASS 0xca09
346 #define MDIO_PMA_REG_MISC_CTRL 0xca0a
347 #define MDIO_PMA_REG_GEN_CTRL 0xca10
348 #define MDIO_PMA_REG_GEN_CTRL_ROM_RESET_INTERNAL_MP 0x0188
349 #define MDIO_PMA_REG_GEN_CTRL_ROM_MICRO_RESET 0x018a
350 #define MDIO_PMA_REG_M8051_MSGIN_REG 0xca12
351 #define MDIO_PMA_REG_M8051_MSGOUT_REG 0xca13
352 #define MDIO_PMA_REG_ROM_VER1 0xca19
353 #define MDIO_PMA_REG_ROM_VER2 0xca1a
354 #define MDIO_PMA_REG_EDC_FFE_MAIN 0xca1b
355 #define MDIO_PMA_REG_PLL_BANDWIDTH 0xca1d
356 #define MDIO_PMA_REG_PLL_CTRL 0xca1e
357 #define MDIO_PMA_REG_MISC_CTRL0 0xca23
358 #define MDIO_PMA_REG_LRM_MODE 0xca3f
359 #define MDIO_PMA_REG_CDR_BANDWIDTH 0xca46
360 #define MDIO_PMA_REG_MISC_CTRL1 0xca85
362 #define MDIO_PMA_REG_SFP_TWO_WIRE_CTRL 0x8000
363 #define MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK 0x000c
364 #define MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_IDLE 0x0000
365 #define MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_COMPLETE 0x0004
366 #define MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_IN_PROGRESS 0x0008
367 #define MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_FAILED 0x000c
368 #define MDIO_PMA_REG_SFP_TWO_WIRE_BYTE_CNT 0x8002
369 #define MDIO_PMA_REG_SFP_TWO_WIRE_MEM_ADDR 0x8003
370 #define MDIO_PMA_REG_8726_TWO_WIRE_DATA_BUF 0xc820
371 #define MDIO_PMA_REG_8726_TWO_WIRE_DATA_MASK 0xff
372 #define MDIO_PMA_REG_8726_TX_CTRL1 0xca01
373 #define MDIO_PMA_REG_8726_TX_CTRL2 0xca05
375 #define MDIO_PMA_REG_8727_TWO_WIRE_SLAVE_ADDR 0x8005
376 #define MDIO_PMA_REG_8727_TWO_WIRE_DATA_BUF 0x8007
377 #define MDIO_PMA_REG_8727_TWO_WIRE_DATA_MASK 0xff
378 #define MDIO_PMA_REG_8727_MISC_CTRL 0x8309
379 #define MDIO_PMA_REG_8727_TX_CTRL1 0xca02
380 #define MDIO_PMA_REG_8727_TX_CTRL2 0xca05
381 #define MDIO_PMA_REG_8727_PCS_OPT_CTRL 0xc808
382 #define MDIO_PMA_REG_8727_GPIO_CTRL 0xc80e
383 #define MDIO_PMA_REG_8727_PCS_GP 0xc842
384 #define MDIO_PMA_REG_8727_OPT_CFG_REG 0xc8e4
386 #define MDIO_AN_REG_8727_MISC_CTRL 0x8309
387 #define MDIO_PMA_REG_8073_CHIP_REV 0xc801
388 #define MDIO_PMA_REG_8073_SPEED_LINK_STATUS 0xc820
389 #define MDIO_PMA_REG_8073_XAUI_WA 0xc841
390 #define MDIO_PMA_REG_8073_OPT_DIGITAL_CTRL 0xcd08
392 #define MDIO_PMA_REG_7101_RESET 0xc000
393 #define MDIO_PMA_REG_7107_LED_CNTL 0xc007
394 #define MDIO_PMA_REG_7107_LINK_LED_CNTL 0xc009
395 #define MDIO_PMA_REG_7101_VER1 0xc026
396 #define MDIO_PMA_REG_7101_VER2 0xc027
398 #define MDIO_PMA_REG_8481_PMD_SIGNAL 0xa811
399 #define MDIO_PMA_REG_8481_LED1_MASK 0xa82c
400 #define MDIO_PMA_REG_8481_LED2_MASK 0xa82f
401 #define MDIO_PMA_REG_8481_LED3_MASK 0xa832
402 #define MDIO_PMA_REG_8481_LED3_BLINK 0xa834
403 #define MDIO_PMA_REG_8481_LED5_MASK 0xa838
404 #define MDIO_PMA_REG_8481_SIGNAL_MASK 0xa835
405 #define MDIO_PMA_REG_8481_LINK_SIGNAL 0xa83b
406 #define MDIO_PMA_REG_8481_LINK_SIGNAL_LED4_ENABLE_MASK 0x800
407 #define MDIO_PMA_REG_8481_LINK_SIGNAL_LED4_ENABLE_SHIFT 11
409 #define MDIO_WIS_DEVAD 0x2
411 #define MDIO_WIS_REG_LASI_CNTL 0x9002
412 #define MDIO_WIS_REG_LASI_STATUS 0x9005
414 #define MDIO_PCS_DEVAD 0x3
415 #define MDIO_PCS_REG_STATUS 0x0020
416 #define MDIO_PCS_REG_LASI_STATUS 0x9005
417 #define MDIO_PCS_REG_7101_DSP_ACCESS 0xD000
418 #define MDIO_PCS_REG_7101_SPI_MUX 0xD008
419 #define MDIO_PCS_REG_7101_SPI_CTRL_ADDR 0xE12A
420 #define MDIO_PCS_REG_7101_SPI_RESET_BIT (5)
421 #define MDIO_PCS_REG_7101_SPI_FIFO_ADDR 0xE02A
422 #define MDIO_PCS_REG_7101_SPI_FIFO_ADDR_WRITE_ENABLE_CMD (6)
423 #define MDIO_PCS_REG_7101_SPI_FIFO_ADDR_BULK_ERASE_CMD (0xC7)
424 #define MDIO_PCS_REG_7101_SPI_FIFO_ADDR_PAGE_PROGRAM_CMD (2)
425 #define MDIO_PCS_REG_7101_SPI_BYTES_TO_TRANSFER_ADDR 0xE028
427 #define MDIO_XS_DEVAD 0x4
428 #define MDIO_XS_REG_STATUS 0x0001
429 #define MDIO_XS_PLL_SEQUENCER 0x8000
430 #define MDIO_XS_SFX7101_XGXS_TEST1 0xc00a
432 #define MDIO_XS_8706_REG_BANK_RX0 0x80bc
433 #define MDIO_XS_8706_REG_BANK_RX1 0x80cc
434 #define MDIO_XS_8706_REG_BANK_RX2 0x80dc
435 #define MDIO_XS_8706_REG_BANK_RX3 0x80ec
436 #define MDIO_XS_8706_REG_BANK_RXA 0x80fc
438 #define MDIO_XS_REG_8073_RX_CTRL_PCIE 0x80FA
440 #define MDIO_AN_DEVAD 0x7
442 #define MDIO_AN_REG_CTRL 0x0000
443 #define MDIO_AN_REG_STATUS 0x0001
444 #define MDIO_AN_REG_STATUS_AN_COMPLETE 0x0020
445 #define MDIO_AN_REG_ADV_PAUSE 0x0010
446 #define MDIO_AN_REG_ADV_PAUSE_PAUSE 0x0400
447 #define MDIO_AN_REG_ADV_PAUSE_ASYMMETRIC 0x0800
448 #define MDIO_AN_REG_ADV_PAUSE_BOTH 0x0C00
449 #define MDIO_AN_REG_ADV_PAUSE_MASK 0x0C00
450 #define MDIO_AN_REG_ADV 0x0011
451 #define MDIO_AN_REG_ADV2 0x0012
452 #define MDIO_AN_REG_LP_AUTO_NEG 0x0013
453 #define MDIO_AN_REG_LP_AUTO_NEG2 0x0014
454 #define MDIO_AN_REG_MASTER_STATUS 0x0021
455 #define MDIO_AN_REG_EEE_ADV 0x003c
456 #define MDIO_AN_REG_LP_EEE_ADV 0x003d
458 #define MDIO_AN_REG_LINK_STATUS 0x8304
459 #define MDIO_AN_REG_CL37_CL73 0x8370
460 #define MDIO_AN_REG_CL37_AN 0xffe0
461 #define MDIO_AN_REG_CL37_FC_LD 0xffe4
462 #define MDIO_AN_REG_CL37_FC_LP 0xffe5
463 #define MDIO_AN_REG_1000T_STATUS 0xffea
465 #define MDIO_AN_REG_8073_2_5G 0x8329
466 #define MDIO_AN_REG_8073_BAM 0x8350
468 #define MDIO_AN_REG_8481_10GBASE_T_AN_CTRL 0x0020
469 #define MDIO_AN_REG_8481_LEGACY_MII_CTRL 0xffe0
470 #define MDIO_AN_REG_8481_MII_CTRL_FORCE_1G 0x40
471 #define MDIO_AN_REG_8481_LEGACY_MII_STATUS 0xffe1
472 #define MDIO_AN_REG_8481_LEGACY_AN_ADV 0xffe4
473 #define MDIO_AN_REG_8481_LEGACY_AN_EXPANSION 0xffe6
474 #define MDIO_AN_REG_8481_1000T_CTRL 0xffe9
475 #define MDIO_AN_REG_8481_1G_100T_EXT_CTRL 0xfff0
476 #define MIDO_AN_REG_8481_EXT_CTRL_FORCE_LEDS_OFF 0x0008
477 #define MDIO_AN_REG_8481_EXPANSION_REG_RD_RW 0xfff5
478 #define MDIO_AN_REG_8481_EXPANSION_REG_ACCESS 0xfff7
479 #define MDIO_AN_REG_8481_AUX_CTRL 0xfff8
480 #define MDIO_AN_REG_8481_LEGACY_SHADOW 0xfffc
482 /* BNX2X84823 only */
483 #define MDIO_CTL_DEVAD 0x1e
484 #define MDIO_CTL_REG_84823_MEDIA 0x401a
485 #define MDIO_CTL_REG_84823_MEDIA_MAC_MASK 0x0018
486 /* These pins configure the BNX2X84823 interface to MAC after reset. */
487 #define MDIO_CTL_REG_84823_CTRL_MAC_XFI 0x0008
488 #define MDIO_CTL_REG_84823_MEDIA_MAC_XAUI_M 0x0010
489 /* These pins configure the BNX2X84823 interface to Line after reset. */
490 #define MDIO_CTL_REG_84823_MEDIA_LINE_MASK 0x0060
491 #define MDIO_CTL_REG_84823_MEDIA_LINE_XAUI_L 0x0020
492 #define MDIO_CTL_REG_84823_MEDIA_LINE_XFI 0x0040
493 /* When this pin is active high during reset, 10GBASE-T core is power
494 * down, When it is active low the 10GBASE-T is power up
496 #define MDIO_CTL_REG_84823_MEDIA_COPPER_CORE_DOWN 0x0080
497 #define MDIO_CTL_REG_84823_MEDIA_PRIORITY_MASK 0x0100
498 #define MDIO_CTL_REG_84823_MEDIA_PRIORITY_COPPER 0x0000
499 #define MDIO_CTL_REG_84823_MEDIA_PRIORITY_FIBER 0x0100
500 #define MDIO_CTL_REG_84823_MEDIA_FIBER_1G 0x1000
501 #define MDIO_CTL_REG_84823_USER_CTRL_REG 0x4005
502 #define MDIO_CTL_REG_84823_USER_CTRL_CMS 0x0080
503 #define MDIO_PMA_REG_84823_CTL_SLOW_CLK_CNT_HIGH 0xa82b
504 #define MDIO_PMA_REG_84823_BLINK_RATE_VAL_15P9HZ 0x2f
505 #define MDIO_PMA_REG_84823_CTL_LED_CTL_1 0xa8e3
506 #define MDIO_PMA_REG_84833_CTL_LED_CTL_1 0xa8ec
507 #define MDIO_PMA_REG_84823_LED3_STRETCH_EN 0x0080
509 /* BNX2X84833 only */
510 #define MDIO_84833_TOP_CFG_FW_REV 0x400f
511 #define MDIO_84833_TOP_CFG_FW_EEE 0x10b1
512 #define MDIO_84833_TOP_CFG_FW_NO_EEE 0x1f81
513 #define MDIO_84833_TOP_CFG_XGPHY_STRAP1 0x401a
514 #define MDIO_84833_SUPER_ISOLATE 0x8000
515 /* These are mailbox register set used by 84833. */
516 #define MDIO_84833_TOP_CFG_SCRATCH_REG0 0x4005
517 #define MDIO_84833_TOP_CFG_SCRATCH_REG1 0x4006
518 #define MDIO_84833_TOP_CFG_SCRATCH_REG2 0x4007
519 #define MDIO_84833_TOP_CFG_SCRATCH_REG3 0x4008
520 #define MDIO_84833_TOP_CFG_SCRATCH_REG4 0x4009
521 #define MDIO_84833_TOP_CFG_SCRATCH_REG26 0x4037
522 #define MDIO_84833_TOP_CFG_SCRATCH_REG27 0x4038
523 #define MDIO_84833_TOP_CFG_SCRATCH_REG28 0x4039
524 #define MDIO_84833_TOP_CFG_SCRATCH_REG29 0x403a
525 #define MDIO_84833_TOP_CFG_SCRATCH_REG30 0x403b
526 #define MDIO_84833_TOP_CFG_SCRATCH_REG31 0x403c
527 #define MDIO_84833_CMD_HDLR_COMMAND MDIO_84833_TOP_CFG_SCRATCH_REG0
528 #define MDIO_84833_CMD_HDLR_STATUS MDIO_84833_TOP_CFG_SCRATCH_REG26
529 #define MDIO_84833_CMD_HDLR_DATA1 MDIO_84833_TOP_CFG_SCRATCH_REG27
530 #define MDIO_84833_CMD_HDLR_DATA2 MDIO_84833_TOP_CFG_SCRATCH_REG28
531 #define MDIO_84833_CMD_HDLR_DATA3 MDIO_84833_TOP_CFG_SCRATCH_REG29
532 #define MDIO_84833_CMD_HDLR_DATA4 MDIO_84833_TOP_CFG_SCRATCH_REG30
533 #define MDIO_84833_CMD_HDLR_DATA5 MDIO_84833_TOP_CFG_SCRATCH_REG31
535 /* Mailbox command set used by 84833. */
536 #define PHY84833_CMD_SET_PAIR_SWAP 0x8001
537 #define PHY84833_CMD_GET_EEE_MODE 0x8008
538 #define PHY84833_CMD_SET_EEE_MODE 0x8009
539 #define PHY84833_CMD_GET_CURRENT_TEMP 0x8031
540 /* Mailbox status set used by 84833. */
541 #define PHY84833_STATUS_CMD_RECEIVED 0x0001
542 #define PHY84833_STATUS_CMD_IN_PROGRESS 0x0002
543 #define PHY84833_STATUS_CMD_COMPLETE_PASS 0x0004
544 #define PHY84833_STATUS_CMD_COMPLETE_ERROR 0x0008
545 #define PHY84833_STATUS_CMD_OPEN_FOR_CMDS 0x0010
546 #define PHY84833_STATUS_CMD_SYSTEM_BOOT 0x0020
547 #define PHY84833_STATUS_CMD_NOT_OPEN_FOR_CMDS 0x0040
548 #define PHY84833_STATUS_CMD_CLEAR_COMPLETE 0x0080
549 #define PHY84833_STATUS_CMD_OPEN_OVERRIDE 0xa5a5
551 /* Warpcore clause 45 addressing */
552 #define MDIO_WC_DEVAD 0x3
553 #define MDIO_WC_REG_IEEE0BLK_MIICNTL 0x0
554 #define MDIO_WC_REG_IEEE0BLK_AUTONEGNP 0x7
555 #define MDIO_WC_REG_AN_IEEE1BLK_AN_ADVERTISEMENT0 0x10
556 #define MDIO_WC_REG_AN_IEEE1BLK_AN_ADVERTISEMENT1 0x11
557 #define MDIO_WC_REG_AN_IEEE1BLK_AN_ADVERTISEMENT2 0x12
558 #define MDIO_WC_REG_AN_IEEE1BLK_AN_ADV2_FEC_ABILITY 0x4000
559 #define MDIO_WC_REG_AN_IEEE1BLK_AN_ADV2_FEC_REQ 0x8000
560 #define MDIO_WC_REG_PCS_STATUS2 0x0021
561 #define MDIO_WC_REG_PMD_KR_CONTROL 0x0096
562 #define MDIO_WC_REG_XGXSBLK0_XGXSCONTROL 0x8000
563 #define MDIO_WC_REG_XGXSBLK0_MISCCONTROL1 0x800e
564 #define MDIO_WC_REG_XGXSBLK1_DESKEW 0x8010
565 #define MDIO_WC_REG_XGXSBLK1_LANECTRL0 0x8015
566 #define MDIO_WC_REG_XGXSBLK1_LANECTRL1 0x8016
567 #define MDIO_WC_REG_XGXSBLK1_LANECTRL2 0x8017
568 #define MDIO_WC_REG_XGXSBLK1_LANECTRL3 0x8018
569 #define MDIO_WC_REG_XGXSBLK1_LANETEST0 0x801a
570 #define MDIO_WC_REG_TX0_ANA_CTRL0 0x8061
571 #define MDIO_WC_REG_TX1_ANA_CTRL0 0x8071
572 #define MDIO_WC_REG_TX2_ANA_CTRL0 0x8081
573 #define MDIO_WC_REG_TX3_ANA_CTRL0 0x8091
574 #define MDIO_WC_REG_TX0_TX_DRIVER 0x8067
575 #define MDIO_WC_REG_TX0_TX_DRIVER_IPRE_DRIVER_OFFSET 0x04
576 #define MDIO_WC_REG_TX0_TX_DRIVER_IPRE_DRIVER_MASK 0x00f0
577 #define MDIO_WC_REG_TX0_TX_DRIVER_IDRIVER_OFFSET 0x08
578 #define MDIO_WC_REG_TX0_TX_DRIVER_IDRIVER_MASK 0x0f00
579 #define MDIO_WC_REG_TX0_TX_DRIVER_POST2_COEFF_OFFSET 0x0c
580 #define MDIO_WC_REG_TX0_TX_DRIVER_POST2_COEFF_MASK 0x7000
581 #define MDIO_WC_REG_TX1_TX_DRIVER 0x8077
582 #define MDIO_WC_REG_TX2_TX_DRIVER 0x8087
583 #define MDIO_WC_REG_TX3_TX_DRIVER 0x8097
584 #define MDIO_WC_REG_RX0_ANARXCONTROL1G 0x80b9
585 #define MDIO_WC_REG_RX2_ANARXCONTROL1G 0x80d9
586 #define MDIO_WC_REG_RX0_PCI_CTRL 0x80ba
587 #define MDIO_WC_REG_RX1_PCI_CTRL 0x80ca
588 #define MDIO_WC_REG_RX2_PCI_CTRL 0x80da
589 #define MDIO_WC_REG_RX3_PCI_CTRL 0x80ea
590 #define MDIO_WC_REG_XGXSBLK2_UNICORE_MODE_10G 0x8104
591 #define MDIO_WC_REG_XGXS_STATUS3 0x8129
592 #define MDIO_WC_REG_PAR_DET_10G_STATUS 0x8130
593 #define MDIO_WC_REG_PAR_DET_10G_CTRL 0x8131
594 #define MDIO_WC_REG_XGXS_STATUS4 0x813c
595 #define MDIO_WC_REG_XGXS_X2_CONTROL2 0x8141
596 #define MDIO_WC_REG_XGXS_X2_CONTROL3 0x8142
597 #define MDIO_WC_REG_XGXS_RX_LN_SWAP1 0x816B
598 #define MDIO_WC_REG_XGXS_TX_LN_SWAP1 0x8169
599 #define MDIO_WC_REG_GP2_STATUS_GP_2_0 0x81d0
600 #define MDIO_WC_REG_GP2_STATUS_GP_2_1 0x81d1
601 #define MDIO_WC_REG_GP2_STATUS_GP_2_2 0x81d2
602 #define MDIO_WC_REG_GP2_STATUS_GP_2_3 0x81d3
603 #define MDIO_WC_REG_GP2_STATUS_GP_2_4 0x81d4
604 #define MDIO_WC_REG_GP2_STATUS_GP_2_4_CL73_AN_CMPL 0x1000
605 #define MDIO_WC_REG_GP2_STATUS_GP_2_4_CL37_AN_CMPL 0x0100
606 #define MDIO_WC_REG_GP2_STATUS_GP_2_4_CL37_LP_AN_CAP 0x0010
607 #define MDIO_WC_REG_GP2_STATUS_GP_2_4_CL37_AN_CAP 0x1
608 #define MDIO_WC_REG_UC_INFO_B0_DEAD_TRAP 0x81EE
609 #define MDIO_WC_REG_UC_INFO_B1_VERSION 0x81F0
610 #define MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE 0x81F2
611 #define MDIO_WC_REG_UC_INFO_B1_FIRMWARE_LANE0_OFFSET 0x0
612 #define MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE_DEFAULT 0x0
613 #define MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE_SFP_OPT_LR 0x1
614 #define MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE_SFP_DAC 0x2
615 #define MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE_SFP_XLAUI 0x3
616 #define MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE_LONG_CH_6G 0x4
617 #define MDIO_WC_REG_UC_INFO_B1_FIRMWARE_LANE1_OFFSET 0x4
618 #define MDIO_WC_REG_UC_INFO_B1_FIRMWARE_LANE2_OFFSET 0x8
619 #define MDIO_WC_REG_UC_INFO_B1_FIRMWARE_LANE3_OFFSET 0xc
620 #define MDIO_WC_REG_UC_INFO_B1_CRC 0x81FE
621 #define MDIO_WC_REG_DSC1B0_UC_CTRL 0x820e
622 #define MDIO_WC_REG_DSC1B0_UC_CTRL_RDY4CMD (1<<7)
623 #define MDIO_WC_REG_DSC_SMC 0x8213
624 #define MDIO_WC_REG_DSC2B0_DSC_MISC_CTRL0 0x821e
625 #define MDIO_WC_REG_TX_FIR_TAP 0x82e2
626 #define MDIO_WC_REG_TX_FIR_TAP_PRE_TAP_OFFSET 0x00
627 #define MDIO_WC_REG_TX_FIR_TAP_PRE_TAP_MASK 0x000f
628 #define MDIO_WC_REG_TX_FIR_TAP_MAIN_TAP_OFFSET 0x04
629 #define MDIO_WC_REG_TX_FIR_TAP_MAIN_TAP_MASK 0x03f0
630 #define MDIO_WC_REG_TX_FIR_TAP_POST_TAP_OFFSET 0x0a
631 #define MDIO_WC_REG_TX_FIR_TAP_POST_TAP_MASK 0x7c00
632 #define MDIO_WC_REG_TX_FIR_TAP_ENABLE 0x8000
633 #define MDIO_WC_REG_CL72_USERB0_CL72_TX_FIR_TAP 0x82e2
634 #define MDIO_WC_REG_CL72_USERB0_CL72_MISC1_CONTROL 0x82e3
635 #define MDIO_WC_REG_CL72_USERB0_CL72_OS_DEF_CTRL 0x82e6
636 #define MDIO_WC_REG_CL72_USERB0_CL72_BR_DEF_CTRL 0x82e7
637 #define MDIO_WC_REG_CL72_USERB0_CL72_2P5_DEF_CTRL 0x82e8
638 #define MDIO_WC_REG_CL72_USERB0_CL72_MISC4_CONTROL 0x82ec
639 #define MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1 0x8300
640 #define MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2 0x8301
641 #define MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X3 0x8302
642 #define MDIO_WC_REG_SERDESDIGITAL_STATUS1000X1 0x8304
643 #define MDIO_WC_REG_SERDESDIGITAL_MISC1 0x8308
644 #define MDIO_WC_REG_SERDESDIGITAL_MISC2 0x8309
645 #define MDIO_WC_REG_DIGITAL3_UP1 0x8329
646 #define MDIO_WC_REG_DIGITAL3_LP_UP1 0x832c
647 #define MDIO_WC_REG_DIGITAL4_MISC3 0x833c
648 #define MDIO_WC_REG_DIGITAL4_MISC5 0x833e
649 #define MDIO_WC_REG_DIGITAL5_MISC6 0x8345
650 #define MDIO_WC_REG_DIGITAL5_MISC7 0x8349
651 #define MDIO_WC_REG_DIGITAL5_LINK_STATUS 0x834d
652 #define MDIO_WC_REG_DIGITAL5_ACTUAL_SPEED 0x834e
653 #define MDIO_WC_REG_DIGITAL6_MP5_NEXTPAGECTRL 0x8350
654 #define MDIO_WC_REG_CL49_USERB0_CTRL 0x8368
655 #define MDIO_WC_REG_CL73_USERB0_CTRL 0x8370
656 #define MDIO_WC_REG_CL73_USERB0_USTAT 0x8371
657 #define MDIO_WC_REG_CL73_BAM_CTRL1 0x8372
658 #define MDIO_WC_REG_CL73_BAM_CTRL2 0x8373
659 #define MDIO_WC_REG_CL73_BAM_CTRL3 0x8374
660 #define MDIO_WC_REG_CL73_BAM_CODE_FIELD 0x837b
661 #define MDIO_WC_REG_EEE_COMBO_CONTROL0 0x8390
662 #define MDIO_WC_REG_TX66_CONTROL 0x83b0
663 #define MDIO_WC_REG_RX66_CONTROL 0x83c0
664 #define MDIO_WC_REG_RX66_SCW0 0x83c2
665 #define MDIO_WC_REG_RX66_SCW1 0x83c3
666 #define MDIO_WC_REG_RX66_SCW2 0x83c4
667 #define MDIO_WC_REG_RX66_SCW3 0x83c5
668 #define MDIO_WC_REG_RX66_SCW0_MASK 0x83c6
669 #define MDIO_WC_REG_RX66_SCW1_MASK 0x83c7
670 #define MDIO_WC_REG_RX66_SCW2_MASK 0x83c8
671 #define MDIO_WC_REG_RX66_SCW3_MASK 0x83c9
672 #define MDIO_WC_REG_FX100_CTRL1 0x8400
673 #define MDIO_WC_REG_FX100_CTRL3 0x8402
674 #define MDIO_WC_REG_CL82_USERB1_TX_CTRL5 0x8436
675 #define MDIO_WC_REG_CL82_USERB1_TX_CTRL6 0x8437
676 #define MDIO_WC_REG_CL82_USERB1_TX_CTRL7 0x8438
677 #define MDIO_WC_REG_CL82_USERB1_TX_CTRL9 0x8439
678 #define MDIO_WC_REG_CL82_USERB1_RX_CTRL10 0x843a
679 #define MDIO_WC_REG_CL82_USERB1_RX_CTRL11 0x843b
680 #define MDIO_WC_REG_ETA_CL73_OUI1 0x8453
681 #define MDIO_WC_REG_ETA_CL73_OUI2 0x8454
682 #define MDIO_WC_REG_ETA_CL73_OUI3 0x8455
683 #define MDIO_WC_REG_ETA_CL73_LD_BAM_CODE 0x8456
684 #define MDIO_WC_REG_ETA_CL73_LD_UD_CODE 0x8457
685 #define MDIO_WC_REG_MICROBLK_CMD 0xffc2
686 #define MDIO_WC_REG_MICROBLK_DL_STATUS 0xffc5
687 #define MDIO_WC_REG_MICROBLK_CMD3 0xffcc
689 #define MDIO_WC_REG_AERBLK_AER 0xffde
690 #define MDIO_WC_REG_COMBO_IEEE0_MIICTRL 0xffe0
691 #define MDIO_WC_REG_COMBO_IEEE0_MIIISTAT 0xffe1
693 #define MDIO_WC0_XGXS_BLK2_LANE_RESET 0x810A
694 #define MDIO_WC0_XGXS_BLK2_LANE_RESET_RX_BITSHIFT 0
695 #define MDIO_WC0_XGXS_BLK2_LANE_RESET_TX_BITSHIFT 4
697 #define MDIO_WC0_XGXS_BLK6_XGXS_X2_CONTROL2 0x8141
699 #define DIGITAL5_ACTUAL_SPEED_TX_MASK 0x003f
702 #define MDIO_REG_GPHY_MII_STATUS 0x1
703 #define MDIO_REG_GPHY_PHYID_LSB 0x3
704 #define MDIO_REG_GPHY_CL45_ADDR_REG 0xd
705 #define MDIO_REG_GPHY_CL45_REG_WRITE 0x4000
706 #define MDIO_REG_GPHY_CL45_REG_READ 0xc000
707 #define MDIO_REG_GPHY_CL45_DATA_REG 0xe
708 #define MDIO_REG_GPHY_EEE_RESOLVED 0x803e
709 #define MDIO_REG_GPHY_EXP_ACCESS_GATE 0x15
710 #define MDIO_REG_GPHY_EXP_ACCESS 0x17
711 #define MDIO_REG_GPHY_EXP_ACCESS_TOP 0xd00
712 #define MDIO_REG_GPHY_EXP_TOP_2K_BUF 0x40
713 #define MDIO_REG_GPHY_AUX_STATUS 0x19
714 #define MDIO_REG_INTR_STATUS 0x1a
715 #define MDIO_REG_INTR_MASK 0x1b
716 #define MDIO_REG_INTR_MASK_LINK_STATUS (0x1 << 1)
717 #define MDIO_REG_GPHY_SHADOW 0x1c
718 #define MDIO_REG_GPHY_SHADOW_LED_SEL1 (0x0d << 10)
719 #define MDIO_REG_GPHY_SHADOW_LED_SEL2 (0x0e << 10)
720 #define MDIO_REG_GPHY_SHADOW_WR_ENA (0x1 << 15)
721 #define MDIO_REG_GPHY_SHADOW_AUTO_DET_MED (0x1e << 10)
722 #define MDIO_REG_GPHY_SHADOW_INVERT_FIB_SD (0x1 << 8)
724 typedef elink_status_t(*read_sfp_module_eeprom_func_p) (struct elink_phy * phy,
725 struct elink_params *
732 /********************************************************/
733 #define ELINK_ETH_HLEN 14
734 /* L2 header size + 2*VLANs (8 bytes) + LLC SNAP (8 bytes) */
735 #define ELINK_ETH_OVREHEAD (ELINK_ETH_HLEN + 8 + 8)
736 #define ELINK_ETH_MIN_PACKET_SIZE 60
737 #define ELINK_ETH_MAX_PACKET_SIZE 1500
738 #define ELINK_ETH_MAX_JUMBO_PACKET_SIZE 9600
739 #define ELINK_MDIO_ACCESS_TIMEOUT 1000
740 #define WC_LANE_MAX 4
741 #define I2C_SWITCH_WIDTH 2
744 #define I2C_WA_RETRY_CNT 3
745 #define I2C_WA_PWR_ITER (I2C_WA_RETRY_CNT - 1)
746 #define MCPR_IMC_COMMAND_READ_OP 1
747 #define MCPR_IMC_COMMAND_WRITE_OP 2
749 /* LED Blink rate that will achieve ~15.9Hz */
750 #define LED_BLINK_RATE_VAL_E3 354
751 #define LED_BLINK_RATE_VAL_E1X_E2 480
752 /***********************************************************/
753 /* Shortcut definitions */
754 /***********************************************************/
756 #define ELINK_NIG_LATCH_BC_ENABLE_MI_INT 0
758 #define ELINK_NIG_STATUS_EMAC0_MI_INT \
759 NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_EMAC0_MISC_MI_INT
760 #define ELINK_NIG_STATUS_XGXS0_LINK10G \
761 NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK10G
762 #define ELINK_NIG_STATUS_XGXS0_LINK_STATUS \
763 NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK_STATUS
764 #define ELINK_NIG_STATUS_XGXS0_LINK_STATUS_SIZE \
765 NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK_STATUS_SIZE
766 #define ELINK_NIG_STATUS_SERDES0_LINK_STATUS \
767 NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_SERDES0_LINK_STATUS
768 #define ELINK_NIG_MASK_MI_INT \
769 NIG_MASK_INTERRUPT_PORT0_REG_MASK_EMAC0_MISC_MI_INT
770 #define ELINK_NIG_MASK_XGXS0_LINK10G \
771 NIG_MASK_INTERRUPT_PORT0_REG_MASK_XGXS0_LINK10G
772 #define ELINK_NIG_MASK_XGXS0_LINK_STATUS \
773 NIG_MASK_INTERRUPT_PORT0_REG_MASK_XGXS0_LINK_STATUS
774 #define ELINK_NIG_MASK_SERDES0_LINK_STATUS \
775 NIG_MASK_INTERRUPT_PORT0_REG_MASK_SERDES0_LINK_STATUS
777 #define ELINK_MDIO_AN_CL73_OR_37_COMPLETE \
778 (MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_AUTONEG_COMPLETE | \
779 MDIO_GP_STATUS_TOP_AN_STATUS1_CL37_AUTONEG_COMPLETE)
781 #define ELINK_XGXS_RESET_BITS \
782 (MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_RSTB_HW | \
783 MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_IDDQ | \
784 MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_PWRDWN | \
785 MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_PWRDWN_SD | \
786 MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_TXD_FIFO_RSTB)
788 #define ELINK_SERDES_RESET_BITS \
789 (MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_RSTB_HW | \
790 MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_IDDQ | \
791 MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_PWRDWN | \
792 MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_PWRDWN_SD)
794 #define ELINK_AUTONEG_CL37 SHARED_HW_CFG_AN_ENABLE_CL37
795 #define ELINK_AUTONEG_CL73 SHARED_HW_CFG_AN_ENABLE_CL73
796 #define ELINK_AUTONEG_BAM SHARED_HW_CFG_AN_ENABLE_BAM
797 #define ELINK_AUTONEG_PARALLEL \
798 SHARED_HW_CFG_AN_ENABLE_PARALLEL_DETECTION
799 #define ELINK_AUTONEG_SGMII_FIBER_AUTODET \
800 SHARED_HW_CFG_AN_EN_SGMII_FIBER_AUTO_DETECT
801 #define ELINK_AUTONEG_REMOTE_PHY SHARED_HW_CFG_AN_ENABLE_REMOTE_PHY
803 #define ELINK_GP_STATUS_PAUSE_RSOLUTION_TXSIDE \
804 MDIO_GP_STATUS_TOP_AN_STATUS1_PAUSE_RSOLUTION_TXSIDE
805 #define ELINK_GP_STATUS_PAUSE_RSOLUTION_RXSIDE \
806 MDIO_GP_STATUS_TOP_AN_STATUS1_PAUSE_RSOLUTION_RXSIDE
807 #define ELINK_GP_STATUS_SPEED_MASK \
808 MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_MASK
809 #define ELINK_GP_STATUS_10M MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10M
810 #define ELINK_GP_STATUS_100M MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_100M
811 #define ELINK_GP_STATUS_1G MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_1G
812 #define ELINK_GP_STATUS_2_5G MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_2_5G
813 #define ELINK_GP_STATUS_5G MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_5G
814 #define ELINK_GP_STATUS_6G MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_6G
815 #define ELINK_GP_STATUS_10G_HIG \
816 MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_HIG
817 #define ELINK_GP_STATUS_10G_CX4 \
818 MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_CX4
819 #define ELINK_GP_STATUS_1G_KX MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_1G_KX
820 #define ELINK_GP_STATUS_10G_KX4 \
821 MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_KX4
822 #define ELINK_GP_STATUS_10G_KR MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_KR
823 #define ELINK_GP_STATUS_10G_XFI MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_XFI
824 #define ELINK_GP_STATUS_20G_DXGXS MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_20G_DXGXS
825 #define ELINK_GP_STATUS_10G_SFI MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_SFI
826 #define ELINK_GP_STATUS_20G_KR2 MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_20G_KR2
827 #define ELINK_LINK_10THD LINK_STATUS_SPEED_AND_DUPLEX_10THD
828 #define ELINK_LINK_10TFD LINK_STATUS_SPEED_AND_DUPLEX_10TFD
829 #define ELINK_LINK_100TXHD LINK_STATUS_SPEED_AND_DUPLEX_100TXHD
830 #define ELINK_LINK_100T4 LINK_STATUS_SPEED_AND_DUPLEX_100T4
831 #define ELINK_LINK_100TXFD LINK_STATUS_SPEED_AND_DUPLEX_100TXFD
832 #define ELINK_LINK_1000THD LINK_STATUS_SPEED_AND_DUPLEX_1000THD
833 #define ELINK_LINK_1000TFD LINK_STATUS_SPEED_AND_DUPLEX_1000TFD
834 #define ELINK_LINK_1000XFD LINK_STATUS_SPEED_AND_DUPLEX_1000XFD
835 #define ELINK_LINK_2500THD LINK_STATUS_SPEED_AND_DUPLEX_2500THD
836 #define ELINK_LINK_2500TFD LINK_STATUS_SPEED_AND_DUPLEX_2500TFD
837 #define ELINK_LINK_2500XFD LINK_STATUS_SPEED_AND_DUPLEX_2500XFD
838 #define ELINK_LINK_10GTFD LINK_STATUS_SPEED_AND_DUPLEX_10GTFD
839 #define ELINK_LINK_10GXFD LINK_STATUS_SPEED_AND_DUPLEX_10GXFD
840 #define ELINK_LINK_20GTFD LINK_STATUS_SPEED_AND_DUPLEX_20GTFD
841 #define ELINK_LINK_20GXFD LINK_STATUS_SPEED_AND_DUPLEX_20GXFD
843 #define ELINK_LINK_UPDATE_MASK \
844 (LINK_STATUS_SPEED_AND_DUPLEX_MASK | \
845 LINK_STATUS_LINK_UP | \
846 LINK_STATUS_PHYSICAL_LINK_FLAG | \
847 LINK_STATUS_AUTO_NEGOTIATE_COMPLETE | \
848 LINK_STATUS_RX_FLOW_CONTROL_FLAG_MASK | \
849 LINK_STATUS_TX_FLOW_CONTROL_FLAG_MASK | \
850 LINK_STATUS_PARALLEL_DETECTION_FLAG_MASK | \
851 LINK_STATUS_LINK_PARTNER_SYMMETRIC_PAUSE | \
852 LINK_STATUS_LINK_PARTNER_ASYMMETRIC_PAUSE)
854 #define ELINK_SFP_EEPROM_CON_TYPE_ADDR 0x2
855 #define ELINK_SFP_EEPROM_CON_TYPE_VAL_LC 0x7
856 #define ELINK_SFP_EEPROM_CON_TYPE_VAL_COPPER 0x21
857 #define ELINK_SFP_EEPROM_CON_TYPE_VAL_RJ45 0x22
859 #define ELINK_SFP_EEPROM_COMP_CODE_ADDR 0x3
860 #define ELINK_SFP_EEPROM_COMP_CODE_SR_MASK (1<<4)
861 #define ELINK_SFP_EEPROM_COMP_CODE_LR_MASK (1<<5)
862 #define ELINK_SFP_EEPROM_COMP_CODE_LRM_MASK (1<<6)
864 #define ELINK_SFP_EEPROM_FC_TX_TECH_ADDR 0x8
865 #define ELINK_SFP_EEPROM_FC_TX_TECH_BITMASK_COPPER_PASSIVE 0x4
866 #define ELINK_SFP_EEPROM_FC_TX_TECH_BITMASK_COPPER_ACTIVE 0x8
868 #define ELINK_SFP_EEPROM_OPTIONS_ADDR 0x40
869 #define ELINK_SFP_EEPROM_OPTIONS_LINEAR_RX_OUT_MASK 0x1
870 #define ELINK_SFP_EEPROM_OPTIONS_SIZE 2
872 #define ELINK_EDC_MODE_LINEAR 0x0022
873 #define ELINK_EDC_MODE_LIMITING 0x0044
874 #define ELINK_EDC_MODE_PASSIVE_DAC 0x0055
875 #define ELINK_EDC_MODE_ACTIVE_DAC 0x0066
878 #define DCBX_INVALID_COS (0xFF)
880 #define ELINK_ETS_BW_LIMIT_CREDIT_UPPER_BOUND (0x5000)
881 #define ELINK_ETS_BW_LIMIT_CREDIT_WEIGHT (0x5000)
882 #define ELINK_ETS_E3B0_NIG_MIN_W_VAL_UP_TO_10GBPS (1360)
883 #define ELINK_ETS_E3B0_NIG_MIN_W_VAL_20GBPS (2720)
884 #define ELINK_ETS_E3B0_PBF_MIN_W_VAL (10000)
886 #define ELINK_MAX_PACKET_SIZE (9700)
887 #define MAX_KR_LINK_RETRY 4
889 /**********************************************************/
891 /**********************************************************/
893 #define CL22_WR_OVER_CL45(_sc, _phy, _bank, _addr, _val) \
894 elink_cl45_write(_sc, _phy, \
895 (_phy)->def_md_devad, \
896 (_bank + (_addr & 0xf)), \
899 #define CL22_RD_OVER_CL45(_sc, _phy, _bank, _addr, _val) \
900 elink_cl45_read(_sc, _phy, \
901 (_phy)->def_md_devad, \
902 (_bank + (_addr & 0xf)), \
905 static uint32_t elink_bits_en(struct bnx2x_softc *sc, uint32_t reg, uint32_t bits)
907 uint32_t val = REG_RD(sc, reg);
910 REG_WR(sc, reg, val);
914 static uint32_t elink_bits_dis(struct bnx2x_softc *sc, uint32_t reg,
917 uint32_t val = REG_RD(sc, reg);
920 REG_WR(sc, reg, val);
925 * elink_check_lfa - This function checks if link reinitialization is required,
926 * or link flap can be avoided.
928 * @params: link parameters
929 * Returns 0 if Link Flap Avoidance conditions are met otherwise, the failed
932 static int elink_check_lfa(struct elink_params *params)
934 uint32_t link_status, cfg_idx, lfa_mask, cfg_size;
935 uint32_t cur_speed_cap_mask, cur_req_fc_auto_adv, additional_config;
936 uint32_t saved_val, req_val, eee_status;
937 struct bnx2x_softc *sc = params->sc;
940 REG_RD(sc, params->lfa_base +
941 offsetof(struct shmem_lfa, additional_config));
943 /* NOTE: must be first condition checked -
944 * to verify DCC bit is cleared in any case!
946 if (additional_config & NO_LFA_DUE_TO_DCC_MASK) {
947 PMD_DRV_LOG(DEBUG, sc, "No LFA due to DCC flap after clp exit");
948 REG_WR(sc, params->lfa_base +
949 offsetof(struct shmem_lfa, additional_config),
950 additional_config & ~NO_LFA_DUE_TO_DCC_MASK);
951 return LFA_DCC_LFA_DISABLED;
954 /* Verify that link is up */
955 link_status = REG_RD(sc, params->shmem_base +
956 offsetof(struct shmem_region,
957 port_mb[params->port].link_status));
958 if (!(link_status & LINK_STATUS_LINK_UP))
959 return LFA_LINK_DOWN;
961 /* if loaded after BOOT from SAN, don't flap the link in any case and
962 * rely on link set by preboot driver
964 if (params->feature_config_flags & ELINK_FEATURE_CONFIG_BOOT_FROM_SAN)
967 /* Verify that loopback mode is not set */
968 if (params->loopback_mode)
969 return LFA_LOOPBACK_ENABLED;
971 /* Verify that MFW supports LFA */
972 if (!params->lfa_base)
973 return LFA_MFW_IS_TOO_OLD;
975 if (params->num_phys == 3) {
977 lfa_mask = 0xffffffff;
984 saved_val = REG_RD(sc, params->lfa_base +
985 offsetof(struct shmem_lfa, req_duplex));
986 req_val = params->req_duplex[0] | (params->req_duplex[1] << 16);
987 if ((saved_val & lfa_mask) != (req_val & lfa_mask)) {
988 PMD_DRV_LOG(INFO, sc, "Duplex mismatch %x vs. %x",
989 (saved_val & lfa_mask), (req_val & lfa_mask));
990 return LFA_DUPLEX_MISMATCH;
992 /* Compare Flow Control */
993 saved_val = REG_RD(sc, params->lfa_base +
994 offsetof(struct shmem_lfa, req_flow_ctrl));
995 req_val = params->req_flow_ctrl[0] | (params->req_flow_ctrl[1] << 16);
996 if ((saved_val & lfa_mask) != (req_val & lfa_mask)) {
997 PMD_DRV_LOG(DEBUG, sc, "Flow control mismatch %x vs. %x",
998 (saved_val & lfa_mask), (req_val & lfa_mask));
999 return LFA_FLOW_CTRL_MISMATCH;
1001 /* Compare Link Speed */
1002 saved_val = REG_RD(sc, params->lfa_base +
1003 offsetof(struct shmem_lfa, req_line_speed));
1004 req_val = params->req_line_speed[0] | (params->req_line_speed[1] << 16);
1005 if ((saved_val & lfa_mask) != (req_val & lfa_mask)) {
1006 PMD_DRV_LOG(DEBUG, sc, "Link speed mismatch %x vs. %x",
1007 (saved_val & lfa_mask), (req_val & lfa_mask));
1008 return LFA_LINK_SPEED_MISMATCH;
1011 for (cfg_idx = 0; cfg_idx < cfg_size; cfg_idx++) {
1012 cur_speed_cap_mask = REG_RD(sc, params->lfa_base +
1013 offsetof(struct shmem_lfa,
1014 speed_cap_mask[cfg_idx]));
1016 if (cur_speed_cap_mask != params->speed_cap_mask[cfg_idx]) {
1017 PMD_DRV_LOG(DEBUG, sc, "Speed Cap mismatch %x vs. %x",
1019 params->speed_cap_mask[cfg_idx]);
1020 return LFA_SPEED_CAP_MISMATCH;
1024 cur_req_fc_auto_adv =
1025 REG_RD(sc, params->lfa_base +
1026 offsetof(struct shmem_lfa, additional_config)) &
1027 REQ_FC_AUTO_ADV_MASK;
1029 if ((uint16_t) cur_req_fc_auto_adv != params->req_fc_auto_adv) {
1030 PMD_DRV_LOG(DEBUG, sc, "Flow Ctrl AN mismatch %x vs. %x",
1031 cur_req_fc_auto_adv, params->req_fc_auto_adv);
1032 return LFA_FLOW_CTRL_MISMATCH;
1035 eee_status = REG_RD(sc, params->shmem2_base +
1036 offsetof(struct shmem2_region,
1037 eee_status[params->port]));
1039 if (((eee_status & SHMEM_EEE_LPI_REQUESTED_BIT) ^
1040 (params->eee_mode & ELINK_EEE_MODE_ENABLE_LPI)) ||
1041 ((eee_status & SHMEM_EEE_REQUESTED_BIT) ^
1042 (params->eee_mode & ELINK_EEE_MODE_ADV_LPI))) {
1043 PMD_DRV_LOG(DEBUG, sc,
1044 "EEE mismatch %x vs. %x", params->eee_mode,
1046 return LFA_EEE_MISMATCH;
1049 /* LFA conditions are met */
1053 /******************************************************************/
1054 /* EPIO/GPIO section */
1055 /******************************************************************/
1056 static void elink_get_epio(struct bnx2x_softc *sc, uint32_t epio_pin,
1059 uint32_t epio_mask, gp_oenable;
1062 if (epio_pin > 31) {
1063 PMD_DRV_LOG(DEBUG, sc, "Invalid EPIO pin %d to get", epio_pin);
1067 epio_mask = 1 << epio_pin;
1068 /* Set this EPIO to output */
1069 gp_oenable = REG_RD(sc, MCP_REG_MCPR_GP_OENABLE);
1070 REG_WR(sc, MCP_REG_MCPR_GP_OENABLE, gp_oenable & ~epio_mask);
1072 *en = (REG_RD(sc, MCP_REG_MCPR_GP_INPUTS) & epio_mask) >> epio_pin;
1075 static void elink_set_epio(struct bnx2x_softc *sc, uint32_t epio_pin, uint32_t en)
1077 uint32_t epio_mask, gp_output, gp_oenable;
1080 if (epio_pin > 31) {
1081 PMD_DRV_LOG(DEBUG, sc, "Invalid EPIO pin %d to set", epio_pin);
1084 PMD_DRV_LOG(DEBUG, sc, "Setting EPIO pin %d to %d", epio_pin, en);
1085 epio_mask = 1 << epio_pin;
1086 /* Set this EPIO to output */
1087 gp_output = REG_RD(sc, MCP_REG_MCPR_GP_OUTPUTS);
1089 gp_output |= epio_mask;
1091 gp_output &= ~epio_mask;
1093 REG_WR(sc, MCP_REG_MCPR_GP_OUTPUTS, gp_output);
1095 /* Set the value for this EPIO */
1096 gp_oenable = REG_RD(sc, MCP_REG_MCPR_GP_OENABLE);
1097 REG_WR(sc, MCP_REG_MCPR_GP_OENABLE, gp_oenable | epio_mask);
1100 static void elink_set_cfg_pin(struct bnx2x_softc *sc, uint32_t pin_cfg,
1103 if (pin_cfg == PIN_CFG_NA)
1105 if (pin_cfg >= PIN_CFG_EPIO0) {
1106 elink_set_epio(sc, pin_cfg - PIN_CFG_EPIO0, val);
1108 uint8_t gpio_num = (pin_cfg - PIN_CFG_GPIO0_P0) & 0x3;
1109 uint8_t gpio_port = (pin_cfg - PIN_CFG_GPIO0_P0) >> 2;
1110 elink_cb_gpio_write(sc, gpio_num, (uint8_t) val, gpio_port);
1114 static uint32_t elink_get_cfg_pin(struct bnx2x_softc *sc, uint32_t pin_cfg,
1117 if (pin_cfg == PIN_CFG_NA)
1118 return ELINK_STATUS_ERROR;
1119 if (pin_cfg >= PIN_CFG_EPIO0) {
1120 elink_get_epio(sc, pin_cfg - PIN_CFG_EPIO0, val);
1122 uint8_t gpio_num = (pin_cfg - PIN_CFG_GPIO0_P0) & 0x3;
1123 uint8_t gpio_port = (pin_cfg - PIN_CFG_GPIO0_P0) >> 2;
1124 *val = elink_cb_gpio_read(sc, gpio_num, gpio_port);
1126 return ELINK_STATUS_OK;
1130 /******************************************************************/
1132 /******************************************************************/
1133 static void elink_update_pfc_xmac(struct elink_params *params,
1134 struct elink_vars *vars)
1136 struct bnx2x_softc *sc = params->sc;
1138 uint32_t pause_val, pfc0_val, pfc1_val;
1140 /* XMAC base adrr */
1141 xmac_base = (params->port) ? GRCBASE_XMAC1 : GRCBASE_XMAC0;
1143 /* Initialize pause and pfc registers */
1144 pause_val = 0x18000;
1145 pfc0_val = 0xFFFF8000;
1148 /* No PFC support */
1149 if (!(params->feature_config_flags & ELINK_FEATURE_CONFIG_PFC_ENABLED)) {
1151 /* RX flow control - Process pause frame in receive direction
1153 if (vars->flow_ctrl & ELINK_FLOW_CTRL_RX)
1154 pause_val |= XMAC_PAUSE_CTRL_REG_RX_PAUSE_EN;
1156 /* TX flow control - Send pause packet when buffer is full */
1157 if (vars->flow_ctrl & ELINK_FLOW_CTRL_TX)
1158 pause_val |= XMAC_PAUSE_CTRL_REG_TX_PAUSE_EN;
1159 } else { /* PFC support */
1160 pfc1_val |= XMAC_PFC_CTRL_HI_REG_PFC_REFRESH_EN |
1161 XMAC_PFC_CTRL_HI_REG_PFC_STATS_EN |
1162 XMAC_PFC_CTRL_HI_REG_RX_PFC_EN |
1163 XMAC_PFC_CTRL_HI_REG_TX_PFC_EN |
1164 XMAC_PFC_CTRL_HI_REG_FORCE_PFC_XON;
1165 /* Write pause and PFC registers */
1166 REG_WR(sc, xmac_base + XMAC_REG_PAUSE_CTRL, pause_val);
1167 REG_WR(sc, xmac_base + XMAC_REG_PFC_CTRL, pfc0_val);
1168 REG_WR(sc, xmac_base + XMAC_REG_PFC_CTRL_HI, pfc1_val);
1169 pfc1_val &= ~XMAC_PFC_CTRL_HI_REG_FORCE_PFC_XON;
1173 /* Write pause and PFC registers */
1174 REG_WR(sc, xmac_base + XMAC_REG_PAUSE_CTRL, pause_val);
1175 REG_WR(sc, xmac_base + XMAC_REG_PFC_CTRL, pfc0_val);
1176 REG_WR(sc, xmac_base + XMAC_REG_PFC_CTRL_HI, pfc1_val);
1178 /* Set MAC address for source TX Pause/PFC frames */
1179 REG_WR(sc, xmac_base + XMAC_REG_CTRL_SA_LO,
1180 ((params->mac_addr[2] << 24) |
1181 (params->mac_addr[3] << 16) |
1182 (params->mac_addr[4] << 8) | (params->mac_addr[5])));
1183 REG_WR(sc, xmac_base + XMAC_REG_CTRL_SA_HI,
1184 ((params->mac_addr[0] << 8) | (params->mac_addr[1])));
1189 /******************************************************************/
1190 /* MAC/PBF section */
1191 /******************************************************************/
1192 static void elink_set_mdio_clk(struct bnx2x_softc *sc, uint32_t emac_base)
1194 uint32_t new_mode, cur_mode;
1196 /* Set clause 45 mode, slow down the MDIO clock to 2.5MHz
1197 * (a value of 49==0x31) and make sure that the AUTO poll is off
1199 cur_mode = REG_RD(sc, emac_base + EMAC_REG_EMAC_MDIO_MODE);
1201 if (USES_WARPCORE(sc))
1202 clc_cnt = 74L << EMAC_MDIO_MODE_CLOCK_CNT_BITSHIFT;
1204 clc_cnt = 49L << EMAC_MDIO_MODE_CLOCK_CNT_BITSHIFT;
1206 if (((cur_mode & EMAC_MDIO_MODE_CLOCK_CNT) == clc_cnt) &&
1207 (cur_mode & (EMAC_MDIO_MODE_CLAUSE_45)))
1210 new_mode = cur_mode &
1211 ~(EMAC_MDIO_MODE_AUTO_POLL | EMAC_MDIO_MODE_CLOCK_CNT);
1212 new_mode |= clc_cnt;
1213 new_mode |= (EMAC_MDIO_MODE_CLAUSE_45);
1215 PMD_DRV_LOG(DEBUG, sc, "Changing emac_mode from 0x%x to 0x%x",
1216 cur_mode, new_mode);
1217 REG_WR(sc, emac_base + EMAC_REG_EMAC_MDIO_MODE, new_mode);
1221 static void elink_set_mdio_emac_per_phy(struct bnx2x_softc *sc,
1222 struct elink_params *params)
1225 /* Set mdio clock per phy */
1226 for (phy_index = ELINK_INT_PHY; phy_index < params->num_phys;
1228 elink_set_mdio_clk(sc, params->phy[phy_index].mdio_ctrl);
1231 static uint8_t elink_is_4_port_mode(struct bnx2x_softc *sc)
1233 uint32_t port4mode_ovwr_val;
1234 /* Check 4-port override enabled */
1235 port4mode_ovwr_val = REG_RD(sc, MISC_REG_PORT4MODE_EN_OVWR);
1236 if (port4mode_ovwr_val & (1 << 0)) {
1237 /* Return 4-port mode override value */
1238 return (port4mode_ovwr_val & (1 << 1)) == (1 << 1);
1240 /* Return 4-port mode from input pin */
1241 return (uint8_t) REG_RD(sc, MISC_REG_PORT4MODE_EN);
1244 static void elink_emac_init(struct elink_params *params)
1246 /* reset and unreset the emac core */
1247 struct bnx2x_softc *sc = params->sc;
1248 uint8_t port = params->port;
1249 uint32_t emac_base = port ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
1253 REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
1254 (MISC_REGISTERS_RESET_REG_2_RST_EMAC0_HARD_CORE << port));
1256 REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,
1257 (MISC_REGISTERS_RESET_REG_2_RST_EMAC0_HARD_CORE << port));
1259 /* init emac - use read-modify-write */
1260 /* self clear reset */
1261 val = REG_RD(sc, emac_base + EMAC_REG_EMAC_MODE);
1262 elink_cb_reg_write(sc, emac_base + EMAC_REG_EMAC_MODE,
1263 (val | EMAC_MODE_RESET));
1267 val = REG_RD(sc, emac_base + EMAC_REG_EMAC_MODE);
1268 PMD_DRV_LOG(DEBUG, sc, "EMAC reset reg is %u", val);
1270 PMD_DRV_LOG(DEBUG, sc, "EMAC timeout!");
1274 } while (val & EMAC_MODE_RESET);
1276 elink_set_mdio_emac_per_phy(sc, params);
1277 /* Set mac address */
1278 val = ((params->mac_addr[0] << 8) | params->mac_addr[1]);
1279 elink_cb_reg_write(sc, emac_base + EMAC_REG_EMAC_MAC_MATCH, val);
1281 val = ((params->mac_addr[2] << 24) |
1282 (params->mac_addr[3] << 16) |
1283 (params->mac_addr[4] << 8) | params->mac_addr[5]);
1284 elink_cb_reg_write(sc, emac_base + EMAC_REG_EMAC_MAC_MATCH + 4, val);
1287 static void elink_set_xumac_nig(struct elink_params *params,
1288 uint16_t tx_pause_en, uint8_t enable)
1290 struct bnx2x_softc *sc = params->sc;
1292 REG_WR(sc, params->port ? NIG_REG_P1_MAC_IN_EN : NIG_REG_P0_MAC_IN_EN,
1294 REG_WR(sc, params->port ? NIG_REG_P1_MAC_OUT_EN : NIG_REG_P0_MAC_OUT_EN,
1296 REG_WR(sc, params->port ? NIG_REG_P1_MAC_PAUSE_OUT_EN :
1297 NIG_REG_P0_MAC_PAUSE_OUT_EN, tx_pause_en);
1300 static void elink_set_umac_rxtx(struct elink_params *params, uint8_t en)
1302 uint32_t umac_base = params->port ? GRCBASE_UMAC1 : GRCBASE_UMAC0;
1304 struct bnx2x_softc *sc = params->sc;
1305 if (!(REG_RD(sc, MISC_REG_RESET_REG_2) &
1306 (MISC_REGISTERS_RESET_REG_2_UMAC0 << params->port)))
1308 val = REG_RD(sc, umac_base + UMAC_REG_COMMAND_CONFIG);
1310 val |= (UMAC_COMMAND_CONFIG_REG_TX_ENA |
1311 UMAC_COMMAND_CONFIG_REG_RX_ENA);
1313 val &= ~(UMAC_COMMAND_CONFIG_REG_TX_ENA |
1314 UMAC_COMMAND_CONFIG_REG_RX_ENA);
1315 /* Disable RX and TX */
1316 REG_WR(sc, umac_base + UMAC_REG_COMMAND_CONFIG, val);
1319 static void elink_umac_enable(struct elink_params *params,
1320 struct elink_vars *vars, uint8_t lb)
1323 uint32_t umac_base = params->port ? GRCBASE_UMAC1 : GRCBASE_UMAC0;
1324 struct bnx2x_softc *sc = params->sc;
1326 REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
1327 (MISC_REGISTERS_RESET_REG_2_UMAC0 << params->port));
1330 REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,
1331 (MISC_REGISTERS_RESET_REG_2_UMAC0 << params->port));
1333 PMD_DRV_LOG(DEBUG, sc, "enabling UMAC");
1335 /* This register opens the gate for the UMAC despite its name */
1336 REG_WR(sc, NIG_REG_EGRESS_EMAC0_PORT + params->port * 4, 1);
1338 val = UMAC_COMMAND_CONFIG_REG_PROMIS_EN |
1339 UMAC_COMMAND_CONFIG_REG_PAD_EN |
1340 UMAC_COMMAND_CONFIG_REG_SW_RESET |
1341 UMAC_COMMAND_CONFIG_REG_NO_LGTH_CHECK;
1342 switch (vars->line_speed) {
1343 case ELINK_SPEED_10:
1346 case ELINK_SPEED_100:
1349 case ELINK_SPEED_1000:
1352 case ELINK_SPEED_2500:
1356 PMD_DRV_LOG(DEBUG, sc, "Invalid speed for UMAC %d",
1360 if (!(vars->flow_ctrl & ELINK_FLOW_CTRL_TX))
1361 val |= UMAC_COMMAND_CONFIG_REG_IGNORE_TX_PAUSE;
1363 if (!(vars->flow_ctrl & ELINK_FLOW_CTRL_RX))
1364 val |= UMAC_COMMAND_CONFIG_REG_PAUSE_IGNORE;
1366 if (vars->duplex == DUPLEX_HALF)
1367 val |= UMAC_COMMAND_CONFIG_REG_HD_ENA;
1369 REG_WR(sc, umac_base + UMAC_REG_COMMAND_CONFIG, val);
1372 /* Configure UMAC for EEE */
1373 if (vars->eee_status & SHMEM_EEE_ADV_STATUS_MASK) {
1374 PMD_DRV_LOG(DEBUG, sc, "configured UMAC for EEE");
1375 REG_WR(sc, umac_base + UMAC_REG_UMAC_EEE_CTRL,
1376 UMAC_UMAC_EEE_CTRL_REG_EEE_EN);
1377 REG_WR(sc, umac_base + UMAC_REG_EEE_WAKE_TIMER, 0x11);
1379 REG_WR(sc, umac_base + UMAC_REG_UMAC_EEE_CTRL, 0x0);
1382 /* Set MAC address for source TX Pause/PFC frames (under SW reset) */
1383 REG_WR(sc, umac_base + UMAC_REG_MAC_ADDR0,
1384 ((params->mac_addr[2] << 24) |
1385 (params->mac_addr[3] << 16) |
1386 (params->mac_addr[4] << 8) | (params->mac_addr[5])));
1387 REG_WR(sc, umac_base + UMAC_REG_MAC_ADDR1,
1388 ((params->mac_addr[0] << 8) | (params->mac_addr[1])));
1390 /* Enable RX and TX */
1391 val &= ~UMAC_COMMAND_CONFIG_REG_PAD_EN;
1392 val |= UMAC_COMMAND_CONFIG_REG_TX_ENA | UMAC_COMMAND_CONFIG_REG_RX_ENA;
1393 REG_WR(sc, umac_base + UMAC_REG_COMMAND_CONFIG, val);
1396 /* Remove SW Reset */
1397 val &= ~UMAC_COMMAND_CONFIG_REG_SW_RESET;
1399 /* Check loopback mode */
1401 val |= UMAC_COMMAND_CONFIG_REG_LOOP_ENA;
1402 REG_WR(sc, umac_base + UMAC_REG_COMMAND_CONFIG, val);
1404 /* Maximum Frame Length (RW). Defines a 14-Bit maximum frame
1405 * length used by the MAC receive logic to check frames.
1407 REG_WR(sc, umac_base + UMAC_REG_MAXFR, 0x2710);
1408 elink_set_xumac_nig(params,
1409 ((vars->flow_ctrl & ELINK_FLOW_CTRL_TX) != 0), 1);
1410 vars->mac_type = ELINK_MAC_TYPE_UMAC;
1414 /* Define the XMAC mode */
1415 static void elink_xmac_init(struct elink_params *params, uint32_t max_speed)
1417 struct bnx2x_softc *sc = params->sc;
1418 uint32_t is_port4mode = elink_is_4_port_mode(sc);
1420 /* In 4-port mode, need to set the mode only once, so if XMAC is
1421 * already out of reset, it means the mode has already been set,
1422 * and it must not* reset the XMAC again, since it controls both
1426 if (((CHIP_NUM(sc) == CHIP_NUM_57840_4_10) ||
1427 (CHIP_NUM(sc) == CHIP_NUM_57840_2_20) ||
1428 (CHIP_NUM(sc) == CHIP_NUM_57840_OBS)) &&
1430 (REG_RD(sc, MISC_REG_RESET_REG_2) &
1431 MISC_REGISTERS_RESET_REG_2_XMAC)) {
1432 PMD_DRV_LOG(DEBUG, sc, "XMAC already out of reset in 4-port mode");
1437 REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
1438 MISC_REGISTERS_RESET_REG_2_XMAC);
1441 REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,
1442 MISC_REGISTERS_RESET_REG_2_XMAC);
1444 PMD_DRV_LOG(DEBUG, sc, "Init XMAC to 2 ports x 10G per path");
1446 /* Set the number of ports on the system side to up to 2 */
1447 REG_WR(sc, MISC_REG_XMAC_CORE_PORT_MODE, 1);
1449 /* Set the number of ports on the Warp Core to 10G */
1450 REG_WR(sc, MISC_REG_XMAC_PHY_PORT_MODE, 3);
1452 /* Set the number of ports on the system side to 1 */
1453 REG_WR(sc, MISC_REG_XMAC_CORE_PORT_MODE, 0);
1454 if (max_speed == ELINK_SPEED_10000) {
1455 PMD_DRV_LOG(DEBUG, sc,
1456 "Init XMAC to 10G x 1 port per path");
1457 /* Set the number of ports on the Warp Core to 10G */
1458 REG_WR(sc, MISC_REG_XMAC_PHY_PORT_MODE, 3);
1460 PMD_DRV_LOG(DEBUG, sc,
1461 "Init XMAC to 20G x 2 ports per path");
1462 /* Set the number of ports on the Warp Core to 20G */
1463 REG_WR(sc, MISC_REG_XMAC_PHY_PORT_MODE, 1);
1467 REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
1468 MISC_REGISTERS_RESET_REG_2_XMAC_SOFT);
1471 REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,
1472 MISC_REGISTERS_RESET_REG_2_XMAC_SOFT);
1476 static void elink_set_xmac_rxtx(struct elink_params *params, uint8_t en)
1478 uint8_t port = params->port;
1479 struct bnx2x_softc *sc = params->sc;
1480 uint32_t pfc_ctrl, xmac_base = (port) ? GRCBASE_XMAC1 : GRCBASE_XMAC0;
1483 if (REG_RD(sc, MISC_REG_RESET_REG_2) & MISC_REGISTERS_RESET_REG_2_XMAC) {
1484 /* Send an indication to change the state in the NIG back to XON
1485 * Clearing this bit enables the next set of this bit to get
1488 pfc_ctrl = REG_RD(sc, xmac_base + XMAC_REG_PFC_CTRL_HI);
1489 REG_WR(sc, xmac_base + XMAC_REG_PFC_CTRL_HI,
1490 (pfc_ctrl & ~(1 << 1)));
1491 REG_WR(sc, xmac_base + XMAC_REG_PFC_CTRL_HI,
1492 (pfc_ctrl | (1 << 1)));
1493 PMD_DRV_LOG(DEBUG, sc, "Disable XMAC on port %x", port);
1494 val = REG_RD(sc, xmac_base + XMAC_REG_CTRL);
1496 val |= (XMAC_CTRL_REG_TX_EN | XMAC_CTRL_REG_RX_EN);
1498 val &= ~(XMAC_CTRL_REG_TX_EN | XMAC_CTRL_REG_RX_EN);
1499 REG_WR(sc, xmac_base + XMAC_REG_CTRL, val);
1503 static elink_status_t elink_xmac_enable(struct elink_params *params,
1504 struct elink_vars *vars, uint8_t lb)
1506 uint32_t val, xmac_base;
1507 struct bnx2x_softc *sc = params->sc;
1508 PMD_DRV_LOG(DEBUG, sc, "enabling XMAC");
1510 xmac_base = (params->port) ? GRCBASE_XMAC1 : GRCBASE_XMAC0;
1512 elink_xmac_init(params, vars->line_speed);
1514 /* This register determines on which events the MAC will assert
1515 * error on the i/f to the NIG along w/ EOP.
1518 /* This register tells the NIG whether to send traffic to UMAC
1521 REG_WR(sc, NIG_REG_EGRESS_EMAC0_PORT + params->port * 4, 0);
1523 /* When XMAC is in XLGMII mode, disable sending idles for fault
1526 if (!(params->phy[ELINK_INT_PHY].flags & ELINK_FLAGS_TX_ERROR_CHECK)) {
1527 REG_WR(sc, xmac_base + XMAC_REG_RX_LSS_CTRL,
1528 (XMAC_RX_LSS_CTRL_REG_LOCAL_FAULT_DISABLE |
1529 XMAC_RX_LSS_CTRL_REG_REMOTE_FAULT_DISABLE));
1530 REG_WR(sc, xmac_base + XMAC_REG_CLEAR_RX_LSS_STATUS, 0);
1531 REG_WR(sc, xmac_base + XMAC_REG_CLEAR_RX_LSS_STATUS,
1532 XMAC_CLEAR_RX_LSS_STATUS_REG_CLEAR_LOCAL_FAULT_STATUS |
1533 XMAC_CLEAR_RX_LSS_STATUS_REG_CLEAR_REMOTE_FAULT_STATUS);
1535 /* Set Max packet size */
1536 REG_WR(sc, xmac_base + XMAC_REG_RX_MAX_SIZE, 0x2710);
1538 /* CRC append for Tx packets */
1539 REG_WR(sc, xmac_base + XMAC_REG_TX_CTRL, 0xC800);
1542 elink_update_pfc_xmac(params, vars);
1544 if (vars->eee_status & SHMEM_EEE_ADV_STATUS_MASK) {
1545 PMD_DRV_LOG(DEBUG, sc, "Setting XMAC for EEE");
1546 REG_WR(sc, xmac_base + XMAC_REG_EEE_TIMERS_HI, 0x1380008);
1547 REG_WR(sc, xmac_base + XMAC_REG_EEE_CTRL, 0x1);
1549 REG_WR(sc, xmac_base + XMAC_REG_EEE_CTRL, 0x0);
1552 /* Enable TX and RX */
1553 val = XMAC_CTRL_REG_TX_EN | XMAC_CTRL_REG_RX_EN;
1555 /* Set MAC in XLGMII mode for dual-mode */
1556 if ((vars->line_speed == ELINK_SPEED_20000) &&
1557 (params->phy[ELINK_INT_PHY].supported &
1558 ELINK_SUPPORTED_20000baseKR2_Full))
1559 val |= XMAC_CTRL_REG_XLGMII_ALIGN_ENB;
1561 /* Check loopback mode */
1563 val |= XMAC_CTRL_REG_LINE_LOCAL_LPBK;
1564 REG_WR(sc, xmac_base + XMAC_REG_CTRL, val);
1565 elink_set_xumac_nig(params,
1566 ((vars->flow_ctrl & ELINK_FLOW_CTRL_TX) != 0), 1);
1568 vars->mac_type = ELINK_MAC_TYPE_XMAC;
1570 return ELINK_STATUS_OK;
1573 static elink_status_t elink_emac_enable(struct elink_params *params,
1574 struct elink_vars *vars, uint8_t lb)
1576 struct bnx2x_softc *sc = params->sc;
1577 uint8_t port = params->port;
1578 uint32_t emac_base = port ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
1581 PMD_DRV_LOG(DEBUG, sc, "enabling EMAC");
1584 REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
1585 (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port));
1587 /* enable emac and not bmac */
1588 REG_WR(sc, NIG_REG_EGRESS_EMAC0_PORT + port * 4, 1);
1590 if (vars->phy_flags & PHY_XGXS_FLAG) {
1591 uint32_t ser_lane = ((params->lane_config &
1592 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK) >>
1593 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT);
1595 PMD_DRV_LOG(DEBUG, sc, "XGXS");
1596 /* select the master lanes (out of 0-3) */
1597 REG_WR(sc, NIG_REG_XGXS_LANE_SEL_P0 + port * 4, ser_lane);
1599 REG_WR(sc, NIG_REG_XGXS_SERDES0_MODE_SEL + port * 4, 1);
1601 } else { /* SerDes */
1602 PMD_DRV_LOG(DEBUG, sc, "SerDes");
1604 REG_WR(sc, NIG_REG_XGXS_SERDES0_MODE_SEL + port * 4, 0);
1607 elink_bits_en(sc, emac_base + EMAC_REG_EMAC_RX_MODE,
1608 EMAC_RX_MODE_RESET);
1609 elink_bits_en(sc, emac_base + EMAC_REG_EMAC_TX_MODE,
1610 EMAC_TX_MODE_RESET);
1612 /* pause enable/disable */
1613 elink_bits_dis(sc, emac_base + EMAC_REG_EMAC_RX_MODE,
1614 EMAC_RX_MODE_FLOW_EN);
1616 elink_bits_dis(sc, emac_base + EMAC_REG_EMAC_TX_MODE,
1617 (EMAC_TX_MODE_EXT_PAUSE_EN |
1618 EMAC_TX_MODE_FLOW_EN));
1619 if (!(params->feature_config_flags &
1620 ELINK_FEATURE_CONFIG_PFC_ENABLED)) {
1621 if (vars->flow_ctrl & ELINK_FLOW_CTRL_RX)
1622 elink_bits_en(sc, emac_base +
1623 EMAC_REG_EMAC_RX_MODE,
1624 EMAC_RX_MODE_FLOW_EN);
1626 if (vars->flow_ctrl & ELINK_FLOW_CTRL_TX)
1627 elink_bits_en(sc, emac_base +
1628 EMAC_REG_EMAC_TX_MODE,
1629 (EMAC_TX_MODE_EXT_PAUSE_EN |
1630 EMAC_TX_MODE_FLOW_EN));
1632 elink_bits_en(sc, emac_base + EMAC_REG_EMAC_TX_MODE,
1633 EMAC_TX_MODE_FLOW_EN);
1635 /* KEEP_VLAN_TAG, promiscuous */
1636 val = REG_RD(sc, emac_base + EMAC_REG_EMAC_RX_MODE);
1637 val |= EMAC_RX_MODE_KEEP_VLAN_TAG | EMAC_RX_MODE_PROMISCUOUS;
1639 /* Setting this bit causes MAC control frames (except for pause
1640 * frames) to be passed on for processing. This setting has no
1641 * affect on the operation of the pause frames. This bit effects
1642 * all packets regardless of RX Parser packet sorting logic.
1643 * Turn the PFC off to make sure we are in Xon state before
1646 elink_cb_reg_write(sc, emac_base + EMAC_REG_RX_PFC_MODE, 0);
1647 if (params->feature_config_flags & ELINK_FEATURE_CONFIG_PFC_ENABLED) {
1648 PMD_DRV_LOG(DEBUG, sc, "PFC is enabled");
1649 /* Enable PFC again */
1650 elink_cb_reg_write(sc, emac_base + EMAC_REG_RX_PFC_MODE,
1651 EMAC_REG_RX_PFC_MODE_RX_EN |
1652 EMAC_REG_RX_PFC_MODE_TX_EN |
1653 EMAC_REG_RX_PFC_MODE_PRIORITIES);
1655 elink_cb_reg_write(sc, emac_base + EMAC_REG_RX_PFC_PARAM,
1657 EMAC_REG_RX_PFC_PARAM_OPCODE_BITSHIFT) |
1659 EMAC_REG_RX_PFC_PARAM_PRIORITY_EN_BITSHIFT)));
1660 val |= EMAC_RX_MODE_KEEP_MAC_CONTROL;
1662 elink_cb_reg_write(sc, emac_base + EMAC_REG_EMAC_RX_MODE, val);
1665 val = REG_RD(sc, emac_base + EMAC_REG_EMAC_MODE);
1670 elink_cb_reg_write(sc, emac_base + EMAC_REG_EMAC_MODE, val);
1673 REG_WR(sc, NIG_REG_NIG_EMAC0_EN + port * 4, 1);
1675 /* Enable emac for jumbo packets */
1676 elink_cb_reg_write(sc, emac_base + EMAC_REG_EMAC_RX_MTU_SIZE,
1677 (EMAC_RX_MTU_SIZE_JUMBO_ENA |
1678 (ELINK_ETH_MAX_JUMBO_PACKET_SIZE +
1679 ELINK_ETH_OVREHEAD)));
1682 REG_WR(sc, NIG_REG_NIG_INGRESS_EMAC0_NO_CRC + port * 4, 0x1);
1684 /* Disable the NIG in/out to the bmac */
1685 REG_WR(sc, NIG_REG_BMAC0_IN_EN + port * 4, 0x0);
1686 REG_WR(sc, NIG_REG_BMAC0_PAUSE_OUT_EN + port * 4, 0x0);
1687 REG_WR(sc, NIG_REG_BMAC0_OUT_EN + port * 4, 0x0);
1689 /* Enable the NIG in/out to the emac */
1690 REG_WR(sc, NIG_REG_EMAC0_IN_EN + port * 4, 0x1);
1692 if ((params->feature_config_flags &
1693 ELINK_FEATURE_CONFIG_PFC_ENABLED) ||
1694 (vars->flow_ctrl & ELINK_FLOW_CTRL_TX))
1697 REG_WR(sc, NIG_REG_EMAC0_PAUSE_OUT_EN + port * 4, val);
1698 REG_WR(sc, NIG_REG_EGRESS_EMAC0_OUT_EN + port * 4, 0x1);
1700 REG_WR(sc, NIG_REG_BMAC0_REGS_OUT_EN + port * 4, 0x0);
1702 vars->mac_type = ELINK_MAC_TYPE_EMAC;
1703 return ELINK_STATUS_OK;
1706 static void elink_update_pfc_bmac1(struct elink_params *params,
1707 struct elink_vars *vars)
1709 uint32_t wb_data[2];
1710 struct bnx2x_softc *sc = params->sc;
1711 uint32_t bmac_addr = params->port ? NIG_REG_INGRESS_BMAC1_MEM :
1712 NIG_REG_INGRESS_BMAC0_MEM;
1714 uint32_t val = 0x14;
1715 if ((!(params->feature_config_flags &
1716 ELINK_FEATURE_CONFIG_PFC_ENABLED)) &&
1717 (vars->flow_ctrl & ELINK_FLOW_CTRL_RX))
1718 /* Enable BigMAC to react on received Pause packets */
1722 REG_WR_DMAE(sc, bmac_addr + BIGMAC_REGISTER_RX_CONTROL, wb_data, 2);
1726 if (!(params->feature_config_flags &
1727 ELINK_FEATURE_CONFIG_PFC_ENABLED) &&
1728 (vars->flow_ctrl & ELINK_FLOW_CTRL_TX))
1732 REG_WR_DMAE(sc, bmac_addr + BIGMAC_REGISTER_TX_CONTROL, wb_data, 2);
1735 static void elink_update_pfc_bmac2(struct elink_params *params,
1736 struct elink_vars *vars, uint8_t is_lb)
1738 /* Set rx control: Strip CRC and enable BigMAC to relay
1739 * control packets to the system as well
1741 uint32_t wb_data[2];
1742 struct bnx2x_softc *sc = params->sc;
1743 uint32_t bmac_addr = params->port ? NIG_REG_INGRESS_BMAC1_MEM :
1744 NIG_REG_INGRESS_BMAC0_MEM;
1745 uint32_t val = 0x14;
1747 if ((!(params->feature_config_flags &
1748 ELINK_FEATURE_CONFIG_PFC_ENABLED)) &&
1749 (vars->flow_ctrl & ELINK_FLOW_CTRL_RX))
1750 /* Enable BigMAC to react on received Pause packets */
1754 REG_WR_DMAE(sc, bmac_addr + BIGMAC2_REGISTER_RX_CONTROL, wb_data, 2);
1759 if (!(params->feature_config_flags &
1760 ELINK_FEATURE_CONFIG_PFC_ENABLED) &&
1761 (vars->flow_ctrl & ELINK_FLOW_CTRL_TX))
1765 REG_WR_DMAE(sc, bmac_addr + BIGMAC2_REGISTER_TX_CONTROL, wb_data, 2);
1767 if (params->feature_config_flags & ELINK_FEATURE_CONFIG_PFC_ENABLED) {
1768 PMD_DRV_LOG(DEBUG, sc, "PFC is enabled");
1769 /* Enable PFC RX & TX & STATS and set 8 COS */
1771 wb_data[0] |= (1 << 0); /* RX */
1772 wb_data[0] |= (1 << 1); /* TX */
1773 wb_data[0] |= (1 << 2); /* Force initial Xon */
1774 wb_data[0] |= (1 << 3); /* 8 cos */
1775 wb_data[0] |= (1 << 5); /* STATS */
1777 REG_WR_DMAE(sc, bmac_addr + BIGMAC2_REGISTER_PFC_CONTROL,
1779 /* Clear the force Xon */
1780 wb_data[0] &= ~(1 << 2);
1782 PMD_DRV_LOG(DEBUG, sc, "PFC is disabled");
1783 /* Disable PFC RX & TX & STATS and set 8 COS */
1788 REG_WR_DMAE(sc, bmac_addr + BIGMAC2_REGISTER_PFC_CONTROL, wb_data, 2);
1790 /* Set Time (based unit is 512 bit time) between automatic
1791 * re-sending of PP packets amd enable automatic re-send of
1792 * Per-Priroity Packet as long as pp_gen is asserted and
1793 * pp_disable is low.
1796 if (params->feature_config_flags & ELINK_FEATURE_CONFIG_PFC_ENABLED)
1797 val |= (1 << 16); /* enable automatic re-send */
1801 REG_WR_DMAE(sc, bmac_addr + BIGMAC2_REGISTER_TX_PAUSE_CONTROL,
1805 val = 0x3; /* Enable RX and TX */
1807 val |= 0x4; /* Local loopback */
1808 PMD_DRV_LOG(DEBUG, sc, "enable bmac loopback");
1810 /* When PFC enabled, Pass pause frames towards the NIG. */
1811 if (params->feature_config_flags & ELINK_FEATURE_CONFIG_PFC_ENABLED)
1812 val |= ((1 << 6) | (1 << 5));
1816 REG_WR_DMAE(sc, bmac_addr + BIGMAC2_REGISTER_BMAC_CONTROL, wb_data, 2);
1819 /******************************************************************************
1821 * This function is needed because NIG ARB_CREDIT_WEIGHT_X are
1822 * not continues and ARB_CREDIT_WEIGHT_0 + offset is suitable.
1823 ******************************************************************************/
1824 static elink_status_t elink_pfc_nig_rx_priority_mask(struct bnx2x_softc *sc,
1826 uint32_t priority_mask,
1829 uint32_t nig_reg_rx_priority_mask_add = 0;
1831 switch (cos_entry) {
1833 nig_reg_rx_priority_mask_add = (port) ?
1834 NIG_REG_P1_RX_COS0_PRIORITY_MASK :
1835 NIG_REG_P0_RX_COS0_PRIORITY_MASK;
1838 nig_reg_rx_priority_mask_add = (port) ?
1839 NIG_REG_P1_RX_COS1_PRIORITY_MASK :
1840 NIG_REG_P0_RX_COS1_PRIORITY_MASK;
1843 nig_reg_rx_priority_mask_add = (port) ?
1844 NIG_REG_P1_RX_COS2_PRIORITY_MASK :
1845 NIG_REG_P0_RX_COS2_PRIORITY_MASK;
1849 return ELINK_STATUS_ERROR;
1850 nig_reg_rx_priority_mask_add = NIG_REG_P0_RX_COS3_PRIORITY_MASK;
1854 return ELINK_STATUS_ERROR;
1855 nig_reg_rx_priority_mask_add = NIG_REG_P0_RX_COS4_PRIORITY_MASK;
1859 return ELINK_STATUS_ERROR;
1860 nig_reg_rx_priority_mask_add = NIG_REG_P0_RX_COS5_PRIORITY_MASK;
1864 REG_WR(sc, nig_reg_rx_priority_mask_add, priority_mask);
1866 return ELINK_STATUS_OK;
1869 static void elink_update_mng(struct elink_params *params, uint32_t link_status)
1871 struct bnx2x_softc *sc = params->sc;
1873 REG_WR(sc, params->shmem_base +
1874 offsetof(struct shmem_region,
1875 port_mb[params->port].link_status), link_status);
1878 static void elink_update_link_attr(struct elink_params *params,
1881 struct bnx2x_softc *sc = params->sc;
1883 if (SHMEM2_HAS(sc, link_attr_sync))
1884 REG_WR(sc, params->shmem2_base +
1885 offsetof(struct shmem2_region,
1886 link_attr_sync[params->port]), link_attr);
1889 static void elink_update_pfc_nig(struct elink_params *params,
1890 struct elink_nig_brb_pfc_port_params
1893 uint32_t xcm_mask = 0, ppp_enable = 0, pause_enable = 0, llfc_out_en =
1895 uint32_t llfc_enable = 0, xcm_out_en = 0, hwpfc_enable = 0;
1896 uint32_t pkt_priority_to_cos = 0;
1897 struct bnx2x_softc *sc = params->sc;
1898 uint8_t port = params->port;
1900 int set_pfc = params->feature_config_flags &
1901 ELINK_FEATURE_CONFIG_PFC_ENABLED;
1902 PMD_DRV_LOG(DEBUG, sc, "updating pfc nig parameters");
1904 /* When NIG_LLH0_XCM_MASK_REG_LLHX_XCM_MASK_BCN bit is set
1905 * MAC control frames (that are not pause packets)
1906 * will be forwarded to the XCM.
1908 xcm_mask = REG_RD(sc, port ? NIG_REG_LLH1_XCM_MASK :
1909 NIG_REG_LLH0_XCM_MASK);
1910 /* NIG params will override non PFC params, since it's possible to
1911 * do transition from PFC to SAFC
1921 xcm_mask &= ~(port ? NIG_LLH1_XCM_MASK_REG_LLH1_XCM_MASK_BCN :
1922 NIG_LLH0_XCM_MASK_REG_LLH0_XCM_MASK_BCN);
1927 llfc_out_en = nig_params->llfc_out_en;
1928 llfc_enable = nig_params->llfc_enable;
1929 pause_enable = nig_params->pause_enable;
1930 } else /* Default non PFC mode - PAUSE */
1933 xcm_mask |= (port ? NIG_LLH1_XCM_MASK_REG_LLH1_XCM_MASK_BCN :
1934 NIG_LLH0_XCM_MASK_REG_LLH0_XCM_MASK_BCN);
1939 REG_WR(sc, port ? NIG_REG_BRB1_PAUSE_IN_EN :
1940 NIG_REG_BRB0_PAUSE_IN_EN, pause_enable);
1941 REG_WR(sc, port ? NIG_REG_LLFC_OUT_EN_1 :
1942 NIG_REG_LLFC_OUT_EN_0, llfc_out_en);
1943 REG_WR(sc, port ? NIG_REG_LLFC_ENABLE_1 :
1944 NIG_REG_LLFC_ENABLE_0, llfc_enable);
1945 REG_WR(sc, port ? NIG_REG_PAUSE_ENABLE_1 :
1946 NIG_REG_PAUSE_ENABLE_0, pause_enable);
1948 REG_WR(sc, port ? NIG_REG_PPP_ENABLE_1 :
1949 NIG_REG_PPP_ENABLE_0, ppp_enable);
1951 REG_WR(sc, port ? NIG_REG_LLH1_XCM_MASK :
1952 NIG_REG_LLH0_XCM_MASK, xcm_mask);
1954 REG_WR(sc, port ? NIG_REG_LLFC_EGRESS_SRC_ENABLE_1 :
1955 NIG_REG_LLFC_EGRESS_SRC_ENABLE_0, 0x7);
1957 /* Output enable for RX_XCM # IF */
1958 REG_WR(sc, port ? NIG_REG_XCM1_OUT_EN :
1959 NIG_REG_XCM0_OUT_EN, xcm_out_en);
1961 /* HW PFC TX enable */
1962 REG_WR(sc, port ? NIG_REG_P1_HWPFC_ENABLE :
1963 NIG_REG_P0_HWPFC_ENABLE, hwpfc_enable);
1967 pkt_priority_to_cos = nig_params->pkt_priority_to_cos;
1969 for (i = 0; i < nig_params->num_of_rx_cos_priority_mask; i++)
1970 elink_pfc_nig_rx_priority_mask(sc, i,
1972 rx_cos_priority_mask[i],
1975 REG_WR(sc, port ? NIG_REG_LLFC_HIGH_PRIORITY_CLASSES_1 :
1976 NIG_REG_LLFC_HIGH_PRIORITY_CLASSES_0,
1977 nig_params->llfc_high_priority_classes);
1979 REG_WR(sc, port ? NIG_REG_LLFC_LOW_PRIORITY_CLASSES_1 :
1980 NIG_REG_LLFC_LOW_PRIORITY_CLASSES_0,
1981 nig_params->llfc_low_priority_classes);
1983 REG_WR(sc, port ? NIG_REG_P1_PKT_PRIORITY_TO_COS :
1984 NIG_REG_P0_PKT_PRIORITY_TO_COS, pkt_priority_to_cos);
1987 elink_status_t elink_update_pfc(struct elink_params *params,
1988 struct elink_vars *vars,
1989 struct elink_nig_brb_pfc_port_params
1992 /* The PFC and pause are orthogonal to one another, meaning when
1993 * PFC is enabled, the pause are disabled, and when PFC is
1994 * disabled, pause are set according to the pause result.
1997 struct bnx2x_softc *sc = params->sc;
1998 elink_status_t elink_status = ELINK_STATUS_OK;
1999 uint8_t bmac_loopback = (params->loopback_mode == ELINK_LOOPBACK_BMAC);
2001 if (params->feature_config_flags & ELINK_FEATURE_CONFIG_PFC_ENABLED)
2002 vars->link_status |= LINK_STATUS_PFC_ENABLED;
2004 vars->link_status &= ~LINK_STATUS_PFC_ENABLED;
2006 elink_update_mng(params, vars->link_status);
2008 /* Update NIG params */
2009 elink_update_pfc_nig(params, pfc_params);
2012 return elink_status;
2014 PMD_DRV_LOG(DEBUG, sc, "About to update PFC in BMAC");
2016 if (CHIP_IS_E3(sc)) {
2017 if (vars->mac_type == ELINK_MAC_TYPE_XMAC)
2018 elink_update_pfc_xmac(params, vars);
2020 val = REG_RD(sc, MISC_REG_RESET_REG_2);
2022 (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << params->port))
2024 PMD_DRV_LOG(DEBUG, sc, "About to update PFC in EMAC");
2025 elink_emac_enable(params, vars, 0);
2026 return elink_status;
2029 elink_update_pfc_bmac2(params, vars, bmac_loopback);
2031 elink_update_pfc_bmac1(params, vars);
2034 if ((params->feature_config_flags &
2035 ELINK_FEATURE_CONFIG_PFC_ENABLED) ||
2036 (vars->flow_ctrl & ELINK_FLOW_CTRL_TX))
2038 REG_WR(sc, NIG_REG_BMAC0_PAUSE_OUT_EN + params->port * 4, val);
2040 return elink_status;
2043 static elink_status_t elink_bmac1_enable(struct elink_params *params,
2044 struct elink_vars *vars, uint8_t is_lb)
2046 struct bnx2x_softc *sc = params->sc;
2047 uint8_t port = params->port;
2048 uint32_t bmac_addr = port ? NIG_REG_INGRESS_BMAC1_MEM :
2049 NIG_REG_INGRESS_BMAC0_MEM;
2050 uint32_t wb_data[2];
2053 PMD_DRV_LOG(DEBUG, sc, "Enabling BigMAC1");
2058 REG_WR_DMAE(sc, bmac_addr + BIGMAC_REGISTER_BMAC_XGXS_CONTROL,
2062 wb_data[0] = ((params->mac_addr[2] << 24) |
2063 (params->mac_addr[3] << 16) |
2064 (params->mac_addr[4] << 8) | params->mac_addr[5]);
2065 wb_data[1] = ((params->mac_addr[0] << 8) | params->mac_addr[1]);
2066 REG_WR_DMAE(sc, bmac_addr + BIGMAC_REGISTER_TX_SOURCE_ADDR, wb_data, 2);
2072 PMD_DRV_LOG(DEBUG, sc, "enable bmac loopback");
2076 REG_WR_DMAE(sc, bmac_addr + BIGMAC_REGISTER_BMAC_CONTROL, wb_data, 2);
2079 wb_data[0] = ELINK_ETH_MAX_JUMBO_PACKET_SIZE + ELINK_ETH_OVREHEAD;
2081 REG_WR_DMAE(sc, bmac_addr + BIGMAC_REGISTER_RX_MAX_SIZE, wb_data, 2);
2083 elink_update_pfc_bmac1(params, vars);
2086 wb_data[0] = ELINK_ETH_MAX_JUMBO_PACKET_SIZE + ELINK_ETH_OVREHEAD;
2088 REG_WR_DMAE(sc, bmac_addr + BIGMAC_REGISTER_TX_MAX_SIZE, wb_data, 2);
2090 /* Set cnt max size */
2091 wb_data[0] = ELINK_ETH_MAX_JUMBO_PACKET_SIZE + ELINK_ETH_OVREHEAD;
2093 REG_WR_DMAE(sc, bmac_addr + BIGMAC_REGISTER_CNT_MAX_SIZE, wb_data, 2);
2095 /* Configure SAFC */
2096 wb_data[0] = 0x1000200;
2098 REG_WR_DMAE(sc, bmac_addr + BIGMAC_REGISTER_RX_LLFC_MSG_FLDS,
2101 return ELINK_STATUS_OK;
2104 static elink_status_t elink_bmac2_enable(struct elink_params *params,
2105 struct elink_vars *vars, uint8_t is_lb)
2107 struct bnx2x_softc *sc = params->sc;
2108 uint8_t port = params->port;
2109 uint32_t bmac_addr = port ? NIG_REG_INGRESS_BMAC1_MEM :
2110 NIG_REG_INGRESS_BMAC0_MEM;
2111 uint32_t wb_data[2];
2113 PMD_DRV_LOG(DEBUG, sc, "Enabling BigMAC2");
2117 REG_WR_DMAE(sc, bmac_addr + BIGMAC2_REGISTER_BMAC_CONTROL, wb_data, 2);
2120 /* XGXS control: Reset phy HW, MDIO registers, PHY PLL and BMAC */
2123 REG_WR_DMAE(sc, bmac_addr + BIGMAC2_REGISTER_BMAC_XGXS_CONTROL,
2129 wb_data[0] = ((params->mac_addr[2] << 24) |
2130 (params->mac_addr[3] << 16) |
2131 (params->mac_addr[4] << 8) | params->mac_addr[5]);
2132 wb_data[1] = ((params->mac_addr[0] << 8) | params->mac_addr[1]);
2133 REG_WR_DMAE(sc, bmac_addr + BIGMAC2_REGISTER_TX_SOURCE_ADDR,
2138 /* Configure SAFC */
2139 wb_data[0] = 0x1000200;
2141 REG_WR_DMAE(sc, bmac_addr + BIGMAC2_REGISTER_RX_LLFC_MSG_FLDS,
2146 wb_data[0] = ELINK_ETH_MAX_JUMBO_PACKET_SIZE + ELINK_ETH_OVREHEAD;
2148 REG_WR_DMAE(sc, bmac_addr + BIGMAC2_REGISTER_RX_MAX_SIZE, wb_data, 2);
2152 wb_data[0] = ELINK_ETH_MAX_JUMBO_PACKET_SIZE + ELINK_ETH_OVREHEAD;
2154 REG_WR_DMAE(sc, bmac_addr + BIGMAC2_REGISTER_TX_MAX_SIZE, wb_data, 2);
2156 /* Set cnt max size */
2157 wb_data[0] = ELINK_ETH_MAX_JUMBO_PACKET_SIZE + ELINK_ETH_OVREHEAD - 2;
2159 REG_WR_DMAE(sc, bmac_addr + BIGMAC2_REGISTER_CNT_MAX_SIZE, wb_data, 2);
2161 elink_update_pfc_bmac2(params, vars, is_lb);
2163 return ELINK_STATUS_OK;
2166 static elink_status_t elink_bmac_enable(struct elink_params *params,
2167 struct elink_vars *vars,
2168 uint8_t is_lb, uint8_t reset_bmac)
2170 elink_status_t rc = ELINK_STATUS_OK;
2171 uint8_t port = params->port;
2172 struct bnx2x_softc *sc = params->sc;
2174 /* Reset and unreset the BigMac */
2176 REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
2177 (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port));
2181 REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,
2182 (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port));
2184 /* Enable access for bmac registers */
2185 REG_WR(sc, NIG_REG_BMAC0_REGS_OUT_EN + port * 4, 0x1);
2187 /* Enable BMAC according to BMAC type */
2189 rc = elink_bmac2_enable(params, vars, is_lb);
2191 rc = elink_bmac1_enable(params, vars, is_lb);
2192 REG_WR(sc, NIG_REG_XGXS_SERDES0_MODE_SEL + port * 4, 0x1);
2193 REG_WR(sc, NIG_REG_XGXS_LANE_SEL_P0 + port * 4, 0x0);
2194 REG_WR(sc, NIG_REG_EGRESS_EMAC0_PORT + port * 4, 0x0);
2196 if ((params->feature_config_flags &
2197 ELINK_FEATURE_CONFIG_PFC_ENABLED) ||
2198 (vars->flow_ctrl & ELINK_FLOW_CTRL_TX))
2200 REG_WR(sc, NIG_REG_BMAC0_PAUSE_OUT_EN + port * 4, val);
2201 REG_WR(sc, NIG_REG_EGRESS_EMAC0_OUT_EN + port * 4, 0x0);
2202 REG_WR(sc, NIG_REG_EMAC0_IN_EN + port * 4, 0x0);
2203 REG_WR(sc, NIG_REG_EMAC0_PAUSE_OUT_EN + port * 4, 0x0);
2204 REG_WR(sc, NIG_REG_BMAC0_IN_EN + port * 4, 0x1);
2205 REG_WR(sc, NIG_REG_BMAC0_OUT_EN + port * 4, 0x1);
2207 vars->mac_type = ELINK_MAC_TYPE_BMAC;
2211 static void elink_set_bmac_rx(struct bnx2x_softc *sc, uint8_t port, uint8_t en)
2213 uint32_t bmac_addr = port ? NIG_REG_INGRESS_BMAC1_MEM :
2214 NIG_REG_INGRESS_BMAC0_MEM;
2215 uint32_t wb_data[2];
2216 uint32_t nig_bmac_enable =
2217 REG_RD(sc, NIG_REG_BMAC0_REGS_OUT_EN + port * 4);
2220 bmac_addr += BIGMAC2_REGISTER_BMAC_CONTROL;
2222 bmac_addr += BIGMAC_REGISTER_BMAC_CONTROL;
2223 /* Only if the bmac is out of reset */
2224 if (REG_RD(sc, MISC_REG_RESET_REG_2) &
2225 (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port) && nig_bmac_enable) {
2226 /* Clear Rx Enable bit in BMAC_CONTROL register */
2227 REG_RD_DMAE(sc, bmac_addr, wb_data, 2);
2229 wb_data[0] |= ELINK_BMAC_CONTROL_RX_ENABLE;
2231 wb_data[0] &= ~ELINK_BMAC_CONTROL_RX_ENABLE;
2232 REG_WR_DMAE(sc, bmac_addr, wb_data, 2);
2237 static elink_status_t elink_pbf_update(struct elink_params *params,
2238 uint32_t flow_ctrl, uint32_t line_speed)
2240 struct bnx2x_softc *sc = params->sc;
2241 uint8_t port = params->port;
2242 uint32_t init_crd, crd;
2243 uint32_t count = 1000;
2246 REG_WR(sc, PBF_REG_DISABLE_NEW_TASK_PROC_P0 + port * 4, 0x1);
2248 /* Wait for init credit */
2249 init_crd = REG_RD(sc, PBF_REG_P0_INIT_CRD + port * 4);
2250 crd = REG_RD(sc, PBF_REG_P0_CREDIT + port * 8);
2251 PMD_DRV_LOG(DEBUG, sc, "init_crd 0x%x crd 0x%x", init_crd, crd);
2253 while ((init_crd != crd) && count) {
2255 crd = REG_RD(sc, PBF_REG_P0_CREDIT + port * 8);
2258 crd = REG_RD(sc, PBF_REG_P0_CREDIT + port * 8);
2259 if (init_crd != crd) {
2260 PMD_DRV_LOG(DEBUG, sc, "BUG! init_crd 0x%x != crd 0x%x",
2262 return ELINK_STATUS_ERROR;
2265 if (flow_ctrl & ELINK_FLOW_CTRL_RX ||
2266 line_speed == ELINK_SPEED_10 ||
2267 line_speed == ELINK_SPEED_100 ||
2268 line_speed == ELINK_SPEED_1000 || line_speed == ELINK_SPEED_2500) {
2269 REG_WR(sc, PBF_REG_P0_PAUSE_ENABLE + port * 4, 1);
2270 /* Update threshold */
2271 REG_WR(sc, PBF_REG_P0_ARB_THRSH + port * 4, 0);
2272 /* Update init credit */
2273 init_crd = 778; /* (800-18-4) */
2276 uint32_t thresh = (ELINK_ETH_MAX_JUMBO_PACKET_SIZE +
2277 ELINK_ETH_OVREHEAD) / 16;
2278 REG_WR(sc, PBF_REG_P0_PAUSE_ENABLE + port * 4, 0);
2279 /* Update threshold */
2280 REG_WR(sc, PBF_REG_P0_ARB_THRSH + port * 4, thresh);
2281 /* Update init credit */
2282 switch (line_speed) {
2283 case ELINK_SPEED_10000:
2284 init_crd = thresh + 553 - 22;
2287 PMD_DRV_LOG(DEBUG, sc, "Invalid line_speed 0x%x",
2289 return ELINK_STATUS_ERROR;
2292 REG_WR(sc, PBF_REG_P0_INIT_CRD + port * 4, init_crd);
2293 PMD_DRV_LOG(DEBUG, sc, "PBF updated to speed %d credit %d",
2294 line_speed, init_crd);
2296 /* Probe the credit changes */
2297 REG_WR(sc, PBF_REG_INIT_P0 + port * 4, 0x1);
2299 REG_WR(sc, PBF_REG_INIT_P0 + port * 4, 0x0);
2302 REG_WR(sc, PBF_REG_DISABLE_NEW_TASK_PROC_P0 + port * 4, 0x0);
2303 return ELINK_STATUS_OK;
2307 * elink_get_emac_base - retrive emac base address
2309 * @bp: driver handle
2310 * @mdc_mdio_access: access type
2313 * This function selects the MDC/MDIO access (through emac0 or
2314 * emac1) depend on the mdc_mdio_access, port, port swapped. Each
2315 * phy has a default access mode, which could also be overridden
2316 * by nvram configuration. This parameter, whether this is the
2317 * default phy configuration, or the nvram overrun
2318 * configuration, is passed here as mdc_mdio_access and selects
2319 * the emac_base for the CL45 read/writes operations
2321 static uint32_t elink_get_emac_base(struct bnx2x_softc *sc,
2322 uint32_t mdc_mdio_access, uint8_t port)
2324 uint32_t emac_base = 0;
2325 switch (mdc_mdio_access) {
2326 case SHARED_HW_CFG_MDC_MDIO_ACCESS1_PHY_TYPE:
2328 case SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC0:
2329 if (REG_RD(sc, NIG_REG_PORT_SWAP))
2330 emac_base = GRCBASE_EMAC1;
2332 emac_base = GRCBASE_EMAC0;
2334 case SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC1:
2335 if (REG_RD(sc, NIG_REG_PORT_SWAP))
2336 emac_base = GRCBASE_EMAC0;
2338 emac_base = GRCBASE_EMAC1;
2340 case SHARED_HW_CFG_MDC_MDIO_ACCESS1_BOTH:
2341 emac_base = (port) ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
2343 case SHARED_HW_CFG_MDC_MDIO_ACCESS1_SWAPPED:
2344 emac_base = (port) ? GRCBASE_EMAC0 : GRCBASE_EMAC1;
2353 /******************************************************************/
2354 /* CL22 access functions */
2355 /******************************************************************/
2356 static elink_status_t elink_cl22_write(struct bnx2x_softc *sc,
2357 struct elink_phy *phy,
2358 uint16_t reg, uint16_t val)
2362 elink_status_t rc = ELINK_STATUS_OK;
2363 /* Switch to CL22 */
2364 mode = REG_RD(sc, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE);
2365 REG_WR(sc, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE,
2366 mode & ~EMAC_MDIO_MODE_CLAUSE_45);
2369 tmp = ((phy->addr << 21) | (reg << 16) | val |
2370 EMAC_MDIO_COMM_COMMAND_WRITE_22 | EMAC_MDIO_COMM_START_BUSY);
2371 REG_WR(sc, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, tmp);
2373 for (i = 0; i < 50; i++) {
2376 tmp = REG_RD(sc, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM);
2377 if (!(tmp & EMAC_MDIO_COMM_START_BUSY)) {
2382 if (tmp & EMAC_MDIO_COMM_START_BUSY) {
2383 PMD_DRV_LOG(DEBUG, sc, "write phy register failed");
2384 rc = ELINK_STATUS_TIMEOUT;
2386 REG_WR(sc, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE, mode);
2390 static elink_status_t elink_cl22_read(struct bnx2x_softc *sc,
2391 struct elink_phy *phy,
2392 uint16_t reg, uint16_t * ret_val)
2396 elink_status_t rc = ELINK_STATUS_OK;
2398 /* Switch to CL22 */
2399 mode = REG_RD(sc, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE);
2400 REG_WR(sc, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE,
2401 mode & ~EMAC_MDIO_MODE_CLAUSE_45);
2404 val = ((phy->addr << 21) | (reg << 16) |
2405 EMAC_MDIO_COMM_COMMAND_READ_22 | EMAC_MDIO_COMM_START_BUSY);
2406 REG_WR(sc, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, val);
2408 for (i = 0; i < 50; i++) {
2411 val = REG_RD(sc, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM);
2412 if (!(val & EMAC_MDIO_COMM_START_BUSY)) {
2413 *ret_val = (uint16_t) (val & EMAC_MDIO_COMM_DATA);
2418 if (val & EMAC_MDIO_COMM_START_BUSY) {
2419 PMD_DRV_LOG(DEBUG, sc, "read phy register failed");
2422 rc = ELINK_STATUS_TIMEOUT;
2424 REG_WR(sc, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE, mode);
2428 /******************************************************************/
2429 /* CL45 access functions */
2430 /******************************************************************/
2431 static elink_status_t elink_cl45_read(struct bnx2x_softc *sc,
2432 struct elink_phy *phy, uint8_t devad,
2433 uint16_t reg, uint16_t * ret_val)
2437 elink_status_t rc = ELINK_STATUS_OK;
2438 if (phy->flags & ELINK_FLAGS_MDC_MDIO_WA_G) {
2439 elink_set_mdio_clk(sc, phy->mdio_ctrl);
2442 if (phy->flags & ELINK_FLAGS_MDC_MDIO_WA_B0)
2443 elink_bits_en(sc, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_STATUS,
2444 EMAC_MDIO_STATUS_10MB);
2446 val = ((phy->addr << 21) | (devad << 16) | reg |
2447 EMAC_MDIO_COMM_COMMAND_ADDRESS | EMAC_MDIO_COMM_START_BUSY);
2448 REG_WR(sc, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, val);
2450 for (i = 0; i < 50; i++) {
2453 val = REG_RD(sc, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM);
2454 if (!(val & EMAC_MDIO_COMM_START_BUSY)) {
2459 if (val & EMAC_MDIO_COMM_START_BUSY) {
2460 PMD_DRV_LOG(DEBUG, sc, "read phy register failed");
2461 elink_cb_event_log(sc, ELINK_LOG_ID_MDIO_ACCESS_TIMEOUT); // "MDC/MDIO access timeout"
2464 rc = ELINK_STATUS_TIMEOUT;
2467 val = ((phy->addr << 21) | (devad << 16) |
2468 EMAC_MDIO_COMM_COMMAND_READ_45 |
2469 EMAC_MDIO_COMM_START_BUSY);
2470 REG_WR(sc, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, val);
2472 for (i = 0; i < 50; i++) {
2475 val = REG_RD(sc, phy->mdio_ctrl +
2476 EMAC_REG_EMAC_MDIO_COMM);
2477 if (!(val & EMAC_MDIO_COMM_START_BUSY)) {
2479 (uint16_t) (val & EMAC_MDIO_COMM_DATA);
2483 if (val & EMAC_MDIO_COMM_START_BUSY) {
2484 PMD_DRV_LOG(DEBUG, sc, "read phy register failed");
2485 elink_cb_event_log(sc, ELINK_LOG_ID_MDIO_ACCESS_TIMEOUT); // "MDC/MDIO access timeout"
2488 rc = ELINK_STATUS_TIMEOUT;
2491 /* Work around for E3 A0 */
2492 if (phy->flags & ELINK_FLAGS_MDC_MDIO_WA) {
2493 phy->flags ^= ELINK_FLAGS_DUMMY_READ;
2494 if (phy->flags & ELINK_FLAGS_DUMMY_READ) {
2496 elink_cl45_read(sc, phy, devad, 0xf, &temp_val);
2500 if (phy->flags & ELINK_FLAGS_MDC_MDIO_WA_B0)
2501 elink_bits_dis(sc, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_STATUS,
2502 EMAC_MDIO_STATUS_10MB);
2506 static elink_status_t elink_cl45_write(struct bnx2x_softc *sc,
2507 struct elink_phy *phy, uint8_t devad,
2508 uint16_t reg, uint16_t val)
2512 elink_status_t rc = ELINK_STATUS_OK;
2513 if (phy->flags & ELINK_FLAGS_MDC_MDIO_WA_G) {
2514 elink_set_mdio_clk(sc, phy->mdio_ctrl);
2517 if (phy->flags & ELINK_FLAGS_MDC_MDIO_WA_B0)
2518 elink_bits_en(sc, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_STATUS,
2519 EMAC_MDIO_STATUS_10MB);
2522 tmp = ((phy->addr << 21) | (devad << 16) | reg |
2523 EMAC_MDIO_COMM_COMMAND_ADDRESS | EMAC_MDIO_COMM_START_BUSY);
2524 REG_WR(sc, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, tmp);
2526 for (i = 0; i < 50; i++) {
2529 tmp = REG_RD(sc, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM);
2530 if (!(tmp & EMAC_MDIO_COMM_START_BUSY)) {
2535 if (tmp & EMAC_MDIO_COMM_START_BUSY) {
2536 PMD_DRV_LOG(DEBUG, sc, "write phy register failed");
2537 elink_cb_event_log(sc, ELINK_LOG_ID_MDIO_ACCESS_TIMEOUT); // "MDC/MDIO access timeout"
2539 rc = ELINK_STATUS_TIMEOUT;
2542 tmp = ((phy->addr << 21) | (devad << 16) | val |
2543 EMAC_MDIO_COMM_COMMAND_WRITE_45 |
2544 EMAC_MDIO_COMM_START_BUSY);
2545 REG_WR(sc, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, tmp);
2547 for (i = 0; i < 50; i++) {
2550 tmp = REG_RD(sc, phy->mdio_ctrl +
2551 EMAC_REG_EMAC_MDIO_COMM);
2552 if (!(tmp & EMAC_MDIO_COMM_START_BUSY)) {
2557 if (tmp & EMAC_MDIO_COMM_START_BUSY) {
2558 PMD_DRV_LOG(DEBUG, sc, "write phy register failed");
2559 elink_cb_event_log(sc, ELINK_LOG_ID_MDIO_ACCESS_TIMEOUT); // "MDC/MDIO access timeout"
2561 rc = ELINK_STATUS_TIMEOUT;
2564 /* Work around for E3 A0 */
2565 if (phy->flags & ELINK_FLAGS_MDC_MDIO_WA) {
2566 phy->flags ^= ELINK_FLAGS_DUMMY_READ;
2567 if (phy->flags & ELINK_FLAGS_DUMMY_READ) {
2569 elink_cl45_read(sc, phy, devad, 0xf, &temp_val);
2572 if (phy->flags & ELINK_FLAGS_MDC_MDIO_WA_B0)
2573 elink_bits_dis(sc, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_STATUS,
2574 EMAC_MDIO_STATUS_10MB);
2578 /******************************************************************/
2580 /******************************************************************/
2581 static uint8_t elink_eee_has_cap(struct elink_params *params)
2583 struct bnx2x_softc *sc = params->sc;
2585 if (REG_RD(sc, params->shmem2_base) <=
2586 offsetof(struct shmem2_region, eee_status[params->port]))
2592 static elink_status_t elink_eee_nvram_to_time(uint32_t nvram_mode,
2593 uint32_t * idle_timer)
2595 switch (nvram_mode) {
2596 case PORT_FEAT_CFG_EEE_POWER_MODE_BALANCED:
2597 *idle_timer = ELINK_EEE_MODE_NVRAM_BALANCED_TIME;
2599 case PORT_FEAT_CFG_EEE_POWER_MODE_AGGRESSIVE:
2600 *idle_timer = ELINK_EEE_MODE_NVRAM_AGGRESSIVE_TIME;
2602 case PORT_FEAT_CFG_EEE_POWER_MODE_LOW_LATENCY:
2603 *idle_timer = ELINK_EEE_MODE_NVRAM_LATENCY_TIME;
2610 return ELINK_STATUS_OK;
2613 static elink_status_t elink_eee_time_to_nvram(uint32_t idle_timer,
2614 uint32_t * nvram_mode)
2616 switch (idle_timer) {
2617 case ELINK_EEE_MODE_NVRAM_BALANCED_TIME:
2618 *nvram_mode = PORT_FEAT_CFG_EEE_POWER_MODE_BALANCED;
2620 case ELINK_EEE_MODE_NVRAM_AGGRESSIVE_TIME:
2621 *nvram_mode = PORT_FEAT_CFG_EEE_POWER_MODE_AGGRESSIVE;
2623 case ELINK_EEE_MODE_NVRAM_LATENCY_TIME:
2624 *nvram_mode = PORT_FEAT_CFG_EEE_POWER_MODE_LOW_LATENCY;
2627 *nvram_mode = PORT_FEAT_CFG_EEE_POWER_MODE_DISABLED;
2631 return ELINK_STATUS_OK;
2634 static uint32_t elink_eee_calc_timer(struct elink_params *params)
2636 uint32_t eee_mode, eee_idle;
2637 struct bnx2x_softc *sc = params->sc;
2639 if (params->eee_mode & ELINK_EEE_MODE_OVERRIDE_NVRAM) {
2640 if (params->eee_mode & ELINK_EEE_MODE_OUTPUT_TIME) {
2641 /* time value in eee_mode --> used directly */
2642 eee_idle = params->eee_mode & ELINK_EEE_MODE_TIMER_MASK;
2644 /* hsi value in eee_mode --> time */
2645 if (elink_eee_nvram_to_time(params->eee_mode &
2646 ELINK_EEE_MODE_NVRAM_MASK,
2651 /* hsi values in nvram --> time */
2652 eee_mode = ((REG_RD(sc, params->shmem_base +
2653 offsetof(struct shmem_region,
2654 dev_info.port_feature_config
2656 port].eee_power_mode)) &
2657 PORT_FEAT_CFG_EEE_POWER_MODE_MASK) >>
2658 PORT_FEAT_CFG_EEE_POWER_MODE_SHIFT);
2660 if (elink_eee_nvram_to_time(eee_mode, &eee_idle))
2667 static elink_status_t elink_eee_set_timers(struct elink_params *params,
2668 struct elink_vars *vars)
2670 uint32_t eee_idle = 0, eee_mode;
2671 struct bnx2x_softc *sc = params->sc;
2673 eee_idle = elink_eee_calc_timer(params);
2676 REG_WR(sc, MISC_REG_CPMU_LP_IDLE_THR_P0 + (params->port << 2),
2678 } else if ((params->eee_mode & ELINK_EEE_MODE_ENABLE_LPI) &&
2679 (params->eee_mode & ELINK_EEE_MODE_OVERRIDE_NVRAM) &&
2680 (params->eee_mode & ELINK_EEE_MODE_OUTPUT_TIME)) {
2681 PMD_DRV_LOG(DEBUG, sc, "Error: Tx LPI is enabled with timer 0");
2682 return ELINK_STATUS_ERROR;
2685 vars->eee_status &= ~(SHMEM_EEE_TIMER_MASK | SHMEM_EEE_TIME_OUTPUT_BIT);
2686 if (params->eee_mode & ELINK_EEE_MODE_OUTPUT_TIME) {
2687 /* eee_idle in 1u --> eee_status in 16u */
2689 vars->eee_status |= (eee_idle & SHMEM_EEE_TIMER_MASK) |
2690 SHMEM_EEE_TIME_OUTPUT_BIT;
2692 if (elink_eee_time_to_nvram(eee_idle, &eee_mode))
2693 return ELINK_STATUS_ERROR;
2694 vars->eee_status |= eee_mode;
2697 return ELINK_STATUS_OK;
2700 static elink_status_t elink_eee_initial_config(struct elink_params *params,
2701 struct elink_vars *vars,
2704 vars->eee_status |= ((uint32_t) mode) << SHMEM_EEE_SUPPORTED_SHIFT;
2706 /* Propogate params' bits --> vars (for migration exposure) */
2707 if (params->eee_mode & ELINK_EEE_MODE_ENABLE_LPI)
2708 vars->eee_status |= SHMEM_EEE_LPI_REQUESTED_BIT;
2710 vars->eee_status &= ~SHMEM_EEE_LPI_REQUESTED_BIT;
2712 if (params->eee_mode & ELINK_EEE_MODE_ADV_LPI)
2713 vars->eee_status |= SHMEM_EEE_REQUESTED_BIT;
2715 vars->eee_status &= ~SHMEM_EEE_REQUESTED_BIT;
2717 return elink_eee_set_timers(params, vars);
2720 static elink_status_t elink_eee_disable(struct elink_phy *phy,
2721 struct elink_params *params,
2722 struct elink_vars *vars)
2724 struct bnx2x_softc *sc = params->sc;
2726 /* Make Certain LPI is disabled */
2727 REG_WR(sc, MISC_REG_CPMU_LP_FW_ENABLE_P0 + (params->port << 2), 0);
2729 elink_cl45_write(sc, phy, MDIO_AN_DEVAD, MDIO_AN_REG_EEE_ADV, 0x0);
2731 vars->eee_status &= ~SHMEM_EEE_ADV_STATUS_MASK;
2733 return ELINK_STATUS_OK;
2736 static elink_status_t elink_eee_advertise(struct elink_phy *phy,
2737 struct elink_params *params,
2738 struct elink_vars *vars,
2741 struct bnx2x_softc *sc = params->sc;
2744 /* Mask events preventing LPI generation */
2745 REG_WR(sc, MISC_REG_CPMU_LP_MASK_EXT_P0 + (params->port << 2), 0xfc20);
2747 if (modes & SHMEM_EEE_10G_ADV) {
2748 PMD_DRV_LOG(DEBUG, sc, "Advertise 10GBase-T EEE");
2751 if (modes & SHMEM_EEE_1G_ADV) {
2752 PMD_DRV_LOG(DEBUG, sc, "Advertise 1GBase-T EEE");
2756 elink_cl45_write(sc, phy, MDIO_AN_DEVAD, MDIO_AN_REG_EEE_ADV, val);
2758 vars->eee_status &= ~SHMEM_EEE_ADV_STATUS_MASK;
2759 vars->eee_status |= (modes << SHMEM_EEE_ADV_STATUS_SHIFT);
2761 return ELINK_STATUS_OK;
2764 static void elink_update_mng_eee(struct elink_params *params,
2765 uint32_t eee_status)
2767 struct bnx2x_softc *sc = params->sc;
2769 if (elink_eee_has_cap(params))
2770 REG_WR(sc, params->shmem2_base +
2771 offsetof(struct shmem2_region,
2772 eee_status[params->port]), eee_status);
2775 static void elink_eee_an_resolve(struct elink_phy *phy,
2776 struct elink_params *params,
2777 struct elink_vars *vars)
2779 struct bnx2x_softc *sc = params->sc;
2780 uint16_t adv = 0, lp = 0;
2781 uint32_t lp_adv = 0;
2784 elink_cl45_read(sc, phy, MDIO_AN_DEVAD, MDIO_AN_REG_EEE_ADV, &adv);
2785 elink_cl45_read(sc, phy, MDIO_AN_DEVAD, MDIO_AN_REG_LP_EEE_ADV, &lp);
2788 lp_adv |= SHMEM_EEE_100M_ADV;
2790 if (vars->line_speed == ELINK_SPEED_100)
2792 PMD_DRV_LOG(DEBUG, sc, "EEE negotiated - 100M");
2796 lp_adv |= SHMEM_EEE_1G_ADV;
2798 if (vars->line_speed == ELINK_SPEED_1000)
2800 PMD_DRV_LOG(DEBUG, sc, "EEE negotiated - 1G");
2804 lp_adv |= SHMEM_EEE_10G_ADV;
2806 if (vars->line_speed == ELINK_SPEED_10000)
2808 PMD_DRV_LOG(DEBUG, sc, "EEE negotiated - 10G");
2812 vars->eee_status &= ~SHMEM_EEE_LP_ADV_STATUS_MASK;
2813 vars->eee_status |= (lp_adv << SHMEM_EEE_LP_ADV_STATUS_SHIFT);
2816 PMD_DRV_LOG(DEBUG, sc, "EEE is active");
2817 vars->eee_status |= SHMEM_EEE_ACTIVE_BIT;
2821 /******************************************************************/
2822 /* BSC access functions from E3 */
2823 /******************************************************************/
2824 static void elink_bsc_module_sel(struct elink_params *params)
2827 uint32_t board_cfg, sfp_ctrl;
2828 uint32_t i2c_pins[I2C_SWITCH_WIDTH], i2c_val[I2C_SWITCH_WIDTH];
2829 struct bnx2x_softc *sc = params->sc;
2830 uint8_t port = params->port;
2831 /* Read I2C output PINs */
2832 board_cfg = REG_RD(sc, params->shmem_base +
2833 offsetof(struct shmem_region,
2834 dev_info.shared_hw_config.board));
2835 i2c_pins[I2C_BSC0] = board_cfg & SHARED_HW_CFG_E3_I2C_MUX0_MASK;
2836 i2c_pins[I2C_BSC1] = (board_cfg & SHARED_HW_CFG_E3_I2C_MUX1_MASK) >>
2837 SHARED_HW_CFG_E3_I2C_MUX1_SHIFT;
2839 /* Read I2C output value */
2840 sfp_ctrl = REG_RD(sc, params->shmem_base +
2841 offsetof(struct shmem_region,
2842 dev_info.port_hw_config[port].
2844 i2c_val[I2C_BSC0] = (sfp_ctrl & PORT_HW_CFG_E3_I2C_MUX0_MASK) > 0;
2845 i2c_val[I2C_BSC1] = (sfp_ctrl & PORT_HW_CFG_E3_I2C_MUX1_MASK) > 0;
2846 PMD_DRV_LOG(DEBUG, sc, "Setting BSC switch");
2847 for (idx = 0; idx < I2C_SWITCH_WIDTH; idx++)
2848 elink_set_cfg_pin(sc, i2c_pins[idx], i2c_val[idx]);
2851 static elink_status_t elink_bsc_read(struct elink_params *params,
2852 struct bnx2x_softc *sc,
2856 uint8_t xfer_cnt, uint32_t * data_array)
2859 elink_status_t rc = ELINK_STATUS_OK;
2861 if (xfer_cnt > 16) {
2862 PMD_DRV_LOG(DEBUG, sc, "invalid xfer_cnt %d. Max is 16 bytes",
2864 return ELINK_STATUS_ERROR;
2867 elink_bsc_module_sel(params);
2869 xfer_cnt = 16 - lc_addr;
2871 /* Enable the engine */
2872 val = REG_RD(sc, MCP_REG_MCPR_IMC_COMMAND);
2873 val |= MCPR_IMC_COMMAND_ENABLE;
2874 REG_WR(sc, MCP_REG_MCPR_IMC_COMMAND, val);
2876 /* Program slave device ID */
2877 val = (sl_devid << 16) | sl_addr;
2878 REG_WR(sc, MCP_REG_MCPR_IMC_SLAVE_CONTROL, val);
2880 /* Start xfer with 0 byte to update the address pointer ??? */
2881 val = (MCPR_IMC_COMMAND_ENABLE) |
2882 (MCPR_IMC_COMMAND_WRITE_OP <<
2883 MCPR_IMC_COMMAND_OPERATION_BITSHIFT) |
2884 (lc_addr << MCPR_IMC_COMMAND_TRANSFER_ADDRESS_BITSHIFT) | (0);
2885 REG_WR(sc, MCP_REG_MCPR_IMC_COMMAND, val);
2887 /* Poll for completion */
2889 val = REG_RD(sc, MCP_REG_MCPR_IMC_COMMAND);
2890 while (((val >> MCPR_IMC_COMMAND_IMC_STATUS_BITSHIFT) & 0x3) != 1) {
2892 val = REG_RD(sc, MCP_REG_MCPR_IMC_COMMAND);
2894 PMD_DRV_LOG(DEBUG, sc, "wr 0 byte timed out after %d try",
2896 rc = ELINK_STATUS_TIMEOUT;
2900 if (rc == ELINK_STATUS_TIMEOUT)
2903 /* Start xfer with read op */
2904 val = (MCPR_IMC_COMMAND_ENABLE) |
2905 (MCPR_IMC_COMMAND_READ_OP <<
2906 MCPR_IMC_COMMAND_OPERATION_BITSHIFT) |
2907 (lc_addr << MCPR_IMC_COMMAND_TRANSFER_ADDRESS_BITSHIFT) |
2909 REG_WR(sc, MCP_REG_MCPR_IMC_COMMAND, val);
2911 /* Poll for completion */
2913 val = REG_RD(sc, MCP_REG_MCPR_IMC_COMMAND);
2914 while (((val >> MCPR_IMC_COMMAND_IMC_STATUS_BITSHIFT) & 0x3) != 1) {
2916 val = REG_RD(sc, MCP_REG_MCPR_IMC_COMMAND);
2918 PMD_DRV_LOG(DEBUG, sc,
2919 "rd op timed out after %d try", i);
2920 rc = ELINK_STATUS_TIMEOUT;
2924 if (rc == ELINK_STATUS_TIMEOUT)
2927 for (i = (lc_addr >> 2); i < 4; i++) {
2928 data_array[i] = REG_RD(sc, (MCP_REG_MCPR_IMC_DATAREG0 + i * 4));
2930 data_array[i] = ((data_array[i] & 0x000000ff) << 24) |
2931 ((data_array[i] & 0x0000ff00) << 8) |
2932 ((data_array[i] & 0x00ff0000) >> 8) |
2933 ((data_array[i] & 0xff000000) >> 24);
2939 static void elink_cl45_read_or_write(struct bnx2x_softc *sc,
2940 struct elink_phy *phy, uint8_t devad,
2941 uint16_t reg, uint16_t or_val)
2944 elink_cl45_read(sc, phy, devad, reg, &val);
2945 elink_cl45_write(sc, phy, devad, reg, val | or_val);
2948 static void elink_cl45_read_and_write(struct bnx2x_softc *sc,
2949 struct elink_phy *phy,
2950 uint8_t devad, uint16_t reg,
2954 elink_cl45_read(sc, phy, devad, reg, &val);
2955 elink_cl45_write(sc, phy, devad, reg, val & and_val);
2958 static uint8_t elink_get_warpcore_lane(struct elink_params *params)
2961 struct bnx2x_softc *sc = params->sc;
2962 uint32_t path_swap, path_swap_ovr;
2966 port = params->port;
2968 if (elink_is_4_port_mode(sc)) {
2969 uint32_t port_swap, port_swap_ovr;
2971 /* Figure out path swap value */
2972 path_swap_ovr = REG_RD(sc, MISC_REG_FOUR_PORT_PATH_SWAP_OVWR);
2973 if (path_swap_ovr & 0x1)
2974 path_swap = (path_swap_ovr & 0x2);
2976 path_swap = REG_RD(sc, MISC_REG_FOUR_PORT_PATH_SWAP);
2981 /* Figure out port swap value */
2982 port_swap_ovr = REG_RD(sc, MISC_REG_FOUR_PORT_PORT_SWAP_OVWR);
2983 if (port_swap_ovr & 0x1)
2984 port_swap = (port_swap_ovr & 0x2);
2986 port_swap = REG_RD(sc, MISC_REG_FOUR_PORT_PORT_SWAP);
2991 lane = (port << 1) + path;
2992 } else { /* Two port mode - no port swap */
2994 /* Figure out path swap value */
2995 path_swap_ovr = REG_RD(sc, MISC_REG_TWO_PORT_PATH_SWAP_OVWR);
2996 if (path_swap_ovr & 0x1) {
2997 path_swap = (path_swap_ovr & 0x2);
2999 path_swap = REG_RD(sc, MISC_REG_TWO_PORT_PATH_SWAP);
3009 static void elink_set_aer_mmd(struct elink_params *params,
3010 struct elink_phy *phy)
3013 uint16_t offset, aer_val;
3014 struct bnx2x_softc *sc = params->sc;
3015 ser_lane = ((params->lane_config &
3016 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK) >>
3017 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT);
3019 offset = (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) ?
3020 (phy->addr + ser_lane) : 0;
3022 if (USES_WARPCORE(sc)) {
3023 aer_val = elink_get_warpcore_lane(params);
3024 /* In Dual-lane mode, two lanes are joined together,
3025 * so in order to configure them, the AER broadcast method is
3027 * 0x200 is the broadcast address for lanes 0,1
3028 * 0x201 is the broadcast address for lanes 2,3
3030 if (phy->flags & ELINK_FLAGS_WC_DUAL_MODE)
3031 aer_val = (aer_val >> 1) | 0x200;
3032 } else if (CHIP_IS_E2(sc))
3033 aer_val = 0x3800 + offset - 1;
3035 aer_val = 0x3800 + offset;
3037 CL22_WR_OVER_CL45(sc, phy, MDIO_REG_BANK_AER_BLOCK,
3038 MDIO_AER_BLOCK_AER_REG, aer_val);
3042 /******************************************************************/
3043 /* Internal phy section */
3044 /******************************************************************/
3046 static void elink_set_serdes_access(struct bnx2x_softc *sc, uint8_t port)
3048 uint32_t emac_base = (port) ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
3051 REG_WR(sc, NIG_REG_SERDES0_CTRL_MD_ST + port * 0x10, 1);
3052 REG_WR(sc, emac_base + EMAC_REG_EMAC_MDIO_COMM, 0x245f8000);
3054 REG_WR(sc, emac_base + EMAC_REG_EMAC_MDIO_COMM, 0x245d000f);
3057 REG_WR(sc, NIG_REG_SERDES0_CTRL_MD_ST + port * 0x10, 0);
3060 static void elink_serdes_deassert(struct bnx2x_softc *sc, uint8_t port)
3064 PMD_DRV_LOG(DEBUG, sc, "elink_serdes_deassert");
3066 val = ELINK_SERDES_RESET_BITS << (port * 16);
3068 /* Reset and unreset the SerDes/XGXS */
3069 REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_CLEAR, val);
3071 REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_SET, val);
3073 elink_set_serdes_access(sc, port);
3075 REG_WR(sc, NIG_REG_SERDES0_CTRL_MD_DEVAD + port * 0x10,
3076 ELINK_DEFAULT_PHY_DEV_ADDR);
3079 static void elink_xgxs_specific_func(struct elink_phy *phy,
3080 struct elink_params *params,
3083 struct bnx2x_softc *sc = params->sc;
3085 case ELINK_PHY_INIT:
3086 /* Set correct devad */
3087 REG_WR(sc, NIG_REG_XGXS0_CTRL_MD_ST + params->port * 0x18, 0);
3088 REG_WR(sc, NIG_REG_XGXS0_CTRL_MD_DEVAD + params->port * 0x18,
3094 static void elink_xgxs_deassert(struct elink_params *params)
3096 struct bnx2x_softc *sc = params->sc;
3099 PMD_DRV_LOG(DEBUG, sc, "elink_xgxs_deassert");
3100 port = params->port;
3102 val = ELINK_XGXS_RESET_BITS << (port * 16);
3104 /* Reset and unreset the SerDes/XGXS */
3105 REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_CLEAR, val);
3107 REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_SET, val);
3108 elink_xgxs_specific_func(¶ms->phy[ELINK_INT_PHY], params,
3112 static void elink_calc_ieee_aneg_adv(struct elink_phy *phy,
3113 struct elink_params *params,
3116 *ieee_fc = MDIO_COMBO_IEEE0_AUTO_NEG_ADV_FULL_DUPLEX;
3117 /* Resolve pause mode and advertisement Please refer to Table
3118 * 28B-3 of the 802.3ab-1999 spec
3121 switch (phy->req_flow_ctrl) {
3122 case ELINK_FLOW_CTRL_AUTO:
3123 switch (params->req_fc_auto_adv) {
3124 case ELINK_FLOW_CTRL_BOTH:
3125 *ieee_fc |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH;
3127 case ELINK_FLOW_CTRL_RX:
3128 case ELINK_FLOW_CTRL_TX:
3130 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC;
3136 case ELINK_FLOW_CTRL_TX:
3137 *ieee_fc |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC;
3140 case ELINK_FLOW_CTRL_RX:
3141 case ELINK_FLOW_CTRL_BOTH:
3142 *ieee_fc |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH;
3145 case ELINK_FLOW_CTRL_NONE:
3147 *ieee_fc |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_NONE;
3150 PMD_DRV_LOG(DEBUG, params->sc, "ieee_fc = 0x%x", *ieee_fc);
3153 static void set_phy_vars(struct elink_params *params, struct elink_vars *vars)
3155 uint8_t actual_phy_idx, phy_index, link_cfg_idx;
3156 uint8_t phy_config_swapped = params->multi_phy_config &
3157 PORT_HW_CFG_PHY_SWAPPED_ENABLED;
3158 for (phy_index = ELINK_INT_PHY; phy_index < params->num_phys;
3160 link_cfg_idx = ELINK_LINK_CONFIG_IDX(phy_index);
3161 actual_phy_idx = phy_index;
3162 if (phy_config_swapped) {
3163 if (phy_index == ELINK_EXT_PHY1)
3164 actual_phy_idx = ELINK_EXT_PHY2;
3165 else if (phy_index == ELINK_EXT_PHY2)
3166 actual_phy_idx = ELINK_EXT_PHY1;
3168 params->phy[actual_phy_idx].req_flow_ctrl =
3169 params->req_flow_ctrl[link_cfg_idx];
3171 params->phy[actual_phy_idx].req_line_speed =
3172 params->req_line_speed[link_cfg_idx];
3174 params->phy[actual_phy_idx].speed_cap_mask =
3175 params->speed_cap_mask[link_cfg_idx];
3177 params->phy[actual_phy_idx].req_duplex =
3178 params->req_duplex[link_cfg_idx];
3180 if (params->req_line_speed[link_cfg_idx] ==
3181 ELINK_SPEED_AUTO_NEG)
3182 vars->link_status |= LINK_STATUS_AUTO_NEGOTIATE_ENABLED;
3184 PMD_DRV_LOG(DEBUG, params->sc, "req_flow_ctrl %x, req_line_speed %x,"
3185 " speed_cap_mask %x",
3186 params->phy[actual_phy_idx].req_flow_ctrl,
3187 params->phy[actual_phy_idx].req_line_speed,
3188 params->phy[actual_phy_idx].speed_cap_mask);
3192 static void elink_ext_phy_set_pause(struct elink_params *params,
3193 struct elink_phy *phy,
3194 struct elink_vars *vars)
3197 struct bnx2x_softc *sc = params->sc;
3198 /* Read modify write pause advertizing */
3199 elink_cl45_read(sc, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV_PAUSE, &val);
3201 val &= ~MDIO_AN_REG_ADV_PAUSE_BOTH;
3203 /* Please refer to Table 28B-3 of 802.3ab-1999 spec. */
3204 elink_calc_ieee_aneg_adv(phy, params, &vars->ieee_fc);
3205 if ((vars->ieee_fc &
3206 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) ==
3207 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) {
3208 val |= MDIO_AN_REG_ADV_PAUSE_ASYMMETRIC;
3210 if ((vars->ieee_fc &
3211 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) ==
3212 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) {
3213 val |= MDIO_AN_REG_ADV_PAUSE_PAUSE;
3215 PMD_DRV_LOG(DEBUG, sc, "Ext phy AN advertize 0x%x", val);
3216 elink_cl45_write(sc, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV_PAUSE, val);
3219 static void elink_pause_resolve(struct elink_vars *vars, uint32_t pause_result)
3221 switch (pause_result) { /* ASYM P ASYM P */
3222 case 0xb: /* 1 0 1 1 */
3223 vars->flow_ctrl = ELINK_FLOW_CTRL_TX;
3226 case 0xe: /* 1 1 1 0 */
3227 vars->flow_ctrl = ELINK_FLOW_CTRL_RX;
3230 case 0x5: /* 0 1 0 1 */
3231 case 0x7: /* 0 1 1 1 */
3232 case 0xd: /* 1 1 0 1 */
3233 case 0xf: /* 1 1 1 1 */
3234 vars->flow_ctrl = ELINK_FLOW_CTRL_BOTH;
3240 if (pause_result & (1 << 0))
3241 vars->link_status |= LINK_STATUS_LINK_PARTNER_SYMMETRIC_PAUSE;
3242 if (pause_result & (1 << 1))
3243 vars->link_status |= LINK_STATUS_LINK_PARTNER_ASYMMETRIC_PAUSE;
3247 static void elink_ext_phy_update_adv_fc(struct elink_phy *phy,
3248 struct elink_params *params,
3249 struct elink_vars *vars)
3251 uint16_t ld_pause; /* local */
3252 uint16_t lp_pause; /* link partner */
3253 uint16_t pause_result;
3254 struct bnx2x_softc *sc = params->sc;
3255 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X54618SE) {
3256 elink_cl22_read(sc, phy, 0x4, &ld_pause);
3257 elink_cl22_read(sc, phy, 0x5, &lp_pause);
3258 } else if (CHIP_IS_E3(sc) && ELINK_SINGLE_MEDIA_DIRECT(params)) {
3259 uint8_t lane = elink_get_warpcore_lane(params);
3260 uint16_t gp_status, gp_mask;
3261 elink_cl45_read(sc, phy,
3262 MDIO_AN_DEVAD, MDIO_WC_REG_GP2_STATUS_GP_2_4,
3264 gp_mask = (MDIO_WC_REG_GP2_STATUS_GP_2_4_CL73_AN_CMPL |
3265 MDIO_WC_REG_GP2_STATUS_GP_2_4_CL37_LP_AN_CAP) <<
3267 if ((gp_status & gp_mask) == gp_mask) {
3268 elink_cl45_read(sc, phy, MDIO_AN_DEVAD,
3269 MDIO_AN_REG_ADV_PAUSE, &ld_pause);
3270 elink_cl45_read(sc, phy, MDIO_AN_DEVAD,
3271 MDIO_AN_REG_LP_AUTO_NEG, &lp_pause);
3273 elink_cl45_read(sc, phy, MDIO_AN_DEVAD,
3274 MDIO_AN_REG_CL37_FC_LD, &ld_pause);
3275 elink_cl45_read(sc, phy, MDIO_AN_DEVAD,
3276 MDIO_AN_REG_CL37_FC_LP, &lp_pause);
3277 ld_pause = ((ld_pause &
3278 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH)
3280 lp_pause = ((lp_pause &
3281 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH)
3285 elink_cl45_read(sc, phy,
3287 MDIO_AN_REG_ADV_PAUSE, &ld_pause);
3288 elink_cl45_read(sc, phy,
3290 MDIO_AN_REG_LP_AUTO_NEG, &lp_pause);
3292 pause_result = (ld_pause & MDIO_AN_REG_ADV_PAUSE_MASK) >> 8;
3293 pause_result |= (lp_pause & MDIO_AN_REG_ADV_PAUSE_MASK) >> 10;
3294 PMD_DRV_LOG(DEBUG, sc, "Ext PHY pause result 0x%x", pause_result);
3295 elink_pause_resolve(vars, pause_result);
3299 static uint8_t elink_ext_phy_resolve_fc(struct elink_phy *phy,
3300 struct elink_params *params,
3301 struct elink_vars *vars)
3304 vars->flow_ctrl = ELINK_FLOW_CTRL_NONE;
3305 if (phy->req_flow_ctrl != ELINK_FLOW_CTRL_AUTO) {
3306 /* Update the advertised flow-controled of LD/LP in AN */
3307 if (phy->req_line_speed == ELINK_SPEED_AUTO_NEG)
3308 elink_ext_phy_update_adv_fc(phy, params, vars);
3309 /* But set the flow-control result as the requested one */
3310 vars->flow_ctrl = phy->req_flow_ctrl;
3311 } else if (phy->req_line_speed != ELINK_SPEED_AUTO_NEG)
3312 vars->flow_ctrl = params->req_fc_auto_adv;
3313 else if (vars->link_status & LINK_STATUS_AUTO_NEGOTIATE_COMPLETE) {
3315 elink_ext_phy_update_adv_fc(phy, params, vars);
3320 /******************************************************************/
3321 /* Warpcore section */
3322 /******************************************************************/
3323 /* The init_internal_warpcore should mirror the xgxs,
3324 * i.e. reset the lane (if needed), set aer for the
3325 * init configuration, and set/clear SGMII flag. Internal
3326 * phy init is done purely in phy_init stage.
3328 #define WC_TX_DRIVER(post2, idriver, ipre) \
3329 ((post2 << MDIO_WC_REG_TX0_TX_DRIVER_POST2_COEFF_OFFSET) | \
3330 (idriver << MDIO_WC_REG_TX0_TX_DRIVER_IDRIVER_OFFSET) | \
3331 (ipre << MDIO_WC_REG_TX0_TX_DRIVER_IPRE_DRIVER_OFFSET))
3333 #define WC_TX_FIR(post, main, pre) \
3334 ((post << MDIO_WC_REG_TX_FIR_TAP_POST_TAP_OFFSET) | \
3335 (main << MDIO_WC_REG_TX_FIR_TAP_MAIN_TAP_OFFSET) | \
3336 (pre << MDIO_WC_REG_TX_FIR_TAP_PRE_TAP_OFFSET))
3338 static void elink_warpcore_enable_AN_KR2(struct elink_phy *phy,
3339 struct elink_params *params,
3340 struct elink_vars *vars)
3342 struct bnx2x_softc *sc = params->sc;
3344 static struct elink_reg_set reg_set[] = {
3345 /* Step 1 - Program the TX/RX alignment markers */
3346 {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_TX_CTRL5, 0xa157},
3347 {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_TX_CTRL7, 0xcbe2},
3348 {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_TX_CTRL6, 0x7537},
3349 {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_TX_CTRL9, 0xa157},
3350 {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_RX_CTRL11, 0xcbe2},
3351 {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_RX_CTRL10, 0x7537},
3352 /* Step 2 - Configure the NP registers */
3353 {MDIO_WC_DEVAD, MDIO_WC_REG_CL73_USERB0_CTRL, 0x000a},
3354 {MDIO_WC_DEVAD, MDIO_WC_REG_CL73_BAM_CTRL1, 0x6400},
3355 {MDIO_WC_DEVAD, MDIO_WC_REG_CL73_BAM_CTRL3, 0x0620},
3356 {MDIO_WC_DEVAD, MDIO_WC_REG_CL73_BAM_CODE_FIELD, 0x0157},
3357 {MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_OUI1, 0x6464},
3358 {MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_OUI2, 0x3150},
3359 {MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_OUI3, 0x3150},
3360 {MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_LD_BAM_CODE, 0x0157},
3361 {MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_LD_UD_CODE, 0x0620}
3363 PMD_DRV_LOG(DEBUG, sc, "Enabling 20G-KR2");
3365 elink_cl45_read_or_write(sc, phy, MDIO_WC_DEVAD,
3366 MDIO_WC_REG_CL49_USERB0_CTRL, (3 << 6));
3368 for (i = 0; i < ARRAY_SIZE(reg_set); i++)
3369 elink_cl45_write(sc, phy, reg_set[i].devad, reg_set[i].reg,
3372 /* Start KR2 work-around timer which handles BNX2X8073 link-parner */
3373 vars->link_attr_sync |= LINK_ATTR_SYNC_KR2_ENABLE;
3374 elink_update_link_attr(params, vars->link_attr_sync);
3377 static void elink_disable_kr2(struct elink_params *params,
3378 struct elink_vars *vars, struct elink_phy *phy)
3380 struct bnx2x_softc *sc = params->sc;
3382 static struct elink_reg_set reg_set[] = {
3383 /* Step 1 - Program the TX/RX alignment markers */
3384 {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_TX_CTRL5, 0x7690},
3385 {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_TX_CTRL7, 0xe647},
3386 {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_TX_CTRL6, 0xc4f0},
3387 {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_TX_CTRL9, 0x7690},
3388 {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_RX_CTRL11, 0xe647},
3389 {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_RX_CTRL10, 0xc4f0},
3390 {MDIO_WC_DEVAD, MDIO_WC_REG_CL73_USERB0_CTRL, 0x000c},
3391 {MDIO_WC_DEVAD, MDIO_WC_REG_CL73_BAM_CTRL1, 0x6000},
3392 {MDIO_WC_DEVAD, MDIO_WC_REG_CL73_BAM_CTRL3, 0x0000},
3393 {MDIO_WC_DEVAD, MDIO_WC_REG_CL73_BAM_CODE_FIELD, 0x0002},
3394 {MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_OUI1, 0x0000},
3395 {MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_OUI2, 0x0af7},
3396 {MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_OUI3, 0x0af7},
3397 {MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_LD_BAM_CODE, 0x0002},
3398 {MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_LD_UD_CODE, 0x0000}
3400 PMD_DRV_LOG(DEBUG, sc, "Disabling 20G-KR2");
3402 for (i = 0; i < ARRAY_SIZE(reg_set); i++)
3403 elink_cl45_write(sc, phy, reg_set[i].devad, reg_set[i].reg,
3405 vars->link_attr_sync &= ~LINK_ATTR_SYNC_KR2_ENABLE;
3406 elink_update_link_attr(params, vars->link_attr_sync);
3408 vars->check_kr2_recovery_cnt = ELINK_CHECK_KR2_RECOVERY_CNT;
3411 static void elink_warpcore_set_lpi_passthrough(struct elink_phy *phy,
3412 struct elink_params *params)
3414 struct bnx2x_softc *sc = params->sc;
3416 PMD_DRV_LOG(DEBUG, sc, "Configure WC for LPI pass through");
3417 elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
3418 MDIO_WC_REG_EEE_COMBO_CONTROL0, 0x7c);
3419 elink_cl45_read_or_write(sc, phy, MDIO_WC_DEVAD,
3420 MDIO_WC_REG_DIGITAL4_MISC5, 0xc000);
3423 static void elink_warpcore_restart_AN_KR(struct elink_phy *phy,
3424 struct elink_params *params)
3426 /* Restart autoneg on the leading lane only */
3427 struct bnx2x_softc *sc = params->sc;
3428 uint16_t lane = elink_get_warpcore_lane(params);
3429 CL22_WR_OVER_CL45(sc, phy, MDIO_REG_BANK_AER_BLOCK,
3430 MDIO_AER_BLOCK_AER_REG, lane);
3431 elink_cl45_write(sc, phy, MDIO_AN_DEVAD,
3432 MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x1200);
3435 elink_set_aer_mmd(params, phy);
3438 static void elink_warpcore_enable_AN_KR(struct elink_phy *phy,
3439 struct elink_params *params,
3440 struct elink_vars *vars)
3442 uint16_t lane, i, cl72_ctrl, an_adv = 0;
3443 struct bnx2x_softc *sc = params->sc;
3444 static struct elink_reg_set reg_set[] = {
3445 {MDIO_WC_DEVAD, MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2, 0x7},
3446 {MDIO_PMA_DEVAD, MDIO_WC_REG_IEEE0BLK_AUTONEGNP, 0x0},
3447 {MDIO_WC_DEVAD, MDIO_WC_REG_RX66_CONTROL, 0x7415},
3448 {MDIO_WC_DEVAD, MDIO_WC_REG_SERDESDIGITAL_MISC2, 0x6190},
3449 /* Disable Autoneg: re-enable it after adv is done. */
3450 {MDIO_AN_DEVAD, MDIO_WC_REG_IEEE0BLK_MIICNTL, 0},
3451 {MDIO_PMA_DEVAD, MDIO_WC_REG_PMD_KR_CONTROL, 0x2},
3452 {MDIO_WC_DEVAD, MDIO_WC_REG_CL72_USERB0_CL72_TX_FIR_TAP, 0},
3454 PMD_DRV_LOG(DEBUG, sc, "Enable Auto Negotiation for KR");
3455 /* Set to default registers that may be overriden by 10G force */
3456 for (i = 0; i < ARRAY_SIZE(reg_set); i++)
3457 elink_cl45_write(sc, phy, reg_set[i].devad, reg_set[i].reg,
3460 elink_cl45_read(sc, phy, MDIO_WC_DEVAD,
3461 MDIO_WC_REG_CL72_USERB0_CL72_MISC1_CONTROL, &cl72_ctrl);
3462 cl72_ctrl &= 0x08ff;
3463 cl72_ctrl |= 0x3800;
3464 elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
3465 MDIO_WC_REG_CL72_USERB0_CL72_MISC1_CONTROL, cl72_ctrl);
3467 /* Check adding advertisement for 1G KX */
3468 if (((vars->line_speed == ELINK_SPEED_AUTO_NEG) &&
3469 (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) ||
3470 (vars->line_speed == ELINK_SPEED_1000)) {
3471 uint16_t addr = MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2;
3474 /* Enable CL37 1G Parallel Detect */
3475 elink_cl45_read_or_write(sc, phy, MDIO_WC_DEVAD, addr, 0x1);
3476 PMD_DRV_LOG(DEBUG, sc, "Advertize 1G");
3478 if (((vars->line_speed == ELINK_SPEED_AUTO_NEG) &&
3479 (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) ||
3480 (vars->line_speed == ELINK_SPEED_10000)) {
3481 /* Check adding advertisement for 10G KR */
3483 /* Enable 10G Parallel Detect */
3484 CL22_WR_OVER_CL45(sc, phy, MDIO_REG_BANK_AER_BLOCK,
3485 MDIO_AER_BLOCK_AER_REG, 0);
3487 elink_cl45_write(sc, phy, MDIO_AN_DEVAD,
3488 MDIO_WC_REG_PAR_DET_10G_CTRL, 1);
3489 elink_set_aer_mmd(params, phy);
3490 PMD_DRV_LOG(DEBUG, sc, "Advertize 10G");
3493 /* Set Transmit PMD settings */
3494 lane = elink_get_warpcore_lane(params);
3495 elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
3496 MDIO_WC_REG_TX0_TX_DRIVER + 0x10 * lane,
3497 WC_TX_DRIVER(0x02, 0x06, 0x09));
3498 /* Configure the next lane if dual mode */
3499 if (phy->flags & ELINK_FLAGS_WC_DUAL_MODE)
3500 elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
3501 MDIO_WC_REG_TX0_TX_DRIVER + 0x10 * (lane + 1),
3502 WC_TX_DRIVER(0x02, 0x06, 0x09));
3503 elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
3504 MDIO_WC_REG_CL72_USERB0_CL72_OS_DEF_CTRL, 0x03f0);
3505 elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
3506 MDIO_WC_REG_CL72_USERB0_CL72_2P5_DEF_CTRL, 0x03f0);
3508 /* Advertised speeds */
3509 elink_cl45_write(sc, phy, MDIO_AN_DEVAD,
3510 MDIO_WC_REG_AN_IEEE1BLK_AN_ADVERTISEMENT1, an_adv);
3512 /* Advertised and set FEC (Forward Error Correction) */
3513 elink_cl45_write(sc, phy, MDIO_AN_DEVAD,
3514 MDIO_WC_REG_AN_IEEE1BLK_AN_ADVERTISEMENT2,
3515 (MDIO_WC_REG_AN_IEEE1BLK_AN_ADV2_FEC_ABILITY |
3516 MDIO_WC_REG_AN_IEEE1BLK_AN_ADV2_FEC_REQ));
3518 /* Enable CL37 BAM */
3519 if (REG_RD(sc, params->shmem_base +
3520 offsetof(struct shmem_region,
3521 dev_info.port_hw_config[params->port].
3523 PORT_HW_CFG_ENABLE_BAM_ON_KR_ENABLED) {
3524 elink_cl45_read_or_write(sc, phy, MDIO_WC_DEVAD,
3525 MDIO_WC_REG_DIGITAL6_MP5_NEXTPAGECTRL,
3527 PMD_DRV_LOG(DEBUG, sc, "Enable CL37 BAM on KR");
3530 /* Advertise pause */
3531 elink_ext_phy_set_pause(params, phy, vars);
3532 vars->rx_tx_asic_rst = MAX_KR_LINK_RETRY;
3533 elink_cl45_read_or_write(sc, phy, MDIO_WC_DEVAD,
3534 MDIO_WC_REG_DIGITAL5_MISC7, 0x100);
3536 /* Over 1G - AN local device user page 1 */
3537 elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
3538 MDIO_WC_REG_DIGITAL3_UP1, 0x1f);
3540 if (((phy->req_line_speed == ELINK_SPEED_AUTO_NEG) &&
3541 (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_20G)) ||
3542 (phy->req_line_speed == ELINK_SPEED_20000)) {
3544 CL22_WR_OVER_CL45(sc, phy, MDIO_REG_BANK_AER_BLOCK,
3545 MDIO_AER_BLOCK_AER_REG, lane);
3547 elink_cl45_read_or_write(sc, phy, MDIO_WC_DEVAD,
3548 MDIO_WC_REG_RX1_PCI_CTRL +
3549 (0x10 * lane), (1 << 11));
3551 elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
3552 MDIO_WC_REG_XGXS_X2_CONTROL3, 0x7);
3553 elink_set_aer_mmd(params, phy);
3555 elink_warpcore_enable_AN_KR2(phy, params, vars);
3557 elink_disable_kr2(params, vars, phy);
3560 /* Enable Autoneg: only on the main lane */
3561 elink_warpcore_restart_AN_KR(phy, params);
3564 static void elink_warpcore_set_10G_KR(struct elink_phy *phy,
3565 struct elink_params *params)
3567 struct bnx2x_softc *sc = params->sc;
3568 uint16_t val16, i, lane;
3569 static struct elink_reg_set reg_set[] = {
3570 /* Disable Autoneg */
3571 {MDIO_WC_DEVAD, MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2, 0x7},
3572 {MDIO_WC_DEVAD, MDIO_WC_REG_CL72_USERB0_CL72_MISC1_CONTROL,
3574 {MDIO_AN_DEVAD, MDIO_WC_REG_AN_IEEE1BLK_AN_ADVERTISEMENT1, 0},
3575 {MDIO_AN_DEVAD, MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x0},
3576 {MDIO_WC_DEVAD, MDIO_WC_REG_DIGITAL3_UP1, 0x1},
3577 {MDIO_WC_DEVAD, MDIO_WC_REG_DIGITAL5_MISC7, 0xa},
3578 /* Leave cl72 training enable, needed for KR */
3579 {MDIO_PMA_DEVAD, MDIO_WC_REG_PMD_KR_CONTROL, 0x2}
3582 for (i = 0; i < ARRAY_SIZE(reg_set); i++)
3583 elink_cl45_write(sc, phy, reg_set[i].devad, reg_set[i].reg,
3586 lane = elink_get_warpcore_lane(params);
3587 /* Global registers */
3588 CL22_WR_OVER_CL45(sc, phy, MDIO_REG_BANK_AER_BLOCK,
3589 MDIO_AER_BLOCK_AER_REG, 0);
3590 /* Disable CL36 PCS Tx */
3591 elink_cl45_read(sc, phy, MDIO_WC_DEVAD,
3592 MDIO_WC_REG_XGXSBLK1_LANECTRL0, &val16);
3593 val16 &= ~(0x0011 << lane);
3594 elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
3595 MDIO_WC_REG_XGXSBLK1_LANECTRL0, val16);
3597 elink_cl45_read(sc, phy, MDIO_WC_DEVAD,
3598 MDIO_WC_REG_XGXSBLK1_LANECTRL1, &val16);
3599 val16 |= (0x0303 << (lane << 1));
3600 elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
3601 MDIO_WC_REG_XGXSBLK1_LANECTRL1, val16);
3603 elink_set_aer_mmd(params, phy);
3604 /* Set speed via PMA/PMD register */
3605 elink_cl45_write(sc, phy, MDIO_PMA_DEVAD,
3606 MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x2040);
3608 elink_cl45_write(sc, phy, MDIO_PMA_DEVAD,
3609 MDIO_WC_REG_IEEE0BLK_AUTONEGNP, 0xB);
3611 /* Enable encoded forced speed */
3612 elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
3613 MDIO_WC_REG_SERDESDIGITAL_MISC2, 0x30);
3615 /* Turn TX scramble payload only the 64/66 scrambler */
3616 elink_cl45_write(sc, phy, MDIO_WC_DEVAD, MDIO_WC_REG_TX66_CONTROL, 0x9);
3618 /* Turn RX scramble payload only the 64/66 scrambler */
3619 elink_cl45_read_or_write(sc, phy, MDIO_WC_DEVAD,
3620 MDIO_WC_REG_RX66_CONTROL, 0xF9);
3622 /* Set and clear loopback to cause a reset to 64/66 decoder */
3623 elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
3624 MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x4000);
3625 elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
3626 MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x0);
3630 static void elink_warpcore_set_10G_XFI(struct elink_phy *phy,
3631 struct elink_params *params,
3634 struct bnx2x_softc *sc = params->sc;
3635 uint16_t misc1_val, tap_val, tx_driver_val, lane, val;
3636 uint32_t cfg_tap_val, tx_drv_brdct, tx_equal;
3638 /* Hold rxSeqStart */
3639 elink_cl45_read_or_write(sc, phy, MDIO_WC_DEVAD,
3640 MDIO_WC_REG_DSC2B0_DSC_MISC_CTRL0, 0x8000);
3642 /* Hold tx_fifo_reset */
3643 elink_cl45_read_or_write(sc, phy, MDIO_WC_DEVAD,
3644 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X3, 0x1);
3646 /* Disable CL73 AN */
3647 elink_cl45_write(sc, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0);
3649 /* Disable 100FX Enable and Auto-Detect */
3650 elink_cl45_read_and_write(sc, phy, MDIO_WC_DEVAD,
3651 MDIO_WC_REG_FX100_CTRL1, 0xFFFA);
3653 /* Disable 100FX Idle detect */
3654 elink_cl45_read_or_write(sc, phy, MDIO_WC_DEVAD,
3655 MDIO_WC_REG_FX100_CTRL3, 0x0080);
3657 /* Set Block address to Remote PHY & Clear forced_speed[5] */
3658 elink_cl45_read_and_write(sc, phy, MDIO_WC_DEVAD,
3659 MDIO_WC_REG_DIGITAL4_MISC3, 0xFF7F);
3661 /* Turn off auto-detect & fiber mode */
3662 elink_cl45_read_and_write(sc, phy, MDIO_WC_DEVAD,
3663 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1,
3666 /* Set filter_force_link, disable_false_link and parallel_detect */
3667 elink_cl45_read(sc, phy, MDIO_WC_DEVAD,
3668 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2, &val);
3669 elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
3670 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2,
3671 ((val | 0x0006) & 0xFFFE));
3674 elink_cl45_read(sc, phy, MDIO_WC_DEVAD,
3675 MDIO_WC_REG_SERDESDIGITAL_MISC1, &misc1_val);
3677 misc1_val &= ~(0x1f);
3681 tap_val = WC_TX_FIR(0x08, 0x37, 0x00);
3682 tx_driver_val = WC_TX_DRIVER(0x00, 0x02, 0x03);
3684 cfg_tap_val = REG_RD(sc, params->shmem_base +
3685 offsetof(struct shmem_region,
3686 dev_info.port_hw_config[params->
3687 port].sfi_tap_values));
3689 tx_equal = cfg_tap_val & PORT_HW_CFG_TX_EQUALIZATION_MASK;
3691 tx_drv_brdct = (cfg_tap_val &
3692 PORT_HW_CFG_TX_DRV_BROADCAST_MASK) >>
3693 PORT_HW_CFG_TX_DRV_BROADCAST_SHIFT;
3697 /* TAP values are controlled by nvram, if value there isn't 0 */
3699 tap_val = (uint16_t) tx_equal;
3701 tap_val = WC_TX_FIR(0x0f, 0x2b, 0x02);
3705 WC_TX_DRIVER(0x03, (uint16_t) tx_drv_brdct, 0x06);
3707 tx_driver_val = WC_TX_DRIVER(0x03, 0x02, 0x06);
3709 elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
3710 MDIO_WC_REG_SERDESDIGITAL_MISC1, misc1_val);
3712 /* Set Transmit PMD settings */
3713 lane = elink_get_warpcore_lane(params);
3714 elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
3715 MDIO_WC_REG_TX_FIR_TAP,
3716 tap_val | MDIO_WC_REG_TX_FIR_TAP_ENABLE);
3717 elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
3718 MDIO_WC_REG_TX0_TX_DRIVER + 0x10 * lane,
3721 /* Enable fiber mode, enable and invert sig_det */
3722 elink_cl45_read_or_write(sc, phy, MDIO_WC_DEVAD,
3723 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1, 0xd);
3725 /* Set Block address to Remote PHY & Set forced_speed[5], 40bit mode */
3726 elink_cl45_read_or_write(sc, phy, MDIO_WC_DEVAD,
3727 MDIO_WC_REG_DIGITAL4_MISC3, 0x8080);
3729 elink_warpcore_set_lpi_passthrough(phy, params);
3731 /* 10G XFI Full Duplex */
3732 elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
3733 MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x100);
3735 /* Release tx_fifo_reset */
3736 elink_cl45_read_and_write(sc, phy, MDIO_WC_DEVAD,
3737 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X3,
3739 /* Release rxSeqStart */
3740 elink_cl45_read_and_write(sc, phy, MDIO_WC_DEVAD,
3741 MDIO_WC_REG_DSC2B0_DSC_MISC_CTRL0, 0x7FFF);
3744 static void elink_warpcore_set_20G_force_KR2(struct elink_phy *phy,
3745 struct elink_params *params)
3748 struct bnx2x_softc *sc = params->sc;
3749 /* Set global registers, so set AER lane to 0 */
3750 CL22_WR_OVER_CL45(sc, phy, MDIO_REG_BANK_AER_BLOCK,
3751 MDIO_AER_BLOCK_AER_REG, 0);
3753 /* Disable sequencer */
3754 elink_cl45_read_and_write(sc, phy, MDIO_WC_DEVAD,
3755 MDIO_WC_REG_XGXSBLK0_XGXSCONTROL, ~(1 << 13));
3757 elink_set_aer_mmd(params, phy);
3759 elink_cl45_read_and_write(sc, phy, MDIO_PMA_DEVAD,
3760 MDIO_WC_REG_PMD_KR_CONTROL, ~(1 << 1));
3761 elink_cl45_write(sc, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0);
3763 elink_cl45_read(sc, phy, MDIO_WC_DEVAD,
3764 MDIO_WC_REG_CL73_USERB0_CTRL, &val);
3767 elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
3768 MDIO_WC_REG_CL73_USERB0_CTRL, val);
3770 /* Set 20G KR2 force speed */
3771 elink_cl45_read_or_write(sc, phy, MDIO_WC_DEVAD,
3772 MDIO_WC_REG_SERDESDIGITAL_MISC1, 0x1f);
3774 elink_cl45_read_or_write(sc, phy, MDIO_WC_DEVAD,
3775 MDIO_WC_REG_DIGITAL4_MISC3, (1 << 7));
3777 elink_cl45_read(sc, phy, MDIO_WC_DEVAD,
3778 MDIO_WC_REG_CL72_USERB0_CL72_MISC1_CONTROL, &val);
3781 elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
3782 MDIO_WC_REG_CL72_USERB0_CL72_MISC1_CONTROL, val);
3783 elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
3784 MDIO_WC_REG_CL72_USERB0_CL72_TX_FIR_TAP, 0x835A);
3786 /* Enable sequencer (over lane 0) */
3787 CL22_WR_OVER_CL45(sc, phy, MDIO_REG_BANK_AER_BLOCK,
3788 MDIO_AER_BLOCK_AER_REG, 0);
3790 elink_cl45_read_or_write(sc, phy, MDIO_WC_DEVAD,
3791 MDIO_WC_REG_XGXSBLK0_XGXSCONTROL, (1 << 13));
3793 elink_set_aer_mmd(params, phy);
3796 static void elink_warpcore_set_20G_DXGXS(struct bnx2x_softc *sc,
3797 struct elink_phy *phy, uint16_t lane)
3799 /* Rx0 anaRxControl1G */
3800 elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
3801 MDIO_WC_REG_RX0_ANARXCONTROL1G, 0x90);
3803 /* Rx2 anaRxControl1G */
3804 elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
3805 MDIO_WC_REG_RX2_ANARXCONTROL1G, 0x90);
3807 elink_cl45_write(sc, phy, MDIO_WC_DEVAD, MDIO_WC_REG_RX66_SCW0, 0xE070);
3809 elink_cl45_write(sc, phy, MDIO_WC_DEVAD, MDIO_WC_REG_RX66_SCW1, 0xC0D0);
3811 elink_cl45_write(sc, phy, MDIO_WC_DEVAD, MDIO_WC_REG_RX66_SCW2, 0xA0B0);
3813 elink_cl45_write(sc, phy, MDIO_WC_DEVAD, MDIO_WC_REG_RX66_SCW3, 0x8090);
3815 elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
3816 MDIO_WC_REG_RX66_SCW0_MASK, 0xF0F0);
3818 elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
3819 MDIO_WC_REG_RX66_SCW1_MASK, 0xF0F0);
3821 elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
3822 MDIO_WC_REG_RX66_SCW2_MASK, 0xF0F0);
3824 elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
3825 MDIO_WC_REG_RX66_SCW3_MASK, 0xF0F0);
3827 /* Serdes Digital Misc1 */
3828 elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
3829 MDIO_WC_REG_SERDESDIGITAL_MISC1, 0x6008);
3831 /* Serdes Digital4 Misc3 */
3832 elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
3833 MDIO_WC_REG_DIGITAL4_MISC3, 0x8088);
3835 /* Set Transmit PMD settings */
3836 elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
3837 MDIO_WC_REG_TX_FIR_TAP,
3838 (WC_TX_FIR(0x12, 0x2d, 0x00) |
3839 MDIO_WC_REG_TX_FIR_TAP_ENABLE));
3840 elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
3841 MDIO_WC_REG_TX0_TX_DRIVER + 0x10 * lane,
3842 WC_TX_DRIVER(0x02, 0x02, 0x02));
3845 static void elink_warpcore_set_sgmii_speed(struct elink_phy *phy,
3846 struct elink_params *params,
3848 uint8_t always_autoneg)
3850 struct bnx2x_softc *sc = params->sc;
3851 uint16_t val16, digctrl_kx1, digctrl_kx2;
3853 /* Clear XFI clock comp in non-10G single lane mode. */
3854 elink_cl45_read_and_write(sc, phy, MDIO_WC_DEVAD,
3855 MDIO_WC_REG_RX66_CONTROL, ~(3 << 13));
3857 elink_warpcore_set_lpi_passthrough(phy, params);
3859 if (always_autoneg || phy->req_line_speed == ELINK_SPEED_AUTO_NEG) {
3861 elink_cl45_read_or_write(sc, phy, MDIO_WC_DEVAD,
3862 MDIO_WC_REG_COMBO_IEEE0_MIICTRL,
3864 PMD_DRV_LOG(DEBUG, sc, "set SGMII AUTONEG");
3866 elink_cl45_read(sc, phy, MDIO_WC_DEVAD,
3867 MDIO_WC_REG_COMBO_IEEE0_MIICTRL, &val16);
3869 switch (phy->req_line_speed) {
3870 case ELINK_SPEED_10:
3872 case ELINK_SPEED_100:
3875 case ELINK_SPEED_1000:
3879 PMD_DRV_LOG(DEBUG, sc,
3880 "Speed not supported: 0x%x",
3881 phy->req_line_speed);
3885 if (phy->req_duplex == DUPLEX_FULL)
3888 elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
3889 MDIO_WC_REG_COMBO_IEEE0_MIICTRL, val16);
3891 PMD_DRV_LOG(DEBUG, sc, "set SGMII force speed %d",
3892 phy->req_line_speed);
3893 elink_cl45_read(sc, phy, MDIO_WC_DEVAD,
3894 MDIO_WC_REG_COMBO_IEEE0_MIICTRL, &val16);
3895 PMD_DRV_LOG(DEBUG, sc, " (readback) %x", val16);
3898 /* SGMII Slave mode and disable signal detect */
3899 elink_cl45_read(sc, phy, MDIO_WC_DEVAD,
3900 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1, &digctrl_kx1);
3904 digctrl_kx1 &= 0xff4a;
3906 elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
3907 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1, digctrl_kx1);
3909 /* Turn off parallel detect */
3910 elink_cl45_read(sc, phy, MDIO_WC_DEVAD,
3911 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2, &digctrl_kx2);
3912 elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
3913 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2,
3914 (digctrl_kx2 & ~(1 << 2)));
3916 /* Re-enable parallel detect */
3917 elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
3918 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2,
3919 (digctrl_kx2 | (1 << 2)));
3921 /* Enable autodet */
3922 elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
3923 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1,
3924 (digctrl_kx1 | 0x10));
3927 static void elink_warpcore_reset_lane(struct bnx2x_softc *sc,
3928 struct elink_phy *phy, uint8_t reset)
3931 /* Take lane out of reset after configuration is finished */
3932 elink_cl45_read(sc, phy, MDIO_WC_DEVAD,
3933 MDIO_WC_REG_DIGITAL5_MISC6, &val);
3938 elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
3939 MDIO_WC_REG_DIGITAL5_MISC6, val);
3940 elink_cl45_read(sc, phy, MDIO_WC_DEVAD,
3941 MDIO_WC_REG_DIGITAL5_MISC6, &val);
3944 /* Clear SFI/XFI link settings registers */
3945 static void elink_warpcore_clear_regs(struct elink_phy *phy,
3946 struct elink_params *params,
3949 struct bnx2x_softc *sc = params->sc;
3951 static struct elink_reg_set wc_regs[] = {
3952 {MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0},
3953 {MDIO_WC_DEVAD, MDIO_WC_REG_FX100_CTRL1, 0x014a},
3954 {MDIO_WC_DEVAD, MDIO_WC_REG_FX100_CTRL3, 0x0800},
3955 {MDIO_WC_DEVAD, MDIO_WC_REG_DIGITAL4_MISC3, 0x8008},
3956 {MDIO_WC_DEVAD, MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1,
3958 {MDIO_WC_DEVAD, MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2,
3960 {MDIO_WC_DEVAD, MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X3,
3962 {MDIO_WC_DEVAD, MDIO_WC_REG_SERDESDIGITAL_MISC1, 0x6000},
3963 {MDIO_WC_DEVAD, MDIO_WC_REG_TX_FIR_TAP, 0x0000},
3964 {MDIO_WC_DEVAD, MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x2040},
3965 {MDIO_WC_DEVAD, MDIO_WC_REG_COMBO_IEEE0_MIICTRL, 0x0140}
3967 /* Set XFI clock comp as default. */
3968 elink_cl45_read_or_write(sc, phy, MDIO_WC_DEVAD,
3969 MDIO_WC_REG_RX66_CONTROL, (3 << 13));
3971 for (i = 0; i < ARRAY_SIZE(wc_regs); i++)
3972 elink_cl45_write(sc, phy, wc_regs[i].devad, wc_regs[i].reg,
3975 lane = elink_get_warpcore_lane(params);
3976 elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
3977 MDIO_WC_REG_TX0_TX_DRIVER + 0x10 * lane, 0x0990);
3981 static elink_status_t elink_get_mod_abs_int_cfg(struct bnx2x_softc *sc,
3982 uint32_t shmem_base,
3985 uint8_t * gpio_port)
3990 if (CHIP_IS_E3(sc)) {
3991 cfg_pin = (REG_RD(sc, shmem_base +
3992 offsetof(struct shmem_region,
3993 dev_info.port_hw_config[port].
3995 PORT_HW_CFG_E3_MOD_ABS_MASK) >>
3996 PORT_HW_CFG_E3_MOD_ABS_SHIFT;
3998 /* Should not happen. This function called upon interrupt
3999 * triggered by GPIO ( since EPIO can only generate interrupts
4001 * So if this function was called and none of the GPIOs was set,
4002 * it means the shit hit the fan.
4004 if ((cfg_pin < PIN_CFG_GPIO0_P0) ||
4005 (cfg_pin > PIN_CFG_GPIO3_P1)) {
4006 PMD_DRV_LOG(DEBUG, sc,
4007 "No cfg pin %x for module detect indication",
4009 return ELINK_STATUS_ERROR;
4012 *gpio_num = (cfg_pin - PIN_CFG_GPIO0_P0) & 0x3;
4013 *gpio_port = (cfg_pin - PIN_CFG_GPIO0_P0) >> 2;
4015 *gpio_num = MISC_REGISTERS_GPIO_3;
4019 return ELINK_STATUS_OK;
4022 static int elink_is_sfp_module_plugged(struct elink_params *params)
4024 struct bnx2x_softc *sc = params->sc;
4025 uint8_t gpio_num, gpio_port;
4027 if (elink_get_mod_abs_int_cfg(sc,
4028 params->shmem_base, params->port,
4029 &gpio_num, &gpio_port) != ELINK_STATUS_OK)
4031 gpio_val = elink_cb_gpio_read(sc, gpio_num, gpio_port);
4033 /* Call the handling function in case module is detected */
4040 static int elink_warpcore_get_sigdet(struct elink_phy *phy,
4041 struct elink_params *params)
4043 uint16_t gp2_status_reg0, lane;
4044 struct bnx2x_softc *sc = params->sc;
4046 lane = elink_get_warpcore_lane(params);
4048 elink_cl45_read(sc, phy, MDIO_WC_DEVAD, MDIO_WC_REG_GP2_STATUS_GP_2_0,
4051 return (gp2_status_reg0 >> (8 + lane)) & 0x1;
4054 static void elink_warpcore_config_runtime(struct elink_phy *phy,
4055 struct elink_params *params,
4056 struct elink_vars *vars)
4058 struct bnx2x_softc *sc = params->sc;
4059 uint32_t serdes_net_if;
4060 uint16_t gp_status1 = 0, lnkup = 0, lnkup_kr = 0;
4062 vars->turn_to_run_wc_rt = vars->turn_to_run_wc_rt ? 0 : 1;
4064 if (!vars->turn_to_run_wc_rt)
4067 if (vars->rx_tx_asic_rst) {
4068 uint16_t lane = elink_get_warpcore_lane(params);
4069 serdes_net_if = (REG_RD(sc, params->shmem_base +
4070 offsetof(struct shmem_region,
4071 dev_info.port_hw_config
4074 PORT_HW_CFG_NET_SERDES_IF_MASK);
4076 switch (serdes_net_if) {
4077 case PORT_HW_CFG_NET_SERDES_IF_KR:
4078 /* Do we get link yet? */
4079 elink_cl45_read(sc, phy, MDIO_WC_DEVAD, 0x81d1,
4081 lnkup = (gp_status1 >> (8 + lane)) & 0x1; /* 1G */
4083 lnkup_kr = (gp_status1 >> (12 + lane)) & 0x1;
4085 if (lnkup_kr || lnkup) {
4086 vars->rx_tx_asic_rst = 0;
4088 /* Reset the lane to see if link comes up. */
4089 elink_warpcore_reset_lane(sc, phy, 1);
4090 elink_warpcore_reset_lane(sc, phy, 0);
4092 /* Restart Autoneg */
4093 elink_cl45_write(sc, phy, MDIO_AN_DEVAD,
4094 MDIO_WC_REG_IEEE0BLK_MIICNTL,
4097 vars->rx_tx_asic_rst--;
4098 PMD_DRV_LOG(DEBUG, sc, "0x%x retry left",
4099 vars->rx_tx_asic_rst);
4108 /*params->rx_tx_asic_rst */
4111 static void elink_warpcore_config_sfi(struct elink_phy *phy,
4112 struct elink_params *params)
4114 uint16_t lane = elink_get_warpcore_lane(params);
4116 elink_warpcore_clear_regs(phy, params, lane);
4117 if ((params->req_line_speed[ELINK_LINK_CONFIG_IDX(ELINK_INT_PHY)] ==
4118 ELINK_SPEED_10000) &&
4119 (phy->media_type != ELINK_ETH_PHY_SFP_1G_FIBER)) {
4120 PMD_DRV_LOG(DEBUG, params->sc, "Setting 10G SFI");
4121 elink_warpcore_set_10G_XFI(phy, params, 0);
4123 PMD_DRV_LOG(DEBUG, params->sc, "Setting 1G Fiber");
4124 elink_warpcore_set_sgmii_speed(phy, params, 1, 0);
4128 static void elink_sfp_e3_set_transmitter(struct elink_params *params,
4129 struct elink_phy *phy, uint8_t tx_en)
4131 struct bnx2x_softc *sc = params->sc;
4133 uint8_t port = params->port;
4135 cfg_pin = REG_RD(sc, params->shmem_base +
4136 offsetof(struct shmem_region,
4137 dev_info.port_hw_config[port].e3_sfp_ctrl)) &
4138 PORT_HW_CFG_E3_TX_LASER_MASK;
4139 /* Set the !tx_en since this pin is DISABLE_TX_LASER */
4140 PMD_DRV_LOG(DEBUG, sc, "Setting WC TX to %d", tx_en);
4142 /* For 20G, the expected pin to be used is 3 pins after the current */
4143 elink_set_cfg_pin(sc, cfg_pin, tx_en ^ 1);
4144 if (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_20G)
4145 elink_set_cfg_pin(sc, cfg_pin + 3, tx_en ^ 1);
4148 static uint8_t elink_warpcore_config_init(struct elink_phy *phy,
4149 struct elink_params *params,
4150 struct elink_vars *vars)
4152 struct bnx2x_softc *sc = params->sc;
4153 uint32_t serdes_net_if;
4155 uint16_t lane = elink_get_warpcore_lane(params);
4156 serdes_net_if = (REG_RD(sc, params->shmem_base +
4157 offsetof(struct shmem_region,
4158 dev_info.port_hw_config[params->port].
4160 PORT_HW_CFG_NET_SERDES_IF_MASK);
4161 PMD_DRV_LOG(DEBUG, sc,
4162 "Begin Warpcore init, link_speed %d, "
4163 "serdes_net_if = 0x%x", vars->line_speed, serdes_net_if);
4164 elink_set_aer_mmd(params, phy);
4165 elink_warpcore_reset_lane(sc, phy, 1);
4166 vars->phy_flags |= PHY_XGXS_FLAG;
4167 if ((serdes_net_if == PORT_HW_CFG_NET_SERDES_IF_SGMII) ||
4168 (phy->req_line_speed &&
4169 ((phy->req_line_speed == ELINK_SPEED_100) ||
4170 (phy->req_line_speed == ELINK_SPEED_10)))) {
4171 vars->phy_flags |= PHY_SGMII_FLAG;
4172 PMD_DRV_LOG(DEBUG, sc, "Setting SGMII mode");
4173 elink_warpcore_clear_regs(phy, params, lane);
4174 elink_warpcore_set_sgmii_speed(phy, params, 0, 1);
4176 switch (serdes_net_if) {
4177 case PORT_HW_CFG_NET_SERDES_IF_KR:
4178 /* Enable KR Auto Neg */
4179 if (params->loopback_mode != ELINK_LOOPBACK_EXT)
4180 elink_warpcore_enable_AN_KR(phy, params, vars);
4182 PMD_DRV_LOG(DEBUG, sc, "Setting KR 10G-Force");
4183 elink_warpcore_set_10G_KR(phy, params);
4187 case PORT_HW_CFG_NET_SERDES_IF_XFI:
4188 elink_warpcore_clear_regs(phy, params, lane);
4189 if (vars->line_speed == ELINK_SPEED_10000) {
4190 PMD_DRV_LOG(DEBUG, sc, "Setting 10G XFI");
4191 elink_warpcore_set_10G_XFI(phy, params, 1);
4193 if (ELINK_SINGLE_MEDIA_DIRECT(params)) {
4194 PMD_DRV_LOG(DEBUG, sc, "1G Fiber");
4197 PMD_DRV_LOG(DEBUG, sc, "10/100/1G SGMII");
4200 elink_warpcore_set_sgmii_speed(phy,
4207 case PORT_HW_CFG_NET_SERDES_IF_SFI:
4208 /* Issue Module detection if module is plugged, or
4209 * enabled transmitter to avoid current leakage in case
4210 * no module is connected
4212 if ((params->loopback_mode == ELINK_LOOPBACK_NONE) ||
4213 (params->loopback_mode == ELINK_LOOPBACK_EXT)) {
4214 if (elink_is_sfp_module_plugged(params))
4215 elink_sfp_module_detection(phy, params);
4217 elink_sfp_e3_set_transmitter(params,
4221 elink_warpcore_config_sfi(phy, params);
4224 case PORT_HW_CFG_NET_SERDES_IF_DXGXS:
4225 if (vars->line_speed != ELINK_SPEED_20000) {
4226 PMD_DRV_LOG(DEBUG, sc, "Speed not supported yet");
4229 PMD_DRV_LOG(DEBUG, sc, "Setting 20G DXGXS");
4230 elink_warpcore_set_20G_DXGXS(sc, phy, lane);
4231 /* Issue Module detection */
4233 elink_sfp_module_detection(phy, params);
4235 case PORT_HW_CFG_NET_SERDES_IF_KR2:
4236 if (!params->loopback_mode) {
4237 elink_warpcore_enable_AN_KR(phy, params, vars);
4239 PMD_DRV_LOG(DEBUG, sc, "Setting KR 20G-Force");
4240 elink_warpcore_set_20G_force_KR2(phy, params);
4244 PMD_DRV_LOG(DEBUG, sc,
4245 "Unsupported Serdes Net Interface 0x%x",
4251 /* Take lane out of reset after configuration is finished */
4252 elink_warpcore_reset_lane(sc, phy, 0);
4253 PMD_DRV_LOG(DEBUG, sc, "Exit config init");
4258 static void elink_warpcore_link_reset(struct elink_phy *phy,
4259 struct elink_params *params)
4261 struct bnx2x_softc *sc = params->sc;
4262 uint16_t val16, lane;
4263 elink_sfp_e3_set_transmitter(params, phy, 0);
4264 elink_set_mdio_emac_per_phy(sc, params);
4265 elink_set_aer_mmd(params, phy);
4266 /* Global register */
4267 elink_warpcore_reset_lane(sc, phy, 1);
4269 /* Clear loopback settings (if any) */
4271 elink_cl45_read_and_write(sc, phy, MDIO_WC_DEVAD,
4272 MDIO_WC_REG_COMBO_IEEE0_MIICTRL, 0xBFFF);
4274 elink_cl45_read_and_write(sc, phy, MDIO_WC_DEVAD,
4275 MDIO_WC_REG_IEEE0BLK_MIICNTL, 0xfffe);
4277 /* Update those 1-copy registers */
4278 CL22_WR_OVER_CL45(sc, phy, MDIO_REG_BANK_AER_BLOCK,
4279 MDIO_AER_BLOCK_AER_REG, 0);
4280 /* Enable 1G MDIO (1-copy) */
4281 elink_cl45_read_and_write(sc, phy, MDIO_WC_DEVAD,
4282 MDIO_WC_REG_XGXSBLK0_XGXSCONTROL, ~0x10);
4284 elink_cl45_read_and_write(sc, phy, MDIO_WC_DEVAD,
4285 MDIO_WC_REG_XGXSBLK1_LANECTRL2, 0xff00);
4286 lane = elink_get_warpcore_lane(params);
4287 /* Disable CL36 PCS Tx */
4288 elink_cl45_read(sc, phy, MDIO_WC_DEVAD,
4289 MDIO_WC_REG_XGXSBLK1_LANECTRL0, &val16);
4290 val16 |= (0x11 << lane);
4291 if (phy->flags & ELINK_FLAGS_WC_DUAL_MODE)
4292 val16 |= (0x22 << lane);
4293 elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
4294 MDIO_WC_REG_XGXSBLK1_LANECTRL0, val16);
4296 elink_cl45_read(sc, phy, MDIO_WC_DEVAD,
4297 MDIO_WC_REG_XGXSBLK1_LANECTRL1, &val16);
4298 val16 &= ~(0x0303 << (lane << 1));
4299 val16 |= (0x0101 << (lane << 1));
4300 if (phy->flags & ELINK_FLAGS_WC_DUAL_MODE) {
4301 val16 &= ~(0x0c0c << (lane << 1));
4302 val16 |= (0x0404 << (lane << 1));
4305 elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
4306 MDIO_WC_REG_XGXSBLK1_LANECTRL1, val16);
4308 elink_set_aer_mmd(params, phy);
4312 static void elink_set_warpcore_loopback(struct elink_phy *phy,
4313 struct elink_params *params)
4315 struct bnx2x_softc *sc = params->sc;
4318 PMD_DRV_LOG(DEBUG, sc, "Setting Warpcore loopback type %x, speed %d",
4319 params->loopback_mode, phy->req_line_speed);
4321 if (phy->req_line_speed < ELINK_SPEED_10000 ||
4322 phy->supported & ELINK_SUPPORTED_20000baseKR2_Full) {
4323 /* 10/100/1000/20G-KR2 */
4325 /* Update those 1-copy registers */
4326 CL22_WR_OVER_CL45(sc, phy, MDIO_REG_BANK_AER_BLOCK,
4327 MDIO_AER_BLOCK_AER_REG, 0);
4328 /* Enable 1G MDIO (1-copy) */
4329 elink_cl45_read_or_write(sc, phy, MDIO_WC_DEVAD,
4330 MDIO_WC_REG_XGXSBLK0_XGXSCONTROL,
4332 /* Set 1G loopback based on lane (1-copy) */
4333 lane = elink_get_warpcore_lane(params);
4334 elink_cl45_read(sc, phy, MDIO_WC_DEVAD,
4335 MDIO_WC_REG_XGXSBLK1_LANECTRL2, &val16);
4336 val16 |= (1 << lane);
4337 if (phy->flags & ELINK_FLAGS_WC_DUAL_MODE)
4338 val16 |= (2 << lane);
4339 elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
4340 MDIO_WC_REG_XGXSBLK1_LANECTRL2, val16);
4342 /* Switch back to 4-copy registers */
4343 elink_set_aer_mmd(params, phy);
4345 /* 10G / 20G-DXGXS */
4346 elink_cl45_read_or_write(sc, phy, MDIO_WC_DEVAD,
4347 MDIO_WC_REG_COMBO_IEEE0_MIICTRL,
4349 elink_cl45_read_or_write(sc, phy, MDIO_WC_DEVAD,
4350 MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x1);
4354 static void elink_sync_link(struct elink_params *params,
4355 struct elink_vars *vars)
4357 struct bnx2x_softc *sc = params->sc;
4358 uint8_t link_10g_plus;
4359 if (vars->link_status & LINK_STATUS_PHYSICAL_LINK_FLAG)
4360 vars->phy_flags |= PHY_PHYSICAL_LINK_FLAG;
4361 vars->link_up = (vars->link_status & LINK_STATUS_LINK_UP);
4362 if (vars->link_up) {
4363 PMD_DRV_LOG(DEBUG, sc, "phy link up");
4365 vars->phy_link_up = 1;
4366 vars->duplex = DUPLEX_FULL;
4367 switch (vars->link_status & LINK_STATUS_SPEED_AND_DUPLEX_MASK) {
4368 case ELINK_LINK_10THD:
4369 vars->duplex = DUPLEX_HALF;
4371 case ELINK_LINK_10TFD:
4372 vars->line_speed = ELINK_SPEED_10;
4375 case ELINK_LINK_100TXHD:
4376 vars->duplex = DUPLEX_HALF;
4378 case ELINK_LINK_100T4:
4379 case ELINK_LINK_100TXFD:
4380 vars->line_speed = ELINK_SPEED_100;
4383 case ELINK_LINK_1000THD:
4384 vars->duplex = DUPLEX_HALF;
4386 case ELINK_LINK_1000TFD:
4387 vars->line_speed = ELINK_SPEED_1000;
4390 case ELINK_LINK_2500THD:
4391 vars->duplex = DUPLEX_HALF;
4393 case ELINK_LINK_2500TFD:
4394 vars->line_speed = ELINK_SPEED_2500;
4397 case ELINK_LINK_10GTFD:
4398 vars->line_speed = ELINK_SPEED_10000;
4400 case ELINK_LINK_20GTFD:
4401 vars->line_speed = ELINK_SPEED_20000;
4406 vars->flow_ctrl = 0;
4407 if (vars->link_status & LINK_STATUS_TX_FLOW_CONTROL_ENABLED)
4408 vars->flow_ctrl |= ELINK_FLOW_CTRL_TX;
4410 if (vars->link_status & LINK_STATUS_RX_FLOW_CONTROL_ENABLED)
4411 vars->flow_ctrl |= ELINK_FLOW_CTRL_RX;
4413 if (!vars->flow_ctrl)
4414 vars->flow_ctrl = ELINK_FLOW_CTRL_NONE;
4416 if (vars->line_speed &&
4417 ((vars->line_speed == ELINK_SPEED_10) ||
4418 (vars->line_speed == ELINK_SPEED_100))) {
4419 vars->phy_flags |= PHY_SGMII_FLAG;
4421 vars->phy_flags &= ~PHY_SGMII_FLAG;
4423 if (vars->line_speed &&
4424 USES_WARPCORE(sc) && (vars->line_speed == ELINK_SPEED_1000))
4425 vars->phy_flags |= PHY_SGMII_FLAG;
4426 /* Anything 10 and over uses the bmac */
4427 link_10g_plus = (vars->line_speed >= ELINK_SPEED_10000);
4429 if (link_10g_plus) {
4430 if (USES_WARPCORE(sc))
4431 vars->mac_type = ELINK_MAC_TYPE_XMAC;
4433 vars->mac_type = ELINK_MAC_TYPE_BMAC;
4435 if (USES_WARPCORE(sc))
4436 vars->mac_type = ELINK_MAC_TYPE_UMAC;
4438 vars->mac_type = ELINK_MAC_TYPE_EMAC;
4440 } else { /* Link down */
4441 PMD_DRV_LOG(DEBUG, sc, "phy link down");
4443 vars->phy_link_up = 0;
4445 vars->line_speed = 0;
4446 vars->duplex = DUPLEX_FULL;
4447 vars->flow_ctrl = ELINK_FLOW_CTRL_NONE;
4449 /* Indicate no mac active */
4450 vars->mac_type = ELINK_MAC_TYPE_NONE;
4451 if (vars->link_status & LINK_STATUS_PHYSICAL_LINK_FLAG)
4452 vars->phy_flags |= PHY_HALF_OPEN_CONN_FLAG;
4453 if (vars->link_status & LINK_STATUS_SFP_TX_FAULT)
4454 vars->phy_flags |= PHY_SFP_TX_FAULT_FLAG;
4458 void elink_link_status_update(struct elink_params *params,
4459 struct elink_vars *vars)
4461 struct bnx2x_softc *sc = params->sc;
4462 uint8_t port = params->port;
4463 uint32_t sync_offset, media_types;
4464 /* Update PHY configuration */
4465 set_phy_vars(params, vars);
4467 vars->link_status = REG_RD(sc, params->shmem_base +
4468 offsetof(struct shmem_region,
4469 port_mb[port].link_status));
4471 /* Force link UP in non LOOPBACK_EXT loopback mode(s) */
4472 if (params->loopback_mode != ELINK_LOOPBACK_NONE &&
4473 params->loopback_mode != ELINK_LOOPBACK_EXT)
4474 vars->link_status |= LINK_STATUS_LINK_UP;
4476 if (elink_eee_has_cap(params))
4477 vars->eee_status = REG_RD(sc, params->shmem2_base +
4478 offsetof(struct shmem2_region,
4479 eee_status[params->port]));
4481 vars->phy_flags = PHY_XGXS_FLAG;
4482 elink_sync_link(params, vars);
4483 /* Sync media type */
4484 sync_offset = params->shmem_base +
4485 offsetof(struct shmem_region,
4486 dev_info.port_hw_config[port].media_type);
4487 media_types = REG_RD(sc, sync_offset);
4489 params->phy[ELINK_INT_PHY].media_type =
4490 (media_types & PORT_HW_CFG_MEDIA_TYPE_PHY0_MASK) >>
4491 PORT_HW_CFG_MEDIA_TYPE_PHY0_SHIFT;
4492 params->phy[ELINK_EXT_PHY1].media_type =
4493 (media_types & PORT_HW_CFG_MEDIA_TYPE_PHY1_MASK) >>
4494 PORT_HW_CFG_MEDIA_TYPE_PHY1_SHIFT;
4495 params->phy[ELINK_EXT_PHY2].media_type =
4496 (media_types & PORT_HW_CFG_MEDIA_TYPE_PHY2_MASK) >>
4497 PORT_HW_CFG_MEDIA_TYPE_PHY2_SHIFT;
4498 PMD_DRV_LOG(DEBUG, sc, "media_types = 0x%x", media_types);
4500 /* Sync AEU offset */
4501 sync_offset = params->shmem_base +
4502 offsetof(struct shmem_region,
4503 dev_info.port_hw_config[port].aeu_int_mask);
4505 vars->aeu_int_mask = REG_RD(sc, sync_offset);
4507 /* Sync PFC status */
4508 if (vars->link_status & LINK_STATUS_PFC_ENABLED)
4509 params->feature_config_flags |=
4510 ELINK_FEATURE_CONFIG_PFC_ENABLED;
4512 params->feature_config_flags &=
4513 ~ELINK_FEATURE_CONFIG_PFC_ENABLED;
4515 if (SHMEM2_HAS(sc, link_attr_sync))
4516 vars->link_attr_sync = SHMEM2_RD(sc,
4517 link_attr_sync[params->port]);
4519 PMD_DRV_LOG(DEBUG, sc, "link_status 0x%x phy_link_up %x int_mask 0x%x",
4520 vars->link_status, vars->phy_link_up, vars->aeu_int_mask);
4521 PMD_DRV_LOG(DEBUG, sc, "line_speed %x duplex %x flow_ctrl 0x%x",
4522 vars->line_speed, vars->duplex, vars->flow_ctrl);
4525 static void elink_set_master_ln(struct elink_params *params,
4526 struct elink_phy *phy)
4528 struct bnx2x_softc *sc = params->sc;
4529 uint16_t new_master_ln, ser_lane;
4530 ser_lane = ((params->lane_config &
4531 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK) >>
4532 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT);
4534 /* Set the master_ln for AN */
4535 CL22_RD_OVER_CL45(sc, phy,
4536 MDIO_REG_BANK_XGXS_BLOCK2,
4537 MDIO_XGXS_BLOCK2_TEST_MODE_LANE, &new_master_ln);
4539 CL22_WR_OVER_CL45(sc, phy,
4540 MDIO_REG_BANK_XGXS_BLOCK2,
4541 MDIO_XGXS_BLOCK2_TEST_MODE_LANE,
4542 (new_master_ln | ser_lane));
4545 static elink_status_t elink_reset_unicore(struct elink_params *params,
4546 struct elink_phy *phy,
4549 struct bnx2x_softc *sc = params->sc;
4550 uint16_t mii_control;
4552 CL22_RD_OVER_CL45(sc, phy,
4553 MDIO_REG_BANK_COMBO_IEEE0,
4554 MDIO_COMBO_IEEE0_MII_CONTROL, &mii_control);
4556 /* Reset the unicore */
4557 CL22_WR_OVER_CL45(sc, phy,
4558 MDIO_REG_BANK_COMBO_IEEE0,
4559 MDIO_COMBO_IEEE0_MII_CONTROL,
4560 (mii_control | MDIO_COMBO_IEEO_MII_CONTROL_RESET));
4562 elink_set_serdes_access(sc, params->port);
4564 /* Wait for the reset to self clear */
4565 for (i = 0; i < ELINK_MDIO_ACCESS_TIMEOUT; i++) {
4568 /* The reset erased the previous bank value */
4569 CL22_RD_OVER_CL45(sc, phy,
4570 MDIO_REG_BANK_COMBO_IEEE0,
4571 MDIO_COMBO_IEEE0_MII_CONTROL, &mii_control);
4573 if (!(mii_control & MDIO_COMBO_IEEO_MII_CONTROL_RESET)) {
4575 return ELINK_STATUS_OK;
4579 elink_cb_event_log(sc, ELINK_LOG_ID_PHY_UNINITIALIZED, params->port); // "Warning: PHY was not initialized,"
4582 PMD_DRV_LOG(DEBUG, sc, "BUG! XGXS is still in reset!");
4583 return ELINK_STATUS_ERROR;
4587 static void elink_set_swap_lanes(struct elink_params *params,
4588 struct elink_phy *phy)
4590 struct bnx2x_softc *sc = params->sc;
4591 /* Each two bits represents a lane number:
4592 * No swap is 0123 => 0x1b no need to enable the swap
4594 uint16_t rx_lane_swap, tx_lane_swap;
4596 rx_lane_swap = ((params->lane_config &
4597 PORT_HW_CFG_LANE_SWAP_CFG_RX_MASK) >>
4598 PORT_HW_CFG_LANE_SWAP_CFG_RX_SHIFT);
4599 tx_lane_swap = ((params->lane_config &
4600 PORT_HW_CFG_LANE_SWAP_CFG_TX_MASK) >>
4601 PORT_HW_CFG_LANE_SWAP_CFG_TX_SHIFT);
4603 if (rx_lane_swap != 0x1b) {
4604 CL22_WR_OVER_CL45(sc, phy,
4605 MDIO_REG_BANK_XGXS_BLOCK2,
4606 MDIO_XGXS_BLOCK2_RX_LN_SWAP,
4608 MDIO_XGXS_BLOCK2_RX_LN_SWAP_ENABLE |
4609 MDIO_XGXS_BLOCK2_RX_LN_SWAP_FORCE_ENABLE));
4611 CL22_WR_OVER_CL45(sc, phy,
4612 MDIO_REG_BANK_XGXS_BLOCK2,
4613 MDIO_XGXS_BLOCK2_RX_LN_SWAP, 0);
4616 if (tx_lane_swap != 0x1b) {
4617 CL22_WR_OVER_CL45(sc, phy,
4618 MDIO_REG_BANK_XGXS_BLOCK2,
4619 MDIO_XGXS_BLOCK2_TX_LN_SWAP,
4621 MDIO_XGXS_BLOCK2_TX_LN_SWAP_ENABLE));
4623 CL22_WR_OVER_CL45(sc, phy,
4624 MDIO_REG_BANK_XGXS_BLOCK2,
4625 MDIO_XGXS_BLOCK2_TX_LN_SWAP, 0);
4629 static void elink_set_parallel_detection(struct elink_phy *phy,
4630 struct elink_params *params)
4632 struct bnx2x_softc *sc = params->sc;
4634 CL22_RD_OVER_CL45(sc, phy,
4635 MDIO_REG_BANK_SERDES_DIGITAL,
4636 MDIO_SERDES_DIGITAL_A_1000X_CONTROL2, &control2);
4637 if (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)
4638 control2 |= MDIO_SERDES_DIGITAL_A_1000X_CONTROL2_PRL_DT_EN;
4640 control2 &= ~MDIO_SERDES_DIGITAL_A_1000X_CONTROL2_PRL_DT_EN;
4641 PMD_DRV_LOG(DEBUG, sc, "phy->speed_cap_mask = 0x%x, control2 = 0x%x",
4642 phy->speed_cap_mask, control2);
4643 CL22_WR_OVER_CL45(sc, phy,
4644 MDIO_REG_BANK_SERDES_DIGITAL,
4645 MDIO_SERDES_DIGITAL_A_1000X_CONTROL2, control2);
4647 if ((phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) &&
4648 (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) {
4649 PMD_DRV_LOG(DEBUG, sc, "XGXS");
4651 CL22_WR_OVER_CL45(sc, phy,
4652 MDIO_REG_BANK_10G_PARALLEL_DETECT,
4653 MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_LINK,
4654 MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_LINK_CNT);
4656 CL22_RD_OVER_CL45(sc, phy,
4657 MDIO_REG_BANK_10G_PARALLEL_DETECT,
4658 MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL,
4662 MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL_PARDET10G_EN;
4664 CL22_WR_OVER_CL45(sc, phy,
4665 MDIO_REG_BANK_10G_PARALLEL_DETECT,
4666 MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL,
4669 /* Disable parallel detection of HiG */
4670 CL22_WR_OVER_CL45(sc, phy,
4671 MDIO_REG_BANK_XGXS_BLOCK2,
4672 MDIO_XGXS_BLOCK2_UNICORE_MODE_10G,
4673 MDIO_XGXS_BLOCK2_UNICORE_MODE_10G_CX4_XGXS |
4674 MDIO_XGXS_BLOCK2_UNICORE_MODE_10G_HIGIG_XGXS);
4678 static void elink_set_autoneg(struct elink_phy *phy,
4679 struct elink_params *params,
4680 struct elink_vars *vars, uint8_t enable_cl73)
4682 struct bnx2x_softc *sc = params->sc;
4686 CL22_RD_OVER_CL45(sc, phy,
4687 MDIO_REG_BANK_COMBO_IEEE0,
4688 MDIO_COMBO_IEEE0_MII_CONTROL, ®_val);
4690 /* CL37 Autoneg Enabled */
4691 if (vars->line_speed == ELINK_SPEED_AUTO_NEG)
4692 reg_val |= MDIO_COMBO_IEEO_MII_CONTROL_AN_EN;
4693 else /* CL37 Autoneg Disabled */
4694 reg_val &= ~(MDIO_COMBO_IEEO_MII_CONTROL_AN_EN |
4695 MDIO_COMBO_IEEO_MII_CONTROL_RESTART_AN);
4697 CL22_WR_OVER_CL45(sc, phy,
4698 MDIO_REG_BANK_COMBO_IEEE0,
4699 MDIO_COMBO_IEEE0_MII_CONTROL, reg_val);
4701 /* Enable/Disable Autodetection */
4703 CL22_RD_OVER_CL45(sc, phy,
4704 MDIO_REG_BANK_SERDES_DIGITAL,
4705 MDIO_SERDES_DIGITAL_A_1000X_CONTROL1, ®_val);
4706 reg_val &= ~(MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_SIGNAL_DETECT_EN |
4707 MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_INVERT_SIGNAL_DETECT);
4708 reg_val |= MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_FIBER_MODE;
4709 if (vars->line_speed == ELINK_SPEED_AUTO_NEG)
4710 reg_val |= MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_AUTODET;
4712 reg_val &= ~MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_AUTODET;
4714 CL22_WR_OVER_CL45(sc, phy,
4715 MDIO_REG_BANK_SERDES_DIGITAL,
4716 MDIO_SERDES_DIGITAL_A_1000X_CONTROL1, reg_val);
4718 /* Enable TetonII and BAM autoneg */
4719 CL22_RD_OVER_CL45(sc, phy,
4720 MDIO_REG_BANK_BAM_NEXT_PAGE,
4721 MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL, ®_val);
4722 if (vars->line_speed == ELINK_SPEED_AUTO_NEG) {
4723 /* Enable BAM aneg Mode and TetonII aneg Mode */
4724 reg_val |= (MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_BAM_MODE |
4725 MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_TETON_AN);
4727 /* TetonII and BAM Autoneg Disabled */
4728 reg_val &= ~(MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_BAM_MODE |
4729 MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_TETON_AN);
4731 CL22_WR_OVER_CL45(sc, phy,
4732 MDIO_REG_BANK_BAM_NEXT_PAGE,
4733 MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL, reg_val);
4736 /* Enable Cl73 FSM status bits */
4737 CL22_WR_OVER_CL45(sc, phy,
4738 MDIO_REG_BANK_CL73_USERB0,
4739 MDIO_CL73_USERB0_CL73_UCTRL, 0xe);
4741 /* Enable BAM Station Manager */
4742 CL22_WR_OVER_CL45(sc, phy,
4743 MDIO_REG_BANK_CL73_USERB0,
4744 MDIO_CL73_USERB0_CL73_BAM_CTRL1,
4745 MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_EN |
4746 MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_STATION_MNGR_EN
4748 MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_NP_AFTER_BP_EN);
4750 /* Advertise CL73 link speeds */
4751 CL22_RD_OVER_CL45(sc, phy,
4752 MDIO_REG_BANK_CL73_IEEEB1,
4753 MDIO_CL73_IEEEB1_AN_ADV2, ®_val);
4754 if (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)
4755 reg_val |= MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KX4;
4756 if (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)
4757 reg_val |= MDIO_CL73_IEEEB1_AN_ADV2_ADVR_1000M_KX;
4759 CL22_WR_OVER_CL45(sc, phy,
4760 MDIO_REG_BANK_CL73_IEEEB1,
4761 MDIO_CL73_IEEEB1_AN_ADV2, reg_val);
4763 /* CL73 Autoneg Enabled */
4764 reg_val = MDIO_CL73_IEEEB0_CL73_AN_CONTROL_AN_EN;
4766 } else /* CL73 Autoneg Disabled */
4769 CL22_WR_OVER_CL45(sc, phy,
4770 MDIO_REG_BANK_CL73_IEEEB0,
4771 MDIO_CL73_IEEEB0_CL73_AN_CONTROL, reg_val);
4774 /* Program SerDes, forced speed */
4775 static void elink_program_serdes(struct elink_phy *phy,
4776 struct elink_params *params,
4777 struct elink_vars *vars)
4779 struct bnx2x_softc *sc = params->sc;
4782 /* Program duplex, disable autoneg and sgmii */
4783 CL22_RD_OVER_CL45(sc, phy,
4784 MDIO_REG_BANK_COMBO_IEEE0,
4785 MDIO_COMBO_IEEE0_MII_CONTROL, ®_val);
4786 reg_val &= ~(MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX |
4787 MDIO_COMBO_IEEO_MII_CONTROL_AN_EN |
4788 MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_MASK);
4789 if (phy->req_duplex == DUPLEX_FULL)
4790 reg_val |= MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX;
4791 CL22_WR_OVER_CL45(sc, phy,
4792 MDIO_REG_BANK_COMBO_IEEE0,
4793 MDIO_COMBO_IEEE0_MII_CONTROL, reg_val);
4796 * - needed only if the speed is greater than 1G (2.5G or 10G)
4798 CL22_RD_OVER_CL45(sc, phy,
4799 MDIO_REG_BANK_SERDES_DIGITAL,
4800 MDIO_SERDES_DIGITAL_MISC1, ®_val);
4801 /* Clearing the speed value before setting the right speed */
4802 PMD_DRV_LOG(DEBUG, sc, "MDIO_REG_BANK_SERDES_DIGITAL = 0x%x", reg_val);
4804 reg_val &= ~(MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_MASK |
4805 MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_SEL);
4807 if (!((vars->line_speed == ELINK_SPEED_1000) ||
4808 (vars->line_speed == ELINK_SPEED_100) ||
4809 (vars->line_speed == ELINK_SPEED_10))) {
4811 reg_val |= (MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_156_25M |
4812 MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_SEL);
4813 if (vars->line_speed == ELINK_SPEED_10000)
4815 MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_10G_CX4;
4818 CL22_WR_OVER_CL45(sc, phy,
4819 MDIO_REG_BANK_SERDES_DIGITAL,
4820 MDIO_SERDES_DIGITAL_MISC1, reg_val);
4824 static void elink_set_brcm_cl37_advertisement(struct elink_phy *phy,
4825 struct elink_params *params)
4827 struct bnx2x_softc *sc = params->sc;
4830 /* Set extended capabilities */
4831 if (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G)
4832 val |= MDIO_OVER_1G_UP1_2_5G;
4833 if (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)
4834 val |= MDIO_OVER_1G_UP1_10G;
4835 CL22_WR_OVER_CL45(sc, phy,
4836 MDIO_REG_BANK_OVER_1G, MDIO_OVER_1G_UP1, val);
4838 CL22_WR_OVER_CL45(sc, phy,
4839 MDIO_REG_BANK_OVER_1G, MDIO_OVER_1G_UP3, 0x400);
4842 static void elink_set_ieee_aneg_advertisement(struct elink_phy *phy,
4843 struct elink_params *params,
4846 struct bnx2x_softc *sc = params->sc;
4848 /* For AN, we are always publishing full duplex */
4850 CL22_WR_OVER_CL45(sc, phy,
4851 MDIO_REG_BANK_COMBO_IEEE0,
4852 MDIO_COMBO_IEEE0_AUTO_NEG_ADV, ieee_fc);
4853 CL22_RD_OVER_CL45(sc, phy,
4854 MDIO_REG_BANK_CL73_IEEEB1,
4855 MDIO_CL73_IEEEB1_AN_ADV1, &val);
4856 val &= ~MDIO_CL73_IEEEB1_AN_ADV1_PAUSE_BOTH;
4857 val |= ((ieee_fc << 3) & MDIO_CL73_IEEEB1_AN_ADV1_PAUSE_MASK);
4858 CL22_WR_OVER_CL45(sc, phy,
4859 MDIO_REG_BANK_CL73_IEEEB1,
4860 MDIO_CL73_IEEEB1_AN_ADV1, val);
4863 static void elink_restart_autoneg(struct elink_phy *phy,
4864 struct elink_params *params,
4865 uint8_t enable_cl73)
4867 struct bnx2x_softc *sc = params->sc;
4868 uint16_t mii_control;
4870 PMD_DRV_LOG(DEBUG, sc, "elink_restart_autoneg");
4871 /* Enable and restart BAM/CL37 aneg */
4874 CL22_RD_OVER_CL45(sc, phy,
4875 MDIO_REG_BANK_CL73_IEEEB0,
4876 MDIO_CL73_IEEEB0_CL73_AN_CONTROL,
4879 CL22_WR_OVER_CL45(sc, phy,
4880 MDIO_REG_BANK_CL73_IEEEB0,
4881 MDIO_CL73_IEEEB0_CL73_AN_CONTROL,
4883 MDIO_CL73_IEEEB0_CL73_AN_CONTROL_AN_EN |
4884 MDIO_CL73_IEEEB0_CL73_AN_CONTROL_RESTART_AN));
4887 CL22_RD_OVER_CL45(sc, phy,
4888 MDIO_REG_BANK_COMBO_IEEE0,
4889 MDIO_COMBO_IEEE0_MII_CONTROL, &mii_control);
4890 PMD_DRV_LOG(DEBUG, sc,
4891 "elink_restart_autoneg mii_control before = 0x%x",
4893 CL22_WR_OVER_CL45(sc, phy,
4894 MDIO_REG_BANK_COMBO_IEEE0,
4895 MDIO_COMBO_IEEE0_MII_CONTROL,
4897 MDIO_COMBO_IEEO_MII_CONTROL_AN_EN |
4898 MDIO_COMBO_IEEO_MII_CONTROL_RESTART_AN));
4902 static void elink_initialize_sgmii_process(struct elink_phy *phy,
4903 struct elink_params *params,
4904 struct elink_vars *vars)
4906 struct bnx2x_softc *sc = params->sc;
4909 /* In SGMII mode, the unicore is always slave */
4911 CL22_RD_OVER_CL45(sc, phy,
4912 MDIO_REG_BANK_SERDES_DIGITAL,
4913 MDIO_SERDES_DIGITAL_A_1000X_CONTROL1, &control1);
4914 control1 |= MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_INVERT_SIGNAL_DETECT;
4915 /* Set sgmii mode (and not fiber) */
4916 control1 &= ~(MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_FIBER_MODE |
4917 MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_AUTODET |
4918 MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_MSTR_MODE);
4919 CL22_WR_OVER_CL45(sc, phy,
4920 MDIO_REG_BANK_SERDES_DIGITAL,
4921 MDIO_SERDES_DIGITAL_A_1000X_CONTROL1, control1);
4923 /* If forced speed */
4924 if (!(vars->line_speed == ELINK_SPEED_AUTO_NEG)) {
4925 /* Set speed, disable autoneg */
4926 uint16_t mii_control;
4928 CL22_RD_OVER_CL45(sc, phy,
4929 MDIO_REG_BANK_COMBO_IEEE0,
4930 MDIO_COMBO_IEEE0_MII_CONTROL, &mii_control);
4931 mii_control &= ~(MDIO_COMBO_IEEO_MII_CONTROL_AN_EN |
4932 MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_MASK |
4933 MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX);
4935 switch (vars->line_speed) {
4936 case ELINK_SPEED_100:
4938 MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_100;
4940 case ELINK_SPEED_1000:
4942 MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_1000;
4944 case ELINK_SPEED_10:
4945 /* There is nothing to set for 10M */
4948 /* Invalid speed for SGMII */
4949 PMD_DRV_LOG(DEBUG, sc, "Invalid line_speed 0x%x",
4954 /* Setting the full duplex */
4955 if (phy->req_duplex == DUPLEX_FULL)
4956 mii_control |= MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX;
4957 CL22_WR_OVER_CL45(sc, phy,
4958 MDIO_REG_BANK_COMBO_IEEE0,
4959 MDIO_COMBO_IEEE0_MII_CONTROL, mii_control);
4961 } else { /* AN mode */
4962 /* Enable and restart AN */
4963 elink_restart_autoneg(phy, params, 0);
4969 static elink_status_t elink_direct_parallel_detect_used(struct elink_phy *phy,
4973 struct bnx2x_softc *sc = params->sc;
4974 uint16_t pd_10g, status2_1000x;
4975 if (phy->req_line_speed != ELINK_SPEED_AUTO_NEG)
4976 return ELINK_STATUS_OK;
4977 CL22_RD_OVER_CL45(sc, phy,
4978 MDIO_REG_BANK_SERDES_DIGITAL,
4979 MDIO_SERDES_DIGITAL_A_1000X_STATUS2, &status2_1000x);
4980 CL22_RD_OVER_CL45(sc, phy,
4981 MDIO_REG_BANK_SERDES_DIGITAL,
4982 MDIO_SERDES_DIGITAL_A_1000X_STATUS2, &status2_1000x);
4983 if (status2_1000x & MDIO_SERDES_DIGITAL_A_1000X_STATUS2_AN_DISABLED) {
4984 PMD_DRV_LOG(DEBUG, sc, "1G parallel detect link on port %d",
4986 return ELINK_STATUS_ERROR;
4989 CL22_RD_OVER_CL45(sc, phy,
4990 MDIO_REG_BANK_10G_PARALLEL_DETECT,
4991 MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_STATUS, &pd_10g);
4993 if (pd_10g & MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_STATUS_PD_LINK) {
4994 PMD_DRV_LOG(DEBUG, sc, "10G parallel detect link on port %d",
4996 return ELINK_STATUS_ERROR;
4998 return ELINK_STATUS_OK;
5001 static void elink_update_adv_fc(struct elink_phy *phy,
5002 struct elink_params *params,
5003 struct elink_vars *vars, uint32_t gp_status)
5005 uint16_t ld_pause; /* local driver */
5006 uint16_t lp_pause; /* link partner */
5007 uint16_t pause_result;
5008 struct bnx2x_softc *sc = params->sc;
5010 (MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_AUTONEG_COMPLETE |
5011 MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_MR_LP_NP_AN_ABLE)) ==
5012 (MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_AUTONEG_COMPLETE |
5013 MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_MR_LP_NP_AN_ABLE)) {
5015 CL22_RD_OVER_CL45(sc, phy,
5016 MDIO_REG_BANK_CL73_IEEEB1,
5017 MDIO_CL73_IEEEB1_AN_ADV1, &ld_pause);
5018 CL22_RD_OVER_CL45(sc, phy,
5019 MDIO_REG_BANK_CL73_IEEEB1,
5020 MDIO_CL73_IEEEB1_AN_LP_ADV1, &lp_pause);
5021 pause_result = (ld_pause &
5022 MDIO_CL73_IEEEB1_AN_ADV1_PAUSE_MASK) >> 8;
5023 pause_result |= (lp_pause &
5024 MDIO_CL73_IEEEB1_AN_LP_ADV1_PAUSE_MASK) >> 10;
5025 PMD_DRV_LOG(DEBUG, sc, "pause_result CL73 0x%x", pause_result);
5027 CL22_RD_OVER_CL45(sc, phy,
5028 MDIO_REG_BANK_COMBO_IEEE0,
5029 MDIO_COMBO_IEEE0_AUTO_NEG_ADV, &ld_pause);
5030 CL22_RD_OVER_CL45(sc, phy,
5031 MDIO_REG_BANK_COMBO_IEEE0,
5032 MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1,
5034 pause_result = (ld_pause &
5035 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK) >> 5;
5036 pause_result |= (lp_pause &
5037 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK) >> 7;
5038 PMD_DRV_LOG(DEBUG, sc, "pause_result CL37 0x%x", pause_result);
5040 elink_pause_resolve(vars, pause_result);
5044 static void elink_flow_ctrl_resolve(struct elink_phy *phy,
5045 struct elink_params *params,
5046 struct elink_vars *vars, uint32_t gp_status)
5048 vars->flow_ctrl = ELINK_FLOW_CTRL_NONE;
5050 /* Resolve from gp_status in case of AN complete and not sgmii */
5051 if (phy->req_flow_ctrl != ELINK_FLOW_CTRL_AUTO) {
5052 /* Update the advertised flow-controled of LD/LP in AN */
5053 if (phy->req_line_speed == ELINK_SPEED_AUTO_NEG)
5054 elink_update_adv_fc(phy, params, vars, gp_status);
5055 /* But set the flow-control result as the requested one */
5056 vars->flow_ctrl = phy->req_flow_ctrl;
5057 } else if (phy->req_line_speed != ELINK_SPEED_AUTO_NEG)
5058 vars->flow_ctrl = params->req_fc_auto_adv;
5059 else if ((gp_status & ELINK_MDIO_AN_CL73_OR_37_COMPLETE) &&
5060 (!(vars->phy_flags & PHY_SGMII_FLAG))) {
5061 if (elink_direct_parallel_detect_used(phy, params)) {
5062 vars->flow_ctrl = params->req_fc_auto_adv;
5065 elink_update_adv_fc(phy, params, vars, gp_status);
5067 PMD_DRV_LOG(DEBUG, params->sc, "flow_ctrl 0x%x", vars->flow_ctrl);
5070 static void elink_check_fallback_to_cl37(struct elink_phy *phy,
5071 struct elink_params *params)
5073 struct bnx2x_softc *sc = params->sc;
5074 uint16_t rx_status, ustat_val, cl37_fsm_received;
5075 PMD_DRV_LOG(DEBUG, sc, "elink_check_fallback_to_cl37");
5076 /* Step 1: Make sure signal is detected */
5077 CL22_RD_OVER_CL45(sc, phy,
5078 MDIO_REG_BANK_RX0, MDIO_RX0_RX_STATUS, &rx_status);
5079 if ((rx_status & MDIO_RX0_RX_STATUS_SIGDET) !=
5080 (MDIO_RX0_RX_STATUS_SIGDET)) {
5081 PMD_DRV_LOG(DEBUG, sc, "Signal is not detected. Restoring CL73."
5082 "rx_status(0x80b0) = 0x%x", rx_status);
5083 CL22_WR_OVER_CL45(sc, phy,
5084 MDIO_REG_BANK_CL73_IEEEB0,
5085 MDIO_CL73_IEEEB0_CL73_AN_CONTROL,
5086 MDIO_CL73_IEEEB0_CL73_AN_CONTROL_AN_EN);
5089 /* Step 2: Check CL73 state machine */
5090 CL22_RD_OVER_CL45(sc, phy,
5091 MDIO_REG_BANK_CL73_USERB0,
5092 MDIO_CL73_USERB0_CL73_USTAT1, &ustat_val);
5094 (MDIO_CL73_USERB0_CL73_USTAT1_LINK_STATUS_CHECK |
5095 MDIO_CL73_USERB0_CL73_USTAT1_AN_GOOD_CHECK_BAM37)) !=
5096 (MDIO_CL73_USERB0_CL73_USTAT1_LINK_STATUS_CHECK |
5097 MDIO_CL73_USERB0_CL73_USTAT1_AN_GOOD_CHECK_BAM37)) {
5098 PMD_DRV_LOG(DEBUG, sc, "CL73 state-machine is not stable. "
5099 "ustat_val(0x8371) = 0x%x", ustat_val);
5102 /* Step 3: Check CL37 Message Pages received to indicate LP
5103 * supports only CL37
5105 CL22_RD_OVER_CL45(sc, phy,
5106 MDIO_REG_BANK_REMOTE_PHY,
5107 MDIO_REMOTE_PHY_MISC_RX_STATUS, &cl37_fsm_received);
5108 if ((cl37_fsm_received &
5109 (MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_OVER1G_MSG |
5110 MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_BRCM_OUI_MSG)) !=
5111 (MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_OVER1G_MSG |
5112 MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_BRCM_OUI_MSG)) {
5113 PMD_DRV_LOG(DEBUG, sc, "No CL37 FSM were received. "
5114 "misc_rx_status(0x8330) = 0x%x", cl37_fsm_received);
5117 /* The combined cl37/cl73 fsm state information indicating that
5118 * we are connected to a device which does not support cl73, but
5119 * does support cl37 BAM. In this case we disable cl73 and
5120 * restart cl37 auto-neg
5124 CL22_WR_OVER_CL45(sc, phy,
5125 MDIO_REG_BANK_CL73_IEEEB0,
5126 MDIO_CL73_IEEEB0_CL73_AN_CONTROL, 0);
5127 /* Restart CL37 autoneg */
5128 elink_restart_autoneg(phy, params, 0);
5129 PMD_DRV_LOG(DEBUG, sc, "Disabling CL73, and restarting CL37 autoneg");
5132 static void elink_xgxs_an_resolve(struct elink_phy *phy,
5133 struct elink_params *params,
5134 struct elink_vars *vars, uint32_t gp_status)
5136 if (gp_status & ELINK_MDIO_AN_CL73_OR_37_COMPLETE)
5137 vars->link_status |= LINK_STATUS_AUTO_NEGOTIATE_COMPLETE;
5139 if (elink_direct_parallel_detect_used(phy, params))
5140 vars->link_status |= LINK_STATUS_PARALLEL_DETECTION_USED;
5143 static elink_status_t elink_get_link_speed_duplex(struct elink_phy *phy,
5144 struct elink_params *params __rte_unused,
5145 struct elink_vars *vars,
5146 uint16_t is_link_up,
5147 uint16_t speed_mask,
5150 if (phy->req_line_speed == ELINK_SPEED_AUTO_NEG)
5151 vars->link_status |= LINK_STATUS_AUTO_NEGOTIATE_ENABLED;
5153 PMD_DRV_LOG(DEBUG, params->sc, "phy link up");
5155 vars->phy_link_up = 1;
5156 vars->link_status |= LINK_STATUS_LINK_UP;
5158 switch (speed_mask) {
5159 case ELINK_GP_STATUS_10M:
5160 vars->line_speed = ELINK_SPEED_10;
5161 if (is_duplex == DUPLEX_FULL)
5162 vars->link_status |= ELINK_LINK_10TFD;
5164 vars->link_status |= ELINK_LINK_10THD;
5167 case ELINK_GP_STATUS_100M:
5168 vars->line_speed = ELINK_SPEED_100;
5169 if (is_duplex == DUPLEX_FULL)
5170 vars->link_status |= ELINK_LINK_100TXFD;
5172 vars->link_status |= ELINK_LINK_100TXHD;
5175 case ELINK_GP_STATUS_1G:
5176 case ELINK_GP_STATUS_1G_KX:
5177 vars->line_speed = ELINK_SPEED_1000;
5178 if (is_duplex == DUPLEX_FULL)
5179 vars->link_status |= ELINK_LINK_1000TFD;
5181 vars->link_status |= ELINK_LINK_1000THD;
5184 case ELINK_GP_STATUS_2_5G:
5185 vars->line_speed = ELINK_SPEED_2500;
5186 if (is_duplex == DUPLEX_FULL)
5187 vars->link_status |= ELINK_LINK_2500TFD;
5189 vars->link_status |= ELINK_LINK_2500THD;
5192 case ELINK_GP_STATUS_5G:
5193 case ELINK_GP_STATUS_6G:
5194 PMD_DRV_LOG(DEBUG, params->sc,
5195 "link speed unsupported gp_status 0x%x",
5197 return ELINK_STATUS_ERROR;
5199 case ELINK_GP_STATUS_10G_KX4:
5200 case ELINK_GP_STATUS_10G_HIG:
5201 case ELINK_GP_STATUS_10G_CX4:
5202 case ELINK_GP_STATUS_10G_KR:
5203 case ELINK_GP_STATUS_10G_SFI:
5204 case ELINK_GP_STATUS_10G_XFI:
5205 vars->line_speed = ELINK_SPEED_10000;
5206 vars->link_status |= ELINK_LINK_10GTFD;
5208 case ELINK_GP_STATUS_20G_DXGXS:
5209 case ELINK_GP_STATUS_20G_KR2:
5210 vars->line_speed = ELINK_SPEED_20000;
5211 vars->link_status |= ELINK_LINK_20GTFD;
5214 PMD_DRV_LOG(DEBUG, params->sc,
5215 "link speed unsupported gp_status 0x%x",
5217 return ELINK_STATUS_ERROR;
5219 } else { /* link_down */
5220 PMD_DRV_LOG(DEBUG, params->sc, "phy link down");
5222 vars->phy_link_up = 0;
5224 vars->duplex = DUPLEX_FULL;
5225 vars->flow_ctrl = ELINK_FLOW_CTRL_NONE;
5226 vars->mac_type = ELINK_MAC_TYPE_NONE;
5228 PMD_DRV_LOG(DEBUG, params->sc, " phy_link_up %x line_speed %d",
5229 vars->phy_link_up, vars->line_speed);
5230 return ELINK_STATUS_OK;
5233 static uint8_t elink_link_settings_status(struct elink_phy *phy,
5234 struct elink_params *params,
5235 struct elink_vars *vars)
5237 struct bnx2x_softc *sc = params->sc;
5239 uint16_t gp_status, duplex = DUPLEX_HALF, link_up = 0, speed_mask;
5240 elink_status_t rc = ELINK_STATUS_OK;
5242 /* Read gp_status */
5243 CL22_RD_OVER_CL45(sc, phy,
5244 MDIO_REG_BANK_GP_STATUS,
5245 MDIO_GP_STATUS_TOP_AN_STATUS1, &gp_status);
5246 if (gp_status & MDIO_GP_STATUS_TOP_AN_STATUS1_DUPLEX_STATUS)
5247 duplex = DUPLEX_FULL;
5248 if (gp_status & MDIO_GP_STATUS_TOP_AN_STATUS1_LINK_STATUS)
5250 speed_mask = gp_status & ELINK_GP_STATUS_SPEED_MASK;
5251 PMD_DRV_LOG(DEBUG, sc, "gp_status 0x%x, is_link_up %d, speed_mask 0x%x",
5252 gp_status, link_up, speed_mask);
5253 rc = elink_get_link_speed_duplex(phy, params, vars, link_up, speed_mask,
5255 if (rc == ELINK_STATUS_ERROR)
5258 if (gp_status & MDIO_GP_STATUS_TOP_AN_STATUS1_LINK_STATUS) {
5259 if (ELINK_SINGLE_MEDIA_DIRECT(params)) {
5260 vars->duplex = duplex;
5261 elink_flow_ctrl_resolve(phy, params, vars, gp_status);
5262 if (phy->req_line_speed == ELINK_SPEED_AUTO_NEG)
5263 elink_xgxs_an_resolve(phy, params, vars,
5266 } else { /* Link_down */
5267 if ((phy->req_line_speed == ELINK_SPEED_AUTO_NEG) &&
5268 ELINK_SINGLE_MEDIA_DIRECT(params)) {
5269 /* Check signal is detected */
5270 elink_check_fallback_to_cl37(phy, params);
5274 /* Read LP advertised speeds */
5275 if (ELINK_SINGLE_MEDIA_DIRECT(params) &&
5276 (vars->link_status & LINK_STATUS_AUTO_NEGOTIATE_COMPLETE)) {
5279 CL22_RD_OVER_CL45(sc, phy, MDIO_REG_BANK_CL73_IEEEB1,
5280 MDIO_CL73_IEEEB1_AN_LP_ADV2, &val);
5282 if (val & MDIO_CL73_IEEEB1_AN_ADV2_ADVR_1000M_KX)
5283 vars->link_status |=
5284 LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE;
5285 if (val & (MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KX4 |
5286 MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KR))
5287 vars->link_status |=
5288 LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE;
5290 CL22_RD_OVER_CL45(sc, phy, MDIO_REG_BANK_OVER_1G,
5291 MDIO_OVER_1G_LP_UP1, &val);
5293 if (val & MDIO_OVER_1G_UP1_2_5G)
5294 vars->link_status |=
5295 LINK_STATUS_LINK_PARTNER_2500XFD_CAPABLE;
5296 if (val & (MDIO_OVER_1G_UP1_10G | MDIO_OVER_1G_UP1_10GH))
5297 vars->link_status |=
5298 LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE;
5301 PMD_DRV_LOG(DEBUG, sc, "duplex %x flow_ctrl 0x%x link_status 0x%x",
5302 vars->duplex, vars->flow_ctrl, vars->link_status);
5306 static uint8_t elink_warpcore_read_status(struct elink_phy *phy,
5307 struct elink_params *params,
5308 struct elink_vars *vars)
5310 struct bnx2x_softc *sc = params->sc;
5312 uint16_t gp_status1, gp_speed, link_up, duplex = DUPLEX_FULL;
5313 elink_status_t rc = ELINK_STATUS_OK;
5314 lane = elink_get_warpcore_lane(params);
5315 /* Read gp_status */
5316 if ((params->loopback_mode) && (phy->flags & ELINK_FLAGS_WC_DUAL_MODE)) {
5317 elink_cl45_read(sc, phy, MDIO_WC_DEVAD,
5318 MDIO_WC_REG_DIGITAL5_LINK_STATUS, &link_up);
5319 elink_cl45_read(sc, phy, MDIO_WC_DEVAD,
5320 MDIO_WC_REG_DIGITAL5_LINK_STATUS, &link_up);
5322 } else if ((phy->req_line_speed > ELINK_SPEED_10000) &&
5323 (phy->supported & ELINK_SUPPORTED_20000baseMLD2_Full)) {
5324 uint16_t temp_link_up;
5325 elink_cl45_read(sc, phy, MDIO_WC_DEVAD, 1, &temp_link_up);
5326 elink_cl45_read(sc, phy, MDIO_WC_DEVAD, 1, &link_up);
5327 PMD_DRV_LOG(DEBUG, sc, "PCS RX link status = 0x%x-->0x%x",
5328 temp_link_up, link_up);
5329 link_up &= (1 << 2);
5331 elink_ext_phy_resolve_fc(phy, params, vars);
5333 elink_cl45_read(sc, phy, MDIO_WC_DEVAD,
5334 MDIO_WC_REG_GP2_STATUS_GP_2_1, &gp_status1);
5335 PMD_DRV_LOG(DEBUG, sc, "0x81d1 = 0x%x", gp_status1);
5336 /* Check for either KR, 1G, or AN up. */
5337 link_up = ((gp_status1 >> 8) |
5338 (gp_status1 >> 12) | (gp_status1)) & (1 << lane);
5339 if (phy->supported & ELINK_SUPPORTED_20000baseKR2_Full) {
5341 elink_cl45_read(sc, phy, MDIO_AN_DEVAD,
5342 MDIO_AN_REG_STATUS, &an_link);
5343 elink_cl45_read(sc, phy, MDIO_AN_DEVAD,
5344 MDIO_AN_REG_STATUS, &an_link);
5345 link_up |= (an_link & (1 << 2));
5347 if (link_up && ELINK_SINGLE_MEDIA_DIRECT(params)) {
5348 uint16_t pd, gp_status4;
5349 if (phy->req_line_speed == ELINK_SPEED_AUTO_NEG) {
5350 /* Check Autoneg complete */
5351 elink_cl45_read(sc, phy, MDIO_WC_DEVAD,
5352 MDIO_WC_REG_GP2_STATUS_GP_2_4,
5354 if (gp_status4 & ((1 << 12) << lane))
5355 vars->link_status |=
5356 LINK_STATUS_AUTO_NEGOTIATE_COMPLETE;
5358 /* Check parallel detect used */
5359 elink_cl45_read(sc, phy, MDIO_WC_DEVAD,
5360 MDIO_WC_REG_PAR_DET_10G_STATUS,
5363 vars->link_status |=
5364 LINK_STATUS_PARALLEL_DETECTION_USED;
5366 elink_ext_phy_resolve_fc(phy, params, vars);
5367 vars->duplex = duplex;
5371 if ((vars->link_status & LINK_STATUS_AUTO_NEGOTIATE_COMPLETE) &&
5372 ELINK_SINGLE_MEDIA_DIRECT(params)) {
5375 elink_cl45_read(sc, phy, MDIO_AN_DEVAD,
5376 MDIO_AN_REG_LP_AUTO_NEG2, &val);
5378 if (val & MDIO_CL73_IEEEB1_AN_ADV2_ADVR_1000M_KX)
5379 vars->link_status |=
5380 LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE;
5381 if (val & (MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KX4 |
5382 MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KR))
5383 vars->link_status |=
5384 LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE;
5386 elink_cl45_read(sc, phy, MDIO_WC_DEVAD,
5387 MDIO_WC_REG_DIGITAL3_LP_UP1, &val);
5389 if (val & MDIO_OVER_1G_UP1_2_5G)
5390 vars->link_status |=
5391 LINK_STATUS_LINK_PARTNER_2500XFD_CAPABLE;
5392 if (val & (MDIO_OVER_1G_UP1_10G | MDIO_OVER_1G_UP1_10GH))
5393 vars->link_status |=
5394 LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE;
5399 elink_cl45_read(sc, phy, MDIO_WC_DEVAD,
5400 MDIO_WC_REG_GP2_STATUS_GP_2_2, &gp_speed);
5402 elink_cl45_read(sc, phy, MDIO_WC_DEVAD,
5403 MDIO_WC_REG_GP2_STATUS_GP_2_3, &gp_speed);
5405 PMD_DRV_LOG(DEBUG, sc, "lane %d gp_speed 0x%x", lane, gp_speed);
5407 if ((lane & 1) == 0)
5410 link_up = ! !link_up;
5412 /* Reset the TX FIFO to fix SGMII issue */
5413 rc = elink_get_link_speed_duplex(phy, params, vars, link_up, gp_speed,
5416 /* In case of KR link down, start up the recovering procedure */
5417 if ((!link_up) && (phy->media_type == ELINK_ETH_PHY_KR) &&
5418 (!(phy->flags & ELINK_FLAGS_WC_DUAL_MODE)))
5419 vars->rx_tx_asic_rst = MAX_KR_LINK_RETRY;
5421 PMD_DRV_LOG(DEBUG, sc, "duplex %x flow_ctrl 0x%x link_status 0x%x",
5422 vars->duplex, vars->flow_ctrl, vars->link_status);
5426 static void elink_set_gmii_tx_driver(struct elink_params *params)
5428 struct bnx2x_softc *sc = params->sc;
5429 struct elink_phy *phy = ¶ms->phy[ELINK_INT_PHY];
5435 CL22_RD_OVER_CL45(sc, phy,
5436 MDIO_REG_BANK_OVER_1G, MDIO_OVER_1G_LP_UP2, &lp_up2);
5438 /* Bits [10:7] at lp_up2, positioned at [15:12] */
5439 lp_up2 = (((lp_up2 & MDIO_OVER_1G_LP_UP2_PREEMPHASIS_MASK) >>
5440 MDIO_OVER_1G_LP_UP2_PREEMPHASIS_SHIFT) <<
5441 MDIO_TX0_TX_DRIVER_PREEMPHASIS_SHIFT);
5446 for (bank = MDIO_REG_BANK_TX0; bank <= MDIO_REG_BANK_TX3;
5447 bank += (MDIO_REG_BANK_TX1 - MDIO_REG_BANK_TX0)) {
5448 CL22_RD_OVER_CL45(sc, phy,
5449 bank, MDIO_TX0_TX_DRIVER, &tx_driver);
5451 /* Replace tx_driver bits [15:12] */
5452 if (lp_up2 != (tx_driver & MDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK)) {
5453 tx_driver &= ~MDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK;
5454 tx_driver |= lp_up2;
5455 CL22_WR_OVER_CL45(sc, phy,
5456 bank, MDIO_TX0_TX_DRIVER, tx_driver);
5461 static elink_status_t elink_emac_program(struct elink_params *params,
5462 struct elink_vars *vars)
5464 struct bnx2x_softc *sc = params->sc;
5465 uint8_t port = params->port;
5468 PMD_DRV_LOG(DEBUG, sc, "setting link speed & duplex");
5469 elink_bits_dis(sc, GRCBASE_EMAC0 + port * 0x400 +
5471 (EMAC_MODE_25G_MODE |
5472 EMAC_MODE_PORT_MII_10M | EMAC_MODE_HALF_DUPLEX));
5473 switch (vars->line_speed) {
5474 case ELINK_SPEED_10:
5475 mode |= EMAC_MODE_PORT_MII_10M;
5478 case ELINK_SPEED_100:
5479 mode |= EMAC_MODE_PORT_MII;
5482 case ELINK_SPEED_1000:
5483 mode |= EMAC_MODE_PORT_GMII;
5486 case ELINK_SPEED_2500:
5487 mode |= (EMAC_MODE_25G_MODE | EMAC_MODE_PORT_GMII);
5491 /* 10G not valid for EMAC */
5492 PMD_DRV_LOG(DEBUG, sc,
5493 "Invalid line_speed 0x%x", vars->line_speed);
5494 return ELINK_STATUS_ERROR;
5497 if (vars->duplex == DUPLEX_HALF)
5498 mode |= EMAC_MODE_HALF_DUPLEX;
5500 GRCBASE_EMAC0 + port * 0x400 + EMAC_REG_EMAC_MODE, mode);
5502 elink_set_led(params, vars, ELINK_LED_MODE_OPER, vars->line_speed);
5503 return ELINK_STATUS_OK;
5506 static void elink_set_preemphasis(struct elink_phy *phy,
5507 struct elink_params *params)
5510 uint16_t bank, i = 0;
5511 struct bnx2x_softc *sc = params->sc;
5513 for (bank = MDIO_REG_BANK_RX0, i = 0; bank <= MDIO_REG_BANK_RX3;
5514 bank += (MDIO_REG_BANK_RX1 - MDIO_REG_BANK_RX0), i++) {
5515 CL22_WR_OVER_CL45(sc, phy,
5517 MDIO_RX0_RX_EQ_BOOST, phy->rx_preemphasis[i]);
5520 for (bank = MDIO_REG_BANK_TX0, i = 0; bank <= MDIO_REG_BANK_TX3;
5521 bank += (MDIO_REG_BANK_TX1 - MDIO_REG_BANK_TX0), i++) {
5522 CL22_WR_OVER_CL45(sc, phy,
5524 MDIO_TX0_TX_DRIVER, phy->tx_preemphasis[i]);
5528 static uint8_t elink_xgxs_config_init(struct elink_phy *phy,
5529 struct elink_params *params,
5530 struct elink_vars *vars)
5532 uint8_t enable_cl73 = (ELINK_SINGLE_MEDIA_DIRECT(params) ||
5533 (params->loopback_mode == ELINK_LOOPBACK_XGXS));
5535 if (!(vars->phy_flags & PHY_SGMII_FLAG)) {
5536 if (ELINK_SINGLE_MEDIA_DIRECT(params) &&
5537 (params->feature_config_flags &
5538 ELINK_FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED))
5539 elink_set_preemphasis(phy, params);
5541 /* Forced speed requested? */
5542 if (vars->line_speed != ELINK_SPEED_AUTO_NEG ||
5543 (ELINK_SINGLE_MEDIA_DIRECT(params) &&
5544 params->loopback_mode == ELINK_LOOPBACK_EXT)) {
5545 PMD_DRV_LOG(DEBUG, params->sc, "not SGMII, no AN");
5547 /* Disable autoneg */
5548 elink_set_autoneg(phy, params, vars, 0);
5550 /* Program speed and duplex */
5551 elink_program_serdes(phy, params, vars);
5553 } else { /* AN_mode */
5554 PMD_DRV_LOG(DEBUG, params->sc, "not SGMII, AN");
5557 elink_set_brcm_cl37_advertisement(phy, params);
5559 /* Program duplex & pause advertisement (for aneg) */
5560 elink_set_ieee_aneg_advertisement(phy, params,
5563 /* Enable autoneg */
5564 elink_set_autoneg(phy, params, vars, enable_cl73);
5566 /* Enable and restart AN */
5567 elink_restart_autoneg(phy, params, enable_cl73);
5570 } else { /* SGMII mode */
5571 PMD_DRV_LOG(DEBUG, params->sc, "SGMII");
5573 elink_initialize_sgmii_process(phy, params, vars);
5579 static elink_status_t elink_prepare_xgxs(struct elink_phy *phy,
5580 struct elink_params *params,
5581 struct elink_vars *vars)
5584 vars->phy_flags |= PHY_XGXS_FLAG;
5585 if ((phy->req_line_speed &&
5586 ((phy->req_line_speed == ELINK_SPEED_100) ||
5587 (phy->req_line_speed == ELINK_SPEED_10))) ||
5588 (!phy->req_line_speed &&
5589 (phy->speed_cap_mask >=
5590 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL) &&
5591 (phy->speed_cap_mask <
5592 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) ||
5593 (phy->type == PORT_HW_CFG_SERDES_EXT_PHY_TYPE_DIRECT_SD))
5594 vars->phy_flags |= PHY_SGMII_FLAG;
5596 vars->phy_flags &= ~PHY_SGMII_FLAG;
5598 elink_calc_ieee_aneg_adv(phy, params, &vars->ieee_fc);
5599 elink_set_aer_mmd(params, phy);
5600 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT)
5601 elink_set_master_ln(params, phy);
5603 rc = elink_reset_unicore(params, phy, 0);
5604 /* Reset the SerDes and wait for reset bit return low */
5605 if (rc != ELINK_STATUS_OK)
5608 elink_set_aer_mmd(params, phy);
5609 /* Setting the masterLn_def again after the reset */
5610 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) {
5611 elink_set_master_ln(params, phy);
5612 elink_set_swap_lanes(params, phy);
5618 static uint16_t elink_wait_reset_complete(struct bnx2x_softc *sc,
5619 struct elink_phy *phy,
5620 struct elink_params *params)
5623 /* Wait for soft reset to get cleared up to 1 sec */
5624 for (cnt = 0; cnt < 1000; cnt++) {
5625 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X54618SE)
5626 elink_cl22_read(sc, phy, MDIO_PMA_REG_CTRL, &ctrl);
5628 elink_cl45_read(sc, phy,
5630 MDIO_PMA_REG_CTRL, &ctrl);
5631 if (!(ctrl & (1 << 15)))
5637 elink_cb_event_log(sc, ELINK_LOG_ID_PHY_UNINITIALIZED, params->port); // "Warning: PHY was not initialized,"
5640 PMD_DRV_LOG(DEBUG, sc, "control reg 0x%x (after %d ms)", ctrl, cnt);
5644 static void elink_link_int_enable(struct elink_params *params)
5646 uint8_t port = params->port;
5648 struct bnx2x_softc *sc = params->sc;
5650 /* Setting the status to report on link up for either XGXS or SerDes */
5651 if (CHIP_IS_E3(sc)) {
5652 mask = ELINK_NIG_MASK_XGXS0_LINK_STATUS;
5653 if (!(ELINK_SINGLE_MEDIA_DIRECT(params)))
5654 mask |= ELINK_NIG_MASK_MI_INT;
5655 } else if (params->switch_cfg == ELINK_SWITCH_CFG_10G) {
5656 mask = (ELINK_NIG_MASK_XGXS0_LINK10G |
5657 ELINK_NIG_MASK_XGXS0_LINK_STATUS);
5658 PMD_DRV_LOG(DEBUG, sc, "enabled XGXS interrupt");
5659 if (!(ELINK_SINGLE_MEDIA_DIRECT(params)) &&
5660 params->phy[ELINK_INT_PHY].type !=
5661 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE) {
5662 mask |= ELINK_NIG_MASK_MI_INT;
5663 PMD_DRV_LOG(DEBUG, sc, "enabled external phy int");
5666 } else { /* SerDes */
5667 mask = ELINK_NIG_MASK_SERDES0_LINK_STATUS;
5668 PMD_DRV_LOG(DEBUG, sc, "enabled SerDes interrupt");
5669 if (!(ELINK_SINGLE_MEDIA_DIRECT(params)) &&
5670 params->phy[ELINK_INT_PHY].type !=
5671 PORT_HW_CFG_SERDES_EXT_PHY_TYPE_NOT_CONN) {
5672 mask |= ELINK_NIG_MASK_MI_INT;
5673 PMD_DRV_LOG(DEBUG, sc, "enabled external phy int");
5676 elink_bits_en(sc, NIG_REG_MASK_INTERRUPT_PORT0 + port * 4, mask);
5678 PMD_DRV_LOG(DEBUG, sc, "port %x, is_xgxs %x, int_status 0x%x", port,
5679 (params->switch_cfg == ELINK_SWITCH_CFG_10G),
5680 REG_RD(sc, NIG_REG_STATUS_INTERRUPT_PORT0 + port * 4));
5681 PMD_DRV_LOG(DEBUG, sc, " int_mask 0x%x, MI_INT %x, SERDES_LINK %x",
5682 REG_RD(sc, NIG_REG_MASK_INTERRUPT_PORT0 + port * 4),
5683 REG_RD(sc, NIG_REG_EMAC0_STATUS_MISC_MI_INT + port * 0x18),
5685 NIG_REG_SERDES0_STATUS_LINK_STATUS + port * 0x3c));
5686 PMD_DRV_LOG(DEBUG, sc, " 10G %x, XGXS_LINK %x",
5687 REG_RD(sc, NIG_REG_XGXS0_STATUS_LINK10G + port * 0x68),
5688 REG_RD(sc, NIG_REG_XGXS0_STATUS_LINK_STATUS + port * 0x68));
5691 static void elink_rearm_latch_signal(struct bnx2x_softc *sc, uint8_t port,
5694 uint32_t latch_status = 0;
5696 /* Disable the MI INT ( external phy int ) by writing 1 to the
5697 * status register. Link down indication is high-active-signal,
5698 * so in this case we need to write the status to clear the XOR
5700 /* Read Latched signals */
5701 latch_status = REG_RD(sc, NIG_REG_LATCH_STATUS_0 + port * 8);
5702 PMD_DRV_LOG(DEBUG, sc, "latch_status = 0x%x", latch_status);
5703 /* Handle only those with latched-signal=up. */
5706 NIG_REG_STATUS_INTERRUPT_PORT0
5707 + port * 4, ELINK_NIG_STATUS_EMAC0_MI_INT);
5710 NIG_REG_STATUS_INTERRUPT_PORT0
5711 + port * 4, ELINK_NIG_STATUS_EMAC0_MI_INT);
5713 if (latch_status & 1) {
5715 /* For all latched-signal=up : Re-Arm Latch signals */
5716 REG_WR(sc, NIG_REG_LATCH_STATUS_0 + port * 8,
5717 (latch_status & 0xfffe) | (latch_status & 1));
5719 /* For all latched-signal=up,Write original_signal to status */
5722 static void elink_link_int_ack(struct elink_params *params,
5723 struct elink_vars *vars, uint8_t is_10g_plus)
5725 struct bnx2x_softc *sc = params->sc;
5726 uint8_t port = params->port;
5728 /* First reset all status we assume only one line will be
5731 elink_bits_dis(sc, NIG_REG_STATUS_INTERRUPT_PORT0 + port * 4,
5732 (ELINK_NIG_STATUS_XGXS0_LINK10G |
5733 ELINK_NIG_STATUS_XGXS0_LINK_STATUS |
5734 ELINK_NIG_STATUS_SERDES0_LINK_STATUS));
5735 if (vars->phy_link_up) {
5736 if (USES_WARPCORE(sc))
5737 mask = ELINK_NIG_STATUS_XGXS0_LINK_STATUS;
5740 mask = ELINK_NIG_STATUS_XGXS0_LINK10G;
5741 else if (params->switch_cfg == ELINK_SWITCH_CFG_10G) {
5742 /* Disable the link interrupt by writing 1 to
5743 * the relevant lane in the status register
5746 ((params->lane_config &
5747 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK) >>
5748 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT);
5749 mask = ((1 << ser_lane) <<
5750 ELINK_NIG_STATUS_XGXS0_LINK_STATUS_SIZE);
5752 mask = ELINK_NIG_STATUS_SERDES0_LINK_STATUS;
5754 PMD_DRV_LOG(DEBUG, sc, "Ack link up interrupt with mask 0x%x",
5757 NIG_REG_STATUS_INTERRUPT_PORT0 + port * 4, mask);
5761 static uint8_t elink_format_ver(uint32_t num, uint8_t * str,
5764 uint8_t *str_ptr = str;
5765 uint32_t mask = 0xf0000000;
5766 uint8_t shift = 8 * 4;
5768 uint8_t remove_leading_zeros = 1;
5770 /* Need more than 10chars for this format */
5773 return ELINK_STATUS_ERROR;
5778 digit = ((num & mask) >> shift);
5779 if (digit == 0 && remove_leading_zeros) {
5782 } else if (digit < 0xa)
5783 *str_ptr = digit + '0';
5785 *str_ptr = digit - 0xa + 'a';
5786 remove_leading_zeros = 0;
5790 if (shift == 4 * 4) {
5794 remove_leading_zeros = 1;
5797 return ELINK_STATUS_OK;
5800 static uint8_t elink_null_format_ver(__rte_unused uint32_t spirom_ver,
5801 uint8_t * str, uint16_t * len)
5805 return ELINK_STATUS_OK;
5808 static void elink_set_xgxs_loopback(struct elink_phy *phy,
5809 struct elink_params *params)
5811 uint8_t port = params->port;
5812 struct bnx2x_softc *sc = params->sc;
5814 if (phy->req_line_speed != ELINK_SPEED_1000) {
5815 uint32_t md_devad = 0;
5817 PMD_DRV_LOG(DEBUG, sc, "XGXS 10G loopback enable");
5819 if (!CHIP_IS_E3(sc)) {
5820 /* Change the uni_phy_addr in the nig */
5821 md_devad = REG_RD(sc, (NIG_REG_XGXS0_CTRL_MD_DEVAD +
5824 REG_WR(sc, NIG_REG_XGXS0_CTRL_MD_DEVAD + port * 0x18,
5828 elink_cl45_write(sc, phy,
5830 (MDIO_REG_BANK_AER_BLOCK +
5831 (MDIO_AER_BLOCK_AER_REG & 0xf)), 0x2800);
5833 elink_cl45_write(sc, phy,
5835 (MDIO_REG_BANK_CL73_IEEEB0 +
5836 (MDIO_CL73_IEEEB0_CL73_AN_CONTROL & 0xf)),
5839 /* Set aer mmd back */
5840 elink_set_aer_mmd(params, phy);
5842 if (!CHIP_IS_E3(sc)) {
5844 REG_WR(sc, NIG_REG_XGXS0_CTRL_MD_DEVAD + port * 0x18,
5849 PMD_DRV_LOG(DEBUG, sc, "XGXS 1G loopback enable");
5850 elink_cl45_read(sc, phy, 5,
5851 (MDIO_REG_BANK_COMBO_IEEE0 +
5852 (MDIO_COMBO_IEEE0_MII_CONTROL & 0xf)),
5854 elink_cl45_write(sc, phy, 5,
5855 (MDIO_REG_BANK_COMBO_IEEE0 +
5856 (MDIO_COMBO_IEEE0_MII_CONTROL & 0xf)),
5858 MDIO_COMBO_IEEO_MII_CONTROL_LOOPBACK);
5862 elink_status_t elink_set_led(struct elink_params *params,
5863 struct elink_vars *vars, uint8_t mode,
5866 uint8_t port = params->port;
5867 uint16_t hw_led_mode = params->hw_led_mode;
5868 elink_status_t rc = ELINK_STATUS_OK;
5871 uint32_t emac_base = port ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
5872 struct bnx2x_softc *sc = params->sc;
5873 PMD_DRV_LOG(DEBUG, sc, "elink_set_led: port %x, mode %d", port, mode);
5874 PMD_DRV_LOG(DEBUG, sc,
5875 "speed 0x%x, hw_led_mode 0x%x", speed, hw_led_mode);
5877 for (phy_idx = ELINK_EXT_PHY1; phy_idx < ELINK_MAX_PHYS; phy_idx++) {
5878 if (params->phy[phy_idx].set_link_led) {
5879 params->phy[phy_idx].set_link_led(¶ms->phy[phy_idx],
5885 case ELINK_LED_MODE_FRONT_PANEL_OFF:
5886 case ELINK_LED_MODE_OFF:
5887 REG_WR(sc, NIG_REG_LED_10G_P0 + port * 4, 0);
5888 REG_WR(sc, NIG_REG_LED_MODE_P0 + port * 4,
5889 SHARED_HW_CFG_LED_MAC1);
5891 tmp = elink_cb_reg_read(sc, emac_base + EMAC_REG_EMAC_LED);
5892 if (params->phy[ELINK_EXT_PHY1].type ==
5893 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X54618SE)
5894 tmp &= ~(EMAC_LED_1000MB_OVERRIDE |
5895 EMAC_LED_100MB_OVERRIDE |
5896 EMAC_LED_10MB_OVERRIDE);
5898 tmp |= EMAC_LED_OVERRIDE;
5900 elink_cb_reg_write(sc, emac_base + EMAC_REG_EMAC_LED, tmp);
5903 case ELINK_LED_MODE_OPER:
5904 /* For all other phys, OPER mode is same as ON, so in case
5905 * link is down, do nothing
5909 case ELINK_LED_MODE_ON:
5910 if (((params->phy[ELINK_EXT_PHY1].type ==
5911 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X8727) ||
5912 (params->phy[ELINK_EXT_PHY1].type ==
5913 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X8722)) &&
5914 CHIP_IS_E2(sc) && params->num_phys == 2) {
5915 /* This is a work-around for E2+8727 Configurations */
5916 if (mode == ELINK_LED_MODE_ON ||
5917 speed == ELINK_SPEED_10000) {
5918 REG_WR(sc, NIG_REG_LED_MODE_P0 + port * 4, 0);
5919 REG_WR(sc, NIG_REG_LED_10G_P0 + port * 4, 1);
5922 elink_cb_reg_read(sc,
5925 elink_cb_reg_write(sc,
5928 (tmp | EMAC_LED_OVERRIDE));
5929 /* Return here without enabling traffic
5930 * LED blink and setting rate in ON mode.
5931 * In oper mode, enabling LED blink
5932 * and setting rate is needed.
5934 if (mode == ELINK_LED_MODE_ON)
5937 } else if (ELINK_SINGLE_MEDIA_DIRECT(params)) {
5938 /* This is a work-around for HW issue found when link
5941 if ((!CHIP_IS_E3(sc)) ||
5942 (CHIP_IS_E3(sc) && mode == ELINK_LED_MODE_ON))
5943 REG_WR(sc, NIG_REG_LED_10G_P0 + port * 4, 1);
5945 if (CHIP_IS_E1x(sc) ||
5946 CHIP_IS_E2(sc) || (mode == ELINK_LED_MODE_ON))
5947 REG_WR(sc, NIG_REG_LED_MODE_P0 + port * 4, 0);
5949 REG_WR(sc, NIG_REG_LED_MODE_P0 + port * 4,
5951 } else if ((params->phy[ELINK_EXT_PHY1].type ==
5952 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X54618SE) &&
5953 (mode == ELINK_LED_MODE_ON)) {
5954 REG_WR(sc, NIG_REG_LED_MODE_P0 + port * 4, 0);
5956 elink_cb_reg_read(sc,
5957 emac_base + EMAC_REG_EMAC_LED);
5958 elink_cb_reg_write(sc, emac_base + EMAC_REG_EMAC_LED,
5959 tmp | EMAC_LED_OVERRIDE |
5960 EMAC_LED_1000MB_OVERRIDE);
5961 /* Break here; otherwise, it'll disable the
5962 * intended override.
5966 uint32_t nig_led_mode = ((params->hw_led_mode <<
5967 SHARED_HW_CFG_LED_MODE_SHIFT)
5969 SHARED_HW_CFG_LED_EXTPHY2)
5970 ? (SHARED_HW_CFG_LED_PHY1 >>
5971 SHARED_HW_CFG_LED_MODE_SHIFT) : hw_led_mode;
5972 REG_WR(sc, NIG_REG_LED_MODE_P0 + port * 4,
5976 REG_WR(sc, NIG_REG_LED_CONTROL_OVERRIDE_TRAFFIC_P0 + port * 4,
5978 /* Set blinking rate to ~15.9Hz */
5980 REG_WR(sc, NIG_REG_LED_CONTROL_BLINK_RATE_P0 + port * 4,
5981 LED_BLINK_RATE_VAL_E3);
5983 REG_WR(sc, NIG_REG_LED_CONTROL_BLINK_RATE_P0 + port * 4,
5984 LED_BLINK_RATE_VAL_E1X_E2);
5985 REG_WR(sc, NIG_REG_LED_CONTROL_BLINK_RATE_ENA_P0 + port * 4, 1);
5986 tmp = elink_cb_reg_read(sc, emac_base + EMAC_REG_EMAC_LED);
5987 elink_cb_reg_write(sc, emac_base + EMAC_REG_EMAC_LED,
5988 (tmp & (~EMAC_LED_OVERRIDE)));
5993 rc = ELINK_STATUS_ERROR;
5994 PMD_DRV_LOG(DEBUG, sc,
5995 "elink_set_led: Invalid led mode %d", mode);
6002 static elink_status_t elink_link_initialize(struct elink_params *params,
6003 struct elink_vars *vars)
6005 elink_status_t rc = ELINK_STATUS_OK;
6006 uint8_t phy_index, non_ext_phy;
6007 struct bnx2x_softc *sc = params->sc;
6008 /* In case of external phy existence, the line speed would be the
6009 * line speed linked up by the external phy. In case it is direct
6010 * only, then the line_speed during initialization will be
6011 * equal to the req_line_speed
6013 vars->line_speed = params->phy[ELINK_INT_PHY].req_line_speed;
6015 /* Initialize the internal phy in case this is a direct board
6016 * (no external phys), or this board has external phy which requires
6019 if (!USES_WARPCORE(sc))
6020 elink_prepare_xgxs(¶ms->phy[ELINK_INT_PHY], params, vars);
6021 /* init ext phy and enable link state int */
6022 non_ext_phy = (ELINK_SINGLE_MEDIA_DIRECT(params) ||
6023 (params->loopback_mode == ELINK_LOOPBACK_XGXS));
6026 (params->phy[ELINK_EXT_PHY1].flags & ELINK_FLAGS_INIT_XGXS_FIRST) ||
6027 (params->loopback_mode == ELINK_LOOPBACK_EXT_PHY)) {
6028 struct elink_phy *phy = ¶ms->phy[ELINK_INT_PHY];
6029 if (vars->line_speed == ELINK_SPEED_AUTO_NEG &&
6030 (CHIP_IS_E1x(sc) || CHIP_IS_E2(sc)))
6031 elink_set_parallel_detection(phy, params);
6032 if (params->phy[ELINK_INT_PHY].config_init)
6033 params->phy[ELINK_INT_PHY].config_init(phy,
6037 /* Re-read this value in case it was changed inside config_init due to
6038 * limitations of optic module
6040 vars->line_speed = params->phy[ELINK_INT_PHY].req_line_speed;
6042 /* Init external phy */
6044 if (params->phy[ELINK_INT_PHY].supported &
6045 ELINK_SUPPORTED_FIBRE)
6046 vars->link_status |= LINK_STATUS_SERDES_LINK;
6048 for (phy_index = ELINK_EXT_PHY1; phy_index < params->num_phys;
6050 /* No need to initialize second phy in case of first
6051 * phy only selection. In case of second phy, we do
6052 * need to initialize the first phy, since they are
6055 if (params->phy[phy_index].supported &
6056 ELINK_SUPPORTED_FIBRE)
6057 vars->link_status |= LINK_STATUS_SERDES_LINK;
6059 if (phy_index == ELINK_EXT_PHY2 &&
6060 (elink_phy_selection(params) ==
6061 PORT_HW_CFG_PHY_SELECTION_FIRST_PHY)) {
6062 PMD_DRV_LOG(DEBUG, sc,
6063 "Not initializing second phy");
6066 params->phy[phy_index].config_init(¶ms->
6071 /* Reset the interrupt indication after phy was initialized */
6072 elink_bits_dis(sc, NIG_REG_STATUS_INTERRUPT_PORT0 +
6074 (ELINK_NIG_STATUS_XGXS0_LINK10G |
6075 ELINK_NIG_STATUS_XGXS0_LINK_STATUS |
6076 ELINK_NIG_STATUS_SERDES0_LINK_STATUS |
6077 ELINK_NIG_MASK_MI_INT));
6081 static void elink_int_link_reset(__rte_unused struct elink_phy *phy,
6082 struct elink_params *params)
6084 /* Reset the SerDes/XGXS */
6085 REG_WR(params->sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_CLEAR,
6086 (0x1ff << (params->port * 16)));
6089 static void elink_common_ext_link_reset(__rte_unused struct elink_phy *phy,
6090 struct elink_params *params)
6092 struct bnx2x_softc *sc = params->sc;
6096 gpio_port = SC_PATH(sc);
6098 gpio_port = params->port;
6099 elink_cb_gpio_write(sc, MISC_REGISTERS_GPIO_1,
6100 MISC_REGISTERS_GPIO_OUTPUT_LOW, gpio_port);
6101 elink_cb_gpio_write(sc, MISC_REGISTERS_GPIO_2,
6102 MISC_REGISTERS_GPIO_OUTPUT_LOW, gpio_port);
6103 PMD_DRV_LOG(DEBUG, sc, "reset external PHY");
6106 static elink_status_t elink_update_link_down(struct elink_params *params,
6107 struct elink_vars *vars)
6109 struct bnx2x_softc *sc = params->sc;
6110 uint8_t port = params->port;
6112 PMD_DRV_LOG(DEBUG, sc, "Port %x: Link is down", port);
6113 elink_set_led(params, vars, ELINK_LED_MODE_OFF, 0);
6114 vars->phy_flags &= ~PHY_PHYSICAL_LINK_FLAG;
6115 /* Indicate no mac active */
6116 vars->mac_type = ELINK_MAC_TYPE_NONE;
6118 /* Update shared memory */
6119 vars->link_status &= ~ELINK_LINK_UPDATE_MASK;
6120 vars->line_speed = 0;
6121 elink_update_mng(params, vars->link_status);
6123 /* Activate nig drain */
6124 REG_WR(sc, NIG_REG_EGRESS_DRAIN0_MODE + port * 4, 1);
6127 if (!CHIP_IS_E3(sc))
6128 REG_WR(sc, NIG_REG_NIG_EMAC0_EN + port * 4, 0);
6131 /* Reset BigMac/Xmac */
6132 if (CHIP_IS_E1x(sc) || CHIP_IS_E2(sc))
6133 elink_set_bmac_rx(sc, params->port, 0);
6135 if (CHIP_IS_E3(sc)) {
6136 /* Prevent LPI Generation by chip */
6137 REG_WR(sc, MISC_REG_CPMU_LP_FW_ENABLE_P0 + (params->port << 2),
6139 REG_WR(sc, MISC_REG_CPMU_LP_MASK_ENT_P0 + (params->port << 2),
6141 vars->eee_status &= ~(SHMEM_EEE_LP_ADV_STATUS_MASK |
6142 SHMEM_EEE_ACTIVE_BIT);
6144 elink_update_mng_eee(params, vars->eee_status);
6145 elink_set_xmac_rxtx(params, 0);
6146 elink_set_umac_rxtx(params, 0);
6149 return ELINK_STATUS_OK;
6152 static elink_status_t elink_update_link_up(struct elink_params *params,
6153 struct elink_vars *vars,
6156 struct bnx2x_softc *sc = params->sc;
6157 uint8_t phy_idx, port = params->port;
6158 elink_status_t rc = ELINK_STATUS_OK;
6160 vars->link_status |= (LINK_STATUS_LINK_UP |
6161 LINK_STATUS_PHYSICAL_LINK_FLAG);
6162 vars->phy_flags |= PHY_PHYSICAL_LINK_FLAG;
6164 if (vars->flow_ctrl & ELINK_FLOW_CTRL_TX)
6165 vars->link_status |= LINK_STATUS_TX_FLOW_CONTROL_ENABLED;
6167 if (vars->flow_ctrl & ELINK_FLOW_CTRL_RX)
6168 vars->link_status |= LINK_STATUS_RX_FLOW_CONTROL_ENABLED;
6169 if (USES_WARPCORE(sc)) {
6171 if (elink_xmac_enable(params, vars, 0) ==
6172 ELINK_STATUS_NO_LINK) {
6173 PMD_DRV_LOG(DEBUG, sc, "Found errors on XMAC");
6175 vars->phy_flags |= PHY_HALF_OPEN_CONN_FLAG;
6176 vars->link_status &= ~LINK_STATUS_LINK_UP;
6179 elink_umac_enable(params, vars, 0);
6180 elink_set_led(params, vars,
6181 ELINK_LED_MODE_OPER, vars->line_speed);
6183 if ((vars->eee_status & SHMEM_EEE_ACTIVE_BIT) &&
6184 (vars->eee_status & SHMEM_EEE_LPI_REQUESTED_BIT)) {
6185 PMD_DRV_LOG(DEBUG, sc, "Enabling LPI assertion");
6186 REG_WR(sc, MISC_REG_CPMU_LP_FW_ENABLE_P0 +
6187 (params->port << 2), 1);
6188 REG_WR(sc, MISC_REG_CPMU_LP_DR_ENABLE, 1);
6189 REG_WR(sc, MISC_REG_CPMU_LP_MASK_ENT_P0 +
6190 (params->port << 2), 0xfc20);
6193 if ((CHIP_IS_E1x(sc) || CHIP_IS_E2(sc))) {
6195 if (elink_bmac_enable(params, vars, 0, 1) ==
6196 ELINK_STATUS_NO_LINK) {
6197 PMD_DRV_LOG(DEBUG, sc, "Found errors on BMAC");
6199 vars->phy_flags |= PHY_HALF_OPEN_CONN_FLAG;
6200 vars->link_status &= ~LINK_STATUS_LINK_UP;
6203 elink_set_led(params, vars,
6204 ELINK_LED_MODE_OPER, ELINK_SPEED_10000);
6206 rc = elink_emac_program(params, vars);
6207 elink_emac_enable(params, vars, 0);
6210 if ((vars->link_status &
6211 LINK_STATUS_AUTO_NEGOTIATE_COMPLETE)
6212 && (!(vars->phy_flags & PHY_SGMII_FLAG)) &&
6213 ELINK_SINGLE_MEDIA_DIRECT(params))
6214 elink_set_gmii_tx_driver(params);
6219 if (CHIP_IS_E1x(sc))
6220 rc |= elink_pbf_update(params, vars->flow_ctrl,
6224 REG_WR(sc, NIG_REG_EGRESS_DRAIN0_MODE + port * 4, 0);
6226 /* Update shared memory */
6227 elink_update_mng(params, vars->link_status);
6228 elink_update_mng_eee(params, vars->eee_status);
6229 /* Check remote fault */
6230 for (phy_idx = ELINK_INT_PHY; phy_idx < ELINK_MAX_PHYS; phy_idx++) {
6231 if (params->phy[phy_idx].flags & ELINK_FLAGS_TX_ERROR_CHECK) {
6232 elink_check_half_open_conn(params, vars, 0);
6240 /* The elink_link_update function should be called upon link
6242 * Link is considered up as follows:
6243 * - DIRECT_SINGLE_MEDIA - Only XGXS link (internal link) needs
6245 * - SINGLE_MEDIA - The link between the 577xx and the external
6246 * phy (XGXS) need to up as well as the external link of the
6248 * - DUAL_MEDIA - The link between the 577xx and the first
6249 * external phy needs to be up, and at least one of the 2
6250 * external phy link must be up.
6252 elink_status_t elink_link_update(struct elink_params * params,
6253 struct elink_vars * vars)
6255 struct bnx2x_softc *sc = params->sc;
6256 struct elink_vars phy_vars[ELINK_MAX_PHYS];
6257 uint8_t port = params->port;
6258 uint8_t link_10g_plus, phy_index;
6259 uint8_t ext_phy_link_up = 0, cur_link_up;
6260 elink_status_t rc = ELINK_STATUS_OK;
6261 __rte_unused uint8_t is_mi_int = 0;
6262 uint16_t ext_phy_line_speed = 0, prev_line_speed = vars->line_speed;
6263 uint8_t active_external_phy = ELINK_INT_PHY;
6264 vars->phy_flags &= ~PHY_HALF_OPEN_CONN_FLAG;
6265 vars->link_status &= ~ELINK_LINK_UPDATE_MASK;
6266 for (phy_index = ELINK_INT_PHY; phy_index < params->num_phys;
6268 phy_vars[phy_index].flow_ctrl = 0;
6269 phy_vars[phy_index].link_status = ETH_LINK_DOWN;
6270 phy_vars[phy_index].line_speed = 0;
6271 phy_vars[phy_index].duplex = DUPLEX_FULL;
6272 phy_vars[phy_index].phy_link_up = 0;
6273 phy_vars[phy_index].link_up = 0;
6274 phy_vars[phy_index].fault_detected = 0;
6275 /* different consideration, since vars holds inner state */
6276 phy_vars[phy_index].eee_status = vars->eee_status;
6279 if (USES_WARPCORE(sc))
6280 elink_set_aer_mmd(params, ¶ms->phy[ELINK_INT_PHY]);
6282 PMD_DRV_LOG(DEBUG, sc, "port %x, XGXS?%x, int_status 0x%x",
6283 port, (vars->phy_flags & PHY_XGXS_FLAG),
6284 REG_RD(sc, NIG_REG_STATUS_INTERRUPT_PORT0 + port * 4));
6286 is_mi_int = (uint8_t) (REG_RD(sc, NIG_REG_EMAC0_STATUS_MISC_MI_INT +
6288 PMD_DRV_LOG(DEBUG, sc, "int_mask 0x%x MI_INT %x, SERDES_LINK %x",
6289 REG_RD(sc, NIG_REG_MASK_INTERRUPT_PORT0 + port * 4),
6292 NIG_REG_SERDES0_STATUS_LINK_STATUS + port * 0x3c));
6294 PMD_DRV_LOG(DEBUG, sc, " 10G %x, XGXS_LINK %x",
6295 REG_RD(sc, NIG_REG_XGXS0_STATUS_LINK10G + port * 0x68),
6296 REG_RD(sc, NIG_REG_XGXS0_STATUS_LINK_STATUS + port * 0x68));
6299 if (!CHIP_IS_E3(sc))
6300 REG_WR(sc, NIG_REG_NIG_EMAC0_EN + port * 4, 0);
6303 * Check external link change only for external phys, and apply
6304 * priority selection between them in case the link on both phys
6305 * is up. Note that instead of the common vars, a temporary
6306 * vars argument is used since each phy may have different link/
6307 * speed/duplex result
6309 for (phy_index = ELINK_EXT_PHY1; phy_index < params->num_phys;
6311 struct elink_phy *phy = ¶ms->phy[phy_index];
6312 if (!phy->read_status)
6314 /* Read link status and params of this ext phy */
6315 cur_link_up = phy->read_status(phy, params,
6316 &phy_vars[phy_index]);
6318 PMD_DRV_LOG(DEBUG, sc, "phy in index %d link is up",
6321 PMD_DRV_LOG(DEBUG, sc, "phy in index %d link is down",
6326 if (!ext_phy_link_up) {
6327 ext_phy_link_up = 1;
6328 active_external_phy = phy_index;
6330 switch (elink_phy_selection(params)) {
6331 case PORT_HW_CFG_PHY_SELECTION_HARDWARE_DEFAULT:
6332 case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY_PRIORITY:
6333 /* In this option, the first PHY makes sure to pass the
6334 * traffic through itself only.
6335 * Its not clear how to reset the link on the second phy
6337 active_external_phy = ELINK_EXT_PHY1;
6339 case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY_PRIORITY:
6340 /* In this option, the first PHY makes sure to pass the
6341 * traffic through the second PHY.
6343 active_external_phy = ELINK_EXT_PHY2;
6346 /* Link indication on both PHYs with the following cases
6348 * - FIRST_PHY means that second phy wasn't initialized,
6349 * hence its link is expected to be down
6350 * - SECOND_PHY means that first phy should not be able
6351 * to link up by itself (using configuration)
6352 * - DEFAULT should be overriden during initialiazation
6354 PMD_DRV_LOG(DEBUG, sc, "Invalid link indication"
6355 "mpc=0x%x. DISABLING LINK !!!",
6356 params->multi_phy_config);
6357 ext_phy_link_up = 0;
6362 prev_line_speed = vars->line_speed;
6364 * Read the status of the internal phy. In case of
6365 * DIRECT_SINGLE_MEDIA board, this link is the external link,
6366 * otherwise this is the link between the 577xx and the first
6369 if (params->phy[ELINK_INT_PHY].read_status)
6370 params->phy[ELINK_INT_PHY].read_status(¶ms->
6373 /* The INT_PHY flow control reside in the vars. This include the
6374 * case where the speed or flow control are not set to AUTO.
6375 * Otherwise, the active external phy flow control result is set
6376 * to the vars. The ext_phy_line_speed is needed to check if the
6377 * speed is different between the internal phy and external phy.
6378 * This case may be result of intermediate link speed change.
6380 if (active_external_phy > ELINK_INT_PHY) {
6381 vars->flow_ctrl = phy_vars[active_external_phy].flow_ctrl;
6382 /* Link speed is taken from the XGXS. AN and FC result from
6385 vars->link_status |= phy_vars[active_external_phy].link_status;
6387 /* if active_external_phy is first PHY and link is up - disable
6388 * disable TX on second external PHY
6390 if (active_external_phy == ELINK_EXT_PHY1) {
6391 if (params->phy[ELINK_EXT_PHY2].phy_specific_func) {
6392 PMD_DRV_LOG(DEBUG, sc, "Disabling TX on EXT_PHY2");
6393 params->phy[ELINK_EXT_PHY2].
6394 phy_specific_func(¶ms->
6395 phy[ELINK_EXT_PHY2],
6396 params, ELINK_DISABLE_TX);
6400 ext_phy_line_speed = phy_vars[active_external_phy].line_speed;
6401 vars->duplex = phy_vars[active_external_phy].duplex;
6402 if (params->phy[active_external_phy].supported &
6403 ELINK_SUPPORTED_FIBRE)
6404 vars->link_status |= LINK_STATUS_SERDES_LINK;
6406 vars->link_status &= ~LINK_STATUS_SERDES_LINK;
6408 vars->eee_status = phy_vars[active_external_phy].eee_status;
6410 PMD_DRV_LOG(DEBUG, sc, "Active external phy selected: %x",
6411 active_external_phy);
6414 for (phy_index = ELINK_EXT_PHY1; phy_index < params->num_phys;
6416 if (params->phy[phy_index].flags &
6417 ELINK_FLAGS_REARM_LATCH_SIGNAL) {
6418 elink_rearm_latch_signal(sc, port,
6420 active_external_phy);
6424 PMD_DRV_LOG(DEBUG, sc, "vars->flow_ctrl = 0x%x, vars->link_status = 0x%x,"
6425 " ext_phy_line_speed = %d", vars->flow_ctrl,
6426 vars->link_status, ext_phy_line_speed);
6427 /* Upon link speed change set the NIG into drain mode. Comes to
6428 * deals with possible FIFO glitch due to clk change when speed
6429 * is decreased without link down indicator
6432 if (vars->phy_link_up) {
6433 if (!(ELINK_SINGLE_MEDIA_DIRECT(params)) && ext_phy_link_up &&
6434 (ext_phy_line_speed != vars->line_speed)) {
6435 PMD_DRV_LOG(DEBUG, sc, "Internal link speed %d is"
6436 " different than the external"
6437 " link speed %d", vars->line_speed,
6438 ext_phy_line_speed);
6439 vars->phy_link_up = 0;
6440 } else if (prev_line_speed != vars->line_speed) {
6442 NIG_REG_EGRESS_DRAIN0_MODE + params->port * 4,
6448 /* Anything 10 and over uses the bmac */
6449 link_10g_plus = (vars->line_speed >= ELINK_SPEED_10000);
6451 elink_link_int_ack(params, vars, link_10g_plus);
6453 /* In case external phy link is up, and internal link is down
6454 * (not initialized yet probably after link initialization, it
6455 * needs to be initialized.
6456 * Note that after link down-up as result of cable plug, the xgxs
6457 * link would probably become up again without the need
6460 if (!(ELINK_SINGLE_MEDIA_DIRECT(params))) {
6461 PMD_DRV_LOG(DEBUG, sc, "ext_phy_link_up = %d, int_link_up = %d,"
6462 " init_preceding = %d", ext_phy_link_up,
6464 params->phy[ELINK_EXT_PHY1].flags &
6465 ELINK_FLAGS_INIT_XGXS_FIRST);
6466 if (!(params->phy[ELINK_EXT_PHY1].flags &
6467 ELINK_FLAGS_INIT_XGXS_FIRST)
6468 && ext_phy_link_up && !vars->phy_link_up) {
6469 vars->line_speed = ext_phy_line_speed;
6470 if (vars->line_speed < ELINK_SPEED_1000)
6471 vars->phy_flags |= PHY_SGMII_FLAG;
6473 vars->phy_flags &= ~PHY_SGMII_FLAG;
6475 if (params->phy[ELINK_INT_PHY].config_init)
6476 params->phy[ELINK_INT_PHY].config_init(¶ms->
6483 /* Link is up only if both local phy and external phy (in case of
6484 * non-direct board) are up and no fault detected on active PHY.
6486 vars->link_up = (vars->phy_link_up &&
6488 ELINK_SINGLE_MEDIA_DIRECT(params)) &&
6489 (phy_vars[active_external_phy].fault_detected == 0));
6491 /* Update the PFC configuration in case it was changed */
6492 if (params->feature_config_flags & ELINK_FEATURE_CONFIG_PFC_ENABLED)
6493 vars->link_status |= LINK_STATUS_PFC_ENABLED;
6495 vars->link_status &= ~LINK_STATUS_PFC_ENABLED;
6498 rc = elink_update_link_up(params, vars, link_10g_plus);
6500 rc = elink_update_link_down(params, vars);
6502 /* Update MCP link status was changed */
6504 feature_config_flags & ELINK_FEATURE_CONFIG_BC_SUPPORTS_AFEX)
6505 elink_cb_fw_command(sc, DRV_MSG_CODE_LINK_STATUS_CHANGED, 0);
6510 /*****************************************************************************/
6511 /* External Phy section */
6512 /*****************************************************************************/
6513 static void elink_ext_phy_hw_reset(struct bnx2x_softc *sc, uint8_t port)
6515 elink_cb_gpio_write(sc, MISC_REGISTERS_GPIO_1,
6516 MISC_REGISTERS_GPIO_OUTPUT_LOW, port);
6518 elink_cb_gpio_write(sc, MISC_REGISTERS_GPIO_1,
6519 MISC_REGISTERS_GPIO_OUTPUT_HIGH, port);
6522 static void elink_save_spirom_version(struct bnx2x_softc *sc,
6523 __rte_unused uint8_t port,
6524 uint32_t spirom_ver, uint32_t ver_addr)
6526 PMD_DRV_LOG(DEBUG, sc, "FW version 0x%x:0x%x for port %d",
6527 (uint16_t) (spirom_ver >> 16), (uint16_t) spirom_ver, port);
6530 REG_WR(sc, ver_addr, spirom_ver);
6533 static void elink_save_bnx2x_spirom_ver(struct bnx2x_softc *sc,
6534 struct elink_phy *phy, uint8_t port)
6536 uint16_t fw_ver1, fw_ver2;
6538 elink_cl45_read(sc, phy, MDIO_PMA_DEVAD,
6539 MDIO_PMA_REG_ROM_VER1, &fw_ver1);
6540 elink_cl45_read(sc, phy, MDIO_PMA_DEVAD,
6541 MDIO_PMA_REG_ROM_VER2, &fw_ver2);
6542 elink_save_spirom_version(sc, port,
6543 (uint32_t) (fw_ver1 << 16 | fw_ver2),
6547 static void elink_ext_phy_10G_an_resolve(struct bnx2x_softc *sc,
6548 struct elink_phy *phy,
6549 struct elink_vars *vars)
6552 elink_cl45_read(sc, phy, MDIO_AN_DEVAD, MDIO_AN_REG_STATUS, &val);
6553 elink_cl45_read(sc, phy, MDIO_AN_DEVAD, MDIO_AN_REG_STATUS, &val);
6555 vars->link_status |= LINK_STATUS_AUTO_NEGOTIATE_COMPLETE;
6556 if ((val & (1 << 0)) == 0)
6557 vars->link_status |= LINK_STATUS_PARALLEL_DETECTION_USED;
6560 /******************************************************************/
6561 /* common BNX2X8073/BNX2X8727 PHY SECTION */
6562 /******************************************************************/
6563 static void elink_8073_resolve_fc(struct elink_phy *phy,
6564 struct elink_params *params,
6565 struct elink_vars *vars)
6567 struct bnx2x_softc *sc = params->sc;
6568 if (phy->req_line_speed == ELINK_SPEED_10 ||
6569 phy->req_line_speed == ELINK_SPEED_100) {
6570 vars->flow_ctrl = phy->req_flow_ctrl;
6574 if (elink_ext_phy_resolve_fc(phy, params, vars) &&
6575 (vars->flow_ctrl == ELINK_FLOW_CTRL_NONE)) {
6576 uint16_t pause_result;
6577 uint16_t ld_pause; /* local */
6578 uint16_t lp_pause; /* link partner */
6579 elink_cl45_read(sc, phy,
6581 MDIO_AN_REG_CL37_FC_LD, &ld_pause);
6583 elink_cl45_read(sc, phy,
6585 MDIO_AN_REG_CL37_FC_LP, &lp_pause);
6586 pause_result = (ld_pause &
6587 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) >> 5;
6588 pause_result |= (lp_pause &
6589 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) >> 7;
6591 elink_pause_resolve(vars, pause_result);
6592 PMD_DRV_LOG(DEBUG, sc, "Ext PHY CL37 pause result 0x%x",
6597 static elink_status_t elink_8073_8727_external_rom_boot(struct bnx2x_softc *sc,
6598 struct elink_phy *phy,
6602 uint16_t fw_ver1 = 0, fw_msgout;
6603 elink_status_t rc = ELINK_STATUS_OK;
6605 /* Boot port from external ROM */
6607 elink_cl45_write(sc, phy,
6608 MDIO_PMA_DEVAD, MDIO_PMA_REG_GEN_CTRL, 0x0001);
6610 /* Ucode reboot and rst */
6611 elink_cl45_write(sc, phy,
6612 MDIO_PMA_DEVAD, MDIO_PMA_REG_GEN_CTRL, 0x008c);
6614 elink_cl45_write(sc, phy,
6615 MDIO_PMA_DEVAD, MDIO_PMA_REG_MISC_CTRL1, 0x0001);
6617 /* Reset internal microprocessor */
6618 elink_cl45_write(sc, phy,
6620 MDIO_PMA_REG_GEN_CTRL,
6621 MDIO_PMA_REG_GEN_CTRL_ROM_MICRO_RESET);
6623 /* Release srst bit */
6624 elink_cl45_write(sc, phy,
6626 MDIO_PMA_REG_GEN_CTRL,
6627 MDIO_PMA_REG_GEN_CTRL_ROM_RESET_INTERNAL_MP);
6629 /* Delay 100ms per the PHY specifications */
6632 /* 8073 sometimes taking longer to download */
6636 PMD_DRV_LOG(DEBUG, sc,
6637 "elink_8073_8727_external_rom_boot port %x:"
6638 "Download failed. fw version = 0x%x",
6640 rc = ELINK_STATUS_ERROR;
6644 elink_cl45_read(sc, phy,
6646 MDIO_PMA_REG_ROM_VER1, &fw_ver1);
6647 elink_cl45_read(sc, phy,
6649 MDIO_PMA_REG_M8051_MSGOUT_REG, &fw_msgout);
6652 } while (fw_ver1 == 0 || fw_ver1 == 0x4321 ||
6653 ((fw_msgout & 0xff) != 0x03 && (phy->type ==
6654 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X8073)));
6656 /* Clear ser_boot_ctl bit */
6657 elink_cl45_write(sc, phy,
6658 MDIO_PMA_DEVAD, MDIO_PMA_REG_MISC_CTRL1, 0x0000);
6659 elink_save_bnx2x_spirom_ver(sc, phy, port);
6661 PMD_DRV_LOG(DEBUG, sc,
6662 "elink_8073_8727_external_rom_boot port %x:"
6663 "Download complete. fw version = 0x%x", port, fw_ver1);
6668 /******************************************************************/
6669 /* BNX2X8073 PHY SECTION */
6670 /******************************************************************/
6671 static elink_status_t elink_8073_is_snr_needed(struct bnx2x_softc *sc,
6672 struct elink_phy *phy)
6674 /* This is only required for 8073A1, version 102 only */
6677 /* Read 8073 HW revision */
6678 elink_cl45_read(sc, phy,
6679 MDIO_PMA_DEVAD, MDIO_PMA_REG_8073_CHIP_REV, &val);
6682 /* No need to workaround in 8073 A1 */
6683 return ELINK_STATUS_OK;
6686 elink_cl45_read(sc, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_ROM_VER2, &val);
6688 /* SNR should be applied only for version 0x102 */
6690 return ELINK_STATUS_OK;
6692 return ELINK_STATUS_ERROR;
6695 static elink_status_t elink_8073_xaui_wa(struct bnx2x_softc *sc,
6696 struct elink_phy *phy)
6698 uint16_t val, cnt, cnt1;
6700 elink_cl45_read(sc, phy,
6701 MDIO_PMA_DEVAD, MDIO_PMA_REG_8073_CHIP_REV, &val);
6704 /* No need to workaround in 8073 A1 */
6705 return ELINK_STATUS_OK;
6707 /* XAUI workaround in 8073 A0: */
6709 /* After loading the boot ROM and restarting Autoneg, poll
6713 for (cnt = 0; cnt < 1000; cnt++) {
6714 elink_cl45_read(sc, phy,
6716 MDIO_PMA_REG_8073_SPEED_LINK_STATUS, &val);
6717 /* If bit [14] = 0 or bit [13] = 0, continue on with
6718 * system initialization (XAUI work-around not required, as
6719 * these bits indicate 2.5G or 1G link up).
6721 if (!(val & (1 << 14)) || !(val & (1 << 13))) {
6722 PMD_DRV_LOG(DEBUG, sc, "XAUI work-around not required");
6723 return ELINK_STATUS_OK;
6724 } else if (!(val & (1 << 15))) {
6725 PMD_DRV_LOG(DEBUG, sc, "bit 15 went off");
6726 /* If bit 15 is 0, then poll Dev1, Reg $C841 until it's
6727 * MSB (bit15) goes to 1 (indicating that the XAUI
6728 * workaround has completed), then continue on with
6729 * system initialization.
6731 for (cnt1 = 0; cnt1 < 1000; cnt1++) {
6732 elink_cl45_read(sc, phy,
6734 MDIO_PMA_REG_8073_XAUI_WA,
6736 if (val & (1 << 15)) {
6737 PMD_DRV_LOG(DEBUG, sc,
6738 "XAUI workaround has completed");
6739 return ELINK_STATUS_OK;
6747 PMD_DRV_LOG(DEBUG, sc, "Warning: XAUI work-around timeout !!!");
6748 return ELINK_STATUS_ERROR;
6751 static void elink_807x_force_10G(struct bnx2x_softc *sc, struct elink_phy *phy)
6753 /* Force KR or KX */
6754 elink_cl45_write(sc, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x2040);
6755 elink_cl45_write(sc, phy,
6756 MDIO_PMA_DEVAD, MDIO_PMA_REG_10G_CTRL2, 0x000b);
6757 elink_cl45_write(sc, phy,
6758 MDIO_PMA_DEVAD, MDIO_PMA_REG_BNX2X_CTRL, 0x0000);
6759 elink_cl45_write(sc, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0x0000);
6762 static void elink_8073_set_pause_cl37(struct elink_params *params,
6763 struct elink_phy *phy,
6764 struct elink_vars *vars)
6767 struct bnx2x_softc *sc = params->sc;
6768 elink_cl45_read(sc, phy,
6769 MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LD, &cl37_val);
6771 cl37_val &= ~MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH;
6772 /* Please refer to Table 28B-3 of 802.3ab-1999 spec. */
6773 elink_calc_ieee_aneg_adv(phy, params, &vars->ieee_fc);
6774 if ((vars->ieee_fc &
6775 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_SYMMETRIC) ==
6776 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_SYMMETRIC) {
6777 cl37_val |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_SYMMETRIC;
6779 if ((vars->ieee_fc &
6780 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) ==
6781 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) {
6782 cl37_val |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC;
6784 if ((vars->ieee_fc &
6785 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) ==
6786 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) {
6787 cl37_val |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH;
6789 PMD_DRV_LOG(DEBUG, sc, "Ext phy AN advertize cl37 0x%x", cl37_val);
6791 elink_cl45_write(sc, phy,
6792 MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LD, cl37_val);
6796 static void elink_8073_specific_func(struct elink_phy *phy,
6797 struct elink_params *params,
6800 struct bnx2x_softc *sc = params->sc;
6802 case ELINK_PHY_INIT:
6804 elink_cl45_write(sc, phy,
6805 MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXCTRL,
6807 elink_cl45_write(sc, phy, MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL,
6813 static uint8_t elink_8073_config_init(struct elink_phy *phy,
6814 struct elink_params *params,
6815 struct elink_vars *vars)
6817 struct bnx2x_softc *sc = params->sc;
6818 uint16_t val = 0, tmp1;
6820 PMD_DRV_LOG(DEBUG, sc, "Init 8073");
6823 gpio_port = SC_PATH(sc);
6825 gpio_port = params->port;
6826 /* Restore normal power mode */
6827 elink_cb_gpio_write(sc, MISC_REGISTERS_GPIO_2,
6828 MISC_REGISTERS_GPIO_OUTPUT_HIGH, gpio_port);
6830 elink_cb_gpio_write(sc, MISC_REGISTERS_GPIO_1,
6831 MISC_REGISTERS_GPIO_OUTPUT_HIGH, gpio_port);
6833 elink_8073_specific_func(phy, params, ELINK_PHY_INIT);
6834 elink_8073_set_pause_cl37(params, phy, vars);
6836 elink_cl45_read(sc, phy,
6837 MDIO_PMA_DEVAD, MDIO_PMA_REG_M8051_MSGOUT_REG, &tmp1);
6839 elink_cl45_read(sc, phy, MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXSTAT, &tmp1);
6841 PMD_DRV_LOG(DEBUG, sc, "Before rom RX_ALARM(port1): 0x%x", tmp1);
6843 /* Swap polarity if required - Must be done only in non-1G mode */
6844 if (params->lane_config & PORT_HW_CFG_SWAP_PHY_POLARITY_ENABLED) {
6845 /* Configure the 8073 to swap _P and _N of the KR lines */
6846 PMD_DRV_LOG(DEBUG, sc, "Swapping polarity for the 8073");
6847 /* 10G Rx/Tx and 1G Tx signal polarity swap */
6848 elink_cl45_read(sc, phy,
6850 MDIO_PMA_REG_8073_OPT_DIGITAL_CTRL, &val);
6851 elink_cl45_write(sc, phy,
6853 MDIO_PMA_REG_8073_OPT_DIGITAL_CTRL,
6857 /* Enable CL37 BAM */
6858 if (REG_RD(sc, params->shmem_base +
6859 offsetof(struct shmem_region,
6860 dev_info.port_hw_config[params->port].
6862 PORT_HW_CFG_ENABLE_BAM_ON_KR_ENABLED) {
6864 elink_cl45_read(sc, phy,
6865 MDIO_AN_DEVAD, MDIO_AN_REG_8073_BAM, &val);
6866 elink_cl45_write(sc, phy,
6867 MDIO_AN_DEVAD, MDIO_AN_REG_8073_BAM, val | 1);
6868 PMD_DRV_LOG(DEBUG, sc, "Enable CL37 BAM on KR");
6870 if (params->loopback_mode == ELINK_LOOPBACK_EXT) {
6871 elink_807x_force_10G(sc, phy);
6872 PMD_DRV_LOG(DEBUG, sc, "Forced speed 10G on 807X");
6873 return ELINK_STATUS_OK;
6875 elink_cl45_write(sc, phy,
6876 MDIO_PMA_DEVAD, MDIO_PMA_REG_BNX2X_CTRL, 0x0002);
6878 if (phy->req_line_speed != ELINK_SPEED_AUTO_NEG) {
6879 if (phy->req_line_speed == ELINK_SPEED_10000) {
6881 } else if (phy->req_line_speed == ELINK_SPEED_2500) {
6883 /* Note that 2.5G works only when used with 1G
6890 if (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)
6893 /* Note that 2.5G works only when used with 1G advertisement */
6894 if (phy->speed_cap_mask &
6895 (PORT_HW_CFG_SPEED_CAPABILITY_D0_1G |
6896 PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G))
6898 PMD_DRV_LOG(DEBUG, sc, "807x autoneg val = 0x%x", val);
6901 elink_cl45_write(sc, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV, val);
6902 elink_cl45_read(sc, phy, MDIO_AN_DEVAD, MDIO_AN_REG_8073_2_5G, &tmp1);
6904 if (((phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G) &&
6905 (phy->req_line_speed == ELINK_SPEED_AUTO_NEG)) ||
6906 (phy->req_line_speed == ELINK_SPEED_2500)) {
6908 /* Allow 2.5G for A1 and above */
6909 elink_cl45_read(sc, phy,
6910 MDIO_PMA_DEVAD, MDIO_PMA_REG_8073_CHIP_REV,
6912 PMD_DRV_LOG(DEBUG, sc, "Add 2.5G");
6918 PMD_DRV_LOG(DEBUG, sc, "Disable 2.5G");
6922 elink_cl45_write(sc, phy, MDIO_AN_DEVAD, MDIO_AN_REG_8073_2_5G, tmp1);
6923 /* Add support for CL37 (passive mode) II */
6925 elink_cl45_read(sc, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LD, &tmp1);
6926 elink_cl45_write(sc, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LD,
6927 (tmp1 | ((phy->req_duplex == DUPLEX_FULL) ?
6930 /* Add support for CL37 (passive mode) III */
6931 elink_cl45_write(sc, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CL37_AN, 0x1000);
6933 /* The SNR will improve about 2db by changing BW and FEE main
6934 * tap. Rest commands are executed after link is up
6935 * Change FFE main cursor to 5 in EDC register
6937 if (elink_8073_is_snr_needed(sc, phy))
6938 elink_cl45_write(sc, phy,
6939 MDIO_PMA_DEVAD, MDIO_PMA_REG_EDC_FFE_MAIN,
6942 /* Enable FEC (Forware Error Correction) Request in the AN */
6943 elink_cl45_read(sc, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV2, &tmp1);
6945 elink_cl45_write(sc, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV2, tmp1);
6947 elink_ext_phy_set_pause(params, phy, vars);
6949 /* Restart autoneg */
6951 elink_cl45_write(sc, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0x1200);
6952 PMD_DRV_LOG(DEBUG, sc, "807x Autoneg Restart: Advertise 1G=%x, 10G=%x",
6953 ((val & (1 << 5)) > 0), ((val & (1 << 7)) > 0));
6954 return ELINK_STATUS_OK;
6957 static uint8_t elink_8073_read_status(struct elink_phy *phy,
6958 struct elink_params *params,
6959 struct elink_vars *vars)
6961 struct bnx2x_softc *sc = params->sc;
6962 uint8_t link_up = 0;
6963 uint16_t val1, val2;
6964 uint16_t link_status = 0;
6965 uint16_t an1000_status = 0;
6967 elink_cl45_read(sc, phy, MDIO_PMA_DEVAD, MDIO_PMA_LASI_STAT, &val1);
6969 PMD_DRV_LOG(DEBUG, sc, "8703 LASI status 0x%x", val1);
6971 /* Clear the interrupt LASI status register */
6972 elink_cl45_read(sc, phy, MDIO_PCS_DEVAD, MDIO_PCS_REG_STATUS, &val2);
6973 elink_cl45_read(sc, phy, MDIO_PCS_DEVAD, MDIO_PCS_REG_STATUS, &val1);
6974 PMD_DRV_LOG(DEBUG, sc, "807x PCS status 0x%x->0x%x", val2, val1);
6976 elink_cl45_read(sc, phy,
6977 MDIO_PMA_DEVAD, MDIO_PMA_REG_M8051_MSGOUT_REG, &val1);
6979 /* Check the LASI */
6980 elink_cl45_read(sc, phy, MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXSTAT, &val2);
6982 PMD_DRV_LOG(DEBUG, sc, "KR 0x9003 0x%x", val2);
6984 /* Check the link status */
6985 elink_cl45_read(sc, phy, MDIO_PCS_DEVAD, MDIO_PCS_REG_STATUS, &val2);
6986 PMD_DRV_LOG(DEBUG, sc, "KR PCS status 0x%x", val2);
6988 elink_cl45_read(sc, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val2);
6989 elink_cl45_read(sc, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val1);
6990 link_up = ((val1 & 4) == 4);
6991 PMD_DRV_LOG(DEBUG, sc, "PMA_REG_STATUS=0x%x", val1);
6993 if (link_up && ((phy->req_line_speed != ELINK_SPEED_10000))) {
6994 if (elink_8073_xaui_wa(sc, phy) != 0)
6997 elink_cl45_read(sc, phy,
6998 MDIO_AN_DEVAD, MDIO_AN_REG_LINK_STATUS, &an1000_status);
6999 elink_cl45_read(sc, phy,
7000 MDIO_AN_DEVAD, MDIO_AN_REG_LINK_STATUS, &an1000_status);
7002 /* Check the link status on 1.1.2 */
7003 elink_cl45_read(sc, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val2);
7004 elink_cl45_read(sc, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val1);
7005 PMD_DRV_LOG(DEBUG, sc, "KR PMA status 0x%x->0x%x,"
7006 "an_link_status=0x%x", val2, val1, an1000_status);
7008 link_up = (((val1 & 4) == 4) || (an1000_status & (1 << 1)));
7009 if (link_up && elink_8073_is_snr_needed(sc, phy)) {
7010 /* The SNR will improve about 2dbby changing the BW and FEE main
7011 * tap. The 1st write to change FFE main tap is set before
7012 * restart AN. Change PLL Bandwidth in EDC register
7014 elink_cl45_write(sc, phy,
7015 MDIO_PMA_DEVAD, MDIO_PMA_REG_PLL_BANDWIDTH,
7018 /* Change CDR Bandwidth in EDC register */
7019 elink_cl45_write(sc, phy,
7020 MDIO_PMA_DEVAD, MDIO_PMA_REG_CDR_BANDWIDTH,
7023 elink_cl45_read(sc, phy,
7024 MDIO_PMA_DEVAD, MDIO_PMA_REG_8073_SPEED_LINK_STATUS,
7027 /* Bits 0..2 --> speed detected, bits 13..15--> link is down */
7028 if ((link_status & (1 << 2)) && (!(link_status & (1 << 15)))) {
7030 vars->line_speed = ELINK_SPEED_10000;
7031 PMD_DRV_LOG(DEBUG, sc, "port %x: External link up in 10G",
7033 } else if ((link_status & (1 << 1)) && (!(link_status & (1 << 14)))) {
7035 vars->line_speed = ELINK_SPEED_2500;
7036 PMD_DRV_LOG(DEBUG, sc, "port %x: External link up in 2.5G",
7038 } else if ((link_status & (1 << 0)) && (!(link_status & (1 << 13)))) {
7040 vars->line_speed = ELINK_SPEED_1000;
7041 PMD_DRV_LOG(DEBUG, sc, "port %x: External link up in 1G",
7045 PMD_DRV_LOG(DEBUG, sc, "port %x: External link is down",
7050 /* Swap polarity if required */
7051 if (params->lane_config & PORT_HW_CFG_SWAP_PHY_POLARITY_ENABLED) {
7052 /* Configure the 8073 to swap P and N of the KR lines */
7053 elink_cl45_read(sc, phy,
7055 MDIO_XS_REG_8073_RX_CTRL_PCIE, &val1);
7056 /* Set bit 3 to invert Rx in 1G mode and clear this bit
7057 * when it`s in 10G mode.
7059 if (vars->line_speed == ELINK_SPEED_1000) {
7060 PMD_DRV_LOG(DEBUG, sc, "Swapping 1G polarity for"
7066 elink_cl45_write(sc, phy,
7068 MDIO_XS_REG_8073_RX_CTRL_PCIE, val1);
7070 elink_ext_phy_10G_an_resolve(sc, phy, vars);
7071 elink_8073_resolve_fc(phy, params, vars);
7072 vars->duplex = DUPLEX_FULL;
7075 if (vars->link_status & LINK_STATUS_AUTO_NEGOTIATE_COMPLETE) {
7076 elink_cl45_read(sc, phy, MDIO_AN_DEVAD,
7077 MDIO_AN_REG_LP_AUTO_NEG2, &val1);
7079 if (val1 & (1 << 5))
7080 vars->link_status |=
7081 LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE;
7082 if (val1 & (1 << 7))
7083 vars->link_status |=
7084 LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE;
7090 static void elink_8073_link_reset(__rte_unused struct elink_phy *phy,
7091 struct elink_params *params)
7093 struct bnx2x_softc *sc = params->sc;
7096 gpio_port = SC_PATH(sc);
7098 gpio_port = params->port;
7099 PMD_DRV_LOG(DEBUG, sc, "Setting 8073 port %d into low power mode",
7101 elink_cb_gpio_write(sc, MISC_REGISTERS_GPIO_2,
7102 MISC_REGISTERS_GPIO_OUTPUT_LOW, gpio_port);
7105 /******************************************************************/
7106 /* BNX2X8705 PHY SECTION */
7107 /******************************************************************/
7108 static uint8_t elink_8705_config_init(struct elink_phy *phy,
7109 struct elink_params *params,
7110 __rte_unused struct elink_vars
7113 struct bnx2x_softc *sc = params->sc;
7114 PMD_DRV_LOG(DEBUG, sc, "init 8705");
7115 /* Restore normal power mode */
7116 elink_cb_gpio_write(sc, MISC_REGISTERS_GPIO_2,
7117 MISC_REGISTERS_GPIO_OUTPUT_HIGH, params->port);
7119 elink_ext_phy_hw_reset(sc, params->port);
7120 elink_cl45_write(sc, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0xa040);
7121 elink_wait_reset_complete(sc, phy, params);
7123 elink_cl45_write(sc, phy,
7124 MDIO_PMA_DEVAD, MDIO_PMA_REG_MISC_CTRL, 0x8288);
7125 elink_cl45_write(sc, phy,
7126 MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER, 0x7fbf);
7127 elink_cl45_write(sc, phy,
7128 MDIO_PMA_DEVAD, MDIO_PMA_REG_CMU_PLL_BYPASS, 0x0100);
7129 elink_cl45_write(sc, phy, MDIO_WIS_DEVAD, MDIO_WIS_REG_LASI_CNTL, 0x1);
7130 /* BNX2X8705 doesn't have microcode, hence the 0 */
7131 elink_save_spirom_version(sc, params->port, params->shmem_base, 0);
7132 return ELINK_STATUS_OK;
7135 static uint8_t elink_8705_read_status(struct elink_phy *phy,
7136 struct elink_params *params,
7137 struct elink_vars *vars)
7139 uint8_t link_up = 0;
7140 uint16_t val1, rx_sd;
7141 struct bnx2x_softc *sc = params->sc;
7142 PMD_DRV_LOG(DEBUG, sc, "read status 8705");
7143 elink_cl45_read(sc, phy,
7144 MDIO_WIS_DEVAD, MDIO_WIS_REG_LASI_STATUS, &val1);
7145 PMD_DRV_LOG(DEBUG, sc, "8705 LASI status 0x%x", val1);
7147 elink_cl45_read(sc, phy,
7148 MDIO_WIS_DEVAD, MDIO_WIS_REG_LASI_STATUS, &val1);
7149 PMD_DRV_LOG(DEBUG, sc, "8705 LASI status 0x%x", val1);
7151 elink_cl45_read(sc, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_RX_SD, &rx_sd);
7153 elink_cl45_read(sc, phy, MDIO_PMA_DEVAD, 0xc809, &val1);
7154 elink_cl45_read(sc, phy, MDIO_PMA_DEVAD, 0xc809, &val1);
7156 PMD_DRV_LOG(DEBUG, sc, "8705 1.c809 val=0x%x", val1);
7157 link_up = ((rx_sd & 0x1) && (val1 & (1 << 9))
7158 && ((val1 & (1 << 8)) == 0));
7160 vars->line_speed = ELINK_SPEED_10000;
7161 elink_ext_phy_resolve_fc(phy, params, vars);
7166 /******************************************************************/
7167 /* SFP+ module Section */
7168 /******************************************************************/
7169 static void elink_set_disable_pmd_transmit(struct elink_params *params,
7170 struct elink_phy *phy,
7173 struct bnx2x_softc *sc = params->sc;
7174 /* Disable transmitter only for bootcodes which can enable it afterwards
7178 if (params->feature_config_flags &
7179 ELINK_FEATURE_CONFIG_BC_SUPPORTS_SFP_TX_DISABLED) {
7180 PMD_DRV_LOG(DEBUG, sc, "Disabling PMD transmitter");
7182 PMD_DRV_LOG(DEBUG, sc, "NOT disabling PMD transmitter");
7186 PMD_DRV_LOG(DEBUG, sc, "Enabling PMD transmitter");
7188 elink_cl45_write(sc, phy,
7189 MDIO_PMA_DEVAD, MDIO_PMA_REG_TX_DISABLE, pmd_dis);
7192 static uint8_t elink_get_gpio_port(struct elink_params *params)
7195 uint32_t swap_val, swap_override;
7196 struct bnx2x_softc *sc = params->sc;
7197 if (CHIP_IS_E2(sc)) {
7198 gpio_port = SC_PATH(sc);
7200 gpio_port = params->port;
7202 swap_val = REG_RD(sc, NIG_REG_PORT_SWAP);
7203 swap_override = REG_RD(sc, NIG_REG_STRAP_OVERRIDE);
7204 return gpio_port ^ (swap_val && swap_override);
7207 static void elink_sfp_e1e2_set_transmitter(struct elink_params *params,
7208 struct elink_phy *phy, uint8_t tx_en)
7211 uint8_t port = params->port;
7212 struct bnx2x_softc *sc = params->sc;
7213 uint32_t tx_en_mode;
7215 /* Disable/Enable transmitter ( TX laser of the SFP+ module.) */
7216 tx_en_mode = REG_RD(sc, params->shmem_base +
7217 offsetof(struct shmem_region,
7218 dev_info.port_hw_config[port].sfp_ctrl)) &
7219 PORT_HW_CFG_TX_LASER_MASK;
7220 PMD_DRV_LOG(DEBUG, sc, "Setting transmitter tx_en=%x for port %x "
7221 "mode = %x", tx_en, port, tx_en_mode);
7222 switch (tx_en_mode) {
7223 case PORT_HW_CFG_TX_LASER_MDIO:
7225 elink_cl45_read(sc, phy,
7227 MDIO_PMA_REG_PHY_IDENTIFIER, &val);
7234 elink_cl45_write(sc, phy,
7236 MDIO_PMA_REG_PHY_IDENTIFIER, val);
7238 case PORT_HW_CFG_TX_LASER_GPIO0:
7239 case PORT_HW_CFG_TX_LASER_GPIO1:
7240 case PORT_HW_CFG_TX_LASER_GPIO2:
7241 case PORT_HW_CFG_TX_LASER_GPIO3:
7244 uint8_t gpio_port, gpio_mode;
7246 gpio_mode = MISC_REGISTERS_GPIO_OUTPUT_HIGH;
7248 gpio_mode = MISC_REGISTERS_GPIO_OUTPUT_LOW;
7250 gpio_pin = tx_en_mode - PORT_HW_CFG_TX_LASER_GPIO0;
7251 gpio_port = elink_get_gpio_port(params);
7252 elink_cb_gpio_write(sc, gpio_pin, gpio_mode, gpio_port);
7256 PMD_DRV_LOG(DEBUG, sc,
7257 "Invalid TX_LASER_MDIO 0x%x", tx_en_mode);
7262 static void elink_sfp_set_transmitter(struct elink_params *params,
7263 struct elink_phy *phy, uint8_t tx_en)
7265 struct bnx2x_softc *sc = params->sc;
7266 PMD_DRV_LOG(DEBUG, sc, "Setting SFP+ transmitter to %d", tx_en);
7268 elink_sfp_e3_set_transmitter(params, phy, tx_en);
7270 elink_sfp_e1e2_set_transmitter(params, phy, tx_en);
7273 static elink_status_t elink_8726_read_sfp_module_eeprom(struct elink_phy *phy,
7280 __rte_unused uint8_t
7283 struct bnx2x_softc *sc = params->sc;
7286 if (byte_cnt > ELINK_SFP_EEPROM_PAGE_SIZE) {
7287 PMD_DRV_LOG(DEBUG, sc, "Reading from eeprom is limited to 0xf");
7288 return ELINK_STATUS_ERROR;
7290 /* Set the read command byte count */
7291 elink_cl45_write(sc, phy,
7292 MDIO_PMA_DEVAD, MDIO_PMA_REG_SFP_TWO_WIRE_BYTE_CNT,
7293 (byte_cnt | (dev_addr << 8)));
7295 /* Set the read command address */
7296 elink_cl45_write(sc, phy,
7297 MDIO_PMA_DEVAD, MDIO_PMA_REG_SFP_TWO_WIRE_MEM_ADDR,
7300 /* Activate read command */
7301 elink_cl45_write(sc, phy,
7302 MDIO_PMA_DEVAD, MDIO_PMA_REG_SFP_TWO_WIRE_CTRL,
7305 /* Wait up to 500us for command complete status */
7306 for (i = 0; i < 100; i++) {
7307 elink_cl45_read(sc, phy,
7309 MDIO_PMA_REG_SFP_TWO_WIRE_CTRL, &val);
7310 if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) ==
7311 MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_COMPLETE)
7316 if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) !=
7317 MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_COMPLETE) {
7318 PMD_DRV_LOG(DEBUG, sc,
7319 "Got bad status 0x%x when reading from SFP+ EEPROM",
7320 (val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK));
7321 return ELINK_STATUS_ERROR;
7324 /* Read the buffer */
7325 for (i = 0; i < byte_cnt; i++) {
7326 elink_cl45_read(sc, phy,
7328 MDIO_PMA_REG_8726_TWO_WIRE_DATA_BUF + i, &val);
7330 (uint8_t) (val & MDIO_PMA_REG_8726_TWO_WIRE_DATA_MASK);
7333 for (i = 0; i < 100; i++) {
7334 elink_cl45_read(sc, phy,
7336 MDIO_PMA_REG_SFP_TWO_WIRE_CTRL, &val);
7337 if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) ==
7338 MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_IDLE)
7339 return ELINK_STATUS_OK;
7342 return ELINK_STATUS_ERROR;
7345 static void elink_warpcore_power_module(struct elink_params *params,
7349 struct bnx2x_softc *sc = params->sc;
7351 pin_cfg = (REG_RD(sc, params->shmem_base +
7352 offsetof(struct shmem_region,
7353 dev_info.port_hw_config[params->port].
7354 e3_sfp_ctrl)) & PORT_HW_CFG_E3_PWR_DIS_MASK)
7355 >> PORT_HW_CFG_E3_PWR_DIS_SHIFT;
7357 if (pin_cfg == PIN_CFG_NA)
7359 PMD_DRV_LOG(DEBUG, sc, "Setting SFP+ module power to %d using pin cfg %d",
7361 /* Low ==> corresponding SFP+ module is powered
7362 * high ==> the SFP+ module is powered down
7364 elink_set_cfg_pin(sc, pin_cfg, power ^ 1);
7367 static elink_status_t elink_warpcore_read_sfp_module_eeprom(__rte_unused struct
7377 elink_status_t rc = ELINK_STATUS_OK;
7378 uint8_t i, j = 0, cnt = 0;
7379 uint32_t data_array[4];
7381 struct bnx2x_softc *sc = params->sc;
7383 if (byte_cnt > ELINK_SFP_EEPROM_PAGE_SIZE) {
7384 PMD_DRV_LOG(DEBUG, sc,
7385 "Reading from eeprom is limited to 16 bytes");
7386 return ELINK_STATUS_ERROR;
7389 /* 4 byte aligned address */
7390 addr32 = addr & (~0x3);
7392 if ((!is_init) && (cnt == I2C_WA_PWR_ITER)) {
7393 elink_warpcore_power_module(params, 0);
7394 /* Note that 100us are not enough here */
7396 elink_warpcore_power_module(params, 1);
7398 rc = elink_bsc_read(params, sc, dev_addr, addr32, 0, byte_cnt,
7400 } while ((rc != ELINK_STATUS_OK) && (++cnt < I2C_WA_RETRY_CNT));
7402 if (rc == ELINK_STATUS_OK) {
7403 for (i = (addr - addr32); i < byte_cnt + (addr - addr32); i++) {
7404 o_buf[j] = *((uint8_t *) data_array + i);
7412 static elink_status_t elink_8727_read_sfp_module_eeprom(struct elink_phy *phy,
7419 __rte_unused uint8_t
7422 struct bnx2x_softc *sc = params->sc;
7425 if (byte_cnt > ELINK_SFP_EEPROM_PAGE_SIZE) {
7426 PMD_DRV_LOG(DEBUG, sc, "Reading from eeprom is limited to 0xf");
7427 return ELINK_STATUS_ERROR;
7430 /* Set 2-wire transfer rate of SFP+ module EEPROM
7431 * to 100Khz since some DACs(direct attached cables) do
7432 * not work at 400Khz.
7434 elink_cl45_write(sc, phy,
7436 MDIO_PMA_REG_8727_TWO_WIRE_SLAVE_ADDR,
7437 ((dev_addr << 8) | 1));
7439 /* Need to read from 1.8000 to clear it */
7440 elink_cl45_read(sc, phy,
7441 MDIO_PMA_DEVAD, MDIO_PMA_REG_SFP_TWO_WIRE_CTRL, &val);
7443 /* Set the read command byte count */
7444 elink_cl45_write(sc, phy,
7446 MDIO_PMA_REG_SFP_TWO_WIRE_BYTE_CNT,
7447 ((byte_cnt < 2) ? 2 : byte_cnt));
7449 /* Set the read command address */
7450 elink_cl45_write(sc, phy,
7452 MDIO_PMA_REG_SFP_TWO_WIRE_MEM_ADDR, addr);
7453 /* Set the destination address */
7454 elink_cl45_write(sc, phy,
7456 0x8004, MDIO_PMA_REG_8727_TWO_WIRE_DATA_BUF);
7458 /* Activate read command */
7459 elink_cl45_write(sc, phy,
7461 MDIO_PMA_REG_SFP_TWO_WIRE_CTRL, 0x8002);
7462 /* Wait appropriate time for two-wire command to finish before
7463 * polling the status register
7467 /* Wait up to 500us for command complete status */
7468 for (i = 0; i < 100; i++) {
7469 elink_cl45_read(sc, phy,
7471 MDIO_PMA_REG_SFP_TWO_WIRE_CTRL, &val);
7472 if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) ==
7473 MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_COMPLETE)
7478 if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) !=
7479 MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_COMPLETE) {
7480 PMD_DRV_LOG(DEBUG, sc,
7481 "Got bad status 0x%x when reading from SFP+ EEPROM",
7482 (val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK));
7483 return ELINK_STATUS_TIMEOUT;
7486 /* Read the buffer */
7487 for (i = 0; i < byte_cnt; i++) {
7488 elink_cl45_read(sc, phy,
7490 MDIO_PMA_REG_8727_TWO_WIRE_DATA_BUF + i, &val);
7492 (uint8_t) (val & MDIO_PMA_REG_8727_TWO_WIRE_DATA_MASK);
7495 for (i = 0; i < 100; i++) {
7496 elink_cl45_read(sc, phy,
7498 MDIO_PMA_REG_SFP_TWO_WIRE_CTRL, &val);
7499 if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) ==
7500 MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_IDLE)
7501 return ELINK_STATUS_OK;
7505 return ELINK_STATUS_ERROR;
7508 static elink_status_t elink_read_sfp_module_eeprom(struct elink_phy *phy,
7509 struct elink_params *params,
7515 elink_status_t rc = ELINK_STATUS_OK;
7517 uint8_t *user_data = o_buf;
7518 read_sfp_module_eeprom_func_p read_func;
7520 if ((dev_addr != 0xa0) && (dev_addr != 0xa2)) {
7521 PMD_DRV_LOG(DEBUG, params->sc,
7522 "invalid dev_addr 0x%x", dev_addr);
7523 return ELINK_STATUS_ERROR;
7526 switch (phy->type) {
7527 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X8726:
7528 read_func = elink_8726_read_sfp_module_eeprom;
7530 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X8727:
7531 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X8722:
7532 read_func = elink_8727_read_sfp_module_eeprom;
7534 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT:
7535 read_func = elink_warpcore_read_sfp_module_eeprom;
7538 return ELINK_OP_NOT_SUPPORTED;
7541 while (!rc && (byte_cnt > 0)) {
7542 xfer_size = (byte_cnt > ELINK_SFP_EEPROM_PAGE_SIZE) ?
7543 ELINK_SFP_EEPROM_PAGE_SIZE : byte_cnt;
7544 rc = read_func(phy, params, dev_addr, addr, xfer_size,
7546 byte_cnt -= xfer_size;
7547 user_data += xfer_size;
7553 static elink_status_t elink_get_edc_mode(struct elink_phy *phy,
7554 struct elink_params *params,
7555 uint16_t * edc_mode)
7557 struct bnx2x_softc *sc = params->sc;
7558 uint32_t sync_offset = 0, phy_idx, media_types;
7559 uint8_t gport, val[2], check_limiting_mode = 0;
7560 *edc_mode = ELINK_EDC_MODE_LIMITING;
7561 phy->media_type = ELINK_ETH_PHY_UNSPECIFIED;
7562 /* First check for copper cable */
7563 if (elink_read_sfp_module_eeprom(phy,
7565 ELINK_I2C_DEV_ADDR_A0,
7566 ELINK_SFP_EEPROM_CON_TYPE_ADDR,
7567 2, (uint8_t *) val) != 0) {
7568 PMD_DRV_LOG(DEBUG, sc, "Failed to read from SFP+ module EEPROM");
7569 return ELINK_STATUS_ERROR;
7573 case ELINK_SFP_EEPROM_CON_TYPE_VAL_COPPER:
7575 uint8_t copper_module_type;
7576 phy->media_type = ELINK_ETH_PHY_DA_TWINAX;
7577 /* Check if its active cable (includes SFP+ module)
7580 if (elink_read_sfp_module_eeprom(phy,
7582 ELINK_I2C_DEV_ADDR_A0,
7583 ELINK_SFP_EEPROM_FC_TX_TECH_ADDR,
7585 &copper_module_type) !=
7587 PMD_DRV_LOG(DEBUG, sc,
7588 "Failed to read copper-cable-type"
7589 " from SFP+ EEPROM");
7590 return ELINK_STATUS_ERROR;
7593 if (copper_module_type &
7594 ELINK_SFP_EEPROM_FC_TX_TECH_BITMASK_COPPER_ACTIVE) {
7595 PMD_DRV_LOG(DEBUG, sc,
7596 "Active Copper cable detected");
7598 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT)
7599 *edc_mode = ELINK_EDC_MODE_ACTIVE_DAC;
7601 check_limiting_mode = 1;
7602 } else if (copper_module_type &
7603 ELINK_SFP_EEPROM_FC_TX_TECH_BITMASK_COPPER_PASSIVE)
7605 PMD_DRV_LOG(DEBUG, sc,
7606 "Passive Copper cable detected");
7607 *edc_mode = ELINK_EDC_MODE_PASSIVE_DAC;
7609 PMD_DRV_LOG(DEBUG, sc,
7610 "Unknown copper-cable-type 0x%x !!!",
7611 copper_module_type);
7612 return ELINK_STATUS_ERROR;
7616 case ELINK_SFP_EEPROM_CON_TYPE_VAL_LC:
7617 case ELINK_SFP_EEPROM_CON_TYPE_VAL_RJ45:
7618 check_limiting_mode = 1;
7619 if ((val[1] & (ELINK_SFP_EEPROM_COMP_CODE_SR_MASK |
7620 ELINK_SFP_EEPROM_COMP_CODE_LR_MASK |
7621 ELINK_SFP_EEPROM_COMP_CODE_LRM_MASK)) == 0) {
7622 PMD_DRV_LOG(DEBUG, sc, "1G SFP module detected");
7623 gport = params->port;
7624 phy->media_type = ELINK_ETH_PHY_SFP_1G_FIBER;
7625 if (phy->req_line_speed != ELINK_SPEED_1000) {
7626 phy->req_line_speed = ELINK_SPEED_1000;
7627 if (!CHIP_IS_E1x(sc)) {
7628 gport = SC_PATH(sc) +
7629 (params->port << 1);
7631 elink_cb_event_log(sc, ELINK_LOG_ID_NON_10G_MODULE, gport); //"Warning: Link speed was forced to 1000Mbps."
7632 // " Current SFP module in port %d is not"
7633 // " compliant with 10G Ethernet",
7637 int idx, cfg_idx = 0;
7638 PMD_DRV_LOG(DEBUG, sc, "10G Optic module detected");
7639 for (idx = ELINK_INT_PHY; idx < ELINK_MAX_PHYS; idx++) {
7640 if (params->phy[idx].type == phy->type) {
7641 cfg_idx = ELINK_LINK_CONFIG_IDX(idx);
7645 phy->media_type = ELINK_ETH_PHY_SFPP_10G_FIBER;
7646 phy->req_line_speed = params->req_line_speed[cfg_idx];
7650 PMD_DRV_LOG(DEBUG, sc, "Unable to determine module type 0x%x !!!",
7652 return ELINK_STATUS_ERROR;
7654 sync_offset = params->shmem_base +
7655 offsetof(struct shmem_region,
7656 dev_info.port_hw_config[params->port].media_type);
7657 media_types = REG_RD(sc, sync_offset);
7658 /* Update media type for non-PMF sync */
7659 for (phy_idx = ELINK_INT_PHY; phy_idx < ELINK_MAX_PHYS; phy_idx++) {
7660 if (&(params->phy[phy_idx]) == phy) {
7661 media_types &= ~(PORT_HW_CFG_MEDIA_TYPE_PHY0_MASK <<
7662 (PORT_HW_CFG_MEDIA_TYPE_PHY1_SHIFT *
7666 media_type & PORT_HW_CFG_MEDIA_TYPE_PHY0_MASK) <<
7667 (PORT_HW_CFG_MEDIA_TYPE_PHY1_SHIFT * phy_idx));
7671 REG_WR(sc, sync_offset, media_types);
7672 if (check_limiting_mode) {
7673 uint8_t options[ELINK_SFP_EEPROM_OPTIONS_SIZE];
7674 if (elink_read_sfp_module_eeprom(phy,
7676 ELINK_I2C_DEV_ADDR_A0,
7677 ELINK_SFP_EEPROM_OPTIONS_ADDR,
7678 ELINK_SFP_EEPROM_OPTIONS_SIZE,
7680 PMD_DRV_LOG(DEBUG, sc,
7681 "Failed to read Option field from module EEPROM");
7682 return ELINK_STATUS_ERROR;
7684 if ((options[0] & ELINK_SFP_EEPROM_OPTIONS_LINEAR_RX_OUT_MASK))
7685 *edc_mode = ELINK_EDC_MODE_LINEAR;
7687 *edc_mode = ELINK_EDC_MODE_LIMITING;
7689 PMD_DRV_LOG(DEBUG, sc, "EDC mode is set to 0x%x", *edc_mode);
7690 return ELINK_STATUS_OK;
7693 /* This function read the relevant field from the module (SFP+), and verify it
7694 * is compliant with this board
7696 static elink_status_t elink_verify_sfp_module(struct elink_phy *phy,
7697 struct elink_params *params)
7699 struct bnx2x_softc *sc = params->sc;
7701 uint32_t fw_resp, fw_cmd_param;
7702 char vendor_name[ELINK_SFP_EEPROM_VENDOR_NAME_SIZE + 1];
7703 char vendor_pn[ELINK_SFP_EEPROM_PART_NO_SIZE + 1];
7704 phy->flags &= ~ELINK_FLAGS_SFP_NOT_APPROVED;
7705 val = REG_RD(sc, params->shmem_base +
7706 offsetof(struct shmem_region,
7707 dev_info.port_feature_config[params->port].
7709 if ((val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) ==
7710 PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_NO_ENFORCEMENT) {
7711 PMD_DRV_LOG(DEBUG, sc, "NOT enforcing module verification");
7712 return ELINK_STATUS_OK;
7715 if (params->feature_config_flags &
7716 ELINK_FEATURE_CONFIG_BC_SUPPORTS_DUAL_PHY_OPT_MDL_VRFY) {
7717 /* Use specific phy request */
7718 cmd = DRV_MSG_CODE_VRFY_SPECIFIC_PHY_OPT_MDL;
7719 } else if (params->feature_config_flags &
7720 ELINK_FEATURE_CONFIG_BC_SUPPORTS_OPT_MDL_VRFY) {
7721 /* Use first phy request only in case of non-dual media */
7722 if (ELINK_DUAL_MEDIA(params)) {
7723 PMD_DRV_LOG(DEBUG, sc,
7724 "FW does not support OPT MDL verification");
7725 return ELINK_STATUS_ERROR;
7727 cmd = DRV_MSG_CODE_VRFY_FIRST_PHY_OPT_MDL;
7729 /* No support in OPT MDL detection */
7730 PMD_DRV_LOG(DEBUG, sc, "FW does not support OPT MDL verification");
7731 return ELINK_STATUS_ERROR;
7734 fw_cmd_param = ELINK_FW_PARAM_SET(phy->addr, phy->type, phy->mdio_ctrl);
7735 fw_resp = elink_cb_fw_command(sc, cmd, fw_cmd_param);
7736 if (fw_resp == FW_MSG_CODE_VRFY_OPT_MDL_SUCCESS) {
7737 PMD_DRV_LOG(DEBUG, sc, "Approved module");
7738 return ELINK_STATUS_OK;
7741 /* Format the warning message */
7742 if (elink_read_sfp_module_eeprom(phy,
7744 ELINK_I2C_DEV_ADDR_A0,
7745 ELINK_SFP_EEPROM_VENDOR_NAME_ADDR,
7746 ELINK_SFP_EEPROM_VENDOR_NAME_SIZE,
7747 (uint8_t *) vendor_name))
7748 vendor_name[0] = '\0';
7750 vendor_name[ELINK_SFP_EEPROM_VENDOR_NAME_SIZE] = '\0';
7751 if (elink_read_sfp_module_eeprom(phy,
7753 ELINK_I2C_DEV_ADDR_A0,
7754 ELINK_SFP_EEPROM_PART_NO_ADDR,
7755 ELINK_SFP_EEPROM_PART_NO_SIZE,
7756 (uint8_t *) vendor_pn))
7757 vendor_pn[0] = '\0';
7759 vendor_pn[ELINK_SFP_EEPROM_PART_NO_SIZE] = '\0';
7761 elink_cb_event_log(sc, ELINK_LOG_ID_UNQUAL_IO_MODULE, params->port, vendor_name, vendor_pn); // "Warning: Unqualified SFP+ module detected,"
7762 // " Port %d from %s part number %s",
7764 if ((val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) !=
7765 PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_WARNING_MSG)
7766 phy->flags |= ELINK_FLAGS_SFP_NOT_APPROVED;
7767 return ELINK_STATUS_ERROR;
7770 static elink_status_t elink_wait_for_sfp_module_initialized(struct elink_phy
7778 /* Initialization time after hot-plug may take up to 300ms for
7779 * some phys type ( e.g. JDSU )
7782 for (timeout = 0; timeout < 60; timeout++) {
7783 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT)
7784 rc = elink_warpcore_read_sfp_module_eeprom(phy, params,
7785 ELINK_I2C_DEV_ADDR_A0,
7789 rc = elink_read_sfp_module_eeprom(phy, params,
7790 ELINK_I2C_DEV_ADDR_A0,
7793 PMD_DRV_LOG(DEBUG, params->sc,
7794 "SFP+ module initialization took %d ms",
7796 return ELINK_STATUS_OK;
7800 rc = elink_read_sfp_module_eeprom(phy, params, ELINK_I2C_DEV_ADDR_A0,
7805 static void elink_8727_power_module(struct bnx2x_softc *sc,
7806 struct elink_phy *phy, uint8_t is_power_up)
7808 /* Make sure GPIOs are not using for LED mode */
7810 /* In the GPIO register, bit 4 is use to determine if the GPIOs are
7811 * operating as INPUT or as OUTPUT. Bit 1 is for input, and 0 for
7813 * Bits 0-1 determine the GPIOs value for OUTPUT in case bit 4 val is 0
7814 * Bits 8-9 determine the GPIOs value for INPUT in case bit 4 val is 1
7815 * where the 1st bit is the over-current(only input), and 2nd bit is
7816 * for power( only output )
7818 * In case of NOC feature is disabled and power is up, set GPIO control
7819 * as input to enable listening of over-current indication
7821 if (phy->flags & ELINK_FLAGS_NOC)
7826 /* Set GPIO control to OUTPUT, and set the power bit
7827 * to according to the is_power_up
7831 elink_cl45_write(sc, phy,
7832 MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_GPIO_CTRL, val);
7835 static elink_status_t elink_8726_set_limiting_mode(struct bnx2x_softc *sc,
7836 struct elink_phy *phy,
7839 uint16_t cur_limiting_mode;
7841 elink_cl45_read(sc, phy,
7843 MDIO_PMA_REG_ROM_VER2, &cur_limiting_mode);
7844 PMD_DRV_LOG(DEBUG, sc,
7845 "Current Limiting mode is 0x%x", cur_limiting_mode);
7847 if (edc_mode == ELINK_EDC_MODE_LIMITING) {
7848 PMD_DRV_LOG(DEBUG, sc, "Setting LIMITING MODE");
7849 elink_cl45_write(sc, phy,
7851 MDIO_PMA_REG_ROM_VER2,
7852 ELINK_EDC_MODE_LIMITING);
7853 } else { /* LRM mode ( default ) */
7855 PMD_DRV_LOG(DEBUG, sc, "Setting LRM MODE");
7857 /* Changing to LRM mode takes quite few seconds. So do it only
7858 * if current mode is limiting (default is LRM)
7860 if (cur_limiting_mode != ELINK_EDC_MODE_LIMITING)
7861 return ELINK_STATUS_OK;
7863 elink_cl45_write(sc, phy,
7864 MDIO_PMA_DEVAD, MDIO_PMA_REG_LRM_MODE, 0);
7865 elink_cl45_write(sc, phy,
7866 MDIO_PMA_DEVAD, MDIO_PMA_REG_ROM_VER2, 0x128);
7867 elink_cl45_write(sc, phy,
7869 MDIO_PMA_REG_MISC_CTRL0, 0x4008);
7870 elink_cl45_write(sc, phy,
7871 MDIO_PMA_DEVAD, MDIO_PMA_REG_LRM_MODE, 0xaaaa);
7873 return ELINK_STATUS_OK;
7876 static elink_status_t elink_8727_set_limiting_mode(struct bnx2x_softc *sc,
7877 struct elink_phy *phy,
7880 uint16_t phy_identifier;
7881 uint16_t rom_ver2_val;
7882 elink_cl45_read(sc, phy,
7884 MDIO_PMA_REG_PHY_IDENTIFIER, &phy_identifier);
7886 elink_cl45_write(sc, phy,
7888 MDIO_PMA_REG_PHY_IDENTIFIER,
7889 (phy_identifier & ~(1 << 9)));
7891 elink_cl45_read(sc, phy,
7892 MDIO_PMA_DEVAD, MDIO_PMA_REG_ROM_VER2, &rom_ver2_val);
7893 /* Keep the MSB 8-bits, and set the LSB 8-bits with the edc_mode */
7894 elink_cl45_write(sc, phy,
7896 MDIO_PMA_REG_ROM_VER2,
7897 (rom_ver2_val & 0xff00) | (edc_mode & 0x00ff));
7899 elink_cl45_write(sc, phy,
7901 MDIO_PMA_REG_PHY_IDENTIFIER,
7902 (phy_identifier | (1 << 9)));
7904 return ELINK_STATUS_OK;
7907 static void elink_8727_specific_func(struct elink_phy *phy,
7908 struct elink_params *params,
7911 struct bnx2x_softc *sc = params->sc;
7914 case ELINK_DISABLE_TX:
7915 elink_sfp_set_transmitter(params, phy, 0);
7917 case ELINK_ENABLE_TX:
7918 if (!(phy->flags & ELINK_FLAGS_SFP_NOT_APPROVED))
7919 elink_sfp_set_transmitter(params, phy, 1);
7921 case ELINK_PHY_INIT:
7922 elink_cl45_write(sc, phy,
7923 MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXCTRL,
7924 (1 << 2) | (1 << 5));
7925 elink_cl45_write(sc, phy,
7926 MDIO_PMA_DEVAD, MDIO_PMA_LASI_TXCTRL, 0);
7927 elink_cl45_write(sc, phy,
7928 MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 0x0006);
7929 /* Make MOD_ABS give interrupt on change */
7930 elink_cl45_read(sc, phy, MDIO_PMA_DEVAD,
7931 MDIO_PMA_REG_8727_PCS_OPT_CTRL, &val);
7933 if (phy->flags & ELINK_FLAGS_NOC)
7935 /* Set 8727 GPIOs to input to allow reading from the 8727 GPIO0
7936 * status which reflect SFP+ module over-current
7938 if (!(phy->flags & ELINK_FLAGS_NOC))
7939 val &= 0xff8f; /* Reset bits 4-6 */
7940 elink_cl45_write(sc, phy,
7941 MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_PCS_OPT_CTRL,
7945 PMD_DRV_LOG(DEBUG, sc, "Function 0x%x not supported by 8727",
7951 static void elink_set_e1e2_module_fault_led(struct elink_params *params,
7954 struct bnx2x_softc *sc = params->sc;
7956 uint32_t fault_led_gpio = REG_RD(sc, params->shmem_base +
7957 offsetof(struct shmem_region,
7959 port_hw_config[params->port].
7961 PORT_HW_CFG_FAULT_MODULE_LED_MASK;
7962 switch (fault_led_gpio) {
7963 case PORT_HW_CFG_FAULT_MODULE_LED_DISABLED:
7965 case PORT_HW_CFG_FAULT_MODULE_LED_GPIO0:
7966 case PORT_HW_CFG_FAULT_MODULE_LED_GPIO1:
7967 case PORT_HW_CFG_FAULT_MODULE_LED_GPIO2:
7968 case PORT_HW_CFG_FAULT_MODULE_LED_GPIO3:
7970 uint8_t gpio_port = elink_get_gpio_port(params);
7971 uint16_t gpio_pin = fault_led_gpio -
7972 PORT_HW_CFG_FAULT_MODULE_LED_GPIO0;
7973 PMD_DRV_LOG(DEBUG, sc, "Set fault module-detected led "
7974 "pin %x port %x mode %x",
7975 gpio_pin, gpio_port, gpio_mode);
7976 elink_cb_gpio_write(sc, gpio_pin, gpio_mode, gpio_port);
7980 PMD_DRV_LOG(DEBUG, sc, "Error: Invalid fault led mode 0x%x",
7985 static void elink_set_e3_module_fault_led(struct elink_params *params,
7989 uint8_t port = params->port;
7990 struct bnx2x_softc *sc = params->sc;
7991 pin_cfg = (REG_RD(sc, params->shmem_base +
7992 offsetof(struct shmem_region,
7993 dev_info.port_hw_config[port].e3_sfp_ctrl)) &
7994 PORT_HW_CFG_E3_FAULT_MDL_LED_MASK) >>
7995 PORT_HW_CFG_E3_FAULT_MDL_LED_SHIFT;
7996 PMD_DRV_LOG(DEBUG, sc, "Setting Fault LED to %d using pin cfg %d",
7997 gpio_mode, pin_cfg);
7998 elink_set_cfg_pin(sc, pin_cfg, gpio_mode);
8001 static void elink_set_sfp_module_fault_led(struct elink_params *params,
8004 struct bnx2x_softc *sc = params->sc;
8005 PMD_DRV_LOG(DEBUG, sc,
8006 "Setting SFP+ module fault LED to %d", gpio_mode);
8007 if (CHIP_IS_E3(sc)) {
8008 /* Low ==> if SFP+ module is supported otherwise
8009 * High ==> if SFP+ module is not on the approved vendor list
8011 elink_set_e3_module_fault_led(params, gpio_mode);
8013 elink_set_e1e2_module_fault_led(params, gpio_mode);
8016 static void elink_warpcore_hw_reset(__rte_unused struct elink_phy *phy,
8017 struct elink_params *params)
8019 struct bnx2x_softc *sc = params->sc;
8020 elink_warpcore_power_module(params, 0);
8021 /* Put Warpcore in low power mode */
8022 REG_WR(sc, MISC_REG_WC0_RESET, 0x0c0e);
8024 /* Put LCPLL in low power mode */
8025 REG_WR(sc, MISC_REG_LCPLL_E40_PWRDWN, 1);
8026 REG_WR(sc, MISC_REG_LCPLL_E40_RESETB_ANA, 0);
8027 REG_WR(sc, MISC_REG_LCPLL_E40_RESETB_DIG, 0);
8030 static void elink_power_sfp_module(struct elink_params *params,
8031 struct elink_phy *phy, uint8_t power)
8033 PMD_DRV_LOG(DEBUG, params->sc, "Setting SFP+ power to %x", power);
8035 switch (phy->type) {
8036 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X8727:
8037 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X8722:
8038 elink_8727_power_module(params->sc, phy, power);
8040 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT:
8041 elink_warpcore_power_module(params, power);
8048 static void elink_warpcore_set_limiting_mode(struct elink_params *params,
8049 struct elink_phy *phy,
8053 uint16_t mode = MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE_DEFAULT;
8054 struct bnx2x_softc *sc = params->sc;
8056 uint8_t lane = elink_get_warpcore_lane(params);
8057 /* This is a global register which controls all lanes */
8058 elink_cl45_read(sc, phy, MDIO_WC_DEVAD,
8059 MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE, &val);
8060 val &= ~(0xf << (lane << 2));
8063 case ELINK_EDC_MODE_LINEAR:
8064 case ELINK_EDC_MODE_LIMITING:
8065 mode = MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE_DEFAULT;
8067 case ELINK_EDC_MODE_PASSIVE_DAC:
8068 case ELINK_EDC_MODE_ACTIVE_DAC:
8069 mode = MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE_SFP_DAC;
8075 val |= (mode << (lane << 2));
8076 elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
8077 MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE, val);
8079 elink_cl45_read(sc, phy, MDIO_WC_DEVAD,
8080 MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE, &val);
8082 /* Restart microcode to re-read the new mode */
8083 elink_warpcore_reset_lane(sc, phy, 1);
8084 elink_warpcore_reset_lane(sc, phy, 0);
8088 static void elink_set_limiting_mode(struct elink_params *params,
8089 struct elink_phy *phy, uint16_t edc_mode)
8091 switch (phy->type) {
8092 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X8726:
8093 elink_8726_set_limiting_mode(params->sc, phy, edc_mode);
8095 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X8727:
8096 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X8722:
8097 elink_8727_set_limiting_mode(params->sc, phy, edc_mode);
8099 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT:
8100 elink_warpcore_set_limiting_mode(params, phy, edc_mode);
8105 static elink_status_t elink_sfp_module_detection(struct elink_phy *phy,
8106 struct elink_params *params)
8108 struct bnx2x_softc *sc = params->sc;
8110 elink_status_t rc = ELINK_STATUS_OK;
8112 uint32_t val = REG_RD(sc, params->shmem_base +
8113 offsetof(struct shmem_region,
8114 dev_info.port_feature_config[params->
8117 /* Enabled transmitter by default */
8118 elink_sfp_set_transmitter(params, phy, 1);
8119 PMD_DRV_LOG(DEBUG, sc, "SFP+ module plugged in/out detected on port %d",
8121 /* Power up module */
8122 elink_power_sfp_module(params, phy, 1);
8123 if (elink_get_edc_mode(phy, params, &edc_mode) != 0) {
8124 PMD_DRV_LOG(DEBUG, sc, "Failed to get valid module type");
8125 return ELINK_STATUS_ERROR;
8126 } else if (elink_verify_sfp_module(phy, params) != 0) {
8127 /* Check SFP+ module compatibility */
8128 PMD_DRV_LOG(DEBUG, sc, "Module verification failed!!");
8129 rc = ELINK_STATUS_ERROR;
8130 /* Turn on fault module-detected led */
8131 elink_set_sfp_module_fault_led(params,
8132 MISC_REGISTERS_GPIO_HIGH);
8134 /* Check if need to power down the SFP+ module */
8135 if ((val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) ==
8136 PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_POWER_DOWN) {
8137 PMD_DRV_LOG(DEBUG, sc, "Shutdown SFP+ module!!");
8138 elink_power_sfp_module(params, phy, 0);
8142 /* Turn off fault module-detected led */
8143 elink_set_sfp_module_fault_led(params, MISC_REGISTERS_GPIO_LOW);
8146 /* Check and set limiting mode / LRM mode on 8726. On 8727 it
8147 * is done automatically
8149 elink_set_limiting_mode(params, phy, edc_mode);
8151 /* Disable transmit for this module if the module is not approved, and
8152 * laser needs to be disabled.
8155 ((val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) ==
8156 PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_DISABLE_TX_LASER))
8157 elink_sfp_set_transmitter(params, phy, 0);
8162 void elink_handle_module_detect_int(struct elink_params *params)
8164 struct bnx2x_softc *sc = params->sc;
8165 struct elink_phy *phy;
8167 uint8_t gpio_num, gpio_port;
8168 if (CHIP_IS_E3(sc)) {
8169 phy = ¶ms->phy[ELINK_INT_PHY];
8170 /* Always enable TX laser,will be disabled in case of fault */
8171 elink_sfp_set_transmitter(params, phy, 1);
8173 phy = ¶ms->phy[ELINK_EXT_PHY1];
8175 if (elink_get_mod_abs_int_cfg(sc, params->shmem_base,
8176 params->port, &gpio_num, &gpio_port) ==
8177 ELINK_STATUS_ERROR) {
8178 PMD_DRV_LOG(DEBUG, sc, "Failed to get MOD_ABS interrupt config");
8182 /* Set valid module led off */
8183 elink_set_sfp_module_fault_led(params, MISC_REGISTERS_GPIO_HIGH);
8185 /* Get current gpio val reflecting module plugged in / out */
8186 gpio_val = elink_cb_gpio_read(sc, gpio_num, gpio_port);
8188 /* Call the handling function in case module is detected */
8189 if (gpio_val == 0) {
8190 elink_set_mdio_emac_per_phy(sc, params);
8191 elink_set_aer_mmd(params, phy);
8193 elink_power_sfp_module(params, phy, 1);
8194 elink_cb_gpio_int_write(sc, gpio_num,
8195 MISC_REGISTERS_GPIO_INT_OUTPUT_CLR,
8197 if (elink_wait_for_sfp_module_initialized(phy, params) == 0) {
8198 elink_sfp_module_detection(phy, params);
8199 if (CHIP_IS_E3(sc)) {
8200 uint16_t rx_tx_in_reset;
8201 /* In case WC is out of reset, reconfigure the
8202 * link speed while taking into account 1G
8203 * module limitation.
8205 elink_cl45_read(sc, phy,
8207 MDIO_WC_REG_DIGITAL5_MISC6,
8209 if ((!rx_tx_in_reset) &&
8210 (params->link_flags &
8211 ELINK_PHY_INITIALIZED)) {
8212 elink_warpcore_reset_lane(sc, phy, 1);
8213 elink_warpcore_config_sfi(phy, params);
8214 elink_warpcore_reset_lane(sc, phy, 0);
8218 PMD_DRV_LOG(DEBUG, sc, "SFP+ module is not initialized");
8221 elink_cb_gpio_int_write(sc, gpio_num,
8222 MISC_REGISTERS_GPIO_INT_OUTPUT_SET,
8224 /* Module was plugged out.
8225 * Disable transmit for this module
8227 phy->media_type = ELINK_ETH_PHY_NOT_PRESENT;
8231 /******************************************************************/
8232 /* Used by 8706 and 8727 */
8233 /******************************************************************/
8234 static void elink_sfp_mask_fault(struct bnx2x_softc *sc,
8235 struct elink_phy *phy,
8236 uint16_t alarm_status_offset,
8237 uint16_t alarm_ctrl_offset)
8239 uint16_t alarm_status, val;
8240 elink_cl45_read(sc, phy,
8241 MDIO_PMA_DEVAD, alarm_status_offset, &alarm_status);
8242 elink_cl45_read(sc, phy,
8243 MDIO_PMA_DEVAD, alarm_status_offset, &alarm_status);
8244 /* Mask or enable the fault event. */
8245 elink_cl45_read(sc, phy, MDIO_PMA_DEVAD, alarm_ctrl_offset, &val);
8246 if (alarm_status & (1 << 0))
8250 elink_cl45_write(sc, phy, MDIO_PMA_DEVAD, alarm_ctrl_offset, val);
8253 /******************************************************************/
8254 /* common BNX2X8706/BNX2X8726 PHY SECTION */
8255 /******************************************************************/
8256 static uint8_t elink_8706_8726_read_status(struct elink_phy *phy,
8257 struct elink_params *params,
8258 struct elink_vars *vars)
8260 uint8_t link_up = 0;
8261 uint16_t val1, val2, rx_sd, pcs_status;
8262 struct bnx2x_softc *sc = params->sc;
8263 PMD_DRV_LOG(DEBUG, sc, "XGXS 8706/8726");
8264 /* Clear RX Alarm */
8265 elink_cl45_read(sc, phy, MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXSTAT, &val2);
8267 elink_sfp_mask_fault(sc, phy, MDIO_PMA_LASI_TXSTAT,
8268 MDIO_PMA_LASI_TXCTRL);
8270 /* Clear LASI indication */
8271 elink_cl45_read(sc, phy, MDIO_PMA_DEVAD, MDIO_PMA_LASI_STAT, &val1);
8272 elink_cl45_read(sc, phy, MDIO_PMA_DEVAD, MDIO_PMA_LASI_STAT, &val2);
8273 PMD_DRV_LOG(DEBUG, sc,
8274 "8706/8726 LASI status 0x%x--> 0x%x", val1, val2);
8276 elink_cl45_read(sc, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_RX_SD, &rx_sd);
8277 elink_cl45_read(sc, phy,
8278 MDIO_PCS_DEVAD, MDIO_PCS_REG_STATUS, &pcs_status);
8279 elink_cl45_read(sc, phy, MDIO_AN_DEVAD, MDIO_AN_REG_LINK_STATUS, &val2);
8280 elink_cl45_read(sc, phy, MDIO_AN_DEVAD, MDIO_AN_REG_LINK_STATUS, &val2);
8282 PMD_DRV_LOG(DEBUG, sc, "8706/8726 rx_sd 0x%x pcs_status 0x%x 1Gbps"
8283 " link_status 0x%x", rx_sd, pcs_status, val2);
8284 /* Link is up if both bit 0 of pmd_rx_sd and bit 0 of pcs_status
8285 * are set, or if the autoneg bit 1 is set
8287 link_up = ((rx_sd & pcs_status & 0x1) || (val2 & (1 << 1)));
8289 if (val2 & (1 << 1))
8290 vars->line_speed = ELINK_SPEED_1000;
8292 vars->line_speed = ELINK_SPEED_10000;
8293 elink_ext_phy_resolve_fc(phy, params, vars);
8294 vars->duplex = DUPLEX_FULL;
8297 /* Capture 10G link fault. Read twice to clear stale value. */
8298 if (vars->line_speed == ELINK_SPEED_10000) {
8299 elink_cl45_read(sc, phy, MDIO_PMA_DEVAD,
8300 MDIO_PMA_LASI_TXSTAT, &val1);
8301 elink_cl45_read(sc, phy, MDIO_PMA_DEVAD,
8302 MDIO_PMA_LASI_TXSTAT, &val1);
8303 if (val1 & (1 << 0))
8304 vars->fault_detected = 1;
8310 /******************************************************************/
8311 /* BNX2X8706 PHY SECTION */
8312 /******************************************************************/
8313 static uint8_t elink_8706_config_init(struct elink_phy *phy,
8314 struct elink_params *params,
8315 __rte_unused struct elink_vars *vars)
8317 uint32_t tx_en_mode;
8318 uint16_t cnt, val, tmp1;
8319 struct bnx2x_softc *sc = params->sc;
8321 elink_cb_gpio_write(sc, MISC_REGISTERS_GPIO_2,
8322 MISC_REGISTERS_GPIO_OUTPUT_HIGH, params->port);
8324 elink_ext_phy_hw_reset(sc, params->port);
8325 elink_cl45_write(sc, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0xa040);
8326 elink_wait_reset_complete(sc, phy, params);
8328 /* Wait until fw is loaded */
8329 for (cnt = 0; cnt < 100; cnt++) {
8330 elink_cl45_read(sc, phy,
8331 MDIO_PMA_DEVAD, MDIO_PMA_REG_ROM_VER1, &val);
8336 PMD_DRV_LOG(DEBUG, sc, "XGXS 8706 is initialized after %d ms", cnt);
8337 if ((params->feature_config_flags &
8338 ELINK_FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED)) {
8341 for (i = 0; i < 4; i++) {
8342 reg = MDIO_XS_8706_REG_BANK_RX0 +
8343 i * (MDIO_XS_8706_REG_BANK_RX1 -
8344 MDIO_XS_8706_REG_BANK_RX0);
8345 elink_cl45_read(sc, phy, MDIO_XS_DEVAD, reg, &val);
8346 /* Clear first 3 bits of the control */
8348 /* Set control bits according to configuration */
8349 val |= (phy->rx_preemphasis[i] & 0x7);
8350 PMD_DRV_LOG(DEBUG, sc, "Setting RX Equalizer to BNX2X8706"
8351 " reg 0x%x <-- val 0x%x", reg, val);
8352 elink_cl45_write(sc, phy, MDIO_XS_DEVAD, reg, val);
8356 if (phy->req_line_speed == ELINK_SPEED_10000) {
8357 PMD_DRV_LOG(DEBUG, sc, "XGXS 8706 force 10Gbps");
8359 elink_cl45_write(sc, phy,
8361 MDIO_PMA_REG_DIGITAL_CTRL, 0x400);
8362 elink_cl45_write(sc, phy,
8363 MDIO_PMA_DEVAD, MDIO_PMA_LASI_TXCTRL, 0);
8364 /* Arm LASI for link and Tx fault. */
8365 elink_cl45_write(sc, phy,
8366 MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 3);
8368 /* Force 1Gbps using autoneg with 1G advertisement */
8370 /* Allow CL37 through CL73 */
8371 PMD_DRV_LOG(DEBUG, sc, "XGXS 8706 AutoNeg");
8372 elink_cl45_write(sc, phy,
8373 MDIO_AN_DEVAD, MDIO_AN_REG_CL37_CL73, 0x040c);
8375 /* Enable Full-Duplex advertisement on CL37 */
8376 elink_cl45_write(sc, phy,
8377 MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LP, 0x0020);
8378 /* Enable CL37 AN */
8379 elink_cl45_write(sc, phy,
8380 MDIO_AN_DEVAD, MDIO_AN_REG_CL37_AN, 0x1000);
8382 elink_cl45_write(sc, phy,
8383 MDIO_AN_DEVAD, MDIO_AN_REG_ADV, (1 << 5));
8385 /* Enable clause 73 AN */
8386 elink_cl45_write(sc, phy,
8387 MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0x1200);
8388 elink_cl45_write(sc, phy,
8389 MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXCTRL, 0x0400);
8390 elink_cl45_write(sc, phy,
8391 MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 0x0004);
8393 elink_save_bnx2x_spirom_ver(sc, phy, params->port);
8395 /* If TX Laser is controlled by GPIO_0, do not let PHY go into low
8396 * power mode, if TX Laser is disabled
8399 tx_en_mode = REG_RD(sc, params->shmem_base +
8400 offsetof(struct shmem_region,
8401 dev_info.port_hw_config[params->port].
8403 & PORT_HW_CFG_TX_LASER_MASK;
8405 if (tx_en_mode == PORT_HW_CFG_TX_LASER_GPIO0) {
8406 PMD_DRV_LOG(DEBUG, sc, "Enabling TXONOFF_PWRDN_DIS");
8407 elink_cl45_read(sc, phy,
8408 MDIO_PMA_DEVAD, MDIO_PMA_REG_DIGITAL_CTRL,
8411 elink_cl45_write(sc, phy,
8412 MDIO_PMA_DEVAD, MDIO_PMA_REG_DIGITAL_CTRL,
8416 return ELINK_STATUS_OK;
8419 static uint8_t elink_8706_read_status(struct elink_phy *phy,
8420 struct elink_params *params,
8421 struct elink_vars *vars)
8423 return elink_8706_8726_read_status(phy, params, vars);
8426 /******************************************************************/
8427 /* BNX2X8726 PHY SECTION */
8428 /******************************************************************/
8429 static void elink_8726_config_loopback(struct elink_phy *phy,
8430 struct elink_params *params)
8432 struct bnx2x_softc *sc = params->sc;
8433 PMD_DRV_LOG(DEBUG, sc, "PMA/PMD ext_phy_loopback: 8726");
8434 elink_cl45_write(sc, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x0001);
8437 static void elink_8726_external_rom_boot(struct elink_phy *phy,
8438 struct elink_params *params)
8440 struct bnx2x_softc *sc = params->sc;
8441 /* Need to wait 100ms after reset */
8444 /* Micro controller re-boot */
8445 elink_cl45_write(sc, phy,
8446 MDIO_PMA_DEVAD, MDIO_PMA_REG_GEN_CTRL, 0x018B);
8448 /* Set soft reset */
8449 elink_cl45_write(sc, phy,
8451 MDIO_PMA_REG_GEN_CTRL,
8452 MDIO_PMA_REG_GEN_CTRL_ROM_MICRO_RESET);
8454 elink_cl45_write(sc, phy,
8455 MDIO_PMA_DEVAD, MDIO_PMA_REG_MISC_CTRL1, 0x0001);
8457 elink_cl45_write(sc, phy,
8459 MDIO_PMA_REG_GEN_CTRL,
8460 MDIO_PMA_REG_GEN_CTRL_ROM_RESET_INTERNAL_MP);
8462 /* Wait for 150ms for microcode load */
8465 /* Disable serial boot control, tristates pins SS_N, SCK, MOSI, MISO */
8466 elink_cl45_write(sc, phy,
8467 MDIO_PMA_DEVAD, MDIO_PMA_REG_MISC_CTRL1, 0x0000);
8470 elink_save_bnx2x_spirom_ver(sc, phy, params->port);
8473 static uint8_t elink_8726_read_status(struct elink_phy *phy,
8474 struct elink_params *params,
8475 struct elink_vars *vars)
8477 struct bnx2x_softc *sc = params->sc;
8479 uint8_t link_up = elink_8706_8726_read_status(phy, params, vars);
8481 elink_cl45_read(sc, phy,
8482 MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER,
8484 if (val1 & (1 << 15)) {
8485 PMD_DRV_LOG(DEBUG, sc, "Tx is disabled");
8487 vars->line_speed = 0;
8493 static uint8_t elink_8726_config_init(struct elink_phy *phy,
8494 struct elink_params *params,
8495 struct elink_vars *vars)
8497 struct bnx2x_softc *sc = params->sc;
8498 PMD_DRV_LOG(DEBUG, sc, "Initializing BNX2X8726");
8500 elink_cl45_write(sc, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 1 << 15);
8501 elink_wait_reset_complete(sc, phy, params);
8503 elink_8726_external_rom_boot(phy, params);
8505 /* Need to call module detected on initialization since the module
8506 * detection triggered by actual module insertion might occur before
8507 * driver is loaded, and when driver is loaded, it reset all
8508 * registers, including the transmitter
8510 elink_sfp_module_detection(phy, params);
8512 if (phy->req_line_speed == ELINK_SPEED_1000) {
8513 PMD_DRV_LOG(DEBUG, sc, "Setting 1G force");
8514 elink_cl45_write(sc, phy,
8515 MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x40);
8516 elink_cl45_write(sc, phy,
8517 MDIO_PMA_DEVAD, MDIO_PMA_REG_10G_CTRL2, 0xD);
8518 elink_cl45_write(sc, phy,
8519 MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 0x5);
8520 elink_cl45_write(sc, phy,
8521 MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXCTRL, 0x400);
8522 } else if ((phy->req_line_speed == ELINK_SPEED_AUTO_NEG) &&
8523 (phy->speed_cap_mask &
8524 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G) &&
8525 ((phy->speed_cap_mask &
8526 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G) !=
8527 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) {
8528 PMD_DRV_LOG(DEBUG, sc, "Setting 1G clause37");
8529 /* Set Flow control */
8530 elink_ext_phy_set_pause(params, phy, vars);
8531 elink_cl45_write(sc, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV, 0x20);
8532 elink_cl45_write(sc, phy,
8533 MDIO_AN_DEVAD, MDIO_AN_REG_CL37_CL73, 0x040c);
8534 elink_cl45_write(sc, phy,
8535 MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LD, 0x0020);
8536 elink_cl45_write(sc, phy,
8537 MDIO_AN_DEVAD, MDIO_AN_REG_CL37_AN, 0x1000);
8538 elink_cl45_write(sc, phy,
8539 MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0x1200);
8540 /* Enable RX-ALARM control to receive interrupt for 1G speed
8543 elink_cl45_write(sc, phy,
8544 MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 0x4);
8545 elink_cl45_write(sc, phy,
8546 MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXCTRL, 0x400);
8548 } else { /* Default 10G. Set only LASI control */
8549 elink_cl45_write(sc, phy,
8550 MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 1);
8553 /* Set TX PreEmphasis if needed */
8554 if ((params->feature_config_flags &
8555 ELINK_FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED)) {
8556 PMD_DRV_LOG(DEBUG, sc,
8557 "Setting TX_CTRL1 0x%x, TX_CTRL2 0x%x",
8558 phy->tx_preemphasis[0], phy->tx_preemphasis[1]);
8559 elink_cl45_write(sc, phy,
8561 MDIO_PMA_REG_8726_TX_CTRL1,
8562 phy->tx_preemphasis[0]);
8564 elink_cl45_write(sc, phy,
8566 MDIO_PMA_REG_8726_TX_CTRL2,
8567 phy->tx_preemphasis[1]);
8570 return ELINK_STATUS_OK;
8574 static void elink_8726_link_reset(struct elink_phy *phy,
8575 struct elink_params *params)
8577 struct bnx2x_softc *sc = params->sc;
8578 PMD_DRV_LOG(DEBUG, sc, "elink_8726_link_reset port %d", params->port);
8579 /* Set serial boot control for external load */
8580 elink_cl45_write(sc, phy,
8581 MDIO_PMA_DEVAD, MDIO_PMA_REG_GEN_CTRL, 0x0001);
8584 /******************************************************************/
8585 /* BNX2X8727 PHY SECTION */
8586 /******************************************************************/
8588 static void elink_8727_set_link_led(struct elink_phy *phy,
8589 struct elink_params *params, uint8_t mode)
8591 struct bnx2x_softc *sc = params->sc;
8592 uint16_t led_mode_bitmask = 0;
8593 uint16_t gpio_pins_bitmask = 0;
8595 /* Only NOC flavor requires to set the LED specifically */
8596 if (!(phy->flags & ELINK_FLAGS_NOC))
8599 case ELINK_LED_MODE_FRONT_PANEL_OFF:
8600 case ELINK_LED_MODE_OFF:
8601 led_mode_bitmask = 0;
8602 gpio_pins_bitmask = 0x03;
8604 case ELINK_LED_MODE_ON:
8605 led_mode_bitmask = 0;
8606 gpio_pins_bitmask = 0x02;
8608 case ELINK_LED_MODE_OPER:
8609 led_mode_bitmask = 0x60;
8610 gpio_pins_bitmask = 0x11;
8613 elink_cl45_read(sc, phy,
8614 MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_PCS_OPT_CTRL, &val);
8616 val |= led_mode_bitmask;
8617 elink_cl45_write(sc, phy,
8618 MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_PCS_OPT_CTRL, val);
8619 elink_cl45_read(sc, phy,
8620 MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_GPIO_CTRL, &val);
8622 val |= gpio_pins_bitmask;
8623 elink_cl45_write(sc, phy,
8624 MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_GPIO_CTRL, val);
8627 static void elink_8727_hw_reset(__rte_unused struct elink_phy *phy,
8628 struct elink_params *params)
8630 uint32_t swap_val, swap_override;
8632 /* The PHY reset is controlled by GPIO 1. Fake the port number
8633 * to cancel the swap done in set_gpio()
8635 struct bnx2x_softc *sc = params->sc;
8636 swap_val = REG_RD(sc, NIG_REG_PORT_SWAP);
8637 swap_override = REG_RD(sc, NIG_REG_STRAP_OVERRIDE);
8638 port = (swap_val && swap_override) ^ 1;
8639 elink_cb_gpio_write(sc, MISC_REGISTERS_GPIO_1,
8640 MISC_REGISTERS_GPIO_OUTPUT_LOW, port);
8643 static void elink_8727_config_speed(struct elink_phy *phy,
8644 struct elink_params *params)
8646 struct bnx2x_softc *sc = params->sc;
8648 /* Set option 1G speed */
8649 if ((phy->req_line_speed == ELINK_SPEED_1000) ||
8650 (phy->media_type == ELINK_ETH_PHY_SFP_1G_FIBER)) {
8651 PMD_DRV_LOG(DEBUG, sc, "Setting 1G force");
8652 elink_cl45_write(sc, phy,
8653 MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x40);
8654 elink_cl45_write(sc, phy,
8655 MDIO_PMA_DEVAD, MDIO_PMA_REG_10G_CTRL2, 0xD);
8656 elink_cl45_read(sc, phy,
8657 MDIO_PMA_DEVAD, MDIO_PMA_REG_10G_CTRL2, &tmp1);
8658 PMD_DRV_LOG(DEBUG, sc, "1.7 = 0x%x", tmp1);
8659 /* Power down the XAUI until link is up in case of dual-media
8662 if (ELINK_DUAL_MEDIA(params)) {
8663 elink_cl45_read(sc, phy,
8665 MDIO_PMA_REG_8727_PCS_GP, &val);
8667 elink_cl45_write(sc, phy,
8669 MDIO_PMA_REG_8727_PCS_GP, val);
8671 } else if ((phy->req_line_speed == ELINK_SPEED_AUTO_NEG) &&
8672 ((phy->speed_cap_mask &
8673 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) &&
8674 ((phy->speed_cap_mask &
8675 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G) !=
8676 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) {
8678 PMD_DRV_LOG(DEBUG, sc, "Setting 1G clause37");
8679 elink_cl45_write(sc, phy,
8680 MDIO_AN_DEVAD, MDIO_AN_REG_8727_MISC_CTRL, 0);
8681 elink_cl45_write(sc, phy,
8682 MDIO_AN_DEVAD, MDIO_AN_REG_CL37_AN, 0x1300);
8684 /* Since the 8727 has only single reset pin, need to set the 10G
8685 * registers although it is default
8687 elink_cl45_write(sc, phy,
8688 MDIO_AN_DEVAD, MDIO_AN_REG_8727_MISC_CTRL,
8690 elink_cl45_write(sc, phy,
8691 MDIO_AN_DEVAD, MDIO_AN_REG_CL37_AN, 0x0100);
8692 elink_cl45_write(sc, phy,
8693 MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x2040);
8694 elink_cl45_write(sc, phy,
8695 MDIO_PMA_DEVAD, MDIO_PMA_REG_10G_CTRL2,
8700 static uint8_t elink_8727_config_init(struct elink_phy *phy,
8701 struct elink_params *params,
8702 __rte_unused struct elink_vars
8705 uint32_t tx_en_mode;
8706 uint16_t tmp1, mod_abs, tmp2;
8707 struct bnx2x_softc *sc = params->sc;
8708 /* Enable PMD link, MOD_ABS_FLT, and 1G link alarm */
8710 elink_wait_reset_complete(sc, phy, params);
8712 PMD_DRV_LOG(DEBUG, sc, "Initializing BNX2X8727");
8714 elink_8727_specific_func(phy, params, ELINK_PHY_INIT);
8715 /* Initially configure MOD_ABS to interrupt when module is
8718 elink_cl45_read(sc, phy,
8719 MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER, &mod_abs);
8720 /* Set EDC off by setting OPTXLOS signal input to low (bit 9).
8721 * When the EDC is off it locks onto a reference clock and avoids
8724 mod_abs &= ~(1 << 8);
8725 if (!(phy->flags & ELINK_FLAGS_NOC))
8726 mod_abs &= ~(1 << 9);
8727 elink_cl45_write(sc, phy,
8728 MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER, mod_abs);
8730 /* Enable/Disable PHY transmitter output */
8731 elink_set_disable_pmd_transmit(params, phy, 0);
8733 elink_8727_power_module(sc, phy, 1);
8735 elink_cl45_read(sc, phy,
8736 MDIO_PMA_DEVAD, MDIO_PMA_REG_M8051_MSGOUT_REG, &tmp1);
8738 elink_cl45_read(sc, phy, MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXSTAT, &tmp1);
8740 elink_8727_config_speed(phy, params);
8742 /* Set TX PreEmphasis if needed */
8743 if ((params->feature_config_flags &
8744 ELINK_FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED)) {
8745 PMD_DRV_LOG(DEBUG, sc, "Setting TX_CTRL1 0x%x, TX_CTRL2 0x%x",
8746 phy->tx_preemphasis[0], phy->tx_preemphasis[1]);
8747 elink_cl45_write(sc, phy,
8748 MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_TX_CTRL1,
8749 phy->tx_preemphasis[0]);
8751 elink_cl45_write(sc, phy,
8752 MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_TX_CTRL2,
8753 phy->tx_preemphasis[1]);
8756 /* If TX Laser is controlled by GPIO_0, do not let PHY go into low
8757 * power mode, if TX Laser is disabled
8759 tx_en_mode = REG_RD(sc, params->shmem_base +
8760 offsetof(struct shmem_region,
8761 dev_info.port_hw_config[params->port].
8763 & PORT_HW_CFG_TX_LASER_MASK;
8765 if (tx_en_mode == PORT_HW_CFG_TX_LASER_GPIO0) {
8767 PMD_DRV_LOG(DEBUG, sc, "Enabling TXONOFF_PWRDN_DIS");
8768 elink_cl45_read(sc, phy,
8769 MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_OPT_CFG_REG,
8773 elink_cl45_write(sc, phy,
8774 MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_OPT_CFG_REG,
8776 elink_cl45_read(sc, phy, MDIO_PMA_DEVAD,
8777 MDIO_PMA_REG_PHY_IDENTIFIER, &tmp2);
8778 elink_cl45_write(sc, phy, MDIO_PMA_DEVAD,
8779 MDIO_PMA_REG_PHY_IDENTIFIER, (tmp2 & 0x7fff));
8782 return ELINK_STATUS_OK;
8785 static void elink_8727_handle_mod_abs(struct elink_phy *phy,
8786 struct elink_params *params)
8788 struct bnx2x_softc *sc = params->sc;
8789 uint16_t mod_abs, rx_alarm_status;
8790 uint32_t val = REG_RD(sc, params->shmem_base +
8791 offsetof(struct shmem_region,
8792 dev_info.port_feature_config[params->
8794 elink_cl45_read(sc, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER,
8796 if (mod_abs & (1 << 8)) {
8798 /* Module is absent */
8799 PMD_DRV_LOG(DEBUG, sc, "MOD_ABS indication show module is absent");
8800 phy->media_type = ELINK_ETH_PHY_NOT_PRESENT;
8801 /* 1. Set mod_abs to detect next module
8803 * 2. Set EDC off by setting OPTXLOS signal input to low
8805 * When the EDC is off it locks onto a reference clock and
8806 * avoids becoming 'lost'.
8808 mod_abs &= ~(1 << 8);
8809 if (!(phy->flags & ELINK_FLAGS_NOC))
8810 mod_abs &= ~(1 << 9);
8811 elink_cl45_write(sc, phy,
8813 MDIO_PMA_REG_PHY_IDENTIFIER, mod_abs);
8815 /* Clear RX alarm since it stays up as long as
8816 * the mod_abs wasn't changed
8818 elink_cl45_read(sc, phy,
8820 MDIO_PMA_LASI_RXSTAT, &rx_alarm_status);
8823 /* Module is present */
8824 PMD_DRV_LOG(DEBUG, sc, "MOD_ABS indication show module is present");
8825 /* First disable transmitter, and if the module is ok, the
8826 * module_detection will enable it
8827 * 1. Set mod_abs to detect next module absent event ( bit 8)
8828 * 2. Restore the default polarity of the OPRXLOS signal and
8829 * this signal will then correctly indicate the presence or
8830 * absence of the Rx signal. (bit 9)
8832 mod_abs |= (1 << 8);
8833 if (!(phy->flags & ELINK_FLAGS_NOC))
8834 mod_abs |= (1 << 9);
8835 elink_cl45_write(sc, phy,
8837 MDIO_PMA_REG_PHY_IDENTIFIER, mod_abs);
8839 /* Clear RX alarm since it stays up as long as the mod_abs
8840 * wasn't changed. This is need to be done before calling the
8841 * module detection, otherwise it will clear* the link update
8844 elink_cl45_read(sc, phy,
8846 MDIO_PMA_LASI_RXSTAT, &rx_alarm_status);
8848 if ((val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) ==
8849 PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_DISABLE_TX_LASER)
8850 elink_sfp_set_transmitter(params, phy, 0);
8852 if (elink_wait_for_sfp_module_initialized(phy, params) == 0) {
8853 elink_sfp_module_detection(phy, params);
8855 PMD_DRV_LOG(DEBUG, sc, "SFP+ module is not initialized");
8858 /* Reconfigure link speed based on module type limitations */
8859 elink_8727_config_speed(phy, params);
8862 PMD_DRV_LOG(DEBUG, sc, "8727 RX_ALARM_STATUS 0x%x", rx_alarm_status);
8863 /* No need to check link status in case of module plugged in/out */
8866 static uint8_t elink_8727_read_status(struct elink_phy *phy,
8867 struct elink_params *params,
8868 struct elink_vars *vars)
8870 struct bnx2x_softc *sc = params->sc;
8871 uint8_t link_up = 0, oc_port = params->port;
8872 uint16_t link_status = 0;
8873 uint16_t rx_alarm_status, lasi_ctrl, val1;
8875 /* If PHY is not initialized, do not check link status */
8876 elink_cl45_read(sc, phy,
8877 MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, &lasi_ctrl);
8881 /* Check the LASI on Rx */
8882 elink_cl45_read(sc, phy,
8883 MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXSTAT, &rx_alarm_status);
8884 vars->line_speed = 0;
8885 PMD_DRV_LOG(DEBUG, sc, "8727 RX_ALARM_STATUS 0x%x", rx_alarm_status);
8887 elink_sfp_mask_fault(sc, phy, MDIO_PMA_LASI_TXSTAT,
8888 MDIO_PMA_LASI_TXCTRL);
8890 elink_cl45_read(sc, phy, MDIO_PMA_DEVAD, MDIO_PMA_LASI_STAT, &val1);
8892 PMD_DRV_LOG(DEBUG, sc, "8727 LASI status 0x%x", val1);
8895 elink_cl45_read(sc, phy,
8896 MDIO_PMA_DEVAD, MDIO_PMA_REG_M8051_MSGOUT_REG, &val1);
8898 /* If a module is present and there is need to check
8901 if (!(phy->flags & ELINK_FLAGS_NOC) && !(rx_alarm_status & (1 << 5))) {
8902 /* Check over-current using 8727 GPIO0 input */
8903 elink_cl45_read(sc, phy,
8904 MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_GPIO_CTRL,
8907 if ((val1 & (1 << 8)) == 0) {
8908 if (!CHIP_IS_E1x(sc))
8909 oc_port = SC_PATH(sc) + (params->port << 1);
8910 PMD_DRV_LOG(DEBUG, sc,
8911 "8727 Power fault has been detected on port %d",
8913 elink_cb_event_log(sc, ELINK_LOG_ID_OVER_CURRENT, oc_port); //"Error: Power fault on Port %d has "
8914 // "been detected and the power to "
8915 // "that SFP+ module has been removed "
8916 // "to prevent failure of the card. "
8917 // "Please remove the SFP+ module and "
8918 // "restart the system to clear this "
8920 /* Disable all RX_ALARMs except for mod_abs */
8921 elink_cl45_write(sc, phy,
8923 MDIO_PMA_LASI_RXCTRL, (1 << 5));
8925 elink_cl45_read(sc, phy,
8927 MDIO_PMA_REG_PHY_IDENTIFIER, &val1);
8928 /* Wait for module_absent_event */
8930 elink_cl45_write(sc, phy,
8932 MDIO_PMA_REG_PHY_IDENTIFIER, val1);
8933 /* Clear RX alarm */
8934 elink_cl45_read(sc, phy,
8936 MDIO_PMA_LASI_RXSTAT, &rx_alarm_status);
8937 elink_8727_power_module(params->sc, phy, 0);
8942 /* Over current check */
8943 /* When module absent bit is set, check module */
8944 if (rx_alarm_status & (1 << 5)) {
8945 elink_8727_handle_mod_abs(phy, params);
8946 /* Enable all mod_abs and link detection bits */
8947 elink_cl45_write(sc, phy,
8948 MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXCTRL,
8949 ((1 << 5) | (1 << 2)));
8952 if (!(phy->flags & ELINK_FLAGS_SFP_NOT_APPROVED)) {
8953 PMD_DRV_LOG(DEBUG, sc, "Enabling 8727 TX laser");
8954 elink_sfp_set_transmitter(params, phy, 1);
8956 PMD_DRV_LOG(DEBUG, sc, "Tx is disabled");
8960 elink_cl45_read(sc, phy,
8962 MDIO_PMA_REG_8073_SPEED_LINK_STATUS, &link_status);
8964 /* Bits 0..2 --> speed detected,
8965 * Bits 13..15--> link is down
8967 if ((link_status & (1 << 2)) && (!(link_status & (1 << 15)))) {
8969 vars->line_speed = ELINK_SPEED_10000;
8970 PMD_DRV_LOG(DEBUG, sc, "port %x: External link up in 10G",
8972 } else if ((link_status & (1 << 0)) && (!(link_status & (1 << 13)))) {
8974 vars->line_speed = ELINK_SPEED_1000;
8975 PMD_DRV_LOG(DEBUG, sc, "port %x: External link up in 1G",
8979 PMD_DRV_LOG(DEBUG, sc, "port %x: External link is down",
8983 /* Capture 10G link fault. */
8984 if (vars->line_speed == ELINK_SPEED_10000) {
8985 elink_cl45_read(sc, phy, MDIO_PMA_DEVAD,
8986 MDIO_PMA_LASI_TXSTAT, &val1);
8988 elink_cl45_read(sc, phy, MDIO_PMA_DEVAD,
8989 MDIO_PMA_LASI_TXSTAT, &val1);
8991 if (val1 & (1 << 0)) {
8992 vars->fault_detected = 1;
8997 elink_ext_phy_resolve_fc(phy, params, vars);
8998 vars->duplex = DUPLEX_FULL;
8999 PMD_DRV_LOG(DEBUG, sc, "duplex = 0x%x", vars->duplex);
9002 if ((ELINK_DUAL_MEDIA(params)) &&
9003 (phy->req_line_speed == ELINK_SPEED_1000)) {
9004 elink_cl45_read(sc, phy,
9006 MDIO_PMA_REG_8727_PCS_GP, &val1);
9007 /* In case of dual-media board and 1G, power up the XAUI side,
9008 * otherwise power it down. For 10G it is done automatically
9014 elink_cl45_write(sc, phy,
9016 MDIO_PMA_REG_8727_PCS_GP, val1);
9021 static void elink_8727_link_reset(struct elink_phy *phy,
9022 struct elink_params *params)
9024 struct bnx2x_softc *sc = params->sc;
9026 /* Enable/Disable PHY transmitter output */
9027 elink_set_disable_pmd_transmit(params, phy, 1);
9029 /* Disable Transmitter */
9030 elink_sfp_set_transmitter(params, phy, 0);
9032 elink_cl45_write(sc, phy, MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 0);
9036 /******************************************************************/
9037 /* BNX2X8481/BNX2X84823/BNX2X84833 PHY SECTION */
9038 /******************************************************************/
9039 static void elink_save_848xx_spirom_version(struct elink_phy *phy,
9040 struct bnx2x_softc *sc, uint8_t port)
9042 uint16_t val, fw_ver2, cnt, i;
9043 static struct elink_reg_set reg_set[] = {
9044 {MDIO_PMA_DEVAD, 0xA819, 0x0014},
9045 {MDIO_PMA_DEVAD, 0xA81A, 0xc200},
9046 {MDIO_PMA_DEVAD, 0xA81B, 0x0000},
9047 {MDIO_PMA_DEVAD, 0xA81C, 0x0300},
9048 {MDIO_PMA_DEVAD, 0xA817, 0x0009}
9052 if ((phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84833) ||
9053 (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84834)) {
9054 elink_cl45_read(sc, phy, MDIO_CTL_DEVAD, 0x400f, &fw_ver1);
9055 elink_save_spirom_version(sc, port, fw_ver1 & 0xfff,
9058 /* For 32-bit registers in 848xx, access via MDIO2ARM i/f. */
9059 /* (1) set reg 0xc200_0014(SPI_BRIDGE_CTRL_2) to 0x03000000 */
9060 for (i = 0; i < ARRAY_SIZE(reg_set); i++)
9061 elink_cl45_write(sc, phy, reg_set[i].devad,
9062 reg_set[i].reg, reg_set[i].val);
9064 for (cnt = 0; cnt < 100; cnt++) {
9065 elink_cl45_read(sc, phy, MDIO_PMA_DEVAD, 0xA818, &val);
9071 PMD_DRV_LOG(DEBUG, sc, "Unable to read 848xx "
9072 "phy fw version(1)");
9073 elink_save_spirom_version(sc, port, 0, phy->ver_addr);
9077 /* 2) read register 0xc200_0000 (SPI_FW_STATUS) */
9078 elink_cl45_write(sc, phy, MDIO_PMA_DEVAD, 0xA819, 0x0000);
9079 elink_cl45_write(sc, phy, MDIO_PMA_DEVAD, 0xA81A, 0xc200);
9080 elink_cl45_write(sc, phy, MDIO_PMA_DEVAD, 0xA817, 0x000A);
9081 for (cnt = 0; cnt < 100; cnt++) {
9082 elink_cl45_read(sc, phy, MDIO_PMA_DEVAD, 0xA818, &val);
9088 PMD_DRV_LOG(DEBUG, sc, "Unable to read 848xx phy fw "
9090 elink_save_spirom_version(sc, port, 0, phy->ver_addr);
9094 /* lower 16 bits of the register SPI_FW_STATUS */
9095 elink_cl45_read(sc, phy, MDIO_PMA_DEVAD, 0xA81B, &fw_ver1);
9096 /* upper 16 bits of register SPI_FW_STATUS */
9097 elink_cl45_read(sc, phy, MDIO_PMA_DEVAD, 0xA81C, &fw_ver2);
9099 elink_save_spirom_version(sc, port, (fw_ver2 << 16) | fw_ver1,
9105 static void elink_848xx_set_led(struct bnx2x_softc *sc, struct elink_phy *phy)
9107 uint16_t val, offset, i;
9108 static struct elink_reg_set reg_set[] = {
9109 {MDIO_PMA_DEVAD, MDIO_PMA_REG_8481_LED1_MASK, 0x0080},
9110 {MDIO_PMA_DEVAD, MDIO_PMA_REG_8481_LED2_MASK, 0x0018},
9111 {MDIO_PMA_DEVAD, MDIO_PMA_REG_8481_LED3_MASK, 0x0006},
9112 {MDIO_PMA_DEVAD, MDIO_PMA_REG_8481_LED3_BLINK, 0x0000},
9113 {MDIO_PMA_DEVAD, MDIO_PMA_REG_84823_CTL_SLOW_CLK_CNT_HIGH,
9114 MDIO_PMA_REG_84823_BLINK_RATE_VAL_15P9HZ},
9115 {MDIO_AN_DEVAD, 0xFFFB, 0xFFFD}
9117 /* PHYC_CTL_LED_CTL */
9118 elink_cl45_read(sc, phy,
9119 MDIO_PMA_DEVAD, MDIO_PMA_REG_8481_LINK_SIGNAL, &val);
9123 elink_cl45_write(sc, phy,
9124 MDIO_PMA_DEVAD, MDIO_PMA_REG_8481_LINK_SIGNAL, val);
9126 for (i = 0; i < ARRAY_SIZE(reg_set); i++)
9127 elink_cl45_write(sc, phy, reg_set[i].devad, reg_set[i].reg,
9130 if ((phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84833) ||
9131 (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84834))
9132 offset = MDIO_PMA_REG_84833_CTL_LED_CTL_1;
9134 offset = MDIO_PMA_REG_84823_CTL_LED_CTL_1;
9136 /* stretch_en for LED3 */
9137 elink_cl45_read_or_write(sc, phy,
9138 MDIO_PMA_DEVAD, offset,
9139 MDIO_PMA_REG_84823_LED3_STRETCH_EN);
9142 static void elink_848xx_specific_func(struct elink_phy *phy,
9143 struct elink_params *params,
9146 struct bnx2x_softc *sc = params->sc;
9148 case ELINK_PHY_INIT:
9149 if ((phy->type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84833) &&
9150 (phy->type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84834)) {
9151 /* Save spirom version */
9152 elink_save_848xx_spirom_version(phy, sc, params->port);
9154 /* This phy uses the NIG latch mechanism since link indication
9155 * arrives through its LED4 and not via its LASI signal, so we
9156 * get steady signal instead of clear on read
9158 elink_bits_en(sc, NIG_REG_LATCH_BC_0 + params->port * 4,
9159 1 << ELINK_NIG_LATCH_BC_ENABLE_MI_INT);
9161 elink_848xx_set_led(sc, phy);
9166 static elink_status_t elink_848xx_cmn_config_init(struct elink_phy *phy,
9167 struct elink_params *params,
9168 struct elink_vars *vars)
9170 struct bnx2x_softc *sc = params->sc;
9171 uint16_t autoneg_val, an_1000_val, an_10_100_val;
9173 elink_848xx_specific_func(phy, params, ELINK_PHY_INIT);
9174 elink_cl45_write(sc, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x0000);
9176 /* set 1000 speed advertisement */
9177 elink_cl45_read(sc, phy,
9178 MDIO_AN_DEVAD, MDIO_AN_REG_8481_1000T_CTRL,
9181 elink_ext_phy_set_pause(params, phy, vars);
9182 elink_cl45_read(sc, phy,
9184 MDIO_AN_REG_8481_LEGACY_AN_ADV, &an_10_100_val);
9185 elink_cl45_read(sc, phy,
9186 MDIO_AN_DEVAD, MDIO_AN_REG_8481_LEGACY_MII_CTRL,
9188 /* Disable forced speed */
9190 ~((1 << 6) | (1 << 8) | (1 << 9) | (1 << 12) | (1 << 13));
9191 an_10_100_val &= ~((1 << 5) | (1 << 6) | (1 << 7) | (1 << 8));
9193 if (((phy->req_line_speed == ELINK_SPEED_AUTO_NEG) &&
9194 (phy->speed_cap_mask &
9195 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) ||
9196 (phy->req_line_speed == ELINK_SPEED_1000)) {
9197 an_1000_val |= (1 << 8);
9198 autoneg_val |= (1 << 9 | 1 << 12);
9199 if (phy->req_duplex == DUPLEX_FULL)
9200 an_1000_val |= (1 << 9);
9201 PMD_DRV_LOG(DEBUG, sc, "Advertising 1G");
9203 an_1000_val &= ~((1 << 8) | (1 << 9));
9205 elink_cl45_write(sc, phy,
9206 MDIO_AN_DEVAD, MDIO_AN_REG_8481_1000T_CTRL,
9209 /* Set 10/100 speed advertisement */
9210 if (phy->req_line_speed == ELINK_SPEED_AUTO_NEG) {
9211 if (phy->speed_cap_mask &
9212 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL) {
9213 /* Enable autoneg and restart autoneg for legacy speeds
9215 autoneg_val |= (1 << 9 | 1 << 12);
9216 an_10_100_val |= (1 << 8);
9217 PMD_DRV_LOG(DEBUG, sc, "Advertising 100M-FD");
9220 if (phy->speed_cap_mask &
9221 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF) {
9222 /* Enable autoneg and restart autoneg for legacy speeds
9224 autoneg_val |= (1 << 9 | 1 << 12);
9225 an_10_100_val |= (1 << 7);
9226 PMD_DRV_LOG(DEBUG, sc, "Advertising 100M-HD");
9229 if ((phy->speed_cap_mask &
9230 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL) &&
9231 (phy->supported & ELINK_SUPPORTED_10baseT_Full)) {
9232 an_10_100_val |= (1 << 6);
9233 autoneg_val |= (1 << 9 | 1 << 12);
9234 PMD_DRV_LOG(DEBUG, sc, "Advertising 10M-FD");
9237 if ((phy->speed_cap_mask &
9238 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF) &&
9239 (phy->supported & ELINK_SUPPORTED_10baseT_Half)) {
9240 an_10_100_val |= (1 << 5);
9241 autoneg_val |= (1 << 9 | 1 << 12);
9242 PMD_DRV_LOG(DEBUG, sc, "Advertising 10M-HD");
9246 /* Only 10/100 are allowed to work in FORCE mode */
9247 if ((phy->req_line_speed == ELINK_SPEED_100) &&
9249 (ELINK_SUPPORTED_100baseT_Half | ELINK_SUPPORTED_100baseT_Full))) {
9250 autoneg_val |= (1 << 13);
9251 /* Enabled AUTO-MDIX when autoneg is disabled */
9252 elink_cl45_write(sc, phy,
9253 MDIO_AN_DEVAD, MDIO_AN_REG_8481_AUX_CTRL,
9254 (1 << 15 | 1 << 9 | 7 << 0));
9255 /* The PHY needs this set even for forced link. */
9256 an_10_100_val |= (1 << 8) | (1 << 7);
9257 PMD_DRV_LOG(DEBUG, sc, "Setting 100M force");
9259 if ((phy->req_line_speed == ELINK_SPEED_10) &&
9261 (ELINK_SUPPORTED_10baseT_Half | ELINK_SUPPORTED_10baseT_Full))) {
9262 /* Enabled AUTO-MDIX when autoneg is disabled */
9263 elink_cl45_write(sc, phy,
9264 MDIO_AN_DEVAD, MDIO_AN_REG_8481_AUX_CTRL,
9265 (1 << 15 | 1 << 9 | 7 << 0));
9266 PMD_DRV_LOG(DEBUG, sc, "Setting 10M force");
9269 elink_cl45_write(sc, phy,
9270 MDIO_AN_DEVAD, MDIO_AN_REG_8481_LEGACY_AN_ADV,
9273 if (phy->req_duplex == DUPLEX_FULL)
9274 autoneg_val |= (1 << 8);
9276 /* Always write this if this is not 84833/4.
9277 * For 84833/4, write it only when it's a forced speed.
9279 if (((phy->type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84833) &&
9280 (phy->type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84834)) ||
9281 ((autoneg_val & (1 << 12)) == 0))
9282 elink_cl45_write(sc, phy,
9284 MDIO_AN_REG_8481_LEGACY_MII_CTRL, autoneg_val);
9286 if (((phy->req_line_speed == ELINK_SPEED_AUTO_NEG) &&
9287 (phy->speed_cap_mask &
9288 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) ||
9289 (phy->req_line_speed == ELINK_SPEED_10000)) {
9290 PMD_DRV_LOG(DEBUG, sc, "Advertising 10G");
9291 /* Restart autoneg for 10G */
9293 elink_cl45_read_or_write(sc, phy,
9295 MDIO_AN_REG_8481_10GBASE_T_AN_CTRL,
9297 elink_cl45_write(sc, phy,
9298 MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0x3200);
9300 elink_cl45_write(sc, phy,
9302 MDIO_AN_REG_8481_10GBASE_T_AN_CTRL, 1);
9304 return ELINK_STATUS_OK;
9307 static uint8_t elink_8481_config_init(struct elink_phy *phy,
9308 struct elink_params *params,
9309 struct elink_vars *vars)
9311 struct bnx2x_softc *sc = params->sc;
9312 /* Restore normal power mode */
9313 elink_cb_gpio_write(sc, MISC_REGISTERS_GPIO_2,
9314 MISC_REGISTERS_GPIO_OUTPUT_HIGH, params->port);
9317 elink_ext_phy_hw_reset(sc, params->port);
9318 elink_wait_reset_complete(sc, phy, params);
9320 elink_cl45_write(sc, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 1 << 15);
9321 return elink_848xx_cmn_config_init(phy, params, vars);
9324 #define PHY84833_CMDHDLR_WAIT 300
9325 #define PHY84833_CMDHDLR_MAX_ARGS 5
9326 static elink_status_t elink_84833_cmd_hdlr(struct elink_phy *phy,
9327 struct elink_params *params,
9328 uint16_t fw_cmd, uint16_t cmd_args[],
9333 struct bnx2x_softc *sc = params->sc;
9334 /* Write CMD_OPEN_OVERRIDE to STATUS reg */
9335 elink_cl45_write(sc, phy, MDIO_CTL_DEVAD,
9336 MDIO_84833_CMD_HDLR_STATUS,
9337 PHY84833_STATUS_CMD_OPEN_OVERRIDE);
9338 for (idx = 0; idx < PHY84833_CMDHDLR_WAIT; idx++) {
9339 elink_cl45_read(sc, phy, MDIO_CTL_DEVAD,
9340 MDIO_84833_CMD_HDLR_STATUS, &val);
9341 if (val == PHY84833_STATUS_CMD_OPEN_FOR_CMDS)
9345 if (idx >= PHY84833_CMDHDLR_WAIT) {
9346 PMD_DRV_LOG(DEBUG, sc, "FW cmd: FW not ready.");
9347 return ELINK_STATUS_ERROR;
9350 /* Prepare argument(s) and issue command */
9351 for (idx = 0; idx < argc; idx++) {
9352 elink_cl45_write(sc, phy, MDIO_CTL_DEVAD,
9353 MDIO_84833_CMD_HDLR_DATA1 + idx,
9356 elink_cl45_write(sc, phy, MDIO_CTL_DEVAD,
9357 MDIO_84833_CMD_HDLR_COMMAND, fw_cmd);
9358 for (idx = 0; idx < PHY84833_CMDHDLR_WAIT; idx++) {
9359 elink_cl45_read(sc, phy, MDIO_CTL_DEVAD,
9360 MDIO_84833_CMD_HDLR_STATUS, &val);
9361 if ((val == PHY84833_STATUS_CMD_COMPLETE_PASS) ||
9362 (val == PHY84833_STATUS_CMD_COMPLETE_ERROR))
9366 if ((idx >= PHY84833_CMDHDLR_WAIT) ||
9367 (val == PHY84833_STATUS_CMD_COMPLETE_ERROR)) {
9368 PMD_DRV_LOG(DEBUG, sc, "FW cmd failed.");
9369 return ELINK_STATUS_ERROR;
9371 /* Gather returning data */
9372 for (idx = 0; idx < argc; idx++) {
9373 elink_cl45_read(sc, phy, MDIO_CTL_DEVAD,
9374 MDIO_84833_CMD_HDLR_DATA1 + idx,
9377 elink_cl45_write(sc, phy, MDIO_CTL_DEVAD,
9378 MDIO_84833_CMD_HDLR_STATUS,
9379 PHY84833_STATUS_CMD_CLEAR_COMPLETE);
9380 return ELINK_STATUS_OK;
9383 static elink_status_t elink_84833_pair_swap_cfg(struct elink_phy *phy,
9384 struct elink_params *params,
9385 __rte_unused struct elink_vars
9389 uint16_t data[PHY84833_CMDHDLR_MAX_ARGS];
9390 elink_status_t status;
9391 struct bnx2x_softc *sc = params->sc;
9393 /* Check for configuration. */
9394 pair_swap = REG_RD(sc, params->shmem_base +
9395 offsetof(struct shmem_region,
9396 dev_info.port_hw_config[params->port].
9398 PORT_HW_CFG_RJ45_PAIR_SWAP_MASK;
9401 return ELINK_STATUS_OK;
9403 /* Only the second argument is used for this command */
9404 data[1] = (uint16_t) pair_swap;
9406 status = elink_84833_cmd_hdlr(phy, params,
9407 PHY84833_CMD_SET_PAIR_SWAP, data,
9408 PHY84833_CMDHDLR_MAX_ARGS);
9409 if (status == ELINK_STATUS_OK) {
9410 PMD_DRV_LOG(DEBUG, sc, "Pairswap OK, val=0x%x", data[1]);
9416 static uint8_t elink_84833_get_reset_gpios(struct bnx2x_softc *sc,
9417 uint32_t shmem_base_path[],
9418 __rte_unused uint32_t chip_id)
9420 uint32_t reset_pin[2];
9422 uint8_t reset_gpios;
9423 if (CHIP_IS_E3(sc)) {
9424 /* Assume that these will be GPIOs, not EPIOs. */
9425 for (idx = 0; idx < 2; idx++) {
9426 /* Map config param to register bit. */
9427 reset_pin[idx] = REG_RD(sc, shmem_base_path[idx] +
9428 offsetof(struct shmem_region,
9433 (reset_pin[idx] & PORT_HW_CFG_E3_PHY_RESET_MASK) >>
9434 PORT_HW_CFG_E3_PHY_RESET_SHIFT;
9435 reset_pin[idx] -= PIN_CFG_GPIO0_P0;
9436 reset_pin[idx] = (1 << reset_pin[idx]);
9438 reset_gpios = (uint8_t) (reset_pin[0] | reset_pin[1]);
9440 /* E2, look from diff place of shmem. */
9441 for (idx = 0; idx < 2; idx++) {
9442 reset_pin[idx] = REG_RD(sc, shmem_base_path[idx] +
9443 offsetof(struct shmem_region,
9447 reset_pin[idx] &= PORT_HW_CFG_EXT_PHY_GPIO_RST_MASK;
9448 reset_pin[idx] -= PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO0_P0;
9449 reset_pin[idx] >>= PORT_HW_CFG_EXT_PHY_GPIO_RST_SHIFT;
9450 reset_pin[idx] = (1 << reset_pin[idx]);
9452 reset_gpios = (uint8_t) (reset_pin[0] | reset_pin[1]);
9458 static void elink_84833_hw_reset_phy(struct elink_phy *phy,
9459 struct elink_params *params)
9461 struct bnx2x_softc *sc = params->sc;
9462 uint8_t reset_gpios;
9463 uint32_t other_shmem_base_addr = REG_RD(sc, params->shmem2_base +
9464 offsetof(struct shmem2_region,
9465 other_shmem_base_addr));
9467 uint32_t shmem_base_path[2];
9469 /* Work around for 84833 LED failure inside RESET status */
9470 elink_cl45_write(sc, phy, MDIO_AN_DEVAD,
9471 MDIO_AN_REG_8481_LEGACY_MII_CTRL,
9472 MDIO_AN_REG_8481_MII_CTRL_FORCE_1G);
9473 elink_cl45_write(sc, phy, MDIO_AN_DEVAD,
9474 MDIO_AN_REG_8481_1G_100T_EXT_CTRL,
9475 MIDO_AN_REG_8481_EXT_CTRL_FORCE_LEDS_OFF);
9477 shmem_base_path[0] = params->shmem_base;
9478 shmem_base_path[1] = other_shmem_base_addr;
9480 reset_gpios = elink_84833_get_reset_gpios(sc, shmem_base_path,
9483 elink_cb_gpio_mult_write(sc, reset_gpios,
9484 MISC_REGISTERS_GPIO_OUTPUT_LOW);
9486 PMD_DRV_LOG(DEBUG, sc,
9487 "84833 hw reset on pin values 0x%x", reset_gpios);
9490 static elink_status_t elink_8483x_disable_eee(struct elink_phy *phy,
9491 struct elink_params *params,
9492 struct elink_vars *vars)
9495 uint16_t cmd_args = 0;
9497 PMD_DRV_LOG(DEBUG, params->sc, "Don't Advertise 10GBase-T EEE");
9499 /* Prevent Phy from working in EEE and advertising it */
9500 rc = elink_84833_cmd_hdlr(phy, params,
9501 PHY84833_CMD_SET_EEE_MODE, &cmd_args, 1);
9502 if (rc != ELINK_STATUS_OK) {
9503 PMD_DRV_LOG(DEBUG, params->sc, "EEE disable failed.");
9507 return elink_eee_disable(phy, params, vars);
9510 static elink_status_t elink_8483x_enable_eee(struct elink_phy *phy,
9511 struct elink_params *params,
9512 struct elink_vars *vars)
9515 uint16_t cmd_args = 1;
9517 rc = elink_84833_cmd_hdlr(phy, params,
9518 PHY84833_CMD_SET_EEE_MODE, &cmd_args, 1);
9519 if (rc != ELINK_STATUS_OK) {
9520 PMD_DRV_LOG(DEBUG, params->sc, "EEE enable failed.");
9524 return elink_eee_advertise(phy, params, vars, SHMEM_EEE_10G_ADV);
9527 #define PHY84833_CONSTANT_LATENCY 1193
9528 static uint8_t elink_848x3_config_init(struct elink_phy *phy,
9529 struct elink_params *params,
9530 struct elink_vars *vars)
9532 struct bnx2x_softc *sc = params->sc;
9533 uint8_t port, initialize = 1;
9535 uint32_t actual_phy_selection;
9536 uint16_t cmd_args[PHY84833_CMDHDLR_MAX_ARGS];
9537 elink_status_t rc = ELINK_STATUS_OK;
9541 if (!(CHIP_IS_E1x(sc)))
9544 port = params->port;
9546 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84823) {
9547 elink_cb_gpio_write(sc, MISC_REGISTERS_GPIO_3,
9548 MISC_REGISTERS_GPIO_OUTPUT_HIGH, port);
9551 elink_cl45_write(sc, phy,
9552 MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x8000);
9555 elink_wait_reset_complete(sc, phy, params);
9557 /* Wait for GPHY to come out of reset */
9559 if ((phy->type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84833) &&
9560 (phy->type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84834)) {
9561 /* BNX2X84823 requires that XGXS links up first @ 10G for normal
9565 temp = vars->line_speed;
9566 vars->line_speed = ELINK_SPEED_10000;
9567 elink_set_autoneg(¶ms->phy[ELINK_INT_PHY], params, vars, 0);
9568 elink_program_serdes(¶ms->phy[ELINK_INT_PHY], params, vars);
9569 vars->line_speed = temp;
9572 elink_cl45_read(sc, phy, MDIO_CTL_DEVAD,
9573 MDIO_CTL_REG_84823_MEDIA, &val);
9574 val &= ~(MDIO_CTL_REG_84823_MEDIA_MAC_MASK |
9575 MDIO_CTL_REG_84823_MEDIA_LINE_MASK |
9576 MDIO_CTL_REG_84823_MEDIA_COPPER_CORE_DOWN |
9577 MDIO_CTL_REG_84823_MEDIA_PRIORITY_MASK |
9578 MDIO_CTL_REG_84823_MEDIA_FIBER_1G);
9580 if (CHIP_IS_E3(sc)) {
9581 val &= ~(MDIO_CTL_REG_84823_MEDIA_MAC_MASK |
9582 MDIO_CTL_REG_84823_MEDIA_LINE_MASK);
9584 val |= (MDIO_CTL_REG_84823_CTRL_MAC_XFI |
9585 MDIO_CTL_REG_84823_MEDIA_LINE_XAUI_L);
9588 actual_phy_selection = elink_phy_selection(params);
9590 switch (actual_phy_selection) {
9591 case PORT_HW_CFG_PHY_SELECTION_HARDWARE_DEFAULT:
9592 /* Do nothing. Essentially this is like the priority copper */
9594 case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY_PRIORITY:
9595 val |= MDIO_CTL_REG_84823_MEDIA_PRIORITY_COPPER;
9597 case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY_PRIORITY:
9598 val |= MDIO_CTL_REG_84823_MEDIA_PRIORITY_FIBER;
9600 case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY:
9601 /* Do nothing here. The first PHY won't be initialized at all */
9603 case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY:
9604 val |= MDIO_CTL_REG_84823_MEDIA_COPPER_CORE_DOWN;
9608 if (params->phy[ELINK_EXT_PHY2].req_line_speed == ELINK_SPEED_1000)
9609 val |= MDIO_CTL_REG_84823_MEDIA_FIBER_1G;
9611 elink_cl45_write(sc, phy, MDIO_CTL_DEVAD,
9612 MDIO_CTL_REG_84823_MEDIA, val);
9613 PMD_DRV_LOG(DEBUG, sc, "Multi_phy config = 0x%x, Media control = 0x%x",
9614 params->multi_phy_config, val);
9616 if ((phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84833) ||
9617 (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84834)) {
9618 elink_84833_pair_swap_cfg(phy, params, vars);
9620 /* Keep AutogrEEEn disabled. */
9623 cmd_args[2] = PHY84833_CONSTANT_LATENCY + 1;
9624 cmd_args[3] = PHY84833_CONSTANT_LATENCY;
9625 rc = elink_84833_cmd_hdlr(phy, params,
9626 PHY84833_CMD_SET_EEE_MODE, cmd_args,
9627 PHY84833_CMDHDLR_MAX_ARGS);
9628 if (rc != ELINK_STATUS_OK) {
9629 PMD_DRV_LOG(DEBUG, sc, "Cfg AutogrEEEn failed.");
9633 rc = elink_848xx_cmn_config_init(phy, params, vars);
9635 elink_save_848xx_spirom_version(phy, sc, params->port);
9637 /* 84833 PHY has a better feature and doesn't need to support this. */
9638 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84823) {
9639 uint32_t cms_enable = REG_RD(sc, params->shmem_base +
9640 offsetof(struct shmem_region,
9642 port_hw_config[params->
9645 PORT_HW_CFG_ENABLE_CMS_MASK;
9647 elink_cl45_read(sc, phy, MDIO_CTL_DEVAD,
9648 MDIO_CTL_REG_84823_USER_CTRL_REG, &val);
9650 val |= MDIO_CTL_REG_84823_USER_CTRL_CMS;
9652 val &= ~MDIO_CTL_REG_84823_USER_CTRL_CMS;
9653 elink_cl45_write(sc, phy, MDIO_CTL_DEVAD,
9654 MDIO_CTL_REG_84823_USER_CTRL_REG, val);
9657 elink_cl45_read(sc, phy, MDIO_CTL_DEVAD,
9658 MDIO_84833_TOP_CFG_FW_REV, &val);
9660 /* Configure EEE support */
9661 if ((val >= MDIO_84833_TOP_CFG_FW_EEE) &&
9662 (val != MDIO_84833_TOP_CFG_FW_NO_EEE) &&
9663 elink_eee_has_cap(params)) {
9664 rc = elink_eee_initial_config(params, vars, SHMEM_EEE_10G_ADV);
9665 if (rc != ELINK_STATUS_OK) {
9666 PMD_DRV_LOG(DEBUG, sc, "Failed to configure EEE timers");
9667 elink_8483x_disable_eee(phy, params, vars);
9671 if ((phy->req_duplex == DUPLEX_FULL) &&
9672 (params->eee_mode & ELINK_EEE_MODE_ADV_LPI) &&
9673 (elink_eee_calc_timer(params) ||
9674 !(params->eee_mode & ELINK_EEE_MODE_ENABLE_LPI)))
9675 rc = elink_8483x_enable_eee(phy, params, vars);
9677 rc = elink_8483x_disable_eee(phy, params, vars);
9678 if (rc != ELINK_STATUS_OK) {
9679 PMD_DRV_LOG(DEBUG, sc, "Failed to set EEE advertisement");
9683 vars->eee_status &= ~SHMEM_EEE_SUPPORTED_MASK;
9686 if ((phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84833) ||
9687 (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84834)) {
9688 /* Bring PHY out of super isolate mode as the final step. */
9689 elink_cl45_read_and_write(sc, phy,
9691 MDIO_84833_TOP_CFG_XGPHY_STRAP1,
9693 MDIO_84833_SUPER_ISOLATE);
9698 static uint8_t elink_848xx_read_status(struct elink_phy *phy,
9699 struct elink_params *params,
9700 struct elink_vars *vars)
9702 struct bnx2x_softc *sc = params->sc;
9703 uint16_t val, val1, val2;
9704 uint8_t link_up = 0;
9706 /* Check 10G-BaseT link status */
9707 /* Check PMD signal ok */
9708 elink_cl45_read(sc, phy, MDIO_AN_DEVAD, 0xFFFA, &val1);
9709 elink_cl45_read(sc, phy,
9710 MDIO_PMA_DEVAD, MDIO_PMA_REG_8481_PMD_SIGNAL, &val2);
9711 PMD_DRV_LOG(DEBUG, sc, "BNX2X848xx: PMD_SIGNAL 1.a811 = 0x%x", val2);
9713 /* Check link 10G */
9714 if (val2 & (1 << 11)) {
9715 vars->line_speed = ELINK_SPEED_10000;
9716 vars->duplex = DUPLEX_FULL;
9718 elink_ext_phy_10G_an_resolve(sc, phy, vars);
9719 } else { /* Check Legacy speed link */
9720 uint16_t legacy_status, legacy_speed, mii_ctrl;
9722 /* Enable expansion register 0x42 (Operation mode status) */
9723 elink_cl45_write(sc, phy,
9725 MDIO_AN_REG_8481_EXPANSION_REG_ACCESS, 0xf42);
9727 /* Get legacy speed operation status */
9728 elink_cl45_read(sc, phy,
9730 MDIO_AN_REG_8481_EXPANSION_REG_RD_RW,
9733 PMD_DRV_LOG(DEBUG, sc,
9734 "Legacy speed status = 0x%x", legacy_status);
9735 link_up = ((legacy_status & (1 << 11)) == (1 << 11));
9736 legacy_speed = (legacy_status & (3 << 9));
9737 if (legacy_speed == (0 << 9))
9738 vars->line_speed = ELINK_SPEED_10;
9739 else if (legacy_speed == (1 << 9))
9740 vars->line_speed = ELINK_SPEED_100;
9741 else if (legacy_speed == (2 << 9))
9742 vars->line_speed = ELINK_SPEED_1000;
9743 else { /* Should not happen: Treat as link down */
9744 vars->line_speed = 0;
9748 if (params->feature_config_flags &
9749 ELINK_FEATURE_CONFIG_IEEE_PHY_TEST) {
9750 elink_cl45_read(sc, phy,
9752 MDIO_AN_REG_8481_LEGACY_MII_CTRL,
9754 /* For IEEE testing, check for a fake link. */
9755 link_up |= ((mii_ctrl & 0x3040) == 0x40);
9759 if (legacy_status & (1 << 8))
9760 vars->duplex = DUPLEX_FULL;
9762 vars->duplex = DUPLEX_HALF;
9764 PMD_DRV_LOG(DEBUG, sc,
9765 "Link is up in %dMbps, is_duplex_full= %d",
9767 (vars->duplex == DUPLEX_FULL));
9768 /* Check legacy speed AN resolution */
9769 elink_cl45_read(sc, phy,
9771 MDIO_AN_REG_8481_LEGACY_MII_STATUS,
9774 vars->link_status |=
9775 LINK_STATUS_AUTO_NEGOTIATE_COMPLETE;
9776 elink_cl45_read(sc, phy,
9778 MDIO_AN_REG_8481_LEGACY_AN_EXPANSION,
9780 if ((val & (1 << 0)) == 0)
9781 vars->link_status |=
9782 LINK_STATUS_PARALLEL_DETECTION_USED;
9786 PMD_DRV_LOG(DEBUG, sc, "BNX2X848x3: link speed is %d",
9788 elink_ext_phy_resolve_fc(phy, params, vars);
9790 /* Read LP advertised speeds */
9791 elink_cl45_read(sc, phy, MDIO_AN_DEVAD,
9792 MDIO_AN_REG_CL37_FC_LP, &val);
9794 vars->link_status |=
9795 LINK_STATUS_LINK_PARTNER_10THD_CAPABLE;
9797 vars->link_status |=
9798 LINK_STATUS_LINK_PARTNER_10TFD_CAPABLE;
9800 vars->link_status |=
9801 LINK_STATUS_LINK_PARTNER_100TXHD_CAPABLE;
9803 vars->link_status |=
9804 LINK_STATUS_LINK_PARTNER_100TXFD_CAPABLE;
9806 vars->link_status |=
9807 LINK_STATUS_LINK_PARTNER_100T4_CAPABLE;
9809 elink_cl45_read(sc, phy, MDIO_AN_DEVAD,
9810 MDIO_AN_REG_1000T_STATUS, &val);
9812 if (val & (1 << 10))
9813 vars->link_status |=
9814 LINK_STATUS_LINK_PARTNER_1000THD_CAPABLE;
9815 if (val & (1 << 11))
9816 vars->link_status |=
9817 LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE;
9819 elink_cl45_read(sc, phy, MDIO_AN_DEVAD,
9820 MDIO_AN_REG_MASTER_STATUS, &val);
9822 if (val & (1 << 11))
9823 vars->link_status |=
9824 LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE;
9826 /* Determine if EEE was negotiated */
9827 if ((phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84833) ||
9828 (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84834))
9829 elink_eee_an_resolve(phy, params, vars);
9835 static uint8_t elink_848xx_format_ver(uint32_t raw_ver, uint8_t * str,
9838 elink_status_t status = ELINK_STATUS_OK;
9839 uint32_t spirom_ver;
9840 spirom_ver = ((raw_ver & 0xF80) >> 7) << 16 | (raw_ver & 0x7F);
9841 status = elink_format_ver(spirom_ver, str, len);
9845 static void elink_8481_hw_reset(__rte_unused struct elink_phy *phy,
9846 struct elink_params *params)
9848 elink_cb_gpio_write(params->sc, MISC_REGISTERS_GPIO_1,
9849 MISC_REGISTERS_GPIO_OUTPUT_LOW, 0);
9850 elink_cb_gpio_write(params->sc, MISC_REGISTERS_GPIO_1,
9851 MISC_REGISTERS_GPIO_OUTPUT_LOW, 1);
9854 static void elink_8481_link_reset(struct elink_phy *phy,
9855 struct elink_params *params)
9857 elink_cl45_write(params->sc, phy,
9858 MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0x0000);
9859 elink_cl45_write(params->sc, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 1);
9862 static void elink_848x3_link_reset(struct elink_phy *phy,
9863 struct elink_params *params)
9865 struct bnx2x_softc *sc = params->sc;
9869 if (!(CHIP_IS_E1x(sc)))
9872 port = params->port;
9874 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84823) {
9875 elink_cb_gpio_write(sc, MISC_REGISTERS_GPIO_3,
9876 MISC_REGISTERS_GPIO_OUTPUT_LOW, port);
9878 elink_cl45_read(sc, phy,
9880 MDIO_84833_TOP_CFG_XGPHY_STRAP1, &val16);
9881 val16 |= MDIO_84833_SUPER_ISOLATE;
9882 elink_cl45_write(sc, phy,
9884 MDIO_84833_TOP_CFG_XGPHY_STRAP1, val16);
9888 static void elink_848xx_set_link_led(struct elink_phy *phy,
9889 struct elink_params *params, uint8_t mode)
9891 struct bnx2x_softc *sc = params->sc;
9893 __rte_unused uint8_t port;
9895 if (!(CHIP_IS_E1x(sc)))
9898 port = params->port;
9901 case ELINK_LED_MODE_OFF:
9903 PMD_DRV_LOG(DEBUG, sc, "Port 0x%x: LED MODE OFF", port);
9905 if ((params->hw_led_mode << SHARED_HW_CFG_LED_MODE_SHIFT) ==
9906 SHARED_HW_CFG_LED_EXTPHY1) {
9909 elink_cl45_write(sc, phy,
9911 MDIO_PMA_REG_8481_LED1_MASK, 0x0);
9913 elink_cl45_write(sc, phy,
9915 MDIO_PMA_REG_8481_LED2_MASK, 0x0);
9917 elink_cl45_write(sc, phy,
9919 MDIO_PMA_REG_8481_LED3_MASK, 0x0);
9921 elink_cl45_write(sc, phy,
9923 MDIO_PMA_REG_8481_LED5_MASK, 0x0);
9926 elink_cl45_write(sc, phy,
9928 MDIO_PMA_REG_8481_LED1_MASK, 0x0);
9931 case ELINK_LED_MODE_FRONT_PANEL_OFF:
9933 PMD_DRV_LOG(DEBUG, sc,
9934 "Port 0x%x: LED MODE FRONT PANEL OFF", port);
9936 if ((params->hw_led_mode << SHARED_HW_CFG_LED_MODE_SHIFT) ==
9937 SHARED_HW_CFG_LED_EXTPHY1) {
9940 elink_cl45_write(sc, phy,
9942 MDIO_PMA_REG_8481_LED1_MASK, 0x0);
9944 elink_cl45_write(sc, phy,
9946 MDIO_PMA_REG_8481_LED2_MASK, 0x0);
9948 elink_cl45_write(sc, phy,
9950 MDIO_PMA_REG_8481_LED3_MASK, 0x0);
9952 elink_cl45_write(sc, phy,
9954 MDIO_PMA_REG_8481_LED5_MASK, 0x20);
9957 elink_cl45_write(sc, phy,
9959 MDIO_PMA_REG_8481_LED1_MASK, 0x0);
9960 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84834) {
9961 /* Disable MI_INT interrupt before setting LED4
9962 * source to constant off.
9964 if (REG_RD(sc, NIG_REG_MASK_INTERRUPT_PORT0 +
9966 ELINK_NIG_MASK_MI_INT) {
9967 params->link_flags |=
9968 ELINK_LINK_FLAGS_INT_DISABLED;
9971 NIG_REG_MASK_INTERRUPT_PORT0
9973 ELINK_NIG_MASK_MI_INT);
9975 elink_cl45_write(sc, phy,
9977 MDIO_PMA_REG_8481_SIGNAL_MASK,
9982 case ELINK_LED_MODE_ON:
9984 PMD_DRV_LOG(DEBUG, sc, "Port 0x%x: LED MODE ON", port);
9986 if ((params->hw_led_mode << SHARED_HW_CFG_LED_MODE_SHIFT) ==
9987 SHARED_HW_CFG_LED_EXTPHY1) {
9988 /* Set control reg */
9989 elink_cl45_read(sc, phy,
9991 MDIO_PMA_REG_8481_LINK_SIGNAL, &val);
9995 elink_cl45_write(sc, phy,
9997 MDIO_PMA_REG_8481_LINK_SIGNAL, val);
10000 elink_cl45_write(sc, phy,
10002 MDIO_PMA_REG_8481_LED1_MASK, 0x0);
10004 elink_cl45_write(sc, phy,
10006 MDIO_PMA_REG_8481_LED2_MASK, 0x20);
10008 elink_cl45_write(sc, phy,
10010 MDIO_PMA_REG_8481_LED3_MASK, 0x20);
10012 elink_cl45_write(sc, phy,
10014 MDIO_PMA_REG_8481_LED5_MASK, 0x0);
10016 elink_cl45_write(sc, phy,
10018 MDIO_PMA_REG_8481_LED1_MASK, 0x20);
10019 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84834) {
10020 /* Disable MI_INT interrupt before setting LED4
10021 * source to constant on.
10023 if (REG_RD(sc, NIG_REG_MASK_INTERRUPT_PORT0 +
10024 params->port * 4) &
10025 ELINK_NIG_MASK_MI_INT) {
10026 params->link_flags |=
10027 ELINK_LINK_FLAGS_INT_DISABLED;
10030 NIG_REG_MASK_INTERRUPT_PORT0
10031 + params->port * 4,
10032 ELINK_NIG_MASK_MI_INT);
10034 elink_cl45_write(sc, phy,
10036 MDIO_PMA_REG_8481_SIGNAL_MASK,
10042 case ELINK_LED_MODE_OPER:
10044 PMD_DRV_LOG(DEBUG, sc, "Port 0x%x: LED MODE OPER", port);
10046 if ((params->hw_led_mode << SHARED_HW_CFG_LED_MODE_SHIFT) ==
10047 SHARED_HW_CFG_LED_EXTPHY1) {
10049 /* Set control reg */
10050 elink_cl45_read(sc, phy,
10052 MDIO_PMA_REG_8481_LINK_SIGNAL, &val);
10055 MDIO_PMA_REG_8481_LINK_SIGNAL_LED4_ENABLE_MASK)
10057 MDIO_PMA_REG_8481_LINK_SIGNAL_LED4_ENABLE_SHIFT))
10059 PMD_DRV_LOG(DEBUG, sc, "Setting LINK_SIGNAL");
10060 elink_cl45_write(sc, phy,
10062 MDIO_PMA_REG_8481_LINK_SIGNAL,
10066 /* Set LED masks */
10067 elink_cl45_write(sc, phy,
10069 MDIO_PMA_REG_8481_LED1_MASK, 0x10);
10071 elink_cl45_write(sc, phy,
10073 MDIO_PMA_REG_8481_LED2_MASK, 0x80);
10075 elink_cl45_write(sc, phy,
10077 MDIO_PMA_REG_8481_LED3_MASK, 0x98);
10079 elink_cl45_write(sc, phy,
10081 MDIO_PMA_REG_8481_LED5_MASK, 0x40);
10084 /* EXTPHY2 LED mode indicate that the 100M/1G/10G LED
10085 * sources are all wired through LED1, rather than only
10086 * 10G in other modes.
10088 val = ((params->hw_led_mode <<
10089 SHARED_HW_CFG_LED_MODE_SHIFT) ==
10090 SHARED_HW_CFG_LED_EXTPHY2) ? 0x98 : 0x80;
10092 elink_cl45_write(sc, phy,
10094 MDIO_PMA_REG_8481_LED1_MASK, val);
10096 /* Tell LED3 to blink on source */
10097 elink_cl45_read(sc, phy,
10099 MDIO_PMA_REG_8481_LINK_SIGNAL, &val);
10101 val |= (1 << 6); /* A83B[8:6]= 1 */
10102 elink_cl45_write(sc, phy,
10104 MDIO_PMA_REG_8481_LINK_SIGNAL, val);
10105 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84834) {
10106 /* Restore LED4 source to external link,
10107 * and re-enable interrupts.
10109 elink_cl45_write(sc, phy,
10111 MDIO_PMA_REG_8481_SIGNAL_MASK,
10113 if (params->link_flags &
10114 ELINK_LINK_FLAGS_INT_DISABLED) {
10115 elink_link_int_enable(params);
10116 params->link_flags &=
10117 ~ELINK_LINK_FLAGS_INT_DISABLED;
10124 /* This is a workaround for E3+84833 until autoneg
10125 * restart is fixed in f/w
10127 if (CHIP_IS_E3(sc)) {
10128 elink_cl45_read(sc, phy, MDIO_WC_DEVAD,
10129 MDIO_WC_REG_GP2_STATUS_GP_2_1, &val);
10133 /******************************************************************/
10134 /* 54618SE PHY SECTION */
10135 /******************************************************************/
10136 static void elink_54618se_specific_func(struct elink_phy *phy,
10137 struct elink_params *params,
10140 struct bnx2x_softc *sc = params->sc;
10143 case ELINK_PHY_INIT:
10144 /* Configure LED4: set to INTR (0x6). */
10145 /* Accessing shadow register 0xe. */
10146 elink_cl22_write(sc, phy,
10147 MDIO_REG_GPHY_SHADOW,
10148 MDIO_REG_GPHY_SHADOW_LED_SEL2);
10149 elink_cl22_read(sc, phy, MDIO_REG_GPHY_SHADOW, &temp);
10150 temp &= ~(0xf << 4);
10151 temp |= (0x6 << 4);
10152 elink_cl22_write(sc, phy,
10153 MDIO_REG_GPHY_SHADOW,
10154 MDIO_REG_GPHY_SHADOW_WR_ENA | temp);
10155 /* Configure INTR based on link status change. */
10156 elink_cl22_write(sc, phy,
10157 MDIO_REG_INTR_MASK,
10158 ~MDIO_REG_INTR_MASK_LINK_STATUS);
10163 static uint8_t elink_54618se_config_init(struct elink_phy *phy,
10164 struct elink_params *params,
10165 struct elink_vars *vars)
10167 struct bnx2x_softc *sc = params->sc;
10169 uint16_t autoneg_val, an_1000_val, an_10_100_val, fc_val, temp;
10172 PMD_DRV_LOG(DEBUG, sc, "54618SE cfg init");
10175 /* This works with E3 only, no need to check the chip
10176 * before determining the port.
10178 port = params->port;
10180 cfg_pin = (REG_RD(sc, params->shmem_base +
10181 offsetof(struct shmem_region,
10182 dev_info.port_hw_config[port].
10184 PORT_HW_CFG_E3_PHY_RESET_MASK) >>
10185 PORT_HW_CFG_E3_PHY_RESET_SHIFT;
10187 /* Drive pin high to bring the GPHY out of reset. */
10188 elink_set_cfg_pin(sc, cfg_pin, 1);
10190 /* wait for GPHY to reset */
10194 elink_cl22_write(sc, phy, MDIO_PMA_REG_CTRL, 0x8000);
10195 elink_wait_reset_complete(sc, phy, params);
10197 /* Wait for GPHY to reset */
10200 elink_54618se_specific_func(phy, params, ELINK_PHY_INIT);
10201 /* Flip the signal detect polarity (set 0x1c.0x1e[8]). */
10202 elink_cl22_write(sc, phy,
10203 MDIO_REG_GPHY_SHADOW,
10204 MDIO_REG_GPHY_SHADOW_AUTO_DET_MED);
10205 elink_cl22_read(sc, phy, MDIO_REG_GPHY_SHADOW, &temp);
10206 temp |= MDIO_REG_GPHY_SHADOW_INVERT_FIB_SD;
10207 elink_cl22_write(sc, phy,
10208 MDIO_REG_GPHY_SHADOW,
10209 MDIO_REG_GPHY_SHADOW_WR_ENA | temp);
10212 /* Please refer to Table 28B-3 of 802.3ab-1999 spec. */
10213 elink_calc_ieee_aneg_adv(phy, params, &vars->ieee_fc);
10215 if ((vars->ieee_fc & MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) ==
10216 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC)
10217 fc_val |= MDIO_AN_REG_ADV_PAUSE_ASYMMETRIC;
10219 if ((vars->ieee_fc & MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) ==
10220 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH)
10221 fc_val |= MDIO_AN_REG_ADV_PAUSE_PAUSE;
10223 /* Read all advertisement */
10224 elink_cl22_read(sc, phy, 0x09, &an_1000_val);
10226 elink_cl22_read(sc, phy, 0x04, &an_10_100_val);
10228 elink_cl22_read(sc, phy, MDIO_PMA_REG_CTRL, &autoneg_val);
10230 /* Disable forced speed */
10232 ~((1 << 6) | (1 << 8) | (1 << 9) | (1 << 12) | (1 << 13));
10234 ~((1 << 5) | (1 << 6) | (1 << 7) | (1 << 8) | (1 << 10) |
10237 if (((phy->req_line_speed == ELINK_SPEED_AUTO_NEG) &&
10238 (phy->speed_cap_mask &
10239 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) ||
10240 (phy->req_line_speed == ELINK_SPEED_1000)) {
10241 an_1000_val |= (1 << 8);
10242 autoneg_val |= (1 << 9 | 1 << 12);
10243 if (phy->req_duplex == DUPLEX_FULL)
10244 an_1000_val |= (1 << 9);
10245 PMD_DRV_LOG(DEBUG, sc, "Advertising 1G");
10247 an_1000_val &= ~((1 << 8) | (1 << 9));
10249 elink_cl22_write(sc, phy, 0x09, an_1000_val);
10250 elink_cl22_read(sc, phy, 0x09, &an_1000_val);
10252 /* Advertise 10/100 link speed */
10253 if (phy->req_line_speed == ELINK_SPEED_AUTO_NEG) {
10254 if (phy->speed_cap_mask &
10255 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF) {
10256 an_10_100_val |= (1 << 5);
10257 autoneg_val |= (1 << 9 | 1 << 12);
10258 PMD_DRV_LOG(DEBUG, sc, "Advertising 10M-HD");
10260 if (phy->speed_cap_mask &
10261 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF) {
10262 an_10_100_val |= (1 << 6);
10263 autoneg_val |= (1 << 9 | 1 << 12);
10264 PMD_DRV_LOG(DEBUG, sc, "Advertising 10M-FD");
10266 if (phy->speed_cap_mask &
10267 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF) {
10268 an_10_100_val |= (1 << 7);
10269 autoneg_val |= (1 << 9 | 1 << 12);
10270 PMD_DRV_LOG(DEBUG, sc, "Advertising 100M-HD");
10272 if (phy->speed_cap_mask &
10273 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL) {
10274 an_10_100_val |= (1 << 8);
10275 autoneg_val |= (1 << 9 | 1 << 12);
10276 PMD_DRV_LOG(DEBUG, sc, "Advertising 100M-FD");
10280 /* Only 10/100 are allowed to work in FORCE mode */
10281 if (phy->req_line_speed == ELINK_SPEED_100) {
10282 autoneg_val |= (1 << 13);
10283 /* Enabled AUTO-MDIX when autoneg is disabled */
10284 elink_cl22_write(sc, phy, 0x18, (1 << 15 | 1 << 9 | 7 << 0));
10285 PMD_DRV_LOG(DEBUG, sc, "Setting 100M force");
10287 if (phy->req_line_speed == ELINK_SPEED_10) {
10288 /* Enabled AUTO-MDIX when autoneg is disabled */
10289 elink_cl22_write(sc, phy, 0x18, (1 << 15 | 1 << 9 | 7 << 0));
10290 PMD_DRV_LOG(DEBUG, sc, "Setting 10M force");
10293 if ((phy->flags & ELINK_FLAGS_EEE) && elink_eee_has_cap(params)) {
10296 elink_cl22_write(sc, phy, MDIO_REG_GPHY_EXP_ACCESS,
10297 MDIO_REG_GPHY_EXP_ACCESS_TOP |
10298 MDIO_REG_GPHY_EXP_TOP_2K_BUF);
10299 elink_cl22_read(sc, phy, MDIO_REG_GPHY_EXP_ACCESS_GATE, &temp);
10301 elink_cl22_write(sc, phy, MDIO_REG_GPHY_EXP_ACCESS_GATE, temp);
10303 rc = elink_eee_initial_config(params, vars, SHMEM_EEE_1G_ADV);
10304 if (rc != ELINK_STATUS_OK) {
10305 PMD_DRV_LOG(DEBUG, sc, "Failed to configure EEE timers");
10306 elink_eee_disable(phy, params, vars);
10307 } else if ((params->eee_mode & ELINK_EEE_MODE_ADV_LPI) &&
10308 (phy->req_duplex == DUPLEX_FULL) &&
10309 (elink_eee_calc_timer(params) ||
10310 !(params->eee_mode & ELINK_EEE_MODE_ENABLE_LPI))) {
10311 /* Need to advertise EEE only when requested,
10312 * and either no LPI assertion was requested,
10313 * or it was requested and a valid timer was set.
10314 * Also notice full duplex is required for EEE.
10316 elink_eee_advertise(phy, params, vars,
10319 PMD_DRV_LOG(DEBUG, sc, "Don't Advertise 1GBase-T EEE");
10320 elink_eee_disable(phy, params, vars);
10323 vars->eee_status &= ~SHMEM_EEE_1G_ADV <<
10324 SHMEM_EEE_SUPPORTED_SHIFT;
10326 if (phy->flags & ELINK_FLAGS_EEE) {
10327 /* Handle legacy auto-grEEEn */
10328 if (params->feature_config_flags &
10329 ELINK_FEATURE_CONFIG_AUTOGREEEN_ENABLED) {
10331 PMD_DRV_LOG(DEBUG, sc, "Enabling Auto-GrEEEn");
10334 PMD_DRV_LOG(DEBUG, sc, "Don't Adv. EEE");
10336 elink_cl45_write(sc, phy, MDIO_AN_DEVAD,
10337 MDIO_AN_REG_EEE_ADV, temp);
10341 elink_cl22_write(sc, phy, 0x04, an_10_100_val | fc_val);
10343 if (phy->req_duplex == DUPLEX_FULL)
10344 autoneg_val |= (1 << 8);
10346 elink_cl22_write(sc, phy, MDIO_PMA_REG_CTRL, autoneg_val);
10348 return ELINK_STATUS_OK;
10351 static void elink_5461x_set_link_led(struct elink_phy *phy,
10352 struct elink_params *params, uint8_t mode)
10354 struct bnx2x_softc *sc = params->sc;
10357 elink_cl22_write(sc, phy,
10358 MDIO_REG_GPHY_SHADOW, MDIO_REG_GPHY_SHADOW_LED_SEL1);
10359 elink_cl22_read(sc, phy, MDIO_REG_GPHY_SHADOW, &temp);
10362 PMD_DRV_LOG(DEBUG, sc, "54618x set link led (mode=%x)", mode);
10364 case ELINK_LED_MODE_FRONT_PANEL_OFF:
10365 case ELINK_LED_MODE_OFF:
10368 case ELINK_LED_MODE_OPER:
10371 case ELINK_LED_MODE_ON:
10377 elink_cl22_write(sc, phy,
10378 MDIO_REG_GPHY_SHADOW,
10379 MDIO_REG_GPHY_SHADOW_WR_ENA | temp);
10383 static void elink_54618se_link_reset(struct elink_phy *phy,
10384 struct elink_params *params)
10386 struct bnx2x_softc *sc = params->sc;
10390 /* In case of no EPIO routed to reset the GPHY, put it
10391 * in low power mode.
10393 elink_cl22_write(sc, phy, MDIO_PMA_REG_CTRL, 0x800);
10394 /* This works with E3 only, no need to check the chip
10395 * before determining the port.
10397 port = params->port;
10398 cfg_pin = (REG_RD(sc, params->shmem_base +
10399 offsetof(struct shmem_region,
10400 dev_info.port_hw_config[port].
10402 PORT_HW_CFG_E3_PHY_RESET_MASK) >>
10403 PORT_HW_CFG_E3_PHY_RESET_SHIFT;
10405 /* Drive pin low to put GPHY in reset. */
10406 elink_set_cfg_pin(sc, cfg_pin, 0);
10409 static uint8_t elink_54618se_read_status(struct elink_phy *phy,
10410 struct elink_params *params,
10411 struct elink_vars *vars)
10413 struct bnx2x_softc *sc = params->sc;
10415 uint8_t link_up = 0;
10416 uint16_t legacy_status, legacy_speed;
10418 /* Get speed operation status */
10419 elink_cl22_read(sc, phy, MDIO_REG_GPHY_AUX_STATUS, &legacy_status);
10420 PMD_DRV_LOG(DEBUG, sc, "54618SE read_status: 0x%x", legacy_status);
10422 /* Read status to clear the PHY interrupt. */
10423 elink_cl22_read(sc, phy, MDIO_REG_INTR_STATUS, &val);
10425 link_up = ((legacy_status & (1 << 2)) == (1 << 2));
10428 legacy_speed = (legacy_status & (7 << 8));
10429 if (legacy_speed == (7 << 8)) {
10430 vars->line_speed = ELINK_SPEED_1000;
10431 vars->duplex = DUPLEX_FULL;
10432 } else if (legacy_speed == (6 << 8)) {
10433 vars->line_speed = ELINK_SPEED_1000;
10434 vars->duplex = DUPLEX_HALF;
10435 } else if (legacy_speed == (5 << 8)) {
10436 vars->line_speed = ELINK_SPEED_100;
10437 vars->duplex = DUPLEX_FULL;
10439 /* Omitting 100Base-T4 for now */
10440 else if (legacy_speed == (3 << 8)) {
10441 vars->line_speed = ELINK_SPEED_100;
10442 vars->duplex = DUPLEX_HALF;
10443 } else if (legacy_speed == (2 << 8)) {
10444 vars->line_speed = ELINK_SPEED_10;
10445 vars->duplex = DUPLEX_FULL;
10446 } else if (legacy_speed == (1 << 8)) {
10447 vars->line_speed = ELINK_SPEED_10;
10448 vars->duplex = DUPLEX_HALF;
10449 } else /* Should not happen */
10450 vars->line_speed = 0;
10452 PMD_DRV_LOG(DEBUG, sc,
10453 "Link is up in %dMbps, is_duplex_full= %d",
10454 vars->line_speed, (vars->duplex == DUPLEX_FULL));
10456 /* Check legacy speed AN resolution */
10457 elink_cl22_read(sc, phy, 0x01, &val);
10458 if (val & (1 << 5))
10459 vars->link_status |=
10460 LINK_STATUS_AUTO_NEGOTIATE_COMPLETE;
10461 elink_cl22_read(sc, phy, 0x06, &val);
10462 if ((val & (1 << 0)) == 0)
10463 vars->link_status |=
10464 LINK_STATUS_PARALLEL_DETECTION_USED;
10466 PMD_DRV_LOG(DEBUG, sc, "BNX2X54618SE: link speed is %d",
10469 elink_ext_phy_resolve_fc(phy, params, vars);
10471 if (vars->link_status & LINK_STATUS_AUTO_NEGOTIATE_COMPLETE) {
10472 /* Report LP advertised speeds */
10473 elink_cl22_read(sc, phy, 0x5, &val);
10475 if (val & (1 << 5))
10476 vars->link_status |=
10477 LINK_STATUS_LINK_PARTNER_10THD_CAPABLE;
10478 if (val & (1 << 6))
10479 vars->link_status |=
10480 LINK_STATUS_LINK_PARTNER_10TFD_CAPABLE;
10481 if (val & (1 << 7))
10482 vars->link_status |=
10483 LINK_STATUS_LINK_PARTNER_100TXHD_CAPABLE;
10484 if (val & (1 << 8))
10485 vars->link_status |=
10486 LINK_STATUS_LINK_PARTNER_100TXFD_CAPABLE;
10487 if (val & (1 << 9))
10488 vars->link_status |=
10489 LINK_STATUS_LINK_PARTNER_100T4_CAPABLE;
10491 elink_cl22_read(sc, phy, 0xa, &val);
10492 if (val & (1 << 10))
10493 vars->link_status |=
10494 LINK_STATUS_LINK_PARTNER_1000THD_CAPABLE;
10495 if (val & (1 << 11))
10496 vars->link_status |=
10497 LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE;
10499 if ((phy->flags & ELINK_FLAGS_EEE) &&
10500 elink_eee_has_cap(params))
10501 elink_eee_an_resolve(phy, params, vars);
10507 static void elink_54618se_config_loopback(struct elink_phy *phy,
10508 struct elink_params *params)
10510 struct bnx2x_softc *sc = params->sc;
10512 uint32_t umac_base = params->port ? GRCBASE_UMAC1 : GRCBASE_UMAC0;
10514 PMD_DRV_LOG(DEBUG, sc, "2PMA/PMD ext_phy_loopback: 54618se");
10516 /* Enable master/slave manual mmode and set to master */
10517 /* mii write 9 [bits set 11 12] */
10518 elink_cl22_write(sc, phy, 0x09, 3 << 11);
10520 /* forced 1G and disable autoneg */
10521 /* set val [mii read 0] */
10522 /* set val [expr $val & [bits clear 6 12 13]] */
10523 /* set val [expr $val | [bits set 6 8]] */
10524 /* mii write 0 $val */
10525 elink_cl22_read(sc, phy, 0x00, &val);
10526 val &= ~((1 << 6) | (1 << 12) | (1 << 13));
10527 val |= (1 << 6) | (1 << 8);
10528 elink_cl22_write(sc, phy, 0x00, val);
10530 /* Set external loopback and Tx using 6dB coding */
10531 /* mii write 0x18 7 */
10532 /* set val [mii read 0x18] */
10533 /* mii write 0x18 [expr $val | [bits set 10 15]] */
10534 elink_cl22_write(sc, phy, 0x18, 7);
10535 elink_cl22_read(sc, phy, 0x18, &val);
10536 elink_cl22_write(sc, phy, 0x18, val | (1 << 10) | (1 << 15));
10538 /* This register opens the gate for the UMAC despite its name */
10539 REG_WR(sc, NIG_REG_EGRESS_EMAC0_PORT + params->port * 4, 1);
10541 /* Maximum Frame Length (RW). Defines a 14-Bit maximum frame
10542 * length used by the MAC receive logic to check frames.
10544 REG_WR(sc, umac_base + UMAC_REG_MAXFR, 0x2710);
10547 /******************************************************************/
10548 /* SFX7101 PHY SECTION */
10549 /******************************************************************/
10550 static void elink_7101_config_loopback(struct elink_phy *phy,
10551 struct elink_params *params)
10553 struct bnx2x_softc *sc = params->sc;
10554 /* SFX7101_XGXS_TEST1 */
10555 elink_cl45_write(sc, phy,
10556 MDIO_XS_DEVAD, MDIO_XS_SFX7101_XGXS_TEST1, 0x100);
10559 static uint8_t elink_7101_config_init(struct elink_phy *phy,
10560 struct elink_params *params,
10561 struct elink_vars *vars)
10563 uint16_t fw_ver1, fw_ver2, val;
10564 struct bnx2x_softc *sc = params->sc;
10565 PMD_DRV_LOG(DEBUG, sc, "Setting the SFX7101 LASI indication");
10567 /* Restore normal power mode */
10568 elink_cb_gpio_write(sc, MISC_REGISTERS_GPIO_2,
10569 MISC_REGISTERS_GPIO_OUTPUT_HIGH, params->port);
10571 elink_ext_phy_hw_reset(sc, params->port);
10572 elink_wait_reset_complete(sc, phy, params);
10574 elink_cl45_write(sc, phy, MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 0x1);
10575 PMD_DRV_LOG(DEBUG, sc, "Setting the SFX7101 LED to blink on traffic");
10576 elink_cl45_write(sc, phy,
10577 MDIO_PMA_DEVAD, MDIO_PMA_REG_7107_LED_CNTL, (1 << 3));
10579 elink_ext_phy_set_pause(params, phy, vars);
10580 /* Restart autoneg */
10581 elink_cl45_read(sc, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, &val);
10583 elink_cl45_write(sc, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, val);
10585 /* Save spirom version */
10586 elink_cl45_read(sc, phy,
10587 MDIO_PMA_DEVAD, MDIO_PMA_REG_7101_VER1, &fw_ver1);
10589 elink_cl45_read(sc, phy,
10590 MDIO_PMA_DEVAD, MDIO_PMA_REG_7101_VER2, &fw_ver2);
10591 elink_save_spirom_version(sc, params->port,
10592 (uint32_t) (fw_ver1 << 16 | fw_ver2),
10594 return ELINK_STATUS_OK;
10597 static uint8_t elink_7101_read_status(struct elink_phy *phy,
10598 struct elink_params *params,
10599 struct elink_vars *vars)
10601 struct bnx2x_softc *sc = params->sc;
10603 uint16_t val1, val2;
10604 elink_cl45_read(sc, phy, MDIO_PMA_DEVAD, MDIO_PMA_LASI_STAT, &val2);
10605 elink_cl45_read(sc, phy, MDIO_PMA_DEVAD, MDIO_PMA_LASI_STAT, &val1);
10606 PMD_DRV_LOG(DEBUG, sc, "10G-base-T LASI status 0x%x->0x%x", val2, val1);
10607 elink_cl45_read(sc, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val2);
10608 elink_cl45_read(sc, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val1);
10609 PMD_DRV_LOG(DEBUG, sc, "10G-base-T PMA status 0x%x->0x%x", val2, val1);
10610 link_up = ((val1 & 4) == 4);
10611 /* If link is up print the AN outcome of the SFX7101 PHY */
10613 elink_cl45_read(sc, phy,
10614 MDIO_AN_DEVAD, MDIO_AN_REG_MASTER_STATUS,
10616 vars->line_speed = ELINK_SPEED_10000;
10617 vars->duplex = DUPLEX_FULL;
10618 PMD_DRV_LOG(DEBUG, sc, "SFX7101 AN status 0x%x->Master=%x",
10619 val2, (val2 & (1 << 14)));
10620 elink_ext_phy_10G_an_resolve(sc, phy, vars);
10621 elink_ext_phy_resolve_fc(phy, params, vars);
10623 /* Read LP advertised speeds */
10624 if (val2 & (1 << 11))
10625 vars->link_status |=
10626 LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE;
10631 static uint8_t elink_7101_format_ver(uint32_t spirom_ver, uint8_t * str,
10635 return ELINK_STATUS_ERROR;
10636 str[0] = (spirom_ver & 0xFF);
10637 str[1] = (spirom_ver & 0xFF00) >> 8;
10638 str[2] = (spirom_ver & 0xFF0000) >> 16;
10639 str[3] = (spirom_ver & 0xFF000000) >> 24;
10642 return ELINK_STATUS_OK;
10645 static void elink_7101_hw_reset(__rte_unused struct elink_phy *phy,
10646 struct elink_params *params)
10648 /* Low power mode is controlled by GPIO 2 */
10649 elink_cb_gpio_write(params->sc, MISC_REGISTERS_GPIO_2,
10650 MISC_REGISTERS_GPIO_OUTPUT_LOW, params->port);
10651 /* The PHY reset is controlled by GPIO 1 */
10652 elink_cb_gpio_write(params->sc, MISC_REGISTERS_GPIO_1,
10653 MISC_REGISTERS_GPIO_OUTPUT_LOW, params->port);
10656 static void elink_7101_set_link_led(struct elink_phy *phy,
10657 struct elink_params *params, uint8_t mode)
10660 struct bnx2x_softc *sc = params->sc;
10662 case ELINK_LED_MODE_FRONT_PANEL_OFF:
10663 case ELINK_LED_MODE_OFF:
10666 case ELINK_LED_MODE_ON:
10669 case ELINK_LED_MODE_OPER:
10673 elink_cl45_write(sc, phy,
10674 MDIO_PMA_DEVAD, MDIO_PMA_REG_7107_LINK_LED_CNTL, val);
10677 /******************************************************************/
10678 /* STATIC PHY DECLARATION */
10679 /******************************************************************/
10681 static const struct elink_phy phy_null = {
10682 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN,
10685 .flags = ELINK_FLAGS_INIT_XGXS_FIRST,
10686 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
10687 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
10690 .media_type = ELINK_ETH_PHY_NOT_PRESENT,
10692 .req_flow_ctrl = 0,
10693 .req_line_speed = 0,
10694 .speed_cap_mask = 0,
10697 .config_init = NULL,
10698 .read_status = NULL,
10699 .link_reset = NULL,
10700 .config_loopback = NULL,
10701 .format_fw_ver = NULL,
10703 .set_link_led = NULL,
10704 .phy_specific_func = NULL
10707 static const struct elink_phy phy_serdes = {
10708 .type = PORT_HW_CFG_SERDES_EXT_PHY_TYPE_DIRECT,
10712 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
10713 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
10715 .supported = (ELINK_SUPPORTED_10baseT_Half |
10716 ELINK_SUPPORTED_10baseT_Full |
10717 ELINK_SUPPORTED_100baseT_Half |
10718 ELINK_SUPPORTED_100baseT_Full |
10719 ELINK_SUPPORTED_1000baseT_Full |
10720 ELINK_SUPPORTED_2500baseX_Full |
10721 ELINK_SUPPORTED_TP |
10722 ELINK_SUPPORTED_Autoneg |
10723 ELINK_SUPPORTED_Pause | ELINK_SUPPORTED_Asym_Pause),
10724 .media_type = ELINK_ETH_PHY_BASE_T,
10726 .req_flow_ctrl = 0,
10727 .req_line_speed = 0,
10728 .speed_cap_mask = 0,
10731 .config_init = elink_xgxs_config_init,
10732 .read_status = elink_link_settings_status,
10733 .link_reset = elink_int_link_reset,
10734 .config_loopback = NULL,
10735 .format_fw_ver = NULL,
10737 .set_link_led = NULL,
10738 .phy_specific_func = NULL
10741 static const struct elink_phy phy_xgxs = {
10742 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT,
10746 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
10747 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
10749 .supported = (ELINK_SUPPORTED_10baseT_Half |
10750 ELINK_SUPPORTED_10baseT_Full |
10751 ELINK_SUPPORTED_100baseT_Half |
10752 ELINK_SUPPORTED_100baseT_Full |
10753 ELINK_SUPPORTED_1000baseT_Full |
10754 ELINK_SUPPORTED_2500baseX_Full |
10755 ELINK_SUPPORTED_10000baseT_Full |
10756 ELINK_SUPPORTED_FIBRE |
10757 ELINK_SUPPORTED_Autoneg |
10758 ELINK_SUPPORTED_Pause | ELINK_SUPPORTED_Asym_Pause),
10759 .media_type = ELINK_ETH_PHY_CX4,
10761 .req_flow_ctrl = 0,
10762 .req_line_speed = 0,
10763 .speed_cap_mask = 0,
10766 .config_init = elink_xgxs_config_init,
10767 .read_status = elink_link_settings_status,
10768 .link_reset = elink_int_link_reset,
10769 .config_loopback = elink_set_xgxs_loopback,
10770 .format_fw_ver = NULL,
10772 .set_link_led = NULL,
10773 .phy_specific_func = elink_xgxs_specific_func
10776 static const struct elink_phy phy_warpcore = {
10777 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT,
10780 .flags = ELINK_FLAGS_TX_ERROR_CHECK,
10781 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
10782 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
10784 .supported = (ELINK_SUPPORTED_10baseT_Half |
10785 ELINK_SUPPORTED_10baseT_Full |
10786 ELINK_SUPPORTED_100baseT_Half |
10787 ELINK_SUPPORTED_100baseT_Full |
10788 ELINK_SUPPORTED_1000baseT_Full |
10789 ELINK_SUPPORTED_10000baseT_Full |
10790 ELINK_SUPPORTED_20000baseKR2_Full |
10791 ELINK_SUPPORTED_20000baseMLD2_Full |
10792 ELINK_SUPPORTED_FIBRE |
10793 ELINK_SUPPORTED_Autoneg |
10794 ELINK_SUPPORTED_Pause | ELINK_SUPPORTED_Asym_Pause),
10795 .media_type = ELINK_ETH_PHY_UNSPECIFIED,
10797 .req_flow_ctrl = 0,
10798 .req_line_speed = 0,
10799 .speed_cap_mask = 0,
10800 /* req_duplex = */ 0,
10802 .config_init = elink_warpcore_config_init,
10803 .read_status = elink_warpcore_read_status,
10804 .link_reset = elink_warpcore_link_reset,
10805 .config_loopback = elink_set_warpcore_loopback,
10806 .format_fw_ver = NULL,
10807 .hw_reset = elink_warpcore_hw_reset,
10808 .set_link_led = NULL,
10809 .phy_specific_func = NULL
10812 static const struct elink_phy phy_7101 = {
10813 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101,
10816 .flags = ELINK_FLAGS_FAN_FAILURE_DET_REQ,
10817 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
10818 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
10820 .supported = (ELINK_SUPPORTED_10000baseT_Full |
10821 ELINK_SUPPORTED_TP |
10822 ELINK_SUPPORTED_Autoneg |
10823 ELINK_SUPPORTED_Pause | ELINK_SUPPORTED_Asym_Pause),
10824 .media_type = ELINK_ETH_PHY_BASE_T,
10826 .req_flow_ctrl = 0,
10827 .req_line_speed = 0,
10828 .speed_cap_mask = 0,
10831 .config_init = elink_7101_config_init,
10832 .read_status = elink_7101_read_status,
10833 .link_reset = elink_common_ext_link_reset,
10834 .config_loopback = elink_7101_config_loopback,
10835 .format_fw_ver = elink_7101_format_ver,
10836 .hw_reset = elink_7101_hw_reset,
10837 .set_link_led = elink_7101_set_link_led,
10838 .phy_specific_func = NULL
10841 static const struct elink_phy phy_8073 = {
10842 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X8073,
10846 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
10847 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
10849 .supported = (ELINK_SUPPORTED_10000baseT_Full |
10850 ELINK_SUPPORTED_2500baseX_Full |
10851 ELINK_SUPPORTED_1000baseT_Full |
10852 ELINK_SUPPORTED_FIBRE |
10853 ELINK_SUPPORTED_Autoneg |
10854 ELINK_SUPPORTED_Pause | ELINK_SUPPORTED_Asym_Pause),
10855 .media_type = ELINK_ETH_PHY_KR,
10857 .req_flow_ctrl = 0,
10858 .req_line_speed = 0,
10859 .speed_cap_mask = 0,
10862 .config_init = elink_8073_config_init,
10863 .read_status = elink_8073_read_status,
10864 .link_reset = elink_8073_link_reset,
10865 .config_loopback = NULL,
10866 .format_fw_ver = elink_format_ver,
10868 .set_link_led = NULL,
10869 .phy_specific_func = elink_8073_specific_func
10872 static const struct elink_phy phy_8705 = {
10873 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X8705,
10876 .flags = ELINK_FLAGS_INIT_XGXS_FIRST,
10877 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
10878 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
10880 .supported = (ELINK_SUPPORTED_10000baseT_Full |
10881 ELINK_SUPPORTED_FIBRE |
10882 ELINK_SUPPORTED_Pause | ELINK_SUPPORTED_Asym_Pause),
10883 .media_type = ELINK_ETH_PHY_XFP_FIBER,
10885 .req_flow_ctrl = 0,
10886 .req_line_speed = 0,
10887 .speed_cap_mask = 0,
10890 .config_init = elink_8705_config_init,
10891 .read_status = elink_8705_read_status,
10892 .link_reset = elink_common_ext_link_reset,
10893 .config_loopback = NULL,
10894 .format_fw_ver = elink_null_format_ver,
10896 .set_link_led = NULL,
10897 .phy_specific_func = NULL
10900 static const struct elink_phy phy_8706 = {
10901 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X8706,
10904 .flags = ELINK_FLAGS_INIT_XGXS_FIRST,
10905 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
10906 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
10908 .supported = (ELINK_SUPPORTED_10000baseT_Full |
10909 ELINK_SUPPORTED_1000baseT_Full |
10910 ELINK_SUPPORTED_FIBRE |
10911 ELINK_SUPPORTED_Pause | ELINK_SUPPORTED_Asym_Pause),
10912 .media_type = ELINK_ETH_PHY_SFPP_10G_FIBER,
10914 .req_flow_ctrl = 0,
10915 .req_line_speed = 0,
10916 .speed_cap_mask = 0,
10919 .config_init = elink_8706_config_init,
10920 .read_status = elink_8706_read_status,
10921 .link_reset = elink_common_ext_link_reset,
10922 .config_loopback = NULL,
10923 .format_fw_ver = elink_format_ver,
10925 .set_link_led = NULL,
10926 .phy_specific_func = NULL
10929 static const struct elink_phy phy_8726 = {
10930 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X8726,
10933 .flags = (ELINK_FLAGS_INIT_XGXS_FIRST | ELINK_FLAGS_TX_ERROR_CHECK),
10934 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
10935 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
10937 .supported = (ELINK_SUPPORTED_10000baseT_Full |
10938 ELINK_SUPPORTED_1000baseT_Full |
10939 ELINK_SUPPORTED_Autoneg |
10940 ELINK_SUPPORTED_FIBRE |
10941 ELINK_SUPPORTED_Pause | ELINK_SUPPORTED_Asym_Pause),
10942 .media_type = ELINK_ETH_PHY_NOT_PRESENT,
10944 .req_flow_ctrl = 0,
10945 .req_line_speed = 0,
10946 .speed_cap_mask = 0,
10949 .config_init = elink_8726_config_init,
10950 .read_status = elink_8726_read_status,
10951 .link_reset = elink_8726_link_reset,
10952 .config_loopback = elink_8726_config_loopback,
10953 .format_fw_ver = elink_format_ver,
10955 .set_link_led = NULL,
10956 .phy_specific_func = NULL
10959 static const struct elink_phy phy_8727 = {
10960 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X8727,
10963 .flags = (ELINK_FLAGS_FAN_FAILURE_DET_REQ | ELINK_FLAGS_TX_ERROR_CHECK),
10964 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
10965 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
10967 .supported = (ELINK_SUPPORTED_10000baseT_Full |
10968 ELINK_SUPPORTED_1000baseT_Full |
10969 ELINK_SUPPORTED_FIBRE |
10970 ELINK_SUPPORTED_Pause | ELINK_SUPPORTED_Asym_Pause),
10971 .media_type = ELINK_ETH_PHY_NOT_PRESENT,
10973 .req_flow_ctrl = 0,
10974 .req_line_speed = 0,
10975 .speed_cap_mask = 0,
10978 .config_init = elink_8727_config_init,
10979 .read_status = elink_8727_read_status,
10980 .link_reset = elink_8727_link_reset,
10981 .config_loopback = NULL,
10982 .format_fw_ver = elink_format_ver,
10983 .hw_reset = elink_8727_hw_reset,
10984 .set_link_led = elink_8727_set_link_led,
10985 .phy_specific_func = elink_8727_specific_func
10988 static const struct elink_phy phy_8481 = {
10989 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X8481,
10992 .flags = ELINK_FLAGS_FAN_FAILURE_DET_REQ |
10993 ELINK_FLAGS_REARM_LATCH_SIGNAL,
10994 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
10995 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
10997 .supported = (ELINK_SUPPORTED_10baseT_Half |
10998 ELINK_SUPPORTED_10baseT_Full |
10999 ELINK_SUPPORTED_100baseT_Half |
11000 ELINK_SUPPORTED_100baseT_Full |
11001 ELINK_SUPPORTED_1000baseT_Full |
11002 ELINK_SUPPORTED_10000baseT_Full |
11003 ELINK_SUPPORTED_TP |
11004 ELINK_SUPPORTED_Autoneg |
11005 ELINK_SUPPORTED_Pause | ELINK_SUPPORTED_Asym_Pause),
11006 .media_type = ELINK_ETH_PHY_BASE_T,
11008 .req_flow_ctrl = 0,
11009 .req_line_speed = 0,
11010 .speed_cap_mask = 0,
11013 .config_init = elink_8481_config_init,
11014 .read_status = elink_848xx_read_status,
11015 .link_reset = elink_8481_link_reset,
11016 .config_loopback = NULL,
11017 .format_fw_ver = elink_848xx_format_ver,
11018 .hw_reset = elink_8481_hw_reset,
11019 .set_link_led = elink_848xx_set_link_led,
11020 .phy_specific_func = NULL
11023 static const struct elink_phy phy_84823 = {
11024 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84823,
11027 .flags = (ELINK_FLAGS_FAN_FAILURE_DET_REQ |
11028 ELINK_FLAGS_REARM_LATCH_SIGNAL | ELINK_FLAGS_TX_ERROR_CHECK),
11029 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11030 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11032 .supported = (ELINK_SUPPORTED_10baseT_Half |
11033 ELINK_SUPPORTED_10baseT_Full |
11034 ELINK_SUPPORTED_100baseT_Half |
11035 ELINK_SUPPORTED_100baseT_Full |
11036 ELINK_SUPPORTED_1000baseT_Full |
11037 ELINK_SUPPORTED_10000baseT_Full |
11038 ELINK_SUPPORTED_TP |
11039 ELINK_SUPPORTED_Autoneg |
11040 ELINK_SUPPORTED_Pause | ELINK_SUPPORTED_Asym_Pause),
11041 .media_type = ELINK_ETH_PHY_BASE_T,
11043 .req_flow_ctrl = 0,
11044 .req_line_speed = 0,
11045 .speed_cap_mask = 0,
11048 .config_init = elink_848x3_config_init,
11049 .read_status = elink_848xx_read_status,
11050 .link_reset = elink_848x3_link_reset,
11051 .config_loopback = NULL,
11052 .format_fw_ver = elink_848xx_format_ver,
11054 .set_link_led = elink_848xx_set_link_led,
11055 .phy_specific_func = elink_848xx_specific_func
11058 static const struct elink_phy phy_84833 = {
11059 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84833,
11062 .flags = (ELINK_FLAGS_FAN_FAILURE_DET_REQ |
11063 ELINK_FLAGS_REARM_LATCH_SIGNAL |
11064 ELINK_FLAGS_TX_ERROR_CHECK | ELINK_FLAGS_TEMPERATURE),
11065 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11066 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11068 .supported = (ELINK_SUPPORTED_100baseT_Half |
11069 ELINK_SUPPORTED_100baseT_Full |
11070 ELINK_SUPPORTED_1000baseT_Full |
11071 ELINK_SUPPORTED_10000baseT_Full |
11072 ELINK_SUPPORTED_TP |
11073 ELINK_SUPPORTED_Autoneg |
11074 ELINK_SUPPORTED_Pause | ELINK_SUPPORTED_Asym_Pause),
11075 .media_type = ELINK_ETH_PHY_BASE_T,
11077 .req_flow_ctrl = 0,
11078 .req_line_speed = 0,
11079 .speed_cap_mask = 0,
11082 .config_init = elink_848x3_config_init,
11083 .read_status = elink_848xx_read_status,
11084 .link_reset = elink_848x3_link_reset,
11085 .config_loopback = NULL,
11086 .format_fw_ver = elink_848xx_format_ver,
11087 .hw_reset = elink_84833_hw_reset_phy,
11088 .set_link_led = elink_848xx_set_link_led,
11089 .phy_specific_func = elink_848xx_specific_func
11092 static const struct elink_phy phy_84834 = {
11093 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84834,
11096 .flags = ELINK_FLAGS_FAN_FAILURE_DET_REQ |
11097 ELINK_FLAGS_REARM_LATCH_SIGNAL,
11098 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11099 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11101 .supported = (ELINK_SUPPORTED_100baseT_Half |
11102 ELINK_SUPPORTED_100baseT_Full |
11103 ELINK_SUPPORTED_1000baseT_Full |
11104 ELINK_SUPPORTED_10000baseT_Full |
11105 ELINK_SUPPORTED_TP |
11106 ELINK_SUPPORTED_Autoneg |
11107 ELINK_SUPPORTED_Pause | ELINK_SUPPORTED_Asym_Pause),
11108 .media_type = ELINK_ETH_PHY_BASE_T,
11110 .req_flow_ctrl = 0,
11111 .req_line_speed = 0,
11112 .speed_cap_mask = 0,
11115 .config_init = elink_848x3_config_init,
11116 .read_status = elink_848xx_read_status,
11117 .link_reset = elink_848x3_link_reset,
11118 .config_loopback = NULL,
11119 .format_fw_ver = elink_848xx_format_ver,
11120 .hw_reset = elink_84833_hw_reset_phy,
11121 .set_link_led = elink_848xx_set_link_led,
11122 .phy_specific_func = elink_848xx_specific_func
11125 static const struct elink_phy phy_54618se = {
11126 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X54618SE,
11129 .flags = ELINK_FLAGS_INIT_XGXS_FIRST,
11130 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11131 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11133 .supported = (ELINK_SUPPORTED_10baseT_Half |
11134 ELINK_SUPPORTED_10baseT_Full |
11135 ELINK_SUPPORTED_100baseT_Half |
11136 ELINK_SUPPORTED_100baseT_Full |
11137 ELINK_SUPPORTED_1000baseT_Full |
11138 ELINK_SUPPORTED_TP |
11139 ELINK_SUPPORTED_Autoneg |
11140 ELINK_SUPPORTED_Pause | ELINK_SUPPORTED_Asym_Pause),
11141 .media_type = ELINK_ETH_PHY_BASE_T,
11143 .req_flow_ctrl = 0,
11144 .req_line_speed = 0,
11145 .speed_cap_mask = 0,
11146 /* req_duplex = */ 0,
11148 .config_init = elink_54618se_config_init,
11149 .read_status = elink_54618se_read_status,
11150 .link_reset = elink_54618se_link_reset,
11151 .config_loopback = elink_54618se_config_loopback,
11152 .format_fw_ver = NULL,
11154 .set_link_led = elink_5461x_set_link_led,
11155 .phy_specific_func = elink_54618se_specific_func
11158 /*****************************************************************/
11160 /* Populate the phy according. Main function: elink_populate_phy */
11162 /*****************************************************************/
11164 static void elink_populate_preemphasis(struct bnx2x_softc *sc,
11165 uint32_t shmem_base,
11166 struct elink_phy *phy, uint8_t port,
11169 /* Get the 4 lanes xgxs config rx and tx */
11170 uint32_t rx = 0, tx = 0, i;
11171 for (i = 0; i < 2; i++) {
11172 /* INT_PHY and ELINK_EXT_PHY1 share the same value location in
11173 * the shmem. When num_phys is greater than 1, than this value
11174 * applies only to ELINK_EXT_PHY1
11176 if (phy_index == ELINK_INT_PHY || phy_index == ELINK_EXT_PHY1) {
11177 rx = REG_RD(sc, shmem_base +
11178 offsetof(struct shmem_region,
11179 dev_info.port_hw_config[port].
11180 xgxs_config_rx[i << 1]));
11182 tx = REG_RD(sc, shmem_base +
11183 offsetof(struct shmem_region,
11184 dev_info.port_hw_config[port].
11185 xgxs_config_tx[i << 1]));
11187 rx = REG_RD(sc, shmem_base +
11188 offsetof(struct shmem_region,
11189 dev_info.port_hw_config[port].
11190 xgxs_config2_rx[i << 1]));
11192 tx = REG_RD(sc, shmem_base +
11193 offsetof(struct shmem_region,
11194 dev_info.port_hw_config[port].
11195 xgxs_config2_rx[i << 1]));
11198 phy->rx_preemphasis[i << 1] = ((rx >> 16) & 0xffff);
11199 phy->rx_preemphasis[(i << 1) + 1] = (rx & 0xffff);
11201 phy->tx_preemphasis[i << 1] = ((tx >> 16) & 0xffff);
11202 phy->tx_preemphasis[(i << 1) + 1] = (tx & 0xffff);
11206 static uint32_t elink_get_ext_phy_config(struct bnx2x_softc *sc,
11207 uint32_t shmem_base, uint8_t phy_index,
11210 uint32_t ext_phy_config = 0;
11211 switch (phy_index) {
11212 case ELINK_EXT_PHY1:
11213 ext_phy_config = REG_RD(sc, shmem_base +
11214 offsetof(struct shmem_region,
11215 dev_info.port_hw_config[port].
11216 external_phy_config));
11218 case ELINK_EXT_PHY2:
11219 ext_phy_config = REG_RD(sc, shmem_base +
11220 offsetof(struct shmem_region,
11221 dev_info.port_hw_config[port].
11222 external_phy_config2));
11225 PMD_DRV_LOG(DEBUG, sc, "Invalid phy_index %d", phy_index);
11226 return ELINK_STATUS_ERROR;
11229 return ext_phy_config;
11232 static elink_status_t elink_populate_int_phy(struct bnx2x_softc *sc,
11233 uint32_t shmem_base, uint8_t port,
11234 struct elink_phy *phy)
11237 __rte_unused uint32_t chip_id;
11238 uint32_t switch_cfg = (REG_RD(sc, shmem_base +
11239 offsetof(struct shmem_region,
11241 port_feature_config[port].
11243 PORT_FEATURE_CONNECTED_SWITCH_MASK);
11245 (REG_RD(sc, MISC_REG_CHIP_NUM) << 16) |
11246 ((REG_RD(sc, MISC_REG_CHIP_REV) & 0xf) << 12);
11248 PMD_DRV_LOG(DEBUG, sc, ":chip_id = 0x%x", chip_id);
11249 if (USES_WARPCORE(sc)) {
11250 uint32_t serdes_net_if;
11251 phy_addr = REG_RD(sc, MISC_REG_WC0_CTRL_PHY_ADDR);
11252 *phy = phy_warpcore;
11253 if (REG_RD(sc, MISC_REG_PORT4MODE_EN_OVWR) == 0x3)
11254 phy->flags |= ELINK_FLAGS_4_PORT_MODE;
11256 phy->flags &= ~ELINK_FLAGS_4_PORT_MODE;
11257 /* Check Dual mode */
11258 serdes_net_if = (REG_RD(sc, shmem_base +
11259 offsetof(struct shmem_region,
11260 dev_info.port_hw_config[port].
11262 PORT_HW_CFG_NET_SERDES_IF_MASK);
11263 /* Set the appropriate supported and flags indications per
11264 * interface type of the chip
11266 switch (serdes_net_if) {
11267 case PORT_HW_CFG_NET_SERDES_IF_SGMII:
11268 phy->supported &= (ELINK_SUPPORTED_10baseT_Half |
11269 ELINK_SUPPORTED_10baseT_Full |
11270 ELINK_SUPPORTED_100baseT_Half |
11271 ELINK_SUPPORTED_100baseT_Full |
11272 ELINK_SUPPORTED_1000baseT_Full |
11273 ELINK_SUPPORTED_FIBRE |
11274 ELINK_SUPPORTED_Autoneg |
11275 ELINK_SUPPORTED_Pause |
11276 ELINK_SUPPORTED_Asym_Pause);
11277 phy->media_type = ELINK_ETH_PHY_BASE_T;
11279 case PORT_HW_CFG_NET_SERDES_IF_XFI:
11280 phy->supported &= (ELINK_SUPPORTED_1000baseT_Full |
11281 ELINK_SUPPORTED_10000baseT_Full |
11282 ELINK_SUPPORTED_FIBRE |
11283 ELINK_SUPPORTED_Pause |
11284 ELINK_SUPPORTED_Asym_Pause);
11285 phy->media_type = ELINK_ETH_PHY_XFP_FIBER;
11287 case PORT_HW_CFG_NET_SERDES_IF_SFI:
11288 phy->supported &= (ELINK_SUPPORTED_1000baseT_Full |
11289 ELINK_SUPPORTED_10000baseT_Full |
11290 ELINK_SUPPORTED_FIBRE |
11291 ELINK_SUPPORTED_Pause |
11292 ELINK_SUPPORTED_Asym_Pause);
11293 phy->media_type = ELINK_ETH_PHY_SFPP_10G_FIBER;
11295 case PORT_HW_CFG_NET_SERDES_IF_KR:
11296 phy->media_type = ELINK_ETH_PHY_KR;
11297 phy->supported &= (ELINK_SUPPORTED_1000baseT_Full |
11298 ELINK_SUPPORTED_10000baseT_Full |
11299 ELINK_SUPPORTED_FIBRE |
11300 ELINK_SUPPORTED_Autoneg |
11301 ELINK_SUPPORTED_Pause |
11302 ELINK_SUPPORTED_Asym_Pause);
11304 case PORT_HW_CFG_NET_SERDES_IF_DXGXS:
11305 phy->media_type = ELINK_ETH_PHY_KR;
11306 phy->flags |= ELINK_FLAGS_WC_DUAL_MODE;
11307 phy->supported &= (ELINK_SUPPORTED_20000baseMLD2_Full |
11308 ELINK_SUPPORTED_FIBRE |
11309 ELINK_SUPPORTED_Pause |
11310 ELINK_SUPPORTED_Asym_Pause);
11312 case PORT_HW_CFG_NET_SERDES_IF_KR2:
11313 phy->media_type = ELINK_ETH_PHY_KR;
11314 phy->flags |= ELINK_FLAGS_WC_DUAL_MODE;
11315 phy->supported &= (ELINK_SUPPORTED_20000baseKR2_Full |
11316 ELINK_SUPPORTED_10000baseT_Full |
11317 ELINK_SUPPORTED_1000baseT_Full |
11318 ELINK_SUPPORTED_Autoneg |
11319 ELINK_SUPPORTED_FIBRE |
11320 ELINK_SUPPORTED_Pause |
11321 ELINK_SUPPORTED_Asym_Pause);
11322 phy->flags &= ~ELINK_FLAGS_TX_ERROR_CHECK;
11325 PMD_DRV_LOG(DEBUG, sc, "Unknown WC interface type 0x%x",
11330 /* Enable MDC/MDIO work-around for E3 A0 since free running MDC
11331 * was not set as expected. For B0, ECO will be enabled so there
11332 * won't be an issue there
11334 if (CHIP_REV(sc) == CHIP_REV_Ax)
11335 phy->flags |= ELINK_FLAGS_MDC_MDIO_WA;
11337 phy->flags |= ELINK_FLAGS_MDC_MDIO_WA_B0;
11339 switch (switch_cfg) {
11340 case ELINK_SWITCH_CFG_1G:
11341 phy_addr = REG_RD(sc,
11342 NIG_REG_SERDES0_CTRL_PHY_ADDR +
11346 case ELINK_SWITCH_CFG_10G:
11347 phy_addr = REG_RD(sc,
11348 NIG_REG_XGXS0_CTRL_PHY_ADDR +
11353 PMD_DRV_LOG(DEBUG, sc, "Invalid switch_cfg");
11354 return ELINK_STATUS_ERROR;
11357 phy->addr = (uint8_t) phy_addr;
11358 phy->mdio_ctrl = elink_get_emac_base(sc,
11359 SHARED_HW_CFG_MDC_MDIO_ACCESS1_BOTH,
11361 if (CHIP_IS_E2(sc))
11362 phy->def_md_devad = ELINK_E2_DEFAULT_PHY_DEV_ADDR;
11364 phy->def_md_devad = ELINK_DEFAULT_PHY_DEV_ADDR;
11366 PMD_DRV_LOG(DEBUG, sc, "Internal phy port=%d, addr=0x%x, mdio_ctl=0x%x",
11367 port, phy->addr, phy->mdio_ctrl);
11369 elink_populate_preemphasis(sc, shmem_base, phy, port, ELINK_INT_PHY);
11370 return ELINK_STATUS_OK;
11373 static elink_status_t elink_populate_ext_phy(struct bnx2x_softc *sc,
11375 uint32_t shmem_base,
11376 uint32_t shmem2_base,
11378 struct elink_phy *phy)
11380 uint32_t ext_phy_config, phy_type, config2;
11381 uint32_t mdc_mdio_access = SHARED_HW_CFG_MDC_MDIO_ACCESS1_BOTH;
11382 ext_phy_config = elink_get_ext_phy_config(sc, shmem_base,
11384 phy_type = ELINK_XGXS_EXT_PHY_TYPE(ext_phy_config);
11385 /* Select the phy type */
11386 switch (phy_type) {
11387 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X8073:
11388 mdc_mdio_access = SHARED_HW_CFG_MDC_MDIO_ACCESS1_SWAPPED;
11391 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X8705:
11394 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X8706:
11397 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X8726:
11398 mdc_mdio_access = SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC1;
11401 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X8727_NOC:
11402 /* BNX2X8727_NOC => BNX2X8727 no over current */
11403 mdc_mdio_access = SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC1;
11405 phy->flags |= ELINK_FLAGS_NOC;
11407 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X8722:
11408 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X8727:
11409 mdc_mdio_access = SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC1;
11412 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X8481:
11415 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84823:
11418 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84833:
11421 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84834:
11424 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X54616:
11425 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X54618SE:
11426 *phy = phy_54618se;
11427 if (phy_type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X54618SE)
11428 phy->flags |= ELINK_FLAGS_EEE;
11430 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101:
11433 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE:
11435 return ELINK_STATUS_ERROR;
11438 /* In case external PHY wasn't found */
11439 if ((phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) &&
11440 (phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN))
11441 return ELINK_STATUS_ERROR;
11442 return ELINK_STATUS_OK;
11445 phy->addr = ELINK_XGXS_EXT_PHY_ADDR(ext_phy_config);
11446 elink_populate_preemphasis(sc, shmem_base, phy, port, phy_index);
11448 /* The shmem address of the phy version is located on different
11449 * structures. In case this structure is too old, do not set
11452 config2 = REG_RD(sc, shmem_base + offsetof(struct shmem_region,
11453 dev_info.shared_hw_config.
11455 if (phy_index == ELINK_EXT_PHY1) {
11456 phy->ver_addr = shmem_base + offsetof(struct shmem_region,
11458 ext_phy_fw_version);
11460 /* Check specific mdc mdio settings */
11461 if (config2 & SHARED_HW_CFG_MDC_MDIO_ACCESS1_MASK)
11462 mdc_mdio_access = config2 &
11463 SHARED_HW_CFG_MDC_MDIO_ACCESS1_MASK;
11465 uint32_t size = REG_RD(sc, shmem2_base);
11467 if (size > offsetof(struct shmem2_region, ext_phy_fw_version2)) {
11468 phy->ver_addr = shmem2_base +
11469 offsetof(struct shmem2_region,
11470 ext_phy_fw_version2[port]);
11472 /* Check specific mdc mdio settings */
11473 if (config2 & SHARED_HW_CFG_MDC_MDIO_ACCESS2_MASK)
11474 mdc_mdio_access = (config2 &
11475 SHARED_HW_CFG_MDC_MDIO_ACCESS2_MASK)
11476 >> (SHARED_HW_CFG_MDC_MDIO_ACCESS2_SHIFT -
11477 SHARED_HW_CFG_MDC_MDIO_ACCESS1_SHIFT);
11479 phy->mdio_ctrl = elink_get_emac_base(sc, mdc_mdio_access, port);
11481 if (((phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84833) ||
11482 (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84834)) &&
11484 /* Remove 100Mb link supported for BNX2X84833/4 when phy fw
11485 * version lower than or equal to 1.39
11487 uint32_t raw_ver = REG_RD(sc, phy->ver_addr);
11488 if (((raw_ver & 0x7F) <= 39) && (((raw_ver & 0xF80) >> 7) <= 1))
11489 phy->supported &= ~(ELINK_SUPPORTED_100baseT_Half |
11490 ELINK_SUPPORTED_100baseT_Full);
11493 PMD_DRV_LOG(DEBUG, sc, "phy_type 0x%x port %d found in index %d",
11494 phy_type, port, phy_index);
11495 PMD_DRV_LOG(DEBUG, sc, " addr=0x%x, mdio_ctl=0x%x",
11496 phy->addr, phy->mdio_ctrl);
11497 return ELINK_STATUS_OK;
11500 static elink_status_t elink_populate_phy(struct bnx2x_softc *sc,
11501 uint8_t phy_index, uint32_t shmem_base,
11502 uint32_t shmem2_base, uint8_t port,
11503 struct elink_phy *phy)
11505 elink_status_t status = ELINK_STATUS_OK;
11506 phy->type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN;
11507 if (phy_index == ELINK_INT_PHY)
11508 return elink_populate_int_phy(sc, shmem_base, port, phy);
11509 status = elink_populate_ext_phy(sc, phy_index, shmem_base, shmem2_base,
11514 static void elink_phy_def_cfg(struct elink_params *params,
11515 struct elink_phy *phy, uint8_t phy_index)
11517 struct bnx2x_softc *sc = params->sc;
11518 uint32_t link_config;
11519 /* Populate the default phy configuration for MF mode */
11520 if (phy_index == ELINK_EXT_PHY2) {
11521 link_config = REG_RD(sc, params->shmem_base +
11522 offsetof(struct shmem_region,
11523 dev_info.port_feature_config
11524 [params->port].link_config2));
11525 phy->speed_cap_mask =
11527 params->shmem_base + offsetof(struct shmem_region,
11528 dev_info.port_hw_config
11530 speed_capability_mask2));
11532 link_config = REG_RD(sc, params->shmem_base +
11533 offsetof(struct shmem_region,
11534 dev_info.port_feature_config
11535 [params->port].link_config));
11536 phy->speed_cap_mask =
11538 params->shmem_base + offsetof(struct shmem_region,
11539 dev_info.port_hw_config
11541 speed_capability_mask));
11544 PMD_DRV_LOG(DEBUG, sc,
11545 "Default config phy idx %x cfg 0x%x speed_cap_mask 0x%x",
11546 phy_index, link_config, phy->speed_cap_mask);
11548 phy->req_duplex = DUPLEX_FULL;
11549 switch (link_config & PORT_FEATURE_LINK_SPEED_MASK) {
11550 case PORT_FEATURE_LINK_SPEED_10M_HALF:
11551 phy->req_duplex = DUPLEX_HALF;
11552 case PORT_FEATURE_LINK_SPEED_10M_FULL:
11553 phy->req_line_speed = ELINK_SPEED_10;
11555 case PORT_FEATURE_LINK_SPEED_100M_HALF:
11556 phy->req_duplex = DUPLEX_HALF;
11557 case PORT_FEATURE_LINK_SPEED_100M_FULL:
11558 phy->req_line_speed = ELINK_SPEED_100;
11560 case PORT_FEATURE_LINK_SPEED_1G:
11561 phy->req_line_speed = ELINK_SPEED_1000;
11563 case PORT_FEATURE_LINK_SPEED_2_5G:
11564 phy->req_line_speed = ELINK_SPEED_2500;
11566 case PORT_FEATURE_LINK_SPEED_10G_CX4:
11567 phy->req_line_speed = ELINK_SPEED_10000;
11570 phy->req_line_speed = ELINK_SPEED_AUTO_NEG;
11574 switch (link_config & PORT_FEATURE_FLOW_CONTROL_MASK) {
11575 case PORT_FEATURE_FLOW_CONTROL_AUTO:
11576 phy->req_flow_ctrl = ELINK_FLOW_CTRL_AUTO;
11578 case PORT_FEATURE_FLOW_CONTROL_TX:
11579 phy->req_flow_ctrl = ELINK_FLOW_CTRL_TX;
11581 case PORT_FEATURE_FLOW_CONTROL_RX:
11582 phy->req_flow_ctrl = ELINK_FLOW_CTRL_RX;
11584 case PORT_FEATURE_FLOW_CONTROL_BOTH:
11585 phy->req_flow_ctrl = ELINK_FLOW_CTRL_BOTH;
11588 phy->req_flow_ctrl = ELINK_FLOW_CTRL_NONE;
11593 uint32_t elink_phy_selection(struct elink_params *params)
11595 uint32_t phy_config_swapped, prio_cfg;
11596 uint32_t return_cfg = PORT_HW_CFG_PHY_SELECTION_HARDWARE_DEFAULT;
11598 phy_config_swapped = params->multi_phy_config &
11599 PORT_HW_CFG_PHY_SWAPPED_ENABLED;
11601 prio_cfg = params->multi_phy_config & PORT_HW_CFG_PHY_SELECTION_MASK;
11603 if (phy_config_swapped) {
11604 switch (prio_cfg) {
11605 case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY_PRIORITY:
11607 PORT_HW_CFG_PHY_SELECTION_SECOND_PHY_PRIORITY;
11609 case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY_PRIORITY:
11611 PORT_HW_CFG_PHY_SELECTION_FIRST_PHY_PRIORITY;
11613 case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY:
11614 return_cfg = PORT_HW_CFG_PHY_SELECTION_FIRST_PHY;
11616 case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY:
11617 return_cfg = PORT_HW_CFG_PHY_SELECTION_SECOND_PHY;
11621 return_cfg = prio_cfg;
11626 elink_status_t elink_phy_probe(struct elink_params * params)
11628 uint8_t phy_index, actual_phy_idx;
11629 uint32_t phy_config_swapped, sync_offset, media_types;
11630 struct bnx2x_softc *sc = params->sc;
11631 struct elink_phy *phy;
11632 params->num_phys = 0;
11633 PMD_DRV_LOG(DEBUG, sc, "Begin phy probe");
11635 phy_config_swapped = params->multi_phy_config &
11636 PORT_HW_CFG_PHY_SWAPPED_ENABLED;
11638 for (phy_index = ELINK_INT_PHY; phy_index < ELINK_MAX_PHYS; phy_index++) {
11639 actual_phy_idx = phy_index;
11640 if (phy_config_swapped) {
11641 if (phy_index == ELINK_EXT_PHY1)
11642 actual_phy_idx = ELINK_EXT_PHY2;
11643 else if (phy_index == ELINK_EXT_PHY2)
11644 actual_phy_idx = ELINK_EXT_PHY1;
11646 PMD_DRV_LOG(DEBUG, sc, "phy_config_swapped %x, phy_index %x,"
11647 " actual_phy_idx %x", phy_config_swapped,
11648 phy_index, actual_phy_idx);
11649 phy = ¶ms->phy[actual_phy_idx];
11650 if (elink_populate_phy(sc, phy_index, params->shmem_base,
11651 params->shmem2_base, params->port,
11652 phy) != ELINK_STATUS_OK) {
11653 params->num_phys = 0;
11654 PMD_DRV_LOG(DEBUG, sc, "phy probe failed in phy index %d",
11656 for (phy_index = ELINK_INT_PHY;
11657 phy_index < ELINK_MAX_PHYS; phy_index++)
11659 return ELINK_STATUS_ERROR;
11661 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN)
11664 if (params->feature_config_flags &
11665 ELINK_FEATURE_CONFIG_DISABLE_REMOTE_FAULT_DET)
11666 phy->flags &= ~ELINK_FLAGS_TX_ERROR_CHECK;
11668 if (!(params->feature_config_flags &
11669 ELINK_FEATURE_CONFIG_MT_SUPPORT))
11670 phy->flags |= ELINK_FLAGS_MDC_MDIO_WA_G;
11672 sync_offset = params->shmem_base +
11673 offsetof(struct shmem_region,
11674 dev_info.port_hw_config[params->port].media_type);
11675 media_types = REG_RD(sc, sync_offset);
11677 /* Update media type for non-PMF sync only for the first time
11678 * In case the media type changes afterwards, it will be updated
11679 * using the update_status function
11681 if ((media_types & (PORT_HW_CFG_MEDIA_TYPE_PHY0_MASK <<
11682 (PORT_HW_CFG_MEDIA_TYPE_PHY1_SHIFT *
11683 actual_phy_idx))) == 0) {
11684 media_types |= ((phy->media_type &
11685 PORT_HW_CFG_MEDIA_TYPE_PHY0_MASK) <<
11686 (PORT_HW_CFG_MEDIA_TYPE_PHY1_SHIFT *
11689 REG_WR(sc, sync_offset, media_types);
11691 elink_phy_def_cfg(params, phy, phy_index);
11692 params->num_phys++;
11695 PMD_DRV_LOG(DEBUG, sc,
11696 "End phy probe. #phys found %x", params->num_phys);
11697 return ELINK_STATUS_OK;
11700 static void elink_init_bmac_loopback(struct elink_params *params,
11701 struct elink_vars *vars)
11703 struct bnx2x_softc *sc = params->sc;
11705 vars->line_speed = ELINK_SPEED_10000;
11706 vars->duplex = DUPLEX_FULL;
11707 vars->flow_ctrl = ELINK_FLOW_CTRL_NONE;
11708 vars->mac_type = ELINK_MAC_TYPE_BMAC;
11710 vars->phy_flags = PHY_XGXS_FLAG;
11712 elink_xgxs_deassert(params);
11714 /* Set bmac loopback */
11715 elink_bmac_enable(params, vars, 1, 1);
11717 REG_WR(sc, NIG_REG_EGRESS_DRAIN0_MODE + params->port * 4, 0);
11720 static void elink_init_emac_loopback(struct elink_params *params,
11721 struct elink_vars *vars)
11723 struct bnx2x_softc *sc = params->sc;
11725 vars->line_speed = ELINK_SPEED_1000;
11726 vars->duplex = DUPLEX_FULL;
11727 vars->flow_ctrl = ELINK_FLOW_CTRL_NONE;
11728 vars->mac_type = ELINK_MAC_TYPE_EMAC;
11730 vars->phy_flags = PHY_XGXS_FLAG;
11732 elink_xgxs_deassert(params);
11733 /* Set bmac loopback */
11734 elink_emac_enable(params, vars, 1);
11735 elink_emac_program(params, vars);
11736 REG_WR(sc, NIG_REG_EGRESS_DRAIN0_MODE + params->port * 4, 0);
11739 static void elink_init_xmac_loopback(struct elink_params *params,
11740 struct elink_vars *vars)
11742 struct bnx2x_softc *sc = params->sc;
11744 if (!params->req_line_speed[0])
11745 vars->line_speed = ELINK_SPEED_10000;
11747 vars->line_speed = params->req_line_speed[0];
11748 vars->duplex = DUPLEX_FULL;
11749 vars->flow_ctrl = ELINK_FLOW_CTRL_NONE;
11750 vars->mac_type = ELINK_MAC_TYPE_XMAC;
11751 vars->phy_flags = PHY_XGXS_FLAG;
11752 /* Set WC to loopback mode since link is required to provide clock
11753 * to the XMAC in 20G mode
11755 elink_set_aer_mmd(params, ¶ms->phy[0]);
11756 elink_warpcore_reset_lane(sc, ¶ms->phy[0], 0);
11757 params->phy[ELINK_INT_PHY].config_loopback(¶ms->phy[ELINK_INT_PHY],
11760 elink_xmac_enable(params, vars, 1);
11761 REG_WR(sc, NIG_REG_EGRESS_DRAIN0_MODE + params->port * 4, 0);
11764 static void elink_init_umac_loopback(struct elink_params *params,
11765 struct elink_vars *vars)
11767 struct bnx2x_softc *sc = params->sc;
11769 vars->line_speed = ELINK_SPEED_1000;
11770 vars->duplex = DUPLEX_FULL;
11771 vars->flow_ctrl = ELINK_FLOW_CTRL_NONE;
11772 vars->mac_type = ELINK_MAC_TYPE_UMAC;
11773 vars->phy_flags = PHY_XGXS_FLAG;
11774 elink_umac_enable(params, vars, 1);
11776 REG_WR(sc, NIG_REG_EGRESS_DRAIN0_MODE + params->port * 4, 0);
11779 static void elink_init_xgxs_loopback(struct elink_params *params,
11780 struct elink_vars *vars)
11782 struct bnx2x_softc *sc = params->sc;
11783 struct elink_phy *int_phy = ¶ms->phy[ELINK_INT_PHY];
11785 vars->flow_ctrl = ELINK_FLOW_CTRL_NONE;
11786 vars->duplex = DUPLEX_FULL;
11787 if (params->req_line_speed[0] == ELINK_SPEED_1000)
11788 vars->line_speed = ELINK_SPEED_1000;
11789 else if ((params->req_line_speed[0] == ELINK_SPEED_20000) ||
11790 (int_phy->flags & ELINK_FLAGS_WC_DUAL_MODE))
11791 vars->line_speed = ELINK_SPEED_20000;
11793 vars->line_speed = ELINK_SPEED_10000;
11795 if (!USES_WARPCORE(sc))
11796 elink_xgxs_deassert(params);
11797 elink_link_initialize(params, vars);
11799 if (params->req_line_speed[0] == ELINK_SPEED_1000) {
11800 if (USES_WARPCORE(sc))
11801 elink_umac_enable(params, vars, 0);
11803 elink_emac_program(params, vars);
11804 elink_emac_enable(params, vars, 0);
11807 if (USES_WARPCORE(sc))
11808 elink_xmac_enable(params, vars, 0);
11810 elink_bmac_enable(params, vars, 0, 1);
11813 if (params->loopback_mode == ELINK_LOOPBACK_XGXS) {
11814 /* Set 10G XGXS loopback */
11815 int_phy->config_loopback(int_phy, params);
11817 /* Set external phy loopback */
11819 for (phy_index = ELINK_EXT_PHY1;
11820 phy_index < params->num_phys; phy_index++)
11821 if (params->phy[phy_index].config_loopback)
11822 params->phy[phy_index].config_loopback(¶ms->
11827 REG_WR(sc, NIG_REG_EGRESS_DRAIN0_MODE + params->port * 4, 0);
11829 elink_set_led(params, vars, ELINK_LED_MODE_OPER, vars->line_speed);
11832 void elink_set_rx_filter(struct elink_params *params, uint8_t en)
11834 struct bnx2x_softc *sc = params->sc;
11835 uint8_t val = en * 0x1F;
11837 /* Open / close the gate between the NIG and the BRB */
11838 if (!CHIP_IS_E1x(sc))
11840 REG_WR(sc, NIG_REG_LLH0_BRB1_DRV_MASK + params->port * 4, val);
11842 REG_WR(sc, NIG_REG_LLH0_BRB1_DRV_MASK_MF + params->port * 4, en * 0x3);
11844 REG_WR(sc, (params->port ? NIG_REG_LLH1_BRB1_NOT_MCP :
11845 NIG_REG_LLH0_BRB1_NOT_MCP), en);
11848 static elink_status_t elink_avoid_link_flap(struct elink_params *params,
11849 struct elink_vars *vars)
11852 uint32_t dont_clear_stat, lfa_sts;
11853 struct bnx2x_softc *sc = params->sc;
11855 /* Sync the link parameters */
11856 elink_link_status_update(params, vars);
11859 * The module verification was already done by previous link owner,
11860 * so this call is meant only to get warning message
11863 for (phy_idx = ELINK_INT_PHY; phy_idx < params->num_phys; phy_idx++) {
11864 struct elink_phy *phy = ¶ms->phy[phy_idx];
11865 if (phy->phy_specific_func) {
11866 PMD_DRV_LOG(DEBUG, sc, "Calling PHY specific func");
11867 phy->phy_specific_func(phy, params, ELINK_PHY_INIT);
11869 if ((phy->media_type == ELINK_ETH_PHY_SFPP_10G_FIBER) ||
11870 (phy->media_type == ELINK_ETH_PHY_SFP_1G_FIBER) ||
11871 (phy->media_type == ELINK_ETH_PHY_DA_TWINAX))
11872 elink_verify_sfp_module(phy, params);
11874 lfa_sts = REG_RD(sc, params->lfa_base +
11875 offsetof(struct shmem_lfa, lfa_sts));
11877 dont_clear_stat = lfa_sts & SHMEM_LFA_DONT_CLEAR_STAT;
11879 /* Re-enable the NIG/MAC */
11880 if (CHIP_IS_E3(sc)) {
11881 if (!dont_clear_stat) {
11882 REG_WR(sc, GRCBASE_MISC +
11883 MISC_REGISTERS_RESET_REG_2_CLEAR,
11884 (MISC_REGISTERS_RESET_REG_2_MSTAT0 <<
11886 REG_WR(sc, GRCBASE_MISC +
11887 MISC_REGISTERS_RESET_REG_2_SET,
11888 (MISC_REGISTERS_RESET_REG_2_MSTAT0 <<
11891 if (vars->line_speed < ELINK_SPEED_10000)
11892 elink_umac_enable(params, vars, 0);
11894 elink_xmac_enable(params, vars, 0);
11896 if (vars->line_speed < ELINK_SPEED_10000)
11897 elink_emac_enable(params, vars, 0);
11899 elink_bmac_enable(params, vars, 0, !dont_clear_stat);
11902 /* Increment LFA count */
11903 lfa_sts = ((lfa_sts & ~LINK_FLAP_AVOIDANCE_COUNT_MASK) |
11904 (((((lfa_sts & LINK_FLAP_AVOIDANCE_COUNT_MASK) >>
11905 LINK_FLAP_AVOIDANCE_COUNT_OFFSET) + 1) & 0xff)
11906 << LINK_FLAP_AVOIDANCE_COUNT_OFFSET));
11907 /* Clear link flap reason */
11908 lfa_sts &= ~LFA_LINK_FLAP_REASON_MASK;
11910 REG_WR(sc, params->lfa_base +
11911 offsetof(struct shmem_lfa, lfa_sts), lfa_sts);
11913 /* Disable NIG DRAIN */
11914 REG_WR(sc, NIG_REG_EGRESS_DRAIN0_MODE + params->port * 4, 0);
11916 /* Enable interrupts */
11917 elink_link_int_enable(params);
11918 return ELINK_STATUS_OK;
11921 static void elink_cannot_avoid_link_flap(struct elink_params *params,
11922 struct elink_vars *vars,
11925 uint32_t lfa_sts, cfg_idx, tmp_val;
11926 struct bnx2x_softc *sc = params->sc;
11928 elink_link_reset(params, vars, 1);
11930 if (!params->lfa_base)
11932 /* Store the new link parameters */
11933 REG_WR(sc, params->lfa_base +
11934 offsetof(struct shmem_lfa, req_duplex),
11935 params->req_duplex[0] | (params->req_duplex[1] << 16));
11937 REG_WR(sc, params->lfa_base +
11938 offsetof(struct shmem_lfa, req_flow_ctrl),
11939 params->req_flow_ctrl[0] | (params->req_flow_ctrl[1] << 16));
11941 REG_WR(sc, params->lfa_base +
11942 offsetof(struct shmem_lfa, req_line_speed),
11943 params->req_line_speed[0] | (params->req_line_speed[1] << 16));
11945 for (cfg_idx = 0; cfg_idx < SHMEM_LINK_CONFIG_SIZE; cfg_idx++) {
11946 REG_WR(sc, params->lfa_base +
11947 offsetof(struct shmem_lfa,
11948 speed_cap_mask[cfg_idx]),
11949 params->speed_cap_mask[cfg_idx]);
11952 tmp_val = REG_RD(sc, params->lfa_base +
11953 offsetof(struct shmem_lfa, additional_config));
11954 tmp_val &= ~REQ_FC_AUTO_ADV_MASK;
11955 tmp_val |= params->req_fc_auto_adv;
11957 REG_WR(sc, params->lfa_base +
11958 offsetof(struct shmem_lfa, additional_config), tmp_val);
11960 lfa_sts = REG_RD(sc, params->lfa_base +
11961 offsetof(struct shmem_lfa, lfa_sts));
11963 /* Clear the "Don't Clear Statistics" bit, and set reason */
11964 lfa_sts &= ~SHMEM_LFA_DONT_CLEAR_STAT;
11966 /* Set link flap reason */
11967 lfa_sts &= ~LFA_LINK_FLAP_REASON_MASK;
11968 lfa_sts |= ((lfa_status & LFA_LINK_FLAP_REASON_MASK) <<
11969 LFA_LINK_FLAP_REASON_OFFSET);
11971 /* Increment link flap counter */
11972 lfa_sts = ((lfa_sts & ~LINK_FLAP_COUNT_MASK) |
11973 (((((lfa_sts & LINK_FLAP_COUNT_MASK) >>
11974 LINK_FLAP_COUNT_OFFSET) + 1) & 0xff)
11975 << LINK_FLAP_COUNT_OFFSET));
11976 REG_WR(sc, params->lfa_base +
11977 offsetof(struct shmem_lfa, lfa_sts), lfa_sts);
11978 /* Proceed with regular link initialization */
11981 elink_status_t elink_phy_init(struct elink_params *params,
11982 struct elink_vars *vars)
11985 struct bnx2x_softc *sc = params->sc;
11986 PMD_DRV_LOG(DEBUG, sc, "Phy Initialization started");
11987 PMD_DRV_LOG(DEBUG, sc, "(1) req_speed %d, req_flowctrl %d",
11988 params->req_line_speed[0], params->req_flow_ctrl[0]);
11989 PMD_DRV_LOG(DEBUG, sc, "(2) req_speed %d, req_flowctrl %d",
11990 params->req_line_speed[1], params->req_flow_ctrl[1]);
11991 PMD_DRV_LOG(DEBUG, sc,
11992 "req_adv_flow_ctrl 0x%x", params->req_fc_auto_adv);
11993 vars->link_status = 0;
11994 vars->phy_link_up = 0;
11996 vars->line_speed = 0;
11997 vars->duplex = DUPLEX_FULL;
11998 vars->flow_ctrl = ELINK_FLOW_CTRL_NONE;
11999 vars->mac_type = ELINK_MAC_TYPE_NONE;
12000 vars->phy_flags = 0;
12001 vars->check_kr2_recovery_cnt = 0;
12002 params->link_flags = ELINK_PHY_INITIALIZED;
12003 /* Driver opens NIG-BRB filters */
12004 elink_set_rx_filter(params, 1);
12005 /* Check if link flap can be avoided */
12006 lfa_status = elink_check_lfa(params);
12008 if (lfa_status == 0) {
12009 PMD_DRV_LOG(DEBUG, sc,
12010 "Link Flap Avoidance in progress");
12011 return elink_avoid_link_flap(params, vars);
12014 PMD_DRV_LOG(DEBUG, sc,
12015 "Cannot avoid link flap lfa_sta=0x%x", lfa_status);
12016 elink_cannot_avoid_link_flap(params, vars, lfa_status);
12018 /* Disable attentions */
12019 elink_bits_dis(sc, NIG_REG_MASK_INTERRUPT_PORT0 + params->port * 4,
12020 (ELINK_NIG_MASK_XGXS0_LINK_STATUS |
12021 ELINK_NIG_MASK_XGXS0_LINK10G |
12022 ELINK_NIG_MASK_SERDES0_LINK_STATUS |
12023 ELINK_NIG_MASK_MI_INT));
12025 elink_emac_init(params);
12027 if (params->feature_config_flags & ELINK_FEATURE_CONFIG_PFC_ENABLED)
12028 vars->link_status |= LINK_STATUS_PFC_ENABLED;
12030 if ((params->num_phys == 0) && !CHIP_REV_IS_SLOW(sc)) {
12031 PMD_DRV_LOG(DEBUG, sc, "No phy found for initialization !!");
12032 return ELINK_STATUS_ERROR;
12034 set_phy_vars(params, vars);
12036 PMD_DRV_LOG(DEBUG, sc, "Num of phys on board: %d", params->num_phys);
12038 switch (params->loopback_mode) {
12039 case ELINK_LOOPBACK_BMAC:
12040 elink_init_bmac_loopback(params, vars);
12042 case ELINK_LOOPBACK_EMAC:
12043 elink_init_emac_loopback(params, vars);
12045 case ELINK_LOOPBACK_XMAC:
12046 elink_init_xmac_loopback(params, vars);
12048 case ELINK_LOOPBACK_UMAC:
12049 elink_init_umac_loopback(params, vars);
12051 case ELINK_LOOPBACK_XGXS:
12052 case ELINK_LOOPBACK_EXT_PHY:
12053 elink_init_xgxs_loopback(params, vars);
12056 if (!CHIP_IS_E3(sc)) {
12057 if (params->switch_cfg == ELINK_SWITCH_CFG_10G)
12058 elink_xgxs_deassert(params);
12060 elink_serdes_deassert(sc, params->port);
12062 elink_link_initialize(params, vars);
12064 elink_link_int_enable(params);
12067 elink_update_mng(params, vars->link_status);
12069 elink_update_mng_eee(params, vars->eee_status);
12070 return ELINK_STATUS_OK;
12073 static elink_status_t elink_link_reset(struct elink_params *params,
12074 struct elink_vars *vars,
12075 uint8_t reset_ext_phy)
12077 struct bnx2x_softc *sc = params->sc;
12078 uint8_t phy_index, port = params->port, clear_latch_ind = 0;
12079 PMD_DRV_LOG(DEBUG, sc, "Resetting the link of port %d", port);
12080 /* Disable attentions */
12081 vars->link_status = 0;
12082 elink_update_mng(params, vars->link_status);
12083 vars->eee_status &= ~(SHMEM_EEE_LP_ADV_STATUS_MASK |
12084 SHMEM_EEE_ACTIVE_BIT);
12085 elink_update_mng_eee(params, vars->eee_status);
12086 elink_bits_dis(sc, NIG_REG_MASK_INTERRUPT_PORT0 + port * 4,
12087 (ELINK_NIG_MASK_XGXS0_LINK_STATUS |
12088 ELINK_NIG_MASK_XGXS0_LINK10G |
12089 ELINK_NIG_MASK_SERDES0_LINK_STATUS |
12090 ELINK_NIG_MASK_MI_INT));
12092 /* Activate nig drain */
12093 REG_WR(sc, NIG_REG_EGRESS_DRAIN0_MODE + port * 4, 1);
12095 /* Disable nig egress interface */
12096 if (!CHIP_IS_E3(sc)) {
12097 REG_WR(sc, NIG_REG_BMAC0_OUT_EN + port * 4, 0);
12098 REG_WR(sc, NIG_REG_EGRESS_EMAC0_OUT_EN + port * 4, 0);
12100 if (!CHIP_IS_E3(sc))
12101 elink_set_bmac_rx(sc, port, 0);
12102 if (CHIP_IS_E3(sc) && !CHIP_REV_IS_FPGA(sc)) {
12103 elink_set_xmac_rxtx(params, 0);
12104 elink_set_umac_rxtx(params, 0);
12107 if (!CHIP_IS_E3(sc))
12108 REG_WR(sc, NIG_REG_NIG_EMAC0_EN + port * 4, 0);
12111 /* The PHY reset is controlled by GPIO 1
12112 * Hold it as vars low
12114 /* Clear link led */
12115 elink_set_mdio_emac_per_phy(sc, params);
12116 elink_set_led(params, vars, ELINK_LED_MODE_OFF, 0);
12118 if (reset_ext_phy && (!CHIP_REV_IS_SLOW(sc))) {
12119 for (phy_index = ELINK_EXT_PHY1; phy_index < params->num_phys;
12121 if (params->phy[phy_index].link_reset) {
12122 elink_set_aer_mmd(params,
12123 ¶ms->phy[phy_index]);
12124 params->phy[phy_index].link_reset(¶ms->
12129 if (params->phy[phy_index].flags &
12130 ELINK_FLAGS_REARM_LATCH_SIGNAL)
12131 clear_latch_ind = 1;
12135 if (clear_latch_ind) {
12136 /* Clear latching indication */
12137 elink_rearm_latch_signal(sc, port, 0);
12138 elink_bits_dis(sc, NIG_REG_LATCH_BC_0 + port * 4,
12139 1 << ELINK_NIG_LATCH_BC_ENABLE_MI_INT);
12141 if (params->phy[ELINK_INT_PHY].link_reset)
12142 params->phy[ELINK_INT_PHY].link_reset(¶ms->
12147 /* Disable nig ingress interface */
12148 if (!CHIP_IS_E3(sc)) {
12150 REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
12151 (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port));
12152 REG_WR(sc, NIG_REG_BMAC0_IN_EN + port * 4, 0);
12153 REG_WR(sc, NIG_REG_EMAC0_IN_EN + port * 4, 0);
12155 uint32_t xmac_base =
12156 (params->port) ? GRCBASE_XMAC1 : GRCBASE_XMAC0;
12157 elink_set_xumac_nig(params, 0, 0);
12158 if (REG_RD(sc, MISC_REG_RESET_REG_2) &
12159 MISC_REGISTERS_RESET_REG_2_XMAC)
12160 REG_WR(sc, xmac_base + XMAC_REG_CTRL,
12161 XMAC_CTRL_REG_SOFT_RESET);
12164 vars->phy_flags = 0;
12165 return ELINK_STATUS_OK;
12168 elink_status_t elink_lfa_reset(struct elink_params * params,
12169 struct elink_vars * vars)
12171 struct bnx2x_softc *sc = params->sc;
12173 vars->phy_flags = 0;
12174 params->link_flags &= ~ELINK_PHY_INITIALIZED;
12175 if (!params->lfa_base)
12176 return elink_link_reset(params, vars, 1);
12178 * Activate NIG drain so that during this time the device won't send
12179 * anything while it is unable to response.
12181 REG_WR(sc, NIG_REG_EGRESS_DRAIN0_MODE + params->port * 4, 1);
12184 * Close gracefully the gate from BMAC to NIG such that no half packets
12187 if (!CHIP_IS_E3(sc))
12188 elink_set_bmac_rx(sc, params->port, 0);
12190 if (CHIP_IS_E3(sc)) {
12191 elink_set_xmac_rxtx(params, 0);
12192 elink_set_umac_rxtx(params, 0);
12194 /* Wait 10ms for the pipe to clean up */
12197 /* Clean the NIG-BRB using the network filters in a way that will
12198 * not cut a packet in the middle.
12200 elink_set_rx_filter(params, 0);
12203 * Re-open the gate between the BMAC and the NIG, after verifying the
12204 * gate to the BRB is closed, otherwise packets may arrive to the
12205 * firmware before driver had initialized it. The target is to achieve
12206 * minimum management protocol down time.
12208 if (!CHIP_IS_E3(sc))
12209 elink_set_bmac_rx(sc, params->port, 1);
12211 if (CHIP_IS_E3(sc)) {
12212 elink_set_xmac_rxtx(params, 1);
12213 elink_set_umac_rxtx(params, 1);
12215 /* Disable NIG drain */
12216 REG_WR(sc, NIG_REG_EGRESS_DRAIN0_MODE + params->port * 4, 0);
12217 return ELINK_STATUS_OK;
12220 /****************************************************************************/
12221 /* Common function */
12222 /****************************************************************************/
12223 static elink_status_t elink_8073_common_init_phy(struct bnx2x_softc *sc,
12224 uint32_t shmem_base_path[],
12225 uint32_t shmem2_base_path[],
12227 __rte_unused uint32_t chip_id)
12229 struct elink_phy phy[PORT_MAX];
12230 struct elink_phy *phy_blk[PORT_MAX];
12233 int8_t port_of_path = 0;
12234 uint32_t swap_val, swap_override;
12235 swap_val = REG_RD(sc, NIG_REG_PORT_SWAP);
12236 swap_override = REG_RD(sc, NIG_REG_STRAP_OVERRIDE);
12237 port ^= (swap_val && swap_override);
12238 elink_ext_phy_hw_reset(sc, port);
12239 /* PART1 - Reset both phys */
12240 for (port = PORT_MAX - 1; port >= PORT_0; port--) {
12241 uint32_t shmem_base, shmem2_base;
12242 /* In E2, same phy is using for port0 of the two paths */
12243 if (CHIP_IS_E1x(sc)) {
12244 shmem_base = shmem_base_path[0];
12245 shmem2_base = shmem2_base_path[0];
12246 port_of_path = port;
12248 shmem_base = shmem_base_path[port];
12249 shmem2_base = shmem2_base_path[port];
12253 /* Extract the ext phy address for the port */
12254 if (elink_populate_phy(sc, phy_index, shmem_base, shmem2_base,
12255 port_of_path, &phy[port]) !=
12257 PMD_DRV_LOG(DEBUG, sc, "populate_phy failed");
12258 return ELINK_STATUS_ERROR;
12260 /* Disable attentions */
12261 elink_bits_dis(sc, NIG_REG_MASK_INTERRUPT_PORT0 +
12263 (ELINK_NIG_MASK_XGXS0_LINK_STATUS |
12264 ELINK_NIG_MASK_XGXS0_LINK10G |
12265 ELINK_NIG_MASK_SERDES0_LINK_STATUS |
12266 ELINK_NIG_MASK_MI_INT));
12268 /* Need to take the phy out of low power mode in order
12269 * to write to access its registers
12271 elink_cb_gpio_write(sc, MISC_REGISTERS_GPIO_2,
12272 MISC_REGISTERS_GPIO_OUTPUT_HIGH, port);
12274 /* Reset the phy */
12275 elink_cl45_write(sc, &phy[port],
12276 MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 1 << 15);
12279 /* Add delay of 150ms after reset */
12282 if (phy[PORT_0].addr & 0x1) {
12283 phy_blk[PORT_0] = &(phy[PORT_1]);
12284 phy_blk[PORT_1] = &(phy[PORT_0]);
12286 phy_blk[PORT_0] = &(phy[PORT_0]);
12287 phy_blk[PORT_1] = &(phy[PORT_1]);
12290 /* PART2 - Download firmware to both phys */
12291 for (port = PORT_MAX - 1; port >= PORT_0; port--) {
12292 if (CHIP_IS_E1x(sc))
12293 port_of_path = port;
12297 PMD_DRV_LOG(DEBUG, sc, "Loading spirom for phy address 0x%x",
12298 phy_blk[port]->addr);
12299 if (elink_8073_8727_external_rom_boot(sc, phy_blk[port],
12301 return ELINK_STATUS_ERROR;
12303 /* Only set bit 10 = 1 (Tx power down) */
12304 elink_cl45_read(sc, phy_blk[port],
12306 MDIO_PMA_REG_TX_POWER_DOWN, &val);
12308 /* Phase1 of TX_POWER_DOWN reset */
12309 elink_cl45_write(sc, phy_blk[port],
12311 MDIO_PMA_REG_TX_POWER_DOWN, (val | 1 << 10));
12314 /* Toggle Transmitter: Power down and then up with 600ms delay
12319 /* PART3 - complete TX_POWER_DOWN process, and set GPIO2 back to low */
12320 for (port = PORT_MAX - 1; port >= PORT_0; port--) {
12321 /* Phase2 of POWER_DOWN_RESET */
12322 /* Release bit 10 (Release Tx power down) */
12323 elink_cl45_read(sc, phy_blk[port],
12325 MDIO_PMA_REG_TX_POWER_DOWN, &val);
12327 elink_cl45_write(sc, phy_blk[port],
12329 MDIO_PMA_REG_TX_POWER_DOWN,
12330 (val & (~(1 << 10))));
12333 /* Read modify write the SPI-ROM version select register */
12334 elink_cl45_read(sc, phy_blk[port],
12336 MDIO_PMA_REG_EDC_FFE_MAIN, &val);
12337 elink_cl45_write(sc, phy_blk[port],
12339 MDIO_PMA_REG_EDC_FFE_MAIN, (val | (1 << 12)));
12341 /* set GPIO2 back to LOW */
12342 elink_cb_gpio_write(sc, MISC_REGISTERS_GPIO_2,
12343 MISC_REGISTERS_GPIO_OUTPUT_LOW, port);
12345 return ELINK_STATUS_OK;
12348 static elink_status_t elink_8726_common_init_phy(struct bnx2x_softc *sc,
12349 uint32_t shmem_base_path[],
12350 uint32_t shmem2_base_path[],
12352 __rte_unused uint32_t chip_id)
12356 struct elink_phy phy;
12357 /* Use port1 because of the static port-swap */
12358 /* Enable the module detection interrupt */
12359 val = REG_RD(sc, MISC_REG_GPIO_EVENT_EN);
12360 val |= ((1 << MISC_REGISTERS_GPIO_3) |
12362 (MISC_REGISTERS_GPIO_3 + MISC_REGISTERS_GPIO_PORT_SHIFT)));
12363 REG_WR(sc, MISC_REG_GPIO_EVENT_EN, val);
12365 elink_ext_phy_hw_reset(sc, 0);
12367 for (port = 0; port < PORT_MAX; port++) {
12368 uint32_t shmem_base, shmem2_base;
12370 /* In E2, same phy is using for port0 of the two paths */
12371 if (CHIP_IS_E1x(sc)) {
12372 shmem_base = shmem_base_path[0];
12373 shmem2_base = shmem2_base_path[0];
12375 shmem_base = shmem_base_path[port];
12376 shmem2_base = shmem2_base_path[port];
12378 /* Extract the ext phy address for the port */
12379 if (elink_populate_phy(sc, phy_index, shmem_base, shmem2_base,
12380 port, &phy) != ELINK_STATUS_OK) {
12381 PMD_DRV_LOG(DEBUG, sc, "populate phy failed");
12382 return ELINK_STATUS_ERROR;
12386 elink_cl45_write(sc, &phy,
12387 MDIO_PMA_DEVAD, MDIO_PMA_REG_GEN_CTRL, 0x0001);
12389 /* Set fault module detected LED on */
12390 elink_cb_gpio_write(sc, MISC_REGISTERS_GPIO_0,
12391 MISC_REGISTERS_GPIO_HIGH, port);
12394 return ELINK_STATUS_OK;
12397 static void elink_get_ext_phy_reset_gpio(struct bnx2x_softc *sc,
12398 uint32_t shmem_base, uint8_t * io_gpio,
12402 uint32_t phy_gpio_reset = REG_RD(sc, shmem_base +
12403 offsetof(struct shmem_region,
12405 port_hw_config[PORT_0].
12407 switch (phy_gpio_reset) {
12408 case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO0_P0:
12412 case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO1_P0:
12416 case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO2_P0:
12420 case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO3_P0:
12424 case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO0_P1:
12428 case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO1_P1:
12432 case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO2_P1:
12436 case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO3_P1:
12441 /* Don't override the io_gpio and io_port */
12446 static elink_status_t elink_8727_common_init_phy(struct bnx2x_softc *sc,
12447 uint32_t shmem_base_path[],
12448 uint32_t shmem2_base_path[],
12450 __rte_unused uint32_t chip_id)
12452 int8_t port, reset_gpio;
12453 uint32_t swap_val, swap_override;
12454 struct elink_phy phy[PORT_MAX];
12455 struct elink_phy *phy_blk[PORT_MAX];
12456 int8_t port_of_path;
12457 swap_val = REG_RD(sc, NIG_REG_PORT_SWAP);
12458 swap_override = REG_RD(sc, NIG_REG_STRAP_OVERRIDE);
12460 reset_gpio = MISC_REGISTERS_GPIO_1;
12463 /* Retrieve the reset gpio/port which control the reset.
12464 * Default is GPIO1, PORT1
12466 elink_get_ext_phy_reset_gpio(sc, shmem_base_path[0],
12467 (uint8_t *) & reset_gpio,
12468 (uint8_t *) & port);
12470 /* Calculate the port based on port swap */
12471 port ^= (swap_val && swap_override);
12473 /* Initiate PHY reset */
12474 elink_cb_gpio_write(sc, reset_gpio, MISC_REGISTERS_GPIO_OUTPUT_LOW,
12477 elink_cb_gpio_write(sc, reset_gpio, MISC_REGISTERS_GPIO_OUTPUT_HIGH,
12482 /* PART1 - Reset both phys */
12483 for (port = PORT_MAX - 1; port >= PORT_0; port--) {
12484 uint32_t shmem_base, shmem2_base;
12486 /* In E2, same phy is using for port0 of the two paths */
12487 if (CHIP_IS_E1x(sc)) {
12488 shmem_base = shmem_base_path[0];
12489 shmem2_base = shmem2_base_path[0];
12490 port_of_path = port;
12492 shmem_base = shmem_base_path[port];
12493 shmem2_base = shmem2_base_path[port];
12497 /* Extract the ext phy address for the port */
12498 if (elink_populate_phy(sc, phy_index, shmem_base, shmem2_base,
12499 port_of_path, &phy[port]) !=
12501 PMD_DRV_LOG(DEBUG, sc, "populate phy failed");
12502 return ELINK_STATUS_ERROR;
12504 /* disable attentions */
12505 elink_bits_dis(sc, NIG_REG_MASK_INTERRUPT_PORT0 +
12507 (ELINK_NIG_MASK_XGXS0_LINK_STATUS |
12508 ELINK_NIG_MASK_XGXS0_LINK10G |
12509 ELINK_NIG_MASK_SERDES0_LINK_STATUS |
12510 ELINK_NIG_MASK_MI_INT));
12512 /* Reset the phy */
12513 elink_cl45_write(sc, &phy[port],
12514 MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 1 << 15);
12517 /* Add delay of 150ms after reset */
12519 if (phy[PORT_0].addr & 0x1) {
12520 phy_blk[PORT_0] = &(phy[PORT_1]);
12521 phy_blk[PORT_1] = &(phy[PORT_0]);
12523 phy_blk[PORT_0] = &(phy[PORT_0]);
12524 phy_blk[PORT_1] = &(phy[PORT_1]);
12526 /* PART2 - Download firmware to both phys */
12527 for (port = PORT_MAX - 1; port >= PORT_0; port--) {
12528 if (CHIP_IS_E1x(sc))
12529 port_of_path = port;
12532 PMD_DRV_LOG(DEBUG, sc, "Loading spirom for phy address 0x%x",
12533 phy_blk[port]->addr);
12534 if (elink_8073_8727_external_rom_boot(sc, phy_blk[port],
12536 return ELINK_STATUS_ERROR;
12537 /* Disable PHY transmitter output */
12538 elink_cl45_write(sc, phy_blk[port],
12539 MDIO_PMA_DEVAD, MDIO_PMA_REG_TX_DISABLE, 1);
12542 return ELINK_STATUS_OK;
12545 static elink_status_t elink_84833_common_init_phy(struct bnx2x_softc *sc,
12546 uint32_t shmem_base_path[],
12547 __rte_unused uint32_t
12548 shmem2_base_path[],
12549 __rte_unused uint8_t
12550 phy_index, uint32_t chip_id)
12552 uint8_t reset_gpios;
12553 reset_gpios = elink_84833_get_reset_gpios(sc, shmem_base_path, chip_id);
12554 elink_cb_gpio_mult_write(sc, reset_gpios,
12555 MISC_REGISTERS_GPIO_OUTPUT_LOW);
12557 elink_cb_gpio_mult_write(sc, reset_gpios,
12558 MISC_REGISTERS_GPIO_OUTPUT_HIGH);
12559 PMD_DRV_LOG(DEBUG, sc,
12560 "84833 reset pulse on pin values 0x%x", reset_gpios);
12561 return ELINK_STATUS_OK;
12564 static elink_status_t elink_ext_phy_common_init(struct bnx2x_softc *sc,
12565 uint32_t shmem_base_path[],
12566 uint32_t shmem2_base_path[],
12568 uint32_t ext_phy_type,
12571 elink_status_t rc = ELINK_STATUS_OK;
12573 switch (ext_phy_type) {
12574 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X8073:
12575 rc = elink_8073_common_init_phy(sc, shmem_base_path,
12577 phy_index, chip_id);
12579 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X8722:
12580 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X8727:
12581 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X8727_NOC:
12582 rc = elink_8727_common_init_phy(sc, shmem_base_path,
12584 phy_index, chip_id);
12587 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X8726:
12588 /* GPIO1 affects both ports, so there's need to pull
12589 * it for single port alone
12591 rc = elink_8726_common_init_phy(sc, shmem_base_path,
12593 phy_index, chip_id);
12595 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84833:
12596 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84834:
12597 /* GPIO3's are linked, and so both need to be toggled
12598 * to obtain required 2us pulse.
12600 rc = elink_84833_common_init_phy(sc, shmem_base_path,
12602 phy_index, chip_id);
12604 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE:
12605 rc = ELINK_STATUS_ERROR;
12608 PMD_DRV_LOG(DEBUG, sc,
12609 "ext_phy 0x%x common init not required",
12614 if (rc != ELINK_STATUS_OK)
12615 elink_cb_event_log(sc, ELINK_LOG_ID_PHY_UNINITIALIZED, 0); // "Warning: PHY was not initialized,"
12621 elink_status_t elink_common_init_phy(struct bnx2x_softc * sc,
12622 uint32_t shmem_base_path[],
12623 uint32_t shmem2_base_path[],
12625 __rte_unused uint8_t one_port_enabled)
12627 elink_status_t rc = ELINK_STATUS_OK;
12628 uint32_t phy_ver, val;
12629 uint8_t phy_index = 0;
12630 uint32_t ext_phy_type, ext_phy_config;
12632 elink_set_mdio_clk(sc, GRCBASE_EMAC0);
12633 elink_set_mdio_clk(sc, GRCBASE_EMAC1);
12634 PMD_DRV_LOG(DEBUG, sc, "Begin common phy init");
12635 if (CHIP_IS_E3(sc)) {
12637 val = REG_RD(sc, MISC_REG_GEN_PURP_HWG);
12638 REG_WR(sc, MISC_REG_GEN_PURP_HWG, val | 1);
12640 /* Check if common init was already done */
12641 phy_ver = REG_RD(sc, shmem_base_path[0] +
12642 offsetof(struct shmem_region,
12643 port_mb[PORT_0].ext_phy_fw_version));
12645 PMD_DRV_LOG(DEBUG, sc, "Not doing common init; phy ver is 0x%x",
12647 return ELINK_STATUS_OK;
12650 /* Read the ext_phy_type for arbitrary port(0) */
12651 for (phy_index = ELINK_EXT_PHY1; phy_index < ELINK_MAX_PHYS;
12653 ext_phy_config = elink_get_ext_phy_config(sc,
12654 shmem_base_path[0],
12656 ext_phy_type = ELINK_XGXS_EXT_PHY_TYPE(ext_phy_config);
12657 rc |= elink_ext_phy_common_init(sc, shmem_base_path,
12659 phy_index, ext_phy_type,
12665 static void elink_check_over_curr(struct elink_params *params,
12666 struct elink_vars *vars)
12668 struct bnx2x_softc *sc = params->sc;
12670 uint8_t port = params->port;
12673 cfg_pin = (REG_RD(sc, params->shmem_base +
12674 offsetof(struct shmem_region,
12675 dev_info.port_hw_config[port].
12676 e3_cmn_pin_cfg1)) &
12677 PORT_HW_CFG_E3_OVER_CURRENT_MASK) >>
12678 PORT_HW_CFG_E3_OVER_CURRENT_SHIFT;
12680 /* Ignore check if no external input PIN available */
12681 if (elink_get_cfg_pin(sc, cfg_pin, &pin_val) != ELINK_STATUS_OK)
12685 if ((vars->phy_flags & PHY_OVER_CURRENT_FLAG) == 0) {
12686 elink_cb_event_log(sc, ELINK_LOG_ID_OVER_CURRENT, params->port); //"Error: Power fault on Port %d has"
12687 // " been detected and the power to "
12688 // "that SFP+ module has been removed"
12689 // " to prevent failure of the card."
12690 // " Please remove the SFP+ module and"
12691 // " restart the system to clear this"
12693 vars->phy_flags |= PHY_OVER_CURRENT_FLAG;
12694 elink_warpcore_power_module(params, 0);
12697 vars->phy_flags &= ~PHY_OVER_CURRENT_FLAG;
12700 /* Returns 0 if no change occured since last check; 1 otherwise. */
12701 static uint8_t elink_analyze_link_error(struct elink_params *params,
12702 struct elink_vars *vars,
12703 uint32_t status, uint32_t phy_flag,
12704 uint32_t link_flag, uint8_t notify)
12706 struct bnx2x_softc *sc = params->sc;
12707 /* Compare new value with previous value */
12709 uint32_t old_status = (vars->phy_flags & phy_flag) ? 1 : 0;
12711 if ((status ^ old_status) == 0)
12714 /* If values differ */
12715 switch (phy_flag) {
12716 case PHY_HALF_OPEN_CONN_FLAG:
12717 PMD_DRV_LOG(DEBUG, sc, "Analyze Remote Fault");
12719 case PHY_SFP_TX_FAULT_FLAG:
12720 PMD_DRV_LOG(DEBUG, sc, "Analyze TX Fault");
12723 PMD_DRV_LOG(DEBUG, sc, "Analyze UNKNOWN");
12725 PMD_DRV_LOG(DEBUG, sc, "Link changed:[%x %x]->%x", vars->link_up,
12726 old_status, status);
12728 /* a. Update shmem->link_status accordingly
12729 * b. Update elink_vars->link_up
12732 vars->link_status &= ~LINK_STATUS_LINK_UP;
12733 vars->link_status |= link_flag;
12735 vars->phy_flags |= phy_flag;
12737 /* activate nig drain */
12738 REG_WR(sc, NIG_REG_EGRESS_DRAIN0_MODE + params->port * 4, 1);
12739 /* Set LED mode to off since the PHY doesn't know about these
12742 led_mode = ELINK_LED_MODE_OFF;
12744 vars->link_status |= LINK_STATUS_LINK_UP;
12745 vars->link_status &= ~link_flag;
12747 vars->phy_flags &= ~phy_flag;
12748 led_mode = ELINK_LED_MODE_OPER;
12750 /* Clear nig drain */
12751 REG_WR(sc, NIG_REG_EGRESS_DRAIN0_MODE + params->port * 4, 0);
12753 elink_sync_link(params, vars);
12754 /* Update the LED according to the link state */
12755 elink_set_led(params, vars, led_mode, ELINK_SPEED_10000);
12757 /* Update link status in the shared memory */
12758 elink_update_mng(params, vars->link_status);
12760 /* C. Trigger General Attention */
12761 vars->periodic_flags |= ELINK_PERIODIC_FLAGS_LINK_EVENT;
12763 elink_cb_notify_link_changed(sc);
12768 /******************************************************************************
12770 * This function checks for half opened connection change indication.
12771 * When such change occurs, it calls the elink_analyze_link_error
12772 * to check if Remote Fault is set or cleared. Reception of remote fault
12773 * status message in the MAC indicates that the peer's MAC has detected
12774 * a fault, for example, due to break in the TX side of fiber.
12776 ******************************************************************************/
12777 static elink_status_t elink_check_half_open_conn(struct elink_params *params,
12778 struct elink_vars *vars,
12781 struct bnx2x_softc *sc = params->sc;
12782 uint32_t lss_status = 0;
12784 /* In case link status is physically up @ 10G do */
12785 if (((vars->phy_flags & PHY_PHYSICAL_LINK_FLAG) == 0) ||
12786 (REG_RD(sc, NIG_REG_EGRESS_EMAC0_PORT + params->port * 4)))
12787 return ELINK_STATUS_OK;
12789 if (CHIP_IS_E3(sc) &&
12790 (REG_RD(sc, MISC_REG_RESET_REG_2) &
12791 (MISC_REGISTERS_RESET_REG_2_XMAC))) {
12792 /* Check E3 XMAC */
12793 /* Note that link speed cannot be queried here, since it may be
12794 * zero while link is down. In case UMAC is active, LSS will
12795 * simply not be set
12797 mac_base = (params->port) ? GRCBASE_XMAC1 : GRCBASE_XMAC0;
12799 /* Clear stick bits (Requires rising edge) */
12800 REG_WR(sc, mac_base + XMAC_REG_CLEAR_RX_LSS_STATUS, 0);
12801 REG_WR(sc, mac_base + XMAC_REG_CLEAR_RX_LSS_STATUS,
12802 XMAC_CLEAR_RX_LSS_STATUS_REG_CLEAR_LOCAL_FAULT_STATUS |
12803 XMAC_CLEAR_RX_LSS_STATUS_REG_CLEAR_REMOTE_FAULT_STATUS);
12804 if (REG_RD(sc, mac_base + XMAC_REG_RX_LSS_STATUS))
12807 elink_analyze_link_error(params, vars, lss_status,
12808 PHY_HALF_OPEN_CONN_FLAG,
12809 LINK_STATUS_NONE, notify);
12810 } else if (REG_RD(sc, MISC_REG_RESET_REG_2) &
12811 (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << params->port)) {
12812 /* Check E1X / E2 BMAC */
12813 uint32_t lss_status_reg;
12814 uint32_t wb_data[2];
12815 mac_base = params->port ? NIG_REG_INGRESS_BMAC1_MEM :
12816 NIG_REG_INGRESS_BMAC0_MEM;
12817 /* Read BIGMAC_REGISTER_RX_LSS_STATUS */
12818 if (CHIP_IS_E2(sc))
12819 lss_status_reg = BIGMAC2_REGISTER_RX_LSS_STAT;
12821 lss_status_reg = BIGMAC_REGISTER_RX_LSS_STATUS;
12823 REG_RD_DMAE(sc, mac_base + lss_status_reg, wb_data, 2);
12824 lss_status = (wb_data[0] > 0);
12826 elink_analyze_link_error(params, vars, lss_status,
12827 PHY_HALF_OPEN_CONN_FLAG,
12828 LINK_STATUS_NONE, notify);
12830 return ELINK_STATUS_OK;
12833 static void elink_sfp_tx_fault_detection(struct elink_phy *phy,
12834 struct elink_params *params,
12835 struct elink_vars *vars)
12837 struct bnx2x_softc *sc = params->sc;
12838 uint32_t cfg_pin, value = 0;
12839 uint8_t led_change, port = params->port;
12841 /* Get The SFP+ TX_Fault controlling pin ([eg]pio) */
12842 cfg_pin = (REG_RD(sc, params->shmem_base + offsetof(struct shmem_region,
12847 PORT_HW_CFG_E3_TX_FAULT_MASK) >>
12848 PORT_HW_CFG_E3_TX_FAULT_SHIFT;
12850 if (elink_get_cfg_pin(sc, cfg_pin, &value)) {
12851 PMD_DRV_LOG(DEBUG, sc, "Failed to read pin 0x%02x", cfg_pin);
12855 led_change = elink_analyze_link_error(params, vars, value,
12856 PHY_SFP_TX_FAULT_FLAG,
12857 LINK_STATUS_SFP_TX_FAULT, 1);
12860 /* Change TX_Fault led, set link status for further syncs */
12863 if (vars->phy_flags & PHY_SFP_TX_FAULT_FLAG) {
12864 led_mode = MISC_REGISTERS_GPIO_HIGH;
12865 vars->link_status |= LINK_STATUS_SFP_TX_FAULT;
12867 led_mode = MISC_REGISTERS_GPIO_LOW;
12868 vars->link_status &= ~LINK_STATUS_SFP_TX_FAULT;
12871 /* If module is unapproved, led should be on regardless */
12872 if (!(phy->flags & ELINK_FLAGS_SFP_NOT_APPROVED)) {
12873 PMD_DRV_LOG(DEBUG, sc, "Change TX_Fault LED: ->%x",
12875 elink_set_e3_module_fault_led(params, led_mode);
12880 static void elink_kr2_recovery(struct elink_params *params,
12881 struct elink_vars *vars, struct elink_phy *phy)
12883 PMD_DRV_LOG(DEBUG, params->sc, "KR2 recovery");
12885 elink_warpcore_enable_AN_KR2(phy, params, vars);
12886 elink_warpcore_restart_AN_KR(phy, params);
12889 static void elink_check_kr2_wa(struct elink_params *params,
12890 struct elink_vars *vars, struct elink_phy *phy)
12892 struct bnx2x_softc *sc = params->sc;
12893 uint16_t base_page, next_page, not_kr2_device, lane;
12896 /* Once KR2 was disabled, wait 5 seconds before checking KR2 recovery
12897 * Since some switches tend to reinit the AN process and clear the
12898 * the advertised BP/NP after ~2 seconds causing the KR2 to be disabled
12899 * and recovered many times
12901 if (vars->check_kr2_recovery_cnt > 0) {
12902 vars->check_kr2_recovery_cnt--;
12906 sigdet = elink_warpcore_get_sigdet(phy, params);
12908 if (!(vars->link_attr_sync & LINK_ATTR_SYNC_KR2_ENABLE)) {
12909 elink_kr2_recovery(params, vars, phy);
12910 PMD_DRV_LOG(DEBUG, sc, "No sigdet");
12915 lane = elink_get_warpcore_lane(params);
12916 CL22_WR_OVER_CL45(sc, phy, MDIO_REG_BANK_AER_BLOCK,
12917 MDIO_AER_BLOCK_AER_REG, lane);
12918 elink_cl45_read(sc, phy, MDIO_AN_DEVAD,
12919 MDIO_AN_REG_LP_AUTO_NEG, &base_page);
12920 elink_cl45_read(sc, phy, MDIO_AN_DEVAD,
12921 MDIO_AN_REG_LP_AUTO_NEG2, &next_page);
12922 elink_set_aer_mmd(params, phy);
12924 /* CL73 has not begun yet */
12925 if (base_page == 0) {
12926 if (!(vars->link_attr_sync & LINK_ATTR_SYNC_KR2_ENABLE)) {
12927 elink_kr2_recovery(params, vars, phy);
12928 PMD_DRV_LOG(DEBUG, sc, "No BP");
12933 /* In case NP bit is not set in the BasePage, or it is set,
12934 * but only KX is advertised, declare this link partner as non-KR2
12937 not_kr2_device = (((base_page & 0x8000) == 0) ||
12938 (((base_page & 0x8000) &&
12939 ((next_page & 0xe0) == 0x20))));
12941 /* In case KR2 is already disabled, check if we need to re-enable it */
12942 if (!(vars->link_attr_sync & LINK_ATTR_SYNC_KR2_ENABLE)) {
12943 if (!not_kr2_device) {
12944 PMD_DRV_LOG(DEBUG, sc, "BP=0x%x, NP=0x%x", base_page,
12946 elink_kr2_recovery(params, vars, phy);
12950 /* KR2 is enabled, but not KR2 device */
12951 if (not_kr2_device) {
12952 /* Disable KR2 on both lanes */
12953 PMD_DRV_LOG(DEBUG, sc,
12954 "BP=0x%x, NP=0x%x", base_page, next_page);
12955 elink_disable_kr2(params, vars, phy);
12956 /* Restart AN on leading lane */
12957 elink_warpcore_restart_AN_KR(phy, params);
12962 void elink_period_func(struct elink_params *params, struct elink_vars *vars)
12965 struct bnx2x_softc *sc = params->sc;
12966 for (phy_idx = ELINK_INT_PHY; phy_idx < ELINK_MAX_PHYS; phy_idx++) {
12967 if (params->phy[phy_idx].flags & ELINK_FLAGS_TX_ERROR_CHECK) {
12968 elink_set_aer_mmd(params, ¶ms->phy[phy_idx]);
12969 if (elink_check_half_open_conn(params, vars, 1) !=
12971 PMD_DRV_LOG(DEBUG, sc, "Fault detection failed");
12977 if (CHIP_IS_E3(sc)) {
12978 struct elink_phy *phy = ¶ms->phy[ELINK_INT_PHY];
12979 elink_set_aer_mmd(params, phy);
12980 if ((phy->supported & ELINK_SUPPORTED_20000baseKR2_Full) &&
12981 (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_20G))
12982 elink_check_kr2_wa(params, vars, phy);
12983 elink_check_over_curr(params, vars);
12984 if (vars->rx_tx_asic_rst)
12985 elink_warpcore_config_runtime(phy, params, vars);
12987 if ((REG_RD(sc, params->shmem_base +
12988 offsetof(struct shmem_region,
12989 dev_info.port_hw_config[params->port].
12991 & PORT_HW_CFG_NET_SERDES_IF_MASK) ==
12992 PORT_HW_CFG_NET_SERDES_IF_SFI) {
12993 if (elink_is_sfp_module_plugged(params)) {
12994 elink_sfp_tx_fault_detection(phy, params, vars);
12995 } else if (vars->link_status & LINK_STATUS_SFP_TX_FAULT) {
12996 /* Clean trail, interrupt corrects the leds */
12997 vars->link_status &= ~LINK_STATUS_SFP_TX_FAULT;
12998 vars->phy_flags &= ~PHY_SFP_TX_FAULT_FLAG;
12999 /* Update link status in the shared memory */
13000 elink_update_mng(params, vars->link_status);
13006 uint8_t elink_fan_failure_det_req(struct bnx2x_softc *sc,
13007 uint32_t shmem_base,
13008 uint32_t shmem2_base, uint8_t port)
13010 uint8_t phy_index, fan_failure_det_req = 0;
13011 struct elink_phy phy;
13012 for (phy_index = ELINK_EXT_PHY1; phy_index < ELINK_MAX_PHYS;
13014 if (elink_populate_phy(sc, phy_index, shmem_base, shmem2_base,
13016 != ELINK_STATUS_OK) {
13017 PMD_DRV_LOG(DEBUG, sc, "populate phy failed");
13020 fan_failure_det_req |= (phy.flags &
13021 ELINK_FLAGS_FAN_FAILURE_DET_REQ);
13023 return fan_failure_det_req;
13026 void elink_hw_reset_phy(struct elink_params *params)
13029 struct bnx2x_softc *sc = params->sc;
13030 elink_update_mng(params, 0);
13031 elink_bits_dis(sc, NIG_REG_MASK_INTERRUPT_PORT0 + params->port * 4,
13032 (ELINK_NIG_MASK_XGXS0_LINK_STATUS |
13033 ELINK_NIG_MASK_XGXS0_LINK10G |
13034 ELINK_NIG_MASK_SERDES0_LINK_STATUS |
13035 ELINK_NIG_MASK_MI_INT));
13037 for (phy_index = ELINK_INT_PHY; phy_index < ELINK_MAX_PHYS; phy_index++) {
13038 if (params->phy[phy_index].hw_reset) {
13039 params->phy[phy_index].hw_reset(¶ms->phy[phy_index],
13041 params->phy[phy_index] = phy_null;
13046 void elink_init_mod_abs_int(struct bnx2x_softc *sc, struct elink_vars *vars,
13047 __rte_unused uint32_t chip_id, uint32_t shmem_base,
13048 uint32_t shmem2_base, uint8_t port)
13050 uint8_t gpio_num = 0xff, gpio_port = 0xff, phy_index;
13052 uint32_t offset, aeu_mask, swap_val, swap_override, sync_offset;
13053 if (CHIP_IS_E3(sc)) {
13054 if (elink_get_mod_abs_int_cfg(sc,
13058 &gpio_port) != ELINK_STATUS_OK)
13061 struct elink_phy phy;
13062 for (phy_index = ELINK_EXT_PHY1; phy_index < ELINK_MAX_PHYS;
13064 if (elink_populate_phy(sc, phy_index, shmem_base,
13065 shmem2_base, port, &phy)
13066 != ELINK_STATUS_OK) {
13067 PMD_DRV_LOG(DEBUG, sc, "populate phy failed");
13070 if (phy.type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X8726) {
13071 gpio_num = MISC_REGISTERS_GPIO_3;
13078 if (gpio_num == 0xff)
13081 /* Set GPIO3 to trigger SFP+ module insertion/removal */
13082 elink_cb_gpio_write(sc, gpio_num, MISC_REGISTERS_GPIO_INPUT_HI_Z,
13085 swap_val = REG_RD(sc, NIG_REG_PORT_SWAP);
13086 swap_override = REG_RD(sc, NIG_REG_STRAP_OVERRIDE);
13087 gpio_port ^= (swap_val && swap_override);
13089 vars->aeu_int_mask = AEU_INPUTS_ATTN_BITS_GPIO0_FUNCTION_0 <<
13090 (gpio_num + (gpio_port << 2));
13092 sync_offset = shmem_base +
13093 offsetof(struct shmem_region,
13094 dev_info.port_hw_config[port].aeu_int_mask);
13095 REG_WR(sc, sync_offset, vars->aeu_int_mask);
13097 PMD_DRV_LOG(DEBUG, sc, "Setting MOD_ABS (GPIO%d_P%d) AEU to 0x%x",
13098 gpio_num, gpio_port, vars->aeu_int_mask);
13101 offset = MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0;
13103 offset = MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0;
13105 /* Open appropriate AEU for interrupts */
13106 aeu_mask = REG_RD(sc, offset);
13107 aeu_mask |= vars->aeu_int_mask;
13108 REG_WR(sc, offset, aeu_mask);
13110 /* Enable the GPIO to trigger interrupt */
13111 val = REG_RD(sc, MISC_REG_GPIO_EVENT_EN);
13112 val |= 1 << (gpio_num + (gpio_port << 2));
13113 REG_WR(sc, MISC_REG_GPIO_EVENT_EN, val);