drivers/net/bnxt/bnxt_ethdev.c

   1 /*-
   2  *   BSD LICENSE
   3  *
   4  *   Copyright(c) Broadcom Limited.
   5  *   All rights reserved.
   6  *
   7  *   Redistribution and use in source and binary forms, with or without
   8  *   modification, are permitted provided that the following conditions
   9  *   are met:
  10  *
  11  *     * Redistributions of source code must retain the above copyright
  12  *       notice, this list of conditions and the following disclaimer.
  13  *     * Redistributions in binary form must reproduce the above copyright
  14  *       notice, this list of conditions and the following disclaimer in
  15  *       the documentation and/or other materials provided with the
  16  *       distribution.
  17  *     * Neither the name of Broadcom Corporation nor the names of its
  18  *       contributors may be used to endorse or promote products derived
  19  *       from this software without specific prior written permission.
  20  *
  21  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 #include <inttypes.h>
  35 #include <stdbool.h>
  36
  37 #include <rte_dev.h>
  38 #include <rte_ethdev.h>
  39 #include <rte_malloc.h>
  40 #include <rte_cycles.h>
  41
  42 #include "bnxt.h"
  43 #include "bnxt_cpr.h"
  44 #include "bnxt_filter.h"
  45 #include "bnxt_hwrm.h"
  46 #include "bnxt_ring.h"
  47 #include "bnxt_rxq.h"
  48 #include "bnxt_rxr.h"
  49 #include "bnxt_stats.h"
  50 #include "bnxt_txq.h"
  51 #include "bnxt_txr.h"
  52 #include "bnxt_vnic.h"
  53 #include "hsi_struct_def_dpdk.h"
  54
  55 #define DRV_MODULE_NAME         "bnxt"
  56 static const char bnxt_version[] =
  57         "Broadcom Cumulus driver " DRV_MODULE_NAME "\n";
  58
  59 #define PCI_VENDOR_ID_BROADCOM 0x14E4
  60
  61 #define BROADCOM_DEV_ID_57301 0x16c8
  62 #define BROADCOM_DEV_ID_57302 0x16c9
  63 #define BROADCOM_DEV_ID_57304_PF 0x16ca
  64 #define BROADCOM_DEV_ID_57304_VF 0x16cb
  65 #define BROADCOM_DEV_ID_57402 0x16d0
  66 #define BROADCOM_DEV_ID_57404 0x16d1
  67 #define BROADCOM_DEV_ID_57406_PF 0x16d2
  68 #define BROADCOM_DEV_ID_57406_VF 0x16d3
  69 #define BROADCOM_DEV_ID_57406_MF 0x16d4
  70 #define BROADCOM_DEV_ID_57314 0x16df
  71
  72 static struct rte_pci_id bnxt_pci_id_map[] = {
  73         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57301) },
  74         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57302) },
  75         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57304_PF) },
  76         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57304_VF) },
  77         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57402) },
  78         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57404) },
  79         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_PF) },
  80         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_VF) },
  81         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_MF) },
  82         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57314) },
  83         { .vendor_id = 0, /* sentinel */ },
  84 };
  85
  86 #define BNXT_ETH_RSS_SUPPORT (  \
  87         ETH_RSS_IPV4 |          \
  88         ETH_RSS_NONFRAG_IPV4_TCP |      \
  89         ETH_RSS_NONFRAG_IPV4_UDP |      \
  90         ETH_RSS_IPV6 |          \
  91         ETH_RSS_NONFRAG_IPV6_TCP |      \
  92         ETH_RSS_NONFRAG_IPV6_UDP)
  93
  94 /***********************/
  95
  96 /*
  97  * High level utility functions
  98  */
  99
 100 static void bnxt_free_mem(struct bnxt *bp)
 101 {
 102         bnxt_free_filter_mem(bp);
 103         bnxt_free_vnic_attributes(bp);
 104         bnxt_free_vnic_mem(bp);
 105
 106         bnxt_free_stats(bp);
 107         bnxt_free_tx_rings(bp);
 108         bnxt_free_rx_rings(bp);
 109         bnxt_free_def_cp_ring(bp);
 110 }
 111
 112 static int bnxt_alloc_mem(struct bnxt *bp)
 113 {
 114         int rc;
 115
 116         /* Default completion ring */
 117         rc = bnxt_init_def_ring_struct(bp, SOCKET_ID_ANY);
 118         if (rc)
 119                 goto alloc_mem_err;
 120
 121         rc = bnxt_alloc_rings(bp, 0, NULL, NULL,
 122                               bp->def_cp_ring, "def_cp");
 123         if (rc)
 124                 goto alloc_mem_err;
 125
 126         rc = bnxt_alloc_vnic_mem(bp);
 127         if (rc)
 128                 goto alloc_mem_err;
 129
 130         rc = bnxt_alloc_vnic_attributes(bp);
 131         if (rc)
 132                 goto alloc_mem_err;
 133
 134         rc = bnxt_alloc_filter_mem(bp);
 135         if (rc)
 136                 goto alloc_mem_err;
 137
 138         return 0;
 139
 140 alloc_mem_err:
 141         bnxt_free_mem(bp);
 142         return rc;
 143 }
 144
 145 static int bnxt_init_chip(struct bnxt *bp)
 146 {
 147         unsigned int i, rss_idx, fw_idx;
 148         int rc;
 149
 150         rc = bnxt_alloc_all_hwrm_stat_ctxs(bp);
 151         if (rc) {
 152                 RTE_LOG(ERR, PMD, "HWRM stat ctx alloc failure rc: %x\n", rc);
 153                 goto err_out;
 154         }
 155
 156         rc = bnxt_alloc_hwrm_rings(bp);
 157         if (rc) {
 158                 RTE_LOG(ERR, PMD, "HWRM ring alloc failure rc: %x\n", rc);
 159                 goto err_out;
 160         }
 161
 162         rc = bnxt_alloc_all_hwrm_ring_grps(bp);
 163         if (rc) {
 164                 RTE_LOG(ERR, PMD, "HWRM ring grp alloc failure: %x\n", rc);
 165                 goto err_out;
 166         }
 167
 168         rc = bnxt_mq_rx_configure(bp);
 169         if (rc) {
 170                 RTE_LOG(ERR, PMD, "MQ mode configure failure rc: %x\n", rc);
 171                 goto err_out;
 172         }
 173
 174         /* VNIC configuration */
 175         for (i = 0; i < bp->nr_vnics; i++) {
 176                 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
 177
 178                 rc = bnxt_hwrm_vnic_alloc(bp, vnic);
 179                 if (rc) {
 180                         RTE_LOG(ERR, PMD, "HWRM vnic alloc failure rc: %x\n",
 181                                 rc);
 182                         goto err_out;
 183                 }
 184
 185                 rc = bnxt_hwrm_vnic_ctx_alloc(bp, vnic);
 186                 if (rc) {
 187                         RTE_LOG(ERR, PMD,
 188                                 "HWRM vnic ctx alloc failure rc: %x\n", rc);
 189                         goto err_out;
 190                 }
 191
 192                 rc = bnxt_hwrm_vnic_cfg(bp, vnic);
 193                 if (rc) {
 194                         RTE_LOG(ERR, PMD, "HWRM vnic cfg failure rc: %x\n", rc);
 195                         goto err_out;
 196                 }
 197
 198                 rc = bnxt_set_hwrm_vnic_filters(bp, vnic);
 199                 if (rc) {
 200                         RTE_LOG(ERR, PMD, "HWRM vnic filter failure rc: %x\n",
 201                                 rc);
 202                         goto err_out;
 203                 }
 204                 if (vnic->rss_table && vnic->hash_type) {
 205                         /*
 206                          * Fill the RSS hash & redirection table with
 207                          * ring group ids for all VNICs
 208                          */
 209                         for (rss_idx = 0, fw_idx = 0;
 210                              rss_idx < HW_HASH_INDEX_SIZE;
 211                              rss_idx++, fw_idx++) {
 212                                 if (vnic->fw_grp_ids[fw_idx] ==
 213                                     INVALID_HW_RING_ID)
 214                                         fw_idx = 0;
 215                                 vnic->rss_table[rss_idx] =
 216                                                 vnic->fw_grp_ids[fw_idx];
 217                         }
 218                         rc = bnxt_hwrm_vnic_rss_cfg(bp, vnic);
 219                         if (rc) {
 220                                 RTE_LOG(ERR, PMD,
 221                                         "HWRM vnic set RSS failure rc: %x\n",
 222                                         rc);
 223                                 goto err_out;
 224                         }
 225                 }
 226         }
 227         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, &bp->vnic_info[0]);
 228         if (rc) {
 229                 RTE_LOG(ERR, PMD,
 230                         "HWRM cfa l2 rx mask failure rc: %x\n", rc);
 231                 goto err_out;
 232         }
 233
 234         return 0;
 235
 236 err_out:
 237         bnxt_free_all_hwrm_resources(bp);
 238
 239         return rc;
 240 }
 241
 242 static int bnxt_shutdown_nic(struct bnxt *bp)
 243 {
 244         bnxt_free_all_hwrm_resources(bp);
 245         bnxt_free_all_filters(bp);
 246         bnxt_free_all_vnics(bp);
 247         return 0;
 248 }
 249
 250 static int bnxt_init_nic(struct bnxt *bp)
 251 {
 252         int rc;
 253
 254         bnxt_init_ring_grps(bp);
 255         bnxt_init_vnics(bp);
 256         bnxt_init_filters(bp);
 257
 258         rc = bnxt_init_chip(bp);
 259         if (rc)
 260                 return rc;
 261
 262         return 0;
 263 }
 264
 265 /*
 266  * Device configuration and status function
 267  */
 268
 269 static void bnxt_dev_info_get_op(struct rte_eth_dev *eth_dev,
 270                                   struct rte_eth_dev_info *dev_info)
 271 {
 272         struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
 273         uint16_t max_vnics, i, j, vpool, vrxq;
 274
 275         /* MAC Specifics */
 276         dev_info->max_mac_addrs = MAX_NUM_MAC_ADDR;
 277         dev_info->max_hash_mac_addrs = 0;
 278
 279         /* PF/VF specifics */
 280         if (BNXT_PF(bp)) {
 281                 dev_info->max_rx_queues = bp->pf.max_rx_rings;
 282                 dev_info->max_tx_queues = bp->pf.max_tx_rings;
 283                 dev_info->max_vfs = bp->pf.active_vfs;
 284                 dev_info->reta_size = bp->pf.max_rsscos_ctx;
 285                 max_vnics = bp->pf.max_vnics;
 286         } else {
 287                 dev_info->max_rx_queues = bp->vf.max_rx_rings;
 288                 dev_info->max_tx_queues = bp->vf.max_tx_rings;
 289                 dev_info->reta_size = bp->vf.max_rsscos_ctx;
 290                 max_vnics = bp->vf.max_vnics;
 291         }
 292
 293         /* Fast path specifics */
 294         dev_info->min_rx_bufsize = 1;
 295         dev_info->max_rx_pktlen = BNXT_MAX_MTU + ETHER_HDR_LEN + ETHER_CRC_LEN
 296                                   + VLAN_TAG_SIZE;
 297         dev_info->rx_offload_capa = 0;
 298         dev_info->tx_offload_capa = DEV_TX_OFFLOAD_IPV4_CKSUM |
 299                                         DEV_TX_OFFLOAD_TCP_CKSUM |
 300                                         DEV_TX_OFFLOAD_UDP_CKSUM |
 301                                         DEV_TX_OFFLOAD_TCP_TSO;
 302
 303         /* *INDENT-OFF* */
 304         dev_info->default_rxconf = (struct rte_eth_rxconf) {
 305                 .rx_thresh = {
 306                         .pthresh = 8,
 307                         .hthresh = 8,
 308                         .wthresh = 0,
 309                 },
 310                 .rx_free_thresh = 32,
 311                 .rx_drop_en = 0,
 312         };
 313
 314         dev_info->default_txconf = (struct rte_eth_txconf) {
 315                 .tx_thresh = {
 316                         .pthresh = 32,
 317                         .hthresh = 0,
 318                         .wthresh = 0,
 319                 },
 320                 .tx_free_thresh = 32,
 321                 .tx_rs_thresh = 32,
 322                 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
 323                              ETH_TXQ_FLAGS_NOOFFLOADS,
 324         };
 325         /* *INDENT-ON* */
 326
 327         /*
 328          * TODO: default_rxconf, default_txconf, rx_desc_lim, and tx_desc_lim
 329          *       need further investigation.
 330          */
 331
 332         /* VMDq resources */
 333         vpool = 64; /* ETH_64_POOLS */
 334         vrxq = 128; /* ETH_VMDQ_DCB_NUM_QUEUES */
 335         for (i = 0; i < 4; vpool >>= 1, i++) {
 336                 if (max_vnics > vpool) {
 337                         for (j = 0; j < 5; vrxq >>= 1, j++) {
 338                                 if (dev_info->max_rx_queues > vrxq) {
 339                                         if (vpool > vrxq)
 340                                                 vpool = vrxq;
 341                                         goto found;
 342                                 }
 343                         }
 344                         /* Not enough resources to support VMDq */
 345                         break;
 346                 }
 347         }
 348         /* Not enough resources to support VMDq */
 349         vpool = 0;
 350         vrxq = 0;
 351 found:
 352         dev_info->max_vmdq_pools = vpool;
 353         dev_info->vmdq_queue_num = vrxq;
 354
 355         dev_info->vmdq_pool_base = 0;
 356         dev_info->vmdq_queue_base = 0;
 357 }
 358
 359 /* Configure the device based on the configuration provided */
 360 static int bnxt_dev_configure_op(struct rte_eth_dev *eth_dev)
 361 {
 362         struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
 363         int rc;
 364
 365         bp->rx_queues = (void *)eth_dev->data->rx_queues;
 366         bp->tx_queues = (void *)eth_dev->data->tx_queues;
 367
 368         /* Inherit new configurations */
 369         bp->rx_nr_rings = eth_dev->data->nb_rx_queues;
 370         bp->tx_nr_rings = eth_dev->data->nb_tx_queues;
 371         bp->rx_cp_nr_rings = bp->rx_nr_rings;
 372         bp->tx_cp_nr_rings = bp->tx_nr_rings;
 373
 374         if (eth_dev->data->dev_conf.rxmode.jumbo_frame)
 375                 eth_dev->data->mtu =
 376                                 eth_dev->data->dev_conf.rxmode.max_rx_pkt_len -
 377                                 ETHER_HDR_LEN - ETHER_CRC_LEN - VLAN_TAG_SIZE;
 378         rc = bnxt_set_hwrm_link_config(bp, true);
 379         return rc;
 380 }
 381
 382 static int bnxt_dev_start_op(struct rte_eth_dev *eth_dev)
 383 {
 384         struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
 385         int rc;
 386
 387         rc = bnxt_hwrm_func_reset(bp);
 388         if (rc) {
 389                 RTE_LOG(ERR, PMD, "hwrm chip reset failure rc: %x\n", rc);
 390                 rc = -1;
 391                 goto error;
 392         }
 393
 394         rc = bnxt_alloc_mem(bp);
 395         if (rc)
 396                 goto error;
 397
 398         rc = bnxt_init_nic(bp);
 399         if (rc)
 400                 goto error;
 401
 402         return 0;
 403
 404 error:
 405         bnxt_shutdown_nic(bp);
 406         bnxt_free_tx_mbufs(bp);
 407         bnxt_free_rx_mbufs(bp);
 408         bnxt_free_mem(bp);
 409         return rc;
 410 }
 411
 412 static int bnxt_dev_set_link_up_op(struct rte_eth_dev *eth_dev)
 413 {
 414         struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
 415
 416         eth_dev->data->dev_link.link_status = 1;
 417         bnxt_set_hwrm_link_config(bp, true);
 418         return 0;
 419 }
 420
 421 static int bnxt_dev_set_link_down_op(struct rte_eth_dev *eth_dev)
 422 {
 423         struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
 424
 425         eth_dev->data->dev_link.link_status = 0;
 426         bnxt_set_hwrm_link_config(bp, false);
 427         return 0;
 428 }
 429
 430 static void bnxt_dev_close_op(struct rte_eth_dev *eth_dev)
 431 {
 432         struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
 433
 434         bnxt_free_tx_mbufs(bp);
 435         bnxt_free_rx_mbufs(bp);
 436         bnxt_free_mem(bp);
 437         rte_free(eth_dev->data->mac_addrs);
 438 }
 439
 440 /* Unload the driver, release resources */
 441 static void bnxt_dev_stop_op(struct rte_eth_dev *eth_dev)
 442 {
 443         struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
 444
 445         if (bp->eth_dev->data->dev_started) {
 446                 /* TBD: STOP HW queues DMA */
 447                 eth_dev->data->dev_link.link_status = 0;
 448         }
 449         bnxt_shutdown_nic(bp);
 450 }
 451
 452 static void bnxt_mac_addr_remove_op(struct rte_eth_dev *eth_dev,
 453                                     uint32_t index)
 454 {
 455         struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
 456         uint64_t pool_mask = eth_dev->data->mac_pool_sel[index];
 457         struct bnxt_vnic_info *vnic;
 458         struct bnxt_filter_info *filter, *temp_filter;
 459         int i;
 460
 461         /*
 462          * Loop through all VNICs from the specified filter flow pools to
 463          * remove the corresponding MAC addr filter
 464          */
 465         for (i = 0; i < MAX_FF_POOLS; i++) {
 466                 if (!(pool_mask & (1 << i)))
 467                         continue;
 468
 469                 STAILQ_FOREACH(vnic, &bp->ff_pool[i], next) {
 470                         filter = STAILQ_FIRST(&vnic->filter);
 471                         while (filter) {
 472                                 temp_filter = STAILQ_NEXT(filter, next);
 473                                 if (filter->mac_index == index) {
 474                                         STAILQ_REMOVE(&vnic->filter, filter,
 475                                                       bnxt_filter_info, next);
 476                                         bnxt_hwrm_clear_filter(bp, filter);
 477                                         filter->mac_index = INVALID_MAC_INDEX;
 478                                         memset(&filter->l2_addr, 0,
 479                                                ETHER_ADDR_LEN);
 480                                         STAILQ_INSERT_TAIL(
 481                                                         &bp->free_filter_list,
 482                                                         filter, next);
 483                                 }
 484                                 filter = temp_filter;
 485                         }
 486                 }
 487         }
 488 }
 489
 490 static void bnxt_mac_addr_add_op(struct rte_eth_dev *eth_dev,
 491                                  struct ether_addr *mac_addr,
 492                                  uint32_t index, uint32_t pool)
 493 {
 494         struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
 495         struct bnxt_vnic_info *vnic = STAILQ_FIRST(&bp->ff_pool[pool]);
 496         struct bnxt_filter_info *filter;
 497
 498         if (!vnic) {
 499                 RTE_LOG(ERR, PMD, "VNIC not found for pool %d!\n", pool);
 500                 return;
 501         }
 502         /* Attach requested MAC address to the new l2_filter */
 503         STAILQ_FOREACH(filter, &vnic->filter, next) {
 504                 if (filter->mac_index == index) {
 505                         RTE_LOG(ERR, PMD,
 506                                 "MAC addr already existed for pool %d\n", pool);
 507                         return;
 508                 }
 509         }
 510         filter = bnxt_alloc_filter(bp);
 511         if (!filter) {
 512                 RTE_LOG(ERR, PMD, "L2 filter alloc failed\n");
 513                 return;
 514         }
 515         STAILQ_INSERT_TAIL(&vnic->filter, filter, next);
 516         filter->mac_index = index;
 517         memcpy(filter->l2_addr, mac_addr, ETHER_ADDR_LEN);
 518         bnxt_hwrm_set_filter(bp, vnic, filter);
 519 }
 520
 521 static int bnxt_link_update_op(struct rte_eth_dev *eth_dev,
 522                                int wait_to_complete)
 523 {
 524         int rc = 0;
 525         struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
 526         struct rte_eth_link new;
 527         unsigned int cnt = BNXT_LINK_WAIT_CNT;
 528
 529         memset(&new, 0, sizeof(new));
 530         do {
 531                 /* Retrieve link info from hardware */
 532                 rc = bnxt_get_hwrm_link_config(bp, &new);
 533                 if (rc) {
 534                         new.link_speed = ETH_LINK_SPEED_100M;
 535                         new.link_duplex = ETH_LINK_FULL_DUPLEX;
 536                         RTE_LOG(ERR, PMD,
 537                                 "Failed to retrieve link rc = 0x%x!", rc);
 538                         goto out;
 539                 }
 540                 if (!wait_to_complete)
 541                         break;
 542
 543                 rte_delay_ms(BNXT_LINK_WAIT_INTERVAL);
 544
 545         } while (!new.link_status && cnt--);
 546
 547         /* Timed out or success */
 548         if (new.link_status) {
 549                 /* Update only if success */
 550                 eth_dev->data->dev_link.link_duplex = new.link_duplex;
 551                 eth_dev->data->dev_link.link_speed = new.link_speed;
 552         }
 553         eth_dev->data->dev_link.link_status = new.link_status;
 554 out:
 555         return rc;
 556 }
 557
 558 static void bnxt_promiscuous_enable_op(struct rte_eth_dev *eth_dev)
 559 {
 560         struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
 561         struct bnxt_vnic_info *vnic;
 562
 563         if (bp->vnic_info == NULL)
 564                 return;
 565
 566         vnic = &bp->vnic_info[0];
 567
 568         vnic->flags |= BNXT_VNIC_INFO_PROMISC;
 569         bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic);
 570 }
 571
 572 static void bnxt_promiscuous_disable_op(struct rte_eth_dev *eth_dev)
 573 {
 574         struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
 575         struct bnxt_vnic_info *vnic;
 576
 577         if (bp->vnic_info == NULL)
 578                 return;
 579
 580         vnic = &bp->vnic_info[0];
 581
 582         vnic->flags &= ~BNXT_VNIC_INFO_PROMISC;
 583         bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic);
 584 }
 585
 586 static void bnxt_allmulticast_enable_op(struct rte_eth_dev *eth_dev)
 587 {
 588         struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
 589         struct bnxt_vnic_info *vnic;
 590
 591         if (bp->vnic_info == NULL)
 592                 return;
 593
 594         vnic = &bp->vnic_info[0];
 595
 596         vnic->flags |= BNXT_VNIC_INFO_ALLMULTI;
 597         bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic);
 598 }
 599
 600 static void bnxt_allmulticast_disable_op(struct rte_eth_dev *eth_dev)
 601 {
 602         struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
 603         struct bnxt_vnic_info *vnic;
 604
 605         if (bp->vnic_info == NULL)
 606                 return;
 607
 608         vnic = &bp->vnic_info[0];
 609
 610         vnic->flags &= ~BNXT_VNIC_INFO_ALLMULTI;
 611         bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic);
 612 }
 613
 614 static int bnxt_reta_update_op(struct rte_eth_dev *eth_dev,
 615                             struct rte_eth_rss_reta_entry64 *reta_conf,
 616                             uint16_t reta_size)
 617 {
 618         struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
 619         struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
 620         struct bnxt_vnic_info *vnic;
 621         int i;
 622
 623         if (!(dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG))
 624                 return -EINVAL;
 625
 626         if (reta_size != HW_HASH_INDEX_SIZE) {
 627                 RTE_LOG(ERR, PMD, "The configured hash table lookup size "
 628                         "(%d) must equal the size supported by the hardware "
 629                         "(%d)\n", reta_size, HW_HASH_INDEX_SIZE);
 630                 return -EINVAL;
 631         }
 632         /* Update the RSS VNIC(s) */
 633         for (i = 0; i < MAX_FF_POOLS; i++) {
 634                 STAILQ_FOREACH(vnic, &bp->ff_pool[i], next) {
 635                         memcpy(vnic->rss_table, reta_conf, reta_size);
 636
 637                         bnxt_hwrm_vnic_rss_cfg(bp, vnic);
 638                 }
 639         }
 640         return 0;
 641 }
 642
 643 static int bnxt_reta_query_op(struct rte_eth_dev *eth_dev,
 644                               struct rte_eth_rss_reta_entry64 *reta_conf,
 645                               uint16_t reta_size)
 646 {
 647         struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
 648         struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
 649
 650         /* Retrieve from the default VNIC */
 651         if (!vnic)
 652                 return -EINVAL;
 653         if (!vnic->rss_table)
 654                 return -EINVAL;
 655
 656         if (reta_size != HW_HASH_INDEX_SIZE) {
 657                 RTE_LOG(ERR, PMD, "The configured hash table lookup size "
 658                         "(%d) must equal the size supported by the hardware "
 659                         "(%d)\n", reta_size, HW_HASH_INDEX_SIZE);
 660                 return -EINVAL;
 661         }
 662         /* EW - need to revisit here copying from u64 to u16 */
 663         memcpy(reta_conf, vnic->rss_table, reta_size);
 664
 665         return 0;
 666 }
 667
 668 static int bnxt_rss_hash_update_op(struct rte_eth_dev *eth_dev,
 669                                    struct rte_eth_rss_conf *rss_conf)
 670 {
 671         struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
 672         struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
 673         struct bnxt_vnic_info *vnic;
 674         uint16_t hash_type = 0;
 675         int i;
 676
 677         /*
 678          * If RSS enablement were different than dev_configure,
 679          * then return -EINVAL
 680          */
 681         if (dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG) {
 682                 if (!rss_conf->rss_hf)
 683                         return -EINVAL;
 684         } else {
 685                 if (rss_conf->rss_hf & BNXT_ETH_RSS_SUPPORT)
 686                         return -EINVAL;
 687         }
 688         if (rss_conf->rss_hf & ETH_RSS_IPV4)
 689                 hash_type |= HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4;
 690         if (rss_conf->rss_hf & ETH_RSS_NONFRAG_IPV4_TCP)
 691                 hash_type |= HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4;
 692         if (rss_conf->rss_hf & ETH_RSS_NONFRAG_IPV4_UDP)
 693                 hash_type |= HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4;
 694         if (rss_conf->rss_hf & ETH_RSS_IPV6)
 695                 hash_type |= HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6;
 696         if (rss_conf->rss_hf & ETH_RSS_NONFRAG_IPV6_TCP)
 697                 hash_type |= HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6;
 698         if (rss_conf->rss_hf & ETH_RSS_NONFRAG_IPV6_UDP)
 699                 hash_type |= HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6;
 700
 701         /* Update the RSS VNIC(s) */
 702         for (i = 0; i < MAX_FF_POOLS; i++) {
 703                 STAILQ_FOREACH(vnic, &bp->ff_pool[i], next) {
 704                         vnic->hash_type = hash_type;
 705
 706                         /*
 707                          * Use the supplied key if the key length is
 708                          * acceptable and the rss_key is not NULL
 709                          */
 710                         if (rss_conf->rss_key &&
 711                             rss_conf->rss_key_len <= HW_HASH_KEY_SIZE)
 712                                 memcpy(vnic->rss_hash_key, rss_conf->rss_key,
 713                                        rss_conf->rss_key_len);
 714
 715                         bnxt_hwrm_vnic_rss_cfg(bp, vnic);
 716                 }
 717         }
 718         return 0;
 719 }
 720
 721 static int bnxt_rss_hash_conf_get_op(struct rte_eth_dev *eth_dev,
 722                                      struct rte_eth_rss_conf *rss_conf)
 723 {
 724         struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
 725         struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
 726         int len;
 727         uint32_t hash_types;
 728
 729         /* RSS configuration is the same for all VNICs */
 730         if (vnic && vnic->rss_hash_key) {
 731                 if (rss_conf->rss_key) {
 732                         len = rss_conf->rss_key_len <= HW_HASH_KEY_SIZE ?
 733                               rss_conf->rss_key_len : HW_HASH_KEY_SIZE;
 734                         memcpy(rss_conf->rss_key, vnic->rss_hash_key, len);
 735                 }
 736
 737                 hash_types = vnic->hash_type;
 738                 rss_conf->rss_hf = 0;
 739                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4) {
 740                         rss_conf->rss_hf |= ETH_RSS_IPV4;
 741                         hash_types &= ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4;
 742                 }
 743                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4) {
 744                         rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
 745                         hash_types &=
 746                                 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4;
 747                 }
 748                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4) {
 749                         rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
 750                         hash_types &=
 751                                 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4;
 752                 }
 753                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6) {
 754                         rss_conf->rss_hf |= ETH_RSS_IPV6;
 755                         hash_types &= ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6;
 756                 }
 757                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6) {
 758                         rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
 759                         hash_types &=
 760                                 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6;
 761                 }
 762                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6) {
 763                         rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
 764                         hash_types &=
 765                                 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6;
 766                 }
 767                 if (hash_types) {
 768                         RTE_LOG(ERR, PMD,
 769                                 "Unknwon RSS config from firmware (%08x), RSS disabled",
 770                                 vnic->hash_type);
 771                         return -ENOTSUP;
 772                 }
 773         } else {
 774                 rss_conf->rss_hf = 0;
 775         }
 776         return 0;
 777 }
 778
 779 static int bnxt_flow_ctrl_get_op(struct rte_eth_dev *dev,
 780                                struct rte_eth_fc_conf *fc_conf __rte_unused)
 781 {
 782         struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
 783         struct rte_eth_link link_info;
 784         int rc;
 785
 786         rc = bnxt_get_hwrm_link_config(bp, &link_info);
 787         if (rc)
 788                 return rc;
 789
 790         memset(fc_conf, 0, sizeof(*fc_conf));
 791         if (bp->link_info.auto_pause)
 792                 fc_conf->autoneg = 1;
 793         switch (bp->link_info.pause) {
 794         case 0:
 795                 fc_conf->mode = RTE_FC_NONE;
 796                 break;
 797         case HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_TX:
 798                 fc_conf->mode = RTE_FC_TX_PAUSE;
 799                 break;
 800         case HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_RX:
 801                 fc_conf->mode = RTE_FC_RX_PAUSE;
 802                 break;
 803         case (HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_TX |
 804                         HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_RX):
 805                 fc_conf->mode = RTE_FC_FULL;
 806                 break;
 807         }
 808         return 0;
 809 }
 810
 811 static int bnxt_flow_ctrl_set_op(struct rte_eth_dev *dev,
 812                                struct rte_eth_fc_conf *fc_conf)
 813 {
 814         struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
 815
 816         switch (fc_conf->mode) {
 817         case RTE_FC_NONE:
 818                 bp->link_info.auto_pause = 0;
 819                 bp->link_info.force_pause = 0;
 820                 break;
 821         case RTE_FC_RX_PAUSE:
 822                 if (fc_conf->autoneg) {
 823                         bp->link_info.auto_pause =
 824                                         HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_RX;
 825                         bp->link_info.force_pause = 0;
 826                 } else {
 827                         bp->link_info.auto_pause = 0;
 828                         bp->link_info.force_pause =
 829                                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_RX;
 830                 }
 831                 break;
 832         case RTE_FC_TX_PAUSE:
 833                 if (fc_conf->autoneg) {
 834                         bp->link_info.auto_pause =
 835                                         HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_TX;
 836                         bp->link_info.force_pause = 0;
 837                 } else {
 838                         bp->link_info.auto_pause = 0;
 839                         bp->link_info.force_pause =
 840                                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_TX;
 841                 }
 842                 break;
 843         case RTE_FC_FULL:
 844                 if (fc_conf->autoneg) {
 845                         bp->link_info.auto_pause =
 846                                         HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_TX |
 847                                         HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_RX;
 848                         bp->link_info.force_pause = 0;
 849                 } else {
 850                         bp->link_info.auto_pause = 0;
 851                         bp->link_info.force_pause =
 852                                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_TX |
 853                                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_RX;
 854                 }
 855                 break;
 856         }
 857         return bnxt_set_hwrm_link_config(bp, true);
 858 }
 859
 860 /*
 861  * Initialization
 862  */
 863
 864 static struct eth_dev_ops bnxt_dev_ops = {
 865         .dev_infos_get = bnxt_dev_info_get_op,
 866         .dev_close = bnxt_dev_close_op,
 867         .dev_configure = bnxt_dev_configure_op,
 868         .dev_start = bnxt_dev_start_op,
 869         .dev_stop = bnxt_dev_stop_op,
 870         .dev_set_link_up = bnxt_dev_set_link_up_op,
 871         .dev_set_link_down = bnxt_dev_set_link_down_op,
 872         .stats_get = bnxt_stats_get_op,
 873         .stats_reset = bnxt_stats_reset_op,
 874         .rx_queue_setup = bnxt_rx_queue_setup_op,
 875         .rx_queue_release = bnxt_rx_queue_release_op,
 876         .tx_queue_setup = bnxt_tx_queue_setup_op,
 877         .tx_queue_release = bnxt_tx_queue_release_op,
 878         .reta_update = bnxt_reta_update_op,
 879         .reta_query = bnxt_reta_query_op,
 880         .rss_hash_update = bnxt_rss_hash_update_op,
 881         .rss_hash_conf_get = bnxt_rss_hash_conf_get_op,
 882         .link_update = bnxt_link_update_op,
 883         .promiscuous_enable = bnxt_promiscuous_enable_op,
 884         .promiscuous_disable = bnxt_promiscuous_disable_op,
 885         .allmulticast_enable = bnxt_allmulticast_enable_op,
 886         .allmulticast_disable = bnxt_allmulticast_disable_op,
 887         .mac_addr_add = bnxt_mac_addr_add_op,
 888         .mac_addr_remove = bnxt_mac_addr_remove_op,
 889         .flow_ctrl_get = bnxt_flow_ctrl_get_op,
 890         .flow_ctrl_set = bnxt_flow_ctrl_set_op,
 891 };
 892
 893 static bool bnxt_vf_pciid(uint16_t id)
 894 {
 895         if (id == BROADCOM_DEV_ID_57304_VF ||
 896             id == BROADCOM_DEV_ID_57406_VF)
 897                 return true;
 898         return false;
 899 }
 900
 901 static int bnxt_init_board(struct rte_eth_dev *eth_dev)
 902 {
 903         int rc;
 904         struct bnxt *bp = eth_dev->data->dev_private;
 905
 906         /* enable device (incl. PCI PM wakeup), and bus-mastering */
 907         if (!eth_dev->pci_dev->mem_resource[0].addr) {
 908                 RTE_LOG(ERR, PMD,
 909                         "Cannot find PCI device base address, aborting\n");
 910                 rc = -ENODEV;
 911                 goto init_err_disable;
 912         }
 913
 914         bp->eth_dev = eth_dev;
 915         bp->pdev = eth_dev->pci_dev;
 916
 917         bp->bar0 = (void *)eth_dev->pci_dev->mem_resource[0].addr;
 918         if (!bp->bar0) {
 919                 RTE_LOG(ERR, PMD, "Cannot map device registers, aborting\n");
 920                 rc = -ENOMEM;
 921                 goto init_err_release;
 922         }
 923         return 0;
 924
 925 init_err_release:
 926         if (bp->bar0)
 927                 bp->bar0 = NULL;
 928
 929 init_err_disable:
 930
 931         return rc;
 932 }
 933
 934 static int
 935 bnxt_dev_init(struct rte_eth_dev *eth_dev)
 936 {
 937         static int version_printed;
 938         struct bnxt *bp;
 939         int rc;
 940
 941         if (version_printed++ == 0)
 942                 RTE_LOG(INFO, PMD, "%s", bnxt_version);
 943
 944         if (eth_dev->pci_dev->addr.function >= 2 &&
 945                         eth_dev->pci_dev->addr.function < 4) {
 946                 RTE_LOG(ERR, PMD, "Function not enabled %x:\n",
 947                         eth_dev->pci_dev->addr.function);
 948                 rc = -ENOMEM;
 949                 goto error;
 950         }
 951
 952         rte_eth_copy_pci_info(eth_dev, eth_dev->pci_dev);
 953         bp = eth_dev->data->dev_private;
 954
 955         if (bnxt_vf_pciid(eth_dev->pci_dev->id.device_id))
 956                 bp->flags |= BNXT_FLAG_VF;
 957
 958         rc = bnxt_init_board(eth_dev);
 959         if (rc) {
 960                 RTE_LOG(ERR, PMD,
 961                         "Board initialization failed rc: %x\n", rc);
 962                 goto error;
 963         }
 964         eth_dev->dev_ops = &bnxt_dev_ops;
 965         eth_dev->rx_pkt_burst = &bnxt_recv_pkts;
 966         eth_dev->tx_pkt_burst = &bnxt_xmit_pkts;
 967
 968         rc = bnxt_alloc_hwrm_resources(bp);
 969         if (rc) {
 970                 RTE_LOG(ERR, PMD,
 971                         "hwrm resource allocation failure rc: %x\n", rc);
 972                 goto error_free;
 973         }
 974         rc = bnxt_hwrm_ver_get(bp);
 975         if (rc)
 976                 goto error_free;
 977         bnxt_hwrm_queue_qportcfg(bp);
 978
 979         /* Get the MAX capabilities for this function */
 980         rc = bnxt_hwrm_func_qcaps(bp);
 981         if (rc) {
 982                 RTE_LOG(ERR, PMD, "hwrm query capability failure rc: %x\n", rc);
 983                 goto error_free;
 984         }
 985         eth_dev->data->mac_addrs = rte_zmalloc("bnxt_mac_addr_tbl",
 986                                         ETHER_ADDR_LEN * MAX_NUM_MAC_ADDR, 0);
 987         if (eth_dev->data->mac_addrs == NULL) {
 988                 RTE_LOG(ERR, PMD,
 989                         "Failed to alloc %u bytes needed to store MAC addr tbl",
 990                         ETHER_ADDR_LEN * MAX_NUM_MAC_ADDR);
 991                 rc = -ENOMEM;
 992                 goto error_free;
 993         }
 994         /* Copy the permanent MAC from the qcap response address now. */
 995         if (BNXT_PF(bp))
 996                 memcpy(bp->mac_addr, bp->pf.mac_addr, sizeof(bp->mac_addr));
 997         else
 998                 memcpy(bp->mac_addr, bp->vf.mac_addr, sizeof(bp->mac_addr));
 999         memcpy(&eth_dev->data->mac_addrs[0], bp->mac_addr, ETHER_ADDR_LEN);
1000         bp->grp_info = rte_zmalloc("bnxt_grp_info",
1001                                 sizeof(*bp->grp_info) * bp->max_ring_grps, 0);
1002         if (!bp->grp_info) {
1003                 RTE_LOG(ERR, PMD,
1004                         "Failed to alloc %zu bytes needed to store group info table\n",
1005                         sizeof(*bp->grp_info) * bp->max_ring_grps);
1006                 rc = -ENOMEM;
1007                 goto error_free;
1008         }
1009
1010         rc = bnxt_hwrm_func_driver_register(bp, 0,
1011                                             bp->pf.vf_req_fwd);
1012         if (rc) {
1013                 RTE_LOG(ERR, PMD,
1014                         "Failed to register driver");
1015                 rc = -EBUSY;
1016                 goto error_free;
1017         }
1018
1019         RTE_LOG(INFO, PMD,
1020                 DRV_MODULE_NAME " found at mem %" PRIx64 ", node addr %pM\n",
1021                 eth_dev->pci_dev->mem_resource[0].phys_addr,
1022                 eth_dev->pci_dev->mem_resource[0].addr);
1023
1024         return 0;
1025
1026 error_free:
1027         eth_dev->driver->eth_dev_uninit(eth_dev);
1028 error:
1029         return rc;
1030 }
1031
1032 static int
1033 bnxt_dev_uninit(struct rte_eth_dev *eth_dev) {
1034         struct bnxt *bp = eth_dev->data->dev_private;
1035         int rc;
1036
1037         if (eth_dev->data->mac_addrs)
1038                 rte_free(eth_dev->data->mac_addrs);
1039         if (bp->grp_info)
1040                 rte_free(bp->grp_info);
1041         rc = bnxt_hwrm_func_driver_unregister(bp, 0);
1042         bnxt_free_hwrm_resources(bp);
1043         return rc;
1044 }
1045
1046 static struct eth_driver bnxt_rte_pmd = {
1047         .pci_drv = {
1048                     .name = "rte_" DRV_MODULE_NAME "_pmd",
1049                     .id_table = bnxt_pci_id_map,
1050                     .drv_flags = RTE_PCI_DRV_NEED_MAPPING,
1051                     },
1052         .eth_dev_init = bnxt_dev_init,
1053         .eth_dev_uninit = bnxt_dev_uninit,
1054         .dev_private_size = sizeof(struct bnxt),
1055 };
1056
1057 static int bnxt_rte_pmd_init(const char *name, const char *params __rte_unused)
1058 {
1059         RTE_LOG(INFO, PMD, "bnxt_rte_pmd_init() called for %s\n", name);
1060         rte_eth_driver_register(&bnxt_rte_pmd);
1061         return 0;
1062 }
1063
1064 static struct rte_driver bnxt_pmd_drv = {
1065         .type = PMD_PDEV,
1066         .init = bnxt_rte_pmd_init,
1067 };
1068
1069 PMD_REGISTER_DRIVER(bnxt_pmd_drv, bnxt);
1070 DRIVER_REGISTER_PCI_TABLE(bnxt, bnxt_pci_id_map);