drivers/net/bnxt/bnxt_ethdev.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2014-2018 Broadcom
   3  * All rights reserved.
   4  */
   5
   6 #include <inttypes.h>
   7 #include <stdbool.h>
   8
   9 #include <rte_dev.h>
  10 #include <rte_ethdev_driver.h>
  11 #include <rte_ethdev_pci.h>
  12 #include <rte_malloc.h>
  13 #include <rte_cycles.h>
  14
  15 #include "bnxt.h"
  16 #include "bnxt_cpr.h"
  17 #include "bnxt_filter.h"
  18 #include "bnxt_hwrm.h"
  19 #include "bnxt_irq.h"
  20 #include "bnxt_ring.h"
  21 #include "bnxt_rxq.h"
  22 #include "bnxt_rxr.h"
  23 #include "bnxt_stats.h"
  24 #include "bnxt_txq.h"
  25 #include "bnxt_txr.h"
  26 #include "bnxt_vnic.h"
  27 #include "hsi_struct_def_dpdk.h"
  28 #include "bnxt_nvm_defs.h"
  29 #include "bnxt_util.h"
  30
  31 #define DRV_MODULE_NAME         "bnxt"
  32 static const char bnxt_version[] =
  33         "Broadcom NetXtreme driver " DRV_MODULE_NAME "\n";
  34 int bnxt_logtype_driver;
  35
  36 #define PCI_VENDOR_ID_BROADCOM 0x14E4
  37
  38 #define BROADCOM_DEV_ID_STRATUS_NIC_VF1 0x1606
  39 #define BROADCOM_DEV_ID_STRATUS_NIC_VF2 0x1609
  40 #define BROADCOM_DEV_ID_STRATUS_NIC 0x1614
  41 #define BROADCOM_DEV_ID_57414_VF 0x16c1
  42 #define BROADCOM_DEV_ID_57301 0x16c8
  43 #define BROADCOM_DEV_ID_57302 0x16c9
  44 #define BROADCOM_DEV_ID_57304_PF 0x16ca
  45 #define BROADCOM_DEV_ID_57304_VF 0x16cb
  46 #define BROADCOM_DEV_ID_57417_MF 0x16cc
  47 #define BROADCOM_DEV_ID_NS2 0x16cd
  48 #define BROADCOM_DEV_ID_57311 0x16ce
  49 #define BROADCOM_DEV_ID_57312 0x16cf
  50 #define BROADCOM_DEV_ID_57402 0x16d0
  51 #define BROADCOM_DEV_ID_57404 0x16d1
  52 #define BROADCOM_DEV_ID_57406_PF 0x16d2
  53 #define BROADCOM_DEV_ID_57406_VF 0x16d3
  54 #define BROADCOM_DEV_ID_57402_MF 0x16d4
  55 #define BROADCOM_DEV_ID_57407_RJ45 0x16d5
  56 #define BROADCOM_DEV_ID_57412 0x16d6
  57 #define BROADCOM_DEV_ID_57414 0x16d7
  58 #define BROADCOM_DEV_ID_57416_RJ45 0x16d8
  59 #define BROADCOM_DEV_ID_57417_RJ45 0x16d9
  60 #define BROADCOM_DEV_ID_5741X_VF 0x16dc
  61 #define BROADCOM_DEV_ID_57412_MF 0x16de
  62 #define BROADCOM_DEV_ID_57314 0x16df
  63 #define BROADCOM_DEV_ID_57317_RJ45 0x16e0
  64 #define BROADCOM_DEV_ID_5731X_VF 0x16e1
  65 #define BROADCOM_DEV_ID_57417_SFP 0x16e2
  66 #define BROADCOM_DEV_ID_57416_SFP 0x16e3
  67 #define BROADCOM_DEV_ID_57317_SFP 0x16e4
  68 #define BROADCOM_DEV_ID_57404_MF 0x16e7
  69 #define BROADCOM_DEV_ID_57406_MF 0x16e8
  70 #define BROADCOM_DEV_ID_57407_SFP 0x16e9
  71 #define BROADCOM_DEV_ID_57407_MF 0x16ea
  72 #define BROADCOM_DEV_ID_57414_MF 0x16ec
  73 #define BROADCOM_DEV_ID_57416_MF 0x16ee
  74 #define BROADCOM_DEV_ID_58802 0xd802
  75 #define BROADCOM_DEV_ID_58804 0xd804
  76 #define BROADCOM_DEV_ID_58808 0x16f0
  77 #define BROADCOM_DEV_ID_58802_VF 0xd800
  78
  79 static const struct rte_pci_id bnxt_pci_id_map[] = {
  80         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM,
  81                          BROADCOM_DEV_ID_STRATUS_NIC_VF1) },
  82         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM,
  83                          BROADCOM_DEV_ID_STRATUS_NIC_VF2) },
  84         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_STRATUS_NIC) },
  85         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414_VF) },
  86         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57301) },
  87         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57302) },
  88         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57304_PF) },
  89         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57304_VF) },
  90         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_NS2) },
  91         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57402) },
  92         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57404) },
  93         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_PF) },
  94         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_VF) },
  95         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57402_MF) },
  96         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_RJ45) },
  97         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57404_MF) },
  98         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_MF) },
  99         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_SFP) },
 100         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_MF) },
 101         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_5741X_VF) },
 102         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_5731X_VF) },
 103         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57314) },
 104         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_MF) },
 105         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57311) },
 106         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57312) },
 107         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57412) },
 108         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414) },
 109         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_RJ45) },
 110         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_RJ45) },
 111         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57412_MF) },
 112         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57317_RJ45) },
 113         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_SFP) },
 114         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_SFP) },
 115         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57317_SFP) },
 116         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414_MF) },
 117         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_MF) },
 118         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58802) },
 119         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58804) },
 120         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58808) },
 121         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58802_VF) },
 122         { .vendor_id = 0, /* sentinel */ },
 123 };
 124
 125 #define BNXT_ETH_RSS_SUPPORT (  \
 126         ETH_RSS_IPV4 |          \
 127         ETH_RSS_NONFRAG_IPV4_TCP |      \
 128         ETH_RSS_NONFRAG_IPV4_UDP |      \
 129         ETH_RSS_IPV6 |          \
 130         ETH_RSS_NONFRAG_IPV6_TCP |      \
 131         ETH_RSS_NONFRAG_IPV6_UDP)
 132
 133 #define BNXT_DEV_TX_OFFLOAD_SUPPORT (DEV_TX_OFFLOAD_VLAN_INSERT | \
 134                                      DEV_TX_OFFLOAD_IPV4_CKSUM | \
 135                                      DEV_TX_OFFLOAD_TCP_CKSUM | \
 136                                      DEV_TX_OFFLOAD_UDP_CKSUM | \
 137                                      DEV_TX_OFFLOAD_TCP_TSO | \
 138                                      DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM | \
 139                                      DEV_TX_OFFLOAD_VXLAN_TNL_TSO | \
 140                                      DEV_TX_OFFLOAD_GRE_TNL_TSO | \
 141                                      DEV_TX_OFFLOAD_IPIP_TNL_TSO | \
 142                                      DEV_TX_OFFLOAD_GENEVE_TNL_TSO | \
 143                                      DEV_TX_OFFLOAD_MULTI_SEGS)
 144
 145 #define BNXT_DEV_RX_OFFLOAD_SUPPORT (DEV_RX_OFFLOAD_VLAN_FILTER | \
 146                                      DEV_RX_OFFLOAD_VLAN_STRIP | \
 147                                      DEV_RX_OFFLOAD_IPV4_CKSUM | \
 148                                      DEV_RX_OFFLOAD_UDP_CKSUM | \
 149                                      DEV_RX_OFFLOAD_TCP_CKSUM | \
 150                                      DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM | \
 151                                      DEV_RX_OFFLOAD_JUMBO_FRAME | \
 152                                      DEV_RX_OFFLOAD_CRC_STRIP | \
 153                                      DEV_RX_OFFLOAD_KEEP_CRC | \
 154                                      DEV_RX_OFFLOAD_TCP_LRO)
 155
 156 static int bnxt_vlan_offload_set_op(struct rte_eth_dev *dev, int mask);
 157 static void bnxt_print_link_info(struct rte_eth_dev *eth_dev);
 158 static int bnxt_mtu_set_op(struct rte_eth_dev *eth_dev, uint16_t new_mtu);
 159 static int bnxt_dev_uninit(struct rte_eth_dev *eth_dev);
 160
 161 /***********************/
 162
 163 /*
 164  * High level utility functions
 165  */
 166
 167 static void bnxt_free_mem(struct bnxt *bp)
 168 {
 169         bnxt_free_filter_mem(bp);
 170         bnxt_free_vnic_attributes(bp);
 171         bnxt_free_vnic_mem(bp);
 172
 173         bnxt_free_stats(bp);
 174         bnxt_free_tx_rings(bp);
 175         bnxt_free_rx_rings(bp);
 176 }
 177
 178 static int bnxt_alloc_mem(struct bnxt *bp)
 179 {
 180         int rc;
 181
 182         rc = bnxt_alloc_vnic_mem(bp);
 183         if (rc)
 184                 goto alloc_mem_err;
 185
 186         rc = bnxt_alloc_vnic_attributes(bp);
 187         if (rc)
 188                 goto alloc_mem_err;
 189
 190         rc = bnxt_alloc_filter_mem(bp);
 191         if (rc)
 192                 goto alloc_mem_err;
 193
 194         return 0;
 195
 196 alloc_mem_err:
 197         bnxt_free_mem(bp);
 198         return rc;
 199 }
 200
 201 static int bnxt_init_chip(struct bnxt *bp)
 202 {
 203         struct bnxt_rx_queue *rxq;
 204         struct rte_eth_link new;
 205         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(bp->eth_dev);
 206         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
 207         uint32_t intr_vector = 0;
 208         uint32_t queue_id, base = BNXT_MISC_VEC_ID;
 209         uint32_t vec = BNXT_MISC_VEC_ID;
 210         unsigned int i, j;
 211         int rc;
 212
 213         /* disable uio/vfio intr/eventfd mapping */
 214         rte_intr_disable(intr_handle);
 215
 216         if (bp->eth_dev->data->mtu > ETHER_MTU) {
 217                 bp->eth_dev->data->dev_conf.rxmode.offloads |=
 218                         DEV_RX_OFFLOAD_JUMBO_FRAME;
 219                 bp->flags |= BNXT_FLAG_JUMBO;
 220         } else {
 221                 bp->eth_dev->data->dev_conf.rxmode.offloads &=
 222                         ~DEV_RX_OFFLOAD_JUMBO_FRAME;
 223                 bp->flags &= ~BNXT_FLAG_JUMBO;
 224         }
 225
 226         rc = bnxt_alloc_all_hwrm_stat_ctxs(bp);
 227         if (rc) {
 228                 PMD_DRV_LOG(ERR, "HWRM stat ctx alloc failure rc: %x\n", rc);
 229                 goto err_out;
 230         }
 231
 232         rc = bnxt_alloc_hwrm_rings(bp);
 233         if (rc) {
 234                 PMD_DRV_LOG(ERR, "HWRM ring alloc failure rc: %x\n", rc);
 235                 goto err_out;
 236         }
 237
 238         rc = bnxt_alloc_all_hwrm_ring_grps(bp);
 239         if (rc) {
 240                 PMD_DRV_LOG(ERR, "HWRM ring grp alloc failure: %x\n", rc);
 241                 goto err_out;
 242         }
 243
 244         rc = bnxt_mq_rx_configure(bp);
 245         if (rc) {
 246                 PMD_DRV_LOG(ERR, "MQ mode configure failure rc: %x\n", rc);
 247                 goto err_out;
 248         }
 249
 250         /* VNIC configuration */
 251         for (i = 0; i < bp->nr_vnics; i++) {
 252                 struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
 253                 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
 254                 uint32_t size = sizeof(*vnic->fw_grp_ids) * bp->max_ring_grps;
 255
 256                 vnic->fw_grp_ids = rte_zmalloc("vnic_fw_grp_ids", size, 0);
 257                 if (!vnic->fw_grp_ids) {
 258                         PMD_DRV_LOG(ERR,
 259                                     "Failed to alloc %d bytes for group ids\n",
 260                                     size);
 261                         rc = -ENOMEM;
 262                         goto err_out;
 263                 }
 264                 memset(vnic->fw_grp_ids, -1, size);
 265
 266                 rc = bnxt_hwrm_vnic_alloc(bp, vnic);
 267                 if (rc) {
 268                         PMD_DRV_LOG(ERR, "HWRM vnic %d alloc failure rc: %x\n",
 269                                 i, rc);
 270                         goto err_out;
 271                 }
 272
 273                 /* Alloc RSS context only if RSS mode is enabled */
 274                 if (dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS) {
 275                         rc = bnxt_hwrm_vnic_ctx_alloc(bp, vnic);
 276                         if (rc) {
 277                                 PMD_DRV_LOG(ERR,
 278                                         "HWRM vnic %d ctx alloc failure rc: %x\n",
 279                                         i, rc);
 280                                 goto err_out;
 281                         }
 282                 }
 283
 284                 rc = bnxt_hwrm_vnic_cfg(bp, vnic);
 285                 if (rc) {
 286                         PMD_DRV_LOG(ERR, "HWRM vnic %d cfg failure rc: %x\n",
 287                                 i, rc);
 288                         goto err_out;
 289                 }
 290
 291                 rc = bnxt_set_hwrm_vnic_filters(bp, vnic);
 292                 if (rc) {
 293                         PMD_DRV_LOG(ERR,
 294                                 "HWRM vnic %d filter failure rc: %x\n",
 295                                 i, rc);
 296                         goto err_out;
 297                 }
 298
 299                 for (j = 0; j < bp->rx_nr_rings; j++) {
 300                         rxq = bp->eth_dev->data->rx_queues[j];
 301
 302                         if (rxq->rx_deferred_start)
 303                                 rxq->vnic->fw_grp_ids[j] = INVALID_HW_RING_ID;
 304                 }
 305
 306                 rc = bnxt_vnic_rss_configure(bp, vnic);
 307                 if (rc) {
 308                         PMD_DRV_LOG(ERR,
 309                                     "HWRM vnic set RSS failure rc: %x\n", rc);
 310                         goto err_out;
 311                 }
 312
 313                 bnxt_hwrm_vnic_plcmode_cfg(bp, vnic);
 314
 315                 if (bp->eth_dev->data->dev_conf.rxmode.offloads &
 316                     DEV_RX_OFFLOAD_TCP_LRO)
 317                         bnxt_hwrm_vnic_tpa_cfg(bp, vnic, 1);
 318                 else
 319                         bnxt_hwrm_vnic_tpa_cfg(bp, vnic, 0);
 320         }
 321         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, &bp->vnic_info[0], 0, NULL);
 322         if (rc) {
 323                 PMD_DRV_LOG(ERR,
 324                         "HWRM cfa l2 rx mask failure rc: %x\n", rc);
 325                 goto err_out;
 326         }
 327
 328         /* check and configure queue intr-vector mapping */
 329         if ((rte_intr_cap_multiple(intr_handle) ||
 330              !RTE_ETH_DEV_SRIOV(bp->eth_dev).active) &&
 331             bp->eth_dev->data->dev_conf.intr_conf.rxq != 0) {
 332                 intr_vector = bp->eth_dev->data->nb_rx_queues;
 333                 PMD_DRV_LOG(DEBUG, "intr_vector = %d\n", intr_vector);
 334                 if (intr_vector > bp->rx_cp_nr_rings) {
 335                         PMD_DRV_LOG(ERR, "At most %d intr queues supported",
 336                                         bp->rx_cp_nr_rings);
 337                         return -ENOTSUP;
 338                 }
 339                 if (rte_intr_efd_enable(intr_handle, intr_vector))
 340                         return -1;
 341         }
 342
 343         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
 344                 intr_handle->intr_vec =
 345                         rte_zmalloc("intr_vec",
 346                                     bp->eth_dev->data->nb_rx_queues *
 347                                     sizeof(int), 0);
 348                 if (intr_handle->intr_vec == NULL) {
 349                         PMD_DRV_LOG(ERR, "Failed to allocate %d rx_queues"
 350                                 " intr_vec", bp->eth_dev->data->nb_rx_queues);
 351                         return -ENOMEM;
 352                 }
 353                 PMD_DRV_LOG(DEBUG, "intr_handle->intr_vec = %p "
 354                         "intr_handle->nb_efd = %d intr_handle->max_intr = %d\n",
 355                          intr_handle->intr_vec, intr_handle->nb_efd,
 356                         intr_handle->max_intr);
 357         }
 358
 359         for (queue_id = 0; queue_id < bp->eth_dev->data->nb_rx_queues;
 360              queue_id++) {
 361                 intr_handle->intr_vec[queue_id] = vec;
 362                 if (vec < base + intr_handle->nb_efd - 1)
 363                         vec++;
 364         }
 365
 366         /* enable uio/vfio intr/eventfd mapping */
 367         rte_intr_enable(intr_handle);
 368
 369         rc = bnxt_get_hwrm_link_config(bp, &new);
 370         if (rc) {
 371                 PMD_DRV_LOG(ERR, "HWRM Get link config failure rc: %x\n", rc);
 372                 goto err_out;
 373         }
 374
 375         if (!bp->link_info.link_up) {
 376                 rc = bnxt_set_hwrm_link_config(bp, true);
 377                 if (rc) {
 378                         PMD_DRV_LOG(ERR,
 379                                 "HWRM link config failure rc: %x\n", rc);
 380                         goto err_out;
 381                 }
 382         }
 383         bnxt_print_link_info(bp->eth_dev);
 384
 385         return 0;
 386
 387 err_out:
 388         bnxt_free_all_hwrm_resources(bp);
 389
 390         /* Some of the error status returned by FW may not be from errno.h */
 391         if (rc > 0)
 392                 rc = -EIO;
 393
 394         return rc;
 395 }
 396
 397 static int bnxt_shutdown_nic(struct bnxt *bp)
 398 {
 399         bnxt_free_all_hwrm_resources(bp);
 400         bnxt_free_all_filters(bp);
 401         bnxt_free_all_vnics(bp);
 402         return 0;
 403 }
 404
 405 static int bnxt_init_nic(struct bnxt *bp)
 406 {
 407         int rc;
 408
 409         rc = bnxt_init_ring_grps(bp);
 410         if (rc)
 411                 return rc;
 412
 413         bnxt_init_vnics(bp);
 414         bnxt_init_filters(bp);
 415
 416         return 0;
 417 }
 418
 419 /*
 420  * Device configuration and status function
 421  */
 422
 423 static void bnxt_dev_info_get_op(struct rte_eth_dev *eth_dev,
 424                                   struct rte_eth_dev_info *dev_info)
 425 {
 426         struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
 427         uint16_t max_vnics, i, j, vpool, vrxq;
 428         unsigned int max_rx_rings;
 429
 430         /* MAC Specifics */
 431         dev_info->max_mac_addrs = bp->max_l2_ctx;
 432         dev_info->max_hash_mac_addrs = 0;
 433
 434         /* PF/VF specifics */
 435         if (BNXT_PF(bp))
 436                 dev_info->max_vfs = bp->pdev->max_vfs;
 437         max_rx_rings = RTE_MIN(bp->max_vnics, bp->max_stat_ctx);
 438         /* For the sake of symmetry, max_rx_queues = max_tx_queues */
 439         dev_info->max_rx_queues = max_rx_rings;
 440         dev_info->max_tx_queues = max_rx_rings;
 441         dev_info->reta_size = HW_HASH_INDEX_SIZE;
 442         dev_info->hash_key_size = 40;
 443         max_vnics = bp->max_vnics;
 444
 445         /* Fast path specifics */
 446         dev_info->min_rx_bufsize = 1;
 447         dev_info->max_rx_pktlen = BNXT_MAX_MTU + ETHER_HDR_LEN + ETHER_CRC_LEN
 448                                   + VLAN_TAG_SIZE;
 449
 450         dev_info->rx_offload_capa = BNXT_DEV_RX_OFFLOAD_SUPPORT;
 451         if (bp->flags & BNXT_FLAG_PTP_SUPPORTED)
 452                 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_TIMESTAMP;
 453         dev_info->tx_offload_capa = BNXT_DEV_TX_OFFLOAD_SUPPORT;
 454         dev_info->flow_type_rss_offloads = BNXT_ETH_RSS_SUPPORT;
 455
 456         /* *INDENT-OFF* */
 457         dev_info->default_rxconf = (struct rte_eth_rxconf) {
 458                 .rx_thresh = {
 459                         .pthresh = 8,
 460                         .hthresh = 8,
 461                         .wthresh = 0,
 462                 },
 463                 .rx_free_thresh = 32,
 464                 /* If no descriptors available, pkts are dropped by default */
 465                 .rx_drop_en = 1,
 466         };
 467
 468         dev_info->default_txconf = (struct rte_eth_txconf) {
 469                 .tx_thresh = {
 470                         .pthresh = 32,
 471                         .hthresh = 0,
 472                         .wthresh = 0,
 473                 },
 474                 .tx_free_thresh = 32,
 475                 .tx_rs_thresh = 32,
 476         };
 477         eth_dev->data->dev_conf.intr_conf.lsc = 1;
 478
 479         eth_dev->data->dev_conf.intr_conf.rxq = 1;
 480         dev_info->rx_desc_lim.nb_min = BNXT_MIN_RING_DESC;
 481         dev_info->rx_desc_lim.nb_max = BNXT_MAX_RX_RING_DESC;
 482         dev_info->tx_desc_lim.nb_min = BNXT_MIN_RING_DESC;
 483         dev_info->tx_desc_lim.nb_max = BNXT_MAX_TX_RING_DESC;
 484
 485         /* *INDENT-ON* */
 486
 487         /*
 488          * TODO: default_rxconf, default_txconf, rx_desc_lim, and tx_desc_lim
 489          *       need further investigation.
 490          */
 491
 492         /* VMDq resources */
 493         vpool = 64; /* ETH_64_POOLS */
 494         vrxq = 128; /* ETH_VMDQ_DCB_NUM_QUEUES */
 495         for (i = 0; i < 4; vpool >>= 1, i++) {
 496                 if (max_vnics > vpool) {
 497                         for (j = 0; j < 5; vrxq >>= 1, j++) {
 498                                 if (dev_info->max_rx_queues > vrxq) {
 499                                         if (vpool > vrxq)
 500                                                 vpool = vrxq;
 501                                         goto found;
 502                                 }
 503                         }
 504                         /* Not enough resources to support VMDq */
 505                         break;
 506                 }
 507         }
 508         /* Not enough resources to support VMDq */
 509         vpool = 0;
 510         vrxq = 0;
 511 found:
 512         dev_info->max_vmdq_pools = vpool;
 513         dev_info->vmdq_queue_num = vrxq;
 514
 515         dev_info->vmdq_pool_base = 0;
 516         dev_info->vmdq_queue_base = 0;
 517 }
 518
 519 /* Configure the device based on the configuration provided */
 520 static int bnxt_dev_configure_op(struct rte_eth_dev *eth_dev)
 521 {
 522         struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
 523         uint64_t rx_offloads = eth_dev->data->dev_conf.rxmode.offloads;
 524         int rc;
 525
 526         bp->rx_queues = (void *)eth_dev->data->rx_queues;
 527         bp->tx_queues = (void *)eth_dev->data->tx_queues;
 528         bp->tx_nr_rings = eth_dev->data->nb_tx_queues;
 529         bp->rx_nr_rings = eth_dev->data->nb_rx_queues;
 530
 531         if (BNXT_VF(bp) && (bp->flags & BNXT_FLAG_NEW_RM)) {
 532                 rc = bnxt_hwrm_check_vf_rings(bp);
 533                 if (rc) {
 534                         PMD_DRV_LOG(ERR, "HWRM insufficient resources\n");
 535                         return -ENOSPC;
 536                 }
 537
 538                 rc = bnxt_hwrm_func_reserve_vf_resc(bp, false);
 539                 if (rc) {
 540                         PMD_DRV_LOG(ERR, "HWRM resource alloc fail:%x\n", rc);
 541                         return -ENOSPC;
 542                 }
 543         } else {
 544                 /* legacy driver needs to get updated values */
 545                 rc = bnxt_hwrm_func_qcaps(bp);
 546                 if (rc) {
 547                         PMD_DRV_LOG(ERR, "hwrm func qcaps fail:%d\n", rc);
 548                         return rc;
 549                 }
 550         }
 551
 552         /* Inherit new configurations */
 553         if (eth_dev->data->nb_rx_queues > bp->max_rx_rings ||
 554             eth_dev->data->nb_tx_queues > bp->max_tx_rings ||
 555             eth_dev->data->nb_rx_queues + eth_dev->data->nb_tx_queues >
 556             bp->max_cp_rings ||
 557             eth_dev->data->nb_rx_queues + eth_dev->data->nb_tx_queues >
 558             bp->max_stat_ctx ||
 559             (uint32_t)(eth_dev->data->nb_rx_queues) > bp->max_ring_grps ||
 560             (!(eth_dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS) &&
 561              bp->max_vnics < eth_dev->data->nb_rx_queues)) {
 562                 PMD_DRV_LOG(ERR,
 563                         "Insufficient resources to support requested config\n");
 564                 PMD_DRV_LOG(ERR,
 565                         "Num Queues Requested: Tx %d, Rx %d\n",
 566                         eth_dev->data->nb_tx_queues,
 567                         eth_dev->data->nb_rx_queues);
 568                 PMD_DRV_LOG(ERR,
 569                         "MAX: TxQ %d, RxQ %d, CQ %d Stat %d, Grp %d, Vnic %d\n",
 570                         bp->max_tx_rings, bp->max_rx_rings, bp->max_cp_rings,
 571                         bp->max_stat_ctx, bp->max_ring_grps, bp->max_vnics);
 572                 return -ENOSPC;
 573         }
 574
 575         bp->rx_cp_nr_rings = bp->rx_nr_rings;
 576         bp->tx_cp_nr_rings = bp->tx_nr_rings;
 577
 578         if (rx_offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) {
 579                 eth_dev->data->mtu =
 580                                 eth_dev->data->dev_conf.rxmode.max_rx_pkt_len -
 581                                 ETHER_HDR_LEN - ETHER_CRC_LEN - VLAN_TAG_SIZE *
 582                                 BNXT_NUM_VLANS;
 583                 bnxt_mtu_set_op(eth_dev, eth_dev->data->mtu);
 584         }
 585         return 0;
 586 }
 587
 588 static void bnxt_print_link_info(struct rte_eth_dev *eth_dev)
 589 {
 590         struct rte_eth_link *link = &eth_dev->data->dev_link;
 591
 592         if (link->link_status)
 593                 PMD_DRV_LOG(INFO, "Port %d Link Up - speed %u Mbps - %s\n",
 594                         eth_dev->data->port_id,
 595                         (uint32_t)link->link_speed,
 596                         (link->link_duplex == ETH_LINK_FULL_DUPLEX) ?
 597                         ("full-duplex") : ("half-duplex\n"));
 598         else
 599                 PMD_DRV_LOG(INFO, "Port %d Link Down\n",
 600                         eth_dev->data->port_id);
 601 }
 602
 603 static int bnxt_dev_lsc_intr_setup(struct rte_eth_dev *eth_dev)
 604 {
 605         bnxt_print_link_info(eth_dev);
 606         return 0;
 607 }
 608
 609 static int bnxt_dev_start_op(struct rte_eth_dev *eth_dev)
 610 {
 611         struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
 612         uint64_t rx_offloads = eth_dev->data->dev_conf.rxmode.offloads;
 613         int vlan_mask = 0;
 614         int rc;
 615
 616         if (bp->rx_cp_nr_rings > RTE_ETHDEV_QUEUE_STAT_CNTRS) {
 617                 PMD_DRV_LOG(ERR,
 618                         "RxQ cnt %d > CONFIG_RTE_ETHDEV_QUEUE_STAT_CNTRS %d\n",
 619                         bp->rx_cp_nr_rings, RTE_ETHDEV_QUEUE_STAT_CNTRS);
 620         }
 621         bp->dev_stopped = 0;
 622
 623         rc = bnxt_init_chip(bp);
 624         if (rc)
 625                 goto error;
 626
 627         bnxt_link_update_op(eth_dev, 1);
 628
 629         if (rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
 630                 vlan_mask |= ETH_VLAN_FILTER_MASK;
 631         if (rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
 632                 vlan_mask |= ETH_VLAN_STRIP_MASK;
 633         rc = bnxt_vlan_offload_set_op(eth_dev, vlan_mask);
 634         if (rc)
 635                 goto error;
 636
 637         bp->flags |= BNXT_FLAG_INIT_DONE;
 638         return 0;
 639
 640 error:
 641         bnxt_shutdown_nic(bp);
 642         bnxt_free_tx_mbufs(bp);
 643         bnxt_free_rx_mbufs(bp);
 644         return rc;
 645 }
 646
 647 static int bnxt_dev_set_link_up_op(struct rte_eth_dev *eth_dev)
 648 {
 649         struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
 650         int rc = 0;
 651
 652         if (!bp->link_info.link_up)
 653                 rc = bnxt_set_hwrm_link_config(bp, true);
 654         if (!rc)
 655                 eth_dev->data->dev_link.link_status = 1;
 656
 657         bnxt_print_link_info(eth_dev);
 658         return 0;
 659 }
 660
 661 static int bnxt_dev_set_link_down_op(struct rte_eth_dev *eth_dev)
 662 {
 663         struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
 664
 665         eth_dev->data->dev_link.link_status = 0;
 666         bnxt_set_hwrm_link_config(bp, false);
 667         bp->link_info.link_up = 0;
 668
 669         return 0;
 670 }
 671
 672 /* Unload the driver, release resources */
 673 static void bnxt_dev_stop_op(struct rte_eth_dev *eth_dev)
 674 {
 675         struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
 676
 677         bp->flags &= ~BNXT_FLAG_INIT_DONE;
 678         if (bp->eth_dev->data->dev_started) {
 679                 /* TBD: STOP HW queues DMA */
 680                 eth_dev->data->dev_link.link_status = 0;
 681         }
 682         bnxt_set_hwrm_link_config(bp, false);
 683         bnxt_hwrm_port_clr_stats(bp);
 684         bnxt_free_tx_mbufs(bp);
 685         bnxt_free_rx_mbufs(bp);
 686         bnxt_shutdown_nic(bp);
 687         bp->dev_stopped = 1;
 688 }
 689
 690 static void bnxt_dev_close_op(struct rte_eth_dev *eth_dev)
 691 {
 692         struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
 693
 694         if (bp->dev_stopped == 0)
 695                 bnxt_dev_stop_op(eth_dev);
 696
 697         bnxt_free_mem(bp);
 698         if (eth_dev->data->mac_addrs != NULL) {
 699                 rte_free(eth_dev->data->mac_addrs);
 700                 eth_dev->data->mac_addrs = NULL;
 701         }
 702         if (bp->grp_info != NULL) {
 703                 rte_free(bp->grp_info);
 704                 bp->grp_info = NULL;
 705         }
 706
 707         bnxt_dev_uninit(eth_dev);
 708 }
 709
 710 static void bnxt_mac_addr_remove_op(struct rte_eth_dev *eth_dev,
 711                                     uint32_t index)
 712 {
 713         struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
 714         uint64_t pool_mask = eth_dev->data->mac_pool_sel[index];
 715         struct bnxt_vnic_info *vnic;
 716         struct bnxt_filter_info *filter, *temp_filter;
 717         uint32_t pool = RTE_MIN(MAX_FF_POOLS, ETH_64_POOLS);
 718         uint32_t i;
 719
 720         /*
 721          * Loop through all VNICs from the specified filter flow pools to
 722          * remove the corresponding MAC addr filter
 723          */
 724         for (i = 0; i < pool; i++) {
 725                 if (!(pool_mask & (1ULL << i)))
 726                         continue;
 727
 728                 STAILQ_FOREACH(vnic, &bp->ff_pool[i], next) {
 729                         filter = STAILQ_FIRST(&vnic->filter);
 730                         while (filter) {
 731                                 temp_filter = STAILQ_NEXT(filter, next);
 732                                 if (filter->mac_index == index) {
 733                                         STAILQ_REMOVE(&vnic->filter, filter,
 734                                                       bnxt_filter_info, next);
 735                                         bnxt_hwrm_clear_l2_filter(bp, filter);
 736                                         filter->mac_index = INVALID_MAC_INDEX;
 737                                         memset(&filter->l2_addr, 0,
 738                                                ETHER_ADDR_LEN);
 739                                         STAILQ_INSERT_TAIL(
 740                                                         &bp->free_filter_list,
 741                                                         filter, next);
 742                                 }
 743                                 filter = temp_filter;
 744                         }
 745                 }
 746         }
 747 }
 748
 749 static int bnxt_mac_addr_add_op(struct rte_eth_dev *eth_dev,
 750                                 struct ether_addr *mac_addr,
 751                                 uint32_t index, uint32_t pool)
 752 {
 753         struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
 754         struct bnxt_vnic_info *vnic = STAILQ_FIRST(&bp->ff_pool[pool]);
 755         struct bnxt_filter_info *filter;
 756
 757         if (BNXT_VF(bp)) {
 758                 PMD_DRV_LOG(ERR, "Cannot add MAC address to a VF interface\n");
 759                 return -ENOTSUP;
 760         }
 761
 762         if (!vnic) {
 763                 PMD_DRV_LOG(ERR, "VNIC not found for pool %d!\n", pool);
 764                 return -EINVAL;
 765         }
 766         /* Attach requested MAC address to the new l2_filter */
 767         STAILQ_FOREACH(filter, &vnic->filter, next) {
 768                 if (filter->mac_index == index) {
 769                         PMD_DRV_LOG(ERR,
 770                                 "MAC addr already existed for pool %d\n", pool);
 771                         return 0;
 772                 }
 773         }
 774         filter = bnxt_alloc_filter(bp);
 775         if (!filter) {
 776                 PMD_DRV_LOG(ERR, "L2 filter alloc failed\n");
 777                 return -ENODEV;
 778         }
 779         STAILQ_INSERT_TAIL(&vnic->filter, filter, next);
 780         filter->mac_index = index;
 781         memcpy(filter->l2_addr, mac_addr, ETHER_ADDR_LEN);
 782         return bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id, filter);
 783 }
 784
 785 int bnxt_link_update_op(struct rte_eth_dev *eth_dev, int wait_to_complete)
 786 {
 787         int rc = 0;
 788         struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
 789         struct rte_eth_link new;
 790         unsigned int cnt = BNXT_LINK_WAIT_CNT;
 791
 792         memset(&new, 0, sizeof(new));
 793         do {
 794                 /* Retrieve link info from hardware */
 795                 rc = bnxt_get_hwrm_link_config(bp, &new);
 796                 if (rc) {
 797                         new.link_speed = ETH_LINK_SPEED_100M;
 798                         new.link_duplex = ETH_LINK_FULL_DUPLEX;
 799                         PMD_DRV_LOG(ERR,
 800                                 "Failed to retrieve link rc = 0x%x!\n", rc);
 801                         goto out;
 802                 }
 803                 rte_delay_ms(BNXT_LINK_WAIT_INTERVAL);
 804
 805                 if (!wait_to_complete)
 806                         break;
 807         } while (!new.link_status && cnt--);
 808
 809 out:
 810         /* Timed out or success */
 811         if (new.link_status != eth_dev->data->dev_link.link_status ||
 812         new.link_speed != eth_dev->data->dev_link.link_speed) {
 813                 memcpy(&eth_dev->data->dev_link, &new,
 814                         sizeof(struct rte_eth_link));
 815
 816                 _rte_eth_dev_callback_process(eth_dev,
 817                                               RTE_ETH_EVENT_INTR_LSC,
 818                                               NULL);
 819
 820                 bnxt_print_link_info(eth_dev);
 821         }
 822
 823         return rc;
 824 }
 825
 826 static void bnxt_promiscuous_enable_op(struct rte_eth_dev *eth_dev)
 827 {
 828         struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
 829         struct bnxt_vnic_info *vnic;
 830
 831         if (bp->vnic_info == NULL)
 832                 return;
 833
 834         vnic = &bp->vnic_info[0];
 835
 836         vnic->flags |= BNXT_VNIC_INFO_PROMISC;
 837         bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
 838 }
 839
 840 static void bnxt_promiscuous_disable_op(struct rte_eth_dev *eth_dev)
 841 {
 842         struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
 843         struct bnxt_vnic_info *vnic;
 844
 845         if (bp->vnic_info == NULL)
 846                 return;
 847
 848         vnic = &bp->vnic_info[0];
 849
 850         vnic->flags &= ~BNXT_VNIC_INFO_PROMISC;
 851         bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
 852 }
 853
 854 static void bnxt_allmulticast_enable_op(struct rte_eth_dev *eth_dev)
 855 {
 856         struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
 857         struct bnxt_vnic_info *vnic;
 858
 859         if (bp->vnic_info == NULL)
 860                 return;
 861
 862         vnic = &bp->vnic_info[0];
 863
 864         vnic->flags |= BNXT_VNIC_INFO_ALLMULTI;
 865         bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
 866 }
 867
 868 static void bnxt_allmulticast_disable_op(struct rte_eth_dev *eth_dev)
 869 {
 870         struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
 871         struct bnxt_vnic_info *vnic;
 872
 873         if (bp->vnic_info == NULL)
 874                 return;
 875
 876         vnic = &bp->vnic_info[0];
 877
 878         vnic->flags &= ~BNXT_VNIC_INFO_ALLMULTI;
 879         bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
 880 }
 881
 882 static int bnxt_reta_update_op(struct rte_eth_dev *eth_dev,
 883                             struct rte_eth_rss_reta_entry64 *reta_conf,
 884                             uint16_t reta_size)
 885 {
 886         struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
 887         struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
 888         struct bnxt_vnic_info *vnic;
 889         int i;
 890
 891         if (!(dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG))
 892                 return -EINVAL;
 893
 894         if (reta_size != HW_HASH_INDEX_SIZE) {
 895                 PMD_DRV_LOG(ERR, "The configured hash table lookup size "
 896                         "(%d) must equal the size supported by the hardware "
 897                         "(%d)\n", reta_size, HW_HASH_INDEX_SIZE);
 898                 return -EINVAL;
 899         }
 900         /* Update the RSS VNIC(s) */
 901         for (i = 0; i < MAX_FF_POOLS; i++) {
 902                 STAILQ_FOREACH(vnic, &bp->ff_pool[i], next) {
 903                         memcpy(vnic->rss_table, reta_conf, reta_size);
 904
 905                         bnxt_hwrm_vnic_rss_cfg(bp, vnic);
 906                 }
 907         }
 908         return 0;
 909 }
 910
 911 static int bnxt_reta_query_op(struct rte_eth_dev *eth_dev,
 912                               struct rte_eth_rss_reta_entry64 *reta_conf,
 913                               uint16_t reta_size)
 914 {
 915         struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
 916         struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
 917         struct rte_intr_handle *intr_handle
 918                 = &bp->pdev->intr_handle;
 919
 920         /* Retrieve from the default VNIC */
 921         if (!vnic)
 922                 return -EINVAL;
 923         if (!vnic->rss_table)
 924                 return -EINVAL;
 925
 926         if (reta_size != HW_HASH_INDEX_SIZE) {
 927                 PMD_DRV_LOG(ERR, "The configured hash table lookup size "
 928                         "(%d) must equal the size supported by the hardware "
 929                         "(%d)\n", reta_size, HW_HASH_INDEX_SIZE);
 930                 return -EINVAL;
 931         }
 932         /* EW - need to revisit here copying from uint64_t to uint16_t */
 933         memcpy(reta_conf, vnic->rss_table, reta_size);
 934
 935         if (rte_intr_allow_others(intr_handle)) {
 936                 if (eth_dev->data->dev_conf.intr_conf.lsc != 0)
 937                         bnxt_dev_lsc_intr_setup(eth_dev);
 938         }
 939
 940         return 0;
 941 }
 942
 943 static int bnxt_rss_hash_update_op(struct rte_eth_dev *eth_dev,
 944                                    struct rte_eth_rss_conf *rss_conf)
 945 {
 946         struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
 947         struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
 948         struct bnxt_vnic_info *vnic;
 949         uint16_t hash_type = 0;
 950         int i;
 951
 952         /*
 953          * If RSS enablement were different than dev_configure,
 954          * then return -EINVAL
 955          */
 956         if (dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG) {
 957                 if (!rss_conf->rss_hf)
 958                         PMD_DRV_LOG(ERR, "Hash type NONE\n");
 959         } else {
 960                 if (rss_conf->rss_hf & BNXT_ETH_RSS_SUPPORT)
 961                         return -EINVAL;
 962         }
 963
 964         bp->flags |= BNXT_FLAG_UPDATE_HASH;
 965         memcpy(&bp->rss_conf, rss_conf, sizeof(*rss_conf));
 966
 967         if (rss_conf->rss_hf & ETH_RSS_IPV4)
 968                 hash_type |= HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4;
 969         if (rss_conf->rss_hf & ETH_RSS_NONFRAG_IPV4_TCP)
 970                 hash_type |= HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4;
 971         if (rss_conf->rss_hf & ETH_RSS_NONFRAG_IPV4_UDP)
 972                 hash_type |= HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4;
 973         if (rss_conf->rss_hf & ETH_RSS_IPV6)
 974                 hash_type |= HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6;
 975         if (rss_conf->rss_hf & ETH_RSS_NONFRAG_IPV6_TCP)
 976                 hash_type |= HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6;
 977         if (rss_conf->rss_hf & ETH_RSS_NONFRAG_IPV6_UDP)
 978                 hash_type |= HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6;
 979
 980         /* Update the RSS VNIC(s) */
 981         for (i = 0; i < MAX_FF_POOLS; i++) {
 982                 STAILQ_FOREACH(vnic, &bp->ff_pool[i], next) {
 983                         vnic->hash_type = hash_type;
 984
 985                         /*
 986                          * Use the supplied key if the key length is
 987                          * acceptable and the rss_key is not NULL
 988                          */
 989                         if (rss_conf->rss_key &&
 990                             rss_conf->rss_key_len <= HW_HASH_KEY_SIZE)
 991                                 memcpy(vnic->rss_hash_key, rss_conf->rss_key,
 992                                        rss_conf->rss_key_len);
 993
 994                         bnxt_hwrm_vnic_rss_cfg(bp, vnic);
 995                 }
 996         }
 997         return 0;
 998 }
 999
1000 static int bnxt_rss_hash_conf_get_op(struct rte_eth_dev *eth_dev,
1001                                      struct rte_eth_rss_conf *rss_conf)
1002 {
1003         struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
1004         struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
1005         int len;
1006         uint32_t hash_types;
1007
1008         /* RSS configuration is the same for all VNICs */
1009         if (vnic && vnic->rss_hash_key) {
1010                 if (rss_conf->rss_key) {
1011                         len = rss_conf->rss_key_len <= HW_HASH_KEY_SIZE ?
1012                               rss_conf->rss_key_len : HW_HASH_KEY_SIZE;
1013                         memcpy(rss_conf->rss_key, vnic->rss_hash_key, len);
1014                 }
1015
1016                 hash_types = vnic->hash_type;
1017                 rss_conf->rss_hf = 0;
1018                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4) {
1019                         rss_conf->rss_hf |= ETH_RSS_IPV4;
1020                         hash_types &= ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4;
1021                 }
1022                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4) {
1023                         rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
1024                         hash_types &=
1025                                 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4;
1026                 }
1027                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4) {
1028                         rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
1029                         hash_types &=
1030                                 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4;
1031                 }
1032                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6) {
1033                         rss_conf->rss_hf |= ETH_RSS_IPV6;
1034                         hash_types &= ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6;
1035                 }
1036                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6) {
1037                         rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
1038                         hash_types &=
1039                                 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6;
1040                 }
1041                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6) {
1042                         rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
1043                         hash_types &=
1044                                 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6;
1045                 }
1046                 if (hash_types) {
1047                         PMD_DRV_LOG(ERR,
1048                                 "Unknwon RSS config from firmware (%08x), RSS disabled",
1049                                 vnic->hash_type);
1050                         return -ENOTSUP;
1051                 }
1052         } else {
1053                 rss_conf->rss_hf = 0;
1054         }
1055         return 0;
1056 }
1057
1058 static int bnxt_flow_ctrl_get_op(struct rte_eth_dev *dev,
1059                                struct rte_eth_fc_conf *fc_conf)
1060 {
1061         struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
1062         struct rte_eth_link link_info;
1063         int rc;
1064
1065         rc = bnxt_get_hwrm_link_config(bp, &link_info);
1066         if (rc)
1067                 return rc;
1068
1069         memset(fc_conf, 0, sizeof(*fc_conf));
1070         if (bp->link_info.auto_pause)
1071                 fc_conf->autoneg = 1;
1072         switch (bp->link_info.pause) {
1073         case 0:
1074                 fc_conf->mode = RTE_FC_NONE;
1075                 break;
1076         case HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_TX:
1077                 fc_conf->mode = RTE_FC_TX_PAUSE;
1078                 break;
1079         case HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_RX:
1080                 fc_conf->mode = RTE_FC_RX_PAUSE;
1081                 break;
1082         case (HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_TX |
1083                         HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_RX):
1084                 fc_conf->mode = RTE_FC_FULL;
1085                 break;
1086         }
1087         return 0;
1088 }
1089
1090 static int bnxt_flow_ctrl_set_op(struct rte_eth_dev *dev,
1091                                struct rte_eth_fc_conf *fc_conf)
1092 {
1093         struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
1094
1095         if (!BNXT_SINGLE_PF(bp) || BNXT_VF(bp)) {
1096                 PMD_DRV_LOG(ERR, "Flow Control Settings cannot be modified\n");
1097                 return -ENOTSUP;
1098         }
1099
1100         switch (fc_conf->mode) {
1101         case RTE_FC_NONE:
1102                 bp->link_info.auto_pause = 0;
1103                 bp->link_info.force_pause = 0;
1104                 break;
1105         case RTE_FC_RX_PAUSE:
1106                 if (fc_conf->autoneg) {
1107                         bp->link_info.auto_pause =
1108                                         HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_RX;
1109                         bp->link_info.force_pause = 0;
1110                 } else {
1111                         bp->link_info.auto_pause = 0;
1112                         bp->link_info.force_pause =
1113                                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_RX;
1114                 }
1115                 break;
1116         case RTE_FC_TX_PAUSE:
1117                 if (fc_conf->autoneg) {
1118                         bp->link_info.auto_pause =
1119                                         HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_TX;
1120                         bp->link_info.force_pause = 0;
1121                 } else {
1122                         bp->link_info.auto_pause = 0;
1123                         bp->link_info.force_pause =
1124                                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_TX;
1125                 }
1126                 break;
1127         case RTE_FC_FULL:
1128                 if (fc_conf->autoneg) {
1129                         bp->link_info.auto_pause =
1130                                         HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_TX |
1131                                         HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_RX;
1132                         bp->link_info.force_pause = 0;
1133                 } else {
1134                         bp->link_info.auto_pause = 0;
1135                         bp->link_info.force_pause =
1136                                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_TX |
1137                                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_RX;
1138                 }
1139                 break;
1140         }
1141         return bnxt_set_hwrm_link_config(bp, true);
1142 }
1143
1144 /* Add UDP tunneling port */
1145 static int
1146 bnxt_udp_tunnel_port_add_op(struct rte_eth_dev *eth_dev,
1147                          struct rte_eth_udp_tunnel *udp_tunnel)
1148 {
1149         struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
1150         uint16_t tunnel_type = 0;
1151         int rc = 0;
1152
1153         switch (udp_tunnel->prot_type) {
1154         case RTE_TUNNEL_TYPE_VXLAN:
1155                 if (bp->vxlan_port_cnt) {
1156                         PMD_DRV_LOG(ERR, "Tunnel Port %d already programmed\n",
1157                                 udp_tunnel->udp_port);
1158                         if (bp->vxlan_port != udp_tunnel->udp_port) {
1159                                 PMD_DRV_LOG(ERR, "Only one port allowed\n");
1160                                 return -ENOSPC;
1161                         }
1162                         bp->vxlan_port_cnt++;
1163                         return 0;
1164                 }
1165                 tunnel_type =
1166                         HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN;
1167                 bp->vxlan_port_cnt++;
1168                 break;
1169         case RTE_TUNNEL_TYPE_GENEVE:
1170                 if (bp->geneve_port_cnt) {
1171                         PMD_DRV_LOG(ERR, "Tunnel Port %d already programmed\n",
1172                                 udp_tunnel->udp_port);
1173                         if (bp->geneve_port != udp_tunnel->udp_port) {
1174                                 PMD_DRV_LOG(ERR, "Only one port allowed\n");
1175                                 return -ENOSPC;
1176                         }
1177                         bp->geneve_port_cnt++;
1178                         return 0;
1179                 }
1180                 tunnel_type =
1181                         HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_GENEVE;
1182                 bp->geneve_port_cnt++;
1183                 break;
1184         default:
1185                 PMD_DRV_LOG(ERR, "Tunnel type is not supported\n");
1186                 return -ENOTSUP;
1187         }
1188         rc = bnxt_hwrm_tunnel_dst_port_alloc(bp, udp_tunnel->udp_port,
1189                                              tunnel_type);
1190         return rc;
1191 }
1192
1193 static int
1194 bnxt_udp_tunnel_port_del_op(struct rte_eth_dev *eth_dev,
1195                          struct rte_eth_udp_tunnel *udp_tunnel)
1196 {
1197         struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
1198         uint16_t tunnel_type = 0;
1199         uint16_t port = 0;
1200         int rc = 0;
1201
1202         switch (udp_tunnel->prot_type) {
1203         case RTE_TUNNEL_TYPE_VXLAN:
1204                 if (!bp->vxlan_port_cnt) {
1205                         PMD_DRV_LOG(ERR, "No Tunnel port configured yet\n");
1206                         return -EINVAL;
1207                 }
1208                 if (bp->vxlan_port != udp_tunnel->udp_port) {
1209                         PMD_DRV_LOG(ERR, "Req Port: %d. Configured port: %d\n",
1210                                 udp_tunnel->udp_port, bp->vxlan_port);
1211                         return -EINVAL;
1212                 }
1213                 if (--bp->vxlan_port_cnt)
1214                         return 0;
1215
1216                 tunnel_type =
1217                         HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN;
1218                 port = bp->vxlan_fw_dst_port_id;
1219                 break;
1220         case RTE_TUNNEL_TYPE_GENEVE:
1221                 if (!bp->geneve_port_cnt) {
1222                         PMD_DRV_LOG(ERR, "No Tunnel port configured yet\n");
1223                         return -EINVAL;
1224                 }
1225                 if (bp->geneve_port != udp_tunnel->udp_port) {
1226                         PMD_DRV_LOG(ERR, "Req Port: %d. Configured port: %d\n",
1227                                 udp_tunnel->udp_port, bp->geneve_port);
1228                         return -EINVAL;
1229                 }
1230                 if (--bp->geneve_port_cnt)
1231                         return 0;
1232
1233                 tunnel_type =
1234                         HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE;
1235                 port = bp->geneve_fw_dst_port_id;
1236                 break;
1237         default:
1238                 PMD_DRV_LOG(ERR, "Tunnel type is not supported\n");
1239                 return -ENOTSUP;
1240         }
1241
1242         rc = bnxt_hwrm_tunnel_dst_port_free(bp, port, tunnel_type);
1243         if (!rc) {
1244                 if (tunnel_type ==
1245                     HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN)
1246                         bp->vxlan_port = 0;
1247                 if (tunnel_type ==
1248                     HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE)
1249                         bp->geneve_port = 0;
1250         }
1251         return rc;
1252 }
1253
1254 static int bnxt_del_vlan_filter(struct bnxt *bp, uint16_t vlan_id)
1255 {
1256         struct bnxt_filter_info *filter, *temp_filter, *new_filter;
1257         struct bnxt_vnic_info *vnic;
1258         unsigned int i;
1259         int rc = 0;
1260         uint32_t chk = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN;
1261
1262         /* Cycle through all VNICs */
1263         for (i = 0; i < bp->nr_vnics; i++) {
1264                 /*
1265                  * For each VNIC and each associated filter(s)
1266                  * if VLAN exists && VLAN matches vlan_id
1267                  *      remove the MAC+VLAN filter
1268                  *      add a new MAC only filter
1269                  * else
1270                  *      VLAN filter doesn't exist, just skip and continue
1271                  */
1272                 STAILQ_FOREACH(vnic, &bp->ff_pool[i], next) {
1273                         filter = STAILQ_FIRST(&vnic->filter);
1274                         while (filter) {
1275                                 temp_filter = STAILQ_NEXT(filter, next);
1276
1277                                 if (filter->enables & chk &&
1278                                     filter->l2_ovlan == vlan_id) {
1279                                         /* Must delete the filter */
1280                                         STAILQ_REMOVE(&vnic->filter, filter,
1281                                                       bnxt_filter_info, next);
1282                                         bnxt_hwrm_clear_l2_filter(bp, filter);
1283                                         STAILQ_INSERT_TAIL(
1284                                                         &bp->free_filter_list,
1285                                                         filter, next);
1286
1287                                         /*
1288                                          * Need to examine to see if the MAC
1289                                          * filter already existed or not before
1290                                          * allocating a new one
1291                                          */
1292
1293                                         new_filter = bnxt_alloc_filter(bp);
1294                                         if (!new_filter) {
1295                                                 PMD_DRV_LOG(ERR,
1296                                                         "MAC/VLAN filter alloc failed\n");
1297                                                 rc = -ENOMEM;
1298                                                 goto exit;
1299                                         }
1300                                         STAILQ_INSERT_TAIL(&vnic->filter,
1301                                                            new_filter, next);
1302                                         /* Inherit MAC from previous filter */
1303                                         new_filter->mac_index =
1304                                                         filter->mac_index;
1305                                         memcpy(new_filter->l2_addr,
1306                                                filter->l2_addr, ETHER_ADDR_LEN);
1307                                         /* MAC only filter */
1308                                         rc = bnxt_hwrm_set_l2_filter(bp,
1309                                                         vnic->fw_vnic_id,
1310                                                         new_filter);
1311                                         if (rc)
1312                                                 goto exit;
1313                                         PMD_DRV_LOG(INFO,
1314                                                 "Del Vlan filter for %d\n",
1315                                                 vlan_id);
1316                                 }
1317                                 filter = temp_filter;
1318                         }
1319                 }
1320         }
1321 exit:
1322         return rc;
1323 }
1324
1325 static int bnxt_add_vlan_filter(struct bnxt *bp, uint16_t vlan_id)
1326 {
1327         struct bnxt_filter_info *filter, *temp_filter, *new_filter;
1328         struct bnxt_vnic_info *vnic;
1329         unsigned int i;
1330         int rc = 0;
1331         uint32_t en = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN |
1332                 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN_MASK;
1333         uint32_t chk = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN;
1334
1335         /* Cycle through all VNICs */
1336         for (i = 0; i < bp->nr_vnics; i++) {
1337                 /*
1338                  * For each VNIC and each associated filter(s)
1339                  * if VLAN exists:
1340                  *   if VLAN matches vlan_id
1341                  *      VLAN filter already exists, just skip and continue
1342                  *   else
1343                  *      add a new MAC+VLAN filter
1344                  * else
1345                  *   Remove the old MAC only filter
1346                  *    Add a new MAC+VLAN filter
1347                  */
1348                 STAILQ_FOREACH(vnic, &bp->ff_pool[i], next) {
1349                         filter = STAILQ_FIRST(&vnic->filter);
1350                         while (filter) {
1351                                 temp_filter = STAILQ_NEXT(filter, next);
1352
1353                                 if (filter->enables & chk) {
1354                                         if (filter->l2_ovlan == vlan_id)
1355                                                 goto cont;
1356                                 } else {
1357                                         /* Must delete the MAC filter */
1358                                         STAILQ_REMOVE(&vnic->filter, filter,
1359                                                       bnxt_filter_info, next);
1360                                         bnxt_hwrm_clear_l2_filter(bp, filter);
1361                                         filter->l2_ovlan = 0;
1362                                         STAILQ_INSERT_TAIL(
1363                                                         &bp->free_filter_list,
1364                                                         filter, next);
1365                                 }
1366                                 new_filter = bnxt_alloc_filter(bp);
1367                                 if (!new_filter) {
1368                                         PMD_DRV_LOG(ERR,
1369                                                 "MAC/VLAN filter alloc failed\n");
1370                                         rc = -ENOMEM;
1371                                         goto exit;
1372                                 }
1373                                 STAILQ_INSERT_TAIL(&vnic->filter, new_filter,
1374                                                    next);
1375                                 /* Inherit MAC from the previous filter */
1376                                 new_filter->mac_index = filter->mac_index;
1377                                 memcpy(new_filter->l2_addr, filter->l2_addr,
1378                                        ETHER_ADDR_LEN);
1379                                 /* MAC + VLAN ID filter */
1380                                 new_filter->l2_ivlan = vlan_id;
1381                                 new_filter->l2_ivlan_mask = 0xF000;
1382                                 new_filter->enables |= en;
1383                                 rc = bnxt_hwrm_set_l2_filter(bp,
1384                                                              vnic->fw_vnic_id,
1385                                                              new_filter);
1386                                 if (rc)
1387                                         goto exit;
1388                                 PMD_DRV_LOG(INFO,
1389                                         "Added Vlan filter for %d\n", vlan_id);
1390 cont:
1391                                 filter = temp_filter;
1392                         }
1393                 }
1394         }
1395 exit:
1396         return rc;
1397 }
1398
1399 static int bnxt_vlan_filter_set_op(struct rte_eth_dev *eth_dev,
1400                                    uint16_t vlan_id, int on)
1401 {
1402         struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
1403
1404         /* These operations apply to ALL existing MAC/VLAN filters */
1405         if (on)
1406                 return bnxt_add_vlan_filter(bp, vlan_id);
1407         else
1408                 return bnxt_del_vlan_filter(bp, vlan_id);
1409 }
1410
1411 static int
1412 bnxt_vlan_offload_set_op(struct rte_eth_dev *dev, int mask)
1413 {
1414         struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
1415         uint64_t rx_offloads = dev->data->dev_conf.rxmode.offloads;
1416         unsigned int i;
1417
1418         if (mask & ETH_VLAN_FILTER_MASK) {
1419                 if (!(rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER)) {
1420                         /* Remove any VLAN filters programmed */
1421                         for (i = 0; i < 4095; i++)
1422                                 bnxt_del_vlan_filter(bp, i);
1423                 }
1424                 PMD_DRV_LOG(DEBUG, "VLAN Filtering: %d\n",
1425                         !!(rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER));
1426         }
1427
1428         if (mask & ETH_VLAN_STRIP_MASK) {
1429                 /* Enable or disable VLAN stripping */
1430                 for (i = 0; i < bp->nr_vnics; i++) {
1431                         struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
1432                         if (rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
1433                                 vnic->vlan_strip = true;
1434                         else
1435                                 vnic->vlan_strip = false;
1436                         bnxt_hwrm_vnic_cfg(bp, vnic);
1437                 }
1438                 PMD_DRV_LOG(DEBUG, "VLAN Strip Offload: %d\n",
1439                         !!(rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP));
1440         }
1441
1442         if (mask & ETH_VLAN_EXTEND_MASK)
1443                 PMD_DRV_LOG(ERR, "Extend VLAN Not supported\n");
1444
1445         return 0;
1446 }
1447
1448 static int
1449 bnxt_set_default_mac_addr_op(struct rte_eth_dev *dev, struct ether_addr *addr)
1450 {
1451         struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
1452         /* Default Filter is tied to VNIC 0 */
1453         struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
1454         struct bnxt_filter_info *filter;
1455         int rc;
1456
1457         if (BNXT_VF(bp))
1458                 return -EPERM;
1459
1460         memcpy(bp->mac_addr, addr, sizeof(bp->mac_addr));
1461
1462         STAILQ_FOREACH(filter, &vnic->filter, next) {
1463                 /* Default Filter is at Index 0 */
1464                 if (filter->mac_index != 0)
1465                         continue;
1466                 rc = bnxt_hwrm_clear_l2_filter(bp, filter);
1467                 if (rc)
1468                         return rc;
1469                 memcpy(filter->l2_addr, bp->mac_addr, ETHER_ADDR_LEN);
1470                 memset(filter->l2_addr_mask, 0xff, ETHER_ADDR_LEN);
1471                 filter->flags |= HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_PATH_RX;
1472                 filter->enables |=
1473                         HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR |
1474                         HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR_MASK;
1475                 rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id, filter);
1476                 if (rc)
1477                         return rc;
1478                 filter->mac_index = 0;
1479                 PMD_DRV_LOG(DEBUG, "Set MAC addr\n");
1480         }
1481
1482         return 0;
1483 }
1484
1485 static int
1486 bnxt_dev_set_mc_addr_list_op(struct rte_eth_dev *eth_dev,
1487                           struct ether_addr *mc_addr_set,
1488                           uint32_t nb_mc_addr)
1489 {
1490         struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
1491         char *mc_addr_list = (char *)mc_addr_set;
1492         struct bnxt_vnic_info *vnic;
1493         uint32_t off = 0, i = 0;
1494
1495         vnic = &bp->vnic_info[0];
1496
1497         if (nb_mc_addr > BNXT_MAX_MC_ADDRS) {
1498                 vnic->flags |= BNXT_VNIC_INFO_ALLMULTI;
1499                 goto allmulti;
1500         }
1501
1502         /* TODO Check for Duplicate mcast addresses */
1503         vnic->flags &= ~BNXT_VNIC_INFO_ALLMULTI;
1504         for (i = 0; i < nb_mc_addr; i++) {
1505                 memcpy(vnic->mc_list + off, &mc_addr_list[i], ETHER_ADDR_LEN);
1506                 off += ETHER_ADDR_LEN;
1507         }
1508
1509         vnic->mc_addr_cnt = i;
1510
1511 allmulti:
1512         return bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1513 }
1514
1515 static int
1516 bnxt_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
1517 {
1518         struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
1519         uint8_t fw_major = (bp->fw_ver >> 24) & 0xff;
1520         uint8_t fw_minor = (bp->fw_ver >> 16) & 0xff;
1521         uint8_t fw_updt = (bp->fw_ver >> 8) & 0xff;
1522         int ret;
1523
1524         ret = snprintf(fw_version, fw_size, "%d.%d.%d",
1525                         fw_major, fw_minor, fw_updt);
1526
1527         ret += 1; /* add the size of '\0' */
1528         if (fw_size < (uint32_t)ret)
1529                 return ret;
1530         else
1531                 return 0;
1532 }
1533
1534 static void
1535 bnxt_rxq_info_get_op(struct rte_eth_dev *dev, uint16_t queue_id,
1536         struct rte_eth_rxq_info *qinfo)
1537 {
1538         struct bnxt_rx_queue *rxq;
1539
1540         rxq = dev->data->rx_queues[queue_id];
1541
1542         qinfo->mp = rxq->mb_pool;
1543         qinfo->scattered_rx = dev->data->scattered_rx;
1544         qinfo->nb_desc = rxq->nb_rx_desc;
1545
1546         qinfo->conf.rx_free_thresh = rxq->rx_free_thresh;
1547         qinfo->conf.rx_drop_en = 0;
1548         qinfo->conf.rx_deferred_start = 0;
1549 }
1550
1551 static void
1552 bnxt_txq_info_get_op(struct rte_eth_dev *dev, uint16_t queue_id,
1553         struct rte_eth_txq_info *qinfo)
1554 {
1555         struct bnxt_tx_queue *txq;
1556
1557         txq = dev->data->tx_queues[queue_id];
1558
1559         qinfo->nb_desc = txq->nb_tx_desc;
1560
1561         qinfo->conf.tx_thresh.pthresh = txq->pthresh;
1562         qinfo->conf.tx_thresh.hthresh = txq->hthresh;
1563         qinfo->conf.tx_thresh.wthresh = txq->wthresh;
1564
1565         qinfo->conf.tx_free_thresh = txq->tx_free_thresh;
1566         qinfo->conf.tx_rs_thresh = 0;
1567         qinfo->conf.tx_deferred_start = txq->tx_deferred_start;
1568 }
1569
1570 static int bnxt_mtu_set_op(struct rte_eth_dev *eth_dev, uint16_t new_mtu)
1571 {
1572         struct bnxt *bp = eth_dev->data->dev_private;
1573         struct rte_eth_dev_info dev_info;
1574         uint32_t max_dev_mtu;
1575         uint32_t rc = 0;
1576         uint32_t i;
1577
1578         bnxt_dev_info_get_op(eth_dev, &dev_info);
1579         max_dev_mtu = dev_info.max_rx_pktlen -
1580                       ETHER_HDR_LEN - ETHER_CRC_LEN - VLAN_TAG_SIZE * 2;
1581
1582         if (new_mtu < ETHER_MIN_MTU || new_mtu > max_dev_mtu) {
1583                 PMD_DRV_LOG(ERR, "MTU requested must be within (%d, %d)\n",
1584                         ETHER_MIN_MTU, max_dev_mtu);
1585                 return -EINVAL;
1586         }
1587
1588
1589         if (new_mtu > ETHER_MTU) {
1590                 bp->flags |= BNXT_FLAG_JUMBO;
1591                 bp->eth_dev->data->dev_conf.rxmode.offloads |=
1592                         DEV_RX_OFFLOAD_JUMBO_FRAME;
1593         } else {
1594                 bp->eth_dev->data->dev_conf.rxmode.offloads &=
1595                         ~DEV_RX_OFFLOAD_JUMBO_FRAME;
1596                 bp->flags &= ~BNXT_FLAG_JUMBO;
1597         }
1598
1599         eth_dev->data->dev_conf.rxmode.max_rx_pkt_len =
1600                 new_mtu + ETHER_HDR_LEN + ETHER_CRC_LEN + VLAN_TAG_SIZE * 2;
1601
1602         eth_dev->data->mtu = new_mtu;
1603         PMD_DRV_LOG(INFO, "New MTU is %d\n", eth_dev->data->mtu);
1604
1605         for (i = 0; i < bp->nr_vnics; i++) {
1606                 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
1607                 uint16_t size = 0;
1608
1609                 vnic->mru = bp->eth_dev->data->mtu + ETHER_HDR_LEN +
1610                                         ETHER_CRC_LEN + VLAN_TAG_SIZE * 2;
1611                 rc = bnxt_hwrm_vnic_cfg(bp, vnic);
1612                 if (rc)
1613                         break;
1614
1615                 size = rte_pktmbuf_data_room_size(bp->rx_queues[0]->mb_pool);
1616                 size -= RTE_PKTMBUF_HEADROOM;
1617
1618                 if (size < new_mtu) {
1619                         rc = bnxt_hwrm_vnic_plcmode_cfg(bp, vnic);
1620                         if (rc)
1621                                 return rc;
1622                 }
1623         }
1624
1625         return rc;
1626 }
1627
1628 static int
1629 bnxt_vlan_pvid_set_op(struct rte_eth_dev *dev, uint16_t pvid, int on)
1630 {
1631         struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
1632         uint16_t vlan = bp->vlan;
1633         int rc;
1634
1635         if (!BNXT_SINGLE_PF(bp) || BNXT_VF(bp)) {
1636                 PMD_DRV_LOG(ERR,
1637                         "PVID cannot be modified for this function\n");
1638                 return -ENOTSUP;
1639         }
1640         bp->vlan = on ? pvid : 0;
1641
1642         rc = bnxt_hwrm_set_default_vlan(bp, 0, 0);
1643         if (rc)
1644                 bp->vlan = vlan;
1645         return rc;
1646 }
1647
1648 static int
1649 bnxt_dev_led_on_op(struct rte_eth_dev *dev)
1650 {
1651         struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
1652
1653         return bnxt_hwrm_port_led_cfg(bp, true);
1654 }
1655
1656 static int
1657 bnxt_dev_led_off_op(struct rte_eth_dev *dev)
1658 {
1659         struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
1660
1661         return bnxt_hwrm_port_led_cfg(bp, false);
1662 }
1663
1664 static uint32_t
1665 bnxt_rx_queue_count_op(struct rte_eth_dev *dev, uint16_t rx_queue_id)
1666 {
1667         uint32_t desc = 0, raw_cons = 0, cons;
1668         struct bnxt_cp_ring_info *cpr;
1669         struct bnxt_rx_queue *rxq;
1670         struct rx_pkt_cmpl *rxcmp;
1671         uint16_t cmp_type;
1672         uint8_t cmp = 1;
1673         bool valid;
1674
1675         rxq = dev->data->rx_queues[rx_queue_id];
1676         cpr = rxq->cp_ring;
1677         valid = cpr->valid;
1678
1679         while (raw_cons < rxq->nb_rx_desc) {
1680                 cons = RING_CMP(cpr->cp_ring_struct, raw_cons);
1681                 rxcmp = (struct rx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
1682
1683                 if (!CMPL_VALID(rxcmp, valid))
1684                         goto nothing_to_do;
1685                 valid = FLIP_VALID(cons, cpr->cp_ring_struct->ring_mask, valid);
1686                 cmp_type = CMP_TYPE(rxcmp);
1687                 if (cmp_type == RX_TPA_END_CMPL_TYPE_RX_TPA_END) {
1688                         cmp = (rte_le_to_cpu_32(
1689                                         ((struct rx_tpa_end_cmpl *)
1690                                          (rxcmp))->agg_bufs_v1) &
1691                                RX_TPA_END_CMPL_AGG_BUFS_MASK) >>
1692                                 RX_TPA_END_CMPL_AGG_BUFS_SFT;
1693                         desc++;
1694                 } else if (cmp_type == 0x11) {
1695                         desc++;
1696                         cmp = (rxcmp->agg_bufs_v1 &
1697                                    RX_PKT_CMPL_AGG_BUFS_MASK) >>
1698                                 RX_PKT_CMPL_AGG_BUFS_SFT;
1699                 } else {
1700                         cmp = 1;
1701                 }
1702 nothing_to_do:
1703                 raw_cons += cmp ? cmp : 2;
1704         }
1705
1706         return desc;
1707 }
1708
1709 static int
1710 bnxt_rx_descriptor_status_op(void *rx_queue, uint16_t offset)
1711 {
1712         struct bnxt_rx_queue *rxq = (struct bnxt_rx_queue *)rx_queue;
1713         struct bnxt_rx_ring_info *rxr;
1714         struct bnxt_cp_ring_info *cpr;
1715         struct bnxt_sw_rx_bd *rx_buf;
1716         struct rx_pkt_cmpl *rxcmp;
1717         uint32_t cons, cp_cons;
1718
1719         if (!rxq)
1720                 return -EINVAL;
1721
1722         cpr = rxq->cp_ring;
1723         rxr = rxq->rx_ring;
1724
1725         if (offset >= rxq->nb_rx_desc)
1726                 return -EINVAL;
1727
1728         cons = RING_CMP(cpr->cp_ring_struct, offset);
1729         cp_cons = cpr->cp_raw_cons;
1730         rxcmp = (struct rx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
1731
1732         if (cons > cp_cons) {
1733                 if (CMPL_VALID(rxcmp, cpr->valid))
1734                         return RTE_ETH_RX_DESC_DONE;
1735         } else {
1736                 if (CMPL_VALID(rxcmp, !cpr->valid))
1737                         return RTE_ETH_RX_DESC_DONE;
1738         }
1739         rx_buf = &rxr->rx_buf_ring[cons];
1740         if (rx_buf->mbuf == NULL)
1741                 return RTE_ETH_RX_DESC_UNAVAIL;
1742
1743
1744         return RTE_ETH_RX_DESC_AVAIL;
1745 }
1746
1747 static int
1748 bnxt_tx_descriptor_status_op(void *tx_queue, uint16_t offset)
1749 {
1750         struct bnxt_tx_queue *txq = (struct bnxt_tx_queue *)tx_queue;
1751         struct bnxt_tx_ring_info *txr;
1752         struct bnxt_cp_ring_info *cpr;
1753         struct bnxt_sw_tx_bd *tx_buf;
1754         struct tx_pkt_cmpl *txcmp;
1755         uint32_t cons, cp_cons;
1756
1757         if (!txq)
1758                 return -EINVAL;
1759
1760         cpr = txq->cp_ring;
1761         txr = txq->tx_ring;
1762
1763         if (offset >= txq->nb_tx_desc)
1764                 return -EINVAL;
1765
1766         cons = RING_CMP(cpr->cp_ring_struct, offset);
1767         txcmp = (struct tx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
1768         cp_cons = cpr->cp_raw_cons;
1769
1770         if (cons > cp_cons) {
1771                 if (CMPL_VALID(txcmp, cpr->valid))
1772                         return RTE_ETH_TX_DESC_UNAVAIL;
1773         } else {
1774                 if (CMPL_VALID(txcmp, !cpr->valid))
1775                         return RTE_ETH_TX_DESC_UNAVAIL;
1776         }
1777         tx_buf = &txr->tx_buf_ring[cons];
1778         if (tx_buf->mbuf == NULL)
1779                 return RTE_ETH_TX_DESC_DONE;
1780
1781         return RTE_ETH_TX_DESC_FULL;
1782 }
1783
1784 static struct bnxt_filter_info *
1785 bnxt_match_and_validate_ether_filter(struct bnxt *bp,
1786                                 struct rte_eth_ethertype_filter *efilter,
1787                                 struct bnxt_vnic_info *vnic0,
1788                                 struct bnxt_vnic_info *vnic,
1789                                 int *ret)
1790 {
1791         struct bnxt_filter_info *mfilter = NULL;
1792         int match = 0;
1793         *ret = 0;
1794
1795         if (efilter->ether_type == ETHER_TYPE_IPv4 ||
1796                 efilter->ether_type == ETHER_TYPE_IPv6) {
1797                 PMD_DRV_LOG(ERR, "invalid ether_type(0x%04x) in"
1798                         " ethertype filter.", efilter->ether_type);
1799                 *ret = -EINVAL;
1800                 goto exit;
1801         }
1802         if (efilter->queue >= bp->rx_nr_rings) {
1803                 PMD_DRV_LOG(ERR, "Invalid queue %d\n", efilter->queue);
1804                 *ret = -EINVAL;
1805                 goto exit;
1806         }
1807
1808         vnic0 = STAILQ_FIRST(&bp->ff_pool[0]);
1809         vnic = STAILQ_FIRST(&bp->ff_pool[efilter->queue]);
1810         if (vnic == NULL) {
1811                 PMD_DRV_LOG(ERR, "Invalid queue %d\n", efilter->queue);
1812                 *ret = -EINVAL;
1813                 goto exit;
1814         }
1815
1816         if (efilter->flags & RTE_ETHTYPE_FLAGS_DROP) {
1817                 STAILQ_FOREACH(mfilter, &vnic0->filter, next) {
1818                         if ((!memcmp(efilter->mac_addr.addr_bytes,
1819                                      mfilter->l2_addr, ETHER_ADDR_LEN) &&
1820                              mfilter->flags ==
1821                              HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DROP &&
1822                              mfilter->ethertype == efilter->ether_type)) {
1823                                 match = 1;
1824                                 break;
1825                         }
1826                 }
1827         } else {
1828                 STAILQ_FOREACH(mfilter, &vnic->filter, next)
1829                         if ((!memcmp(efilter->mac_addr.addr_bytes,
1830                                      mfilter->l2_addr, ETHER_ADDR_LEN) &&
1831                              mfilter->ethertype == efilter->ether_type &&
1832                              mfilter->flags ==
1833                              HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_PATH_RX)) {
1834                                 match = 1;
1835                                 break;
1836                         }
1837         }
1838
1839         if (match)
1840                 *ret = -EEXIST;
1841
1842 exit:
1843         return mfilter;
1844 }
1845
1846 static int
1847 bnxt_ethertype_filter(struct rte_eth_dev *dev,
1848                         enum rte_filter_op filter_op,
1849                         void *arg)
1850 {
1851         struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
1852         struct rte_eth_ethertype_filter *efilter =
1853                         (struct rte_eth_ethertype_filter *)arg;
1854         struct bnxt_filter_info *bfilter, *filter1;
1855         struct bnxt_vnic_info *vnic, *vnic0;
1856         int ret;
1857
1858         if (filter_op == RTE_ETH_FILTER_NOP)
1859                 return 0;
1860
1861         if (arg == NULL) {
1862                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
1863                             filter_op);
1864                 return -EINVAL;
1865         }
1866
1867         vnic0 = STAILQ_FIRST(&bp->ff_pool[0]);
1868         vnic = STAILQ_FIRST(&bp->ff_pool[efilter->queue]);
1869
1870         switch (filter_op) {
1871         case RTE_ETH_FILTER_ADD:
1872                 bnxt_match_and_validate_ether_filter(bp, efilter,
1873                                                         vnic0, vnic, &ret);
1874                 if (ret < 0)
1875                         return ret;
1876
1877                 bfilter = bnxt_get_unused_filter(bp);
1878                 if (bfilter == NULL) {
1879                         PMD_DRV_LOG(ERR,
1880                                 "Not enough resources for a new filter.\n");
1881                         return -ENOMEM;
1882                 }
1883                 bfilter->filter_type = HWRM_CFA_NTUPLE_FILTER;
1884                 memcpy(bfilter->l2_addr, efilter->mac_addr.addr_bytes,
1885                        ETHER_ADDR_LEN);
1886                 memcpy(bfilter->dst_macaddr, efilter->mac_addr.addr_bytes,
1887                        ETHER_ADDR_LEN);
1888                 bfilter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_MACADDR;
1889                 bfilter->ethertype = efilter->ether_type;
1890                 bfilter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
1891
1892                 filter1 = bnxt_get_l2_filter(bp, bfilter, vnic0);
1893                 if (filter1 == NULL) {
1894                         ret = -1;
1895                         goto cleanup;
1896                 }
1897                 bfilter->enables |=
1898                         HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID;
1899                 bfilter->fw_l2_filter_id = filter1->fw_l2_filter_id;
1900
1901                 bfilter->dst_id = vnic->fw_vnic_id;
1902
1903                 if (efilter->flags & RTE_ETHTYPE_FLAGS_DROP) {
1904                         bfilter->flags =
1905                                 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DROP;
1906                 }
1907
1908                 ret = bnxt_hwrm_set_ntuple_filter(bp, bfilter->dst_id, bfilter);
1909                 if (ret)
1910                         goto cleanup;
1911                 STAILQ_INSERT_TAIL(&vnic->filter, bfilter, next);
1912                 break;
1913         case RTE_ETH_FILTER_DELETE:
1914                 filter1 = bnxt_match_and_validate_ether_filter(bp, efilter,
1915                                                         vnic0, vnic, &ret);
1916                 if (ret == -EEXIST) {
1917                         ret = bnxt_hwrm_clear_ntuple_filter(bp, filter1);
1918
1919                         STAILQ_REMOVE(&vnic->filter, filter1, bnxt_filter_info,
1920                                       next);
1921                         bnxt_free_filter(bp, filter1);
1922                 } else if (ret == 0) {
1923                         PMD_DRV_LOG(ERR, "No matching filter found\n");
1924                 }
1925                 break;
1926         default:
1927                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
1928                 ret = -EINVAL;
1929                 goto error;
1930         }
1931         return ret;
1932 cleanup:
1933         bnxt_free_filter(bp, bfilter);
1934 error:
1935         return ret;
1936 }
1937
1938 static inline int
1939 parse_ntuple_filter(struct bnxt *bp,
1940                     struct rte_eth_ntuple_filter *nfilter,
1941                     struct bnxt_filter_info *bfilter)
1942 {
1943         uint32_t en = 0;
1944
1945         if (nfilter->queue >= bp->rx_nr_rings) {
1946                 PMD_DRV_LOG(ERR, "Invalid queue %d\n", nfilter->queue);
1947                 return -EINVAL;
1948         }
1949
1950         switch (nfilter->dst_port_mask) {
1951         case UINT16_MAX:
1952                 bfilter->dst_port_mask = -1;
1953                 bfilter->dst_port = nfilter->dst_port;
1954                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT |
1955                         NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
1956                 break;
1957         default:
1958                 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
1959                 return -EINVAL;
1960         }
1961
1962         bfilter->ip_addr_type = NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
1963         en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
1964
1965         switch (nfilter->proto_mask) {
1966         case UINT8_MAX:
1967                 if (nfilter->proto == 17) /* IPPROTO_UDP */
1968                         bfilter->ip_protocol = 17;
1969                 else if (nfilter->proto == 6) /* IPPROTO_TCP */
1970                         bfilter->ip_protocol = 6;
1971                 else
1972                         return -EINVAL;
1973                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
1974                 break;
1975         default:
1976                 PMD_DRV_LOG(ERR, "invalid protocol mask.");
1977                 return -EINVAL;
1978         }
1979
1980         switch (nfilter->dst_ip_mask) {
1981         case UINT32_MAX:
1982                 bfilter->dst_ipaddr_mask[0] = -1;
1983                 bfilter->dst_ipaddr[0] = nfilter->dst_ip;
1984                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR |
1985                         NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
1986                 break;
1987         default:
1988                 PMD_DRV_LOG(ERR, "invalid dst_ip mask.");
1989                 return -EINVAL;
1990         }
1991
1992         switch (nfilter->src_ip_mask) {
1993         case UINT32_MAX:
1994                 bfilter->src_ipaddr_mask[0] = -1;
1995                 bfilter->src_ipaddr[0] = nfilter->src_ip;
1996                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR |
1997                         NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
1998                 break;
1999         default:
2000                 PMD_DRV_LOG(ERR, "invalid src_ip mask.");
2001                 return -EINVAL;
2002         }
2003
2004         switch (nfilter->src_port_mask) {
2005         case UINT16_MAX:
2006                 bfilter->src_port_mask = -1;
2007                 bfilter->src_port = nfilter->src_port;
2008                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT |
2009                         NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
2010                 break;
2011         default:
2012                 PMD_DRV_LOG(ERR, "invalid src_port mask.");
2013                 return -EINVAL;
2014         }
2015
2016         //TODO Priority
2017         //nfilter->priority = (uint8_t)filter->priority;
2018
2019         bfilter->enables = en;
2020         return 0;
2021 }
2022
2023 static struct bnxt_filter_info*
2024 bnxt_match_ntuple_filter(struct bnxt *bp,
2025                          struct bnxt_filter_info *bfilter,
2026                          struct bnxt_vnic_info **mvnic)
2027 {
2028         struct bnxt_filter_info *mfilter = NULL;
2029         int i;
2030
2031         for (i = bp->nr_vnics - 1; i >= 0; i--) {
2032                 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
2033                 STAILQ_FOREACH(mfilter, &vnic->filter, next) {
2034                         if (bfilter->src_ipaddr[0] == mfilter->src_ipaddr[0] &&
2035                             bfilter->src_ipaddr_mask[0] ==
2036                             mfilter->src_ipaddr_mask[0] &&
2037                             bfilter->src_port == mfilter->src_port &&
2038                             bfilter->src_port_mask == mfilter->src_port_mask &&
2039                             bfilter->dst_ipaddr[0] == mfilter->dst_ipaddr[0] &&
2040                             bfilter->dst_ipaddr_mask[0] ==
2041                             mfilter->dst_ipaddr_mask[0] &&
2042                             bfilter->dst_port == mfilter->dst_port &&
2043                             bfilter->dst_port_mask == mfilter->dst_port_mask &&
2044                             bfilter->flags == mfilter->flags &&
2045                             bfilter->enables == mfilter->enables) {
2046                                 if (mvnic)
2047                                         *mvnic = vnic;
2048                                 return mfilter;
2049                         }
2050                 }
2051         }
2052         return NULL;
2053 }
2054
2055 static int
2056 bnxt_cfg_ntuple_filter(struct bnxt *bp,
2057                        struct rte_eth_ntuple_filter *nfilter,
2058                        enum rte_filter_op filter_op)
2059 {
2060         struct bnxt_filter_info *bfilter, *mfilter, *filter1;
2061         struct bnxt_vnic_info *vnic, *vnic0, *mvnic;
2062         int ret;
2063
2064         if (nfilter->flags != RTE_5TUPLE_FLAGS) {
2065                 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
2066                 return -EINVAL;
2067         }
2068
2069         if (nfilter->flags & RTE_NTUPLE_FLAGS_TCP_FLAG) {
2070                 PMD_DRV_LOG(ERR, "Ntuple filter: TCP flags not supported\n");
2071                 return -EINVAL;
2072         }
2073
2074         bfilter = bnxt_get_unused_filter(bp);
2075         if (bfilter == NULL) {
2076                 PMD_DRV_LOG(ERR,
2077                         "Not enough resources for a new filter.\n");
2078                 return -ENOMEM;
2079         }
2080         ret = parse_ntuple_filter(bp, nfilter, bfilter);
2081         if (ret < 0)
2082                 goto free_filter;
2083
2084         vnic = STAILQ_FIRST(&bp->ff_pool[nfilter->queue]);
2085         vnic0 = STAILQ_FIRST(&bp->ff_pool[0]);
2086         filter1 = STAILQ_FIRST(&vnic0->filter);
2087         if (filter1 == NULL) {
2088                 ret = -1;
2089                 goto free_filter;
2090         }
2091
2092         bfilter->dst_id = vnic->fw_vnic_id;
2093         bfilter->fw_l2_filter_id = filter1->fw_l2_filter_id;
2094         bfilter->enables |=
2095                 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID;
2096         bfilter->ethertype = 0x800;
2097         bfilter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2098
2099         mfilter = bnxt_match_ntuple_filter(bp, bfilter, &mvnic);
2100
2101         if (mfilter != NULL && filter_op == RTE_ETH_FILTER_ADD &&
2102             bfilter->dst_id == mfilter->dst_id) {
2103                 PMD_DRV_LOG(ERR, "filter exists.\n");
2104                 ret = -EEXIST;
2105                 goto free_filter;
2106         } else if (mfilter != NULL && filter_op == RTE_ETH_FILTER_ADD &&
2107                    bfilter->dst_id != mfilter->dst_id) {
2108                 mfilter->dst_id = vnic->fw_vnic_id;
2109                 ret = bnxt_hwrm_set_ntuple_filter(bp, mfilter->dst_id, mfilter);
2110                 STAILQ_REMOVE(&mvnic->filter, mfilter, bnxt_filter_info, next);
2111                 STAILQ_INSERT_TAIL(&vnic->filter, mfilter, next);
2112                 PMD_DRV_LOG(ERR, "filter with matching pattern exists.\n");
2113                 PMD_DRV_LOG(ERR, " Updated it to the new destination queue\n");
2114                 goto free_filter;
2115         }
2116         if (mfilter == NULL && filter_op == RTE_ETH_FILTER_DELETE) {
2117                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
2118                 ret = -ENOENT;
2119                 goto free_filter;
2120         }
2121
2122         if (filter_op == RTE_ETH_FILTER_ADD) {
2123                 bfilter->filter_type = HWRM_CFA_NTUPLE_FILTER;
2124                 ret = bnxt_hwrm_set_ntuple_filter(bp, bfilter->dst_id, bfilter);
2125                 if (ret)
2126                         goto free_filter;
2127                 STAILQ_INSERT_TAIL(&vnic->filter, bfilter, next);
2128         } else {
2129                 if (mfilter == NULL) {
2130                         /* This should not happen. But for Coverity! */
2131                         ret = -ENOENT;
2132                         goto free_filter;
2133                 }
2134                 ret = bnxt_hwrm_clear_ntuple_filter(bp, mfilter);
2135
2136                 STAILQ_REMOVE(&vnic->filter, mfilter, bnxt_filter_info, next);
2137                 bnxt_free_filter(bp, mfilter);
2138                 mfilter->fw_l2_filter_id = -1;
2139                 bnxt_free_filter(bp, bfilter);
2140                 bfilter->fw_l2_filter_id = -1;
2141         }
2142
2143         return 0;
2144 free_filter:
2145         bfilter->fw_l2_filter_id = -1;
2146         bnxt_free_filter(bp, bfilter);
2147         return ret;
2148 }
2149
2150 static int
2151 bnxt_ntuple_filter(struct rte_eth_dev *dev,
2152                         enum rte_filter_op filter_op,
2153                         void *arg)
2154 {
2155         struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
2156         int ret;
2157
2158         if (filter_op == RTE_ETH_FILTER_NOP)
2159                 return 0;
2160
2161         if (arg == NULL) {
2162                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
2163                             filter_op);
2164                 return -EINVAL;
2165         }
2166
2167         switch (filter_op) {
2168         case RTE_ETH_FILTER_ADD:
2169                 ret = bnxt_cfg_ntuple_filter(bp,
2170                         (struct rte_eth_ntuple_filter *)arg,
2171                         filter_op);
2172                 break;
2173         case RTE_ETH_FILTER_DELETE:
2174                 ret = bnxt_cfg_ntuple_filter(bp,
2175                         (struct rte_eth_ntuple_filter *)arg,
2176                         filter_op);
2177                 break;
2178         default:
2179                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
2180                 ret = -EINVAL;
2181                 break;
2182         }
2183         return ret;
2184 }
2185
2186 static int
2187 bnxt_parse_fdir_filter(struct bnxt *bp,
2188                        struct rte_eth_fdir_filter *fdir,
2189                        struct bnxt_filter_info *filter)
2190 {
2191         enum rte_fdir_mode fdir_mode =
2192                 bp->eth_dev->data->dev_conf.fdir_conf.mode;
2193         struct bnxt_vnic_info *vnic0, *vnic;
2194         struct bnxt_filter_info *filter1;
2195         uint32_t en = 0;
2196         int i;
2197
2198         if (fdir_mode == RTE_FDIR_MODE_PERFECT_TUNNEL)
2199                 return -EINVAL;
2200
2201         filter->l2_ovlan = fdir->input.flow_ext.vlan_tci;
2202         en |= EM_FLOW_ALLOC_INPUT_EN_OVLAN_VID;
2203
2204         switch (fdir->input.flow_type) {
2205         case RTE_ETH_FLOW_IPV4:
2206         case RTE_ETH_FLOW_NONFRAG_IPV4_OTHER:
2207                 /* FALLTHROUGH */
2208                 filter->src_ipaddr[0] = fdir->input.flow.ip4_flow.src_ip;
2209                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2210                 filter->dst_ipaddr[0] = fdir->input.flow.ip4_flow.dst_ip;
2211                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2212                 filter->ip_protocol = fdir->input.flow.ip4_flow.proto;
2213                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2214                 filter->ip_addr_type =
2215                         NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
2216                 filter->src_ipaddr_mask[0] = 0xffffffff;
2217                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2218                 filter->dst_ipaddr_mask[0] = 0xffffffff;
2219                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2220                 filter->ethertype = 0x800;
2221                 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2222                 break;
2223         case RTE_ETH_FLOW_NONFRAG_IPV4_TCP:
2224                 filter->src_port = fdir->input.flow.tcp4_flow.src_port;
2225                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
2226                 filter->dst_port = fdir->input.flow.tcp4_flow.dst_port;
2227                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
2228                 filter->dst_port_mask = 0xffff;
2229                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
2230                 filter->src_port_mask = 0xffff;
2231                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
2232                 filter->src_ipaddr[0] = fdir->input.flow.tcp4_flow.ip.src_ip;
2233                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2234                 filter->dst_ipaddr[0] = fdir->input.flow.tcp4_flow.ip.dst_ip;
2235                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2236                 filter->ip_protocol = 6;
2237                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2238                 filter->ip_addr_type =
2239                         NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
2240                 filter->src_ipaddr_mask[0] = 0xffffffff;
2241                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2242                 filter->dst_ipaddr_mask[0] = 0xffffffff;
2243                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2244                 filter->ethertype = 0x800;
2245                 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2246                 break;
2247         case RTE_ETH_FLOW_NONFRAG_IPV4_UDP:
2248                 filter->src_port = fdir->input.flow.udp4_flow.src_port;
2249                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
2250                 filter->dst_port = fdir->input.flow.udp4_flow.dst_port;
2251                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
2252                 filter->dst_port_mask = 0xffff;
2253                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
2254                 filter->src_port_mask = 0xffff;
2255                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
2256                 filter->src_ipaddr[0] = fdir->input.flow.udp4_flow.ip.src_ip;
2257                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2258                 filter->dst_ipaddr[0] = fdir->input.flow.udp4_flow.ip.dst_ip;
2259                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2260                 filter->ip_protocol = 17;
2261                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2262                 filter->ip_addr_type =
2263                         NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
2264                 filter->src_ipaddr_mask[0] = 0xffffffff;
2265                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2266                 filter->dst_ipaddr_mask[0] = 0xffffffff;
2267                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2268                 filter->ethertype = 0x800;
2269                 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2270                 break;
2271         case RTE_ETH_FLOW_IPV6:
2272         case RTE_ETH_FLOW_NONFRAG_IPV6_OTHER:
2273                 /* FALLTHROUGH */
2274                 filter->ip_addr_type =
2275                         NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV6;
2276                 filter->ip_protocol = fdir->input.flow.ipv6_flow.proto;
2277                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2278                 rte_memcpy(filter->src_ipaddr,
2279                            fdir->input.flow.ipv6_flow.src_ip, 16);
2280                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2281                 rte_memcpy(filter->dst_ipaddr,
2282                            fdir->input.flow.ipv6_flow.dst_ip, 16);
2283                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2284                 memset(filter->dst_ipaddr_mask, 0xff, 16);
2285                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2286                 memset(filter->src_ipaddr_mask, 0xff, 16);
2287                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2288                 filter->ethertype = 0x86dd;
2289                 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2290                 break;
2291         case RTE_ETH_FLOW_NONFRAG_IPV6_TCP:
2292                 filter->src_port = fdir->input.flow.tcp6_flow.src_port;
2293                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
2294                 filter->dst_port = fdir->input.flow.tcp6_flow.dst_port;
2295                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
2296                 filter->dst_port_mask = 0xffff;
2297                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
2298                 filter->src_port_mask = 0xffff;
2299                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
2300                 filter->ip_addr_type =
2301                         NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV6;
2302                 filter->ip_protocol = fdir->input.flow.tcp6_flow.ip.proto;
2303                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2304                 rte_memcpy(filter->src_ipaddr,
2305                            fdir->input.flow.tcp6_flow.ip.src_ip, 16);
2306                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2307                 rte_memcpy(filter->dst_ipaddr,
2308                            fdir->input.flow.tcp6_flow.ip.dst_ip, 16);
2309                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2310                 memset(filter->dst_ipaddr_mask, 0xff, 16);
2311                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2312                 memset(filter->src_ipaddr_mask, 0xff, 16);
2313                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2314                 filter->ethertype = 0x86dd;
2315                 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2316                 break;
2317         case RTE_ETH_FLOW_NONFRAG_IPV6_UDP:
2318                 filter->src_port = fdir->input.flow.udp6_flow.src_port;
2319                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
2320                 filter->dst_port = fdir->input.flow.udp6_flow.dst_port;
2321                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
2322                 filter->dst_port_mask = 0xffff;
2323                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
2324                 filter->src_port_mask = 0xffff;
2325                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
2326                 filter->ip_addr_type =
2327                         NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV6;
2328                 filter->ip_protocol = fdir->input.flow.udp6_flow.ip.proto;
2329                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2330                 rte_memcpy(filter->src_ipaddr,
2331                            fdir->input.flow.udp6_flow.ip.src_ip, 16);
2332                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2333                 rte_memcpy(filter->dst_ipaddr,
2334                            fdir->input.flow.udp6_flow.ip.dst_ip, 16);
2335                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2336                 memset(filter->dst_ipaddr_mask, 0xff, 16);
2337                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2338                 memset(filter->src_ipaddr_mask, 0xff, 16);
2339                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2340                 filter->ethertype = 0x86dd;
2341                 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2342                 break;
2343         case RTE_ETH_FLOW_L2_PAYLOAD:
2344                 filter->ethertype = fdir->input.flow.l2_flow.ether_type;
2345                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2346                 break;
2347         case RTE_ETH_FLOW_VXLAN:
2348                 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT)
2349                         return -EINVAL;
2350                 filter->vni = fdir->input.flow.tunnel_flow.tunnel_id;
2351                 filter->tunnel_type =
2352                         CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN;
2353                 en |= HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_TYPE;
2354                 break;
2355         case RTE_ETH_FLOW_NVGRE:
2356                 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT)
2357                         return -EINVAL;
2358                 filter->vni = fdir->input.flow.tunnel_flow.tunnel_id;
2359                 filter->tunnel_type =
2360                         CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_NVGRE;
2361                 en |= HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_TYPE;
2362                 break;
2363         case RTE_ETH_FLOW_UNKNOWN:
2364         case RTE_ETH_FLOW_RAW:
2365         case RTE_ETH_FLOW_FRAG_IPV4:
2366         case RTE_ETH_FLOW_NONFRAG_IPV4_SCTP:
2367         case RTE_ETH_FLOW_FRAG_IPV6:
2368         case RTE_ETH_FLOW_NONFRAG_IPV6_SCTP:
2369         case RTE_ETH_FLOW_IPV6_EX:
2370         case RTE_ETH_FLOW_IPV6_TCP_EX:
2371         case RTE_ETH_FLOW_IPV6_UDP_EX:
2372         case RTE_ETH_FLOW_GENEVE:
2373                 /* FALLTHROUGH */
2374         default:
2375                 return -EINVAL;
2376         }
2377
2378         vnic0 = STAILQ_FIRST(&bp->ff_pool[0]);
2379         vnic = STAILQ_FIRST(&bp->ff_pool[fdir->action.rx_queue]);
2380         if (vnic == NULL) {
2381                 PMD_DRV_LOG(ERR, "Invalid queue %d\n", fdir->action.rx_queue);
2382                 return -EINVAL;
2383         }
2384
2385
2386         if (fdir_mode == RTE_FDIR_MODE_PERFECT_MAC_VLAN) {
2387                 rte_memcpy(filter->dst_macaddr,
2388                         fdir->input.flow.mac_vlan_flow.mac_addr.addr_bytes, 6);
2389                         en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_MACADDR;
2390         }
2391
2392         if (fdir->action.behavior == RTE_ETH_FDIR_REJECT) {
2393                 filter->flags = HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DROP;
2394                 filter1 = STAILQ_FIRST(&vnic0->filter);
2395                 //filter1 = bnxt_get_l2_filter(bp, filter, vnic0);
2396         } else {
2397                 filter->dst_id = vnic->fw_vnic_id;
2398                 for (i = 0; i < ETHER_ADDR_LEN; i++)
2399                         if (filter->dst_macaddr[i] == 0x00)
2400                                 filter1 = STAILQ_FIRST(&vnic0->filter);
2401                         else
2402                                 filter1 = bnxt_get_l2_filter(bp, filter, vnic);
2403         }
2404
2405         if (filter1 == NULL)
2406                 return -EINVAL;
2407
2408         en |= HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID;
2409         filter->fw_l2_filter_id = filter1->fw_l2_filter_id;
2410
2411         filter->enables = en;
2412
2413         return 0;
2414 }
2415
2416 static struct bnxt_filter_info *
2417 bnxt_match_fdir(struct bnxt *bp, struct bnxt_filter_info *nf,
2418                 struct bnxt_vnic_info **mvnic)
2419 {
2420         struct bnxt_filter_info *mf = NULL;
2421         int i;
2422
2423         for (i = bp->nr_vnics - 1; i >= 0; i--) {
2424                 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
2425
2426                 STAILQ_FOREACH(mf, &vnic->filter, next) {
2427                         if (mf->filter_type == nf->filter_type &&
2428                             mf->flags == nf->flags &&
2429                             mf->src_port == nf->src_port &&
2430                             mf->src_port_mask == nf->src_port_mask &&
2431                             mf->dst_port == nf->dst_port &&
2432                             mf->dst_port_mask == nf->dst_port_mask &&
2433                             mf->ip_protocol == nf->ip_protocol &&
2434                             mf->ip_addr_type == nf->ip_addr_type &&
2435                             mf->ethertype == nf->ethertype &&
2436                             mf->vni == nf->vni &&
2437                             mf->tunnel_type == nf->tunnel_type &&
2438                             mf->l2_ovlan == nf->l2_ovlan &&
2439                             mf->l2_ovlan_mask == nf->l2_ovlan_mask &&
2440                             mf->l2_ivlan == nf->l2_ivlan &&
2441                             mf->l2_ivlan_mask == nf->l2_ivlan_mask &&
2442                             !memcmp(mf->l2_addr, nf->l2_addr, ETHER_ADDR_LEN) &&
2443                             !memcmp(mf->l2_addr_mask, nf->l2_addr_mask,
2444                                     ETHER_ADDR_LEN) &&
2445                             !memcmp(mf->src_macaddr, nf->src_macaddr,
2446                                     ETHER_ADDR_LEN) &&
2447                             !memcmp(mf->dst_macaddr, nf->dst_macaddr,
2448                                     ETHER_ADDR_LEN) &&
2449                             !memcmp(mf->src_ipaddr, nf->src_ipaddr,
2450                                     sizeof(nf->src_ipaddr)) &&
2451                             !memcmp(mf->src_ipaddr_mask, nf->src_ipaddr_mask,
2452                                     sizeof(nf->src_ipaddr_mask)) &&
2453                             !memcmp(mf->dst_ipaddr, nf->dst_ipaddr,
2454                                     sizeof(nf->dst_ipaddr)) &&
2455                             !memcmp(mf->dst_ipaddr_mask, nf->dst_ipaddr_mask,
2456                                     sizeof(nf->dst_ipaddr_mask))) {
2457                                 if (mvnic)
2458                                         *mvnic = vnic;
2459                                 return mf;
2460                         }
2461                 }
2462         }
2463         return NULL;
2464 }
2465
2466 static int
2467 bnxt_fdir_filter(struct rte_eth_dev *dev,
2468                  enum rte_filter_op filter_op,
2469                  void *arg)
2470 {
2471         struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
2472         struct rte_eth_fdir_filter *fdir  = (struct rte_eth_fdir_filter *)arg;
2473         struct bnxt_filter_info *filter, *match;
2474         struct bnxt_vnic_info *vnic, *mvnic;
2475         int ret = 0, i;
2476
2477         if (filter_op == RTE_ETH_FILTER_NOP)
2478                 return 0;
2479
2480         if (arg == NULL && filter_op != RTE_ETH_FILTER_FLUSH)
2481                 return -EINVAL;
2482
2483         switch (filter_op) {
2484         case RTE_ETH_FILTER_ADD:
2485         case RTE_ETH_FILTER_DELETE:
2486                 /* FALLTHROUGH */
2487                 filter = bnxt_get_unused_filter(bp);
2488                 if (filter == NULL) {
2489                         PMD_DRV_LOG(ERR,
2490                                 "Not enough resources for a new flow.\n");
2491                         return -ENOMEM;
2492                 }
2493
2494                 ret = bnxt_parse_fdir_filter(bp, fdir, filter);
2495                 if (ret != 0)
2496                         goto free_filter;
2497                 filter->filter_type = HWRM_CFA_NTUPLE_FILTER;
2498
2499                 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT)
2500                         vnic = STAILQ_FIRST(&bp->ff_pool[0]);
2501                 else
2502                         vnic = STAILQ_FIRST(&bp->ff_pool[fdir->action.rx_queue]);
2503
2504                 match = bnxt_match_fdir(bp, filter, &mvnic);
2505                 if (match != NULL && filter_op == RTE_ETH_FILTER_ADD) {
2506                         if (match->dst_id == vnic->fw_vnic_id) {
2507                                 PMD_DRV_LOG(ERR, "Flow already exists.\n");
2508                                 ret = -EEXIST;
2509                                 goto free_filter;
2510                         } else {
2511                                 match->dst_id = vnic->fw_vnic_id;
2512                                 ret = bnxt_hwrm_set_ntuple_filter(bp,
2513                                                                   match->dst_id,
2514                                                                   match);
2515                                 STAILQ_REMOVE(&mvnic->filter, match,
2516                                               bnxt_filter_info, next);
2517                                 STAILQ_INSERT_TAIL(&vnic->filter, match, next);
2518                                 PMD_DRV_LOG(ERR,
2519                                         "Filter with matching pattern exist\n");
2520                                 PMD_DRV_LOG(ERR,
2521                                         "Updated it to new destination q\n");
2522                                 goto free_filter;
2523                         }
2524                 }
2525                 if (match == NULL && filter_op == RTE_ETH_FILTER_DELETE) {
2526                         PMD_DRV_LOG(ERR, "Flow does not exist.\n");
2527                         ret = -ENOENT;
2528                         goto free_filter;
2529                 }
2530
2531                 if (filter_op == RTE_ETH_FILTER_ADD) {
2532                         ret = bnxt_hwrm_set_ntuple_filter(bp,
2533                                                           filter->dst_id,
2534                                                           filter);
2535                         if (ret)
2536                                 goto free_filter;
2537                         STAILQ_INSERT_TAIL(&vnic->filter, filter, next);
2538                 } else {
2539                         ret = bnxt_hwrm_clear_ntuple_filter(bp, match);
2540                         STAILQ_REMOVE(&vnic->filter, match,
2541                                       bnxt_filter_info, next);
2542                         bnxt_free_filter(bp, match);
2543                         filter->fw_l2_filter_id = -1;
2544                         bnxt_free_filter(bp, filter);
2545                 }
2546                 break;
2547         case RTE_ETH_FILTER_FLUSH:
2548                 for (i = bp->nr_vnics - 1; i >= 0; i--) {
2549                         struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
2550
2551                         STAILQ_FOREACH(filter, &vnic->filter, next) {
2552                                 if (filter->filter_type ==
2553                                     HWRM_CFA_NTUPLE_FILTER) {
2554                                         ret =
2555                                         bnxt_hwrm_clear_ntuple_filter(bp,
2556                                                                       filter);
2557                                         STAILQ_REMOVE(&vnic->filter, filter,
2558                                                       bnxt_filter_info, next);
2559                                 }
2560                         }
2561                 }
2562                 return ret;
2563         case RTE_ETH_FILTER_UPDATE:
2564         case RTE_ETH_FILTER_STATS:
2565         case RTE_ETH_FILTER_INFO:
2566                 PMD_DRV_LOG(ERR, "operation %u not implemented", filter_op);
2567                 break;
2568         default:
2569                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
2570                 ret = -EINVAL;
2571                 break;
2572         }
2573         return ret;
2574
2575 free_filter:
2576         filter->fw_l2_filter_id = -1;
2577         bnxt_free_filter(bp, filter);
2578         return ret;
2579 }
2580
2581 static int
2582 bnxt_filter_ctrl_op(struct rte_eth_dev *dev __rte_unused,
2583                     enum rte_filter_type filter_type,
2584                     enum rte_filter_op filter_op, void *arg)
2585 {
2586         int ret = 0;
2587
2588         switch (filter_type) {
2589         case RTE_ETH_FILTER_TUNNEL:
2590                 PMD_DRV_LOG(ERR,
2591                         "filter type: %d: To be implemented\n", filter_type);
2592                 break;
2593         case RTE_ETH_FILTER_FDIR:
2594                 ret = bnxt_fdir_filter(dev, filter_op, arg);
2595                 break;
2596         case RTE_ETH_FILTER_NTUPLE:
2597                 ret = bnxt_ntuple_filter(dev, filter_op, arg);
2598                 break;
2599         case RTE_ETH_FILTER_ETHERTYPE:
2600                 ret = bnxt_ethertype_filter(dev, filter_op, arg);
2601                 break;
2602         case RTE_ETH_FILTER_GENERIC:
2603                 if (filter_op != RTE_ETH_FILTER_GET)
2604                         return -EINVAL;
2605                 *(const void **)arg = &bnxt_flow_ops;
2606                 break;
2607         default:
2608                 PMD_DRV_LOG(ERR,
2609                         "Filter type (%d) not supported", filter_type);
2610                 ret = -EINVAL;
2611                 break;
2612         }
2613         return ret;
2614 }
2615
2616 static const uint32_t *
2617 bnxt_dev_supported_ptypes_get_op(struct rte_eth_dev *dev)
2618 {
2619         static const uint32_t ptypes[] = {
2620                 RTE_PTYPE_L2_ETHER_VLAN,
2621                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN,
2622                 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN,
2623                 RTE_PTYPE_L4_ICMP,
2624                 RTE_PTYPE_L4_TCP,
2625                 RTE_PTYPE_L4_UDP,
2626                 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN,
2627                 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN,
2628                 RTE_PTYPE_INNER_L4_ICMP,
2629                 RTE_PTYPE_INNER_L4_TCP,
2630                 RTE_PTYPE_INNER_L4_UDP,
2631                 RTE_PTYPE_UNKNOWN
2632         };
2633
2634         if (dev->rx_pkt_burst == bnxt_recv_pkts)
2635                 return ptypes;
2636         return NULL;
2637 }
2638
2639 static int bnxt_map_regs(struct bnxt *bp, uint32_t *reg_arr, int count,
2640                          int reg_win)
2641 {
2642         uint32_t reg_base = *reg_arr & 0xfffff000;
2643         uint32_t win_off;
2644         int i;
2645
2646         for (i = 0; i < count; i++) {
2647                 if ((reg_arr[i] & 0xfffff000) != reg_base)
2648                         return -ERANGE;
2649         }
2650         win_off = BNXT_GRCPF_REG_WINDOW_BASE_OUT + (reg_win - 1) * 4;
2651         rte_cpu_to_le_32(rte_write32(reg_base, (uint8_t *)bp->bar0 + win_off));
2652         return 0;
2653 }
2654
2655 static int bnxt_map_ptp_regs(struct bnxt *bp)
2656 {
2657         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
2658         uint32_t *reg_arr;
2659         int rc, i;
2660
2661         reg_arr = ptp->rx_regs;
2662         rc = bnxt_map_regs(bp, reg_arr, BNXT_PTP_RX_REGS, 5);
2663         if (rc)
2664                 return rc;
2665
2666         reg_arr = ptp->tx_regs;
2667         rc = bnxt_map_regs(bp, reg_arr, BNXT_PTP_TX_REGS, 6);
2668         if (rc)
2669                 return rc;
2670
2671         for (i = 0; i < BNXT_PTP_RX_REGS; i++)
2672                 ptp->rx_mapped_regs[i] = 0x5000 + (ptp->rx_regs[i] & 0xfff);
2673
2674         for (i = 0; i < BNXT_PTP_TX_REGS; i++)
2675                 ptp->tx_mapped_regs[i] = 0x6000 + (ptp->tx_regs[i] & 0xfff);
2676
2677         return 0;
2678 }
2679
2680 static void bnxt_unmap_ptp_regs(struct bnxt *bp)
2681 {
2682         rte_cpu_to_le_32(rte_write32(0, (uint8_t *)bp->bar0 +
2683                          BNXT_GRCPF_REG_WINDOW_BASE_OUT + 16));
2684         rte_cpu_to_le_32(rte_write32(0, (uint8_t *)bp->bar0 +
2685                          BNXT_GRCPF_REG_WINDOW_BASE_OUT + 20));
2686 }
2687
2688 static uint64_t bnxt_cc_read(struct bnxt *bp)
2689 {
2690         uint64_t ns;
2691
2692         ns = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
2693                               BNXT_GRCPF_REG_SYNC_TIME));
2694         ns |= (uint64_t)(rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
2695                                           BNXT_GRCPF_REG_SYNC_TIME + 4))) << 32;
2696         return ns;
2697 }
2698
2699 static int bnxt_get_tx_ts(struct bnxt *bp, uint64_t *ts)
2700 {
2701         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
2702         uint32_t fifo;
2703
2704         fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
2705                                 ptp->tx_mapped_regs[BNXT_PTP_TX_FIFO]));
2706         if (fifo & BNXT_PTP_TX_FIFO_EMPTY)
2707                 return -EAGAIN;
2708
2709         fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
2710                                 ptp->tx_mapped_regs[BNXT_PTP_TX_FIFO]));
2711         *ts = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
2712                                 ptp->tx_mapped_regs[BNXT_PTP_TX_TS_L]));
2713         *ts |= (uint64_t)rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
2714                                 ptp->tx_mapped_regs[BNXT_PTP_TX_TS_H])) << 32;
2715
2716         return 0;
2717 }
2718
2719 static int bnxt_get_rx_ts(struct bnxt *bp, uint64_t *ts)
2720 {
2721         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
2722         struct bnxt_pf_info *pf = &bp->pf;
2723         uint16_t port_id;
2724         uint32_t fifo;
2725
2726         if (!ptp)
2727                 return -ENODEV;
2728
2729         fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
2730                                 ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO]));
2731         if (!(fifo & BNXT_PTP_RX_FIFO_PENDING))
2732                 return -EAGAIN;
2733
2734         port_id = pf->port_id;
2735         rte_cpu_to_le_32(rte_write32(1 << port_id, (uint8_t *)bp->bar0 +
2736                ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO_ADV]));
2737
2738         fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
2739                                    ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO]));
2740         if (fifo & BNXT_PTP_RX_FIFO_PENDING) {
2741 /*              bnxt_clr_rx_ts(bp);       TBD  */
2742                 return -EBUSY;
2743         }
2744
2745         *ts = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
2746                                 ptp->rx_mapped_regs[BNXT_PTP_RX_TS_L]));
2747         *ts |= (uint64_t)rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
2748                                 ptp->rx_mapped_regs[BNXT_PTP_RX_TS_H])) << 32;
2749
2750         return 0;
2751 }
2752
2753 static int
2754 bnxt_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
2755 {
2756         uint64_t ns;
2757         struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
2758         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
2759
2760         if (!ptp)
2761                 return 0;
2762
2763         ns = rte_timespec_to_ns(ts);
2764         /* Set the timecounters to a new value. */
2765         ptp->tc.nsec = ns;
2766
2767         return 0;
2768 }
2769
2770 static int
2771 bnxt_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
2772 {
2773         uint64_t ns, systime_cycles;
2774         struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
2775         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
2776
2777         if (!ptp)
2778                 return 0;
2779
2780         systime_cycles = bnxt_cc_read(bp);
2781         ns = rte_timecounter_update(&ptp->tc, systime_cycles);
2782         *ts = rte_ns_to_timespec(ns);
2783
2784         return 0;
2785 }
2786 static int
2787 bnxt_timesync_enable(struct rte_eth_dev *dev)
2788 {
2789         struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
2790         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
2791         uint32_t shift = 0;
2792
2793         if (!ptp)
2794                 return 0;
2795
2796         ptp->rx_filter = 1;
2797         ptp->tx_tstamp_en = 1;
2798         ptp->rxctl = BNXT_PTP_MSG_EVENTS;
2799
2800         if (!bnxt_hwrm_ptp_cfg(bp))
2801                 bnxt_map_ptp_regs(bp);
2802
2803         memset(&ptp->tc, 0, sizeof(struct rte_timecounter));
2804         memset(&ptp->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
2805         memset(&ptp->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
2806
2807         ptp->tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
2808         ptp->tc.cc_shift = shift;
2809         ptp->tc.nsec_mask = (1ULL << shift) - 1;
2810
2811         ptp->rx_tstamp_tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
2812         ptp->rx_tstamp_tc.cc_shift = shift;
2813         ptp->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
2814
2815         ptp->tx_tstamp_tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
2816         ptp->tx_tstamp_tc.cc_shift = shift;
2817         ptp->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
2818
2819         return 0;
2820 }
2821
2822 static int
2823 bnxt_timesync_disable(struct rte_eth_dev *dev)
2824 {
2825         struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
2826         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
2827
2828         if (!ptp)
2829                 return 0;
2830
2831         ptp->rx_filter = 0;
2832         ptp->tx_tstamp_en = 0;
2833         ptp->rxctl = 0;
2834
2835         bnxt_hwrm_ptp_cfg(bp);
2836
2837         bnxt_unmap_ptp_regs(bp);
2838
2839         return 0;
2840 }
2841
2842 static int
2843 bnxt_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
2844                                  struct timespec *timestamp,
2845                                  uint32_t flags __rte_unused)
2846 {
2847         struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
2848         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
2849         uint64_t rx_tstamp_cycles = 0;
2850         uint64_t ns;
2851
2852         if (!ptp)
2853                 return 0;
2854
2855         bnxt_get_rx_ts(bp, &rx_tstamp_cycles);
2856         ns = rte_timecounter_update(&ptp->rx_tstamp_tc, rx_tstamp_cycles);
2857         *timestamp = rte_ns_to_timespec(ns);
2858         return  0;
2859 }
2860
2861 static int
2862 bnxt_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
2863                                  struct timespec *timestamp)
2864 {
2865         struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
2866         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
2867         uint64_t tx_tstamp_cycles = 0;
2868         uint64_t ns;
2869
2870         if (!ptp)
2871                 return 0;
2872
2873         bnxt_get_tx_ts(bp, &tx_tstamp_cycles);
2874         ns = rte_timecounter_update(&ptp->tx_tstamp_tc, tx_tstamp_cycles);
2875         *timestamp = rte_ns_to_timespec(ns);
2876
2877         return 0;
2878 }
2879
2880 static int
2881 bnxt_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
2882 {
2883         struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
2884         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
2885
2886         if (!ptp)
2887                 return 0;
2888
2889         ptp->tc.nsec += delta;
2890
2891         return 0;
2892 }
2893
2894 static int
2895 bnxt_get_eeprom_length_op(struct rte_eth_dev *dev)
2896 {
2897         struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
2898         int rc;
2899         uint32_t dir_entries;
2900         uint32_t entry_length;
2901
2902         PMD_DRV_LOG(INFO, "%04x:%02x:%02x:%02x\n",
2903                 bp->pdev->addr.domain, bp->pdev->addr.bus,
2904                 bp->pdev->addr.devid, bp->pdev->addr.function);
2905
2906         rc = bnxt_hwrm_nvm_get_dir_info(bp, &dir_entries, &entry_length);
2907         if (rc != 0)
2908                 return rc;
2909
2910         return dir_entries * entry_length;
2911 }
2912
2913 static int
2914 bnxt_get_eeprom_op(struct rte_eth_dev *dev,
2915                 struct rte_dev_eeprom_info *in_eeprom)
2916 {
2917         struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
2918         uint32_t index;
2919         uint32_t offset;
2920
2921         PMD_DRV_LOG(INFO, "%04x:%02x:%02x:%02x in_eeprom->offset = %d "
2922                 "len = %d\n", bp->pdev->addr.domain,
2923                 bp->pdev->addr.bus, bp->pdev->addr.devid,
2924                 bp->pdev->addr.function, in_eeprom->offset, in_eeprom->length);
2925
2926         if (in_eeprom->offset == 0) /* special offset value to get directory */
2927                 return bnxt_get_nvram_directory(bp, in_eeprom->length,
2928                                                 in_eeprom->data);
2929
2930         index = in_eeprom->offset >> 24;
2931         offset = in_eeprom->offset & 0xffffff;
2932
2933         if (index != 0)
2934                 return bnxt_hwrm_get_nvram_item(bp, index - 1, offset,
2935                                            in_eeprom->length, in_eeprom->data);
2936
2937         return 0;
2938 }
2939
2940 static bool bnxt_dir_type_is_ape_bin_format(uint16_t dir_type)
2941 {
2942         switch (dir_type) {
2943         case BNX_DIR_TYPE_CHIMP_PATCH:
2944         case BNX_DIR_TYPE_BOOTCODE:
2945         case BNX_DIR_TYPE_BOOTCODE_2:
2946         case BNX_DIR_TYPE_APE_FW:
2947         case BNX_DIR_TYPE_APE_PATCH:
2948         case BNX_DIR_TYPE_KONG_FW:
2949         case BNX_DIR_TYPE_KONG_PATCH:
2950         case BNX_DIR_TYPE_BONO_FW:
2951         case BNX_DIR_TYPE_BONO_PATCH:
2952                 /* FALLTHROUGH */
2953                 return true;
2954         }
2955
2956         return false;
2957 }
2958
2959 static bool bnxt_dir_type_is_other_exec_format(uint16_t dir_type)
2960 {
2961         switch (dir_type) {
2962         case BNX_DIR_TYPE_AVS:
2963         case BNX_DIR_TYPE_EXP_ROM_MBA:
2964         case BNX_DIR_TYPE_PCIE:
2965         case BNX_DIR_TYPE_TSCF_UCODE:
2966         case BNX_DIR_TYPE_EXT_PHY:
2967         case BNX_DIR_TYPE_CCM:
2968         case BNX_DIR_TYPE_ISCSI_BOOT:
2969         case BNX_DIR_TYPE_ISCSI_BOOT_IPV6:
2970         case BNX_DIR_TYPE_ISCSI_BOOT_IPV4N6:
2971                 /* FALLTHROUGH */
2972                 return true;
2973         }
2974
2975         return false;
2976 }
2977
2978 static bool bnxt_dir_type_is_executable(uint16_t dir_type)
2979 {
2980         return bnxt_dir_type_is_ape_bin_format(dir_type) ||
2981                 bnxt_dir_type_is_other_exec_format(dir_type);
2982 }
2983
2984 static int
2985 bnxt_set_eeprom_op(struct rte_eth_dev *dev,
2986                 struct rte_dev_eeprom_info *in_eeprom)
2987 {
2988         struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
2989         uint8_t index, dir_op;
2990         uint16_t type, ext, ordinal, attr;
2991
2992         PMD_DRV_LOG(INFO, "%04x:%02x:%02x:%02x in_eeprom->offset = %d "
2993                 "len = %d\n", bp->pdev->addr.domain,
2994                 bp->pdev->addr.bus, bp->pdev->addr.devid,
2995                 bp->pdev->addr.function, in_eeprom->offset, in_eeprom->length);
2996
2997         if (!BNXT_PF(bp)) {
2998                 PMD_DRV_LOG(ERR, "NVM write not supported from a VF\n");
2999                 return -EINVAL;
3000         }
3001
3002         type = in_eeprom->magic >> 16;
3003
3004         if (type == 0xffff) { /* special value for directory operations */
3005                 index = in_eeprom->magic & 0xff;
3006                 dir_op = in_eeprom->magic >> 8;
3007                 if (index == 0)
3008                         return -EINVAL;
3009                 switch (dir_op) {
3010                 case 0x0e: /* erase */
3011                         if (in_eeprom->offset != ~in_eeprom->magic)
3012                                 return -EINVAL;
3013                         return bnxt_hwrm_erase_nvram_directory(bp, index - 1);
3014                 default:
3015                         return -EINVAL;
3016                 }
3017         }
3018
3019         /* Create or re-write an NVM item: */
3020         if (bnxt_dir_type_is_executable(type) == true)
3021                 return -EOPNOTSUPP;
3022         ext = in_eeprom->magic & 0xffff;
3023         ordinal = in_eeprom->offset >> 16;
3024         attr = in_eeprom->offset & 0xffff;
3025
3026         return bnxt_hwrm_flash_nvram(bp, type, ordinal, ext, attr,
3027                                      in_eeprom->data, in_eeprom->length);
3028         return 0;
3029 }
3030
3031 /*
3032  * Initialization
3033  */
3034
3035 static const struct eth_dev_ops bnxt_dev_ops = {
3036         .dev_infos_get = bnxt_dev_info_get_op,
3037         .dev_close = bnxt_dev_close_op,
3038         .dev_configure = bnxt_dev_configure_op,
3039         .dev_start = bnxt_dev_start_op,
3040         .dev_stop = bnxt_dev_stop_op,
3041         .dev_set_link_up = bnxt_dev_set_link_up_op,
3042         .dev_set_link_down = bnxt_dev_set_link_down_op,
3043         .stats_get = bnxt_stats_get_op,
3044         .stats_reset = bnxt_stats_reset_op,
3045         .rx_queue_setup = bnxt_rx_queue_setup_op,
3046         .rx_queue_release = bnxt_rx_queue_release_op,
3047         .tx_queue_setup = bnxt_tx_queue_setup_op,
3048         .tx_queue_release = bnxt_tx_queue_release_op,
3049         .rx_queue_intr_enable = bnxt_rx_queue_intr_enable_op,
3050         .rx_queue_intr_disable = bnxt_rx_queue_intr_disable_op,
3051         .reta_update = bnxt_reta_update_op,
3052         .reta_query = bnxt_reta_query_op,
3053         .rss_hash_update = bnxt_rss_hash_update_op,
3054         .rss_hash_conf_get = bnxt_rss_hash_conf_get_op,
3055         .link_update = bnxt_link_update_op,
3056         .promiscuous_enable = bnxt_promiscuous_enable_op,
3057         .promiscuous_disable = bnxt_promiscuous_disable_op,
3058         .allmulticast_enable = bnxt_allmulticast_enable_op,
3059         .allmulticast_disable = bnxt_allmulticast_disable_op,
3060         .mac_addr_add = bnxt_mac_addr_add_op,
3061         .mac_addr_remove = bnxt_mac_addr_remove_op,
3062         .flow_ctrl_get = bnxt_flow_ctrl_get_op,
3063         .flow_ctrl_set = bnxt_flow_ctrl_set_op,
3064         .udp_tunnel_port_add  = bnxt_udp_tunnel_port_add_op,
3065         .udp_tunnel_port_del  = bnxt_udp_tunnel_port_del_op,
3066         .vlan_filter_set = bnxt_vlan_filter_set_op,
3067         .vlan_offload_set = bnxt_vlan_offload_set_op,
3068         .vlan_pvid_set = bnxt_vlan_pvid_set_op,
3069         .mtu_set = bnxt_mtu_set_op,
3070         .mac_addr_set = bnxt_set_default_mac_addr_op,
3071         .xstats_get = bnxt_dev_xstats_get_op,
3072         .xstats_get_names = bnxt_dev_xstats_get_names_op,
3073         .xstats_reset = bnxt_dev_xstats_reset_op,
3074         .fw_version_get = bnxt_fw_version_get,
3075         .set_mc_addr_list = bnxt_dev_set_mc_addr_list_op,
3076         .rxq_info_get = bnxt_rxq_info_get_op,
3077         .txq_info_get = bnxt_txq_info_get_op,
3078         .dev_led_on = bnxt_dev_led_on_op,
3079         .dev_led_off = bnxt_dev_led_off_op,
3080         .xstats_get_by_id = bnxt_dev_xstats_get_by_id_op,
3081         .xstats_get_names_by_id = bnxt_dev_xstats_get_names_by_id_op,
3082         .rx_queue_count = bnxt_rx_queue_count_op,
3083         .rx_descriptor_status = bnxt_rx_descriptor_status_op,
3084         .tx_descriptor_status = bnxt_tx_descriptor_status_op,
3085         .rx_queue_start = bnxt_rx_queue_start,
3086         .rx_queue_stop = bnxt_rx_queue_stop,
3087         .tx_queue_start = bnxt_tx_queue_start,
3088         .tx_queue_stop = bnxt_tx_queue_stop,
3089         .filter_ctrl = bnxt_filter_ctrl_op,
3090         .dev_supported_ptypes_get = bnxt_dev_supported_ptypes_get_op,
3091         .get_eeprom_length    = bnxt_get_eeprom_length_op,
3092         .get_eeprom           = bnxt_get_eeprom_op,
3093         .set_eeprom           = bnxt_set_eeprom_op,
3094         .timesync_enable      = bnxt_timesync_enable,
3095         .timesync_disable     = bnxt_timesync_disable,
3096         .timesync_read_time   = bnxt_timesync_read_time,
3097         .timesync_write_time   = bnxt_timesync_write_time,
3098         .timesync_adjust_time = bnxt_timesync_adjust_time,
3099         .timesync_read_rx_timestamp = bnxt_timesync_read_rx_timestamp,
3100         .timesync_read_tx_timestamp = bnxt_timesync_read_tx_timestamp,
3101 };
3102
3103 static bool bnxt_vf_pciid(uint16_t id)
3104 {
3105         if (id == BROADCOM_DEV_ID_57304_VF ||
3106             id == BROADCOM_DEV_ID_57406_VF ||
3107             id == BROADCOM_DEV_ID_5731X_VF ||
3108             id == BROADCOM_DEV_ID_5741X_VF ||
3109             id == BROADCOM_DEV_ID_57414_VF ||
3110             id == BROADCOM_DEV_ID_STRATUS_NIC_VF1 ||
3111             id == BROADCOM_DEV_ID_STRATUS_NIC_VF2 ||
3112             id == BROADCOM_DEV_ID_58802_VF)
3113                 return true;
3114         return false;
3115 }
3116
3117 bool bnxt_stratus_device(struct bnxt *bp)
3118 {
3119         uint16_t id = bp->pdev->id.device_id;
3120
3121         if (id == BROADCOM_DEV_ID_STRATUS_NIC ||
3122             id == BROADCOM_DEV_ID_STRATUS_NIC_VF1 ||
3123             id == BROADCOM_DEV_ID_STRATUS_NIC_VF2)
3124                 return true;
3125         return false;
3126 }
3127
3128 static int bnxt_init_board(struct rte_eth_dev *eth_dev)
3129 {
3130         struct bnxt *bp = eth_dev->data->dev_private;
3131         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
3132         int rc;
3133
3134         /* enable device (incl. PCI PM wakeup), and bus-mastering */
3135         if (!pci_dev->mem_resource[0].addr) {
3136                 PMD_DRV_LOG(ERR,
3137                         "Cannot find PCI device base address, aborting\n");
3138                 rc = -ENODEV;
3139                 goto init_err_disable;
3140         }
3141
3142         bp->eth_dev = eth_dev;
3143         bp->pdev = pci_dev;
3144
3145         bp->bar0 = (void *)pci_dev->mem_resource[0].addr;
3146         if (!bp->bar0) {
3147                 PMD_DRV_LOG(ERR, "Cannot map device registers, aborting\n");
3148                 rc = -ENOMEM;
3149                 goto init_err_release;
3150         }
3151
3152         if (!pci_dev->mem_resource[2].addr) {
3153                 PMD_DRV_LOG(ERR,
3154                             "Cannot find PCI device BAR 2 address, aborting\n");
3155                 rc = -ENODEV;
3156                 goto init_err_release;
3157         } else {
3158                 bp->doorbell_base = (void *)pci_dev->mem_resource[2].addr;
3159         }
3160
3161         return 0;
3162
3163 init_err_release:
3164         if (bp->bar0)
3165                 bp->bar0 = NULL;
3166         if (bp->doorbell_base)
3167                 bp->doorbell_base = NULL;
3168
3169 init_err_disable:
3170
3171         return rc;
3172 }
3173
3174
3175 #define ALLOW_FUNC(x)   \
3176         { \
3177                 typeof(x) arg = (x); \
3178                 bp->pf.vf_req_fwd[((arg) >> 5)] &= \
3179                 ~rte_cpu_to_le_32(1 << ((arg) & 0x1f)); \
3180         }
3181 static int
3182 bnxt_dev_init(struct rte_eth_dev *eth_dev)
3183 {
3184         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
3185         char mz_name[RTE_MEMZONE_NAMESIZE];
3186         const struct rte_memzone *mz = NULL;
3187         static int version_printed;
3188         uint32_t total_alloc_len;
3189         rte_iova_t mz_phys_addr;
3190         struct bnxt *bp;
3191         int rc;
3192
3193         if (version_printed++ == 0)
3194                 PMD_DRV_LOG(INFO, "%s\n", bnxt_version);
3195
3196         rte_eth_copy_pci_info(eth_dev, pci_dev);
3197
3198         bp = eth_dev->data->dev_private;
3199
3200         bp->dev_stopped = 1;
3201
3202         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
3203                 goto skip_init;
3204
3205         if (bnxt_vf_pciid(pci_dev->id.device_id))
3206                 bp->flags |= BNXT_FLAG_VF;
3207
3208         rc = bnxt_init_board(eth_dev);
3209         if (rc) {
3210                 PMD_DRV_LOG(ERR,
3211                         "Board initialization failed rc: %x\n", rc);
3212                 goto error;
3213         }
3214 skip_init:
3215         eth_dev->dev_ops = &bnxt_dev_ops;
3216         eth_dev->rx_pkt_burst = &bnxt_recv_pkts;
3217         eth_dev->tx_pkt_burst = &bnxt_xmit_pkts;
3218         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
3219                 return 0;
3220
3221         if (pci_dev->id.device_id != BROADCOM_DEV_ID_NS2) {
3222                 snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
3223                          "bnxt_%04x:%02x:%02x:%02x-%s", pci_dev->addr.domain,
3224                          pci_dev->addr.bus, pci_dev->addr.devid,
3225                          pci_dev->addr.function, "rx_port_stats");
3226                 mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
3227                 mz = rte_memzone_lookup(mz_name);
3228                 total_alloc_len = RTE_CACHE_LINE_ROUNDUP(
3229                                 sizeof(struct rx_port_stats) + 512);
3230                 if (!mz) {
3231                         mz = rte_memzone_reserve(mz_name, total_alloc_len,
3232                                         SOCKET_ID_ANY,
3233                                         RTE_MEMZONE_2MB |
3234                                         RTE_MEMZONE_SIZE_HINT_ONLY |
3235                                         RTE_MEMZONE_IOVA_CONTIG);
3236                         if (mz == NULL)
3237                                 return -ENOMEM;
3238                 }
3239                 memset(mz->addr, 0, mz->len);
3240                 mz_phys_addr = mz->iova;
3241                 if ((unsigned long)mz->addr == mz_phys_addr) {
3242                         PMD_DRV_LOG(WARNING,
3243                                 "Memzone physical address same as virtual.\n");
3244                         PMD_DRV_LOG(WARNING,
3245                                 "Using rte_mem_virt2iova()\n");
3246                         mz_phys_addr = rte_mem_virt2iova(mz->addr);
3247                         if (mz_phys_addr == 0) {
3248                                 PMD_DRV_LOG(ERR,
3249                                 "unable to map address to physical memory\n");
3250                                 return -ENOMEM;
3251                         }
3252                 }
3253
3254                 bp->rx_mem_zone = (const void *)mz;
3255                 bp->hw_rx_port_stats = mz->addr;
3256                 bp->hw_rx_port_stats_map = mz_phys_addr;
3257
3258                 snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
3259                          "bnxt_%04x:%02x:%02x:%02x-%s", pci_dev->addr.domain,
3260                          pci_dev->addr.bus, pci_dev->addr.devid,
3261                          pci_dev->addr.function, "tx_port_stats");
3262                 mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
3263                 mz = rte_memzone_lookup(mz_name);
3264                 total_alloc_len = RTE_CACHE_LINE_ROUNDUP(
3265                                 sizeof(struct tx_port_stats) + 512);
3266                 if (!mz) {
3267                         mz = rte_memzone_reserve(mz_name,
3268                                         total_alloc_len,
3269                                         SOCKET_ID_ANY,
3270                                         RTE_MEMZONE_2MB |
3271                                         RTE_MEMZONE_SIZE_HINT_ONLY |
3272                                         RTE_MEMZONE_IOVA_CONTIG);
3273                         if (mz == NULL)
3274                                 return -ENOMEM;
3275                 }
3276                 memset(mz->addr, 0, mz->len);
3277                 mz_phys_addr = mz->iova;
3278                 if ((unsigned long)mz->addr == mz_phys_addr) {
3279                         PMD_DRV_LOG(WARNING,
3280                                 "Memzone physical address same as virtual.\n");
3281                         PMD_DRV_LOG(WARNING,
3282                                 "Using rte_mem_virt2iova()\n");
3283                         mz_phys_addr = rte_mem_virt2iova(mz->addr);
3284                         if (mz_phys_addr == 0) {
3285                                 PMD_DRV_LOG(ERR,
3286                                 "unable to map address to physical memory\n");
3287                                 return -ENOMEM;
3288                         }
3289                 }
3290
3291                 bp->tx_mem_zone = (const void *)mz;
3292                 bp->hw_tx_port_stats = mz->addr;
3293                 bp->hw_tx_port_stats_map = mz_phys_addr;
3294
3295                 bp->flags |= BNXT_FLAG_PORT_STATS;
3296         }
3297
3298         rc = bnxt_alloc_hwrm_resources(bp);
3299         if (rc) {
3300                 PMD_DRV_LOG(ERR,
3301                         "hwrm resource allocation failure rc: %x\n", rc);
3302                 goto error_free;
3303         }
3304         rc = bnxt_hwrm_ver_get(bp);
3305         if (rc)
3306                 goto error_free;
3307         rc = bnxt_hwrm_queue_qportcfg(bp);
3308         if (rc) {
3309                 PMD_DRV_LOG(ERR, "hwrm queue qportcfg failed\n");
3310                 goto error_free;
3311         }
3312
3313         rc = bnxt_hwrm_func_qcfg(bp);
3314         if (rc) {
3315                 PMD_DRV_LOG(ERR, "hwrm func qcfg failed\n");
3316                 goto error_free;
3317         }
3318
3319         /* Get the MAX capabilities for this function */
3320         rc = bnxt_hwrm_func_qcaps(bp);
3321         if (rc) {
3322                 PMD_DRV_LOG(ERR, "hwrm query capability failure rc: %x\n", rc);
3323                 goto error_free;
3324         }
3325         if (bp->max_tx_rings == 0) {
3326                 PMD_DRV_LOG(ERR, "No TX rings available!\n");
3327                 rc = -EBUSY;
3328                 goto error_free;
3329         }
3330         eth_dev->data->mac_addrs = rte_zmalloc("bnxt_mac_addr_tbl",
3331                                         ETHER_ADDR_LEN * bp->max_l2_ctx, 0);
3332         if (eth_dev->data->mac_addrs == NULL) {
3333                 PMD_DRV_LOG(ERR,
3334                         "Failed to alloc %u bytes needed to store MAC addr tbl",
3335                         ETHER_ADDR_LEN * bp->max_l2_ctx);
3336                 rc = -ENOMEM;
3337                 goto error_free;
3338         }
3339
3340         if (bnxt_check_zero_bytes(bp->dflt_mac_addr, ETHER_ADDR_LEN)) {
3341                 PMD_DRV_LOG(ERR,
3342                             "Invalid MAC addr %02X:%02X:%02X:%02X:%02X:%02X\n",
3343                             bp->dflt_mac_addr[0], bp->dflt_mac_addr[1],
3344                             bp->dflt_mac_addr[2], bp->dflt_mac_addr[3],
3345                             bp->dflt_mac_addr[4], bp->dflt_mac_addr[5]);
3346                 rc = -EINVAL;
3347                 goto error_free;
3348         }
3349         /* Copy the permanent MAC from the qcap response address now. */
3350         memcpy(bp->mac_addr, bp->dflt_mac_addr, sizeof(bp->mac_addr));
3351         memcpy(&eth_dev->data->mac_addrs[0], bp->mac_addr, ETHER_ADDR_LEN);
3352
3353         if (bp->max_ring_grps < bp->rx_cp_nr_rings) {
3354                 /* 1 ring is for default completion ring */
3355                 PMD_DRV_LOG(ERR, "Insufficient resource: Ring Group\n");
3356                 rc = -ENOSPC;
3357                 goto error_free;
3358         }
3359
3360         bp->grp_info = rte_zmalloc("bnxt_grp_info",
3361                                 sizeof(*bp->grp_info) * bp->max_ring_grps, 0);
3362         if (!bp->grp_info) {
3363                 PMD_DRV_LOG(ERR,
3364                         "Failed to alloc %zu bytes to store group info table\n",
3365                         sizeof(*bp->grp_info) * bp->max_ring_grps);
3366                 rc = -ENOMEM;
3367                 goto error_free;
3368         }
3369
3370         /* Forward all requests if firmware is new enough */
3371         if (((bp->fw_ver >= ((20 << 24) | (6 << 16) | (100 << 8))) &&
3372             (bp->fw_ver < ((20 << 24) | (7 << 16)))) ||
3373             ((bp->fw_ver >= ((20 << 24) | (8 << 16))))) {
3374                 memset(bp->pf.vf_req_fwd, 0xff, sizeof(bp->pf.vf_req_fwd));
3375         } else {
3376                 PMD_DRV_LOG(WARNING,
3377                         "Firmware too old for VF mailbox functionality\n");
3378                 memset(bp->pf.vf_req_fwd, 0, sizeof(bp->pf.vf_req_fwd));
3379         }
3380
3381         /*
3382          * The following are used for driver cleanup.  If we disallow these,
3383          * VF drivers can't clean up cleanly.
3384          */
3385         ALLOW_FUNC(HWRM_FUNC_DRV_UNRGTR);
3386         ALLOW_FUNC(HWRM_VNIC_FREE);
3387         ALLOW_FUNC(HWRM_RING_FREE);
3388         ALLOW_FUNC(HWRM_RING_GRP_FREE);
3389         ALLOW_FUNC(HWRM_VNIC_RSS_COS_LB_CTX_FREE);
3390         ALLOW_FUNC(HWRM_CFA_L2_FILTER_FREE);
3391         ALLOW_FUNC(HWRM_STAT_CTX_FREE);
3392         ALLOW_FUNC(HWRM_PORT_PHY_QCFG);
3393         ALLOW_FUNC(HWRM_VNIC_TPA_CFG);
3394         rc = bnxt_hwrm_func_driver_register(bp);
3395         if (rc) {
3396                 PMD_DRV_LOG(ERR,
3397                         "Failed to register driver");
3398                 rc = -EBUSY;
3399                 goto error_free;
3400         }
3401
3402         PMD_DRV_LOG(INFO,
3403                 DRV_MODULE_NAME " found at mem %" PRIx64 ", node addr %pM\n",
3404                 pci_dev->mem_resource[0].phys_addr,
3405                 pci_dev->mem_resource[0].addr);
3406
3407         rc = bnxt_hwrm_func_reset(bp);
3408         if (rc) {
3409                 PMD_DRV_LOG(ERR, "hwrm chip reset failure rc: %x\n", rc);
3410                 rc = -EIO;
3411                 goto error_free;
3412         }
3413
3414         if (BNXT_PF(bp)) {
3415                 //if (bp->pf.active_vfs) {
3416                         // TODO: Deallocate VF resources?
3417                 //}
3418                 if (bp->pdev->max_vfs) {
3419                         rc = bnxt_hwrm_allocate_vfs(bp, bp->pdev->max_vfs);
3420                         if (rc) {
3421                                 PMD_DRV_LOG(ERR, "Failed to allocate VFs\n");
3422                                 goto error_free;
3423                         }
3424                 } else {
3425                         rc = bnxt_hwrm_allocate_pf_only(bp);
3426                         if (rc) {
3427                                 PMD_DRV_LOG(ERR,
3428                                         "Failed to allocate PF resources\n");
3429                                 goto error_free;
3430                         }
3431                 }
3432         }
3433
3434         bnxt_hwrm_port_led_qcaps(bp);
3435
3436         rc = bnxt_setup_int(bp);
3437         if (rc)
3438                 goto error_free;
3439
3440         rc = bnxt_alloc_mem(bp);
3441         if (rc)
3442                 goto error_free_int;
3443
3444         rc = bnxt_request_int(bp);
3445         if (rc)
3446                 goto error_free_int;
3447
3448         bnxt_enable_int(bp);
3449         bnxt_init_nic(bp);
3450
3451         return 0;
3452
3453 error_free_int:
3454         bnxt_disable_int(bp);
3455         bnxt_hwrm_func_buf_unrgtr(bp);
3456         bnxt_free_int(bp);
3457         bnxt_free_mem(bp);
3458 error_free:
3459         bnxt_dev_uninit(eth_dev);
3460 error:
3461         return rc;
3462 }
3463
3464 static int
3465 bnxt_dev_uninit(struct rte_eth_dev *eth_dev)
3466 {
3467         struct bnxt *bp = eth_dev->data->dev_private;
3468         int rc;
3469
3470         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
3471                 return -EPERM;
3472
3473         PMD_DRV_LOG(DEBUG, "Calling Device uninit\n");
3474         bnxt_disable_int(bp);
3475         bnxt_free_int(bp);
3476         bnxt_free_mem(bp);
3477         if (eth_dev->data->mac_addrs != NULL) {
3478                 rte_free(eth_dev->data->mac_addrs);
3479                 eth_dev->data->mac_addrs = NULL;
3480         }
3481         if (bp->grp_info != NULL) {
3482                 rte_free(bp->grp_info);
3483                 bp->grp_info = NULL;
3484         }
3485         rc = bnxt_hwrm_func_driver_unregister(bp, 0);
3486         bnxt_free_hwrm_resources(bp);
3487
3488         if (bp->tx_mem_zone) {
3489                 rte_memzone_free((const struct rte_memzone *)bp->tx_mem_zone);
3490                 bp->tx_mem_zone = NULL;
3491         }
3492
3493         if (bp->rx_mem_zone) {
3494                 rte_memzone_free((const struct rte_memzone *)bp->rx_mem_zone);
3495                 bp->rx_mem_zone = NULL;
3496         }
3497
3498         if (bp->dev_stopped == 0)
3499                 bnxt_dev_close_op(eth_dev);
3500         if (bp->pf.vf_info)
3501                 rte_free(bp->pf.vf_info);
3502         eth_dev->dev_ops = NULL;
3503         eth_dev->rx_pkt_burst = NULL;
3504         eth_dev->tx_pkt_burst = NULL;
3505
3506         return rc;
3507 }
3508
3509 static int bnxt_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
3510         struct rte_pci_device *pci_dev)
3511 {
3512         return rte_eth_dev_pci_generic_probe(pci_dev, sizeof(struct bnxt),
3513                 bnxt_dev_init);
3514 }
3515
3516 static int bnxt_pci_remove(struct rte_pci_device *pci_dev)
3517 {
3518         return rte_eth_dev_pci_generic_remove(pci_dev, bnxt_dev_uninit);
3519 }
3520
3521 static struct rte_pci_driver bnxt_rte_pmd = {
3522         .id_table = bnxt_pci_id_map,
3523         .drv_flags = RTE_PCI_DRV_NEED_MAPPING |
3524                 RTE_PCI_DRV_INTR_LSC,
3525         .probe = bnxt_pci_probe,
3526         .remove = bnxt_pci_remove,
3527 };
3528
3529 static bool
3530 is_device_supported(struct rte_eth_dev *dev, struct rte_pci_driver *drv)
3531 {
3532         if (strcmp(dev->device->driver->name, drv->driver.name))
3533                 return false;
3534
3535         return true;
3536 }
3537
3538 bool is_bnxt_supported(struct rte_eth_dev *dev)
3539 {
3540         return is_device_supported(dev, &bnxt_rte_pmd);
3541 }
3542
3543 RTE_INIT(bnxt_init_log)
3544 {
3545         bnxt_logtype_driver = rte_log_register("pmd.bnxt.driver");
3546         if (bnxt_logtype_driver >= 0)
3547                 rte_log_set_level(bnxt_logtype_driver, RTE_LOG_INFO);
3548 }
3549
3550 RTE_PMD_REGISTER_PCI(net_bnxt, bnxt_rte_pmd);
3551 RTE_PMD_REGISTER_PCI_TABLE(net_bnxt, bnxt_pci_id_map);
3552 RTE_PMD_REGISTER_KMOD_DEP(net_bnxt, "* igb_uio | uio_pci_generic | vfio-pci");