drivers/net/bnxt/bnxt_filter.h

   1 /*-
   2  *   BSD LICENSE
   3  *
   4  *   Copyright(c) Broadcom Limited.
   5  *   All rights reserved.
   6  *
   7  *   Redistribution and use in source and binary forms, with or without
   8  *   modification, are permitted provided that the following conditions
   9  *   are met:
  10  *
  11  *     * Redistributions of source code must retain the above copyright
  12  *       notice, this list of conditions and the following disclaimer.
  13  *     * Redistributions in binary form must reproduce the above copyright
  14  *       notice, this list of conditions and the following disclaimer in
  15  *       the documentation and/or other materials provided with the
  16  *       distribution.
  17  *     * Neither the name of Broadcom Corporation nor the names of its
  18  *       contributors may be used to endorse or promote products derived
  19  *       from this software without specific prior written permission.
  20  *
  21  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 #ifndef _BNXT_FILTER_H_
  35 #define _BNXT_FILTER_H_
  36
  37 #include <rte_ether.h>
  38
  39 struct bnxt;
  40 struct bnxt_filter_info {
  41         STAILQ_ENTRY(bnxt_filter_info)  next;
  42         uint64_t                fw_l2_filter_id;
  43         uint64_t                fw_em_filter_id;
  44         uint64_t                fw_ntuple_filter_id;
  45 #define INVALID_MAC_INDEX       ((uint16_t)-1)
  46         uint16_t                mac_index;
  47 #define HWRM_CFA_L2_FILTER      0
  48 #define HWRM_CFA_EM_FILTER      1
  49 #define HWRM_CFA_NTUPLE_FILTER  2
  50         uint8_t                 filter_type;    //L2 or EM or NTUPLE filter
  51         uint32_t                dst_id;
  52
  53         /* Filter Characteristics */
  54         uint32_t                flags;
  55         uint32_t                enables;
  56         uint8_t                 l2_addr[ETHER_ADDR_LEN];
  57         uint8_t                 l2_addr_mask[ETHER_ADDR_LEN];
  58         uint16_t                l2_ovlan;
  59         uint16_t                l2_ovlan_mask;
  60         uint16_t                l2_ivlan;
  61         uint16_t                l2_ivlan_mask;
  62         uint8_t                 t_l2_addr[ETHER_ADDR_LEN];
  63         uint8_t                 t_l2_addr_mask[ETHER_ADDR_LEN];
  64         uint16_t                t_l2_ovlan;
  65         uint16_t                t_l2_ovlan_mask;
  66         uint16_t                t_l2_ivlan;
  67         uint16_t                t_l2_ivlan_mask;
  68         uint8_t                 tunnel_type;
  69         uint16_t                mirror_vnic_id;
  70         uint32_t                vni;
  71         uint8_t                 pri_hint;
  72         uint64_t                l2_filter_id_hint;
  73         uint32_t                src_id;
  74         uint8_t                 src_type;
  75         uint8_t                 src_macaddr[6];
  76         uint8_t                 dst_macaddr[6];
  77         uint32_t                dst_ipaddr[4];
  78         uint32_t                dst_ipaddr_mask[4];
  79         uint32_t                src_ipaddr[4];
  80         uint32_t                src_ipaddr_mask[4];
  81         uint16_t                dst_port;
  82         uint16_t                dst_port_mask;
  83         uint16_t                src_port;
  84         uint16_t                src_port_mask;
  85         uint16_t                ip_protocol;
  86         uint16_t                ip_addr_type;
  87         uint16_t                ethertype;
  88 };
  89
  90 struct bnxt_filter_info *bnxt_alloc_filter(struct bnxt *bp);
  91 struct bnxt_filter_info *bnxt_alloc_vf_filter(struct bnxt *bp, uint16_t vf);
  92 void bnxt_init_filters(struct bnxt *bp);
  93 void bnxt_free_all_filters(struct bnxt *bp);
  94 void bnxt_free_filter_mem(struct bnxt *bp);
  95 int bnxt_alloc_filter_mem(struct bnxt *bp);
  96 struct bnxt_filter_info *bnxt_get_unused_filter(struct bnxt *bp);
  97 void bnxt_free_filter(struct bnxt *bp, struct bnxt_filter_info *filter);
  98 struct bnxt_filter_info *bnxt_get_l2_filter(struct bnxt *bp,
  99                 struct bnxt_filter_info *nf, struct bnxt_vnic_info *vnic);
 100 int check_zero_bytes(const uint8_t *bytes, int len);
 101
 102 #define NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_MACADDR  \
 103         HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_MACADDR
 104 #define EM_FLOW_ALLOC_INPUT_EN_SRC_MACADDR      \
 105         HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_MACADDR
 106 #define NTUPLE_FLTR_ALLOC_INPUT_EN_DST_MACADDR  \
 107         HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_MACADDR
 108 #define EM_FLOW_ALLOC_INPUT_EN_DST_MACADDR      \
 109         HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_MACADDR
 110 #define NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE   \
 111         HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_ETHERTYPE
 112 #define EM_FLOW_ALLOC_INPUT_EN_ETHERTYPE       \
 113         HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_ETHERTYPE
 114 #define EM_FLOW_ALLOC_INPUT_EN_OVLAN_VID       \
 115         HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_OVLAN_VID
 116 #define NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR  \
 117         HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_IPADDR
 118 #define NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK     \
 119         HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_IPADDR_MASK
 120 #define NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR  \
 121         HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_IPADDR
 122 #define NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK     \
 123         HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_IPADDR_MASK
 124 #define NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT    \
 125         HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_PORT
 126 #define NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK       \
 127         HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_PORT_MASK
 128 #define NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT    \
 129         HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_PORT
 130 #define NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK       \
 131         HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_PORT_MASK
 132 #define NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO        \
 133         HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_IP_PROTOCOL
 134 #define EM_FLOW_ALLOC_INPUT_EN_SRC_IPADDR       \
 135         HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_IPADDR
 136 #define EM_FLOW_ALLOC_INPUT_EN_DST_IPADDR       \
 137         HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_IPADDR
 138 #define EM_FLOW_ALLOC_INPUT_EN_SRC_PORT \
 139         HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_PORT
 140 #define EM_FLOW_ALLOC_INPUT_EN_DST_PORT \
 141         HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_PORT
 142 #define EM_FLOW_ALLOC_INPUT_EN_IP_PROTO \
 143         HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IP_PROTOCOL
 144 #define EM_FLOW_ALLOC_INPUT_IP_ADDR_TYPE_IPV6   \
 145         HWRM_CFA_EM_FLOW_ALLOC_INPUT_IP_ADDR_TYPE_IPV6
 146 #define NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV6       \
 147         HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_IP_ADDR_TYPE_IPV6
 148 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN   \
 149         HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN
 150 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_NVGRE   \
 151         HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_NVGRE
 152 #define L2_FILTER_ALLOC_INPUT_EN_L2_ADDR_MASK   \
 153         HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR_MASK
 154 #define NTUPLE_FLTR_ALLOC_INPUT_IP_PROTOCOL_UDP \
 155         HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_IP_PROTOCOL_UDP
 156 #define NTUPLE_FLTR_ALLOC_INPUT_IP_PROTOCOL_TCP \
 157         HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_IP_PROTOCOL_TCP
 158 #define NTUPLE_FLTR_ALLOC_INPUT_IP_PROTOCOL_UNKNOWN     \
 159         HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_IP_PROTOCOL_UNKNOWN
 160 #define NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4       \
 161         HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_IP_ADDR_TYPE_IPV4
 162 #define NTUPLE_FLTR_ALLOC_INPUT_EN_MIRROR_VNIC_ID       \
 163         HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID
 164 #define NTUPLE_FLTR_ALLOC_INPUT_EN_MIRROR_VNIC_ID       \
 165         HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID
 166 #endif