drivers/net/bnxt/bnxt_hwrm.c

   1 /*-
   2  *   BSD LICENSE
   3  *
   4  *   Copyright(c) Broadcom Limited.
   5  *   All rights reserved.
   6  *
   7  *   Redistribution and use in source and binary forms, with or without
   8  *   modification, are permitted provided that the following conditions
   9  *   are met:
  10  *
  11  *     * Redistributions of source code must retain the above copyright
  12  *       notice, this list of conditions and the following disclaimer.
  13  *     * Redistributions in binary form must reproduce the above copyright
  14  *       notice, this list of conditions and the following disclaimer in
  15  *       the documentation and/or other materials provided with the
  16  *       distribution.
  17  *     * Neither the name of Broadcom Corporation nor the names of its
  18  *       contributors may be used to endorse or promote products derived
  19  *       from this software without specific prior written permission.
  20  *
  21  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 #include <unistd.h>
  35
  36 #include <rte_byteorder.h>
  37 #include <rte_common.h>
  38 #include <rte_cycles.h>
  39 #include <rte_malloc.h>
  40 #include <rte_memzone.h>
  41 #include <rte_version.h>
  42
  43 #include "bnxt.h"
  44 #include "bnxt_cpr.h"
  45 #include "bnxt_filter.h"
  46 #include "bnxt_hwrm.h"
  47 #include "bnxt_rxq.h"
  48 #include "bnxt_rxr.h"
  49 #include "bnxt_ring.h"
  50 #include "bnxt_txq.h"
  51 #include "bnxt_txr.h"
  52 #include "bnxt_vnic.h"
  53 #include "hsi_struct_def_dpdk.h"
  54
  55 #include <rte_io.h>
  56
  57 #define HWRM_CMD_TIMEOUT                10000
  58
  59 struct bnxt_plcmodes_cfg {
  60         uint32_t        flags;
  61         uint16_t        jumbo_thresh;
  62         uint16_t        hds_offset;
  63         uint16_t        hds_threshold;
  64 };
  65
  66 static int page_getenum(size_t size)
  67 {
  68         if (size <= 1 << 4)
  69                 return 4;
  70         if (size <= 1 << 12)
  71                 return 12;
  72         if (size <= 1 << 13)
  73                 return 13;
  74         if (size <= 1 << 16)
  75                 return 16;
  76         if (size <= 1 << 21)
  77                 return 21;
  78         if (size <= 1 << 22)
  79                 return 22;
  80         if (size <= 1 << 30)
  81                 return 30;
  82         RTE_LOG(ERR, PMD, "Page size %zu out of range\n", size);
  83         return sizeof(void *) * 8 - 1;
  84 }
  85
  86 static int page_roundup(size_t size)
  87 {
  88         return 1 << page_getenum(size);
  89 }
  90
  91 /*
  92  * HWRM Functions (sent to HWRM)
  93  * These are named bnxt_hwrm_*() and return -1 if bnxt_hwrm_send_message()
  94  * fails (ie: a timeout), and a positive non-zero HWRM error code if the HWRM
  95  * command was failed by the ChiMP.
  96  */
  97
  98 static int bnxt_hwrm_send_message(struct bnxt *bp, void *msg,
  99                                         uint32_t msg_len)
 100 {
 101         unsigned int i;
 102         struct input *req = msg;
 103         struct output *resp = bp->hwrm_cmd_resp_addr;
 104         uint32_t *data = msg;
 105         uint8_t *bar;
 106         uint8_t *valid;
 107         uint16_t max_req_len = bp->max_req_len;
 108         struct hwrm_short_input short_input = { 0 };
 109
 110         if (bp->flags & BNXT_FLAG_SHORT_CMD) {
 111                 void *short_cmd_req = bp->hwrm_short_cmd_req_addr;
 112
 113                 memset(short_cmd_req, 0, bp->max_req_len);
 114                 memcpy(short_cmd_req, req, msg_len);
 115
 116                 short_input.req_type = rte_cpu_to_le_16(req->req_type);
 117                 short_input.signature = rte_cpu_to_le_16(
 118                                         HWRM_SHORT_REQ_SIGNATURE_SHORT_CMD);
 119                 short_input.size = rte_cpu_to_le_16(msg_len);
 120                 short_input.req_addr =
 121                         rte_cpu_to_le_64(bp->hwrm_short_cmd_req_dma_addr);
 122
 123                 data = (uint32_t *)&short_input;
 124                 msg_len = sizeof(short_input);
 125
 126                 /* Sync memory write before updating doorbell */
 127                 rte_wmb();
 128
 129                 max_req_len = BNXT_HWRM_SHORT_REQ_LEN;
 130         }
 131
 132         /* Write request msg to hwrm channel */
 133         for (i = 0; i < msg_len; i += 4) {
 134                 bar = (uint8_t *)bp->bar0 + i;
 135                 rte_write32(*data, bar);
 136                 data++;
 137         }
 138
 139         /* Zero the rest of the request space */
 140         for (; i < max_req_len; i += 4) {
 141                 bar = (uint8_t *)bp->bar0 + i;
 142                 rte_write32(0, bar);
 143         }
 144
 145         /* Ring channel doorbell */
 146         bar = (uint8_t *)bp->bar0 + 0x100;
 147         rte_write32(1, bar);
 148
 149         /* Poll for the valid bit */
 150         for (i = 0; i < HWRM_CMD_TIMEOUT; i++) {
 151                 /* Sanity check on the resp->resp_len */
 152                 rte_rmb();
 153                 if (resp->resp_len && resp->resp_len <=
 154                                 bp->max_resp_len) {
 155                         /* Last byte of resp contains the valid key */
 156                         valid = (uint8_t *)resp + resp->resp_len - 1;
 157                         if (*valid == HWRM_RESP_VALID_KEY)
 158                                 break;
 159                 }
 160                 rte_delay_us(600);
 161         }
 162
 163         if (i >= HWRM_CMD_TIMEOUT) {
 164                 RTE_LOG(ERR, PMD, "Error sending msg 0x%04x\n",
 165                         req->req_type);
 166                 goto err_ret;
 167         }
 168         return 0;
 169
 170 err_ret:
 171         return -1;
 172 }
 173
 174 /*
 175  * HWRM_PREP() should be used to prepare *ALL* HWRM commands.  It grabs the
 176  * spinlock, and does initial processing.
 177  *
 178  * HWRM_CHECK_RESULT() returns errors on failure and may not be used.  It
 179  * releases the spinlock only if it returns.  If the regular int return codes
 180  * are not used by the function, HWRM_CHECK_RESULT() should not be used
 181  * directly, rather it should be copied and modified to suit the function.
 182  *
 183  * HWRM_UNLOCK() must be called after all response processing is completed.
 184  */
 185 #define HWRM_PREP(req, type) do { \
 186         rte_spinlock_lock(&bp->hwrm_lock); \
 187         memset(bp->hwrm_cmd_resp_addr, 0, bp->max_resp_len); \
 188         req.req_type = rte_cpu_to_le_16(HWRM_##type); \
 189         req.cmpl_ring = rte_cpu_to_le_16(-1); \
 190         req.seq_id = rte_cpu_to_le_16(bp->hwrm_cmd_seq++); \
 191         req.target_id = rte_cpu_to_le_16(0xffff); \
 192         req.resp_addr = rte_cpu_to_le_64(bp->hwrm_cmd_resp_dma_addr); \
 193 } while (0)
 194
 195 #define HWRM_CHECK_RESULT() do {\
 196         if (rc) { \
 197                 RTE_LOG(ERR, PMD, "%s failed rc:%d\n", \
 198                         __func__, rc); \
 199                 rte_spinlock_unlock(&bp->hwrm_lock); \
 200                 return rc; \
 201         } \
 202         if (resp->error_code) { \
 203                 rc = rte_le_to_cpu_16(resp->error_code); \
 204                 if (resp->resp_len >= 16) { \
 205                         struct hwrm_err_output *tmp_hwrm_err_op = \
 206                                                 (void *)resp; \
 207                         RTE_LOG(ERR, PMD, \
 208                                 "%s error %d:%d:%08x:%04x\n", \
 209                                 __func__, \
 210                                 rc, tmp_hwrm_err_op->cmd_err, \
 211                                 rte_le_to_cpu_32(\
 212                                         tmp_hwrm_err_op->opaque_0), \
 213                                 rte_le_to_cpu_16(\
 214                                         tmp_hwrm_err_op->opaque_1)); \
 215                 } \
 216                 else { \
 217                         RTE_LOG(ERR, PMD, \
 218                                 "%s error %d\n", __func__, rc); \
 219                 } \
 220                 rte_spinlock_unlock(&bp->hwrm_lock); \
 221                 return rc; \
 222         } \
 223 } while (0)
 224
 225 #define HWRM_UNLOCK()           rte_spinlock_unlock(&bp->hwrm_lock)
 226
 227 int bnxt_hwrm_cfa_l2_clear_rx_mask(struct bnxt *bp, struct bnxt_vnic_info *vnic)
 228 {
 229         int rc = 0;
 230         struct hwrm_cfa_l2_set_rx_mask_input req = {.req_type = 0 };
 231         struct hwrm_cfa_l2_set_rx_mask_output *resp = bp->hwrm_cmd_resp_addr;
 232
 233         HWRM_PREP(req, CFA_L2_SET_RX_MASK);
 234         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
 235         req.mask = 0;
 236
 237         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
 238
 239         HWRM_CHECK_RESULT();
 240         HWRM_UNLOCK();
 241
 242         return rc;
 243 }
 244
 245 int bnxt_hwrm_cfa_l2_set_rx_mask(struct bnxt *bp,
 246                                  struct bnxt_vnic_info *vnic,
 247                                  uint16_t vlan_count,
 248                                  struct bnxt_vlan_table_entry *vlan_table)
 249 {
 250         int rc = 0;
 251         struct hwrm_cfa_l2_set_rx_mask_input req = {.req_type = 0 };
 252         struct hwrm_cfa_l2_set_rx_mask_output *resp = bp->hwrm_cmd_resp_addr;
 253         uint32_t mask = 0;
 254
 255         HWRM_PREP(req, CFA_L2_SET_RX_MASK);
 256         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
 257
 258         /* FIXME add multicast flag, when multicast adding options is supported
 259          * by ethtool.
 260          */
 261         if (vnic->flags & BNXT_VNIC_INFO_BCAST)
 262                 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_BCAST;
 263         if (vnic->flags & BNXT_VNIC_INFO_UNTAGGED)
 264                 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_VLAN_NONVLAN;
 265         if (vnic->flags & BNXT_VNIC_INFO_PROMISC)
 266                 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_PROMISCUOUS;
 267         if (vnic->flags & BNXT_VNIC_INFO_ALLMULTI)
 268                 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_ALL_MCAST;
 269         if (vnic->flags & BNXT_VNIC_INFO_MCAST)
 270                 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_MCAST;
 271         if (vnic->mc_addr_cnt) {
 272                 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_MCAST;
 273                 req.num_mc_entries = rte_cpu_to_le_32(vnic->mc_addr_cnt);
 274                 req.mc_tbl_addr = rte_cpu_to_le_64(vnic->mc_list_dma_addr);
 275         }
 276         if (vlan_table) {
 277                 if (!(mask & HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_VLAN_NONVLAN))
 278                         mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_VLANONLY;
 279                 req.vlan_tag_tbl_addr = rte_cpu_to_le_64(
 280                          rte_mem_virt2iova(vlan_table));
 281                 req.num_vlan_tags = rte_cpu_to_le_32((uint32_t)vlan_count);
 282         }
 283         req.mask = rte_cpu_to_le_32(mask);
 284
 285         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
 286
 287         HWRM_CHECK_RESULT();
 288         HWRM_UNLOCK();
 289
 290         return rc;
 291 }
 292
 293 int bnxt_hwrm_cfa_vlan_antispoof_cfg(struct bnxt *bp, uint16_t fid,
 294                         uint16_t vlan_count,
 295                         struct bnxt_vlan_antispoof_table_entry *vlan_table)
 296 {
 297         int rc = 0;
 298         struct hwrm_cfa_vlan_antispoof_cfg_input req = {.req_type = 0 };
 299         struct hwrm_cfa_vlan_antispoof_cfg_output *resp =
 300                                                 bp->hwrm_cmd_resp_addr;
 301
 302         /*
 303          * Older HWRM versions did not support this command, and the set_rx_mask
 304          * list was used for anti-spoof. In 1.8.0, the TX path configuration was
 305          * removed from set_rx_mask call, and this command was added.
 306          *
 307          * This command is also present from 1.7.8.11 and higher,
 308          * as well as 1.7.8.0
 309          */
 310         if (bp->fw_ver < ((1 << 24) | (8 << 16))) {
 311                 if (bp->fw_ver != ((1 << 24) | (7 << 16) | (8 << 8))) {
 312                         if (bp->fw_ver < ((1 << 24) | (7 << 16) | (8 << 8) |
 313                                         (11)))
 314                                 return 0;
 315                 }
 316         }
 317         HWRM_PREP(req, CFA_VLAN_ANTISPOOF_CFG);
 318         req.fid = rte_cpu_to_le_16(fid);
 319
 320         req.vlan_tag_mask_tbl_addr =
 321                 rte_cpu_to_le_64(rte_mem_virt2iova(vlan_table));
 322         req.num_vlan_entries = rte_cpu_to_le_32((uint32_t)vlan_count);
 323
 324         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
 325
 326         HWRM_CHECK_RESULT();
 327         HWRM_UNLOCK();
 328
 329         return rc;
 330 }
 331
 332 int bnxt_hwrm_clear_l2_filter(struct bnxt *bp,
 333                            struct bnxt_filter_info *filter)
 334 {
 335         int rc = 0;
 336         struct hwrm_cfa_l2_filter_free_input req = {.req_type = 0 };
 337         struct hwrm_cfa_l2_filter_free_output *resp = bp->hwrm_cmd_resp_addr;
 338
 339         if (filter->fw_l2_filter_id == UINT64_MAX)
 340                 return 0;
 341
 342         HWRM_PREP(req, CFA_L2_FILTER_FREE);
 343
 344         req.l2_filter_id = rte_cpu_to_le_64(filter->fw_l2_filter_id);
 345
 346         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
 347
 348         HWRM_CHECK_RESULT();
 349         HWRM_UNLOCK();
 350
 351         filter->fw_l2_filter_id = -1;
 352
 353         return 0;
 354 }
 355
 356 int bnxt_hwrm_set_l2_filter(struct bnxt *bp,
 357                          uint16_t dst_id,
 358                          struct bnxt_filter_info *filter)
 359 {
 360         int rc = 0;
 361         struct hwrm_cfa_l2_filter_alloc_input req = {.req_type = 0 };
 362         struct hwrm_cfa_l2_filter_alloc_output *resp = bp->hwrm_cmd_resp_addr;
 363         struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
 364         const struct rte_eth_vmdq_rx_conf *conf =
 365                     &dev_conf->rx_adv_conf.vmdq_rx_conf;
 366         uint32_t enables = 0;
 367         uint16_t j = dst_id - 1;
 368
 369         //TODO: Is there a better way to add VLANs to each VNIC in case of VMDQ
 370         if ((dev_conf->rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG) &&
 371             conf->pool_map[j].pools & (1UL << j)) {
 372                 RTE_LOG(DEBUG, PMD,
 373                         "Add vlan %u to vmdq pool %u\n",
 374                         conf->pool_map[j].vlan_id, j);
 375
 376                 filter->l2_ivlan = conf->pool_map[j].vlan_id;
 377                 filter->enables |=
 378                         HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN |
 379                         HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN_MASK;
 380         }
 381
 382         if (filter->fw_l2_filter_id != UINT64_MAX)
 383                 bnxt_hwrm_clear_l2_filter(bp, filter);
 384
 385         HWRM_PREP(req, CFA_L2_FILTER_ALLOC);
 386
 387         req.flags = rte_cpu_to_le_32(filter->flags);
 388
 389         enables = filter->enables |
 390               HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_DST_ID;
 391         req.dst_id = rte_cpu_to_le_16(dst_id);
 392
 393         if (enables &
 394             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR)
 395                 memcpy(req.l2_addr, filter->l2_addr,
 396                        ETHER_ADDR_LEN);
 397         if (enables &
 398             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR_MASK)
 399                 memcpy(req.l2_addr_mask, filter->l2_addr_mask,
 400                        ETHER_ADDR_LEN);
 401         if (enables &
 402             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN)
 403                 req.l2_ovlan = filter->l2_ovlan;
 404         if (enables &
 405             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN)
 406                 req.l2_ovlan = filter->l2_ivlan;
 407         if (enables &
 408             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN_MASK)
 409                 req.l2_ovlan_mask = filter->l2_ovlan_mask;
 410         if (enables &
 411             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN_MASK)
 412                 req.l2_ovlan_mask = filter->l2_ivlan_mask;
 413         if (enables & HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_SRC_ID)
 414                 req.src_id = rte_cpu_to_le_32(filter->src_id);
 415         if (enables & HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_SRC_TYPE)
 416                 req.src_type = filter->src_type;
 417
 418         req.enables = rte_cpu_to_le_32(enables);
 419
 420         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
 421
 422         HWRM_CHECK_RESULT();
 423
 424         filter->fw_l2_filter_id = rte_le_to_cpu_64(resp->l2_filter_id);
 425         HWRM_UNLOCK();
 426
 427         return rc;
 428 }
 429
 430 int bnxt_hwrm_func_qcaps(struct bnxt *bp)
 431 {
 432         int rc = 0;
 433         struct hwrm_func_qcaps_input req = {.req_type = 0 };
 434         struct hwrm_func_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
 435         uint16_t new_max_vfs;
 436         int i;
 437
 438         HWRM_PREP(req, FUNC_QCAPS);
 439
 440         req.fid = rte_cpu_to_le_16(0xffff);
 441
 442         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
 443
 444         HWRM_CHECK_RESULT();
 445
 446         bp->max_ring_grps = rte_le_to_cpu_32(resp->max_hw_ring_grps);
 447         if (BNXT_PF(bp)) {
 448                 bp->pf.port_id = resp->port_id;
 449                 bp->pf.first_vf_id = rte_le_to_cpu_16(resp->first_vf_id);
 450                 new_max_vfs = bp->pdev->max_vfs;
 451                 if (new_max_vfs != bp->pf.max_vfs) {
 452                         if (bp->pf.vf_info)
 453                                 rte_free(bp->pf.vf_info);
 454                         bp->pf.vf_info = rte_malloc("bnxt_vf_info",
 455                             sizeof(bp->pf.vf_info[0]) * new_max_vfs, 0);
 456                         bp->pf.max_vfs = new_max_vfs;
 457                         for (i = 0; i < new_max_vfs; i++) {
 458                                 bp->pf.vf_info[i].fid = bp->pf.first_vf_id + i;
 459                                 bp->pf.vf_info[i].vlan_table =
 460                                         rte_zmalloc("VF VLAN table",
 461                                                     getpagesize(),
 462                                                     getpagesize());
 463                                 if (bp->pf.vf_info[i].vlan_table == NULL)
 464                                         RTE_LOG(ERR, PMD,
 465                                         "Fail to alloc VLAN table for VF %d\n",
 466                                         i);
 467                                 else
 468                                         rte_mem_lock_page(
 469                                                 bp->pf.vf_info[i].vlan_table);
 470                                 bp->pf.vf_info[i].vlan_as_table =
 471                                         rte_zmalloc("VF VLAN AS table",
 472                                                     getpagesize(),
 473                                                     getpagesize());
 474                                 if (bp->pf.vf_info[i].vlan_as_table == NULL)
 475                                         RTE_LOG(ERR, PMD,
 476                                         "Alloc VLAN AS table for VF %d fail\n",
 477                                         i);
 478                                 else
 479                                         rte_mem_lock_page(
 480                                                bp->pf.vf_info[i].vlan_as_table);
 481                                 STAILQ_INIT(&bp->pf.vf_info[i].filter);
 482                         }
 483                 }
 484         }
 485
 486         bp->fw_fid = rte_le_to_cpu_32(resp->fid);
 487         memcpy(bp->dflt_mac_addr, &resp->mac_address, ETHER_ADDR_LEN);
 488         bp->max_rsscos_ctx = rte_le_to_cpu_16(resp->max_rsscos_ctx);
 489         bp->max_cp_rings = rte_le_to_cpu_16(resp->max_cmpl_rings);
 490         bp->max_tx_rings = rte_le_to_cpu_16(resp->max_tx_rings);
 491         bp->max_rx_rings = rte_le_to_cpu_16(resp->max_rx_rings);
 492         bp->max_l2_ctx = rte_le_to_cpu_16(resp->max_l2_ctxs);
 493         /* TODO: For now, do not support VMDq/RFS on VFs. */
 494         if (BNXT_PF(bp)) {
 495                 if (bp->pf.max_vfs)
 496                         bp->max_vnics = 1;
 497                 else
 498                         bp->max_vnics = rte_le_to_cpu_16(resp->max_vnics);
 499         } else {
 500                 bp->max_vnics = 1;
 501         }
 502         bp->max_stat_ctx = rte_le_to_cpu_16(resp->max_stat_ctx);
 503         if (BNXT_PF(bp))
 504                 bp->pf.total_vnics = rte_le_to_cpu_16(resp->max_vnics);
 505         HWRM_UNLOCK();
 506
 507         return rc;
 508 }
 509
 510 int bnxt_hwrm_func_reset(struct bnxt *bp)
 511 {
 512         int rc = 0;
 513         struct hwrm_func_reset_input req = {.req_type = 0 };
 514         struct hwrm_func_reset_output *resp = bp->hwrm_cmd_resp_addr;
 515
 516         HWRM_PREP(req, FUNC_RESET);
 517
 518         req.enables = rte_cpu_to_le_32(0);
 519
 520         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
 521
 522         HWRM_CHECK_RESULT();
 523         HWRM_UNLOCK();
 524
 525         return rc;
 526 }
 527
 528 int bnxt_hwrm_func_driver_register(struct bnxt *bp)
 529 {
 530         int rc;
 531         struct hwrm_func_drv_rgtr_input req = {.req_type = 0 };
 532         struct hwrm_func_drv_rgtr_output *resp = bp->hwrm_cmd_resp_addr;
 533
 534         if (bp->flags & BNXT_FLAG_REGISTERED)
 535                 return 0;
 536
 537         HWRM_PREP(req, FUNC_DRV_RGTR);
 538         req.enables = rte_cpu_to_le_32(HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_VER |
 539                         HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_ASYNC_EVENT_FWD);
 540         req.ver_maj = RTE_VER_YEAR;
 541         req.ver_min = RTE_VER_MONTH;
 542         req.ver_upd = RTE_VER_MINOR;
 543
 544         if (BNXT_PF(bp)) {
 545                 req.enables |= rte_cpu_to_le_32(
 546                         HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_VF_INPUT_FWD);
 547                 memcpy(req.vf_req_fwd, bp->pf.vf_req_fwd,
 548                        RTE_MIN(sizeof(req.vf_req_fwd),
 549                                sizeof(bp->pf.vf_req_fwd)));
 550         }
 551
 552         req.async_event_fwd[0] |= rte_cpu_to_le_32(0x1);   /* TODO: Use MACRO */
 553         memset(req.async_event_fwd, 0xff, sizeof(req.async_event_fwd));
 554
 555         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
 556
 557         HWRM_CHECK_RESULT();
 558         HWRM_UNLOCK();
 559
 560         bp->flags |= BNXT_FLAG_REGISTERED;
 561
 562         return rc;
 563 }
 564
 565 int bnxt_hwrm_ver_get(struct bnxt *bp)
 566 {
 567         int rc = 0;
 568         struct hwrm_ver_get_input req = {.req_type = 0 };
 569         struct hwrm_ver_get_output *resp = bp->hwrm_cmd_resp_addr;
 570         uint32_t my_version;
 571         uint32_t fw_version;
 572         uint16_t max_resp_len;
 573         char type[RTE_MEMZONE_NAMESIZE];
 574         uint32_t dev_caps_cfg;
 575
 576         bp->max_req_len = HWRM_MAX_REQ_LEN;
 577         HWRM_PREP(req, VER_GET);
 578
 579         req.hwrm_intf_maj = HWRM_VERSION_MAJOR;
 580         req.hwrm_intf_min = HWRM_VERSION_MINOR;
 581         req.hwrm_intf_upd = HWRM_VERSION_UPDATE;
 582
 583         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
 584
 585         HWRM_CHECK_RESULT();
 586
 587         RTE_LOG(INFO, PMD, "%d.%d.%d:%d.%d.%d\n",
 588                 resp->hwrm_intf_maj, resp->hwrm_intf_min,
 589                 resp->hwrm_intf_upd,
 590                 resp->hwrm_fw_maj, resp->hwrm_fw_min, resp->hwrm_fw_bld);
 591         bp->fw_ver = (resp->hwrm_fw_maj << 24) | (resp->hwrm_fw_min << 16) |
 592                         (resp->hwrm_fw_bld << 8) | resp->hwrm_fw_rsvd;
 593         RTE_LOG(INFO, PMD, "Driver HWRM version: %d.%d.%d\n",
 594                 HWRM_VERSION_MAJOR, HWRM_VERSION_MINOR, HWRM_VERSION_UPDATE);
 595
 596         my_version = HWRM_VERSION_MAJOR << 16;
 597         my_version |= HWRM_VERSION_MINOR << 8;
 598         my_version |= HWRM_VERSION_UPDATE;
 599
 600         fw_version = resp->hwrm_intf_maj << 16;
 601         fw_version |= resp->hwrm_intf_min << 8;
 602         fw_version |= resp->hwrm_intf_upd;
 603
 604         if (resp->hwrm_intf_maj != HWRM_VERSION_MAJOR) {
 605                 RTE_LOG(ERR, PMD, "Unsupported firmware API version\n");
 606                 rc = -EINVAL;
 607                 goto error;
 608         }
 609
 610         if (my_version != fw_version) {
 611                 RTE_LOG(INFO, PMD, "BNXT Driver/HWRM API mismatch.\n");
 612                 if (my_version < fw_version) {
 613                         RTE_LOG(INFO, PMD,
 614                                 "Firmware API version is newer than driver.\n");
 615                         RTE_LOG(INFO, PMD,
 616                                 "The driver may be missing features.\n");
 617                 } else {
 618                         RTE_LOG(INFO, PMD,
 619                                 "Firmware API version is older than driver.\n");
 620                         RTE_LOG(INFO, PMD,
 621                                 "Not all driver features may be functional.\n");
 622                 }
 623         }
 624
 625         if (bp->max_req_len > resp->max_req_win_len) {
 626                 RTE_LOG(ERR, PMD, "Unsupported request length\n");
 627                 rc = -EINVAL;
 628         }
 629         bp->max_req_len = rte_le_to_cpu_16(resp->max_req_win_len);
 630         max_resp_len = resp->max_resp_len;
 631         dev_caps_cfg = rte_le_to_cpu_32(resp->dev_caps_cfg);
 632
 633         if (bp->max_resp_len != max_resp_len) {
 634                 sprintf(type, "bnxt_hwrm_%04x:%02x:%02x:%02x",
 635                         bp->pdev->addr.domain, bp->pdev->addr.bus,
 636                         bp->pdev->addr.devid, bp->pdev->addr.function);
 637
 638                 rte_free(bp->hwrm_cmd_resp_addr);
 639
 640                 bp->hwrm_cmd_resp_addr = rte_malloc(type, max_resp_len, 0);
 641                 if (bp->hwrm_cmd_resp_addr == NULL) {
 642                         rc = -ENOMEM;
 643                         goto error;
 644                 }
 645                 rte_mem_lock_page(bp->hwrm_cmd_resp_addr);
 646                 bp->hwrm_cmd_resp_dma_addr =
 647                         rte_mem_virt2iova(bp->hwrm_cmd_resp_addr);
 648                 if (bp->hwrm_cmd_resp_dma_addr == 0) {
 649                         RTE_LOG(ERR, PMD,
 650                         "Unable to map response buffer to physical memory.\n");
 651                         rc = -ENOMEM;
 652                         goto error;
 653                 }
 654                 bp->max_resp_len = max_resp_len;
 655         }
 656
 657         if ((dev_caps_cfg &
 658                 HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_SUPPORTED) &&
 659             (dev_caps_cfg &
 660              HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_INPUTUIRED)) {
 661                 RTE_LOG(DEBUG, PMD, "Short command supported\n");
 662
 663                 rte_free(bp->hwrm_short_cmd_req_addr);
 664
 665                 bp->hwrm_short_cmd_req_addr = rte_malloc(type,
 666                                                         bp->max_req_len, 0);
 667                 if (bp->hwrm_short_cmd_req_addr == NULL) {
 668                         rc = -ENOMEM;
 669                         goto error;
 670                 }
 671                 rte_mem_lock_page(bp->hwrm_short_cmd_req_addr);
 672                 bp->hwrm_short_cmd_req_dma_addr =
 673                         rte_mem_virt2iova(bp->hwrm_short_cmd_req_addr);
 674                 if (bp->hwrm_short_cmd_req_dma_addr == 0) {
 675                         rte_free(bp->hwrm_short_cmd_req_addr);
 676                         RTE_LOG(ERR, PMD,
 677                                 "Unable to map buffer to physical memory.\n");
 678                         rc = -ENOMEM;
 679                         goto error;
 680                 }
 681
 682                 bp->flags |= BNXT_FLAG_SHORT_CMD;
 683         }
 684
 685 error:
 686         HWRM_UNLOCK();
 687         return rc;
 688 }
 689
 690 int bnxt_hwrm_func_driver_unregister(struct bnxt *bp, uint32_t flags)
 691 {
 692         int rc;
 693         struct hwrm_func_drv_unrgtr_input req = {.req_type = 0 };
 694         struct hwrm_func_drv_unrgtr_output *resp = bp->hwrm_cmd_resp_addr;
 695
 696         if (!(bp->flags & BNXT_FLAG_REGISTERED))
 697                 return 0;
 698
 699         HWRM_PREP(req, FUNC_DRV_UNRGTR);
 700         req.flags = flags;
 701
 702         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
 703
 704         HWRM_CHECK_RESULT();
 705         HWRM_UNLOCK();
 706
 707         bp->flags &= ~BNXT_FLAG_REGISTERED;
 708
 709         return rc;
 710 }
 711
 712 static int bnxt_hwrm_port_phy_cfg(struct bnxt *bp, struct bnxt_link_info *conf)
 713 {
 714         int rc = 0;
 715         struct hwrm_port_phy_cfg_input req = {0};
 716         struct hwrm_port_phy_cfg_output *resp = bp->hwrm_cmd_resp_addr;
 717         uint32_t enables = 0;
 718         uint32_t link_speed_mask =
 719                 HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_LINK_SPEED_MASK;
 720
 721         HWRM_PREP(req, PORT_PHY_CFG);
 722
 723         if (conf->link_up) {
 724                 req.flags = rte_cpu_to_le_32(conf->phy_flags);
 725                 req.force_link_speed = rte_cpu_to_le_16(conf->link_speed);
 726                 /*
 727                  * Note, ChiMP FW 20.2.1 and 20.2.2 return an error when we set
 728                  * any auto mode, even "none".
 729                  */
 730                 if (!conf->link_speed) {
 731                         req.auto_mode = conf->auto_mode;
 732                         enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_MODE;
 733                         if (conf->auto_mode ==
 734                             HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_SPEED_MASK) {
 735                                 req.auto_link_speed_mask =
 736                                         conf->auto_link_speed_mask;
 737                                 enables |= link_speed_mask;
 738                         }
 739                         if (bp->link_info.auto_link_speed) {
 740                                 req.auto_link_speed =
 741                                         bp->link_info.auto_link_speed;
 742                                 enables |=
 743                                 HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_LINK_SPEED;
 744                         }
 745                 }
 746                 req.auto_duplex = conf->duplex;
 747                 enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_DUPLEX;
 748                 req.auto_pause = conf->auto_pause;
 749                 req.force_pause = conf->force_pause;
 750                 /* Set force_pause if there is no auto or if there is a force */
 751                 if (req.auto_pause && !req.force_pause)
 752                         enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_PAUSE;
 753                 else
 754                         enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_FORCE_PAUSE;
 755
 756                 req.enables = rte_cpu_to_le_32(enables);
 757         } else {
 758                 req.flags =
 759                 rte_cpu_to_le_32(HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE_LINK_DWN);
 760                 RTE_LOG(INFO, PMD, "Force Link Down\n");
 761         }
 762
 763         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
 764
 765         HWRM_CHECK_RESULT();
 766         HWRM_UNLOCK();
 767
 768         return rc;
 769 }
 770
 771 static int bnxt_hwrm_port_phy_qcfg(struct bnxt *bp,
 772                                    struct bnxt_link_info *link_info)
 773 {
 774         int rc = 0;
 775         struct hwrm_port_phy_qcfg_input req = {0};
 776         struct hwrm_port_phy_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
 777
 778         HWRM_PREP(req, PORT_PHY_QCFG);
 779
 780         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
 781
 782         HWRM_CHECK_RESULT();
 783
 784         link_info->phy_link_status = resp->link;
 785         link_info->link_up =
 786                 (link_info->phy_link_status ==
 787                  HWRM_PORT_PHY_QCFG_OUTPUT_LINK_LINK) ? 1 : 0;
 788         link_info->link_speed = rte_le_to_cpu_16(resp->link_speed);
 789         link_info->duplex = resp->duplex_cfg;
 790         link_info->pause = resp->pause;
 791         link_info->auto_pause = resp->auto_pause;
 792         link_info->force_pause = resp->force_pause;
 793         link_info->auto_mode = resp->auto_mode;
 794
 795         link_info->support_speeds = rte_le_to_cpu_16(resp->support_speeds);
 796         link_info->auto_link_speed = rte_le_to_cpu_16(resp->auto_link_speed);
 797         link_info->preemphasis = rte_le_to_cpu_32(resp->preemphasis);
 798         link_info->phy_ver[0] = resp->phy_maj;
 799         link_info->phy_ver[1] = resp->phy_min;
 800         link_info->phy_ver[2] = resp->phy_bld;
 801
 802         HWRM_UNLOCK();
 803
 804         return rc;
 805 }
 806
 807 int bnxt_hwrm_queue_qportcfg(struct bnxt *bp)
 808 {
 809         int rc = 0;
 810         struct hwrm_queue_qportcfg_input req = {.req_type = 0 };
 811         struct hwrm_queue_qportcfg_output *resp = bp->hwrm_cmd_resp_addr;
 812
 813         HWRM_PREP(req, QUEUE_QPORTCFG);
 814
 815         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
 816
 817         HWRM_CHECK_RESULT();
 818
 819 #define GET_QUEUE_INFO(x) \
 820         bp->cos_queue[x].id = resp->queue_id##x; \
 821         bp->cos_queue[x].profile = resp->queue_id##x##_service_profile
 822
 823         GET_QUEUE_INFO(0);
 824         GET_QUEUE_INFO(1);
 825         GET_QUEUE_INFO(2);
 826         GET_QUEUE_INFO(3);
 827         GET_QUEUE_INFO(4);
 828         GET_QUEUE_INFO(5);
 829         GET_QUEUE_INFO(6);
 830         GET_QUEUE_INFO(7);
 831
 832         HWRM_UNLOCK();
 833
 834         return rc;
 835 }
 836
 837 int bnxt_hwrm_ring_alloc(struct bnxt *bp,
 838                          struct bnxt_ring *ring,
 839                          uint32_t ring_type, uint32_t map_index,
 840                          uint32_t stats_ctx_id, uint32_t cmpl_ring_id)
 841 {
 842         int rc = 0;
 843         uint32_t enables = 0;
 844         struct hwrm_ring_alloc_input req = {.req_type = 0 };
 845         struct hwrm_ring_alloc_output *resp = bp->hwrm_cmd_resp_addr;
 846
 847         HWRM_PREP(req, RING_ALLOC);
 848
 849         req.page_tbl_addr = rte_cpu_to_le_64(ring->bd_dma);
 850         req.fbo = rte_cpu_to_le_32(0);
 851         /* Association of ring index with doorbell index */
 852         req.logical_id = rte_cpu_to_le_16(map_index);
 853         req.length = rte_cpu_to_le_32(ring->ring_size);
 854
 855         switch (ring_type) {
 856         case HWRM_RING_ALLOC_INPUT_RING_TYPE_TX:
 857                 req.queue_id = bp->cos_queue[0].id;
 858                 /* FALLTHROUGH */
 859         case HWRM_RING_ALLOC_INPUT_RING_TYPE_RX:
 860                 req.ring_type = ring_type;
 861                 req.cmpl_ring_id = rte_cpu_to_le_16(cmpl_ring_id);
 862                 req.stat_ctx_id = rte_cpu_to_le_16(stats_ctx_id);
 863                 if (stats_ctx_id != INVALID_STATS_CTX_ID)
 864                         enables |=
 865                         HWRM_RING_ALLOC_INPUT_ENABLES_STAT_CTX_ID_VALID;
 866                 break;
 867         case HWRM_RING_ALLOC_INPUT_RING_TYPE_L2_CMPL:
 868                 req.ring_type = ring_type;
 869                 /*
 870                  * TODO: Some HWRM versions crash with
 871                  * HWRM_RING_ALLOC_INPUT_INT_MODE_POLL
 872                  */
 873                 req.int_mode = HWRM_RING_ALLOC_INPUT_INT_MODE_MSIX;
 874                 break;
 875         default:
 876                 RTE_LOG(ERR, PMD, "hwrm alloc invalid ring type %d\n",
 877                         ring_type);
 878                 HWRM_UNLOCK();
 879                 return -1;
 880         }
 881         req.enables = rte_cpu_to_le_32(enables);
 882
 883         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
 884
 885         if (rc || resp->error_code) {
 886                 if (rc == 0 && resp->error_code)
 887                         rc = rte_le_to_cpu_16(resp->error_code);
 888                 switch (ring_type) {
 889                 case HWRM_RING_FREE_INPUT_RING_TYPE_L2_CMPL:
 890                         RTE_LOG(ERR, PMD,
 891                                 "hwrm_ring_alloc cp failed. rc:%d\n", rc);
 892                         HWRM_UNLOCK();
 893                         return rc;
 894                 case HWRM_RING_FREE_INPUT_RING_TYPE_RX:
 895                         RTE_LOG(ERR, PMD,
 896                                 "hwrm_ring_alloc rx failed. rc:%d\n", rc);
 897                         HWRM_UNLOCK();
 898                         return rc;
 899                 case HWRM_RING_FREE_INPUT_RING_TYPE_TX:
 900                         RTE_LOG(ERR, PMD,
 901                                 "hwrm_ring_alloc tx failed. rc:%d\n", rc);
 902                         HWRM_UNLOCK();
 903                         return rc;
 904                 default:
 905                         RTE_LOG(ERR, PMD, "Invalid ring. rc:%d\n", rc);
 906                         HWRM_UNLOCK();
 907                         return rc;
 908                 }
 909         }
 910
 911         ring->fw_ring_id = rte_le_to_cpu_16(resp->ring_id);
 912         HWRM_UNLOCK();
 913         return rc;
 914 }
 915
 916 int bnxt_hwrm_ring_free(struct bnxt *bp,
 917                         struct bnxt_ring *ring, uint32_t ring_type)
 918 {
 919         int rc;
 920         struct hwrm_ring_free_input req = {.req_type = 0 };
 921         struct hwrm_ring_free_output *resp = bp->hwrm_cmd_resp_addr;
 922
 923         HWRM_PREP(req, RING_FREE);
 924
 925         req.ring_type = ring_type;
 926         req.ring_id = rte_cpu_to_le_16(ring->fw_ring_id);
 927
 928         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
 929
 930         if (rc || resp->error_code) {
 931                 if (rc == 0 && resp->error_code)
 932                         rc = rte_le_to_cpu_16(resp->error_code);
 933                 HWRM_UNLOCK();
 934
 935                 switch (ring_type) {
 936                 case HWRM_RING_FREE_INPUT_RING_TYPE_L2_CMPL:
 937                         RTE_LOG(ERR, PMD, "hwrm_ring_free cp failed. rc:%d\n",
 938                                 rc);
 939                         return rc;
 940                 case HWRM_RING_FREE_INPUT_RING_TYPE_RX:
 941                         RTE_LOG(ERR, PMD, "hwrm_ring_free rx failed. rc:%d\n",
 942                                 rc);
 943                         return rc;
 944                 case HWRM_RING_FREE_INPUT_RING_TYPE_TX:
 945                         RTE_LOG(ERR, PMD, "hwrm_ring_free tx failed. rc:%d\n",
 946                                 rc);
 947                         return rc;
 948                 default:
 949                         RTE_LOG(ERR, PMD, "Invalid ring, rc:%d\n", rc);
 950                         return rc;
 951                 }
 952         }
 953         HWRM_UNLOCK();
 954         return 0;
 955 }
 956
 957 int bnxt_hwrm_ring_grp_alloc(struct bnxt *bp, unsigned int idx)
 958 {
 959         int rc = 0;
 960         struct hwrm_ring_grp_alloc_input req = {.req_type = 0 };
 961         struct hwrm_ring_grp_alloc_output *resp = bp->hwrm_cmd_resp_addr;
 962
 963         HWRM_PREP(req, RING_GRP_ALLOC);
 964
 965         req.cr = rte_cpu_to_le_16(bp->grp_info[idx].cp_fw_ring_id);
 966         req.rr = rte_cpu_to_le_16(bp->grp_info[idx].rx_fw_ring_id);
 967         req.ar = rte_cpu_to_le_16(bp->grp_info[idx].ag_fw_ring_id);
 968         req.sc = rte_cpu_to_le_16(bp->grp_info[idx].fw_stats_ctx);
 969
 970         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
 971
 972         HWRM_CHECK_RESULT();
 973
 974         bp->grp_info[idx].fw_grp_id =
 975             rte_le_to_cpu_16(resp->ring_group_id);
 976
 977         HWRM_UNLOCK();
 978
 979         return rc;
 980 }
 981
 982 int bnxt_hwrm_ring_grp_free(struct bnxt *bp, unsigned int idx)
 983 {
 984         int rc;
 985         struct hwrm_ring_grp_free_input req = {.req_type = 0 };
 986         struct hwrm_ring_grp_free_output *resp = bp->hwrm_cmd_resp_addr;
 987
 988         HWRM_PREP(req, RING_GRP_FREE);
 989
 990         req.ring_group_id = rte_cpu_to_le_16(bp->grp_info[idx].fw_grp_id);
 991
 992         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
 993
 994         HWRM_CHECK_RESULT();
 995         HWRM_UNLOCK();
 996
 997         bp->grp_info[idx].fw_grp_id = INVALID_HW_RING_ID;
 998         return rc;
 999 }
1000
1001 int bnxt_hwrm_stat_clear(struct bnxt *bp, struct bnxt_cp_ring_info *cpr)
1002 {
1003         int rc = 0;
1004         struct hwrm_stat_ctx_clr_stats_input req = {.req_type = 0 };
1005         struct hwrm_stat_ctx_clr_stats_output *resp = bp->hwrm_cmd_resp_addr;
1006
1007         if (cpr->hw_stats_ctx_id == (uint32_t)HWRM_NA_SIGNATURE)
1008                 return rc;
1009
1010         HWRM_PREP(req, STAT_CTX_CLR_STATS);
1011
1012         req.stat_ctx_id = rte_cpu_to_le_16(cpr->hw_stats_ctx_id);
1013
1014         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
1015
1016         HWRM_CHECK_RESULT();
1017         HWRM_UNLOCK();
1018
1019         return rc;
1020 }
1021
1022 int bnxt_hwrm_stat_ctx_alloc(struct bnxt *bp, struct bnxt_cp_ring_info *cpr,
1023                                 unsigned int idx __rte_unused)
1024 {
1025         int rc;
1026         struct hwrm_stat_ctx_alloc_input req = {.req_type = 0 };
1027         struct hwrm_stat_ctx_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1028
1029         HWRM_PREP(req, STAT_CTX_ALLOC);
1030
1031         req.update_period_ms = rte_cpu_to_le_32(0);
1032
1033         req.stats_dma_addr =
1034             rte_cpu_to_le_64(cpr->hw_stats_map);
1035
1036         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
1037
1038         HWRM_CHECK_RESULT();
1039
1040         cpr->hw_stats_ctx_id = rte_le_to_cpu_16(resp->stat_ctx_id);
1041
1042         HWRM_UNLOCK();
1043         bp->grp_info[idx].fw_stats_ctx = cpr->hw_stats_ctx_id;
1044
1045         return rc;
1046 }
1047
1048 int bnxt_hwrm_stat_ctx_free(struct bnxt *bp, struct bnxt_cp_ring_info *cpr,
1049                                 unsigned int idx __rte_unused)
1050 {
1051         int rc;
1052         struct hwrm_stat_ctx_free_input req = {.req_type = 0 };
1053         struct hwrm_stat_ctx_free_output *resp = bp->hwrm_cmd_resp_addr;
1054
1055         HWRM_PREP(req, STAT_CTX_FREE);
1056
1057         req.stat_ctx_id = rte_cpu_to_le_16(cpr->hw_stats_ctx_id);
1058
1059         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
1060
1061         HWRM_CHECK_RESULT();
1062         HWRM_UNLOCK();
1063
1064         return rc;
1065 }
1066
1067 int bnxt_hwrm_vnic_alloc(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1068 {
1069         int rc = 0, i, j;
1070         struct hwrm_vnic_alloc_input req = { 0 };
1071         struct hwrm_vnic_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1072
1073         /* map ring groups to this vnic */
1074         RTE_LOG(DEBUG, PMD, "Alloc VNIC. Start %x, End %x\n",
1075                 vnic->start_grp_id, vnic->end_grp_id);
1076         for (i = vnic->start_grp_id, j = 0; i <= vnic->end_grp_id; i++, j++)
1077                 vnic->fw_grp_ids[j] = bp->grp_info[i].fw_grp_id;
1078         vnic->dflt_ring_grp = bp->grp_info[vnic->start_grp_id].fw_grp_id;
1079         vnic->rss_rule = (uint16_t)HWRM_NA_SIGNATURE;
1080         vnic->cos_rule = (uint16_t)HWRM_NA_SIGNATURE;
1081         vnic->lb_rule = (uint16_t)HWRM_NA_SIGNATURE;
1082         vnic->mru = bp->eth_dev->data->mtu + ETHER_HDR_LEN +
1083                                 ETHER_CRC_LEN + VLAN_TAG_SIZE;
1084         HWRM_PREP(req, VNIC_ALLOC);
1085
1086         if (vnic->func_default)
1087                 req.flags = HWRM_VNIC_ALLOC_INPUT_FLAGS_DEFAULT;
1088         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
1089
1090         HWRM_CHECK_RESULT();
1091
1092         vnic->fw_vnic_id = rte_le_to_cpu_16(resp->vnic_id);
1093         HWRM_UNLOCK();
1094         RTE_LOG(DEBUG, PMD, "VNIC ID %x\n", vnic->fw_vnic_id);
1095         return rc;
1096 }
1097
1098 static int bnxt_hwrm_vnic_plcmodes_qcfg(struct bnxt *bp,
1099                                         struct bnxt_vnic_info *vnic,
1100                                         struct bnxt_plcmodes_cfg *pmode)
1101 {
1102         int rc = 0;
1103         struct hwrm_vnic_plcmodes_qcfg_input req = {.req_type = 0 };
1104         struct hwrm_vnic_plcmodes_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
1105
1106         HWRM_PREP(req, VNIC_PLCMODES_QCFG);
1107
1108         req.vnic_id = rte_cpu_to_le_32(vnic->fw_vnic_id);
1109
1110         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
1111
1112         HWRM_CHECK_RESULT();
1113
1114         pmode->flags = rte_le_to_cpu_32(resp->flags);
1115         /* dflt_vnic bit doesn't exist in the _cfg command */
1116         pmode->flags &= ~(HWRM_VNIC_PLCMODES_QCFG_OUTPUT_FLAGS_DFLT_VNIC);
1117         pmode->jumbo_thresh = rte_le_to_cpu_16(resp->jumbo_thresh);
1118         pmode->hds_offset = rte_le_to_cpu_16(resp->hds_offset);
1119         pmode->hds_threshold = rte_le_to_cpu_16(resp->hds_threshold);
1120
1121         HWRM_UNLOCK();
1122
1123         return rc;
1124 }
1125
1126 static int bnxt_hwrm_vnic_plcmodes_cfg(struct bnxt *bp,
1127                                        struct bnxt_vnic_info *vnic,
1128                                        struct bnxt_plcmodes_cfg *pmode)
1129 {
1130         int rc = 0;
1131         struct hwrm_vnic_plcmodes_cfg_input req = {.req_type = 0 };
1132         struct hwrm_vnic_plcmodes_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1133
1134         HWRM_PREP(req, VNIC_PLCMODES_CFG);
1135
1136         req.vnic_id = rte_cpu_to_le_32(vnic->fw_vnic_id);
1137         req.flags = rte_cpu_to_le_32(pmode->flags);
1138         req.jumbo_thresh = rte_cpu_to_le_16(pmode->jumbo_thresh);
1139         req.hds_offset = rte_cpu_to_le_16(pmode->hds_offset);
1140         req.hds_threshold = rte_cpu_to_le_16(pmode->hds_threshold);
1141         req.enables = rte_cpu_to_le_32(
1142             HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_HDS_THRESHOLD_VALID |
1143             HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_HDS_OFFSET_VALID |
1144             HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_JUMBO_THRESH_VALID
1145         );
1146
1147         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
1148
1149         HWRM_CHECK_RESULT();
1150         HWRM_UNLOCK();
1151
1152         return rc;
1153 }
1154
1155 int bnxt_hwrm_vnic_cfg(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1156 {
1157         int rc = 0;
1158         struct hwrm_vnic_cfg_input req = {.req_type = 0 };
1159         struct hwrm_vnic_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1160         uint32_t ctx_enable_flag = 0;
1161         struct bnxt_plcmodes_cfg pmodes;
1162
1163         if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
1164                 RTE_LOG(DEBUG, PMD, "VNIC ID %x\n", vnic->fw_vnic_id);
1165                 return rc;
1166         }
1167
1168         rc = bnxt_hwrm_vnic_plcmodes_qcfg(bp, vnic, &pmodes);
1169         if (rc)
1170                 return rc;
1171
1172         HWRM_PREP(req, VNIC_CFG);
1173
1174         /* Only RSS support for now TBD: COS & LB */
1175         req.enables =
1176             rte_cpu_to_le_32(HWRM_VNIC_CFG_INPUT_ENABLES_DFLT_RING_GRP);
1177         if (vnic->lb_rule != 0xffff)
1178                 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_LB_RULE;
1179         if (vnic->cos_rule != 0xffff)
1180                 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_COS_RULE;
1181         if (vnic->rss_rule != 0xffff) {
1182                 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_MRU;
1183                 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_RSS_RULE;
1184         }
1185         req.enables |= rte_cpu_to_le_32(ctx_enable_flag);
1186         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1187         req.dflt_ring_grp = rte_cpu_to_le_16(vnic->dflt_ring_grp);
1188         req.rss_rule = rte_cpu_to_le_16(vnic->rss_rule);
1189         req.cos_rule = rte_cpu_to_le_16(vnic->cos_rule);
1190         req.lb_rule = rte_cpu_to_le_16(vnic->lb_rule);
1191         req.mru = rte_cpu_to_le_16(vnic->mru);
1192         if (vnic->func_default)
1193                 req.flags |=
1194                     rte_cpu_to_le_32(HWRM_VNIC_CFG_INPUT_FLAGS_DEFAULT);
1195         if (vnic->vlan_strip)
1196                 req.flags |=
1197                     rte_cpu_to_le_32(HWRM_VNIC_CFG_INPUT_FLAGS_VLAN_STRIP_MODE);
1198         if (vnic->bd_stall)
1199                 req.flags |=
1200                     rte_cpu_to_le_32(HWRM_VNIC_CFG_INPUT_FLAGS_BD_STALL_MODE);
1201         if (vnic->roce_dual)
1202                 req.flags |= rte_cpu_to_le_32(
1203                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_DUAL_VNIC_MODE);
1204         if (vnic->roce_only)
1205                 req.flags |= rte_cpu_to_le_32(
1206                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_ONLY_VNIC_MODE);
1207         if (vnic->rss_dflt_cr)
1208                 req.flags |= rte_cpu_to_le_32(
1209                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_RSS_DFLT_CR_MODE);
1210
1211         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
1212
1213         HWRM_CHECK_RESULT();
1214         HWRM_UNLOCK();
1215
1216         rc = bnxt_hwrm_vnic_plcmodes_cfg(bp, vnic, &pmodes);
1217
1218         return rc;
1219 }
1220
1221 int bnxt_hwrm_vnic_qcfg(struct bnxt *bp, struct bnxt_vnic_info *vnic,
1222                 int16_t fw_vf_id)
1223 {
1224         int rc = 0;
1225         struct hwrm_vnic_qcfg_input req = {.req_type = 0 };
1226         struct hwrm_vnic_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
1227
1228         if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
1229                 RTE_LOG(DEBUG, PMD, "VNIC QCFG ID %d\n", vnic->fw_vnic_id);
1230                 return rc;
1231         }
1232         HWRM_PREP(req, VNIC_QCFG);
1233
1234         req.enables =
1235                 rte_cpu_to_le_32(HWRM_VNIC_QCFG_INPUT_ENABLES_VF_ID_VALID);
1236         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1237         req.vf_id = rte_cpu_to_le_16(fw_vf_id);
1238
1239         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
1240
1241         HWRM_CHECK_RESULT();
1242
1243         vnic->dflt_ring_grp = rte_le_to_cpu_16(resp->dflt_ring_grp);
1244         vnic->rss_rule = rte_le_to_cpu_16(resp->rss_rule);
1245         vnic->cos_rule = rte_le_to_cpu_16(resp->cos_rule);
1246         vnic->lb_rule = rte_le_to_cpu_16(resp->lb_rule);
1247         vnic->mru = rte_le_to_cpu_16(resp->mru);
1248         vnic->func_default = rte_le_to_cpu_32(
1249                         resp->flags) & HWRM_VNIC_QCFG_OUTPUT_FLAGS_DEFAULT;
1250         vnic->vlan_strip = rte_le_to_cpu_32(resp->flags) &
1251                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_VLAN_STRIP_MODE;
1252         vnic->bd_stall = rte_le_to_cpu_32(resp->flags) &
1253                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_BD_STALL_MODE;
1254         vnic->roce_dual = rte_le_to_cpu_32(resp->flags) &
1255                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_DUAL_VNIC_MODE;
1256         vnic->roce_only = rte_le_to_cpu_32(resp->flags) &
1257                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_ONLY_VNIC_MODE;
1258         vnic->rss_dflt_cr = rte_le_to_cpu_32(resp->flags) &
1259                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_RSS_DFLT_CR_MODE;
1260
1261         HWRM_UNLOCK();
1262
1263         return rc;
1264 }
1265
1266 int bnxt_hwrm_vnic_ctx_alloc(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1267 {
1268         int rc = 0;
1269         struct hwrm_vnic_rss_cos_lb_ctx_alloc_input req = {.req_type = 0 };
1270         struct hwrm_vnic_rss_cos_lb_ctx_alloc_output *resp =
1271                                                 bp->hwrm_cmd_resp_addr;
1272
1273         HWRM_PREP(req, VNIC_RSS_COS_LB_CTX_ALLOC);
1274
1275         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
1276
1277         HWRM_CHECK_RESULT();
1278
1279         vnic->rss_rule = rte_le_to_cpu_16(resp->rss_cos_lb_ctx_id);
1280         HWRM_UNLOCK();
1281         RTE_LOG(DEBUG, PMD, "VNIC RSS Rule %x\n", vnic->rss_rule);
1282
1283         return rc;
1284 }
1285
1286 int bnxt_hwrm_vnic_ctx_free(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1287 {
1288         int rc = 0;
1289         struct hwrm_vnic_rss_cos_lb_ctx_free_input req = {.req_type = 0 };
1290         struct hwrm_vnic_rss_cos_lb_ctx_free_output *resp =
1291                                                 bp->hwrm_cmd_resp_addr;
1292
1293         if (vnic->rss_rule == 0xffff) {
1294                 RTE_LOG(DEBUG, PMD, "VNIC RSS Rule %x\n", vnic->rss_rule);
1295                 return rc;
1296         }
1297         HWRM_PREP(req, VNIC_RSS_COS_LB_CTX_FREE);
1298
1299         req.rss_cos_lb_ctx_id = rte_cpu_to_le_16(vnic->rss_rule);
1300
1301         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
1302
1303         HWRM_CHECK_RESULT();
1304         HWRM_UNLOCK();
1305
1306         vnic->rss_rule = INVALID_HW_RING_ID;
1307
1308         return rc;
1309 }
1310
1311 int bnxt_hwrm_vnic_free(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1312 {
1313         int rc = 0;
1314         struct hwrm_vnic_free_input req = {.req_type = 0 };
1315         struct hwrm_vnic_free_output *resp = bp->hwrm_cmd_resp_addr;
1316
1317         if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
1318                 RTE_LOG(DEBUG, PMD, "VNIC FREE ID %x\n", vnic->fw_vnic_id);
1319                 return rc;
1320         }
1321
1322         HWRM_PREP(req, VNIC_FREE);
1323
1324         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1325
1326         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
1327
1328         HWRM_CHECK_RESULT();
1329         HWRM_UNLOCK();
1330
1331         vnic->fw_vnic_id = INVALID_HW_RING_ID;
1332         return rc;
1333 }
1334
1335 int bnxt_hwrm_vnic_rss_cfg(struct bnxt *bp,
1336                            struct bnxt_vnic_info *vnic)
1337 {
1338         int rc = 0;
1339         struct hwrm_vnic_rss_cfg_input req = {.req_type = 0 };
1340         struct hwrm_vnic_rss_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1341
1342         HWRM_PREP(req, VNIC_RSS_CFG);
1343
1344         req.hash_type = rte_cpu_to_le_32(vnic->hash_type);
1345
1346         req.ring_grp_tbl_addr =
1347             rte_cpu_to_le_64(vnic->rss_table_dma_addr);
1348         req.hash_key_tbl_addr =
1349             rte_cpu_to_le_64(vnic->rss_hash_key_dma_addr);
1350         req.rss_ctx_idx = rte_cpu_to_le_16(vnic->rss_rule);
1351
1352         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
1353
1354         HWRM_CHECK_RESULT();
1355         HWRM_UNLOCK();
1356
1357         return rc;
1358 }
1359
1360 int bnxt_hwrm_vnic_plcmode_cfg(struct bnxt *bp,
1361                         struct bnxt_vnic_info *vnic)
1362 {
1363         int rc = 0;
1364         struct hwrm_vnic_plcmodes_cfg_input req = {.req_type = 0 };
1365         struct hwrm_vnic_plcmodes_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1366         uint16_t size;
1367
1368         HWRM_PREP(req, VNIC_PLCMODES_CFG);
1369
1370         req.flags = rte_cpu_to_le_32(
1371                         HWRM_VNIC_PLCMODES_CFG_INPUT_FLAGS_JUMBO_PLACEMENT);
1372
1373         req.enables = rte_cpu_to_le_32(
1374                 HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_JUMBO_THRESH_VALID);
1375
1376         size = rte_pktmbuf_data_room_size(bp->rx_queues[0]->mb_pool);
1377         size -= RTE_PKTMBUF_HEADROOM;
1378
1379         req.jumbo_thresh = rte_cpu_to_le_16(size);
1380         req.vnic_id = rte_cpu_to_le_32(vnic->fw_vnic_id);
1381
1382         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
1383
1384         HWRM_CHECK_RESULT();
1385         HWRM_UNLOCK();
1386
1387         return rc;
1388 }
1389
1390 int bnxt_hwrm_vnic_tpa_cfg(struct bnxt *bp,
1391                         struct bnxt_vnic_info *vnic, bool enable)
1392 {
1393         int rc = 0;
1394         struct hwrm_vnic_tpa_cfg_input req = {.req_type = 0 };
1395         struct hwrm_vnic_tpa_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1396
1397         HWRM_PREP(req, VNIC_TPA_CFG);
1398
1399         if (enable) {
1400                 req.enables = rte_cpu_to_le_32(
1401                                 HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MAX_AGG_SEGS |
1402                                 HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MAX_AGGS |
1403                                 HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MIN_AGG_LEN);
1404                 req.flags = rte_cpu_to_le_32(
1405                                 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_TPA |
1406                                 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_ENCAP_TPA |
1407                                 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_RSC_WND_UPDATE |
1408                                 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_GRO |
1409                                 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_AGG_WITH_ECN |
1410                         HWRM_VNIC_TPA_CFG_INPUT_FLAGS_AGG_WITH_SAME_GRE_SEQ);
1411                 req.vnic_id = rte_cpu_to_le_32(vnic->fw_vnic_id);
1412                 req.max_agg_segs = rte_cpu_to_le_16(5);
1413                 req.max_aggs =
1414                         rte_cpu_to_le_16(HWRM_VNIC_TPA_CFG_INPUT_MAX_AGGS_MAX);
1415                 req.min_agg_len = rte_cpu_to_le_32(512);
1416         }
1417
1418         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
1419
1420         HWRM_CHECK_RESULT();
1421         HWRM_UNLOCK();
1422
1423         return rc;
1424 }
1425
1426 int bnxt_hwrm_func_vf_mac(struct bnxt *bp, uint16_t vf, const uint8_t *mac_addr)
1427 {
1428         struct hwrm_func_cfg_input req = {0};
1429         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1430         int rc;
1431
1432         req.flags = rte_cpu_to_le_32(bp->pf.vf_info[vf].func_cfg_flags);
1433         req.enables = rte_cpu_to_le_32(
1434                         HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
1435         memcpy(req.dflt_mac_addr, mac_addr, sizeof(req.dflt_mac_addr));
1436         req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
1437
1438         HWRM_PREP(req, FUNC_CFG);
1439
1440         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
1441         HWRM_CHECK_RESULT();
1442         HWRM_UNLOCK();
1443
1444         bp->pf.vf_info[vf].random_mac = false;
1445
1446         return rc;
1447 }
1448
1449 int bnxt_hwrm_func_qstats_tx_drop(struct bnxt *bp, uint16_t fid,
1450                                   uint64_t *dropped)
1451 {
1452         int rc = 0;
1453         struct hwrm_func_qstats_input req = {.req_type = 0};
1454         struct hwrm_func_qstats_output *resp = bp->hwrm_cmd_resp_addr;
1455
1456         HWRM_PREP(req, FUNC_QSTATS);
1457
1458         req.fid = rte_cpu_to_le_16(fid);
1459
1460         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
1461
1462         HWRM_CHECK_RESULT();
1463
1464         if (dropped)
1465                 *dropped = rte_le_to_cpu_64(resp->tx_drop_pkts);
1466
1467         HWRM_UNLOCK();
1468
1469         return rc;
1470 }
1471
1472 int bnxt_hwrm_func_qstats(struct bnxt *bp, uint16_t fid,
1473                           struct rte_eth_stats *stats)
1474 {
1475         int rc = 0;
1476         struct hwrm_func_qstats_input req = {.req_type = 0};
1477         struct hwrm_func_qstats_output *resp = bp->hwrm_cmd_resp_addr;
1478
1479         HWRM_PREP(req, FUNC_QSTATS);
1480
1481         req.fid = rte_cpu_to_le_16(fid);
1482
1483         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
1484
1485         HWRM_CHECK_RESULT();
1486
1487         stats->ipackets = rte_le_to_cpu_64(resp->rx_ucast_pkts);
1488         stats->ipackets += rte_le_to_cpu_64(resp->rx_mcast_pkts);
1489         stats->ipackets += rte_le_to_cpu_64(resp->rx_bcast_pkts);
1490         stats->ibytes = rte_le_to_cpu_64(resp->rx_ucast_bytes);
1491         stats->ibytes += rte_le_to_cpu_64(resp->rx_mcast_bytes);
1492         stats->ibytes += rte_le_to_cpu_64(resp->rx_bcast_bytes);
1493
1494         stats->opackets = rte_le_to_cpu_64(resp->tx_ucast_pkts);
1495         stats->opackets += rte_le_to_cpu_64(resp->tx_mcast_pkts);
1496         stats->opackets += rte_le_to_cpu_64(resp->tx_bcast_pkts);
1497         stats->obytes = rte_le_to_cpu_64(resp->tx_ucast_bytes);
1498         stats->obytes += rte_le_to_cpu_64(resp->tx_mcast_bytes);
1499         stats->obytes += rte_le_to_cpu_64(resp->tx_bcast_bytes);
1500
1501         stats->ierrors = rte_le_to_cpu_64(resp->rx_err_pkts);
1502         stats->oerrors = rte_le_to_cpu_64(resp->tx_err_pkts);
1503
1504         stats->imissed = rte_le_to_cpu_64(resp->rx_drop_pkts);
1505
1506         HWRM_UNLOCK();
1507
1508         return rc;
1509 }
1510
1511 int bnxt_hwrm_func_clr_stats(struct bnxt *bp, uint16_t fid)
1512 {
1513         int rc = 0;
1514         struct hwrm_func_clr_stats_input req = {.req_type = 0};
1515         struct hwrm_func_clr_stats_output *resp = bp->hwrm_cmd_resp_addr;
1516
1517         HWRM_PREP(req, FUNC_CLR_STATS);
1518
1519         req.fid = rte_cpu_to_le_16(fid);
1520
1521         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
1522
1523         HWRM_CHECK_RESULT();
1524         HWRM_UNLOCK();
1525
1526         return rc;
1527 }
1528
1529 /*
1530  * HWRM utility functions
1531  */
1532
1533 int bnxt_clear_all_hwrm_stat_ctxs(struct bnxt *bp)
1534 {
1535         unsigned int i;
1536         int rc = 0;
1537
1538         for (i = 0; i < bp->rx_cp_nr_rings + bp->tx_cp_nr_rings; i++) {
1539                 struct bnxt_tx_queue *txq;
1540                 struct bnxt_rx_queue *rxq;
1541                 struct bnxt_cp_ring_info *cpr;
1542
1543                 if (i >= bp->rx_cp_nr_rings) {
1544                         txq = bp->tx_queues[i - bp->rx_cp_nr_rings];
1545                         cpr = txq->cp_ring;
1546                 } else {
1547                         rxq = bp->rx_queues[i];
1548                         cpr = rxq->cp_ring;
1549                 }
1550
1551                 rc = bnxt_hwrm_stat_clear(bp, cpr);
1552                 if (rc)
1553                         return rc;
1554         }
1555         return 0;
1556 }
1557
1558 int bnxt_free_all_hwrm_stat_ctxs(struct bnxt *bp)
1559 {
1560         int rc;
1561         unsigned int i;
1562         struct bnxt_cp_ring_info *cpr;
1563
1564         for (i = 0; i < bp->rx_cp_nr_rings + bp->tx_cp_nr_rings; i++) {
1565
1566                 if (i >= bp->rx_cp_nr_rings)
1567                         cpr = bp->tx_queues[i - bp->rx_cp_nr_rings]->cp_ring;
1568                 else
1569                         cpr = bp->rx_queues[i]->cp_ring;
1570                 if (cpr->hw_stats_ctx_id != HWRM_NA_SIGNATURE) {
1571                         rc = bnxt_hwrm_stat_ctx_free(bp, cpr, i);
1572                         cpr->hw_stats_ctx_id = HWRM_NA_SIGNATURE;
1573                         /*
1574                          * TODO. Need a better way to reset grp_info.stats_ctx
1575                          * for Rx rings only. stats_ctx is not saved for Tx
1576                          * in grp_info.
1577                          */
1578                         bp->grp_info[i].fw_stats_ctx = cpr->hw_stats_ctx_id;
1579                         if (rc)
1580                                 return rc;
1581                 }
1582         }
1583         return 0;
1584 }
1585
1586 int bnxt_alloc_all_hwrm_stat_ctxs(struct bnxt *bp)
1587 {
1588         unsigned int i;
1589         int rc = 0;
1590
1591         for (i = 0; i < bp->rx_cp_nr_rings + bp->tx_cp_nr_rings; i++) {
1592                 struct bnxt_tx_queue *txq;
1593                 struct bnxt_rx_queue *rxq;
1594                 struct bnxt_cp_ring_info *cpr;
1595
1596                 if (i >= bp->rx_cp_nr_rings) {
1597                         txq = bp->tx_queues[i - bp->rx_cp_nr_rings];
1598                         cpr = txq->cp_ring;
1599                 } else {
1600                         rxq = bp->rx_queues[i];
1601                         cpr = rxq->cp_ring;
1602                 }
1603
1604                 rc = bnxt_hwrm_stat_ctx_alloc(bp, cpr, i);
1605
1606                 if (rc)
1607                         return rc;
1608         }
1609         return rc;
1610 }
1611
1612 int bnxt_free_all_hwrm_ring_grps(struct bnxt *bp)
1613 {
1614         uint16_t idx;
1615         uint32_t rc = 0;
1616
1617         for (idx = 0; idx < bp->rx_cp_nr_rings; idx++) {
1618
1619                 if (bp->grp_info[idx].fw_grp_id == INVALID_HW_RING_ID)
1620                         continue;
1621
1622                 rc = bnxt_hwrm_ring_grp_free(bp, idx);
1623
1624                 if (rc)
1625                         return rc;
1626         }
1627         return rc;
1628 }
1629
1630 static void bnxt_free_cp_ring(struct bnxt *bp, struct bnxt_cp_ring_info *cpr,
1631                                 unsigned int idx __rte_unused)
1632 {
1633         struct bnxt_ring *cp_ring = cpr->cp_ring_struct;
1634
1635         bnxt_hwrm_ring_free(bp, cp_ring,
1636                         HWRM_RING_FREE_INPUT_RING_TYPE_L2_CMPL);
1637         cp_ring->fw_ring_id = INVALID_HW_RING_ID;
1638         bp->grp_info[idx].cp_fw_ring_id = INVALID_HW_RING_ID;
1639         memset(cpr->cp_desc_ring, 0, cpr->cp_ring_struct->ring_size *
1640                         sizeof(*cpr->cp_desc_ring));
1641         cpr->cp_raw_cons = 0;
1642 }
1643
1644 int bnxt_free_all_hwrm_rings(struct bnxt *bp)
1645 {
1646         unsigned int i;
1647         int rc = 0;
1648
1649         for (i = 0; i < bp->tx_cp_nr_rings; i++) {
1650                 struct bnxt_tx_queue *txq = bp->tx_queues[i];
1651                 struct bnxt_tx_ring_info *txr = txq->tx_ring;
1652                 struct bnxt_ring *ring = txr->tx_ring_struct;
1653                 struct bnxt_cp_ring_info *cpr = txq->cp_ring;
1654                 unsigned int idx = bp->rx_cp_nr_rings + i + 1;
1655
1656                 if (ring->fw_ring_id != INVALID_HW_RING_ID) {
1657                         bnxt_hwrm_ring_free(bp, ring,
1658                                         HWRM_RING_FREE_INPUT_RING_TYPE_TX);
1659                         ring->fw_ring_id = INVALID_HW_RING_ID;
1660                         memset(txr->tx_desc_ring, 0,
1661                                         txr->tx_ring_struct->ring_size *
1662                                         sizeof(*txr->tx_desc_ring));
1663                         memset(txr->tx_buf_ring, 0,
1664                                         txr->tx_ring_struct->ring_size *
1665                                         sizeof(*txr->tx_buf_ring));
1666                         txr->tx_prod = 0;
1667                         txr->tx_cons = 0;
1668                 }
1669                 if (cpr->cp_ring_struct->fw_ring_id != INVALID_HW_RING_ID) {
1670                         bnxt_free_cp_ring(bp, cpr, idx);
1671                         cpr->cp_ring_struct->fw_ring_id = INVALID_HW_RING_ID;
1672                 }
1673         }
1674
1675         for (i = 0; i < bp->rx_cp_nr_rings; i++) {
1676                 struct bnxt_rx_queue *rxq = bp->rx_queues[i];
1677                 struct bnxt_rx_ring_info *rxr = rxq->rx_ring;
1678                 struct bnxt_ring *ring = rxr->rx_ring_struct;
1679                 struct bnxt_cp_ring_info *cpr = rxq->cp_ring;
1680                 unsigned int idx = i + 1;
1681
1682                 if (ring->fw_ring_id != INVALID_HW_RING_ID) {
1683                         bnxt_hwrm_ring_free(bp, ring,
1684                                         HWRM_RING_FREE_INPUT_RING_TYPE_RX);
1685                         ring->fw_ring_id = INVALID_HW_RING_ID;
1686                         bp->grp_info[idx].rx_fw_ring_id = INVALID_HW_RING_ID;
1687                         memset(rxr->rx_desc_ring, 0,
1688                                         rxr->rx_ring_struct->ring_size *
1689                                         sizeof(*rxr->rx_desc_ring));
1690                         memset(rxr->rx_buf_ring, 0,
1691                                         rxr->rx_ring_struct->ring_size *
1692                                         sizeof(*rxr->rx_buf_ring));
1693                         rxr->rx_prod = 0;
1694                         memset(rxr->ag_buf_ring, 0,
1695                                         rxr->ag_ring_struct->ring_size *
1696                                         sizeof(*rxr->ag_buf_ring));
1697                         rxr->ag_prod = 0;
1698                 }
1699                 if (cpr->cp_ring_struct->fw_ring_id != INVALID_HW_RING_ID) {
1700                         bnxt_free_cp_ring(bp, cpr, idx);
1701                         bp->grp_info[i].cp_fw_ring_id = INVALID_HW_RING_ID;
1702                         cpr->cp_ring_struct->fw_ring_id = INVALID_HW_RING_ID;
1703                 }
1704         }
1705
1706         /* Default completion ring */
1707         {
1708                 struct bnxt_cp_ring_info *cpr = bp->def_cp_ring;
1709
1710                 if (cpr->cp_ring_struct->fw_ring_id != INVALID_HW_RING_ID) {
1711                         bnxt_free_cp_ring(bp, cpr, 0);
1712                         cpr->cp_ring_struct->fw_ring_id = INVALID_HW_RING_ID;
1713                 }
1714         }
1715
1716         return rc;
1717 }
1718
1719 int bnxt_alloc_all_hwrm_ring_grps(struct bnxt *bp)
1720 {
1721         uint16_t i;
1722         uint32_t rc = 0;
1723
1724         for (i = 0; i < bp->rx_cp_nr_rings; i++) {
1725                 rc = bnxt_hwrm_ring_grp_alloc(bp, i);
1726                 if (rc)
1727                         return rc;
1728         }
1729         return rc;
1730 }
1731
1732 void bnxt_free_hwrm_resources(struct bnxt *bp)
1733 {
1734         /* Release memzone */
1735         rte_free(bp->hwrm_cmd_resp_addr);
1736         rte_free(bp->hwrm_short_cmd_req_addr);
1737         bp->hwrm_cmd_resp_addr = NULL;
1738         bp->hwrm_short_cmd_req_addr = NULL;
1739         bp->hwrm_cmd_resp_dma_addr = 0;
1740         bp->hwrm_short_cmd_req_dma_addr = 0;
1741 }
1742
1743 int bnxt_alloc_hwrm_resources(struct bnxt *bp)
1744 {
1745         struct rte_pci_device *pdev = bp->pdev;
1746         char type[RTE_MEMZONE_NAMESIZE];
1747
1748         sprintf(type, "bnxt_hwrm_%04x:%02x:%02x:%02x", pdev->addr.domain,
1749                 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
1750         bp->max_resp_len = HWRM_MAX_RESP_LEN;
1751         bp->hwrm_cmd_resp_addr = rte_malloc(type, bp->max_resp_len, 0);
1752         rte_mem_lock_page(bp->hwrm_cmd_resp_addr);
1753         if (bp->hwrm_cmd_resp_addr == NULL)
1754                 return -ENOMEM;
1755         bp->hwrm_cmd_resp_dma_addr =
1756                 rte_mem_virt2iova(bp->hwrm_cmd_resp_addr);
1757         if (bp->hwrm_cmd_resp_dma_addr == 0) {
1758                 RTE_LOG(ERR, PMD,
1759                         "unable to map response address to physical memory\n");
1760                 return -ENOMEM;
1761         }
1762         rte_spinlock_init(&bp->hwrm_lock);
1763
1764         return 0;
1765 }
1766
1767 int bnxt_clear_hwrm_vnic_filters(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1768 {
1769         struct bnxt_filter_info *filter;
1770         int rc = 0;
1771
1772         STAILQ_FOREACH(filter, &vnic->filter, next) {
1773                 if (filter->filter_type == HWRM_CFA_EM_FILTER)
1774                         rc = bnxt_hwrm_clear_em_filter(bp, filter);
1775                 else if (filter->filter_type == HWRM_CFA_NTUPLE_FILTER)
1776                         rc = bnxt_hwrm_clear_ntuple_filter(bp, filter);
1777                 else
1778                         rc = bnxt_hwrm_clear_l2_filter(bp, filter);
1779                 //if (rc)
1780                         //break;
1781         }
1782         return rc;
1783 }
1784
1785 static int
1786 bnxt_clear_hwrm_vnic_flows(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1787 {
1788         struct bnxt_filter_info *filter;
1789         struct rte_flow *flow;
1790         int rc = 0;
1791
1792         STAILQ_FOREACH(flow, &vnic->flow_list, next) {
1793                 filter = flow->filter;
1794                 RTE_LOG(ERR, PMD, "filter type %d\n", filter->filter_type);
1795                 if (filter->filter_type == HWRM_CFA_EM_FILTER)
1796                         rc = bnxt_hwrm_clear_em_filter(bp, filter);
1797                 else if (filter->filter_type == HWRM_CFA_NTUPLE_FILTER)
1798                         rc = bnxt_hwrm_clear_ntuple_filter(bp, filter);
1799                 else
1800                         rc = bnxt_hwrm_clear_l2_filter(bp, filter);
1801
1802                 STAILQ_REMOVE(&vnic->flow_list, flow, rte_flow, next);
1803                 rte_free(flow);
1804                 //if (rc)
1805                         //break;
1806         }
1807         return rc;
1808 }
1809
1810 int bnxt_set_hwrm_vnic_filters(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1811 {
1812         struct bnxt_filter_info *filter;
1813         int rc = 0;
1814
1815         STAILQ_FOREACH(filter, &vnic->filter, next) {
1816                 if (filter->filter_type == HWRM_CFA_EM_FILTER)
1817                         rc = bnxt_hwrm_set_em_filter(bp, filter->dst_id,
1818                                                      filter);
1819                 else if (filter->filter_type == HWRM_CFA_NTUPLE_FILTER)
1820                         rc = bnxt_hwrm_set_ntuple_filter(bp, filter->dst_id,
1821                                                          filter);
1822                 else
1823                         rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id,
1824                                                      filter);
1825                 if (rc)
1826                         break;
1827         }
1828         return rc;
1829 }
1830
1831 void bnxt_free_tunnel_ports(struct bnxt *bp)
1832 {
1833         if (bp->vxlan_port_cnt)
1834                 bnxt_hwrm_tunnel_dst_port_free(bp, bp->vxlan_fw_dst_port_id,
1835                         HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN);
1836         bp->vxlan_port = 0;
1837         if (bp->geneve_port_cnt)
1838                 bnxt_hwrm_tunnel_dst_port_free(bp, bp->geneve_fw_dst_port_id,
1839                         HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE);
1840         bp->geneve_port = 0;
1841 }
1842
1843 void bnxt_free_all_hwrm_resources(struct bnxt *bp)
1844 {
1845         int i;
1846
1847         if (bp->vnic_info == NULL)
1848                 return;
1849
1850         /*
1851          * Cleanup VNICs in reverse order, to make sure the L2 filter
1852          * from vnic0 is last to be cleaned up.
1853          */
1854         for (i = bp->nr_vnics - 1; i >= 0; i--) {
1855                 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
1856
1857                 bnxt_clear_hwrm_vnic_flows(bp, vnic);
1858
1859                 bnxt_clear_hwrm_vnic_filters(bp, vnic);
1860
1861                 bnxt_hwrm_vnic_ctx_free(bp, vnic);
1862
1863                 bnxt_hwrm_vnic_tpa_cfg(bp, vnic, false);
1864
1865                 bnxt_hwrm_vnic_free(bp, vnic);
1866         }
1867         /* Ring resources */
1868         bnxt_free_all_hwrm_rings(bp);
1869         bnxt_free_all_hwrm_ring_grps(bp);
1870         bnxt_free_all_hwrm_stat_ctxs(bp);
1871         bnxt_free_tunnel_ports(bp);
1872 }
1873
1874 static uint16_t bnxt_parse_eth_link_duplex(uint32_t conf_link_speed)
1875 {
1876         uint8_t hw_link_duplex = HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH;
1877
1878         if ((conf_link_speed & ETH_LINK_SPEED_FIXED) == ETH_LINK_SPEED_AUTONEG)
1879                 return HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH;
1880
1881         switch (conf_link_speed) {
1882         case ETH_LINK_SPEED_10M_HD:
1883         case ETH_LINK_SPEED_100M_HD:
1884                 return HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_HALF;
1885         }
1886         return hw_link_duplex;
1887 }
1888
1889 static uint16_t bnxt_parse_eth_link_speed(uint32_t conf_link_speed)
1890 {
1891         uint16_t eth_link_speed = 0;
1892
1893         if (conf_link_speed == ETH_LINK_SPEED_AUTONEG)
1894                 return ETH_LINK_SPEED_AUTONEG;
1895
1896         switch (conf_link_speed & ~ETH_LINK_SPEED_FIXED) {
1897         case ETH_LINK_SPEED_100M:
1898         case ETH_LINK_SPEED_100M_HD:
1899                 eth_link_speed =
1900                         HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_100MB;
1901                 break;
1902         case ETH_LINK_SPEED_1G:
1903                 eth_link_speed =
1904                         HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_1GB;
1905                 break;
1906         case ETH_LINK_SPEED_2_5G:
1907                 eth_link_speed =
1908                         HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_2_5GB;
1909                 break;
1910         case ETH_LINK_SPEED_10G:
1911                 eth_link_speed =
1912                         HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_10GB;
1913                 break;
1914         case ETH_LINK_SPEED_20G:
1915                 eth_link_speed =
1916                         HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_20GB;
1917                 break;
1918         case ETH_LINK_SPEED_25G:
1919                 eth_link_speed =
1920                         HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_25GB;
1921                 break;
1922         case ETH_LINK_SPEED_40G:
1923                 eth_link_speed =
1924                         HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_40GB;
1925                 break;
1926         case ETH_LINK_SPEED_50G:
1927                 eth_link_speed =
1928                         HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_50GB;
1929                 break;
1930         default:
1931                 RTE_LOG(ERR, PMD,
1932                         "Unsupported link speed %d; default to AUTO\n",
1933                         conf_link_speed);
1934                 break;
1935         }
1936         return eth_link_speed;
1937 }
1938
1939 #define BNXT_SUPPORTED_SPEEDS (ETH_LINK_SPEED_100M | ETH_LINK_SPEED_100M_HD | \
1940                 ETH_LINK_SPEED_1G | ETH_LINK_SPEED_2_5G | \
1941                 ETH_LINK_SPEED_10G | ETH_LINK_SPEED_20G | ETH_LINK_SPEED_25G | \
1942                 ETH_LINK_SPEED_40G | ETH_LINK_SPEED_50G)
1943
1944 static int bnxt_valid_link_speed(uint32_t link_speed, uint16_t port_id)
1945 {
1946         uint32_t one_speed;
1947
1948         if (link_speed == ETH_LINK_SPEED_AUTONEG)
1949                 return 0;
1950
1951         if (link_speed & ETH_LINK_SPEED_FIXED) {
1952                 one_speed = link_speed & ~ETH_LINK_SPEED_FIXED;
1953
1954                 if (one_speed & (one_speed - 1)) {
1955                         RTE_LOG(ERR, PMD,
1956                                 "Invalid advertised speeds (%u) for port %u\n",
1957                                 link_speed, port_id);
1958                         return -EINVAL;
1959                 }
1960                 if ((one_speed & BNXT_SUPPORTED_SPEEDS) != one_speed) {
1961                         RTE_LOG(ERR, PMD,
1962                                 "Unsupported advertised speed (%u) for port %u\n",
1963                                 link_speed, port_id);
1964                         return -EINVAL;
1965                 }
1966         } else {
1967                 if (!(link_speed & BNXT_SUPPORTED_SPEEDS)) {
1968                         RTE_LOG(ERR, PMD,
1969                                 "Unsupported advertised speeds (%u) for port %u\n",
1970                                 link_speed, port_id);
1971                         return -EINVAL;
1972                 }
1973         }
1974         return 0;
1975 }
1976
1977 static uint16_t
1978 bnxt_parse_eth_link_speed_mask(struct bnxt *bp, uint32_t link_speed)
1979 {
1980         uint16_t ret = 0;
1981
1982         if (link_speed == ETH_LINK_SPEED_AUTONEG) {
1983                 if (bp->link_info.support_speeds)
1984                         return bp->link_info.support_speeds;
1985                 link_speed = BNXT_SUPPORTED_SPEEDS;
1986         }
1987
1988         if (link_speed & ETH_LINK_SPEED_100M)
1989                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100MB;
1990         if (link_speed & ETH_LINK_SPEED_100M_HD)
1991                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100MB;
1992         if (link_speed & ETH_LINK_SPEED_1G)
1993                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_1GB;
1994         if (link_speed & ETH_LINK_SPEED_2_5G)
1995                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_2_5GB;
1996         if (link_speed & ETH_LINK_SPEED_10G)
1997                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_10GB;
1998         if (link_speed & ETH_LINK_SPEED_20G)
1999                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_20GB;
2000         if (link_speed & ETH_LINK_SPEED_25G)
2001                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_25GB;
2002         if (link_speed & ETH_LINK_SPEED_40G)
2003                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_40GB;
2004         if (link_speed & ETH_LINK_SPEED_50G)
2005                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_50GB;
2006         return ret;
2007 }
2008
2009 static uint32_t bnxt_parse_hw_link_speed(uint16_t hw_link_speed)
2010 {
2011         uint32_t eth_link_speed = ETH_SPEED_NUM_NONE;
2012
2013         switch (hw_link_speed) {
2014         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_100MB:
2015                 eth_link_speed = ETH_SPEED_NUM_100M;
2016                 break;
2017         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_1GB:
2018                 eth_link_speed = ETH_SPEED_NUM_1G;
2019                 break;
2020         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_2_5GB:
2021                 eth_link_speed = ETH_SPEED_NUM_2_5G;
2022                 break;
2023         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_10GB:
2024                 eth_link_speed = ETH_SPEED_NUM_10G;
2025                 break;
2026         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_20GB:
2027                 eth_link_speed = ETH_SPEED_NUM_20G;
2028                 break;
2029         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_25GB:
2030                 eth_link_speed = ETH_SPEED_NUM_25G;
2031                 break;
2032         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_40GB:
2033                 eth_link_speed = ETH_SPEED_NUM_40G;
2034                 break;
2035         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_50GB:
2036                 eth_link_speed = ETH_SPEED_NUM_50G;
2037                 break;
2038         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_2GB:
2039         default:
2040                 RTE_LOG(ERR, PMD, "HWRM link speed %d not defined\n",
2041                         hw_link_speed);
2042                 break;
2043         }
2044         return eth_link_speed;
2045 }
2046
2047 static uint16_t bnxt_parse_hw_link_duplex(uint16_t hw_link_duplex)
2048 {
2049         uint16_t eth_link_duplex = ETH_LINK_FULL_DUPLEX;
2050
2051         switch (hw_link_duplex) {
2052         case HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH:
2053         case HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_FULL:
2054                 eth_link_duplex = ETH_LINK_FULL_DUPLEX;
2055                 break;
2056         case HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_HALF:
2057                 eth_link_duplex = ETH_LINK_HALF_DUPLEX;
2058                 break;
2059         default:
2060                 RTE_LOG(ERR, PMD, "HWRM link duplex %d not defined\n",
2061                         hw_link_duplex);
2062                 break;
2063         }
2064         return eth_link_duplex;
2065 }
2066
2067 int bnxt_get_hwrm_link_config(struct bnxt *bp, struct rte_eth_link *link)
2068 {
2069         int rc = 0;
2070         struct bnxt_link_info *link_info = &bp->link_info;
2071
2072         rc = bnxt_hwrm_port_phy_qcfg(bp, link_info);
2073         if (rc) {
2074                 RTE_LOG(ERR, PMD,
2075                         "Get link config failed with rc %d\n", rc);
2076                 goto exit;
2077         }
2078         if (link_info->link_speed)
2079                 link->link_speed =
2080                         bnxt_parse_hw_link_speed(link_info->link_speed);
2081         else
2082                 link->link_speed = ETH_SPEED_NUM_NONE;
2083         link->link_duplex = bnxt_parse_hw_link_duplex(link_info->duplex);
2084         link->link_status = link_info->link_up;
2085         link->link_autoneg = link_info->auto_mode ==
2086                 HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_MODE_NONE ?
2087                 ETH_LINK_FIXED : ETH_LINK_AUTONEG;
2088 exit:
2089         return rc;
2090 }
2091
2092 int bnxt_set_hwrm_link_config(struct bnxt *bp, bool link_up)
2093 {
2094         int rc = 0;
2095         struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
2096         struct bnxt_link_info link_req;
2097         uint16_t speed;
2098
2099         if (BNXT_NPAR_PF(bp) || BNXT_VF(bp))
2100                 return 0;
2101
2102         rc = bnxt_valid_link_speed(dev_conf->link_speeds,
2103                         bp->eth_dev->data->port_id);
2104         if (rc)
2105                 goto error;
2106
2107         memset(&link_req, 0, sizeof(link_req));
2108         link_req.link_up = link_up;
2109         if (!link_up)
2110                 goto port_phy_cfg;
2111
2112         speed = bnxt_parse_eth_link_speed(dev_conf->link_speeds);
2113         link_req.phy_flags = HWRM_PORT_PHY_CFG_INPUT_FLAGS_RESET_PHY;
2114         if (speed == 0) {
2115                 link_req.phy_flags |=
2116                                 HWRM_PORT_PHY_CFG_INPUT_FLAGS_RESTART_AUTONEG;
2117                 link_req.auto_mode =
2118                                 HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_SPEED_MASK;
2119                 link_req.auto_link_speed_mask =
2120                         bnxt_parse_eth_link_speed_mask(bp,
2121                                                        dev_conf->link_speeds);
2122         } else {
2123                 link_req.phy_flags |= HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE;
2124                 link_req.link_speed = speed;
2125                 RTE_LOG(INFO, PMD, "Set Link Speed %x\n", speed);
2126         }
2127         link_req.duplex = bnxt_parse_eth_link_duplex(dev_conf->link_speeds);
2128         link_req.auto_pause = bp->link_info.auto_pause;
2129         link_req.force_pause = bp->link_info.force_pause;
2130
2131 port_phy_cfg:
2132         rc = bnxt_hwrm_port_phy_cfg(bp, &link_req);
2133         if (rc) {
2134                 RTE_LOG(ERR, PMD,
2135                         "Set link config failed with rc %d\n", rc);
2136         }
2137
2138 error:
2139         return rc;
2140 }
2141
2142 /* JIRA 22088 */
2143 int bnxt_hwrm_func_qcfg(struct bnxt *bp)
2144 {
2145         struct hwrm_func_qcfg_input req = {0};
2146         struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
2147         int rc = 0;
2148
2149         HWRM_PREP(req, FUNC_QCFG);
2150         req.fid = rte_cpu_to_le_16(0xffff);
2151
2152         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2153
2154         HWRM_CHECK_RESULT();
2155
2156         /* Hard Coded.. 0xfff VLAN ID mask */
2157         bp->vlan = rte_le_to_cpu_16(resp->vlan) & 0xfff;
2158
2159         switch (resp->port_partition_type) {
2160         case HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR1_0:
2161         case HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR1_5:
2162         case HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR2_0:
2163                 bp->port_partition_type = resp->port_partition_type;
2164                 break;
2165         default:
2166                 bp->port_partition_type = 0;
2167                 break;
2168         }
2169
2170         HWRM_UNLOCK();
2171
2172         return rc;
2173 }
2174
2175 static void copy_func_cfg_to_qcaps(struct hwrm_func_cfg_input *fcfg,
2176                                    struct hwrm_func_qcaps_output *qcaps)
2177 {
2178         qcaps->max_rsscos_ctx = fcfg->num_rsscos_ctxs;
2179         memcpy(qcaps->mac_address, fcfg->dflt_mac_addr,
2180                sizeof(qcaps->mac_address));
2181         qcaps->max_l2_ctxs = fcfg->num_l2_ctxs;
2182         qcaps->max_rx_rings = fcfg->num_rx_rings;
2183         qcaps->max_tx_rings = fcfg->num_tx_rings;
2184         qcaps->max_cmpl_rings = fcfg->num_cmpl_rings;
2185         qcaps->max_stat_ctx = fcfg->num_stat_ctxs;
2186         qcaps->max_vfs = 0;
2187         qcaps->first_vf_id = 0;
2188         qcaps->max_vnics = fcfg->num_vnics;
2189         qcaps->max_decap_records = 0;
2190         qcaps->max_encap_records = 0;
2191         qcaps->max_tx_wm_flows = 0;
2192         qcaps->max_tx_em_flows = 0;
2193         qcaps->max_rx_wm_flows = 0;
2194         qcaps->max_rx_em_flows = 0;
2195         qcaps->max_flow_id = 0;
2196         qcaps->max_mcast_filters = fcfg->num_mcast_filters;
2197         qcaps->max_sp_tx_rings = 0;
2198         qcaps->max_hw_ring_grps = fcfg->num_hw_ring_grps;
2199 }
2200
2201 static int bnxt_hwrm_pf_func_cfg(struct bnxt *bp, int tx_rings)
2202 {
2203         struct hwrm_func_cfg_input req = {0};
2204         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2205         int rc;
2206
2207         req.enables = rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_MTU |
2208                         HWRM_FUNC_CFG_INPUT_ENABLES_MRU |
2209                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS |
2210                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_STAT_CTXS |
2211                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_CMPL_RINGS |
2212                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_TX_RINGS |
2213                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RX_RINGS |
2214                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_L2_CTXS |
2215                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_VNICS |
2216                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_HW_RING_GRPS);
2217         req.flags = rte_cpu_to_le_32(bp->pf.func_cfg_flags);
2218         req.mtu = rte_cpu_to_le_16(BNXT_MAX_MTU);
2219         req.mru = rte_cpu_to_le_16(bp->eth_dev->data->mtu + ETHER_HDR_LEN +
2220                                    ETHER_CRC_LEN + VLAN_TAG_SIZE);
2221         req.num_rsscos_ctxs = rte_cpu_to_le_16(bp->max_rsscos_ctx);
2222         req.num_stat_ctxs = rte_cpu_to_le_16(bp->max_stat_ctx);
2223         req.num_cmpl_rings = rte_cpu_to_le_16(bp->max_cp_rings);
2224         req.num_tx_rings = rte_cpu_to_le_16(tx_rings);
2225         req.num_rx_rings = rte_cpu_to_le_16(bp->max_rx_rings);
2226         req.num_l2_ctxs = rte_cpu_to_le_16(bp->max_l2_ctx);
2227         req.num_vnics = rte_cpu_to_le_16(bp->max_vnics);
2228         req.num_hw_ring_grps = rte_cpu_to_le_16(bp->max_ring_grps);
2229         req.fid = rte_cpu_to_le_16(0xffff);
2230
2231         HWRM_PREP(req, FUNC_CFG);
2232
2233         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2234
2235         HWRM_CHECK_RESULT();
2236         HWRM_UNLOCK();
2237
2238         return rc;
2239 }
2240
2241 static void populate_vf_func_cfg_req(struct bnxt *bp,
2242                                      struct hwrm_func_cfg_input *req,
2243                                      int num_vfs)
2244 {
2245         req->enables = rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_MTU |
2246                         HWRM_FUNC_CFG_INPUT_ENABLES_MRU |
2247                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS |
2248                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_STAT_CTXS |
2249                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_CMPL_RINGS |
2250                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_TX_RINGS |
2251                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RX_RINGS |
2252                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_L2_CTXS |
2253                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_VNICS |
2254                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_HW_RING_GRPS);
2255
2256         req->mtu = rte_cpu_to_le_16(bp->eth_dev->data->mtu + ETHER_HDR_LEN +
2257                                     ETHER_CRC_LEN + VLAN_TAG_SIZE);
2258         req->mru = rte_cpu_to_le_16(bp->eth_dev->data->mtu + ETHER_HDR_LEN +
2259                                     ETHER_CRC_LEN + VLAN_TAG_SIZE);
2260         req->num_rsscos_ctxs = rte_cpu_to_le_16(bp->max_rsscos_ctx /
2261                                                 (num_vfs + 1));
2262         req->num_stat_ctxs = rte_cpu_to_le_16(bp->max_stat_ctx / (num_vfs + 1));
2263         req->num_cmpl_rings = rte_cpu_to_le_16(bp->max_cp_rings /
2264                                                (num_vfs + 1));
2265         req->num_tx_rings = rte_cpu_to_le_16(bp->max_tx_rings / (num_vfs + 1));
2266         req->num_rx_rings = rte_cpu_to_le_16(bp->max_rx_rings / (num_vfs + 1));
2267         req->num_l2_ctxs = rte_cpu_to_le_16(bp->max_l2_ctx / (num_vfs + 1));
2268         /* TODO: For now, do not support VMDq/RFS on VFs. */
2269         req->num_vnics = rte_cpu_to_le_16(1);
2270         req->num_hw_ring_grps = rte_cpu_to_le_16(bp->max_ring_grps /
2271                                                  (num_vfs + 1));
2272 }
2273
2274 static void add_random_mac_if_needed(struct bnxt *bp,
2275                                      struct hwrm_func_cfg_input *cfg_req,
2276                                      int vf)
2277 {
2278         struct ether_addr mac;
2279
2280         if (bnxt_hwrm_func_qcfg_vf_default_mac(bp, vf, &mac))
2281                 return;
2282
2283         if (memcmp(mac.addr_bytes, "\x00\x00\x00\x00\x00", 6) == 0) {
2284                 cfg_req->enables |=
2285                 rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
2286                 eth_random_addr(cfg_req->dflt_mac_addr);
2287                 bp->pf.vf_info[vf].random_mac = true;
2288         } else {
2289                 memcpy(cfg_req->dflt_mac_addr, mac.addr_bytes, ETHER_ADDR_LEN);
2290         }
2291 }
2292
2293 static void reserve_resources_from_vf(struct bnxt *bp,
2294                                       struct hwrm_func_cfg_input *cfg_req,
2295                                       int vf)
2296 {
2297         struct hwrm_func_qcaps_input req = {0};
2298         struct hwrm_func_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
2299         int rc;
2300
2301         /* Get the actual allocated values now */
2302         HWRM_PREP(req, FUNC_QCAPS);
2303         req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
2304         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2305
2306         if (rc) {
2307                 RTE_LOG(ERR, PMD, "hwrm_func_qcaps failed rc:%d\n", rc);
2308                 copy_func_cfg_to_qcaps(cfg_req, resp);
2309         } else if (resp->error_code) {
2310                 rc = rte_le_to_cpu_16(resp->error_code);
2311                 RTE_LOG(ERR, PMD, "hwrm_func_qcaps error %d\n", rc);
2312                 copy_func_cfg_to_qcaps(cfg_req, resp);
2313         }
2314
2315         bp->max_rsscos_ctx -= rte_le_to_cpu_16(resp->max_rsscos_ctx);
2316         bp->max_stat_ctx -= rte_le_to_cpu_16(resp->max_stat_ctx);
2317         bp->max_cp_rings -= rte_le_to_cpu_16(resp->max_cmpl_rings);
2318         bp->max_tx_rings -= rte_le_to_cpu_16(resp->max_tx_rings);
2319         bp->max_rx_rings -= rte_le_to_cpu_16(resp->max_rx_rings);
2320         bp->max_l2_ctx -= rte_le_to_cpu_16(resp->max_l2_ctxs);
2321         /*
2322          * TODO: While not supporting VMDq with VFs, max_vnics is always
2323          * forced to 1 in this case
2324          */
2325         //bp->max_vnics -= rte_le_to_cpu_16(esp->max_vnics);
2326         bp->max_ring_grps -= rte_le_to_cpu_16(resp->max_hw_ring_grps);
2327
2328         HWRM_UNLOCK();
2329 }
2330
2331 int bnxt_hwrm_func_qcfg_current_vf_vlan(struct bnxt *bp, int vf)
2332 {
2333         struct hwrm_func_qcfg_input req = {0};
2334         struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
2335         int rc;
2336
2337         /* Check for zero MAC address */
2338         HWRM_PREP(req, FUNC_QCFG);
2339         req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
2340         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2341         if (rc) {
2342                 RTE_LOG(ERR, PMD, "hwrm_func_qcfg failed rc:%d\n", rc);
2343                 return -1;
2344         } else if (resp->error_code) {
2345                 rc = rte_le_to_cpu_16(resp->error_code);
2346                 RTE_LOG(ERR, PMD, "hwrm_func_qcfg error %d\n", rc);
2347                 return -1;
2348         }
2349         rc = rte_le_to_cpu_16(resp->vlan);
2350
2351         HWRM_UNLOCK();
2352
2353         return rc;
2354 }
2355
2356 static int update_pf_resource_max(struct bnxt *bp)
2357 {
2358         struct hwrm_func_qcfg_input req = {0};
2359         struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
2360         int rc;
2361
2362         /* And copy the allocated numbers into the pf struct */
2363         HWRM_PREP(req, FUNC_QCFG);
2364         req.fid = rte_cpu_to_le_16(0xffff);
2365         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2366         HWRM_CHECK_RESULT();
2367
2368         /* Only TX ring value reflects actual allocation? TODO */
2369         bp->max_tx_rings = rte_le_to_cpu_16(resp->alloc_tx_rings);
2370         bp->pf.evb_mode = resp->evb_mode;
2371
2372         HWRM_UNLOCK();
2373
2374         return rc;
2375 }
2376
2377 int bnxt_hwrm_allocate_pf_only(struct bnxt *bp)
2378 {
2379         int rc;
2380
2381         if (!BNXT_PF(bp)) {
2382                 RTE_LOG(ERR, PMD, "Attempt to allcoate VFs on a VF!\n");
2383                 return -1;
2384         }
2385
2386         rc = bnxt_hwrm_func_qcaps(bp);
2387         if (rc)
2388                 return rc;
2389
2390         bp->pf.func_cfg_flags &=
2391                 ~(HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_ENABLE |
2392                   HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_DISABLE);
2393         bp->pf.func_cfg_flags |=
2394                 HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_DISABLE;
2395         rc = bnxt_hwrm_pf_func_cfg(bp, bp->max_tx_rings);
2396         return rc;
2397 }
2398
2399 int bnxt_hwrm_allocate_vfs(struct bnxt *bp, int num_vfs)
2400 {
2401         struct hwrm_func_cfg_input req = {0};
2402         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2403         int i;
2404         size_t sz;
2405         int rc = 0;
2406         size_t req_buf_sz;
2407
2408         if (!BNXT_PF(bp)) {
2409                 RTE_LOG(ERR, PMD, "Attempt to allcoate VFs on a VF!\n");
2410                 return -1;
2411         }
2412
2413         rc = bnxt_hwrm_func_qcaps(bp);
2414
2415         if (rc)
2416                 return rc;
2417
2418         bp->pf.active_vfs = num_vfs;
2419
2420         /*
2421          * First, configure the PF to only use one TX ring.  This ensures that
2422          * there are enough rings for all VFs.
2423          *
2424          * If we don't do this, when we call func_alloc() later, we will lock
2425          * extra rings to the PF that won't be available during func_cfg() of
2426          * the VFs.
2427          *
2428          * This has been fixed with firmware versions above 20.6.54
2429          */
2430         bp->pf.func_cfg_flags &=
2431                 ~(HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_ENABLE |
2432                   HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_DISABLE);
2433         bp->pf.func_cfg_flags |=
2434                 HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_ENABLE;
2435         rc = bnxt_hwrm_pf_func_cfg(bp, 1);
2436         if (rc)
2437                 return rc;
2438
2439         /*
2440          * Now, create and register a buffer to hold forwarded VF requests
2441          */
2442         req_buf_sz = num_vfs * HWRM_MAX_REQ_LEN;
2443         bp->pf.vf_req_buf = rte_malloc("bnxt_vf_fwd", req_buf_sz,
2444                 page_roundup(num_vfs * HWRM_MAX_REQ_LEN));
2445         if (bp->pf.vf_req_buf == NULL) {
2446                 rc = -ENOMEM;
2447                 goto error_free;
2448         }
2449         for (sz = 0; sz < req_buf_sz; sz += getpagesize())
2450                 rte_mem_lock_page(((char *)bp->pf.vf_req_buf) + sz);
2451         for (i = 0; i < num_vfs; i++)
2452                 bp->pf.vf_info[i].req_buf = ((char *)bp->pf.vf_req_buf) +
2453                                         (i * HWRM_MAX_REQ_LEN);
2454
2455         rc = bnxt_hwrm_func_buf_rgtr(bp);
2456         if (rc)
2457                 goto error_free;
2458
2459         populate_vf_func_cfg_req(bp, &req, num_vfs);
2460
2461         bp->pf.active_vfs = 0;
2462         for (i = 0; i < num_vfs; i++) {
2463                 add_random_mac_if_needed(bp, &req, i);
2464
2465                 HWRM_PREP(req, FUNC_CFG);
2466                 req.flags = rte_cpu_to_le_32(bp->pf.vf_info[i].func_cfg_flags);
2467                 req.fid = rte_cpu_to_le_16(bp->pf.vf_info[i].fid);
2468                 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2469
2470                 /* Clear enable flag for next pass */
2471                 req.enables &= ~rte_cpu_to_le_32(
2472                                 HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
2473
2474                 if (rc || resp->error_code) {
2475                         RTE_LOG(ERR, PMD,
2476                                 "Failed to initizlie VF %d\n", i);
2477                         RTE_LOG(ERR, PMD,
2478                                 "Not all VFs available. (%d, %d)\n",
2479                                 rc, resp->error_code);
2480                         HWRM_UNLOCK();
2481                         break;
2482                 }
2483
2484                 HWRM_UNLOCK();
2485
2486                 reserve_resources_from_vf(bp, &req, i);
2487                 bp->pf.active_vfs++;
2488                 bnxt_hwrm_func_clr_stats(bp, bp->pf.vf_info[i].fid);
2489         }
2490
2491         /*
2492          * Now configure the PF to use "the rest" of the resources
2493          * We're using STD_TX_RING_MODE here though which will limit the TX
2494          * rings.  This will allow QoS to function properly.  Not setting this
2495          * will cause PF rings to break bandwidth settings.
2496          */
2497         rc = bnxt_hwrm_pf_func_cfg(bp, bp->max_tx_rings);
2498         if (rc)
2499                 goto error_free;
2500
2501         rc = update_pf_resource_max(bp);
2502         if (rc)
2503                 goto error_free;
2504
2505         return rc;
2506
2507 error_free:
2508         bnxt_hwrm_func_buf_unrgtr(bp);
2509         return rc;
2510 }
2511
2512 int bnxt_hwrm_pf_evb_mode(struct bnxt *bp)
2513 {
2514         struct hwrm_func_cfg_input req = {0};
2515         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2516         int rc;
2517
2518         HWRM_PREP(req, FUNC_CFG);
2519
2520         req.fid = rte_cpu_to_le_16(0xffff);
2521         req.enables = rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_EVB_MODE);
2522         req.evb_mode = bp->pf.evb_mode;
2523
2524         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2525         HWRM_CHECK_RESULT();
2526         HWRM_UNLOCK();
2527
2528         return rc;
2529 }
2530
2531 int bnxt_hwrm_tunnel_dst_port_alloc(struct bnxt *bp, uint16_t port,
2532                                 uint8_t tunnel_type)
2533 {
2534         struct hwrm_tunnel_dst_port_alloc_input req = {0};
2535         struct hwrm_tunnel_dst_port_alloc_output *resp = bp->hwrm_cmd_resp_addr;
2536         int rc = 0;
2537
2538         HWRM_PREP(req, TUNNEL_DST_PORT_ALLOC);
2539         req.tunnel_type = tunnel_type;
2540         req.tunnel_dst_port_val = port;
2541         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2542         HWRM_CHECK_RESULT();
2543
2544         switch (tunnel_type) {
2545         case HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN:
2546                 bp->vxlan_fw_dst_port_id = resp->tunnel_dst_port_id;
2547                 bp->vxlan_port = port;
2548                 break;
2549         case HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_GENEVE:
2550                 bp->geneve_fw_dst_port_id = resp->tunnel_dst_port_id;
2551                 bp->geneve_port = port;
2552                 break;
2553         default:
2554                 break;
2555         }
2556
2557         HWRM_UNLOCK();
2558
2559         return rc;
2560 }
2561
2562 int bnxt_hwrm_tunnel_dst_port_free(struct bnxt *bp, uint16_t port,
2563                                 uint8_t tunnel_type)
2564 {
2565         struct hwrm_tunnel_dst_port_free_input req = {0};
2566         struct hwrm_tunnel_dst_port_free_output *resp = bp->hwrm_cmd_resp_addr;
2567         int rc = 0;
2568
2569         HWRM_PREP(req, TUNNEL_DST_PORT_FREE);
2570
2571         req.tunnel_type = tunnel_type;
2572         req.tunnel_dst_port_id = rte_cpu_to_be_16(port);
2573         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2574
2575         HWRM_CHECK_RESULT();
2576         HWRM_UNLOCK();
2577
2578         return rc;
2579 }
2580
2581 int bnxt_hwrm_func_cfg_vf_set_flags(struct bnxt *bp, uint16_t vf,
2582                                         uint32_t flags)
2583 {
2584         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2585         struct hwrm_func_cfg_input req = {0};
2586         int rc;
2587
2588         HWRM_PREP(req, FUNC_CFG);
2589
2590         req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
2591         req.flags = rte_cpu_to_le_32(flags);
2592         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2593
2594         HWRM_CHECK_RESULT();
2595         HWRM_UNLOCK();
2596
2597         return rc;
2598 }
2599
2600 void vf_vnic_set_rxmask_cb(struct bnxt_vnic_info *vnic, void *flagp)
2601 {
2602         uint32_t *flag = flagp;
2603
2604         vnic->flags = *flag;
2605 }
2606
2607 int bnxt_set_rx_mask_no_vlan(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2608 {
2609         return bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
2610 }
2611
2612 int bnxt_hwrm_func_buf_rgtr(struct bnxt *bp)
2613 {
2614         int rc = 0;
2615         struct hwrm_func_buf_rgtr_input req = {.req_type = 0 };
2616         struct hwrm_func_buf_rgtr_output *resp = bp->hwrm_cmd_resp_addr;
2617
2618         HWRM_PREP(req, FUNC_BUF_RGTR);
2619
2620         req.req_buf_num_pages = rte_cpu_to_le_16(1);
2621         req.req_buf_page_size = rte_cpu_to_le_16(
2622                          page_getenum(bp->pf.active_vfs * HWRM_MAX_REQ_LEN));
2623         req.req_buf_len = rte_cpu_to_le_16(HWRM_MAX_REQ_LEN);
2624         req.req_buf_page_addr[0] =
2625                 rte_cpu_to_le_64(rte_mem_virt2iova(bp->pf.vf_req_buf));
2626         if (req.req_buf_page_addr[0] == 0) {
2627                 RTE_LOG(ERR, PMD,
2628                         "unable to map buffer address to physical memory\n");
2629                 return -ENOMEM;
2630         }
2631
2632         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2633
2634         HWRM_CHECK_RESULT();
2635         HWRM_UNLOCK();
2636
2637         return rc;
2638 }
2639
2640 int bnxt_hwrm_func_buf_unrgtr(struct bnxt *bp)
2641 {
2642         int rc = 0;
2643         struct hwrm_func_buf_unrgtr_input req = {.req_type = 0 };
2644         struct hwrm_func_buf_unrgtr_output *resp = bp->hwrm_cmd_resp_addr;
2645
2646         HWRM_PREP(req, FUNC_BUF_UNRGTR);
2647
2648         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2649
2650         HWRM_CHECK_RESULT();
2651         HWRM_UNLOCK();
2652
2653         return rc;
2654 }
2655
2656 int bnxt_hwrm_func_cfg_def_cp(struct bnxt *bp)
2657 {
2658         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2659         struct hwrm_func_cfg_input req = {0};
2660         int rc;
2661
2662         HWRM_PREP(req, FUNC_CFG);
2663
2664         req.fid = rte_cpu_to_le_16(0xffff);
2665         req.flags = rte_cpu_to_le_32(bp->pf.func_cfg_flags);
2666         req.enables = rte_cpu_to_le_32(
2667                         HWRM_FUNC_CFG_INPUT_ENABLES_ASYNC_EVENT_CR);
2668         req.async_event_cr = rte_cpu_to_le_16(
2669                         bp->def_cp_ring->cp_ring_struct->fw_ring_id);
2670         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2671
2672         HWRM_CHECK_RESULT();
2673         HWRM_UNLOCK();
2674
2675         return rc;
2676 }
2677
2678 int bnxt_hwrm_vf_func_cfg_def_cp(struct bnxt *bp)
2679 {
2680         struct hwrm_func_vf_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2681         struct hwrm_func_vf_cfg_input req = {0};
2682         int rc;
2683
2684         HWRM_PREP(req, FUNC_VF_CFG);
2685
2686         req.enables = rte_cpu_to_le_32(
2687                         HWRM_FUNC_CFG_INPUT_ENABLES_ASYNC_EVENT_CR);
2688         req.async_event_cr = rte_cpu_to_le_16(
2689                         bp->def_cp_ring->cp_ring_struct->fw_ring_id);
2690         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2691
2692         HWRM_CHECK_RESULT();
2693         HWRM_UNLOCK();
2694
2695         return rc;
2696 }
2697
2698 int bnxt_hwrm_set_default_vlan(struct bnxt *bp, int vf, uint8_t is_vf)
2699 {
2700         struct hwrm_func_cfg_input req = {0};
2701         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2702         uint16_t dflt_vlan, fid;
2703         uint32_t func_cfg_flags;
2704         int rc = 0;
2705
2706         HWRM_PREP(req, FUNC_CFG);
2707
2708         if (is_vf) {
2709                 dflt_vlan = bp->pf.vf_info[vf].dflt_vlan;
2710                 fid = bp->pf.vf_info[vf].fid;
2711                 func_cfg_flags = bp->pf.vf_info[vf].func_cfg_flags;
2712         } else {
2713                 fid = rte_cpu_to_le_16(0xffff);
2714                 func_cfg_flags = bp->pf.func_cfg_flags;
2715                 dflt_vlan = bp->vlan;
2716         }
2717
2718         req.flags = rte_cpu_to_le_32(func_cfg_flags);
2719         req.fid = rte_cpu_to_le_16(fid);
2720         req.enables |= rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_VLAN);
2721         req.dflt_vlan = rte_cpu_to_le_16(dflt_vlan);
2722
2723         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2724
2725         HWRM_CHECK_RESULT();
2726         HWRM_UNLOCK();
2727
2728         return rc;
2729 }
2730
2731 int bnxt_hwrm_func_bw_cfg(struct bnxt *bp, uint16_t vf,
2732                         uint16_t max_bw, uint16_t enables)
2733 {
2734         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2735         struct hwrm_func_cfg_input req = {0};
2736         int rc;
2737
2738         HWRM_PREP(req, FUNC_CFG);
2739
2740         req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
2741         req.enables |= rte_cpu_to_le_32(enables);
2742         req.flags = rte_cpu_to_le_32(bp->pf.vf_info[vf].func_cfg_flags);
2743         req.max_bw = rte_cpu_to_le_32(max_bw);
2744         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2745
2746         HWRM_CHECK_RESULT();
2747         HWRM_UNLOCK();
2748
2749         return rc;
2750 }
2751
2752 int bnxt_hwrm_set_vf_vlan(struct bnxt *bp, int vf)
2753 {
2754         struct hwrm_func_cfg_input req = {0};
2755         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2756         int rc = 0;
2757
2758         HWRM_PREP(req, FUNC_CFG);
2759
2760         req.flags = rte_cpu_to_le_32(bp->pf.vf_info[vf].func_cfg_flags);
2761         req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
2762         req.enables |= rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_VLAN);
2763         req.dflt_vlan = rte_cpu_to_le_16(bp->pf.vf_info[vf].dflt_vlan);
2764
2765         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2766
2767         HWRM_CHECK_RESULT();
2768         HWRM_UNLOCK();
2769
2770         return rc;
2771 }
2772
2773 int bnxt_hwrm_reject_fwd_resp(struct bnxt *bp, uint16_t target_id,
2774                               void *encaped, size_t ec_size)
2775 {
2776         int rc = 0;
2777         struct hwrm_reject_fwd_resp_input req = {.req_type = 0};
2778         struct hwrm_reject_fwd_resp_output *resp = bp->hwrm_cmd_resp_addr;
2779
2780         if (ec_size > sizeof(req.encap_request))
2781                 return -1;
2782
2783         HWRM_PREP(req, REJECT_FWD_RESP);
2784
2785         req.encap_resp_target_id = rte_cpu_to_le_16(target_id);
2786         memcpy(req.encap_request, encaped, ec_size);
2787
2788         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2789
2790         HWRM_CHECK_RESULT();
2791         HWRM_UNLOCK();
2792
2793         return rc;
2794 }
2795
2796 int bnxt_hwrm_func_qcfg_vf_default_mac(struct bnxt *bp, uint16_t vf,
2797                                        struct ether_addr *mac)
2798 {
2799         struct hwrm_func_qcfg_input req = {0};
2800         struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
2801         int rc;
2802
2803         HWRM_PREP(req, FUNC_QCFG);
2804
2805         req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
2806         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2807
2808         HWRM_CHECK_RESULT();
2809
2810         memcpy(mac->addr_bytes, resp->mac_address, ETHER_ADDR_LEN);
2811
2812         HWRM_UNLOCK();
2813
2814         return rc;
2815 }
2816
2817 int bnxt_hwrm_exec_fwd_resp(struct bnxt *bp, uint16_t target_id,
2818                             void *encaped, size_t ec_size)
2819 {
2820         int rc = 0;
2821         struct hwrm_exec_fwd_resp_input req = {.req_type = 0};
2822         struct hwrm_exec_fwd_resp_output *resp = bp->hwrm_cmd_resp_addr;
2823
2824         if (ec_size > sizeof(req.encap_request))
2825                 return -1;
2826
2827         HWRM_PREP(req, EXEC_FWD_RESP);
2828
2829         req.encap_resp_target_id = rte_cpu_to_le_16(target_id);
2830         memcpy(req.encap_request, encaped, ec_size);
2831
2832         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2833
2834         HWRM_CHECK_RESULT();
2835         HWRM_UNLOCK();
2836
2837         return rc;
2838 }
2839
2840 int bnxt_hwrm_ctx_qstats(struct bnxt *bp, uint32_t cid, int idx,
2841                          struct rte_eth_stats *stats, uint8_t rx)
2842 {
2843         int rc = 0;
2844         struct hwrm_stat_ctx_query_input req = {.req_type = 0};
2845         struct hwrm_stat_ctx_query_output *resp = bp->hwrm_cmd_resp_addr;
2846
2847         HWRM_PREP(req, STAT_CTX_QUERY);
2848
2849         req.stat_ctx_id = rte_cpu_to_le_32(cid);
2850
2851         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2852
2853         HWRM_CHECK_RESULT();
2854
2855         if (rx) {
2856                 stats->q_ipackets[idx] = rte_le_to_cpu_64(resp->rx_ucast_pkts);
2857                 stats->q_ipackets[idx] += rte_le_to_cpu_64(resp->rx_mcast_pkts);
2858                 stats->q_ipackets[idx] += rte_le_to_cpu_64(resp->rx_bcast_pkts);
2859                 stats->q_ibytes[idx] = rte_le_to_cpu_64(resp->rx_ucast_bytes);
2860                 stats->q_ibytes[idx] += rte_le_to_cpu_64(resp->rx_mcast_bytes);
2861                 stats->q_ibytes[idx] += rte_le_to_cpu_64(resp->rx_bcast_bytes);
2862                 stats->q_errors[idx] = rte_le_to_cpu_64(resp->rx_err_pkts);
2863                 stats->q_errors[idx] += rte_le_to_cpu_64(resp->rx_drop_pkts);
2864         } else {
2865                 stats->q_opackets[idx] = rte_le_to_cpu_64(resp->tx_ucast_pkts);
2866                 stats->q_opackets[idx] += rte_le_to_cpu_64(resp->tx_mcast_pkts);
2867                 stats->q_opackets[idx] += rte_le_to_cpu_64(resp->tx_bcast_pkts);
2868                 stats->q_obytes[idx] = rte_le_to_cpu_64(resp->tx_ucast_bytes);
2869                 stats->q_obytes[idx] += rte_le_to_cpu_64(resp->tx_mcast_bytes);
2870                 stats->q_obytes[idx] += rte_le_to_cpu_64(resp->tx_bcast_bytes);
2871                 stats->q_errors[idx] += rte_le_to_cpu_64(resp->tx_err_pkts);
2872         }
2873
2874
2875         HWRM_UNLOCK();
2876
2877         return rc;
2878 }
2879
2880 int bnxt_hwrm_port_qstats(struct bnxt *bp)
2881 {
2882         struct hwrm_port_qstats_input req = {0};
2883         struct hwrm_port_qstats_output *resp = bp->hwrm_cmd_resp_addr;
2884         struct bnxt_pf_info *pf = &bp->pf;
2885         int rc;
2886
2887         if (!(bp->flags & BNXT_FLAG_PORT_STATS))
2888                 return 0;
2889
2890         HWRM_PREP(req, PORT_QSTATS);
2891
2892         req.port_id = rte_cpu_to_le_16(pf->port_id);
2893         req.tx_stat_host_addr = rte_cpu_to_le_64(bp->hw_tx_port_stats_map);
2894         req.rx_stat_host_addr = rte_cpu_to_le_64(bp->hw_rx_port_stats_map);
2895         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2896
2897         HWRM_CHECK_RESULT();
2898         HWRM_UNLOCK();
2899
2900         return rc;
2901 }
2902
2903 int bnxt_hwrm_port_clr_stats(struct bnxt *bp)
2904 {
2905         struct hwrm_port_clr_stats_input req = {0};
2906         struct hwrm_port_clr_stats_output *resp = bp->hwrm_cmd_resp_addr;
2907         struct bnxt_pf_info *pf = &bp->pf;
2908         int rc;
2909
2910         if (!(bp->flags & BNXT_FLAG_PORT_STATS))
2911                 return 0;
2912
2913         HWRM_PREP(req, PORT_CLR_STATS);
2914
2915         req.port_id = rte_cpu_to_le_16(pf->port_id);
2916         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2917
2918         HWRM_CHECK_RESULT();
2919         HWRM_UNLOCK();
2920
2921         return rc;
2922 }
2923
2924 int bnxt_hwrm_port_led_qcaps(struct bnxt *bp)
2925 {
2926         struct hwrm_port_led_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
2927         struct hwrm_port_led_qcaps_input req = {0};
2928         int rc;
2929
2930         if (BNXT_VF(bp))
2931                 return 0;
2932
2933         HWRM_PREP(req, PORT_LED_QCAPS);
2934         req.port_id = bp->pf.port_id;
2935         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2936
2937         HWRM_CHECK_RESULT();
2938
2939         if (resp->num_leds > 0 && resp->num_leds < BNXT_MAX_LED) {
2940                 unsigned int i;
2941
2942                 bp->num_leds = resp->num_leds;
2943                 memcpy(bp->leds, &resp->led0_id,
2944                         sizeof(bp->leds[0]) * bp->num_leds);
2945                 for (i = 0; i < bp->num_leds; i++) {
2946                         struct bnxt_led_info *led = &bp->leds[i];
2947
2948                         uint16_t caps = led->led_state_caps;
2949
2950                         if (!led->led_group_id ||
2951                                 !BNXT_LED_ALT_BLINK_CAP(caps)) {
2952                                 bp->num_leds = 0;
2953                                 break;
2954                         }
2955                 }
2956         }
2957
2958         HWRM_UNLOCK();
2959
2960         return rc;
2961 }
2962
2963 int bnxt_hwrm_port_led_cfg(struct bnxt *bp, bool led_on)
2964 {
2965         struct hwrm_port_led_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2966         struct hwrm_port_led_cfg_input req = {0};
2967         struct bnxt_led_cfg *led_cfg;
2968         uint8_t led_state = HWRM_PORT_LED_QCFG_OUTPUT_LED0_STATE_DEFAULT;
2969         uint16_t duration = 0;
2970         int rc, i;
2971
2972         if (!bp->num_leds || BNXT_VF(bp))
2973                 return -EOPNOTSUPP;
2974
2975         HWRM_PREP(req, PORT_LED_CFG);
2976
2977         if (led_on) {
2978                 led_state = HWRM_PORT_LED_CFG_INPUT_LED0_STATE_BLINKALT;
2979                 duration = rte_cpu_to_le_16(500);
2980         }
2981         req.port_id = bp->pf.port_id;
2982         req.num_leds = bp->num_leds;
2983         led_cfg = (struct bnxt_led_cfg *)&req.led0_id;
2984         for (i = 0; i < bp->num_leds; i++, led_cfg++) {
2985                 req.enables |= BNXT_LED_DFLT_ENABLES(i);
2986                 led_cfg->led_id = bp->leds[i].led_id;
2987                 led_cfg->led_state = led_state;
2988                 led_cfg->led_blink_on = duration;
2989                 led_cfg->led_blink_off = duration;
2990                 led_cfg->led_group_id = bp->leds[i].led_group_id;
2991         }
2992
2993         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2994
2995         HWRM_CHECK_RESULT();
2996         HWRM_UNLOCK();
2997
2998         return rc;
2999 }
3000
3001 int bnxt_hwrm_nvm_get_dir_info(struct bnxt *bp, uint32_t *entries,
3002                                uint32_t *length)
3003 {
3004         int rc;
3005         struct hwrm_nvm_get_dir_info_input req = {0};
3006         struct hwrm_nvm_get_dir_info_output *resp = bp->hwrm_cmd_resp_addr;
3007
3008         HWRM_PREP(req, NVM_GET_DIR_INFO);
3009
3010         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
3011
3012         HWRM_CHECK_RESULT();
3013         HWRM_UNLOCK();
3014
3015         if (!rc) {
3016                 *entries = rte_le_to_cpu_32(resp->entries);
3017                 *length = rte_le_to_cpu_32(resp->entry_length);
3018         }
3019         return rc;
3020 }
3021
3022 int bnxt_get_nvram_directory(struct bnxt *bp, uint32_t len, uint8_t *data)
3023 {
3024         int rc;
3025         uint32_t dir_entries;
3026         uint32_t entry_length;
3027         uint8_t *buf;
3028         size_t buflen;
3029         rte_iova_t dma_handle;
3030         struct hwrm_nvm_get_dir_entries_input req = {0};
3031         struct hwrm_nvm_get_dir_entries_output *resp = bp->hwrm_cmd_resp_addr;
3032
3033         rc = bnxt_hwrm_nvm_get_dir_info(bp, &dir_entries, &entry_length);
3034         if (rc != 0)
3035                 return rc;
3036
3037         *data++ = dir_entries;
3038         *data++ = entry_length;
3039         len -= 2;
3040         memset(data, 0xff, len);
3041
3042         buflen = dir_entries * entry_length;
3043         buf = rte_malloc("nvm_dir", buflen, 0);
3044         rte_mem_lock_page(buf);
3045         if (buf == NULL)
3046                 return -ENOMEM;
3047         dma_handle = rte_mem_virt2iova(buf);
3048         if (dma_handle == 0) {
3049                 RTE_LOG(ERR, PMD,
3050                         "unable to map response address to physical memory\n");
3051                 return -ENOMEM;
3052         }
3053         HWRM_PREP(req, NVM_GET_DIR_ENTRIES);
3054         req.host_dest_addr = rte_cpu_to_le_64(dma_handle);
3055         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
3056
3057         HWRM_CHECK_RESULT();
3058         HWRM_UNLOCK();
3059
3060         if (rc == 0)
3061                 memcpy(data, buf, len > buflen ? buflen : len);
3062
3063         rte_free(buf);
3064
3065         return rc;
3066 }
3067
3068 int bnxt_hwrm_get_nvram_item(struct bnxt *bp, uint32_t index,
3069                              uint32_t offset, uint32_t length,
3070                              uint8_t *data)
3071 {
3072         int rc;
3073         uint8_t *buf;
3074         rte_iova_t dma_handle;
3075         struct hwrm_nvm_read_input req = {0};
3076         struct hwrm_nvm_read_output *resp = bp->hwrm_cmd_resp_addr;
3077
3078         buf = rte_malloc("nvm_item", length, 0);
3079         rte_mem_lock_page(buf);
3080         if (!buf)
3081                 return -ENOMEM;
3082
3083         dma_handle = rte_mem_virt2iova(buf);
3084         if (dma_handle == 0) {
3085                 RTE_LOG(ERR, PMD,
3086                         "unable to map response address to physical memory\n");
3087                 return -ENOMEM;
3088         }
3089         HWRM_PREP(req, NVM_READ);
3090         req.host_dest_addr = rte_cpu_to_le_64(dma_handle);
3091         req.dir_idx = rte_cpu_to_le_16(index);
3092         req.offset = rte_cpu_to_le_32(offset);
3093         req.len = rte_cpu_to_le_32(length);
3094         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
3095         HWRM_CHECK_RESULT();
3096         HWRM_UNLOCK();
3097         if (rc == 0)
3098                 memcpy(data, buf, length);
3099
3100         rte_free(buf);
3101         return rc;
3102 }
3103
3104 int bnxt_hwrm_erase_nvram_directory(struct bnxt *bp, uint8_t index)
3105 {
3106         int rc;
3107         struct hwrm_nvm_erase_dir_entry_input req = {0};
3108         struct hwrm_nvm_erase_dir_entry_output *resp = bp->hwrm_cmd_resp_addr;
3109
3110         HWRM_PREP(req, NVM_ERASE_DIR_ENTRY);
3111         req.dir_idx = rte_cpu_to_le_16(index);
3112         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
3113         HWRM_CHECK_RESULT();
3114         HWRM_UNLOCK();
3115
3116         return rc;
3117 }
3118
3119
3120 int bnxt_hwrm_flash_nvram(struct bnxt *bp, uint16_t dir_type,
3121                           uint16_t dir_ordinal, uint16_t dir_ext,
3122                           uint16_t dir_attr, const uint8_t *data,
3123                           size_t data_len)
3124 {
3125         int rc;
3126         struct hwrm_nvm_write_input req = {0};
3127         struct hwrm_nvm_write_output *resp = bp->hwrm_cmd_resp_addr;
3128         rte_iova_t dma_handle;
3129         uint8_t *buf;
3130
3131         HWRM_PREP(req, NVM_WRITE);
3132
3133         req.dir_type = rte_cpu_to_le_16(dir_type);
3134         req.dir_ordinal = rte_cpu_to_le_16(dir_ordinal);
3135         req.dir_ext = rte_cpu_to_le_16(dir_ext);
3136         req.dir_attr = rte_cpu_to_le_16(dir_attr);
3137         req.dir_data_length = rte_cpu_to_le_32(data_len);
3138
3139         buf = rte_malloc("nvm_write", data_len, 0);
3140         rte_mem_lock_page(buf);
3141         if (!buf)
3142                 return -ENOMEM;
3143
3144         dma_handle = rte_mem_virt2iova(buf);
3145         if (dma_handle == 0) {
3146                 RTE_LOG(ERR, PMD,
3147                         "unable to map response address to physical memory\n");
3148                 return -ENOMEM;
3149         }
3150         memcpy(buf, data, data_len);
3151         req.host_src_addr = rte_cpu_to_le_64(dma_handle);
3152
3153         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
3154
3155         HWRM_CHECK_RESULT();
3156         HWRM_UNLOCK();
3157
3158         rte_free(buf);
3159         return rc;
3160 }
3161
3162 static void
3163 bnxt_vnic_count(struct bnxt_vnic_info *vnic __rte_unused, void *cbdata)
3164 {
3165         uint32_t *count = cbdata;
3166
3167         *count = *count + 1;
3168 }
3169
3170 static int bnxt_vnic_count_hwrm_stub(struct bnxt *bp __rte_unused,
3171                                      struct bnxt_vnic_info *vnic __rte_unused)
3172 {
3173         return 0;
3174 }
3175
3176 int bnxt_vf_vnic_count(struct bnxt *bp, uint16_t vf)
3177 {
3178         uint32_t count = 0;
3179
3180         bnxt_hwrm_func_vf_vnic_query_and_config(bp, vf, bnxt_vnic_count,
3181             &count, bnxt_vnic_count_hwrm_stub);
3182
3183         return count;
3184 }
3185
3186 static int bnxt_hwrm_func_vf_vnic_query(struct bnxt *bp, uint16_t vf,
3187                                         uint16_t *vnic_ids)
3188 {
3189         struct hwrm_func_vf_vnic_ids_query_input req = {0};
3190         struct hwrm_func_vf_vnic_ids_query_output *resp =
3191                                                 bp->hwrm_cmd_resp_addr;
3192         int rc;
3193
3194         /* First query all VNIC ids */
3195         HWRM_PREP(req, FUNC_VF_VNIC_IDS_QUERY);
3196
3197         req.vf_id = rte_cpu_to_le_16(bp->pf.first_vf_id + vf);
3198         req.max_vnic_id_cnt = rte_cpu_to_le_32(bp->pf.total_vnics);
3199         req.vnic_id_tbl_addr = rte_cpu_to_le_64(rte_mem_virt2iova(vnic_ids));
3200
3201         if (req.vnic_id_tbl_addr == 0) {
3202                 HWRM_UNLOCK();
3203                 RTE_LOG(ERR, PMD,
3204                 "unable to map VNIC ID table address to physical memory\n");
3205                 return -ENOMEM;
3206         }
3207         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
3208         if (rc) {
3209                 HWRM_UNLOCK();
3210                 RTE_LOG(ERR, PMD, "hwrm_func_vf_vnic_query failed rc:%d\n", rc);
3211                 return -1;
3212         } else if (resp->error_code) {
3213                 rc = rte_le_to_cpu_16(resp->error_code);
3214                 HWRM_UNLOCK();
3215                 RTE_LOG(ERR, PMD, "hwrm_func_vf_vnic_query error %d\n", rc);
3216                 return -1;
3217         }
3218         rc = rte_le_to_cpu_32(resp->vnic_id_cnt);
3219
3220         HWRM_UNLOCK();
3221
3222         return rc;
3223 }
3224
3225 /*
3226  * This function queries the VNIC IDs  for a specified VF. It then calls
3227  * the vnic_cb to update the necessary field in vnic_info with cbdata.
3228  * Then it calls the hwrm_cb function to program this new vnic configuration.
3229  */
3230 int bnxt_hwrm_func_vf_vnic_query_and_config(struct bnxt *bp, uint16_t vf,
3231         void (*vnic_cb)(struct bnxt_vnic_info *, void *), void *cbdata,
3232         int (*hwrm_cb)(struct bnxt *bp, struct bnxt_vnic_info *vnic))
3233 {
3234         struct bnxt_vnic_info vnic;
3235         int rc = 0;
3236         int i, num_vnic_ids;
3237         uint16_t *vnic_ids;
3238         size_t vnic_id_sz;
3239         size_t sz;
3240
3241         /* First query all VNIC ids */
3242         vnic_id_sz = bp->pf.total_vnics * sizeof(*vnic_ids);
3243         vnic_ids = rte_malloc("bnxt_hwrm_vf_vnic_ids_query", vnic_id_sz,
3244                         RTE_CACHE_LINE_SIZE);
3245         if (vnic_ids == NULL) {
3246                 rc = -ENOMEM;
3247                 return rc;
3248         }
3249         for (sz = 0; sz < vnic_id_sz; sz += getpagesize())
3250                 rte_mem_lock_page(((char *)vnic_ids) + sz);
3251
3252         num_vnic_ids = bnxt_hwrm_func_vf_vnic_query(bp, vf, vnic_ids);
3253
3254         if (num_vnic_ids < 0)
3255                 return num_vnic_ids;
3256
3257         /* Retrieve VNIC, update bd_stall then update */
3258
3259         for (i = 0; i < num_vnic_ids; i++) {
3260                 memset(&vnic, 0, sizeof(struct bnxt_vnic_info));
3261                 vnic.fw_vnic_id = rte_le_to_cpu_16(vnic_ids[i]);
3262                 rc = bnxt_hwrm_vnic_qcfg(bp, &vnic, bp->pf.first_vf_id + vf);
3263                 if (rc)
3264                         break;
3265                 if (vnic.mru <= 4)      /* Indicates unallocated */
3266                         continue;
3267
3268                 vnic_cb(&vnic, cbdata);
3269
3270                 rc = hwrm_cb(bp, &vnic);
3271                 if (rc)
3272                         break;
3273         }
3274
3275         rte_free(vnic_ids);
3276
3277         return rc;
3278 }
3279
3280 int bnxt_hwrm_func_cfg_vf_set_vlan_anti_spoof(struct bnxt *bp, uint16_t vf,
3281                                               bool on)
3282 {
3283         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3284         struct hwrm_func_cfg_input req = {0};
3285         int rc;
3286
3287         HWRM_PREP(req, FUNC_CFG);
3288
3289         req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
3290         req.enables |= rte_cpu_to_le_32(
3291                         HWRM_FUNC_CFG_INPUT_ENABLES_VLAN_ANTISPOOF_MODE);
3292         req.vlan_antispoof_mode = on ?
3293                 HWRM_FUNC_CFG_INPUT_VLAN_ANTISPOOF_MODE_VALIDATE_VLAN :
3294                 HWRM_FUNC_CFG_INPUT_VLAN_ANTISPOOF_MODE_NOCHECK;
3295         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
3296
3297         HWRM_CHECK_RESULT();
3298         HWRM_UNLOCK();
3299
3300         return rc;
3301 }
3302
3303 int bnxt_hwrm_func_qcfg_vf_dflt_vnic_id(struct bnxt *bp, int vf)
3304 {
3305         struct bnxt_vnic_info vnic;
3306         uint16_t *vnic_ids;
3307         size_t vnic_id_sz;
3308         int num_vnic_ids, i;
3309         size_t sz;
3310         int rc;
3311
3312         vnic_id_sz = bp->pf.total_vnics * sizeof(*vnic_ids);
3313         vnic_ids = rte_malloc("bnxt_hwrm_vf_vnic_ids_query", vnic_id_sz,
3314                         RTE_CACHE_LINE_SIZE);
3315         if (vnic_ids == NULL) {
3316                 rc = -ENOMEM;
3317                 return rc;
3318         }
3319
3320         for (sz = 0; sz < vnic_id_sz; sz += getpagesize())
3321                 rte_mem_lock_page(((char *)vnic_ids) + sz);
3322
3323         rc = bnxt_hwrm_func_vf_vnic_query(bp, vf, vnic_ids);
3324         if (rc <= 0)
3325                 goto exit;
3326         num_vnic_ids = rc;
3327
3328         /*
3329          * Loop through to find the default VNIC ID.
3330          * TODO: The easier way would be to obtain the resp->dflt_vnic_id
3331          * by sending the hwrm_func_qcfg command to the firmware.
3332          */
3333         for (i = 0; i < num_vnic_ids; i++) {
3334                 memset(&vnic, 0, sizeof(struct bnxt_vnic_info));
3335                 vnic.fw_vnic_id = rte_le_to_cpu_16(vnic_ids[i]);
3336                 rc = bnxt_hwrm_vnic_qcfg(bp, &vnic,
3337                                         bp->pf.first_vf_id + vf);
3338                 if (rc)
3339                         goto exit;
3340                 if (vnic.func_default) {
3341                         rte_free(vnic_ids);
3342                         return vnic.fw_vnic_id;
3343                 }
3344         }
3345         /* Could not find a default VNIC. */
3346         RTE_LOG(ERR, PMD, "No default VNIC\n");
3347 exit:
3348         rte_free(vnic_ids);
3349         return -1;
3350 }
3351
3352 int bnxt_hwrm_set_em_filter(struct bnxt *bp,
3353                          uint16_t dst_id,
3354                          struct bnxt_filter_info *filter)
3355 {
3356         int rc = 0;
3357         struct hwrm_cfa_em_flow_alloc_input req = {.req_type = 0 };
3358         struct hwrm_cfa_em_flow_alloc_output *resp = bp->hwrm_cmd_resp_addr;
3359         uint32_t enables = 0;
3360
3361         if (filter->fw_em_filter_id != UINT64_MAX)
3362                 bnxt_hwrm_clear_em_filter(bp, filter);
3363
3364         HWRM_PREP(req, CFA_EM_FLOW_ALLOC);
3365
3366         req.flags = rte_cpu_to_le_32(filter->flags);
3367
3368         enables = filter->enables |
3369               HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_ID;
3370         req.dst_id = rte_cpu_to_le_16(dst_id);
3371
3372         if (filter->ip_addr_type) {
3373                 req.ip_addr_type = filter->ip_addr_type;
3374                 enables |= HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IPADDR_TYPE;
3375         }
3376         if (enables &
3377             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_L2_FILTER_ID)
3378                 req.l2_filter_id = rte_cpu_to_le_64(filter->fw_l2_filter_id);
3379         if (enables &
3380             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_MACADDR)
3381                 memcpy(req.src_macaddr, filter->src_macaddr,
3382                        ETHER_ADDR_LEN);
3383         if (enables &
3384             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_MACADDR)
3385                 memcpy(req.dst_macaddr, filter->dst_macaddr,
3386                        ETHER_ADDR_LEN);
3387         if (enables &
3388             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_OVLAN_VID)
3389                 req.ovlan_vid = filter->l2_ovlan;
3390         if (enables &
3391             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IVLAN_VID)
3392                 req.ivlan_vid = filter->l2_ivlan;
3393         if (enables &
3394             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_ETHERTYPE)
3395                 req.ethertype = rte_cpu_to_be_16(filter->ethertype);
3396         if (enables &
3397             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IP_PROTOCOL)
3398                 req.ip_protocol = filter->ip_protocol;
3399         if (enables &
3400             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_IPADDR)
3401                 req.src_ipaddr[0] = rte_cpu_to_be_32(filter->src_ipaddr[0]);
3402         if (enables &
3403             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_IPADDR)
3404                 req.dst_ipaddr[0] = rte_cpu_to_be_32(filter->dst_ipaddr[0]);
3405         if (enables &
3406             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_PORT)
3407                 req.src_port = rte_cpu_to_be_16(filter->src_port);
3408         if (enables &
3409             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_PORT)
3410                 req.dst_port = rte_cpu_to_be_16(filter->dst_port);
3411         if (enables &
3412             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID)
3413                 req.mirror_vnic_id = filter->mirror_vnic_id;
3414
3415         req.enables = rte_cpu_to_le_32(enables);
3416
3417         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
3418
3419         HWRM_CHECK_RESULT();
3420
3421         filter->fw_em_filter_id = rte_le_to_cpu_64(resp->em_filter_id);
3422         HWRM_UNLOCK();
3423
3424         return rc;
3425 }
3426
3427 int bnxt_hwrm_clear_em_filter(struct bnxt *bp, struct bnxt_filter_info *filter)
3428 {
3429         int rc = 0;
3430         struct hwrm_cfa_em_flow_free_input req = {.req_type = 0 };
3431         struct hwrm_cfa_em_flow_free_output *resp = bp->hwrm_cmd_resp_addr;
3432
3433         if (filter->fw_em_filter_id == UINT64_MAX)
3434                 return 0;
3435
3436         RTE_LOG(ERR, PMD, "Clear EM filter\n");
3437         HWRM_PREP(req, CFA_EM_FLOW_FREE);
3438
3439         req.em_filter_id = rte_cpu_to_le_64(filter->fw_em_filter_id);
3440
3441         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
3442
3443         HWRM_CHECK_RESULT();
3444         HWRM_UNLOCK();
3445
3446         filter->fw_em_filter_id = -1;
3447         filter->fw_l2_filter_id = -1;
3448
3449         return 0;
3450 }
3451
3452 int bnxt_hwrm_set_ntuple_filter(struct bnxt *bp,
3453                          uint16_t dst_id,
3454                          struct bnxt_filter_info *filter)
3455 {
3456         int rc = 0;
3457         struct hwrm_cfa_ntuple_filter_alloc_input req = {.req_type = 0 };
3458         struct hwrm_cfa_ntuple_filter_alloc_output *resp =
3459                                                 bp->hwrm_cmd_resp_addr;
3460         uint32_t enables = 0;
3461
3462         if (filter->fw_ntuple_filter_id != UINT64_MAX)
3463                 bnxt_hwrm_clear_ntuple_filter(bp, filter);
3464
3465         HWRM_PREP(req, CFA_NTUPLE_FILTER_ALLOC);
3466
3467         req.flags = rte_cpu_to_le_32(filter->flags);
3468
3469         enables = filter->enables |
3470               HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_ID;
3471         req.dst_id = rte_cpu_to_le_16(dst_id);
3472
3473
3474         if (filter->ip_addr_type) {
3475                 req.ip_addr_type = filter->ip_addr_type;
3476                 enables |=
3477                         HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_IPADDR_TYPE;
3478         }
3479         if (enables &
3480             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID)
3481                 req.l2_filter_id = rte_cpu_to_le_64(filter->fw_l2_filter_id);
3482         if (enables &
3483             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_MACADDR)
3484                 memcpy(req.src_macaddr, filter->src_macaddr,
3485                        ETHER_ADDR_LEN);
3486         //if (enables &
3487             //HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_MACADDR)
3488                 //memcpy(req.dst_macaddr, filter->dst_macaddr,
3489                        //ETHER_ADDR_LEN);
3490         if (enables &
3491             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_ETHERTYPE)
3492                 req.ethertype = rte_cpu_to_be_16(filter->ethertype);
3493         if (enables &
3494             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_IP_PROTOCOL)
3495                 req.ip_protocol = filter->ip_protocol;
3496         if (enables &
3497             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_IPADDR)
3498                 req.src_ipaddr[0] = rte_cpu_to_le_32(filter->src_ipaddr[0]);
3499         if (enables &
3500             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_IPADDR_MASK)
3501                 req.src_ipaddr_mask[0] =
3502                         rte_cpu_to_le_32(filter->src_ipaddr_mask[0]);
3503         if (enables &
3504             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_IPADDR)
3505                 req.dst_ipaddr[0] = rte_cpu_to_le_32(filter->dst_ipaddr[0]);
3506         if (enables &
3507             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_IPADDR_MASK)
3508                 req.dst_ipaddr_mask[0] =
3509                         rte_cpu_to_be_32(filter->dst_ipaddr_mask[0]);
3510         if (enables &
3511             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_PORT)
3512                 req.src_port = rte_cpu_to_le_16(filter->src_port);
3513         if (enables &
3514             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_PORT_MASK)
3515                 req.src_port_mask = rte_cpu_to_le_16(filter->src_port_mask);
3516         if (enables &
3517             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_PORT)
3518                 req.dst_port = rte_cpu_to_le_16(filter->dst_port);
3519         if (enables &
3520             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_PORT_MASK)
3521                 req.dst_port_mask = rte_cpu_to_le_16(filter->dst_port_mask);
3522         if (enables &
3523             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID)
3524                 req.mirror_vnic_id = filter->mirror_vnic_id;
3525
3526         req.enables = rte_cpu_to_le_32(enables);
3527
3528         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
3529
3530         HWRM_CHECK_RESULT();
3531
3532         filter->fw_ntuple_filter_id = rte_le_to_cpu_64(resp->ntuple_filter_id);
3533         HWRM_UNLOCK();
3534
3535         return rc;
3536 }
3537
3538 int bnxt_hwrm_clear_ntuple_filter(struct bnxt *bp,
3539                                 struct bnxt_filter_info *filter)
3540 {
3541         int rc = 0;
3542         struct hwrm_cfa_ntuple_filter_free_input req = {.req_type = 0 };
3543         struct hwrm_cfa_ntuple_filter_free_output *resp =
3544                                                 bp->hwrm_cmd_resp_addr;
3545
3546         if (filter->fw_ntuple_filter_id == UINT64_MAX)
3547                 return 0;
3548
3549         HWRM_PREP(req, CFA_NTUPLE_FILTER_FREE);
3550
3551         req.ntuple_filter_id = rte_cpu_to_le_64(filter->fw_ntuple_filter_id);
3552
3553         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
3554
3555         HWRM_CHECK_RESULT();
3556         HWRM_UNLOCK();
3557
3558         filter->fw_ntuple_filter_id = -1;
3559         filter->fw_l2_filter_id = -1;
3560
3561         return 0;
3562 }