drivers/net/bnxt/bnxt_hwrm.c

   1 /*-
   2  *   BSD LICENSE
   3  *
   4  *   Copyright(c) Broadcom Limited.
   5  *   All rights reserved.
   6  *
   7  *   Redistribution and use in source and binary forms, with or without
   8  *   modification, are permitted provided that the following conditions
   9  *   are met:
  10  *
  11  *     * Redistributions of source code must retain the above copyright
  12  *       notice, this list of conditions and the following disclaimer.
  13  *     * Redistributions in binary form must reproduce the above copyright
  14  *       notice, this list of conditions and the following disclaimer in
  15  *       the documentation and/or other materials provided with the
  16  *       distribution.
  17  *     * Neither the name of Broadcom Corporation nor the names of its
  18  *       contributors may be used to endorse or promote products derived
  19  *       from this software without specific prior written permission.
  20  *
  21  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 #include <unistd.h>
  35
  36 #include <rte_byteorder.h>
  37 #include <rte_common.h>
  38 #include <rte_cycles.h>
  39 #include <rte_malloc.h>
  40 #include <rte_memzone.h>
  41 #include <rte_version.h>
  42
  43 #include "bnxt.h"
  44 #include "bnxt_cpr.h"
  45 #include "bnxt_filter.h"
  46 #include "bnxt_hwrm.h"
  47 #include "bnxt_rxq.h"
  48 #include "bnxt_rxr.h"
  49 #include "bnxt_ring.h"
  50 #include "bnxt_txq.h"
  51 #include "bnxt_txr.h"
  52 #include "bnxt_vnic.h"
  53 #include "hsi_struct_def_dpdk.h"
  54
  55 #include <rte_io.h>
  56
  57 #define HWRM_CMD_TIMEOUT                10000
  58
  59 struct bnxt_plcmodes_cfg {
  60         uint32_t        flags;
  61         uint16_t        jumbo_thresh;
  62         uint16_t        hds_offset;
  63         uint16_t        hds_threshold;
  64 };
  65
  66 static int page_getenum(size_t size)
  67 {
  68         if (size <= 1 << 4)
  69                 return 4;
  70         if (size <= 1 << 12)
  71                 return 12;
  72         if (size <= 1 << 13)
  73                 return 13;
  74         if (size <= 1 << 16)
  75                 return 16;
  76         if (size <= 1 << 21)
  77                 return 21;
  78         if (size <= 1 << 22)
  79                 return 22;
  80         if (size <= 1 << 30)
  81                 return 30;
  82         RTE_LOG(ERR, PMD, "Page size %zu out of range\n", size);
  83         return sizeof(void *) * 8 - 1;
  84 }
  85
  86 static int page_roundup(size_t size)
  87 {
  88         return 1 << page_getenum(size);
  89 }
  90
  91 /*
  92  * HWRM Functions (sent to HWRM)
  93  * These are named bnxt_hwrm_*() and return -1 if bnxt_hwrm_send_message()
  94  * fails (ie: a timeout), and a positive non-zero HWRM error code if the HWRM
  95  * command was failed by the ChiMP.
  96  */
  97
  98 static int bnxt_hwrm_send_message(struct bnxt *bp, void *msg,
  99                                         uint32_t msg_len)
 100 {
 101         unsigned int i;
 102         struct input *req = msg;
 103         struct output *resp = bp->hwrm_cmd_resp_addr;
 104         uint32_t *data = msg;
 105         uint8_t *bar;
 106         uint8_t *valid;
 107         uint16_t max_req_len = bp->max_req_len;
 108         struct hwrm_short_input short_input = { 0 };
 109
 110         if (bp->flags & BNXT_FLAG_SHORT_CMD) {
 111                 void *short_cmd_req = bp->hwrm_short_cmd_req_addr;
 112
 113                 memset(short_cmd_req, 0, bp->max_req_len);
 114                 memcpy(short_cmd_req, req, msg_len);
 115
 116                 short_input.req_type = rte_cpu_to_le_16(req->req_type);
 117                 short_input.signature = rte_cpu_to_le_16(
 118                                         HWRM_SHORT_REQ_SIGNATURE_SHORT_CMD);
 119                 short_input.size = rte_cpu_to_le_16(msg_len);
 120                 short_input.req_addr =
 121                         rte_cpu_to_le_64(bp->hwrm_short_cmd_req_dma_addr);
 122
 123                 data = (uint32_t *)&short_input;
 124                 msg_len = sizeof(short_input);
 125
 126                 /* Sync memory write before updating doorbell */
 127                 rte_wmb();
 128
 129                 max_req_len = BNXT_HWRM_SHORT_REQ_LEN;
 130         }
 131
 132         /* Write request msg to hwrm channel */
 133         for (i = 0; i < msg_len; i += 4) {
 134                 bar = (uint8_t *)bp->bar0 + i;
 135                 rte_write32(*data, bar);
 136                 data++;
 137         }
 138
 139         /* Zero the rest of the request space */
 140         for (; i < max_req_len; i += 4) {
 141                 bar = (uint8_t *)bp->bar0 + i;
 142                 rte_write32(0, bar);
 143         }
 144
 145         /* Ring channel doorbell */
 146         bar = (uint8_t *)bp->bar0 + 0x100;
 147         rte_write32(1, bar);
 148
 149         /* Poll for the valid bit */
 150         for (i = 0; i < HWRM_CMD_TIMEOUT; i++) {
 151                 /* Sanity check on the resp->resp_len */
 152                 rte_rmb();
 153                 if (resp->resp_len && resp->resp_len <=
 154                                 bp->max_resp_len) {
 155                         /* Last byte of resp contains the valid key */
 156                         valid = (uint8_t *)resp + resp->resp_len - 1;
 157                         if (*valid == HWRM_RESP_VALID_KEY)
 158                                 break;
 159                 }
 160                 rte_delay_us(600);
 161         }
 162
 163         if (i >= HWRM_CMD_TIMEOUT) {
 164                 RTE_LOG(ERR, PMD, "Error sending msg 0x%04x\n",
 165                         req->req_type);
 166                 goto err_ret;
 167         }
 168         return 0;
 169
 170 err_ret:
 171         return -1;
 172 }
 173
 174 /*
 175  * HWRM_PREP() should be used to prepare *ALL* HWRM commands.  It grabs the
 176  * spinlock, and does initial processing.
 177  *
 178  * HWRM_CHECK_RESULT() returns errors on failure and may not be used.  It
 179  * releases the spinlock only if it returns.  If the regular int return codes
 180  * are not used by the function, HWRM_CHECK_RESULT() should not be used
 181  * directly, rather it should be copied and modified to suit the function.
 182  *
 183  * HWRM_UNLOCK() must be called after all response processing is completed.
 184  */
 185 #define HWRM_PREP(req, type) do { \
 186         rte_spinlock_lock(&bp->hwrm_lock); \
 187         memset(bp->hwrm_cmd_resp_addr, 0, bp->max_resp_len); \
 188         req.req_type = rte_cpu_to_le_16(HWRM_##type); \
 189         req.cmpl_ring = rte_cpu_to_le_16(-1); \
 190         req.seq_id = rte_cpu_to_le_16(bp->hwrm_cmd_seq++); \
 191         req.target_id = rte_cpu_to_le_16(0xffff); \
 192         req.resp_addr = rte_cpu_to_le_64(bp->hwrm_cmd_resp_dma_addr); \
 193 } while (0)
 194
 195 #define HWRM_CHECK_RESULT() do {\
 196         if (rc) { \
 197                 RTE_LOG(ERR, PMD, "%s failed rc:%d\n", \
 198                         __func__, rc); \
 199                 rte_spinlock_unlock(&bp->hwrm_lock); \
 200                 return rc; \
 201         } \
 202         if (resp->error_code) { \
 203                 rc = rte_le_to_cpu_16(resp->error_code); \
 204                 if (resp->resp_len >= 16) { \
 205                         struct hwrm_err_output *tmp_hwrm_err_op = \
 206                                                 (void *)resp; \
 207                         RTE_LOG(ERR, PMD, \
 208                                 "%s error %d:%d:%08x:%04x\n", \
 209                                 __func__, \
 210                                 rc, tmp_hwrm_err_op->cmd_err, \
 211                                 rte_le_to_cpu_32(\
 212                                         tmp_hwrm_err_op->opaque_0), \
 213                                 rte_le_to_cpu_16(\
 214                                         tmp_hwrm_err_op->opaque_1)); \
 215                 } \
 216                 else { \
 217                         RTE_LOG(ERR, PMD, \
 218                                 "%s error %d\n", __func__, rc); \
 219                 } \
 220                 rte_spinlock_unlock(&bp->hwrm_lock); \
 221                 return rc; \
 222         } \
 223 } while (0)
 224
 225 #define HWRM_UNLOCK()           rte_spinlock_unlock(&bp->hwrm_lock)
 226
 227 int bnxt_hwrm_cfa_l2_clear_rx_mask(struct bnxt *bp, struct bnxt_vnic_info *vnic)
 228 {
 229         int rc = 0;
 230         struct hwrm_cfa_l2_set_rx_mask_input req = {.req_type = 0 };
 231         struct hwrm_cfa_l2_set_rx_mask_output *resp = bp->hwrm_cmd_resp_addr;
 232
 233         HWRM_PREP(req, CFA_L2_SET_RX_MASK);
 234         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
 235         req.mask = 0;
 236
 237         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
 238
 239         HWRM_CHECK_RESULT();
 240         HWRM_UNLOCK();
 241
 242         return rc;
 243 }
 244
 245 int bnxt_hwrm_cfa_l2_set_rx_mask(struct bnxt *bp,
 246                                  struct bnxt_vnic_info *vnic,
 247                                  uint16_t vlan_count,
 248                                  struct bnxt_vlan_table_entry *vlan_table)
 249 {
 250         int rc = 0;
 251         struct hwrm_cfa_l2_set_rx_mask_input req = {.req_type = 0 };
 252         struct hwrm_cfa_l2_set_rx_mask_output *resp = bp->hwrm_cmd_resp_addr;
 253         uint32_t mask = 0;
 254
 255         HWRM_PREP(req, CFA_L2_SET_RX_MASK);
 256         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
 257
 258         /* FIXME add multicast flag, when multicast adding options is supported
 259          * by ethtool.
 260          */
 261         if (vnic->flags & BNXT_VNIC_INFO_BCAST)
 262                 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_BCAST;
 263         if (vnic->flags & BNXT_VNIC_INFO_UNTAGGED)
 264                 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_VLAN_NONVLAN;
 265         if (vnic->flags & BNXT_VNIC_INFO_PROMISC)
 266                 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_PROMISCUOUS;
 267         if (vnic->flags & BNXT_VNIC_INFO_ALLMULTI)
 268                 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_ALL_MCAST;
 269         if (vnic->flags & BNXT_VNIC_INFO_MCAST)
 270                 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_MCAST;
 271         if (vnic->mc_addr_cnt) {
 272                 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_MCAST;
 273                 req.num_mc_entries = rte_cpu_to_le_32(vnic->mc_addr_cnt);
 274                 req.mc_tbl_addr = rte_cpu_to_le_64(vnic->mc_list_dma_addr);
 275         }
 276         if (vlan_table) {
 277                 if (!(mask & HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_VLAN_NONVLAN))
 278                         mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_VLANONLY;
 279                 req.vlan_tag_tbl_addr = rte_cpu_to_le_64(
 280                          rte_mem_virt2iova(vlan_table));
 281                 req.num_vlan_tags = rte_cpu_to_le_32((uint32_t)vlan_count);
 282         }
 283         req.mask = rte_cpu_to_le_32(mask);
 284
 285         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
 286
 287         HWRM_CHECK_RESULT();
 288         HWRM_UNLOCK();
 289
 290         return rc;
 291 }
 292
 293 int bnxt_hwrm_cfa_vlan_antispoof_cfg(struct bnxt *bp, uint16_t fid,
 294                         uint16_t vlan_count,
 295                         struct bnxt_vlan_antispoof_table_entry *vlan_table)
 296 {
 297         int rc = 0;
 298         struct hwrm_cfa_vlan_antispoof_cfg_input req = {.req_type = 0 };
 299         struct hwrm_cfa_vlan_antispoof_cfg_output *resp =
 300                                                 bp->hwrm_cmd_resp_addr;
 301
 302         /*
 303          * Older HWRM versions did not support this command, and the set_rx_mask
 304          * list was used for anti-spoof. In 1.8.0, the TX path configuration was
 305          * removed from set_rx_mask call, and this command was added.
 306          *
 307          * This command is also present from 1.7.8.11 and higher,
 308          * as well as 1.7.8.0
 309          */
 310         if (bp->fw_ver < ((1 << 24) | (8 << 16))) {
 311                 if (bp->fw_ver != ((1 << 24) | (7 << 16) | (8 << 8))) {
 312                         if (bp->fw_ver < ((1 << 24) | (7 << 16) | (8 << 8) |
 313                                         (11)))
 314                                 return 0;
 315                 }
 316         }
 317         HWRM_PREP(req, CFA_VLAN_ANTISPOOF_CFG);
 318         req.fid = rte_cpu_to_le_16(fid);
 319
 320         req.vlan_tag_mask_tbl_addr =
 321                 rte_cpu_to_le_64(rte_mem_virt2iova(vlan_table));
 322         req.num_vlan_entries = rte_cpu_to_le_32((uint32_t)vlan_count);
 323
 324         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
 325
 326         HWRM_CHECK_RESULT();
 327         HWRM_UNLOCK();
 328
 329         return rc;
 330 }
 331
 332 int bnxt_hwrm_clear_l2_filter(struct bnxt *bp,
 333                            struct bnxt_filter_info *filter)
 334 {
 335         int rc = 0;
 336         struct hwrm_cfa_l2_filter_free_input req = {.req_type = 0 };
 337         struct hwrm_cfa_l2_filter_free_output *resp = bp->hwrm_cmd_resp_addr;
 338
 339         if (filter->fw_l2_filter_id == UINT64_MAX)
 340                 return 0;
 341
 342         HWRM_PREP(req, CFA_L2_FILTER_FREE);
 343
 344         req.l2_filter_id = rte_cpu_to_le_64(filter->fw_l2_filter_id);
 345
 346         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
 347
 348         HWRM_CHECK_RESULT();
 349         HWRM_UNLOCK();
 350
 351         filter->fw_l2_filter_id = -1;
 352
 353         return 0;
 354 }
 355
 356 int bnxt_hwrm_set_l2_filter(struct bnxt *bp,
 357                          uint16_t dst_id,
 358                          struct bnxt_filter_info *filter)
 359 {
 360         int rc = 0;
 361         struct hwrm_cfa_l2_filter_alloc_input req = {.req_type = 0 };
 362         struct hwrm_cfa_l2_filter_alloc_output *resp = bp->hwrm_cmd_resp_addr;
 363         struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
 364         const struct rte_eth_vmdq_rx_conf *conf =
 365                     &dev_conf->rx_adv_conf.vmdq_rx_conf;
 366         uint32_t enables = 0;
 367         uint16_t j = dst_id - 1;
 368
 369         //TODO: Is there a better way to add VLANs to each VNIC in case of VMDQ
 370         if ((dev_conf->rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG) &&
 371             conf->pool_map[j].pools & (1UL << j)) {
 372                 RTE_LOG(DEBUG, PMD,
 373                         "Add vlan %u to vmdq pool %u\n",
 374                         conf->pool_map[j].vlan_id, j);
 375
 376                 filter->l2_ivlan = conf->pool_map[j].vlan_id;
 377                 filter->enables |=
 378                         HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN |
 379                         HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN_MASK;
 380         }
 381
 382         if (filter->fw_l2_filter_id != UINT64_MAX)
 383                 bnxt_hwrm_clear_l2_filter(bp, filter);
 384
 385         HWRM_PREP(req, CFA_L2_FILTER_ALLOC);
 386
 387         req.flags = rte_cpu_to_le_32(filter->flags);
 388
 389         enables = filter->enables |
 390               HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_DST_ID;
 391         req.dst_id = rte_cpu_to_le_16(dst_id);
 392
 393         if (enables &
 394             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR)
 395                 memcpy(req.l2_addr, filter->l2_addr,
 396                        ETHER_ADDR_LEN);
 397         if (enables &
 398             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR_MASK)
 399                 memcpy(req.l2_addr_mask, filter->l2_addr_mask,
 400                        ETHER_ADDR_LEN);
 401         if (enables &
 402             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN)
 403                 req.l2_ovlan = filter->l2_ovlan;
 404         if (enables &
 405             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN)
 406                 req.l2_ovlan = filter->l2_ivlan;
 407         if (enables &
 408             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN_MASK)
 409                 req.l2_ovlan_mask = filter->l2_ovlan_mask;
 410         if (enables &
 411             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN_MASK)
 412                 req.l2_ovlan_mask = filter->l2_ivlan_mask;
 413         if (enables & HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_SRC_ID)
 414                 req.src_id = rte_cpu_to_le_32(filter->src_id);
 415         if (enables & HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_SRC_TYPE)
 416                 req.src_type = filter->src_type;
 417
 418         req.enables = rte_cpu_to_le_32(enables);
 419
 420         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
 421
 422         HWRM_CHECK_RESULT();
 423
 424         filter->fw_l2_filter_id = rte_le_to_cpu_64(resp->l2_filter_id);
 425         HWRM_UNLOCK();
 426
 427         return rc;
 428 }
 429
 430 int bnxt_hwrm_func_qcaps(struct bnxt *bp)
 431 {
 432         int rc = 0;
 433         struct hwrm_func_qcaps_input req = {.req_type = 0 };
 434         struct hwrm_func_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
 435         uint16_t new_max_vfs;
 436         int i;
 437
 438         HWRM_PREP(req, FUNC_QCAPS);
 439
 440         req.fid = rte_cpu_to_le_16(0xffff);
 441
 442         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
 443
 444         HWRM_CHECK_RESULT();
 445
 446         bp->max_ring_grps = rte_le_to_cpu_32(resp->max_hw_ring_grps);
 447         if (BNXT_PF(bp)) {
 448                 bp->pf.port_id = resp->port_id;
 449                 bp->pf.first_vf_id = rte_le_to_cpu_16(resp->first_vf_id);
 450                 new_max_vfs = bp->pdev->max_vfs;
 451                 if (new_max_vfs != bp->pf.max_vfs) {
 452                         if (bp->pf.vf_info)
 453                                 rte_free(bp->pf.vf_info);
 454                         bp->pf.vf_info = rte_malloc("bnxt_vf_info",
 455                             sizeof(bp->pf.vf_info[0]) * new_max_vfs, 0);
 456                         bp->pf.max_vfs = new_max_vfs;
 457                         for (i = 0; i < new_max_vfs; i++) {
 458                                 bp->pf.vf_info[i].fid = bp->pf.first_vf_id + i;
 459                                 bp->pf.vf_info[i].vlan_table =
 460                                         rte_zmalloc("VF VLAN table",
 461                                                     getpagesize(),
 462                                                     getpagesize());
 463                                 if (bp->pf.vf_info[i].vlan_table == NULL)
 464                                         RTE_LOG(ERR, PMD,
 465                                         "Fail to alloc VLAN table for VF %d\n",
 466                                         i);
 467                                 else
 468                                         rte_mem_lock_page(
 469                                                 bp->pf.vf_info[i].vlan_table);
 470                                 bp->pf.vf_info[i].vlan_as_table =
 471                                         rte_zmalloc("VF VLAN AS table",
 472                                                     getpagesize(),
 473                                                     getpagesize());
 474                                 if (bp->pf.vf_info[i].vlan_as_table == NULL)
 475                                         RTE_LOG(ERR, PMD,
 476                                         "Alloc VLAN AS table for VF %d fail\n",
 477                                         i);
 478                                 else
 479                                         rte_mem_lock_page(
 480                                                bp->pf.vf_info[i].vlan_as_table);
 481                                 STAILQ_INIT(&bp->pf.vf_info[i].filter);
 482                         }
 483                 }
 484         }
 485
 486         bp->fw_fid = rte_le_to_cpu_32(resp->fid);
 487         memcpy(bp->dflt_mac_addr, &resp->mac_address, ETHER_ADDR_LEN);
 488         bp->max_rsscos_ctx = rte_le_to_cpu_16(resp->max_rsscos_ctx);
 489         bp->max_cp_rings = rte_le_to_cpu_16(resp->max_cmpl_rings);
 490         bp->max_tx_rings = rte_le_to_cpu_16(resp->max_tx_rings);
 491         bp->max_rx_rings = rte_le_to_cpu_16(resp->max_rx_rings);
 492         bp->max_l2_ctx = rte_le_to_cpu_16(resp->max_l2_ctxs);
 493         /* TODO: For now, do not support VMDq/RFS on VFs. */
 494         if (BNXT_PF(bp)) {
 495                 if (bp->pf.max_vfs)
 496                         bp->max_vnics = 1;
 497                 else
 498                         bp->max_vnics = rte_le_to_cpu_16(resp->max_vnics);
 499         } else {
 500                 bp->max_vnics = 1;
 501         }
 502         bp->max_stat_ctx = rte_le_to_cpu_16(resp->max_stat_ctx);
 503         if (BNXT_PF(bp))
 504                 bp->pf.total_vnics = rte_le_to_cpu_16(resp->max_vnics);
 505         HWRM_UNLOCK();
 506
 507         return rc;
 508 }
 509
 510 int bnxt_hwrm_func_reset(struct bnxt *bp)
 511 {
 512         int rc = 0;
 513         struct hwrm_func_reset_input req = {.req_type = 0 };
 514         struct hwrm_func_reset_output *resp = bp->hwrm_cmd_resp_addr;
 515
 516         HWRM_PREP(req, FUNC_RESET);
 517
 518         req.enables = rte_cpu_to_le_32(0);
 519
 520         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
 521
 522         HWRM_CHECK_RESULT();
 523         HWRM_UNLOCK();
 524
 525         return rc;
 526 }
 527
 528 int bnxt_hwrm_func_driver_register(struct bnxt *bp)
 529 {
 530         int rc;
 531         struct hwrm_func_drv_rgtr_input req = {.req_type = 0 };
 532         struct hwrm_func_drv_rgtr_output *resp = bp->hwrm_cmd_resp_addr;
 533
 534         if (bp->flags & BNXT_FLAG_REGISTERED)
 535                 return 0;
 536
 537         HWRM_PREP(req, FUNC_DRV_RGTR);
 538         req.enables = rte_cpu_to_le_32(HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_VER |
 539                         HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_ASYNC_EVENT_FWD);
 540         req.ver_maj = RTE_VER_YEAR;
 541         req.ver_min = RTE_VER_MONTH;
 542         req.ver_upd = RTE_VER_MINOR;
 543
 544         if (BNXT_PF(bp)) {
 545                 req.enables |= rte_cpu_to_le_32(
 546                         HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_VF_INPUT_FWD);
 547                 memcpy(req.vf_req_fwd, bp->pf.vf_req_fwd,
 548                        RTE_MIN(sizeof(req.vf_req_fwd),
 549                                sizeof(bp->pf.vf_req_fwd)));
 550         }
 551
 552         req.async_event_fwd[0] |= rte_cpu_to_le_32(0x1);   /* TODO: Use MACRO */
 553         //memset(req.async_event_fwd, 0xff, sizeof(req.async_event_fwd));
 554
 555         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
 556
 557         HWRM_CHECK_RESULT();
 558         HWRM_UNLOCK();
 559
 560         bp->flags |= BNXT_FLAG_REGISTERED;
 561
 562         return rc;
 563 }
 564
 565 int bnxt_hwrm_ver_get(struct bnxt *bp)
 566 {
 567         int rc = 0;
 568         struct hwrm_ver_get_input req = {.req_type = 0 };
 569         struct hwrm_ver_get_output *resp = bp->hwrm_cmd_resp_addr;
 570         uint32_t my_version;
 571         uint32_t fw_version;
 572         uint16_t max_resp_len;
 573         char type[RTE_MEMZONE_NAMESIZE];
 574         uint32_t dev_caps_cfg;
 575
 576         bp->max_req_len = HWRM_MAX_REQ_LEN;
 577         HWRM_PREP(req, VER_GET);
 578
 579         req.hwrm_intf_maj = HWRM_VERSION_MAJOR;
 580         req.hwrm_intf_min = HWRM_VERSION_MINOR;
 581         req.hwrm_intf_upd = HWRM_VERSION_UPDATE;
 582
 583         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
 584
 585         HWRM_CHECK_RESULT();
 586
 587         RTE_LOG(INFO, PMD, "%d.%d.%d:%d.%d.%d\n",
 588                 resp->hwrm_intf_maj, resp->hwrm_intf_min,
 589                 resp->hwrm_intf_upd,
 590                 resp->hwrm_fw_maj, resp->hwrm_fw_min, resp->hwrm_fw_bld);
 591         bp->fw_ver = (resp->hwrm_fw_maj << 24) | (resp->hwrm_fw_min << 16) |
 592                         (resp->hwrm_fw_bld << 8) | resp->hwrm_fw_rsvd;
 593         RTE_LOG(INFO, PMD, "Driver HWRM version: %d.%d.%d\n",
 594                 HWRM_VERSION_MAJOR, HWRM_VERSION_MINOR, HWRM_VERSION_UPDATE);
 595
 596         my_version = HWRM_VERSION_MAJOR << 16;
 597         my_version |= HWRM_VERSION_MINOR << 8;
 598         my_version |= HWRM_VERSION_UPDATE;
 599
 600         fw_version = resp->hwrm_intf_maj << 16;
 601         fw_version |= resp->hwrm_intf_min << 8;
 602         fw_version |= resp->hwrm_intf_upd;
 603
 604         if (resp->hwrm_intf_maj != HWRM_VERSION_MAJOR) {
 605                 RTE_LOG(ERR, PMD, "Unsupported firmware API version\n");
 606                 rc = -EINVAL;
 607                 goto error;
 608         }
 609
 610         if (my_version != fw_version) {
 611                 RTE_LOG(INFO, PMD, "BNXT Driver/HWRM API mismatch.\n");
 612                 if (my_version < fw_version) {
 613                         RTE_LOG(INFO, PMD,
 614                                 "Firmware API version is newer than driver.\n");
 615                         RTE_LOG(INFO, PMD,
 616                                 "The driver may be missing features.\n");
 617                 } else {
 618                         RTE_LOG(INFO, PMD,
 619                                 "Firmware API version is older than driver.\n");
 620                         RTE_LOG(INFO, PMD,
 621                                 "Not all driver features may be functional.\n");
 622                 }
 623         }
 624
 625         if (bp->max_req_len > resp->max_req_win_len) {
 626                 RTE_LOG(ERR, PMD, "Unsupported request length\n");
 627                 rc = -EINVAL;
 628         }
 629         bp->max_req_len = rte_le_to_cpu_16(resp->max_req_win_len);
 630         max_resp_len = resp->max_resp_len;
 631         dev_caps_cfg = rte_le_to_cpu_32(resp->dev_caps_cfg);
 632
 633         if (bp->max_resp_len != max_resp_len) {
 634                 sprintf(type, "bnxt_hwrm_%04x:%02x:%02x:%02x",
 635                         bp->pdev->addr.domain, bp->pdev->addr.bus,
 636                         bp->pdev->addr.devid, bp->pdev->addr.function);
 637
 638                 rte_free(bp->hwrm_cmd_resp_addr);
 639
 640                 bp->hwrm_cmd_resp_addr = rte_malloc(type, max_resp_len, 0);
 641                 if (bp->hwrm_cmd_resp_addr == NULL) {
 642                         rc = -ENOMEM;
 643                         goto error;
 644                 }
 645                 rte_mem_lock_page(bp->hwrm_cmd_resp_addr);
 646                 bp->hwrm_cmd_resp_dma_addr =
 647                         rte_mem_virt2iova(bp->hwrm_cmd_resp_addr);
 648                 if (bp->hwrm_cmd_resp_dma_addr == 0) {
 649                         RTE_LOG(ERR, PMD,
 650                         "Unable to map response buffer to physical memory.\n");
 651                         rc = -ENOMEM;
 652                         goto error;
 653                 }
 654                 bp->max_resp_len = max_resp_len;
 655         }
 656
 657         if ((dev_caps_cfg &
 658                 HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_SUPPORTED) &&
 659             (dev_caps_cfg &
 660              HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_INPUTUIRED)) {
 661                 RTE_LOG(DEBUG, PMD, "Short command supported\n");
 662
 663                 rte_free(bp->hwrm_short_cmd_req_addr);
 664
 665                 bp->hwrm_short_cmd_req_addr = rte_malloc(type,
 666                                                         bp->max_req_len, 0);
 667                 if (bp->hwrm_short_cmd_req_addr == NULL) {
 668                         rc = -ENOMEM;
 669                         goto error;
 670                 }
 671                 rte_mem_lock_page(bp->hwrm_short_cmd_req_addr);
 672                 bp->hwrm_short_cmd_req_dma_addr =
 673                         rte_mem_virt2iova(bp->hwrm_short_cmd_req_addr);
 674                 if (bp->hwrm_short_cmd_req_dma_addr == 0) {
 675                         rte_free(bp->hwrm_short_cmd_req_addr);
 676                         RTE_LOG(ERR, PMD,
 677                                 "Unable to map buffer to physical memory.\n");
 678                         rc = -ENOMEM;
 679                         goto error;
 680                 }
 681
 682                 bp->flags |= BNXT_FLAG_SHORT_CMD;
 683         }
 684
 685 error:
 686         HWRM_UNLOCK();
 687         return rc;
 688 }
 689
 690 int bnxt_hwrm_func_driver_unregister(struct bnxt *bp, uint32_t flags)
 691 {
 692         int rc;
 693         struct hwrm_func_drv_unrgtr_input req = {.req_type = 0 };
 694         struct hwrm_func_drv_unrgtr_output *resp = bp->hwrm_cmd_resp_addr;
 695
 696         if (!(bp->flags & BNXT_FLAG_REGISTERED))
 697                 return 0;
 698
 699         HWRM_PREP(req, FUNC_DRV_UNRGTR);
 700         req.flags = flags;
 701
 702         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
 703
 704         HWRM_CHECK_RESULT();
 705         HWRM_UNLOCK();
 706
 707         bp->flags &= ~BNXT_FLAG_REGISTERED;
 708
 709         return rc;
 710 }
 711
 712 static int bnxt_hwrm_port_phy_cfg(struct bnxt *bp, struct bnxt_link_info *conf)
 713 {
 714         int rc = 0;
 715         struct hwrm_port_phy_cfg_input req = {0};
 716         struct hwrm_port_phy_cfg_output *resp = bp->hwrm_cmd_resp_addr;
 717         uint32_t enables = 0;
 718
 719         HWRM_PREP(req, PORT_PHY_CFG);
 720
 721         if (conf->link_up) {
 722                 /* Setting Fixed Speed. But AutoNeg is ON, So disable it */
 723                 if (bp->link_info.auto_mode && conf->link_speed) {
 724                         req.auto_mode = HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_NONE;
 725                         RTE_LOG(DEBUG, PMD, "Disabling AutoNeg\n");
 726                 }
 727
 728                 req.flags = rte_cpu_to_le_32(conf->phy_flags);
 729                 req.force_link_speed = rte_cpu_to_le_16(conf->link_speed);
 730                 enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_MODE;
 731                 /*
 732                  * Note, ChiMP FW 20.2.1 and 20.2.2 return an error when we set
 733                  * any auto mode, even "none".
 734                  */
 735                 if (!conf->link_speed) {
 736                         /* No speeds specified. Enable AutoNeg - all speeds */
 737                         req.auto_mode =
 738                                 HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_ALL_SPEEDS;
 739                 }
 740                 /* AutoNeg - Advertise speeds specified. */
 741                 if (conf->auto_link_speed_mask) {
 742                         req.auto_mode =
 743                                 HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_SPEED_MASK;
 744                         req.auto_link_speed_mask =
 745                                 conf->auto_link_speed_mask;
 746                         enables |=
 747                         HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_LINK_SPEED_MASK;
 748                 }
 749
 750                 req.auto_duplex = conf->duplex;
 751                 enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_DUPLEX;
 752                 req.auto_pause = conf->auto_pause;
 753                 req.force_pause = conf->force_pause;
 754                 /* Set force_pause if there is no auto or if there is a force */
 755                 if (req.auto_pause && !req.force_pause)
 756                         enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_PAUSE;
 757                 else
 758                         enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_FORCE_PAUSE;
 759
 760                 req.enables = rte_cpu_to_le_32(enables);
 761         } else {
 762                 req.flags =
 763                 rte_cpu_to_le_32(HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE_LINK_DWN);
 764                 RTE_LOG(INFO, PMD, "Force Link Down\n");
 765         }
 766
 767         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
 768
 769         HWRM_CHECK_RESULT();
 770         HWRM_UNLOCK();
 771
 772         return rc;
 773 }
 774
 775 static int bnxt_hwrm_port_phy_qcfg(struct bnxt *bp,
 776                                    struct bnxt_link_info *link_info)
 777 {
 778         int rc = 0;
 779         struct hwrm_port_phy_qcfg_input req = {0};
 780         struct hwrm_port_phy_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
 781
 782         HWRM_PREP(req, PORT_PHY_QCFG);
 783
 784         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
 785
 786         HWRM_CHECK_RESULT();
 787
 788         link_info->phy_link_status = resp->link;
 789         link_info->link_up =
 790                 (link_info->phy_link_status ==
 791                  HWRM_PORT_PHY_QCFG_OUTPUT_LINK_LINK) ? 1 : 0;
 792         link_info->link_speed = rte_le_to_cpu_16(resp->link_speed);
 793         link_info->duplex = resp->duplex_cfg;
 794         link_info->pause = resp->pause;
 795         link_info->auto_pause = resp->auto_pause;
 796         link_info->force_pause = resp->force_pause;
 797         link_info->auto_mode = resp->auto_mode;
 798         link_info->phy_type = resp->phy_type;
 799         link_info->media_type = resp->media_type;
 800
 801         link_info->support_speeds = rte_le_to_cpu_16(resp->support_speeds);
 802         link_info->auto_link_speed = rte_le_to_cpu_16(resp->auto_link_speed);
 803         link_info->preemphasis = rte_le_to_cpu_32(resp->preemphasis);
 804         link_info->phy_ver[0] = resp->phy_maj;
 805         link_info->phy_ver[1] = resp->phy_min;
 806         link_info->phy_ver[2] = resp->phy_bld;
 807
 808         HWRM_UNLOCK();
 809
 810         return rc;
 811 }
 812
 813 int bnxt_hwrm_queue_qportcfg(struct bnxt *bp)
 814 {
 815         int rc = 0;
 816         struct hwrm_queue_qportcfg_input req = {.req_type = 0 };
 817         struct hwrm_queue_qportcfg_output *resp = bp->hwrm_cmd_resp_addr;
 818
 819         HWRM_PREP(req, QUEUE_QPORTCFG);
 820
 821         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
 822
 823         HWRM_CHECK_RESULT();
 824
 825 #define GET_QUEUE_INFO(x) \
 826         bp->cos_queue[x].id = resp->queue_id##x; \
 827         bp->cos_queue[x].profile = resp->queue_id##x##_service_profile
 828
 829         GET_QUEUE_INFO(0);
 830         GET_QUEUE_INFO(1);
 831         GET_QUEUE_INFO(2);
 832         GET_QUEUE_INFO(3);
 833         GET_QUEUE_INFO(4);
 834         GET_QUEUE_INFO(5);
 835         GET_QUEUE_INFO(6);
 836         GET_QUEUE_INFO(7);
 837
 838         HWRM_UNLOCK();
 839
 840         return rc;
 841 }
 842
 843 int bnxt_hwrm_ring_alloc(struct bnxt *bp,
 844                          struct bnxt_ring *ring,
 845                          uint32_t ring_type, uint32_t map_index,
 846                          uint32_t stats_ctx_id, uint32_t cmpl_ring_id)
 847 {
 848         int rc = 0;
 849         uint32_t enables = 0;
 850         struct hwrm_ring_alloc_input req = {.req_type = 0 };
 851         struct hwrm_ring_alloc_output *resp = bp->hwrm_cmd_resp_addr;
 852
 853         HWRM_PREP(req, RING_ALLOC);
 854
 855         req.page_tbl_addr = rte_cpu_to_le_64(ring->bd_dma);
 856         req.fbo = rte_cpu_to_le_32(0);
 857         /* Association of ring index with doorbell index */
 858         req.logical_id = rte_cpu_to_le_16(map_index);
 859         req.length = rte_cpu_to_le_32(ring->ring_size);
 860
 861         switch (ring_type) {
 862         case HWRM_RING_ALLOC_INPUT_RING_TYPE_TX:
 863                 req.queue_id = bp->cos_queue[0].id;
 864                 /* FALLTHROUGH */
 865         case HWRM_RING_ALLOC_INPUT_RING_TYPE_RX:
 866                 req.ring_type = ring_type;
 867                 req.cmpl_ring_id = rte_cpu_to_le_16(cmpl_ring_id);
 868                 req.stat_ctx_id = rte_cpu_to_le_16(stats_ctx_id);
 869                 if (stats_ctx_id != INVALID_STATS_CTX_ID)
 870                         enables |=
 871                         HWRM_RING_ALLOC_INPUT_ENABLES_STAT_CTX_ID_VALID;
 872                 break;
 873         case HWRM_RING_ALLOC_INPUT_RING_TYPE_L2_CMPL:
 874                 req.ring_type = ring_type;
 875                 /*
 876                  * TODO: Some HWRM versions crash with
 877                  * HWRM_RING_ALLOC_INPUT_INT_MODE_POLL
 878                  */
 879                 req.int_mode = HWRM_RING_ALLOC_INPUT_INT_MODE_MSIX;
 880                 break;
 881         default:
 882                 RTE_LOG(ERR, PMD, "hwrm alloc invalid ring type %d\n",
 883                         ring_type);
 884                 HWRM_UNLOCK();
 885                 return -1;
 886         }
 887         req.enables = rte_cpu_to_le_32(enables);
 888
 889         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
 890
 891         if (rc || resp->error_code) {
 892                 if (rc == 0 && resp->error_code)
 893                         rc = rte_le_to_cpu_16(resp->error_code);
 894                 switch (ring_type) {
 895                 case HWRM_RING_FREE_INPUT_RING_TYPE_L2_CMPL:
 896                         RTE_LOG(ERR, PMD,
 897                                 "hwrm_ring_alloc cp failed. rc:%d\n", rc);
 898                         HWRM_UNLOCK();
 899                         return rc;
 900                 case HWRM_RING_FREE_INPUT_RING_TYPE_RX:
 901                         RTE_LOG(ERR, PMD,
 902                                 "hwrm_ring_alloc rx failed. rc:%d\n", rc);
 903                         HWRM_UNLOCK();
 904                         return rc;
 905                 case HWRM_RING_FREE_INPUT_RING_TYPE_TX:
 906                         RTE_LOG(ERR, PMD,
 907                                 "hwrm_ring_alloc tx failed. rc:%d\n", rc);
 908                         HWRM_UNLOCK();
 909                         return rc;
 910                 default:
 911                         RTE_LOG(ERR, PMD, "Invalid ring. rc:%d\n", rc);
 912                         HWRM_UNLOCK();
 913                         return rc;
 914                 }
 915         }
 916
 917         ring->fw_ring_id = rte_le_to_cpu_16(resp->ring_id);
 918         HWRM_UNLOCK();
 919         return rc;
 920 }
 921
 922 int bnxt_hwrm_ring_free(struct bnxt *bp,
 923                         struct bnxt_ring *ring, uint32_t ring_type)
 924 {
 925         int rc;
 926         struct hwrm_ring_free_input req = {.req_type = 0 };
 927         struct hwrm_ring_free_output *resp = bp->hwrm_cmd_resp_addr;
 928
 929         HWRM_PREP(req, RING_FREE);
 930
 931         req.ring_type = ring_type;
 932         req.ring_id = rte_cpu_to_le_16(ring->fw_ring_id);
 933
 934         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
 935
 936         if (rc || resp->error_code) {
 937                 if (rc == 0 && resp->error_code)
 938                         rc = rte_le_to_cpu_16(resp->error_code);
 939                 HWRM_UNLOCK();
 940
 941                 switch (ring_type) {
 942                 case HWRM_RING_FREE_INPUT_RING_TYPE_L2_CMPL:
 943                         RTE_LOG(ERR, PMD, "hwrm_ring_free cp failed. rc:%d\n",
 944                                 rc);
 945                         return rc;
 946                 case HWRM_RING_FREE_INPUT_RING_TYPE_RX:
 947                         RTE_LOG(ERR, PMD, "hwrm_ring_free rx failed. rc:%d\n",
 948                                 rc);
 949                         return rc;
 950                 case HWRM_RING_FREE_INPUT_RING_TYPE_TX:
 951                         RTE_LOG(ERR, PMD, "hwrm_ring_free tx failed. rc:%d\n",
 952                                 rc);
 953                         return rc;
 954                 default:
 955                         RTE_LOG(ERR, PMD, "Invalid ring, rc:%d\n", rc);
 956                         return rc;
 957                 }
 958         }
 959         HWRM_UNLOCK();
 960         return 0;
 961 }
 962
 963 int bnxt_hwrm_ring_grp_alloc(struct bnxt *bp, unsigned int idx)
 964 {
 965         int rc = 0;
 966         struct hwrm_ring_grp_alloc_input req = {.req_type = 0 };
 967         struct hwrm_ring_grp_alloc_output *resp = bp->hwrm_cmd_resp_addr;
 968
 969         HWRM_PREP(req, RING_GRP_ALLOC);
 970
 971         req.cr = rte_cpu_to_le_16(bp->grp_info[idx].cp_fw_ring_id);
 972         req.rr = rte_cpu_to_le_16(bp->grp_info[idx].rx_fw_ring_id);
 973         req.ar = rte_cpu_to_le_16(bp->grp_info[idx].ag_fw_ring_id);
 974         req.sc = rte_cpu_to_le_16(bp->grp_info[idx].fw_stats_ctx);
 975
 976         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
 977
 978         HWRM_CHECK_RESULT();
 979
 980         bp->grp_info[idx].fw_grp_id =
 981             rte_le_to_cpu_16(resp->ring_group_id);
 982
 983         HWRM_UNLOCK();
 984
 985         return rc;
 986 }
 987
 988 int bnxt_hwrm_ring_grp_free(struct bnxt *bp, unsigned int idx)
 989 {
 990         int rc;
 991         struct hwrm_ring_grp_free_input req = {.req_type = 0 };
 992         struct hwrm_ring_grp_free_output *resp = bp->hwrm_cmd_resp_addr;
 993
 994         HWRM_PREP(req, RING_GRP_FREE);
 995
 996         req.ring_group_id = rte_cpu_to_le_16(bp->grp_info[idx].fw_grp_id);
 997
 998         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
 999
1000         HWRM_CHECK_RESULT();
1001         HWRM_UNLOCK();
1002
1003         bp->grp_info[idx].fw_grp_id = INVALID_HW_RING_ID;
1004         return rc;
1005 }
1006
1007 int bnxt_hwrm_stat_clear(struct bnxt *bp, struct bnxt_cp_ring_info *cpr)
1008 {
1009         int rc = 0;
1010         struct hwrm_stat_ctx_clr_stats_input req = {.req_type = 0 };
1011         struct hwrm_stat_ctx_clr_stats_output *resp = bp->hwrm_cmd_resp_addr;
1012
1013         if (cpr->hw_stats_ctx_id == (uint32_t)HWRM_NA_SIGNATURE)
1014                 return rc;
1015
1016         HWRM_PREP(req, STAT_CTX_CLR_STATS);
1017
1018         req.stat_ctx_id = rte_cpu_to_le_16(cpr->hw_stats_ctx_id);
1019
1020         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
1021
1022         HWRM_CHECK_RESULT();
1023         HWRM_UNLOCK();
1024
1025         return rc;
1026 }
1027
1028 int bnxt_hwrm_stat_ctx_alloc(struct bnxt *bp, struct bnxt_cp_ring_info *cpr,
1029                                 unsigned int idx __rte_unused)
1030 {
1031         int rc;
1032         struct hwrm_stat_ctx_alloc_input req = {.req_type = 0 };
1033         struct hwrm_stat_ctx_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1034
1035         HWRM_PREP(req, STAT_CTX_ALLOC);
1036
1037         req.update_period_ms = rte_cpu_to_le_32(0);
1038
1039         req.stats_dma_addr =
1040             rte_cpu_to_le_64(cpr->hw_stats_map);
1041
1042         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
1043
1044         HWRM_CHECK_RESULT();
1045
1046         cpr->hw_stats_ctx_id = rte_le_to_cpu_16(resp->stat_ctx_id);
1047
1048         HWRM_UNLOCK();
1049         bp->grp_info[idx].fw_stats_ctx = cpr->hw_stats_ctx_id;
1050
1051         return rc;
1052 }
1053
1054 int bnxt_hwrm_stat_ctx_free(struct bnxt *bp, struct bnxt_cp_ring_info *cpr,
1055                                 unsigned int idx __rte_unused)
1056 {
1057         int rc;
1058         struct hwrm_stat_ctx_free_input req = {.req_type = 0 };
1059         struct hwrm_stat_ctx_free_output *resp = bp->hwrm_cmd_resp_addr;
1060
1061         HWRM_PREP(req, STAT_CTX_FREE);
1062
1063         req.stat_ctx_id = rte_cpu_to_le_16(cpr->hw_stats_ctx_id);
1064
1065         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
1066
1067         HWRM_CHECK_RESULT();
1068         HWRM_UNLOCK();
1069
1070         return rc;
1071 }
1072
1073 int bnxt_hwrm_vnic_alloc(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1074 {
1075         int rc = 0, i, j;
1076         struct hwrm_vnic_alloc_input req = { 0 };
1077         struct hwrm_vnic_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1078
1079         /* map ring groups to this vnic */
1080         RTE_LOG(DEBUG, PMD, "Alloc VNIC. Start %x, End %x\n",
1081                 vnic->start_grp_id, vnic->end_grp_id);
1082         for (i = vnic->start_grp_id, j = 0; i <= vnic->end_grp_id; i++, j++)
1083                 vnic->fw_grp_ids[j] = bp->grp_info[i].fw_grp_id;
1084         vnic->dflt_ring_grp = bp->grp_info[vnic->start_grp_id].fw_grp_id;
1085         vnic->rss_rule = (uint16_t)HWRM_NA_SIGNATURE;
1086         vnic->cos_rule = (uint16_t)HWRM_NA_SIGNATURE;
1087         vnic->lb_rule = (uint16_t)HWRM_NA_SIGNATURE;
1088         vnic->mru = bp->eth_dev->data->mtu + ETHER_HDR_LEN +
1089                                 ETHER_CRC_LEN + VLAN_TAG_SIZE;
1090         HWRM_PREP(req, VNIC_ALLOC);
1091
1092         if (vnic->func_default)
1093                 req.flags = HWRM_VNIC_ALLOC_INPUT_FLAGS_DEFAULT;
1094         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
1095
1096         HWRM_CHECK_RESULT();
1097
1098         vnic->fw_vnic_id = rte_le_to_cpu_16(resp->vnic_id);
1099         HWRM_UNLOCK();
1100         RTE_LOG(DEBUG, PMD, "VNIC ID %x\n", vnic->fw_vnic_id);
1101         return rc;
1102 }
1103
1104 static int bnxt_hwrm_vnic_plcmodes_qcfg(struct bnxt *bp,
1105                                         struct bnxt_vnic_info *vnic,
1106                                         struct bnxt_plcmodes_cfg *pmode)
1107 {
1108         int rc = 0;
1109         struct hwrm_vnic_plcmodes_qcfg_input req = {.req_type = 0 };
1110         struct hwrm_vnic_plcmodes_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
1111
1112         HWRM_PREP(req, VNIC_PLCMODES_QCFG);
1113
1114         req.vnic_id = rte_cpu_to_le_32(vnic->fw_vnic_id);
1115
1116         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
1117
1118         HWRM_CHECK_RESULT();
1119
1120         pmode->flags = rte_le_to_cpu_32(resp->flags);
1121         /* dflt_vnic bit doesn't exist in the _cfg command */
1122         pmode->flags &= ~(HWRM_VNIC_PLCMODES_QCFG_OUTPUT_FLAGS_DFLT_VNIC);
1123         pmode->jumbo_thresh = rte_le_to_cpu_16(resp->jumbo_thresh);
1124         pmode->hds_offset = rte_le_to_cpu_16(resp->hds_offset);
1125         pmode->hds_threshold = rte_le_to_cpu_16(resp->hds_threshold);
1126
1127         HWRM_UNLOCK();
1128
1129         return rc;
1130 }
1131
1132 static int bnxt_hwrm_vnic_plcmodes_cfg(struct bnxt *bp,
1133                                        struct bnxt_vnic_info *vnic,
1134                                        struct bnxt_plcmodes_cfg *pmode)
1135 {
1136         int rc = 0;
1137         struct hwrm_vnic_plcmodes_cfg_input req = {.req_type = 0 };
1138         struct hwrm_vnic_plcmodes_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1139
1140         HWRM_PREP(req, VNIC_PLCMODES_CFG);
1141
1142         req.vnic_id = rte_cpu_to_le_32(vnic->fw_vnic_id);
1143         req.flags = rte_cpu_to_le_32(pmode->flags);
1144         req.jumbo_thresh = rte_cpu_to_le_16(pmode->jumbo_thresh);
1145         req.hds_offset = rte_cpu_to_le_16(pmode->hds_offset);
1146         req.hds_threshold = rte_cpu_to_le_16(pmode->hds_threshold);
1147         req.enables = rte_cpu_to_le_32(
1148             HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_HDS_THRESHOLD_VALID |
1149             HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_HDS_OFFSET_VALID |
1150             HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_JUMBO_THRESH_VALID
1151         );
1152
1153         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
1154
1155         HWRM_CHECK_RESULT();
1156         HWRM_UNLOCK();
1157
1158         return rc;
1159 }
1160
1161 int bnxt_hwrm_vnic_cfg(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1162 {
1163         int rc = 0;
1164         struct hwrm_vnic_cfg_input req = {.req_type = 0 };
1165         struct hwrm_vnic_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1166         uint32_t ctx_enable_flag = 0;
1167         struct bnxt_plcmodes_cfg pmodes;
1168
1169         if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
1170                 RTE_LOG(DEBUG, PMD, "VNIC ID %x\n", vnic->fw_vnic_id);
1171                 return rc;
1172         }
1173
1174         rc = bnxt_hwrm_vnic_plcmodes_qcfg(bp, vnic, &pmodes);
1175         if (rc)
1176                 return rc;
1177
1178         HWRM_PREP(req, VNIC_CFG);
1179
1180         /* Only RSS support for now TBD: COS & LB */
1181         req.enables =
1182             rte_cpu_to_le_32(HWRM_VNIC_CFG_INPUT_ENABLES_DFLT_RING_GRP);
1183         if (vnic->lb_rule != 0xffff)
1184                 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_LB_RULE;
1185         if (vnic->cos_rule != 0xffff)
1186                 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_COS_RULE;
1187         if (vnic->rss_rule != 0xffff) {
1188                 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_MRU;
1189                 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_RSS_RULE;
1190         }
1191         req.enables |= rte_cpu_to_le_32(ctx_enable_flag);
1192         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1193         req.dflt_ring_grp = rte_cpu_to_le_16(vnic->dflt_ring_grp);
1194         req.rss_rule = rte_cpu_to_le_16(vnic->rss_rule);
1195         req.cos_rule = rte_cpu_to_le_16(vnic->cos_rule);
1196         req.lb_rule = rte_cpu_to_le_16(vnic->lb_rule);
1197         req.mru = rte_cpu_to_le_16(vnic->mru);
1198         if (vnic->func_default)
1199                 req.flags |=
1200                     rte_cpu_to_le_32(HWRM_VNIC_CFG_INPUT_FLAGS_DEFAULT);
1201         if (vnic->vlan_strip)
1202                 req.flags |=
1203                     rte_cpu_to_le_32(HWRM_VNIC_CFG_INPUT_FLAGS_VLAN_STRIP_MODE);
1204         if (vnic->bd_stall)
1205                 req.flags |=
1206                     rte_cpu_to_le_32(HWRM_VNIC_CFG_INPUT_FLAGS_BD_STALL_MODE);
1207         if (vnic->roce_dual)
1208                 req.flags |= rte_cpu_to_le_32(
1209                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_DUAL_VNIC_MODE);
1210         if (vnic->roce_only)
1211                 req.flags |= rte_cpu_to_le_32(
1212                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_ONLY_VNIC_MODE);
1213         if (vnic->rss_dflt_cr)
1214                 req.flags |= rte_cpu_to_le_32(
1215                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_RSS_DFLT_CR_MODE);
1216
1217         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
1218
1219         HWRM_CHECK_RESULT();
1220         HWRM_UNLOCK();
1221
1222         rc = bnxt_hwrm_vnic_plcmodes_cfg(bp, vnic, &pmodes);
1223
1224         return rc;
1225 }
1226
1227 int bnxt_hwrm_vnic_qcfg(struct bnxt *bp, struct bnxt_vnic_info *vnic,
1228                 int16_t fw_vf_id)
1229 {
1230         int rc = 0;
1231         struct hwrm_vnic_qcfg_input req = {.req_type = 0 };
1232         struct hwrm_vnic_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
1233
1234         if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
1235                 RTE_LOG(DEBUG, PMD, "VNIC QCFG ID %d\n", vnic->fw_vnic_id);
1236                 return rc;
1237         }
1238         HWRM_PREP(req, VNIC_QCFG);
1239
1240         req.enables =
1241                 rte_cpu_to_le_32(HWRM_VNIC_QCFG_INPUT_ENABLES_VF_ID_VALID);
1242         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1243         req.vf_id = rte_cpu_to_le_16(fw_vf_id);
1244
1245         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
1246
1247         HWRM_CHECK_RESULT();
1248
1249         vnic->dflt_ring_grp = rte_le_to_cpu_16(resp->dflt_ring_grp);
1250         vnic->rss_rule = rte_le_to_cpu_16(resp->rss_rule);
1251         vnic->cos_rule = rte_le_to_cpu_16(resp->cos_rule);
1252         vnic->lb_rule = rte_le_to_cpu_16(resp->lb_rule);
1253         vnic->mru = rte_le_to_cpu_16(resp->mru);
1254         vnic->func_default = rte_le_to_cpu_32(
1255                         resp->flags) & HWRM_VNIC_QCFG_OUTPUT_FLAGS_DEFAULT;
1256         vnic->vlan_strip = rte_le_to_cpu_32(resp->flags) &
1257                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_VLAN_STRIP_MODE;
1258         vnic->bd_stall = rte_le_to_cpu_32(resp->flags) &
1259                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_BD_STALL_MODE;
1260         vnic->roce_dual = rte_le_to_cpu_32(resp->flags) &
1261                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_DUAL_VNIC_MODE;
1262         vnic->roce_only = rte_le_to_cpu_32(resp->flags) &
1263                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_ONLY_VNIC_MODE;
1264         vnic->rss_dflt_cr = rte_le_to_cpu_32(resp->flags) &
1265                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_RSS_DFLT_CR_MODE;
1266
1267         HWRM_UNLOCK();
1268
1269         return rc;
1270 }
1271
1272 int bnxt_hwrm_vnic_ctx_alloc(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1273 {
1274         int rc = 0;
1275         struct hwrm_vnic_rss_cos_lb_ctx_alloc_input req = {.req_type = 0 };
1276         struct hwrm_vnic_rss_cos_lb_ctx_alloc_output *resp =
1277                                                 bp->hwrm_cmd_resp_addr;
1278
1279         HWRM_PREP(req, VNIC_RSS_COS_LB_CTX_ALLOC);
1280
1281         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
1282
1283         HWRM_CHECK_RESULT();
1284
1285         vnic->rss_rule = rte_le_to_cpu_16(resp->rss_cos_lb_ctx_id);
1286         HWRM_UNLOCK();
1287         RTE_LOG(DEBUG, PMD, "VNIC RSS Rule %x\n", vnic->rss_rule);
1288
1289         return rc;
1290 }
1291
1292 int bnxt_hwrm_vnic_ctx_free(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1293 {
1294         int rc = 0;
1295         struct hwrm_vnic_rss_cos_lb_ctx_free_input req = {.req_type = 0 };
1296         struct hwrm_vnic_rss_cos_lb_ctx_free_output *resp =
1297                                                 bp->hwrm_cmd_resp_addr;
1298
1299         if (vnic->rss_rule == 0xffff) {
1300                 RTE_LOG(DEBUG, PMD, "VNIC RSS Rule %x\n", vnic->rss_rule);
1301                 return rc;
1302         }
1303         HWRM_PREP(req, VNIC_RSS_COS_LB_CTX_FREE);
1304
1305         req.rss_cos_lb_ctx_id = rte_cpu_to_le_16(vnic->rss_rule);
1306
1307         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
1308
1309         HWRM_CHECK_RESULT();
1310         HWRM_UNLOCK();
1311
1312         vnic->rss_rule = INVALID_HW_RING_ID;
1313
1314         return rc;
1315 }
1316
1317 int bnxt_hwrm_vnic_free(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1318 {
1319         int rc = 0;
1320         struct hwrm_vnic_free_input req = {.req_type = 0 };
1321         struct hwrm_vnic_free_output *resp = bp->hwrm_cmd_resp_addr;
1322
1323         if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
1324                 RTE_LOG(DEBUG, PMD, "VNIC FREE ID %x\n", vnic->fw_vnic_id);
1325                 return rc;
1326         }
1327
1328         HWRM_PREP(req, VNIC_FREE);
1329
1330         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1331
1332         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
1333
1334         HWRM_CHECK_RESULT();
1335         HWRM_UNLOCK();
1336
1337         vnic->fw_vnic_id = INVALID_HW_RING_ID;
1338         return rc;
1339 }
1340
1341 int bnxt_hwrm_vnic_rss_cfg(struct bnxt *bp,
1342                            struct bnxt_vnic_info *vnic)
1343 {
1344         int rc = 0;
1345         struct hwrm_vnic_rss_cfg_input req = {.req_type = 0 };
1346         struct hwrm_vnic_rss_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1347
1348         HWRM_PREP(req, VNIC_RSS_CFG);
1349
1350         req.hash_type = rte_cpu_to_le_32(vnic->hash_type);
1351
1352         req.ring_grp_tbl_addr =
1353             rte_cpu_to_le_64(vnic->rss_table_dma_addr);
1354         req.hash_key_tbl_addr =
1355             rte_cpu_to_le_64(vnic->rss_hash_key_dma_addr);
1356         req.rss_ctx_idx = rte_cpu_to_le_16(vnic->rss_rule);
1357
1358         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
1359
1360         HWRM_CHECK_RESULT();
1361         HWRM_UNLOCK();
1362
1363         return rc;
1364 }
1365
1366 int bnxt_hwrm_vnic_plcmode_cfg(struct bnxt *bp,
1367                         struct bnxt_vnic_info *vnic)
1368 {
1369         int rc = 0;
1370         struct hwrm_vnic_plcmodes_cfg_input req = {.req_type = 0 };
1371         struct hwrm_vnic_plcmodes_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1372         uint16_t size;
1373
1374         HWRM_PREP(req, VNIC_PLCMODES_CFG);
1375
1376         req.flags = rte_cpu_to_le_32(
1377                         HWRM_VNIC_PLCMODES_CFG_INPUT_FLAGS_JUMBO_PLACEMENT);
1378
1379         req.enables = rte_cpu_to_le_32(
1380                 HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_JUMBO_THRESH_VALID);
1381
1382         size = rte_pktmbuf_data_room_size(bp->rx_queues[0]->mb_pool);
1383         size -= RTE_PKTMBUF_HEADROOM;
1384
1385         req.jumbo_thresh = rte_cpu_to_le_16(size);
1386         req.vnic_id = rte_cpu_to_le_32(vnic->fw_vnic_id);
1387
1388         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
1389
1390         HWRM_CHECK_RESULT();
1391         HWRM_UNLOCK();
1392
1393         return rc;
1394 }
1395
1396 int bnxt_hwrm_vnic_tpa_cfg(struct bnxt *bp,
1397                         struct bnxt_vnic_info *vnic, bool enable)
1398 {
1399         int rc = 0;
1400         struct hwrm_vnic_tpa_cfg_input req = {.req_type = 0 };
1401         struct hwrm_vnic_tpa_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1402
1403         HWRM_PREP(req, VNIC_TPA_CFG);
1404
1405         if (enable) {
1406                 req.enables = rte_cpu_to_le_32(
1407                                 HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MAX_AGG_SEGS |
1408                                 HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MAX_AGGS |
1409                                 HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MIN_AGG_LEN);
1410                 req.flags = rte_cpu_to_le_32(
1411                                 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_TPA |
1412                                 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_ENCAP_TPA |
1413                                 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_RSC_WND_UPDATE |
1414                                 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_GRO |
1415                                 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_AGG_WITH_ECN |
1416                         HWRM_VNIC_TPA_CFG_INPUT_FLAGS_AGG_WITH_SAME_GRE_SEQ);
1417                 req.vnic_id = rte_cpu_to_le_32(vnic->fw_vnic_id);
1418                 req.max_agg_segs = rte_cpu_to_le_16(5);
1419                 req.max_aggs =
1420                         rte_cpu_to_le_16(HWRM_VNIC_TPA_CFG_INPUT_MAX_AGGS_MAX);
1421                 req.min_agg_len = rte_cpu_to_le_32(512);
1422         }
1423
1424         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
1425
1426         HWRM_CHECK_RESULT();
1427         HWRM_UNLOCK();
1428
1429         return rc;
1430 }
1431
1432 int bnxt_hwrm_func_vf_mac(struct bnxt *bp, uint16_t vf, const uint8_t *mac_addr)
1433 {
1434         struct hwrm_func_cfg_input req = {0};
1435         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1436         int rc;
1437
1438         req.flags = rte_cpu_to_le_32(bp->pf.vf_info[vf].func_cfg_flags);
1439         req.enables = rte_cpu_to_le_32(
1440                         HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
1441         memcpy(req.dflt_mac_addr, mac_addr, sizeof(req.dflt_mac_addr));
1442         req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
1443
1444         HWRM_PREP(req, FUNC_CFG);
1445
1446         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
1447         HWRM_CHECK_RESULT();
1448         HWRM_UNLOCK();
1449
1450         bp->pf.vf_info[vf].random_mac = false;
1451
1452         return rc;
1453 }
1454
1455 int bnxt_hwrm_func_qstats_tx_drop(struct bnxt *bp, uint16_t fid,
1456                                   uint64_t *dropped)
1457 {
1458         int rc = 0;
1459         struct hwrm_func_qstats_input req = {.req_type = 0};
1460         struct hwrm_func_qstats_output *resp = bp->hwrm_cmd_resp_addr;
1461
1462         HWRM_PREP(req, FUNC_QSTATS);
1463
1464         req.fid = rte_cpu_to_le_16(fid);
1465
1466         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
1467
1468         HWRM_CHECK_RESULT();
1469
1470         if (dropped)
1471                 *dropped = rte_le_to_cpu_64(resp->tx_drop_pkts);
1472
1473         HWRM_UNLOCK();
1474
1475         return rc;
1476 }
1477
1478 int bnxt_hwrm_func_qstats(struct bnxt *bp, uint16_t fid,
1479                           struct rte_eth_stats *stats)
1480 {
1481         int rc = 0;
1482         struct hwrm_func_qstats_input req = {.req_type = 0};
1483         struct hwrm_func_qstats_output *resp = bp->hwrm_cmd_resp_addr;
1484
1485         HWRM_PREP(req, FUNC_QSTATS);
1486
1487         req.fid = rte_cpu_to_le_16(fid);
1488
1489         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
1490
1491         HWRM_CHECK_RESULT();
1492
1493         stats->ipackets = rte_le_to_cpu_64(resp->rx_ucast_pkts);
1494         stats->ipackets += rte_le_to_cpu_64(resp->rx_mcast_pkts);
1495         stats->ipackets += rte_le_to_cpu_64(resp->rx_bcast_pkts);
1496         stats->ibytes = rte_le_to_cpu_64(resp->rx_ucast_bytes);
1497         stats->ibytes += rte_le_to_cpu_64(resp->rx_mcast_bytes);
1498         stats->ibytes += rte_le_to_cpu_64(resp->rx_bcast_bytes);
1499
1500         stats->opackets = rte_le_to_cpu_64(resp->tx_ucast_pkts);
1501         stats->opackets += rte_le_to_cpu_64(resp->tx_mcast_pkts);
1502         stats->opackets += rte_le_to_cpu_64(resp->tx_bcast_pkts);
1503         stats->obytes = rte_le_to_cpu_64(resp->tx_ucast_bytes);
1504         stats->obytes += rte_le_to_cpu_64(resp->tx_mcast_bytes);
1505         stats->obytes += rte_le_to_cpu_64(resp->tx_bcast_bytes);
1506
1507         stats->ierrors = rte_le_to_cpu_64(resp->rx_err_pkts);
1508         stats->oerrors = rte_le_to_cpu_64(resp->tx_err_pkts);
1509
1510         stats->imissed = rte_le_to_cpu_64(resp->rx_drop_pkts);
1511
1512         HWRM_UNLOCK();
1513
1514         return rc;
1515 }
1516
1517 int bnxt_hwrm_func_clr_stats(struct bnxt *bp, uint16_t fid)
1518 {
1519         int rc = 0;
1520         struct hwrm_func_clr_stats_input req = {.req_type = 0};
1521         struct hwrm_func_clr_stats_output *resp = bp->hwrm_cmd_resp_addr;
1522
1523         HWRM_PREP(req, FUNC_CLR_STATS);
1524
1525         req.fid = rte_cpu_to_le_16(fid);
1526
1527         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
1528
1529         HWRM_CHECK_RESULT();
1530         HWRM_UNLOCK();
1531
1532         return rc;
1533 }
1534
1535 /*
1536  * HWRM utility functions
1537  */
1538
1539 int bnxt_clear_all_hwrm_stat_ctxs(struct bnxt *bp)
1540 {
1541         unsigned int i;
1542         int rc = 0;
1543
1544         for (i = 0; i < bp->rx_cp_nr_rings + bp->tx_cp_nr_rings; i++) {
1545                 struct bnxt_tx_queue *txq;
1546                 struct bnxt_rx_queue *rxq;
1547                 struct bnxt_cp_ring_info *cpr;
1548
1549                 if (i >= bp->rx_cp_nr_rings) {
1550                         txq = bp->tx_queues[i - bp->rx_cp_nr_rings];
1551                         cpr = txq->cp_ring;
1552                 } else {
1553                         rxq = bp->rx_queues[i];
1554                         cpr = rxq->cp_ring;
1555                 }
1556
1557                 rc = bnxt_hwrm_stat_clear(bp, cpr);
1558                 if (rc)
1559                         return rc;
1560         }
1561         return 0;
1562 }
1563
1564 int bnxt_free_all_hwrm_stat_ctxs(struct bnxt *bp)
1565 {
1566         int rc;
1567         unsigned int i;
1568         struct bnxt_cp_ring_info *cpr;
1569
1570         for (i = 0; i < bp->rx_cp_nr_rings + bp->tx_cp_nr_rings; i++) {
1571
1572                 if (i >= bp->rx_cp_nr_rings)
1573                         cpr = bp->tx_queues[i - bp->rx_cp_nr_rings]->cp_ring;
1574                 else
1575                         cpr = bp->rx_queues[i]->cp_ring;
1576                 if (cpr->hw_stats_ctx_id != HWRM_NA_SIGNATURE) {
1577                         rc = bnxt_hwrm_stat_ctx_free(bp, cpr, i);
1578                         cpr->hw_stats_ctx_id = HWRM_NA_SIGNATURE;
1579                         /*
1580                          * TODO. Need a better way to reset grp_info.stats_ctx
1581                          * for Rx rings only. stats_ctx is not saved for Tx
1582                          * in grp_info.
1583                          */
1584                         bp->grp_info[i].fw_stats_ctx = cpr->hw_stats_ctx_id;
1585                         if (rc)
1586                                 return rc;
1587                 }
1588         }
1589         return 0;
1590 }
1591
1592 int bnxt_alloc_all_hwrm_stat_ctxs(struct bnxt *bp)
1593 {
1594         unsigned int i;
1595         int rc = 0;
1596
1597         for (i = 0; i < bp->rx_cp_nr_rings + bp->tx_cp_nr_rings; i++) {
1598                 struct bnxt_tx_queue *txq;
1599                 struct bnxt_rx_queue *rxq;
1600                 struct bnxt_cp_ring_info *cpr;
1601
1602                 if (i >= bp->rx_cp_nr_rings) {
1603                         txq = bp->tx_queues[i - bp->rx_cp_nr_rings];
1604                         cpr = txq->cp_ring;
1605                 } else {
1606                         rxq = bp->rx_queues[i];
1607                         cpr = rxq->cp_ring;
1608                 }
1609
1610                 rc = bnxt_hwrm_stat_ctx_alloc(bp, cpr, i);
1611
1612                 if (rc)
1613                         return rc;
1614         }
1615         return rc;
1616 }
1617
1618 int bnxt_free_all_hwrm_ring_grps(struct bnxt *bp)
1619 {
1620         uint16_t idx;
1621         uint32_t rc = 0;
1622
1623         for (idx = 0; idx < bp->rx_cp_nr_rings; idx++) {
1624
1625                 if (bp->grp_info[idx].fw_grp_id == INVALID_HW_RING_ID)
1626                         continue;
1627
1628                 rc = bnxt_hwrm_ring_grp_free(bp, idx);
1629
1630                 if (rc)
1631                         return rc;
1632         }
1633         return rc;
1634 }
1635
1636 static void bnxt_free_cp_ring(struct bnxt *bp, struct bnxt_cp_ring_info *cpr,
1637                                 unsigned int idx __rte_unused)
1638 {
1639         struct bnxt_ring *cp_ring = cpr->cp_ring_struct;
1640
1641         bnxt_hwrm_ring_free(bp, cp_ring,
1642                         HWRM_RING_FREE_INPUT_RING_TYPE_L2_CMPL);
1643         cp_ring->fw_ring_id = INVALID_HW_RING_ID;
1644         bp->grp_info[idx].cp_fw_ring_id = INVALID_HW_RING_ID;
1645         memset(cpr->cp_desc_ring, 0, cpr->cp_ring_struct->ring_size *
1646                         sizeof(*cpr->cp_desc_ring));
1647         cpr->cp_raw_cons = 0;
1648 }
1649
1650 int bnxt_free_all_hwrm_rings(struct bnxt *bp)
1651 {
1652         unsigned int i;
1653         int rc = 0;
1654
1655         for (i = 0; i < bp->tx_cp_nr_rings; i++) {
1656                 struct bnxt_tx_queue *txq = bp->tx_queues[i];
1657                 struct bnxt_tx_ring_info *txr = txq->tx_ring;
1658                 struct bnxt_ring *ring = txr->tx_ring_struct;
1659                 struct bnxt_cp_ring_info *cpr = txq->cp_ring;
1660                 unsigned int idx = bp->rx_cp_nr_rings + i + 1;
1661
1662                 if (ring->fw_ring_id != INVALID_HW_RING_ID) {
1663                         bnxt_hwrm_ring_free(bp, ring,
1664                                         HWRM_RING_FREE_INPUT_RING_TYPE_TX);
1665                         ring->fw_ring_id = INVALID_HW_RING_ID;
1666                         memset(txr->tx_desc_ring, 0,
1667                                         txr->tx_ring_struct->ring_size *
1668                                         sizeof(*txr->tx_desc_ring));
1669                         memset(txr->tx_buf_ring, 0,
1670                                         txr->tx_ring_struct->ring_size *
1671                                         sizeof(*txr->tx_buf_ring));
1672                         txr->tx_prod = 0;
1673                         txr->tx_cons = 0;
1674                 }
1675                 if (cpr->cp_ring_struct->fw_ring_id != INVALID_HW_RING_ID) {
1676                         bnxt_free_cp_ring(bp, cpr, idx);
1677                         cpr->cp_ring_struct->fw_ring_id = INVALID_HW_RING_ID;
1678                 }
1679         }
1680
1681         for (i = 0; i < bp->rx_cp_nr_rings; i++) {
1682                 struct bnxt_rx_queue *rxq = bp->rx_queues[i];
1683                 struct bnxt_rx_ring_info *rxr = rxq->rx_ring;
1684                 struct bnxt_ring *ring = rxr->rx_ring_struct;
1685                 struct bnxt_cp_ring_info *cpr = rxq->cp_ring;
1686                 unsigned int idx = i + 1;
1687
1688                 if (ring->fw_ring_id != INVALID_HW_RING_ID) {
1689                         bnxt_hwrm_ring_free(bp, ring,
1690                                         HWRM_RING_FREE_INPUT_RING_TYPE_RX);
1691                         ring->fw_ring_id = INVALID_HW_RING_ID;
1692                         bp->grp_info[idx].rx_fw_ring_id = INVALID_HW_RING_ID;
1693                         memset(rxr->rx_desc_ring, 0,
1694                                         rxr->rx_ring_struct->ring_size *
1695                                         sizeof(*rxr->rx_desc_ring));
1696                         memset(rxr->rx_buf_ring, 0,
1697                                         rxr->rx_ring_struct->ring_size *
1698                                         sizeof(*rxr->rx_buf_ring));
1699                         rxr->rx_prod = 0;
1700                         memset(rxr->ag_buf_ring, 0,
1701                                         rxr->ag_ring_struct->ring_size *
1702                                         sizeof(*rxr->ag_buf_ring));
1703                         rxr->ag_prod = 0;
1704                 }
1705                 if (cpr->cp_ring_struct->fw_ring_id != INVALID_HW_RING_ID) {
1706                         bnxt_free_cp_ring(bp, cpr, idx);
1707                         bp->grp_info[i].cp_fw_ring_id = INVALID_HW_RING_ID;
1708                         cpr->cp_ring_struct->fw_ring_id = INVALID_HW_RING_ID;
1709                 }
1710         }
1711
1712         /* Default completion ring */
1713         {
1714                 struct bnxt_cp_ring_info *cpr = bp->def_cp_ring;
1715
1716                 if (cpr->cp_ring_struct->fw_ring_id != INVALID_HW_RING_ID) {
1717                         bnxt_free_cp_ring(bp, cpr, 0);
1718                         cpr->cp_ring_struct->fw_ring_id = INVALID_HW_RING_ID;
1719                 }
1720         }
1721
1722         return rc;
1723 }
1724
1725 int bnxt_alloc_all_hwrm_ring_grps(struct bnxt *bp)
1726 {
1727         uint16_t i;
1728         uint32_t rc = 0;
1729
1730         for (i = 0; i < bp->rx_cp_nr_rings; i++) {
1731                 rc = bnxt_hwrm_ring_grp_alloc(bp, i);
1732                 if (rc)
1733                         return rc;
1734         }
1735         return rc;
1736 }
1737
1738 void bnxt_free_hwrm_resources(struct bnxt *bp)
1739 {
1740         /* Release memzone */
1741         rte_free(bp->hwrm_cmd_resp_addr);
1742         rte_free(bp->hwrm_short_cmd_req_addr);
1743         bp->hwrm_cmd_resp_addr = NULL;
1744         bp->hwrm_short_cmd_req_addr = NULL;
1745         bp->hwrm_cmd_resp_dma_addr = 0;
1746         bp->hwrm_short_cmd_req_dma_addr = 0;
1747 }
1748
1749 int bnxt_alloc_hwrm_resources(struct bnxt *bp)
1750 {
1751         struct rte_pci_device *pdev = bp->pdev;
1752         char type[RTE_MEMZONE_NAMESIZE];
1753
1754         sprintf(type, "bnxt_hwrm_%04x:%02x:%02x:%02x", pdev->addr.domain,
1755                 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
1756         bp->max_resp_len = HWRM_MAX_RESP_LEN;
1757         bp->hwrm_cmd_resp_addr = rte_malloc(type, bp->max_resp_len, 0);
1758         rte_mem_lock_page(bp->hwrm_cmd_resp_addr);
1759         if (bp->hwrm_cmd_resp_addr == NULL)
1760                 return -ENOMEM;
1761         bp->hwrm_cmd_resp_dma_addr =
1762                 rte_mem_virt2iova(bp->hwrm_cmd_resp_addr);
1763         if (bp->hwrm_cmd_resp_dma_addr == 0) {
1764                 RTE_LOG(ERR, PMD,
1765                         "unable to map response address to physical memory\n");
1766                 return -ENOMEM;
1767         }
1768         rte_spinlock_init(&bp->hwrm_lock);
1769
1770         return 0;
1771 }
1772
1773 int bnxt_clear_hwrm_vnic_filters(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1774 {
1775         struct bnxt_filter_info *filter;
1776         int rc = 0;
1777
1778         STAILQ_FOREACH(filter, &vnic->filter, next) {
1779                 if (filter->filter_type == HWRM_CFA_EM_FILTER)
1780                         rc = bnxt_hwrm_clear_em_filter(bp, filter);
1781                 else if (filter->filter_type == HWRM_CFA_NTUPLE_FILTER)
1782                         rc = bnxt_hwrm_clear_ntuple_filter(bp, filter);
1783                 else
1784                         rc = bnxt_hwrm_clear_l2_filter(bp, filter);
1785                 //if (rc)
1786                         //break;
1787         }
1788         return rc;
1789 }
1790
1791 static int
1792 bnxt_clear_hwrm_vnic_flows(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1793 {
1794         struct bnxt_filter_info *filter;
1795         struct rte_flow *flow;
1796         int rc = 0;
1797
1798         STAILQ_FOREACH(flow, &vnic->flow_list, next) {
1799                 filter = flow->filter;
1800                 RTE_LOG(ERR, PMD, "filter type %d\n", filter->filter_type);
1801                 if (filter->filter_type == HWRM_CFA_EM_FILTER)
1802                         rc = bnxt_hwrm_clear_em_filter(bp, filter);
1803                 else if (filter->filter_type == HWRM_CFA_NTUPLE_FILTER)
1804                         rc = bnxt_hwrm_clear_ntuple_filter(bp, filter);
1805                 else
1806                         rc = bnxt_hwrm_clear_l2_filter(bp, filter);
1807
1808                 STAILQ_REMOVE(&vnic->flow_list, flow, rte_flow, next);
1809                 rte_free(flow);
1810                 //if (rc)
1811                         //break;
1812         }
1813         return rc;
1814 }
1815
1816 int bnxt_set_hwrm_vnic_filters(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1817 {
1818         struct bnxt_filter_info *filter;
1819         int rc = 0;
1820
1821         STAILQ_FOREACH(filter, &vnic->filter, next) {
1822                 if (filter->filter_type == HWRM_CFA_EM_FILTER)
1823                         rc = bnxt_hwrm_set_em_filter(bp, filter->dst_id,
1824                                                      filter);
1825                 else if (filter->filter_type == HWRM_CFA_NTUPLE_FILTER)
1826                         rc = bnxt_hwrm_set_ntuple_filter(bp, filter->dst_id,
1827                                                          filter);
1828                 else
1829                         rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id,
1830                                                      filter);
1831                 if (rc)
1832                         break;
1833         }
1834         return rc;
1835 }
1836
1837 void bnxt_free_tunnel_ports(struct bnxt *bp)
1838 {
1839         if (bp->vxlan_port_cnt)
1840                 bnxt_hwrm_tunnel_dst_port_free(bp, bp->vxlan_fw_dst_port_id,
1841                         HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN);
1842         bp->vxlan_port = 0;
1843         if (bp->geneve_port_cnt)
1844                 bnxt_hwrm_tunnel_dst_port_free(bp, bp->geneve_fw_dst_port_id,
1845                         HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE);
1846         bp->geneve_port = 0;
1847 }
1848
1849 void bnxt_free_all_hwrm_resources(struct bnxt *bp)
1850 {
1851         int i;
1852
1853         if (bp->vnic_info == NULL)
1854                 return;
1855
1856         /*
1857          * Cleanup VNICs in reverse order, to make sure the L2 filter
1858          * from vnic0 is last to be cleaned up.
1859          */
1860         for (i = bp->nr_vnics - 1; i >= 0; i--) {
1861                 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
1862
1863                 bnxt_clear_hwrm_vnic_flows(bp, vnic);
1864
1865                 bnxt_clear_hwrm_vnic_filters(bp, vnic);
1866
1867                 bnxt_hwrm_vnic_ctx_free(bp, vnic);
1868
1869                 bnxt_hwrm_vnic_tpa_cfg(bp, vnic, false);
1870
1871                 bnxt_hwrm_vnic_free(bp, vnic);
1872         }
1873         /* Ring resources */
1874         bnxt_free_all_hwrm_rings(bp);
1875         bnxt_free_all_hwrm_ring_grps(bp);
1876         bnxt_free_all_hwrm_stat_ctxs(bp);
1877         bnxt_free_tunnel_ports(bp);
1878 }
1879
1880 static uint16_t bnxt_parse_eth_link_duplex(uint32_t conf_link_speed)
1881 {
1882         uint8_t hw_link_duplex = HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH;
1883
1884         if ((conf_link_speed & ETH_LINK_SPEED_FIXED) == ETH_LINK_SPEED_AUTONEG)
1885                 return HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH;
1886
1887         switch (conf_link_speed) {
1888         case ETH_LINK_SPEED_10M_HD:
1889         case ETH_LINK_SPEED_100M_HD:
1890                 return HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_HALF;
1891         }
1892         return hw_link_duplex;
1893 }
1894
1895 static uint16_t bnxt_check_eth_link_autoneg(uint32_t conf_link)
1896 {
1897         return (conf_link & ETH_LINK_SPEED_FIXED) ? 0 : 1;
1898 }
1899
1900 static uint16_t bnxt_parse_eth_link_speed(uint32_t conf_link_speed)
1901 {
1902         uint16_t eth_link_speed = 0;
1903
1904         if (conf_link_speed == ETH_LINK_SPEED_AUTONEG)
1905                 return ETH_LINK_SPEED_AUTONEG;
1906
1907         switch (conf_link_speed & ~ETH_LINK_SPEED_FIXED) {
1908         case ETH_LINK_SPEED_100M:
1909         case ETH_LINK_SPEED_100M_HD:
1910                 eth_link_speed =
1911                         HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_100MB;
1912                 break;
1913         case ETH_LINK_SPEED_1G:
1914                 eth_link_speed =
1915                         HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_1GB;
1916                 break;
1917         case ETH_LINK_SPEED_2_5G:
1918                 eth_link_speed =
1919                         HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_2_5GB;
1920                 break;
1921         case ETH_LINK_SPEED_10G:
1922                 eth_link_speed =
1923                         HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_10GB;
1924                 break;
1925         case ETH_LINK_SPEED_20G:
1926                 eth_link_speed =
1927                         HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_20GB;
1928                 break;
1929         case ETH_LINK_SPEED_25G:
1930                 eth_link_speed =
1931                         HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_25GB;
1932                 break;
1933         case ETH_LINK_SPEED_40G:
1934                 eth_link_speed =
1935                         HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_40GB;
1936                 break;
1937         case ETH_LINK_SPEED_50G:
1938                 eth_link_speed =
1939                         HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_50GB;
1940                 break;
1941         default:
1942                 RTE_LOG(ERR, PMD,
1943                         "Unsupported link speed %d; default to AUTO\n",
1944                         conf_link_speed);
1945                 break;
1946         }
1947         return eth_link_speed;
1948 }
1949
1950 #define BNXT_SUPPORTED_SPEEDS (ETH_LINK_SPEED_100M | ETH_LINK_SPEED_100M_HD | \
1951                 ETH_LINK_SPEED_1G | ETH_LINK_SPEED_2_5G | \
1952                 ETH_LINK_SPEED_10G | ETH_LINK_SPEED_20G | ETH_LINK_SPEED_25G | \
1953                 ETH_LINK_SPEED_40G | ETH_LINK_SPEED_50G)
1954
1955 static int bnxt_valid_link_speed(uint32_t link_speed, uint16_t port_id)
1956 {
1957         uint32_t one_speed;
1958
1959         if (link_speed == ETH_LINK_SPEED_AUTONEG)
1960                 return 0;
1961
1962         if (link_speed & ETH_LINK_SPEED_FIXED) {
1963                 one_speed = link_speed & ~ETH_LINK_SPEED_FIXED;
1964
1965                 if (one_speed & (one_speed - 1)) {
1966                         RTE_LOG(ERR, PMD,
1967                                 "Invalid advertised speeds (%u) for port %u\n",
1968                                 link_speed, port_id);
1969                         return -EINVAL;
1970                 }
1971                 if ((one_speed & BNXT_SUPPORTED_SPEEDS) != one_speed) {
1972                         RTE_LOG(ERR, PMD,
1973                                 "Unsupported advertised speed (%u) for port %u\n",
1974                                 link_speed, port_id);
1975                         return -EINVAL;
1976                 }
1977         } else {
1978                 if (!(link_speed & BNXT_SUPPORTED_SPEEDS)) {
1979                         RTE_LOG(ERR, PMD,
1980                                 "Unsupported advertised speeds (%u) for port %u\n",
1981                                 link_speed, port_id);
1982                         return -EINVAL;
1983                 }
1984         }
1985         return 0;
1986 }
1987
1988 static uint16_t
1989 bnxt_parse_eth_link_speed_mask(struct bnxt *bp, uint32_t link_speed)
1990 {
1991         uint16_t ret = 0;
1992
1993         if (link_speed == ETH_LINK_SPEED_AUTONEG) {
1994                 if (bp->link_info.support_speeds)
1995                         return bp->link_info.support_speeds;
1996                 link_speed = BNXT_SUPPORTED_SPEEDS;
1997         }
1998
1999         if (link_speed & ETH_LINK_SPEED_100M)
2000                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100MB;
2001         if (link_speed & ETH_LINK_SPEED_100M_HD)
2002                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100MB;
2003         if (link_speed & ETH_LINK_SPEED_1G)
2004                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_1GB;
2005         if (link_speed & ETH_LINK_SPEED_2_5G)
2006                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_2_5GB;
2007         if (link_speed & ETH_LINK_SPEED_10G)
2008                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_10GB;
2009         if (link_speed & ETH_LINK_SPEED_20G)
2010                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_20GB;
2011         if (link_speed & ETH_LINK_SPEED_25G)
2012                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_25GB;
2013         if (link_speed & ETH_LINK_SPEED_40G)
2014                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_40GB;
2015         if (link_speed & ETH_LINK_SPEED_50G)
2016                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_50GB;
2017         return ret;
2018 }
2019
2020 static uint32_t bnxt_parse_hw_link_speed(uint16_t hw_link_speed)
2021 {
2022         uint32_t eth_link_speed = ETH_SPEED_NUM_NONE;
2023
2024         switch (hw_link_speed) {
2025         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_100MB:
2026                 eth_link_speed = ETH_SPEED_NUM_100M;
2027                 break;
2028         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_1GB:
2029                 eth_link_speed = ETH_SPEED_NUM_1G;
2030                 break;
2031         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_2_5GB:
2032                 eth_link_speed = ETH_SPEED_NUM_2_5G;
2033                 break;
2034         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_10GB:
2035                 eth_link_speed = ETH_SPEED_NUM_10G;
2036                 break;
2037         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_20GB:
2038                 eth_link_speed = ETH_SPEED_NUM_20G;
2039                 break;
2040         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_25GB:
2041                 eth_link_speed = ETH_SPEED_NUM_25G;
2042                 break;
2043         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_40GB:
2044                 eth_link_speed = ETH_SPEED_NUM_40G;
2045                 break;
2046         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_50GB:
2047                 eth_link_speed = ETH_SPEED_NUM_50G;
2048                 break;
2049         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_2GB:
2050         default:
2051                 RTE_LOG(ERR, PMD, "HWRM link speed %d not defined\n",
2052                         hw_link_speed);
2053                 break;
2054         }
2055         return eth_link_speed;
2056 }
2057
2058 static uint16_t bnxt_parse_hw_link_duplex(uint16_t hw_link_duplex)
2059 {
2060         uint16_t eth_link_duplex = ETH_LINK_FULL_DUPLEX;
2061
2062         switch (hw_link_duplex) {
2063         case HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH:
2064         case HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_FULL:
2065                 eth_link_duplex = ETH_LINK_FULL_DUPLEX;
2066                 break;
2067         case HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_HALF:
2068                 eth_link_duplex = ETH_LINK_HALF_DUPLEX;
2069                 break;
2070         default:
2071                 RTE_LOG(ERR, PMD, "HWRM link duplex %d not defined\n",
2072                         hw_link_duplex);
2073                 break;
2074         }
2075         return eth_link_duplex;
2076 }
2077
2078 int bnxt_get_hwrm_link_config(struct bnxt *bp, struct rte_eth_link *link)
2079 {
2080         int rc = 0;
2081         struct bnxt_link_info *link_info = &bp->link_info;
2082
2083         rc = bnxt_hwrm_port_phy_qcfg(bp, link_info);
2084         if (rc) {
2085                 RTE_LOG(ERR, PMD,
2086                         "Get link config failed with rc %d\n", rc);
2087                 goto exit;
2088         }
2089         if (link_info->link_speed)
2090                 link->link_speed =
2091                         bnxt_parse_hw_link_speed(link_info->link_speed);
2092         else
2093                 link->link_speed = ETH_SPEED_NUM_NONE;
2094         link->link_duplex = bnxt_parse_hw_link_duplex(link_info->duplex);
2095         link->link_status = link_info->link_up;
2096         link->link_autoneg = link_info->auto_mode ==
2097                 HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_MODE_NONE ?
2098                 ETH_LINK_FIXED : ETH_LINK_AUTONEG;
2099 exit:
2100         return rc;
2101 }
2102
2103 int bnxt_set_hwrm_link_config(struct bnxt *bp, bool link_up)
2104 {
2105         int rc = 0;
2106         struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
2107         struct bnxt_link_info link_req;
2108         uint16_t speed, autoneg;
2109
2110         if (BNXT_NPAR_PF(bp) || BNXT_VF(bp))
2111                 return 0;
2112
2113         rc = bnxt_valid_link_speed(dev_conf->link_speeds,
2114                         bp->eth_dev->data->port_id);
2115         if (rc)
2116                 goto error;
2117
2118         memset(&link_req, 0, sizeof(link_req));
2119         link_req.link_up = link_up;
2120         if (!link_up)
2121                 goto port_phy_cfg;
2122
2123         autoneg = bnxt_check_eth_link_autoneg(dev_conf->link_speeds);
2124         speed = bnxt_parse_eth_link_speed(dev_conf->link_speeds);
2125         link_req.phy_flags = HWRM_PORT_PHY_CFG_INPUT_FLAGS_RESET_PHY;
2126         if (autoneg == 1) {
2127                 link_req.phy_flags |=
2128                                 HWRM_PORT_PHY_CFG_INPUT_FLAGS_RESTART_AUTONEG;
2129                 link_req.auto_link_speed_mask =
2130                         bnxt_parse_eth_link_speed_mask(bp,
2131                                                        dev_conf->link_speeds);
2132         } else {
2133                 if (bp->link_info.phy_type ==
2134                     HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASET ||
2135                     bp->link_info.phy_type ==
2136                     HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASETE ||
2137                     bp->link_info.media_type ==
2138                     HWRM_PORT_PHY_QCFG_OUTPUT_MEDIA_TYPE_TP) {
2139                         RTE_LOG(ERR, PMD, "10GBase-T devices must autoneg\n");
2140                         return -EINVAL;
2141                 }
2142
2143                 link_req.phy_flags |= HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE;
2144                 link_req.link_speed = speed;
2145         }
2146         link_req.duplex = bnxt_parse_eth_link_duplex(dev_conf->link_speeds);
2147         link_req.auto_pause = bp->link_info.auto_pause;
2148         link_req.force_pause = bp->link_info.force_pause;
2149
2150 port_phy_cfg:
2151         rc = bnxt_hwrm_port_phy_cfg(bp, &link_req);
2152         if (rc) {
2153                 RTE_LOG(ERR, PMD,
2154                         "Set link config failed with rc %d\n", rc);
2155         }
2156
2157 error:
2158         return rc;
2159 }
2160
2161 /* JIRA 22088 */
2162 int bnxt_hwrm_func_qcfg(struct bnxt *bp)
2163 {
2164         struct hwrm_func_qcfg_input req = {0};
2165         struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
2166         int rc = 0;
2167
2168         HWRM_PREP(req, FUNC_QCFG);
2169         req.fid = rte_cpu_to_le_16(0xffff);
2170
2171         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2172
2173         HWRM_CHECK_RESULT();
2174
2175         /* Hard Coded.. 0xfff VLAN ID mask */
2176         bp->vlan = rte_le_to_cpu_16(resp->vlan) & 0xfff;
2177
2178         switch (resp->port_partition_type) {
2179         case HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR1_0:
2180         case HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR1_5:
2181         case HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR2_0:
2182                 bp->port_partition_type = resp->port_partition_type;
2183                 break;
2184         default:
2185                 bp->port_partition_type = 0;
2186                 break;
2187         }
2188
2189         HWRM_UNLOCK();
2190
2191         return rc;
2192 }
2193
2194 static void copy_func_cfg_to_qcaps(struct hwrm_func_cfg_input *fcfg,
2195                                    struct hwrm_func_qcaps_output *qcaps)
2196 {
2197         qcaps->max_rsscos_ctx = fcfg->num_rsscos_ctxs;
2198         memcpy(qcaps->mac_address, fcfg->dflt_mac_addr,
2199                sizeof(qcaps->mac_address));
2200         qcaps->max_l2_ctxs = fcfg->num_l2_ctxs;
2201         qcaps->max_rx_rings = fcfg->num_rx_rings;
2202         qcaps->max_tx_rings = fcfg->num_tx_rings;
2203         qcaps->max_cmpl_rings = fcfg->num_cmpl_rings;
2204         qcaps->max_stat_ctx = fcfg->num_stat_ctxs;
2205         qcaps->max_vfs = 0;
2206         qcaps->first_vf_id = 0;
2207         qcaps->max_vnics = fcfg->num_vnics;
2208         qcaps->max_decap_records = 0;
2209         qcaps->max_encap_records = 0;
2210         qcaps->max_tx_wm_flows = 0;
2211         qcaps->max_tx_em_flows = 0;
2212         qcaps->max_rx_wm_flows = 0;
2213         qcaps->max_rx_em_flows = 0;
2214         qcaps->max_flow_id = 0;
2215         qcaps->max_mcast_filters = fcfg->num_mcast_filters;
2216         qcaps->max_sp_tx_rings = 0;
2217         qcaps->max_hw_ring_grps = fcfg->num_hw_ring_grps;
2218 }
2219
2220 static int bnxt_hwrm_pf_func_cfg(struct bnxt *bp, int tx_rings)
2221 {
2222         struct hwrm_func_cfg_input req = {0};
2223         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2224         int rc;
2225
2226         req.enables = rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_MTU |
2227                         HWRM_FUNC_CFG_INPUT_ENABLES_MRU |
2228                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS |
2229                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_STAT_CTXS |
2230                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_CMPL_RINGS |
2231                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_TX_RINGS |
2232                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RX_RINGS |
2233                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_L2_CTXS |
2234                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_VNICS |
2235                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_HW_RING_GRPS);
2236         req.flags = rte_cpu_to_le_32(bp->pf.func_cfg_flags);
2237         req.mtu = rte_cpu_to_le_16(BNXT_MAX_MTU);
2238         req.mru = rte_cpu_to_le_16(bp->eth_dev->data->mtu + ETHER_HDR_LEN +
2239                                    ETHER_CRC_LEN + VLAN_TAG_SIZE);
2240         req.num_rsscos_ctxs = rte_cpu_to_le_16(bp->max_rsscos_ctx);
2241         req.num_stat_ctxs = rte_cpu_to_le_16(bp->max_stat_ctx);
2242         req.num_cmpl_rings = rte_cpu_to_le_16(bp->max_cp_rings);
2243         req.num_tx_rings = rte_cpu_to_le_16(tx_rings);
2244         req.num_rx_rings = rte_cpu_to_le_16(bp->max_rx_rings);
2245         req.num_l2_ctxs = rte_cpu_to_le_16(bp->max_l2_ctx);
2246         req.num_vnics = rte_cpu_to_le_16(bp->max_vnics);
2247         req.num_hw_ring_grps = rte_cpu_to_le_16(bp->max_ring_grps);
2248         req.fid = rte_cpu_to_le_16(0xffff);
2249
2250         HWRM_PREP(req, FUNC_CFG);
2251
2252         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2253
2254         HWRM_CHECK_RESULT();
2255         HWRM_UNLOCK();
2256
2257         return rc;
2258 }
2259
2260 static void populate_vf_func_cfg_req(struct bnxt *bp,
2261                                      struct hwrm_func_cfg_input *req,
2262                                      int num_vfs)
2263 {
2264         req->enables = rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_MTU |
2265                         HWRM_FUNC_CFG_INPUT_ENABLES_MRU |
2266                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS |
2267                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_STAT_CTXS |
2268                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_CMPL_RINGS |
2269                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_TX_RINGS |
2270                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RX_RINGS |
2271                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_L2_CTXS |
2272                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_VNICS |
2273                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_HW_RING_GRPS);
2274
2275         req->mtu = rte_cpu_to_le_16(bp->eth_dev->data->mtu + ETHER_HDR_LEN +
2276                                     ETHER_CRC_LEN + VLAN_TAG_SIZE);
2277         req->mru = rte_cpu_to_le_16(bp->eth_dev->data->mtu + ETHER_HDR_LEN +
2278                                     ETHER_CRC_LEN + VLAN_TAG_SIZE);
2279         req->num_rsscos_ctxs = rte_cpu_to_le_16(bp->max_rsscos_ctx /
2280                                                 (num_vfs + 1));
2281         req->num_stat_ctxs = rte_cpu_to_le_16(bp->max_stat_ctx / (num_vfs + 1));
2282         req->num_cmpl_rings = rte_cpu_to_le_16(bp->max_cp_rings /
2283                                                (num_vfs + 1));
2284         req->num_tx_rings = rte_cpu_to_le_16(bp->max_tx_rings / (num_vfs + 1));
2285         req->num_rx_rings = rte_cpu_to_le_16(bp->max_rx_rings / (num_vfs + 1));
2286         req->num_l2_ctxs = rte_cpu_to_le_16(bp->max_l2_ctx / (num_vfs + 1));
2287         /* TODO: For now, do not support VMDq/RFS on VFs. */
2288         req->num_vnics = rte_cpu_to_le_16(1);
2289         req->num_hw_ring_grps = rte_cpu_to_le_16(bp->max_ring_grps /
2290                                                  (num_vfs + 1));
2291 }
2292
2293 static void add_random_mac_if_needed(struct bnxt *bp,
2294                                      struct hwrm_func_cfg_input *cfg_req,
2295                                      int vf)
2296 {
2297         struct ether_addr mac;
2298
2299         if (bnxt_hwrm_func_qcfg_vf_default_mac(bp, vf, &mac))
2300                 return;
2301
2302         if (memcmp(mac.addr_bytes, "\x00\x00\x00\x00\x00", 6) == 0) {
2303                 cfg_req->enables |=
2304                 rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
2305                 eth_random_addr(cfg_req->dflt_mac_addr);
2306                 bp->pf.vf_info[vf].random_mac = true;
2307         } else {
2308                 memcpy(cfg_req->dflt_mac_addr, mac.addr_bytes, ETHER_ADDR_LEN);
2309         }
2310 }
2311
2312 static void reserve_resources_from_vf(struct bnxt *bp,
2313                                       struct hwrm_func_cfg_input *cfg_req,
2314                                       int vf)
2315 {
2316         struct hwrm_func_qcaps_input req = {0};
2317         struct hwrm_func_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
2318         int rc;
2319
2320         /* Get the actual allocated values now */
2321         HWRM_PREP(req, FUNC_QCAPS);
2322         req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
2323         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2324
2325         if (rc) {
2326                 RTE_LOG(ERR, PMD, "hwrm_func_qcaps failed rc:%d\n", rc);
2327                 copy_func_cfg_to_qcaps(cfg_req, resp);
2328         } else if (resp->error_code) {
2329                 rc = rte_le_to_cpu_16(resp->error_code);
2330                 RTE_LOG(ERR, PMD, "hwrm_func_qcaps error %d\n", rc);
2331                 copy_func_cfg_to_qcaps(cfg_req, resp);
2332         }
2333
2334         bp->max_rsscos_ctx -= rte_le_to_cpu_16(resp->max_rsscos_ctx);
2335         bp->max_stat_ctx -= rte_le_to_cpu_16(resp->max_stat_ctx);
2336         bp->max_cp_rings -= rte_le_to_cpu_16(resp->max_cmpl_rings);
2337         bp->max_tx_rings -= rte_le_to_cpu_16(resp->max_tx_rings);
2338         bp->max_rx_rings -= rte_le_to_cpu_16(resp->max_rx_rings);
2339         bp->max_l2_ctx -= rte_le_to_cpu_16(resp->max_l2_ctxs);
2340         /*
2341          * TODO: While not supporting VMDq with VFs, max_vnics is always
2342          * forced to 1 in this case
2343          */
2344         //bp->max_vnics -= rte_le_to_cpu_16(esp->max_vnics);
2345         bp->max_ring_grps -= rte_le_to_cpu_16(resp->max_hw_ring_grps);
2346
2347         HWRM_UNLOCK();
2348 }
2349
2350 int bnxt_hwrm_func_qcfg_current_vf_vlan(struct bnxt *bp, int vf)
2351 {
2352         struct hwrm_func_qcfg_input req = {0};
2353         struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
2354         int rc;
2355
2356         /* Check for zero MAC address */
2357         HWRM_PREP(req, FUNC_QCFG);
2358         req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
2359         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2360         if (rc) {
2361                 RTE_LOG(ERR, PMD, "hwrm_func_qcfg failed rc:%d\n", rc);
2362                 return -1;
2363         } else if (resp->error_code) {
2364                 rc = rte_le_to_cpu_16(resp->error_code);
2365                 RTE_LOG(ERR, PMD, "hwrm_func_qcfg error %d\n", rc);
2366                 return -1;
2367         }
2368         rc = rte_le_to_cpu_16(resp->vlan);
2369
2370         HWRM_UNLOCK();
2371
2372         return rc;
2373 }
2374
2375 static int update_pf_resource_max(struct bnxt *bp)
2376 {
2377         struct hwrm_func_qcfg_input req = {0};
2378         struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
2379         int rc;
2380
2381         /* And copy the allocated numbers into the pf struct */
2382         HWRM_PREP(req, FUNC_QCFG);
2383         req.fid = rte_cpu_to_le_16(0xffff);
2384         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2385         HWRM_CHECK_RESULT();
2386
2387         /* Only TX ring value reflects actual allocation? TODO */
2388         bp->max_tx_rings = rte_le_to_cpu_16(resp->alloc_tx_rings);
2389         bp->pf.evb_mode = resp->evb_mode;
2390
2391         HWRM_UNLOCK();
2392
2393         return rc;
2394 }
2395
2396 int bnxt_hwrm_allocate_pf_only(struct bnxt *bp)
2397 {
2398         int rc;
2399
2400         if (!BNXT_PF(bp)) {
2401                 RTE_LOG(ERR, PMD, "Attempt to allcoate VFs on a VF!\n");
2402                 return -1;
2403         }
2404
2405         rc = bnxt_hwrm_func_qcaps(bp);
2406         if (rc)
2407                 return rc;
2408
2409         bp->pf.func_cfg_flags &=
2410                 ~(HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_ENABLE |
2411                   HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_DISABLE);
2412         bp->pf.func_cfg_flags |=
2413                 HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_DISABLE;
2414         rc = bnxt_hwrm_pf_func_cfg(bp, bp->max_tx_rings);
2415         return rc;
2416 }
2417
2418 int bnxt_hwrm_allocate_vfs(struct bnxt *bp, int num_vfs)
2419 {
2420         struct hwrm_func_cfg_input req = {0};
2421         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2422         int i;
2423         size_t sz;
2424         int rc = 0;
2425         size_t req_buf_sz;
2426
2427         if (!BNXT_PF(bp)) {
2428                 RTE_LOG(ERR, PMD, "Attempt to allcoate VFs on a VF!\n");
2429                 return -1;
2430         }
2431
2432         rc = bnxt_hwrm_func_qcaps(bp);
2433
2434         if (rc)
2435                 return rc;
2436
2437         bp->pf.active_vfs = num_vfs;
2438
2439         /*
2440          * First, configure the PF to only use one TX ring.  This ensures that
2441          * there are enough rings for all VFs.
2442          *
2443          * If we don't do this, when we call func_alloc() later, we will lock
2444          * extra rings to the PF that won't be available during func_cfg() of
2445          * the VFs.
2446          *
2447          * This has been fixed with firmware versions above 20.6.54
2448          */
2449         bp->pf.func_cfg_flags &=
2450                 ~(HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_ENABLE |
2451                   HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_DISABLE);
2452         bp->pf.func_cfg_flags |=
2453                 HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_ENABLE;
2454         rc = bnxt_hwrm_pf_func_cfg(bp, 1);
2455         if (rc)
2456                 return rc;
2457
2458         /*
2459          * Now, create and register a buffer to hold forwarded VF requests
2460          */
2461         req_buf_sz = num_vfs * HWRM_MAX_REQ_LEN;
2462         bp->pf.vf_req_buf = rte_malloc("bnxt_vf_fwd", req_buf_sz,
2463                 page_roundup(num_vfs * HWRM_MAX_REQ_LEN));
2464         if (bp->pf.vf_req_buf == NULL) {
2465                 rc = -ENOMEM;
2466                 goto error_free;
2467         }
2468         for (sz = 0; sz < req_buf_sz; sz += getpagesize())
2469                 rte_mem_lock_page(((char *)bp->pf.vf_req_buf) + sz);
2470         for (i = 0; i < num_vfs; i++)
2471                 bp->pf.vf_info[i].req_buf = ((char *)bp->pf.vf_req_buf) +
2472                                         (i * HWRM_MAX_REQ_LEN);
2473
2474         rc = bnxt_hwrm_func_buf_rgtr(bp);
2475         if (rc)
2476                 goto error_free;
2477
2478         populate_vf_func_cfg_req(bp, &req, num_vfs);
2479
2480         bp->pf.active_vfs = 0;
2481         for (i = 0; i < num_vfs; i++) {
2482                 add_random_mac_if_needed(bp, &req, i);
2483
2484                 HWRM_PREP(req, FUNC_CFG);
2485                 req.flags = rte_cpu_to_le_32(bp->pf.vf_info[i].func_cfg_flags);
2486                 req.fid = rte_cpu_to_le_16(bp->pf.vf_info[i].fid);
2487                 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2488
2489                 /* Clear enable flag for next pass */
2490                 req.enables &= ~rte_cpu_to_le_32(
2491                                 HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
2492
2493                 if (rc || resp->error_code) {
2494                         RTE_LOG(ERR, PMD,
2495                                 "Failed to initizlie VF %d\n", i);
2496                         RTE_LOG(ERR, PMD,
2497                                 "Not all VFs available. (%d, %d)\n",
2498                                 rc, resp->error_code);
2499                         HWRM_UNLOCK();
2500                         break;
2501                 }
2502
2503                 HWRM_UNLOCK();
2504
2505                 reserve_resources_from_vf(bp, &req, i);
2506                 bp->pf.active_vfs++;
2507                 bnxt_hwrm_func_clr_stats(bp, bp->pf.vf_info[i].fid);
2508         }
2509
2510         /*
2511          * Now configure the PF to use "the rest" of the resources
2512          * We're using STD_TX_RING_MODE here though which will limit the TX
2513          * rings.  This will allow QoS to function properly.  Not setting this
2514          * will cause PF rings to break bandwidth settings.
2515          */
2516         rc = bnxt_hwrm_pf_func_cfg(bp, bp->max_tx_rings);
2517         if (rc)
2518                 goto error_free;
2519
2520         rc = update_pf_resource_max(bp);
2521         if (rc)
2522                 goto error_free;
2523
2524         return rc;
2525
2526 error_free:
2527         bnxt_hwrm_func_buf_unrgtr(bp);
2528         return rc;
2529 }
2530
2531 int bnxt_hwrm_pf_evb_mode(struct bnxt *bp)
2532 {
2533         struct hwrm_func_cfg_input req = {0};
2534         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2535         int rc;
2536
2537         HWRM_PREP(req, FUNC_CFG);
2538
2539         req.fid = rte_cpu_to_le_16(0xffff);
2540         req.enables = rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_EVB_MODE);
2541         req.evb_mode = bp->pf.evb_mode;
2542
2543         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2544         HWRM_CHECK_RESULT();
2545         HWRM_UNLOCK();
2546
2547         return rc;
2548 }
2549
2550 int bnxt_hwrm_tunnel_dst_port_alloc(struct bnxt *bp, uint16_t port,
2551                                 uint8_t tunnel_type)
2552 {
2553         struct hwrm_tunnel_dst_port_alloc_input req = {0};
2554         struct hwrm_tunnel_dst_port_alloc_output *resp = bp->hwrm_cmd_resp_addr;
2555         int rc = 0;
2556
2557         HWRM_PREP(req, TUNNEL_DST_PORT_ALLOC);
2558         req.tunnel_type = tunnel_type;
2559         req.tunnel_dst_port_val = port;
2560         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2561         HWRM_CHECK_RESULT();
2562
2563         switch (tunnel_type) {
2564         case HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN:
2565                 bp->vxlan_fw_dst_port_id = resp->tunnel_dst_port_id;
2566                 bp->vxlan_port = port;
2567                 break;
2568         case HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_GENEVE:
2569                 bp->geneve_fw_dst_port_id = resp->tunnel_dst_port_id;
2570                 bp->geneve_port = port;
2571                 break;
2572         default:
2573                 break;
2574         }
2575
2576         HWRM_UNLOCK();
2577
2578         return rc;
2579 }
2580
2581 int bnxt_hwrm_tunnel_dst_port_free(struct bnxt *bp, uint16_t port,
2582                                 uint8_t tunnel_type)
2583 {
2584         struct hwrm_tunnel_dst_port_free_input req = {0};
2585         struct hwrm_tunnel_dst_port_free_output *resp = bp->hwrm_cmd_resp_addr;
2586         int rc = 0;
2587
2588         HWRM_PREP(req, TUNNEL_DST_PORT_FREE);
2589
2590         req.tunnel_type = tunnel_type;
2591         req.tunnel_dst_port_id = rte_cpu_to_be_16(port);
2592         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2593
2594         HWRM_CHECK_RESULT();
2595         HWRM_UNLOCK();
2596
2597         return rc;
2598 }
2599
2600 int bnxt_hwrm_func_cfg_vf_set_flags(struct bnxt *bp, uint16_t vf,
2601                                         uint32_t flags)
2602 {
2603         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2604         struct hwrm_func_cfg_input req = {0};
2605         int rc;
2606
2607         HWRM_PREP(req, FUNC_CFG);
2608
2609         req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
2610         req.flags = rte_cpu_to_le_32(flags);
2611         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2612
2613         HWRM_CHECK_RESULT();
2614         HWRM_UNLOCK();
2615
2616         return rc;
2617 }
2618
2619 void vf_vnic_set_rxmask_cb(struct bnxt_vnic_info *vnic, void *flagp)
2620 {
2621         uint32_t *flag = flagp;
2622
2623         vnic->flags = *flag;
2624 }
2625
2626 int bnxt_set_rx_mask_no_vlan(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2627 {
2628         return bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
2629 }
2630
2631 int bnxt_hwrm_func_buf_rgtr(struct bnxt *bp)
2632 {
2633         int rc = 0;
2634         struct hwrm_func_buf_rgtr_input req = {.req_type = 0 };
2635         struct hwrm_func_buf_rgtr_output *resp = bp->hwrm_cmd_resp_addr;
2636
2637         HWRM_PREP(req, FUNC_BUF_RGTR);
2638
2639         req.req_buf_num_pages = rte_cpu_to_le_16(1);
2640         req.req_buf_page_size = rte_cpu_to_le_16(
2641                          page_getenum(bp->pf.active_vfs * HWRM_MAX_REQ_LEN));
2642         req.req_buf_len = rte_cpu_to_le_16(HWRM_MAX_REQ_LEN);
2643         req.req_buf_page_addr[0] =
2644                 rte_cpu_to_le_64(rte_mem_virt2iova(bp->pf.vf_req_buf));
2645         if (req.req_buf_page_addr[0] == 0) {
2646                 RTE_LOG(ERR, PMD,
2647                         "unable to map buffer address to physical memory\n");
2648                 return -ENOMEM;
2649         }
2650
2651         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2652
2653         HWRM_CHECK_RESULT();
2654         HWRM_UNLOCK();
2655
2656         return rc;
2657 }
2658
2659 int bnxt_hwrm_func_buf_unrgtr(struct bnxt *bp)
2660 {
2661         int rc = 0;
2662         struct hwrm_func_buf_unrgtr_input req = {.req_type = 0 };
2663         struct hwrm_func_buf_unrgtr_output *resp = bp->hwrm_cmd_resp_addr;
2664
2665         HWRM_PREP(req, FUNC_BUF_UNRGTR);
2666
2667         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2668
2669         HWRM_CHECK_RESULT();
2670         HWRM_UNLOCK();
2671
2672         return rc;
2673 }
2674
2675 int bnxt_hwrm_func_cfg_def_cp(struct bnxt *bp)
2676 {
2677         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2678         struct hwrm_func_cfg_input req = {0};
2679         int rc;
2680
2681         HWRM_PREP(req, FUNC_CFG);
2682
2683         req.fid = rte_cpu_to_le_16(0xffff);
2684         req.flags = rte_cpu_to_le_32(bp->pf.func_cfg_flags);
2685         req.enables = rte_cpu_to_le_32(
2686                         HWRM_FUNC_CFG_INPUT_ENABLES_ASYNC_EVENT_CR);
2687         req.async_event_cr = rte_cpu_to_le_16(
2688                         bp->def_cp_ring->cp_ring_struct->fw_ring_id);
2689         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2690
2691         HWRM_CHECK_RESULT();
2692         HWRM_UNLOCK();
2693
2694         return rc;
2695 }
2696
2697 int bnxt_hwrm_vf_func_cfg_def_cp(struct bnxt *bp)
2698 {
2699         struct hwrm_func_vf_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2700         struct hwrm_func_vf_cfg_input req = {0};
2701         int rc;
2702
2703         HWRM_PREP(req, FUNC_VF_CFG);
2704
2705         req.enables = rte_cpu_to_le_32(
2706                         HWRM_FUNC_CFG_INPUT_ENABLES_ASYNC_EVENT_CR);
2707         req.async_event_cr = rte_cpu_to_le_16(
2708                         bp->def_cp_ring->cp_ring_struct->fw_ring_id);
2709         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2710
2711         HWRM_CHECK_RESULT();
2712         HWRM_UNLOCK();
2713
2714         return rc;
2715 }
2716
2717 int bnxt_hwrm_set_default_vlan(struct bnxt *bp, int vf, uint8_t is_vf)
2718 {
2719         struct hwrm_func_cfg_input req = {0};
2720         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2721         uint16_t dflt_vlan, fid;
2722         uint32_t func_cfg_flags;
2723         int rc = 0;
2724
2725         HWRM_PREP(req, FUNC_CFG);
2726
2727         if (is_vf) {
2728                 dflt_vlan = bp->pf.vf_info[vf].dflt_vlan;
2729                 fid = bp->pf.vf_info[vf].fid;
2730                 func_cfg_flags = bp->pf.vf_info[vf].func_cfg_flags;
2731         } else {
2732                 fid = rte_cpu_to_le_16(0xffff);
2733                 func_cfg_flags = bp->pf.func_cfg_flags;
2734                 dflt_vlan = bp->vlan;
2735         }
2736
2737         req.flags = rte_cpu_to_le_32(func_cfg_flags);
2738         req.fid = rte_cpu_to_le_16(fid);
2739         req.enables |= rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_VLAN);
2740         req.dflt_vlan = rte_cpu_to_le_16(dflt_vlan);
2741
2742         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2743
2744         HWRM_CHECK_RESULT();
2745         HWRM_UNLOCK();
2746
2747         return rc;
2748 }
2749
2750 int bnxt_hwrm_func_bw_cfg(struct bnxt *bp, uint16_t vf,
2751                         uint16_t max_bw, uint16_t enables)
2752 {
2753         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2754         struct hwrm_func_cfg_input req = {0};
2755         int rc;
2756
2757         HWRM_PREP(req, FUNC_CFG);
2758
2759         req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
2760         req.enables |= rte_cpu_to_le_32(enables);
2761         req.flags = rte_cpu_to_le_32(bp->pf.vf_info[vf].func_cfg_flags);
2762         req.max_bw = rte_cpu_to_le_32(max_bw);
2763         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2764
2765         HWRM_CHECK_RESULT();
2766         HWRM_UNLOCK();
2767
2768         return rc;
2769 }
2770
2771 int bnxt_hwrm_set_vf_vlan(struct bnxt *bp, int vf)
2772 {
2773         struct hwrm_func_cfg_input req = {0};
2774         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2775         int rc = 0;
2776
2777         HWRM_PREP(req, FUNC_CFG);
2778
2779         req.flags = rte_cpu_to_le_32(bp->pf.vf_info[vf].func_cfg_flags);
2780         req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
2781         req.enables |= rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_VLAN);
2782         req.dflt_vlan = rte_cpu_to_le_16(bp->pf.vf_info[vf].dflt_vlan);
2783
2784         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2785
2786         HWRM_CHECK_RESULT();
2787         HWRM_UNLOCK();
2788
2789         return rc;
2790 }
2791
2792 int bnxt_hwrm_reject_fwd_resp(struct bnxt *bp, uint16_t target_id,
2793                               void *encaped, size_t ec_size)
2794 {
2795         int rc = 0;
2796         struct hwrm_reject_fwd_resp_input req = {.req_type = 0};
2797         struct hwrm_reject_fwd_resp_output *resp = bp->hwrm_cmd_resp_addr;
2798
2799         if (ec_size > sizeof(req.encap_request))
2800                 return -1;
2801
2802         HWRM_PREP(req, REJECT_FWD_RESP);
2803
2804         req.encap_resp_target_id = rte_cpu_to_le_16(target_id);
2805         memcpy(req.encap_request, encaped, ec_size);
2806
2807         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2808
2809         HWRM_CHECK_RESULT();
2810         HWRM_UNLOCK();
2811
2812         return rc;
2813 }
2814
2815 int bnxt_hwrm_func_qcfg_vf_default_mac(struct bnxt *bp, uint16_t vf,
2816                                        struct ether_addr *mac)
2817 {
2818         struct hwrm_func_qcfg_input req = {0};
2819         struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
2820         int rc;
2821
2822         HWRM_PREP(req, FUNC_QCFG);
2823
2824         req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
2825         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2826
2827         HWRM_CHECK_RESULT();
2828
2829         memcpy(mac->addr_bytes, resp->mac_address, ETHER_ADDR_LEN);
2830
2831         HWRM_UNLOCK();
2832
2833         return rc;
2834 }
2835
2836 int bnxt_hwrm_exec_fwd_resp(struct bnxt *bp, uint16_t target_id,
2837                             void *encaped, size_t ec_size)
2838 {
2839         int rc = 0;
2840         struct hwrm_exec_fwd_resp_input req = {.req_type = 0};
2841         struct hwrm_exec_fwd_resp_output *resp = bp->hwrm_cmd_resp_addr;
2842
2843         if (ec_size > sizeof(req.encap_request))
2844                 return -1;
2845
2846         HWRM_PREP(req, EXEC_FWD_RESP);
2847
2848         req.encap_resp_target_id = rte_cpu_to_le_16(target_id);
2849         memcpy(req.encap_request, encaped, ec_size);
2850
2851         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2852
2853         HWRM_CHECK_RESULT();
2854         HWRM_UNLOCK();
2855
2856         return rc;
2857 }
2858
2859 int bnxt_hwrm_ctx_qstats(struct bnxt *bp, uint32_t cid, int idx,
2860                          struct rte_eth_stats *stats, uint8_t rx)
2861 {
2862         int rc = 0;
2863         struct hwrm_stat_ctx_query_input req = {.req_type = 0};
2864         struct hwrm_stat_ctx_query_output *resp = bp->hwrm_cmd_resp_addr;
2865
2866         HWRM_PREP(req, STAT_CTX_QUERY);
2867
2868         req.stat_ctx_id = rte_cpu_to_le_32(cid);
2869
2870         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2871
2872         HWRM_CHECK_RESULT();
2873
2874         if (rx) {
2875                 stats->q_ipackets[idx] = rte_le_to_cpu_64(resp->rx_ucast_pkts);
2876                 stats->q_ipackets[idx] += rte_le_to_cpu_64(resp->rx_mcast_pkts);
2877                 stats->q_ipackets[idx] += rte_le_to_cpu_64(resp->rx_bcast_pkts);
2878                 stats->q_ibytes[idx] = rte_le_to_cpu_64(resp->rx_ucast_bytes);
2879                 stats->q_ibytes[idx] += rte_le_to_cpu_64(resp->rx_mcast_bytes);
2880                 stats->q_ibytes[idx] += rte_le_to_cpu_64(resp->rx_bcast_bytes);
2881                 stats->q_errors[idx] = rte_le_to_cpu_64(resp->rx_err_pkts);
2882                 stats->q_errors[idx] += rte_le_to_cpu_64(resp->rx_drop_pkts);
2883         } else {
2884                 stats->q_opackets[idx] = rte_le_to_cpu_64(resp->tx_ucast_pkts);
2885                 stats->q_opackets[idx] += rte_le_to_cpu_64(resp->tx_mcast_pkts);
2886                 stats->q_opackets[idx] += rte_le_to_cpu_64(resp->tx_bcast_pkts);
2887                 stats->q_obytes[idx] = rte_le_to_cpu_64(resp->tx_ucast_bytes);
2888                 stats->q_obytes[idx] += rte_le_to_cpu_64(resp->tx_mcast_bytes);
2889                 stats->q_obytes[idx] += rte_le_to_cpu_64(resp->tx_bcast_bytes);
2890                 stats->q_errors[idx] += rte_le_to_cpu_64(resp->tx_err_pkts);
2891         }
2892
2893
2894         HWRM_UNLOCK();
2895
2896         return rc;
2897 }
2898
2899 int bnxt_hwrm_port_qstats(struct bnxt *bp)
2900 {
2901         struct hwrm_port_qstats_input req = {0};
2902         struct hwrm_port_qstats_output *resp = bp->hwrm_cmd_resp_addr;
2903         struct bnxt_pf_info *pf = &bp->pf;
2904         int rc;
2905
2906         if (!(bp->flags & BNXT_FLAG_PORT_STATS))
2907                 return 0;
2908
2909         HWRM_PREP(req, PORT_QSTATS);
2910
2911         req.port_id = rte_cpu_to_le_16(pf->port_id);
2912         req.tx_stat_host_addr = rte_cpu_to_le_64(bp->hw_tx_port_stats_map);
2913         req.rx_stat_host_addr = rte_cpu_to_le_64(bp->hw_rx_port_stats_map);
2914         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2915
2916         HWRM_CHECK_RESULT();
2917         HWRM_UNLOCK();
2918
2919         return rc;
2920 }
2921
2922 int bnxt_hwrm_port_clr_stats(struct bnxt *bp)
2923 {
2924         struct hwrm_port_clr_stats_input req = {0};
2925         struct hwrm_port_clr_stats_output *resp = bp->hwrm_cmd_resp_addr;
2926         struct bnxt_pf_info *pf = &bp->pf;
2927         int rc;
2928
2929         if (!(bp->flags & BNXT_FLAG_PORT_STATS))
2930                 return 0;
2931
2932         HWRM_PREP(req, PORT_CLR_STATS);
2933
2934         req.port_id = rte_cpu_to_le_16(pf->port_id);
2935         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2936
2937         HWRM_CHECK_RESULT();
2938         HWRM_UNLOCK();
2939
2940         return rc;
2941 }
2942
2943 int bnxt_hwrm_port_led_qcaps(struct bnxt *bp)
2944 {
2945         struct hwrm_port_led_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
2946         struct hwrm_port_led_qcaps_input req = {0};
2947         int rc;
2948
2949         if (BNXT_VF(bp))
2950                 return 0;
2951
2952         HWRM_PREP(req, PORT_LED_QCAPS);
2953         req.port_id = bp->pf.port_id;
2954         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2955
2956         HWRM_CHECK_RESULT();
2957
2958         if (resp->num_leds > 0 && resp->num_leds < BNXT_MAX_LED) {
2959                 unsigned int i;
2960
2961                 bp->num_leds = resp->num_leds;
2962                 memcpy(bp->leds, &resp->led0_id,
2963                         sizeof(bp->leds[0]) * bp->num_leds);
2964                 for (i = 0; i < bp->num_leds; i++) {
2965                         struct bnxt_led_info *led = &bp->leds[i];
2966
2967                         uint16_t caps = led->led_state_caps;
2968
2969                         if (!led->led_group_id ||
2970                                 !BNXT_LED_ALT_BLINK_CAP(caps)) {
2971                                 bp->num_leds = 0;
2972                                 break;
2973                         }
2974                 }
2975         }
2976
2977         HWRM_UNLOCK();
2978
2979         return rc;
2980 }
2981
2982 int bnxt_hwrm_port_led_cfg(struct bnxt *bp, bool led_on)
2983 {
2984         struct hwrm_port_led_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2985         struct hwrm_port_led_cfg_input req = {0};
2986         struct bnxt_led_cfg *led_cfg;
2987         uint8_t led_state = HWRM_PORT_LED_QCFG_OUTPUT_LED0_STATE_DEFAULT;
2988         uint16_t duration = 0;
2989         int rc, i;
2990
2991         if (!bp->num_leds || BNXT_VF(bp))
2992                 return -EOPNOTSUPP;
2993
2994         HWRM_PREP(req, PORT_LED_CFG);
2995
2996         if (led_on) {
2997                 led_state = HWRM_PORT_LED_CFG_INPUT_LED0_STATE_BLINKALT;
2998                 duration = rte_cpu_to_le_16(500);
2999         }
3000         req.port_id = bp->pf.port_id;
3001         req.num_leds = bp->num_leds;
3002         led_cfg = (struct bnxt_led_cfg *)&req.led0_id;
3003         for (i = 0; i < bp->num_leds; i++, led_cfg++) {
3004                 req.enables |= BNXT_LED_DFLT_ENABLES(i);
3005                 led_cfg->led_id = bp->leds[i].led_id;
3006                 led_cfg->led_state = led_state;
3007                 led_cfg->led_blink_on = duration;
3008                 led_cfg->led_blink_off = duration;
3009                 led_cfg->led_group_id = bp->leds[i].led_group_id;
3010         }
3011
3012         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
3013
3014         HWRM_CHECK_RESULT();
3015         HWRM_UNLOCK();
3016
3017         return rc;
3018 }
3019
3020 int bnxt_hwrm_nvm_get_dir_info(struct bnxt *bp, uint32_t *entries,
3021                                uint32_t *length)
3022 {
3023         int rc;
3024         struct hwrm_nvm_get_dir_info_input req = {0};
3025         struct hwrm_nvm_get_dir_info_output *resp = bp->hwrm_cmd_resp_addr;
3026
3027         HWRM_PREP(req, NVM_GET_DIR_INFO);
3028
3029         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
3030
3031         HWRM_CHECK_RESULT();
3032         HWRM_UNLOCK();
3033
3034         if (!rc) {
3035                 *entries = rte_le_to_cpu_32(resp->entries);
3036                 *length = rte_le_to_cpu_32(resp->entry_length);
3037         }
3038         return rc;
3039 }
3040
3041 int bnxt_get_nvram_directory(struct bnxt *bp, uint32_t len, uint8_t *data)
3042 {
3043         int rc;
3044         uint32_t dir_entries;
3045         uint32_t entry_length;
3046         uint8_t *buf;
3047         size_t buflen;
3048         rte_iova_t dma_handle;
3049         struct hwrm_nvm_get_dir_entries_input req = {0};
3050         struct hwrm_nvm_get_dir_entries_output *resp = bp->hwrm_cmd_resp_addr;
3051
3052         rc = bnxt_hwrm_nvm_get_dir_info(bp, &dir_entries, &entry_length);
3053         if (rc != 0)
3054                 return rc;
3055
3056         *data++ = dir_entries;
3057         *data++ = entry_length;
3058         len -= 2;
3059         memset(data, 0xff, len);
3060
3061         buflen = dir_entries * entry_length;
3062         buf = rte_malloc("nvm_dir", buflen, 0);
3063         rte_mem_lock_page(buf);
3064         if (buf == NULL)
3065                 return -ENOMEM;
3066         dma_handle = rte_mem_virt2iova(buf);
3067         if (dma_handle == 0) {
3068                 RTE_LOG(ERR, PMD,
3069                         "unable to map response address to physical memory\n");
3070                 return -ENOMEM;
3071         }
3072         HWRM_PREP(req, NVM_GET_DIR_ENTRIES);
3073         req.host_dest_addr = rte_cpu_to_le_64(dma_handle);
3074         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
3075
3076         HWRM_CHECK_RESULT();
3077         HWRM_UNLOCK();
3078
3079         if (rc == 0)
3080                 memcpy(data, buf, len > buflen ? buflen : len);
3081
3082         rte_free(buf);
3083
3084         return rc;
3085 }
3086
3087 int bnxt_hwrm_get_nvram_item(struct bnxt *bp, uint32_t index,
3088                              uint32_t offset, uint32_t length,
3089                              uint8_t *data)
3090 {
3091         int rc;
3092         uint8_t *buf;
3093         rte_iova_t dma_handle;
3094         struct hwrm_nvm_read_input req = {0};
3095         struct hwrm_nvm_read_output *resp = bp->hwrm_cmd_resp_addr;
3096
3097         buf = rte_malloc("nvm_item", length, 0);
3098         rte_mem_lock_page(buf);
3099         if (!buf)
3100                 return -ENOMEM;
3101
3102         dma_handle = rte_mem_virt2iova(buf);
3103         if (dma_handle == 0) {
3104                 RTE_LOG(ERR, PMD,
3105                         "unable to map response address to physical memory\n");
3106                 return -ENOMEM;
3107         }
3108         HWRM_PREP(req, NVM_READ);
3109         req.host_dest_addr = rte_cpu_to_le_64(dma_handle);
3110         req.dir_idx = rte_cpu_to_le_16(index);
3111         req.offset = rte_cpu_to_le_32(offset);
3112         req.len = rte_cpu_to_le_32(length);
3113         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
3114         HWRM_CHECK_RESULT();
3115         HWRM_UNLOCK();
3116         if (rc == 0)
3117                 memcpy(data, buf, length);
3118
3119         rte_free(buf);
3120         return rc;
3121 }
3122
3123 int bnxt_hwrm_erase_nvram_directory(struct bnxt *bp, uint8_t index)
3124 {
3125         int rc;
3126         struct hwrm_nvm_erase_dir_entry_input req = {0};
3127         struct hwrm_nvm_erase_dir_entry_output *resp = bp->hwrm_cmd_resp_addr;
3128
3129         HWRM_PREP(req, NVM_ERASE_DIR_ENTRY);
3130         req.dir_idx = rte_cpu_to_le_16(index);
3131         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
3132         HWRM_CHECK_RESULT();
3133         HWRM_UNLOCK();
3134
3135         return rc;
3136 }
3137
3138
3139 int bnxt_hwrm_flash_nvram(struct bnxt *bp, uint16_t dir_type,
3140                           uint16_t dir_ordinal, uint16_t dir_ext,
3141                           uint16_t dir_attr, const uint8_t *data,
3142                           size_t data_len)
3143 {
3144         int rc;
3145         struct hwrm_nvm_write_input req = {0};
3146         struct hwrm_nvm_write_output *resp = bp->hwrm_cmd_resp_addr;
3147         rte_iova_t dma_handle;
3148         uint8_t *buf;
3149
3150         HWRM_PREP(req, NVM_WRITE);
3151
3152         req.dir_type = rte_cpu_to_le_16(dir_type);
3153         req.dir_ordinal = rte_cpu_to_le_16(dir_ordinal);
3154         req.dir_ext = rte_cpu_to_le_16(dir_ext);
3155         req.dir_attr = rte_cpu_to_le_16(dir_attr);
3156         req.dir_data_length = rte_cpu_to_le_32(data_len);
3157
3158         buf = rte_malloc("nvm_write", data_len, 0);
3159         rte_mem_lock_page(buf);
3160         if (!buf)
3161                 return -ENOMEM;
3162
3163         dma_handle = rte_mem_virt2iova(buf);
3164         if (dma_handle == 0) {
3165                 RTE_LOG(ERR, PMD,
3166                         "unable to map response address to physical memory\n");
3167                 return -ENOMEM;
3168         }
3169         memcpy(buf, data, data_len);
3170         req.host_src_addr = rte_cpu_to_le_64(dma_handle);
3171
3172         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
3173
3174         HWRM_CHECK_RESULT();
3175         HWRM_UNLOCK();
3176
3177         rte_free(buf);
3178         return rc;
3179 }
3180
3181 static void
3182 bnxt_vnic_count(struct bnxt_vnic_info *vnic __rte_unused, void *cbdata)
3183 {
3184         uint32_t *count = cbdata;
3185
3186         *count = *count + 1;
3187 }
3188
3189 static int bnxt_vnic_count_hwrm_stub(struct bnxt *bp __rte_unused,
3190                                      struct bnxt_vnic_info *vnic __rte_unused)
3191 {
3192         return 0;
3193 }
3194
3195 int bnxt_vf_vnic_count(struct bnxt *bp, uint16_t vf)
3196 {
3197         uint32_t count = 0;
3198
3199         bnxt_hwrm_func_vf_vnic_query_and_config(bp, vf, bnxt_vnic_count,
3200             &count, bnxt_vnic_count_hwrm_stub);
3201
3202         return count;
3203 }
3204
3205 static int bnxt_hwrm_func_vf_vnic_query(struct bnxt *bp, uint16_t vf,
3206                                         uint16_t *vnic_ids)
3207 {
3208         struct hwrm_func_vf_vnic_ids_query_input req = {0};
3209         struct hwrm_func_vf_vnic_ids_query_output *resp =
3210                                                 bp->hwrm_cmd_resp_addr;
3211         int rc;
3212
3213         /* First query all VNIC ids */
3214         HWRM_PREP(req, FUNC_VF_VNIC_IDS_QUERY);
3215
3216         req.vf_id = rte_cpu_to_le_16(bp->pf.first_vf_id + vf);
3217         req.max_vnic_id_cnt = rte_cpu_to_le_32(bp->pf.total_vnics);
3218         req.vnic_id_tbl_addr = rte_cpu_to_le_64(rte_mem_virt2iova(vnic_ids));
3219
3220         if (req.vnic_id_tbl_addr == 0) {
3221                 HWRM_UNLOCK();
3222                 RTE_LOG(ERR, PMD,
3223                 "unable to map VNIC ID table address to physical memory\n");
3224                 return -ENOMEM;
3225         }
3226         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
3227         if (rc) {
3228                 HWRM_UNLOCK();
3229                 RTE_LOG(ERR, PMD, "hwrm_func_vf_vnic_query failed rc:%d\n", rc);
3230                 return -1;
3231         } else if (resp->error_code) {
3232                 rc = rte_le_to_cpu_16(resp->error_code);
3233                 HWRM_UNLOCK();
3234                 RTE_LOG(ERR, PMD, "hwrm_func_vf_vnic_query error %d\n", rc);
3235                 return -1;
3236         }
3237         rc = rte_le_to_cpu_32(resp->vnic_id_cnt);
3238
3239         HWRM_UNLOCK();
3240
3241         return rc;
3242 }
3243
3244 /*
3245  * This function queries the VNIC IDs  for a specified VF. It then calls
3246  * the vnic_cb to update the necessary field in vnic_info with cbdata.
3247  * Then it calls the hwrm_cb function to program this new vnic configuration.
3248  */
3249 int bnxt_hwrm_func_vf_vnic_query_and_config(struct bnxt *bp, uint16_t vf,
3250         void (*vnic_cb)(struct bnxt_vnic_info *, void *), void *cbdata,
3251         int (*hwrm_cb)(struct bnxt *bp, struct bnxt_vnic_info *vnic))
3252 {
3253         struct bnxt_vnic_info vnic;
3254         int rc = 0;
3255         int i, num_vnic_ids;
3256         uint16_t *vnic_ids;
3257         size_t vnic_id_sz;
3258         size_t sz;
3259
3260         /* First query all VNIC ids */
3261         vnic_id_sz = bp->pf.total_vnics * sizeof(*vnic_ids);
3262         vnic_ids = rte_malloc("bnxt_hwrm_vf_vnic_ids_query", vnic_id_sz,
3263                         RTE_CACHE_LINE_SIZE);
3264         if (vnic_ids == NULL) {
3265                 rc = -ENOMEM;
3266                 return rc;
3267         }
3268         for (sz = 0; sz < vnic_id_sz; sz += getpagesize())
3269                 rte_mem_lock_page(((char *)vnic_ids) + sz);
3270
3271         num_vnic_ids = bnxt_hwrm_func_vf_vnic_query(bp, vf, vnic_ids);
3272
3273         if (num_vnic_ids < 0)
3274                 return num_vnic_ids;
3275
3276         /* Retrieve VNIC, update bd_stall then update */
3277
3278         for (i = 0; i < num_vnic_ids; i++) {
3279                 memset(&vnic, 0, sizeof(struct bnxt_vnic_info));
3280                 vnic.fw_vnic_id = rte_le_to_cpu_16(vnic_ids[i]);
3281                 rc = bnxt_hwrm_vnic_qcfg(bp, &vnic, bp->pf.first_vf_id + vf);
3282                 if (rc)
3283                         break;
3284                 if (vnic.mru <= 4)      /* Indicates unallocated */
3285                         continue;
3286
3287                 vnic_cb(&vnic, cbdata);
3288
3289                 rc = hwrm_cb(bp, &vnic);
3290                 if (rc)
3291                         break;
3292         }
3293
3294         rte_free(vnic_ids);
3295
3296         return rc;
3297 }
3298
3299 int bnxt_hwrm_func_cfg_vf_set_vlan_anti_spoof(struct bnxt *bp, uint16_t vf,
3300                                               bool on)
3301 {
3302         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3303         struct hwrm_func_cfg_input req = {0};
3304         int rc;
3305
3306         HWRM_PREP(req, FUNC_CFG);
3307
3308         req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
3309         req.enables |= rte_cpu_to_le_32(
3310                         HWRM_FUNC_CFG_INPUT_ENABLES_VLAN_ANTISPOOF_MODE);
3311         req.vlan_antispoof_mode = on ?
3312                 HWRM_FUNC_CFG_INPUT_VLAN_ANTISPOOF_MODE_VALIDATE_VLAN :
3313                 HWRM_FUNC_CFG_INPUT_VLAN_ANTISPOOF_MODE_NOCHECK;
3314         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
3315
3316         HWRM_CHECK_RESULT();
3317         HWRM_UNLOCK();
3318
3319         return rc;
3320 }
3321
3322 int bnxt_hwrm_func_qcfg_vf_dflt_vnic_id(struct bnxt *bp, int vf)
3323 {
3324         struct bnxt_vnic_info vnic;
3325         uint16_t *vnic_ids;
3326         size_t vnic_id_sz;
3327         int num_vnic_ids, i;
3328         size_t sz;
3329         int rc;
3330
3331         vnic_id_sz = bp->pf.total_vnics * sizeof(*vnic_ids);
3332         vnic_ids = rte_malloc("bnxt_hwrm_vf_vnic_ids_query", vnic_id_sz,
3333                         RTE_CACHE_LINE_SIZE);
3334         if (vnic_ids == NULL) {
3335                 rc = -ENOMEM;
3336                 return rc;
3337         }
3338
3339         for (sz = 0; sz < vnic_id_sz; sz += getpagesize())
3340                 rte_mem_lock_page(((char *)vnic_ids) + sz);
3341
3342         rc = bnxt_hwrm_func_vf_vnic_query(bp, vf, vnic_ids);
3343         if (rc <= 0)
3344                 goto exit;
3345         num_vnic_ids = rc;
3346
3347         /*
3348          * Loop through to find the default VNIC ID.
3349          * TODO: The easier way would be to obtain the resp->dflt_vnic_id
3350          * by sending the hwrm_func_qcfg command to the firmware.
3351          */
3352         for (i = 0; i < num_vnic_ids; i++) {
3353                 memset(&vnic, 0, sizeof(struct bnxt_vnic_info));
3354                 vnic.fw_vnic_id = rte_le_to_cpu_16(vnic_ids[i]);
3355                 rc = bnxt_hwrm_vnic_qcfg(bp, &vnic,
3356                                         bp->pf.first_vf_id + vf);
3357                 if (rc)
3358                         goto exit;
3359                 if (vnic.func_default) {
3360                         rte_free(vnic_ids);
3361                         return vnic.fw_vnic_id;
3362                 }
3363         }
3364         /* Could not find a default VNIC. */
3365         RTE_LOG(ERR, PMD, "No default VNIC\n");
3366 exit:
3367         rte_free(vnic_ids);
3368         return -1;
3369 }
3370
3371 int bnxt_hwrm_set_em_filter(struct bnxt *bp,
3372                          uint16_t dst_id,
3373                          struct bnxt_filter_info *filter)
3374 {
3375         int rc = 0;
3376         struct hwrm_cfa_em_flow_alloc_input req = {.req_type = 0 };
3377         struct hwrm_cfa_em_flow_alloc_output *resp = bp->hwrm_cmd_resp_addr;
3378         uint32_t enables = 0;
3379
3380         if (filter->fw_em_filter_id != UINT64_MAX)
3381                 bnxt_hwrm_clear_em_filter(bp, filter);
3382
3383         HWRM_PREP(req, CFA_EM_FLOW_ALLOC);
3384
3385         req.flags = rte_cpu_to_le_32(filter->flags);
3386
3387         enables = filter->enables |
3388               HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_ID;
3389         req.dst_id = rte_cpu_to_le_16(dst_id);
3390
3391         if (filter->ip_addr_type) {
3392                 req.ip_addr_type = filter->ip_addr_type;
3393                 enables |= HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IPADDR_TYPE;
3394         }
3395         if (enables &
3396             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_L2_FILTER_ID)
3397                 req.l2_filter_id = rte_cpu_to_le_64(filter->fw_l2_filter_id);
3398         if (enables &
3399             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_MACADDR)
3400                 memcpy(req.src_macaddr, filter->src_macaddr,
3401                        ETHER_ADDR_LEN);
3402         if (enables &
3403             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_MACADDR)
3404                 memcpy(req.dst_macaddr, filter->dst_macaddr,
3405                        ETHER_ADDR_LEN);
3406         if (enables &
3407             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_OVLAN_VID)
3408                 req.ovlan_vid = filter->l2_ovlan;
3409         if (enables &
3410             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IVLAN_VID)
3411                 req.ivlan_vid = filter->l2_ivlan;
3412         if (enables &
3413             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_ETHERTYPE)
3414                 req.ethertype = rte_cpu_to_be_16(filter->ethertype);
3415         if (enables &
3416             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IP_PROTOCOL)
3417                 req.ip_protocol = filter->ip_protocol;
3418         if (enables &
3419             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_IPADDR)
3420                 req.src_ipaddr[0] = rte_cpu_to_be_32(filter->src_ipaddr[0]);
3421         if (enables &
3422             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_IPADDR)
3423                 req.dst_ipaddr[0] = rte_cpu_to_be_32(filter->dst_ipaddr[0]);
3424         if (enables &
3425             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_PORT)
3426                 req.src_port = rte_cpu_to_be_16(filter->src_port);
3427         if (enables &
3428             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_PORT)
3429                 req.dst_port = rte_cpu_to_be_16(filter->dst_port);
3430         if (enables &
3431             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID)
3432                 req.mirror_vnic_id = filter->mirror_vnic_id;
3433
3434         req.enables = rte_cpu_to_le_32(enables);
3435
3436         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
3437
3438         HWRM_CHECK_RESULT();
3439
3440         filter->fw_em_filter_id = rte_le_to_cpu_64(resp->em_filter_id);
3441         HWRM_UNLOCK();
3442
3443         return rc;
3444 }
3445
3446 int bnxt_hwrm_clear_em_filter(struct bnxt *bp, struct bnxt_filter_info *filter)
3447 {
3448         int rc = 0;
3449         struct hwrm_cfa_em_flow_free_input req = {.req_type = 0 };
3450         struct hwrm_cfa_em_flow_free_output *resp = bp->hwrm_cmd_resp_addr;
3451
3452         if (filter->fw_em_filter_id == UINT64_MAX)
3453                 return 0;
3454
3455         RTE_LOG(ERR, PMD, "Clear EM filter\n");
3456         HWRM_PREP(req, CFA_EM_FLOW_FREE);
3457
3458         req.em_filter_id = rte_cpu_to_le_64(filter->fw_em_filter_id);
3459
3460         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
3461
3462         HWRM_CHECK_RESULT();
3463         HWRM_UNLOCK();
3464
3465         filter->fw_em_filter_id = -1;
3466         filter->fw_l2_filter_id = -1;
3467
3468         return 0;
3469 }
3470
3471 int bnxt_hwrm_set_ntuple_filter(struct bnxt *bp,
3472                          uint16_t dst_id,
3473                          struct bnxt_filter_info *filter)
3474 {
3475         int rc = 0;
3476         struct hwrm_cfa_ntuple_filter_alloc_input req = {.req_type = 0 };
3477         struct hwrm_cfa_ntuple_filter_alloc_output *resp =
3478                                                 bp->hwrm_cmd_resp_addr;
3479         uint32_t enables = 0;
3480
3481         if (filter->fw_ntuple_filter_id != UINT64_MAX)
3482                 bnxt_hwrm_clear_ntuple_filter(bp, filter);
3483
3484         HWRM_PREP(req, CFA_NTUPLE_FILTER_ALLOC);
3485
3486         req.flags = rte_cpu_to_le_32(filter->flags);
3487
3488         enables = filter->enables |
3489               HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_ID;
3490         req.dst_id = rte_cpu_to_le_16(dst_id);
3491
3492
3493         if (filter->ip_addr_type) {
3494                 req.ip_addr_type = filter->ip_addr_type;
3495                 enables |=
3496                         HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_IPADDR_TYPE;
3497         }
3498         if (enables &
3499             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID)
3500                 req.l2_filter_id = rte_cpu_to_le_64(filter->fw_l2_filter_id);
3501         if (enables &
3502             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_MACADDR)
3503                 memcpy(req.src_macaddr, filter->src_macaddr,
3504                        ETHER_ADDR_LEN);
3505         //if (enables &
3506             //HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_MACADDR)
3507                 //memcpy(req.dst_macaddr, filter->dst_macaddr,
3508                        //ETHER_ADDR_LEN);
3509         if (enables &
3510             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_ETHERTYPE)
3511                 req.ethertype = rte_cpu_to_be_16(filter->ethertype);
3512         if (enables &
3513             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_IP_PROTOCOL)
3514                 req.ip_protocol = filter->ip_protocol;
3515         if (enables &
3516             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_IPADDR)
3517                 req.src_ipaddr[0] = rte_cpu_to_le_32(filter->src_ipaddr[0]);
3518         if (enables &
3519             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_IPADDR_MASK)
3520                 req.src_ipaddr_mask[0] =
3521                         rte_cpu_to_le_32(filter->src_ipaddr_mask[0]);
3522         if (enables &
3523             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_IPADDR)
3524                 req.dst_ipaddr[0] = rte_cpu_to_le_32(filter->dst_ipaddr[0]);
3525         if (enables &
3526             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_IPADDR_MASK)
3527                 req.dst_ipaddr_mask[0] =
3528                         rte_cpu_to_be_32(filter->dst_ipaddr_mask[0]);
3529         if (enables &
3530             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_PORT)
3531                 req.src_port = rte_cpu_to_le_16(filter->src_port);
3532         if (enables &
3533             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_PORT_MASK)
3534                 req.src_port_mask = rte_cpu_to_le_16(filter->src_port_mask);
3535         if (enables &
3536             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_PORT)
3537                 req.dst_port = rte_cpu_to_le_16(filter->dst_port);
3538         if (enables &
3539             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_PORT_MASK)
3540                 req.dst_port_mask = rte_cpu_to_le_16(filter->dst_port_mask);
3541         if (enables &
3542             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID)
3543                 req.mirror_vnic_id = filter->mirror_vnic_id;
3544
3545         req.enables = rte_cpu_to_le_32(enables);
3546
3547         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
3548
3549         HWRM_CHECK_RESULT();
3550
3551         filter->fw_ntuple_filter_id = rte_le_to_cpu_64(resp->ntuple_filter_id);
3552         HWRM_UNLOCK();
3553
3554         return rc;
3555 }
3556
3557 int bnxt_hwrm_clear_ntuple_filter(struct bnxt *bp,
3558                                 struct bnxt_filter_info *filter)
3559 {
3560         int rc = 0;
3561         struct hwrm_cfa_ntuple_filter_free_input req = {.req_type = 0 };
3562         struct hwrm_cfa_ntuple_filter_free_output *resp =
3563                                                 bp->hwrm_cmd_resp_addr;
3564
3565         if (filter->fw_ntuple_filter_id == UINT64_MAX)
3566                 return 0;
3567
3568         HWRM_PREP(req, CFA_NTUPLE_FILTER_FREE);
3569
3570         req.ntuple_filter_id = rte_cpu_to_le_64(filter->fw_ntuple_filter_id);
3571
3572         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
3573
3574         HWRM_CHECK_RESULT();
3575         HWRM_UNLOCK();
3576
3577         filter->fw_ntuple_filter_id = -1;
3578         filter->fw_l2_filter_id = -1;
3579
3580         return 0;
3581 }