drivers/net/bnxt/bnxt_hwrm.c

   1 /*-
   2  *   BSD LICENSE
   3  *
   4  *   Copyright(c) Broadcom Limited.
   5  *   All rights reserved.
   6  *
   7  *   Redistribution and use in source and binary forms, with or without
   8  *   modification, are permitted provided that the following conditions
   9  *   are met:
  10  *
  11  *     * Redistributions of source code must retain the above copyright
  12  *       notice, this list of conditions and the following disclaimer.
  13  *     * Redistributions in binary form must reproduce the above copyright
  14  *       notice, this list of conditions and the following disclaimer in
  15  *       the documentation and/or other materials provided with the
  16  *       distribution.
  17  *     * Neither the name of Broadcom Corporation nor the names of its
  18  *       contributors may be used to endorse or promote products derived
  19  *       from this software without specific prior written permission.
  20  *
  21  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 #include <unistd.h>
  35
  36 #include <rte_byteorder.h>
  37 #include <rte_common.h>
  38 #include <rte_cycles.h>
  39 #include <rte_malloc.h>
  40 #include <rte_memzone.h>
  41 #include <rte_version.h>
  42
  43 #include "bnxt.h"
  44 #include "bnxt_cpr.h"
  45 #include "bnxt_filter.h"
  46 #include "bnxt_hwrm.h"
  47 #include "bnxt_rxq.h"
  48 #include "bnxt_rxr.h"
  49 #include "bnxt_ring.h"
  50 #include "bnxt_txq.h"
  51 #include "bnxt_txr.h"
  52 #include "bnxt_vnic.h"
  53 #include "hsi_struct_def_dpdk.h"
  54
  55 #include <rte_io.h>
  56
  57 #define HWRM_CMD_TIMEOUT                10000
  58
  59 struct bnxt_plcmodes_cfg {
  60         uint32_t        flags;
  61         uint16_t        jumbo_thresh;
  62         uint16_t        hds_offset;
  63         uint16_t        hds_threshold;
  64 };
  65
  66 static int page_getenum(size_t size)
  67 {
  68         if (size <= 1 << 4)
  69                 return 4;
  70         if (size <= 1 << 12)
  71                 return 12;
  72         if (size <= 1 << 13)
  73                 return 13;
  74         if (size <= 1 << 16)
  75                 return 16;
  76         if (size <= 1 << 21)
  77                 return 21;
  78         if (size <= 1 << 22)
  79                 return 22;
  80         if (size <= 1 << 30)
  81                 return 30;
  82         RTE_LOG(ERR, PMD, "Page size %zu out of range\n", size);
  83         return sizeof(void *) * 8 - 1;
  84 }
  85
  86 static int page_roundup(size_t size)
  87 {
  88         return 1 << page_getenum(size);
  89 }
  90
  91 /*
  92  * HWRM Functions (sent to HWRM)
  93  * These are named bnxt_hwrm_*() and return -1 if bnxt_hwrm_send_message()
  94  * fails (ie: a timeout), and a positive non-zero HWRM error code if the HWRM
  95  * command was failed by the ChiMP.
  96  */
  97
  98 static int bnxt_hwrm_send_message(struct bnxt *bp, void *msg,
  99                                         uint32_t msg_len)
 100 {
 101         unsigned int i;
 102         struct input *req = msg;
 103         struct output *resp = bp->hwrm_cmd_resp_addr;
 104         uint32_t *data = msg;
 105         uint8_t *bar;
 106         uint8_t *valid;
 107         uint16_t max_req_len = bp->max_req_len;
 108         struct hwrm_short_input short_input = { 0 };
 109
 110         if (bp->flags & BNXT_FLAG_SHORT_CMD) {
 111                 void *short_cmd_req = bp->hwrm_short_cmd_req_addr;
 112
 113                 memset(short_cmd_req, 0, bp->max_req_len);
 114                 memcpy(short_cmd_req, req, msg_len);
 115
 116                 short_input.req_type = rte_cpu_to_le_16(req->req_type);
 117                 short_input.signature = rte_cpu_to_le_16(
 118                                         HWRM_SHORT_REQ_SIGNATURE_SHORT_CMD);
 119                 short_input.size = rte_cpu_to_le_16(msg_len);
 120                 short_input.req_addr =
 121                         rte_cpu_to_le_64(bp->hwrm_short_cmd_req_dma_addr);
 122
 123                 data = (uint32_t *)&short_input;
 124                 msg_len = sizeof(short_input);
 125
 126                 /* Sync memory write before updating doorbell */
 127                 rte_wmb();
 128
 129                 max_req_len = BNXT_HWRM_SHORT_REQ_LEN;
 130         }
 131
 132         /* Write request msg to hwrm channel */
 133         for (i = 0; i < msg_len; i += 4) {
 134                 bar = (uint8_t *)bp->bar0 + i;
 135                 rte_write32(*data, bar);
 136                 data++;
 137         }
 138
 139         /* Zero the rest of the request space */
 140         for (; i < max_req_len; i += 4) {
 141                 bar = (uint8_t *)bp->bar0 + i;
 142                 rte_write32(0, bar);
 143         }
 144
 145         /* Ring channel doorbell */
 146         bar = (uint8_t *)bp->bar0 + 0x100;
 147         rte_write32(1, bar);
 148
 149         /* Poll for the valid bit */
 150         for (i = 0; i < HWRM_CMD_TIMEOUT; i++) {
 151                 /* Sanity check on the resp->resp_len */
 152                 rte_rmb();
 153                 if (resp->resp_len && resp->resp_len <=
 154                                 bp->max_resp_len) {
 155                         /* Last byte of resp contains the valid key */
 156                         valid = (uint8_t *)resp + resp->resp_len - 1;
 157                         if (*valid == HWRM_RESP_VALID_KEY)
 158                                 break;
 159                 }
 160                 rte_delay_us(600);
 161         }
 162
 163         if (i >= HWRM_CMD_TIMEOUT) {
 164                 RTE_LOG(ERR, PMD, "Error sending msg 0x%04x\n",
 165                         req->req_type);
 166                 goto err_ret;
 167         }
 168         return 0;
 169
 170 err_ret:
 171         return -1;
 172 }
 173
 174 /*
 175  * HWRM_PREP() should be used to prepare *ALL* HWRM commands.  It grabs the
 176  * spinlock, and does initial processing.
 177  *
 178  * HWRM_CHECK_RESULT() returns errors on failure and may not be used.  It
 179  * releases the spinlock only if it returns.  If the regular int return codes
 180  * are not used by the function, HWRM_CHECK_RESULT() should not be used
 181  * directly, rather it should be copied and modified to suit the function.
 182  *
 183  * HWRM_UNLOCK() must be called after all response processing is completed.
 184  */
 185 #define HWRM_PREP(req, type) do { \
 186         rte_spinlock_lock(&bp->hwrm_lock); \
 187         memset(bp->hwrm_cmd_resp_addr, 0, bp->max_resp_len); \
 188         req.req_type = rte_cpu_to_le_16(HWRM_##type); \
 189         req.cmpl_ring = rte_cpu_to_le_16(-1); \
 190         req.seq_id = rte_cpu_to_le_16(bp->hwrm_cmd_seq++); \
 191         req.target_id = rte_cpu_to_le_16(0xffff); \
 192         req.resp_addr = rte_cpu_to_le_64(bp->hwrm_cmd_resp_dma_addr); \
 193 } while (0)
 194
 195 #define HWRM_CHECK_RESULT() do {\
 196         if (rc) { \
 197                 RTE_LOG(ERR, PMD, "%s failed rc:%d\n", \
 198                         __func__, rc); \
 199                 rte_spinlock_unlock(&bp->hwrm_lock); \
 200                 if (rc == HWRM_ERR_CODE_RESOURCE_ACCESS_DENIED) \
 201                         rc = -EACCES; \
 202                 else if (rc > 0) \
 203                         rc = -EINVAL; \
 204                 return rc; \
 205         } \
 206         if (resp->error_code) { \
 207                 rc = rte_le_to_cpu_16(resp->error_code); \
 208                 if (resp->resp_len >= 16) { \
 209                         struct hwrm_err_output *tmp_hwrm_err_op = \
 210                                                 (void *)resp; \
 211                         RTE_LOG(ERR, PMD, \
 212                                 "%s error %d:%d:%08x:%04x\n", \
 213                                 __func__, \
 214                                 rc, tmp_hwrm_err_op->cmd_err, \
 215                                 rte_le_to_cpu_32(\
 216                                         tmp_hwrm_err_op->opaque_0), \
 217                                 rte_le_to_cpu_16(\
 218                                         tmp_hwrm_err_op->opaque_1)); \
 219                 } \
 220                 else { \
 221                         RTE_LOG(ERR, PMD, \
 222                                 "%s error %d\n", __func__, rc); \
 223                 } \
 224                 rte_spinlock_unlock(&bp->hwrm_lock); \
 225                 if (rc == HWRM_ERR_CODE_RESOURCE_ACCESS_DENIED) \
 226                         rc = -EACCES; \
 227                 else if (rc > 0) \
 228                         rc = -EINVAL; \
 229                 return rc; \
 230         } \
 231 } while (0)
 232
 233 #define HWRM_UNLOCK()           rte_spinlock_unlock(&bp->hwrm_lock)
 234
 235 int bnxt_hwrm_cfa_l2_clear_rx_mask(struct bnxt *bp, struct bnxt_vnic_info *vnic)
 236 {
 237         int rc = 0;
 238         struct hwrm_cfa_l2_set_rx_mask_input req = {.req_type = 0 };
 239         struct hwrm_cfa_l2_set_rx_mask_output *resp = bp->hwrm_cmd_resp_addr;
 240
 241         HWRM_PREP(req, CFA_L2_SET_RX_MASK);
 242         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
 243         req.mask = 0;
 244
 245         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
 246
 247         HWRM_CHECK_RESULT();
 248         HWRM_UNLOCK();
 249
 250         return rc;
 251 }
 252
 253 int bnxt_hwrm_cfa_l2_set_rx_mask(struct bnxt *bp,
 254                                  struct bnxt_vnic_info *vnic,
 255                                  uint16_t vlan_count,
 256                                  struct bnxt_vlan_table_entry *vlan_table)
 257 {
 258         int rc = 0;
 259         struct hwrm_cfa_l2_set_rx_mask_input req = {.req_type = 0 };
 260         struct hwrm_cfa_l2_set_rx_mask_output *resp = bp->hwrm_cmd_resp_addr;
 261         uint32_t mask = 0;
 262
 263         if (vnic->fw_vnic_id == INVALID_HW_RING_ID)
 264                 return rc;
 265
 266         HWRM_PREP(req, CFA_L2_SET_RX_MASK);
 267         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
 268
 269         /* FIXME add multicast flag, when multicast adding options is supported
 270          * by ethtool.
 271          */
 272         if (vnic->flags & BNXT_VNIC_INFO_BCAST)
 273                 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_BCAST;
 274         if (vnic->flags & BNXT_VNIC_INFO_UNTAGGED)
 275                 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_VLAN_NONVLAN;
 276         if (vnic->flags & BNXT_VNIC_INFO_PROMISC)
 277                 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_PROMISCUOUS;
 278         if (vnic->flags & BNXT_VNIC_INFO_ALLMULTI)
 279                 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_ALL_MCAST;
 280         if (vnic->flags & BNXT_VNIC_INFO_MCAST)
 281                 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_MCAST;
 282         if (vnic->mc_addr_cnt) {
 283                 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_MCAST;
 284                 req.num_mc_entries = rte_cpu_to_le_32(vnic->mc_addr_cnt);
 285                 req.mc_tbl_addr = rte_cpu_to_le_64(vnic->mc_list_dma_addr);
 286         }
 287         if (vlan_table) {
 288                 if (!(mask & HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_VLAN_NONVLAN))
 289                         mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_VLANONLY;
 290                 req.vlan_tag_tbl_addr = rte_cpu_to_le_64(
 291                          rte_mem_virt2iova(vlan_table));
 292                 req.num_vlan_tags = rte_cpu_to_le_32((uint32_t)vlan_count);
 293         }
 294         req.mask = rte_cpu_to_le_32(mask);
 295
 296         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
 297
 298         HWRM_CHECK_RESULT();
 299         HWRM_UNLOCK();
 300
 301         return rc;
 302 }
 303
 304 int bnxt_hwrm_cfa_vlan_antispoof_cfg(struct bnxt *bp, uint16_t fid,
 305                         uint16_t vlan_count,
 306                         struct bnxt_vlan_antispoof_table_entry *vlan_table)
 307 {
 308         int rc = 0;
 309         struct hwrm_cfa_vlan_antispoof_cfg_input req = {.req_type = 0 };
 310         struct hwrm_cfa_vlan_antispoof_cfg_output *resp =
 311                                                 bp->hwrm_cmd_resp_addr;
 312
 313         /*
 314          * Older HWRM versions did not support this command, and the set_rx_mask
 315          * list was used for anti-spoof. In 1.8.0, the TX path configuration was
 316          * removed from set_rx_mask call, and this command was added.
 317          *
 318          * This command is also present from 1.7.8.11 and higher,
 319          * as well as 1.7.8.0
 320          */
 321         if (bp->fw_ver < ((1 << 24) | (8 << 16))) {
 322                 if (bp->fw_ver != ((1 << 24) | (7 << 16) | (8 << 8))) {
 323                         if (bp->fw_ver < ((1 << 24) | (7 << 16) | (8 << 8) |
 324                                         (11)))
 325                                 return 0;
 326                 }
 327         }
 328         HWRM_PREP(req, CFA_VLAN_ANTISPOOF_CFG);
 329         req.fid = rte_cpu_to_le_16(fid);
 330
 331         req.vlan_tag_mask_tbl_addr =
 332                 rte_cpu_to_le_64(rte_mem_virt2iova(vlan_table));
 333         req.num_vlan_entries = rte_cpu_to_le_32((uint32_t)vlan_count);
 334
 335         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
 336
 337         HWRM_CHECK_RESULT();
 338         HWRM_UNLOCK();
 339
 340         return rc;
 341 }
 342
 343 int bnxt_hwrm_clear_l2_filter(struct bnxt *bp,
 344                            struct bnxt_filter_info *filter)
 345 {
 346         int rc = 0;
 347         struct hwrm_cfa_l2_filter_free_input req = {.req_type = 0 };
 348         struct hwrm_cfa_l2_filter_free_output *resp = bp->hwrm_cmd_resp_addr;
 349
 350         if (filter->fw_l2_filter_id == UINT64_MAX)
 351                 return 0;
 352
 353         HWRM_PREP(req, CFA_L2_FILTER_FREE);
 354
 355         req.l2_filter_id = rte_cpu_to_le_64(filter->fw_l2_filter_id);
 356
 357         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
 358
 359         HWRM_CHECK_RESULT();
 360         HWRM_UNLOCK();
 361
 362         filter->fw_l2_filter_id = -1;
 363
 364         return 0;
 365 }
 366
 367 int bnxt_hwrm_set_l2_filter(struct bnxt *bp,
 368                          uint16_t dst_id,
 369                          struct bnxt_filter_info *filter)
 370 {
 371         int rc = 0;
 372         struct hwrm_cfa_l2_filter_alloc_input req = {.req_type = 0 };
 373         struct hwrm_cfa_l2_filter_alloc_output *resp = bp->hwrm_cmd_resp_addr;
 374         struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
 375         const struct rte_eth_vmdq_rx_conf *conf =
 376                     &dev_conf->rx_adv_conf.vmdq_rx_conf;
 377         uint32_t enables = 0;
 378         uint16_t j = dst_id - 1;
 379
 380         //TODO: Is there a better way to add VLANs to each VNIC in case of VMDQ
 381         if ((dev_conf->rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG) &&
 382             conf->pool_map[j].pools & (1UL << j)) {
 383                 RTE_LOG(DEBUG, PMD,
 384                         "Add vlan %u to vmdq pool %u\n",
 385                         conf->pool_map[j].vlan_id, j);
 386
 387                 filter->l2_ivlan = conf->pool_map[j].vlan_id;
 388                 filter->enables |=
 389                         HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN |
 390                         HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN_MASK;
 391         }
 392
 393         if (filter->fw_l2_filter_id != UINT64_MAX)
 394                 bnxt_hwrm_clear_l2_filter(bp, filter);
 395
 396         HWRM_PREP(req, CFA_L2_FILTER_ALLOC);
 397
 398         req.flags = rte_cpu_to_le_32(filter->flags);
 399
 400         enables = filter->enables |
 401               HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_DST_ID;
 402         req.dst_id = rte_cpu_to_le_16(dst_id);
 403
 404         if (enables &
 405             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR)
 406                 memcpy(req.l2_addr, filter->l2_addr,
 407                        ETHER_ADDR_LEN);
 408         if (enables &
 409             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR_MASK)
 410                 memcpy(req.l2_addr_mask, filter->l2_addr_mask,
 411                        ETHER_ADDR_LEN);
 412         if (enables &
 413             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN)
 414                 req.l2_ovlan = filter->l2_ovlan;
 415         if (enables &
 416             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN)
 417                 req.l2_ivlan = filter->l2_ivlan;
 418         if (enables &
 419             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN_MASK)
 420                 req.l2_ovlan_mask = filter->l2_ovlan_mask;
 421         if (enables &
 422             HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN_MASK)
 423                 req.l2_ivlan_mask = filter->l2_ivlan_mask;
 424         if (enables & HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_SRC_ID)
 425                 req.src_id = rte_cpu_to_le_32(filter->src_id);
 426         if (enables & HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_SRC_TYPE)
 427                 req.src_type = filter->src_type;
 428
 429         req.enables = rte_cpu_to_le_32(enables);
 430
 431         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
 432
 433         HWRM_CHECK_RESULT();
 434
 435         filter->fw_l2_filter_id = rte_le_to_cpu_64(resp->l2_filter_id);
 436         HWRM_UNLOCK();
 437
 438         return rc;
 439 }
 440
 441 int bnxt_hwrm_func_qcaps(struct bnxt *bp)
 442 {
 443         int rc = 0;
 444         struct hwrm_func_qcaps_input req = {.req_type = 0 };
 445         struct hwrm_func_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
 446         uint16_t new_max_vfs;
 447         int i;
 448
 449         HWRM_PREP(req, FUNC_QCAPS);
 450
 451         req.fid = rte_cpu_to_le_16(0xffff);
 452
 453         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
 454
 455         HWRM_CHECK_RESULT();
 456
 457         bp->max_ring_grps = rte_le_to_cpu_32(resp->max_hw_ring_grps);
 458         if (BNXT_PF(bp)) {
 459                 bp->pf.port_id = resp->port_id;
 460                 bp->pf.first_vf_id = rte_le_to_cpu_16(resp->first_vf_id);
 461                 new_max_vfs = bp->pdev->max_vfs;
 462                 if (new_max_vfs != bp->pf.max_vfs) {
 463                         if (bp->pf.vf_info)
 464                                 rte_free(bp->pf.vf_info);
 465                         bp->pf.vf_info = rte_malloc("bnxt_vf_info",
 466                             sizeof(bp->pf.vf_info[0]) * new_max_vfs, 0);
 467                         bp->pf.max_vfs = new_max_vfs;
 468                         for (i = 0; i < new_max_vfs; i++) {
 469                                 bp->pf.vf_info[i].fid = bp->pf.first_vf_id + i;
 470                                 bp->pf.vf_info[i].vlan_table =
 471                                         rte_zmalloc("VF VLAN table",
 472                                                     getpagesize(),
 473                                                     getpagesize());
 474                                 if (bp->pf.vf_info[i].vlan_table == NULL)
 475                                         RTE_LOG(ERR, PMD,
 476                                         "Fail to alloc VLAN table for VF %d\n",
 477                                         i);
 478                                 else
 479                                         rte_mem_lock_page(
 480                                                 bp->pf.vf_info[i].vlan_table);
 481                                 bp->pf.vf_info[i].vlan_as_table =
 482                                         rte_zmalloc("VF VLAN AS table",
 483                                                     getpagesize(),
 484                                                     getpagesize());
 485                                 if (bp->pf.vf_info[i].vlan_as_table == NULL)
 486                                         RTE_LOG(ERR, PMD,
 487                                         "Alloc VLAN AS table for VF %d fail\n",
 488                                         i);
 489                                 else
 490                                         rte_mem_lock_page(
 491                                                bp->pf.vf_info[i].vlan_as_table);
 492                                 STAILQ_INIT(&bp->pf.vf_info[i].filter);
 493                         }
 494                 }
 495         }
 496
 497         bp->fw_fid = rte_le_to_cpu_32(resp->fid);
 498         memcpy(bp->dflt_mac_addr, &resp->mac_address, ETHER_ADDR_LEN);
 499         bp->max_rsscos_ctx = rte_le_to_cpu_16(resp->max_rsscos_ctx);
 500         bp->max_cp_rings = rte_le_to_cpu_16(resp->max_cmpl_rings);
 501         bp->max_tx_rings = rte_le_to_cpu_16(resp->max_tx_rings);
 502         bp->max_rx_rings = rte_le_to_cpu_16(resp->max_rx_rings);
 503         bp->max_l2_ctx = rte_le_to_cpu_16(resp->max_l2_ctxs);
 504         /* TODO: For now, do not support VMDq/RFS on VFs. */
 505         if (BNXT_PF(bp)) {
 506                 if (bp->pf.max_vfs)
 507                         bp->max_vnics = 1;
 508                 else
 509                         bp->max_vnics = rte_le_to_cpu_16(resp->max_vnics);
 510         } else {
 511                 bp->max_vnics = 1;
 512         }
 513         bp->max_stat_ctx = rte_le_to_cpu_16(resp->max_stat_ctx);
 514         if (BNXT_PF(bp))
 515                 bp->pf.total_vnics = rte_le_to_cpu_16(resp->max_vnics);
 516         HWRM_UNLOCK();
 517
 518         return rc;
 519 }
 520
 521 int bnxt_hwrm_func_reset(struct bnxt *bp)
 522 {
 523         int rc = 0;
 524         struct hwrm_func_reset_input req = {.req_type = 0 };
 525         struct hwrm_func_reset_output *resp = bp->hwrm_cmd_resp_addr;
 526
 527         HWRM_PREP(req, FUNC_RESET);
 528
 529         req.enables = rte_cpu_to_le_32(0);
 530
 531         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
 532
 533         HWRM_CHECK_RESULT();
 534         HWRM_UNLOCK();
 535
 536         return rc;
 537 }
 538
 539 int bnxt_hwrm_func_driver_register(struct bnxt *bp)
 540 {
 541         int rc;
 542         struct hwrm_func_drv_rgtr_input req = {.req_type = 0 };
 543         struct hwrm_func_drv_rgtr_output *resp = bp->hwrm_cmd_resp_addr;
 544
 545         if (bp->flags & BNXT_FLAG_REGISTERED)
 546                 return 0;
 547
 548         HWRM_PREP(req, FUNC_DRV_RGTR);
 549         req.enables = rte_cpu_to_le_32(HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_VER |
 550                         HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_ASYNC_EVENT_FWD);
 551         req.ver_maj = RTE_VER_YEAR;
 552         req.ver_min = RTE_VER_MONTH;
 553         req.ver_upd = RTE_VER_MINOR;
 554
 555         if (BNXT_PF(bp)) {
 556                 req.enables |= rte_cpu_to_le_32(
 557                         HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_VF_INPUT_FWD);
 558                 memcpy(req.vf_req_fwd, bp->pf.vf_req_fwd,
 559                        RTE_MIN(sizeof(req.vf_req_fwd),
 560                                sizeof(bp->pf.vf_req_fwd)));
 561         }
 562
 563         req.async_event_fwd[0] |= rte_cpu_to_le_32(0x1);   /* TODO: Use MACRO */
 564         //memset(req.async_event_fwd, 0xff, sizeof(req.async_event_fwd));
 565
 566         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
 567
 568         HWRM_CHECK_RESULT();
 569         HWRM_UNLOCK();
 570
 571         bp->flags |= BNXT_FLAG_REGISTERED;
 572
 573         return rc;
 574 }
 575
 576 int bnxt_hwrm_ver_get(struct bnxt *bp)
 577 {
 578         int rc = 0;
 579         struct hwrm_ver_get_input req = {.req_type = 0 };
 580         struct hwrm_ver_get_output *resp = bp->hwrm_cmd_resp_addr;
 581         uint32_t my_version;
 582         uint32_t fw_version;
 583         uint16_t max_resp_len;
 584         char type[RTE_MEMZONE_NAMESIZE];
 585         uint32_t dev_caps_cfg;
 586
 587         bp->max_req_len = HWRM_MAX_REQ_LEN;
 588         HWRM_PREP(req, VER_GET);
 589
 590         req.hwrm_intf_maj = HWRM_VERSION_MAJOR;
 591         req.hwrm_intf_min = HWRM_VERSION_MINOR;
 592         req.hwrm_intf_upd = HWRM_VERSION_UPDATE;
 593
 594         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
 595
 596         HWRM_CHECK_RESULT();
 597
 598         RTE_LOG(INFO, PMD, "%d.%d.%d:%d.%d.%d\n",
 599                 resp->hwrm_intf_maj, resp->hwrm_intf_min,
 600                 resp->hwrm_intf_upd,
 601                 resp->hwrm_fw_maj, resp->hwrm_fw_min, resp->hwrm_fw_bld);
 602         bp->fw_ver = (resp->hwrm_fw_maj << 24) | (resp->hwrm_fw_min << 16) |
 603                         (resp->hwrm_fw_bld << 8) | resp->hwrm_fw_rsvd;
 604         RTE_LOG(INFO, PMD, "Driver HWRM version: %d.%d.%d\n",
 605                 HWRM_VERSION_MAJOR, HWRM_VERSION_MINOR, HWRM_VERSION_UPDATE);
 606
 607         my_version = HWRM_VERSION_MAJOR << 16;
 608         my_version |= HWRM_VERSION_MINOR << 8;
 609         my_version |= HWRM_VERSION_UPDATE;
 610
 611         fw_version = resp->hwrm_intf_maj << 16;
 612         fw_version |= resp->hwrm_intf_min << 8;
 613         fw_version |= resp->hwrm_intf_upd;
 614
 615         if (resp->hwrm_intf_maj != HWRM_VERSION_MAJOR) {
 616                 RTE_LOG(ERR, PMD, "Unsupported firmware API version\n");
 617                 rc = -EINVAL;
 618                 goto error;
 619         }
 620
 621         if (my_version != fw_version) {
 622                 RTE_LOG(INFO, PMD, "BNXT Driver/HWRM API mismatch.\n");
 623                 if (my_version < fw_version) {
 624                         RTE_LOG(INFO, PMD,
 625                                 "Firmware API version is newer than driver.\n");
 626                         RTE_LOG(INFO, PMD,
 627                                 "The driver may be missing features.\n");
 628                 } else {
 629                         RTE_LOG(INFO, PMD,
 630                                 "Firmware API version is older than driver.\n");
 631                         RTE_LOG(INFO, PMD,
 632                                 "Not all driver features may be functional.\n");
 633                 }
 634         }
 635
 636         if (bp->max_req_len > resp->max_req_win_len) {
 637                 RTE_LOG(ERR, PMD, "Unsupported request length\n");
 638                 rc = -EINVAL;
 639         }
 640         bp->max_req_len = rte_le_to_cpu_16(resp->max_req_win_len);
 641         max_resp_len = resp->max_resp_len;
 642         dev_caps_cfg = rte_le_to_cpu_32(resp->dev_caps_cfg);
 643
 644         if (bp->max_resp_len != max_resp_len) {
 645                 sprintf(type, "bnxt_hwrm_%04x:%02x:%02x:%02x",
 646                         bp->pdev->addr.domain, bp->pdev->addr.bus,
 647                         bp->pdev->addr.devid, bp->pdev->addr.function);
 648
 649                 rte_free(bp->hwrm_cmd_resp_addr);
 650
 651                 bp->hwrm_cmd_resp_addr = rte_malloc(type, max_resp_len, 0);
 652                 if (bp->hwrm_cmd_resp_addr == NULL) {
 653                         rc = -ENOMEM;
 654                         goto error;
 655                 }
 656                 rte_mem_lock_page(bp->hwrm_cmd_resp_addr);
 657                 bp->hwrm_cmd_resp_dma_addr =
 658                         rte_mem_virt2iova(bp->hwrm_cmd_resp_addr);
 659                 if (bp->hwrm_cmd_resp_dma_addr == 0) {
 660                         RTE_LOG(ERR, PMD,
 661                         "Unable to map response buffer to physical memory.\n");
 662                         rc = -ENOMEM;
 663                         goto error;
 664                 }
 665                 bp->max_resp_len = max_resp_len;
 666         }
 667
 668         if ((dev_caps_cfg &
 669                 HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_SUPPORTED) &&
 670             (dev_caps_cfg &
 671              HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_INPUTUIRED)) {
 672                 RTE_LOG(DEBUG, PMD, "Short command supported\n");
 673
 674                 rte_free(bp->hwrm_short_cmd_req_addr);
 675
 676                 bp->hwrm_short_cmd_req_addr = rte_malloc(type,
 677                                                         bp->max_req_len, 0);
 678                 if (bp->hwrm_short_cmd_req_addr == NULL) {
 679                         rc = -ENOMEM;
 680                         goto error;
 681                 }
 682                 rte_mem_lock_page(bp->hwrm_short_cmd_req_addr);
 683                 bp->hwrm_short_cmd_req_dma_addr =
 684                         rte_mem_virt2iova(bp->hwrm_short_cmd_req_addr);
 685                 if (bp->hwrm_short_cmd_req_dma_addr == 0) {
 686                         rte_free(bp->hwrm_short_cmd_req_addr);
 687                         RTE_LOG(ERR, PMD,
 688                                 "Unable to map buffer to physical memory.\n");
 689                         rc = -ENOMEM;
 690                         goto error;
 691                 }
 692
 693                 bp->flags |= BNXT_FLAG_SHORT_CMD;
 694         }
 695
 696 error:
 697         HWRM_UNLOCK();
 698         return rc;
 699 }
 700
 701 int bnxt_hwrm_func_driver_unregister(struct bnxt *bp, uint32_t flags)
 702 {
 703         int rc;
 704         struct hwrm_func_drv_unrgtr_input req = {.req_type = 0 };
 705         struct hwrm_func_drv_unrgtr_output *resp = bp->hwrm_cmd_resp_addr;
 706
 707         if (!(bp->flags & BNXT_FLAG_REGISTERED))
 708                 return 0;
 709
 710         HWRM_PREP(req, FUNC_DRV_UNRGTR);
 711         req.flags = flags;
 712
 713         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
 714
 715         HWRM_CHECK_RESULT();
 716         HWRM_UNLOCK();
 717
 718         bp->flags &= ~BNXT_FLAG_REGISTERED;
 719
 720         return rc;
 721 }
 722
 723 static int bnxt_hwrm_port_phy_cfg(struct bnxt *bp, struct bnxt_link_info *conf)
 724 {
 725         int rc = 0;
 726         struct hwrm_port_phy_cfg_input req = {0};
 727         struct hwrm_port_phy_cfg_output *resp = bp->hwrm_cmd_resp_addr;
 728         uint32_t enables = 0;
 729
 730         HWRM_PREP(req, PORT_PHY_CFG);
 731
 732         if (conf->link_up) {
 733                 /* Setting Fixed Speed. But AutoNeg is ON, So disable it */
 734                 if (bp->link_info.auto_mode && conf->link_speed) {
 735                         req.auto_mode = HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_NONE;
 736                         RTE_LOG(DEBUG, PMD, "Disabling AutoNeg\n");
 737                 }
 738
 739                 req.flags = rte_cpu_to_le_32(conf->phy_flags);
 740                 req.force_link_speed = rte_cpu_to_le_16(conf->link_speed);
 741                 enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_MODE;
 742                 /*
 743                  * Note, ChiMP FW 20.2.1 and 20.2.2 return an error when we set
 744                  * any auto mode, even "none".
 745                  */
 746                 if (!conf->link_speed) {
 747                         /* No speeds specified. Enable AutoNeg - all speeds */
 748                         req.auto_mode =
 749                                 HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_ALL_SPEEDS;
 750                 }
 751                 /* AutoNeg - Advertise speeds specified. */
 752                 if (conf->auto_link_speed_mask &&
 753                     !(conf->phy_flags & HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE)) {
 754                         req.auto_mode =
 755                                 HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_SPEED_MASK;
 756                         req.auto_link_speed_mask =
 757                                 conf->auto_link_speed_mask;
 758                         enables |=
 759                         HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_LINK_SPEED_MASK;
 760                 }
 761
 762                 req.auto_duplex = conf->duplex;
 763                 enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_DUPLEX;
 764                 req.auto_pause = conf->auto_pause;
 765                 req.force_pause = conf->force_pause;
 766                 /* Set force_pause if there is no auto or if there is a force */
 767                 if (req.auto_pause && !req.force_pause)
 768                         enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_PAUSE;
 769                 else
 770                         enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_FORCE_PAUSE;
 771
 772                 req.enables = rte_cpu_to_le_32(enables);
 773         } else {
 774                 req.flags =
 775                 rte_cpu_to_le_32(HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE_LINK_DWN);
 776                 RTE_LOG(INFO, PMD, "Force Link Down\n");
 777         }
 778
 779         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
 780
 781         HWRM_CHECK_RESULT();
 782         HWRM_UNLOCK();
 783
 784         return rc;
 785 }
 786
 787 static int bnxt_hwrm_port_phy_qcfg(struct bnxt *bp,
 788                                    struct bnxt_link_info *link_info)
 789 {
 790         int rc = 0;
 791         struct hwrm_port_phy_qcfg_input req = {0};
 792         struct hwrm_port_phy_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
 793
 794         HWRM_PREP(req, PORT_PHY_QCFG);
 795
 796         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
 797
 798         HWRM_CHECK_RESULT();
 799
 800         link_info->phy_link_status = resp->link;
 801         link_info->link_up =
 802                 (link_info->phy_link_status ==
 803                  HWRM_PORT_PHY_QCFG_OUTPUT_LINK_LINK) ? 1 : 0;
 804         link_info->link_speed = rte_le_to_cpu_16(resp->link_speed);
 805         link_info->duplex = resp->duplex_cfg;
 806         link_info->pause = resp->pause;
 807         link_info->auto_pause = resp->auto_pause;
 808         link_info->force_pause = resp->force_pause;
 809         link_info->auto_mode = resp->auto_mode;
 810         link_info->phy_type = resp->phy_type;
 811         link_info->media_type = resp->media_type;
 812
 813         link_info->support_speeds = rte_le_to_cpu_16(resp->support_speeds);
 814         link_info->auto_link_speed = rte_le_to_cpu_16(resp->auto_link_speed);
 815         link_info->preemphasis = rte_le_to_cpu_32(resp->preemphasis);
 816         link_info->force_link_speed = rte_le_to_cpu_16(resp->force_link_speed);
 817         link_info->phy_ver[0] = resp->phy_maj;
 818         link_info->phy_ver[1] = resp->phy_min;
 819         link_info->phy_ver[2] = resp->phy_bld;
 820
 821         HWRM_UNLOCK();
 822
 823         RTE_LOG(DEBUG, PMD, "Link Speed %d\n", link_info->link_speed);
 824         RTE_LOG(DEBUG, PMD, "Auto Mode %d\n", link_info->auto_mode);
 825         RTE_LOG(DEBUG, PMD, "Support Speeds %x\n", link_info->support_speeds);
 826         RTE_LOG(DEBUG, PMD, "Auto Link Speed %x\n", link_info->auto_link_speed);
 827         RTE_LOG(DEBUG, PMD, "Auto Link Speed Mask %x\n",
 828                     link_info->auto_link_speed_mask);
 829         RTE_LOG(DEBUG, PMD, "Forced Link Speed %x\n",
 830                     link_info->force_link_speed);
 831
 832         return rc;
 833 }
 834
 835 int bnxt_hwrm_queue_qportcfg(struct bnxt *bp)
 836 {
 837         int rc = 0;
 838         struct hwrm_queue_qportcfg_input req = {.req_type = 0 };
 839         struct hwrm_queue_qportcfg_output *resp = bp->hwrm_cmd_resp_addr;
 840
 841         HWRM_PREP(req, QUEUE_QPORTCFG);
 842
 843         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
 844
 845         HWRM_CHECK_RESULT();
 846
 847 #define GET_QUEUE_INFO(x) \
 848         bp->cos_queue[x].id = resp->queue_id##x; \
 849         bp->cos_queue[x].profile = resp->queue_id##x##_service_profile
 850
 851         GET_QUEUE_INFO(0);
 852         GET_QUEUE_INFO(1);
 853         GET_QUEUE_INFO(2);
 854         GET_QUEUE_INFO(3);
 855         GET_QUEUE_INFO(4);
 856         GET_QUEUE_INFO(5);
 857         GET_QUEUE_INFO(6);
 858         GET_QUEUE_INFO(7);
 859
 860         HWRM_UNLOCK();
 861
 862         return rc;
 863 }
 864
 865 int bnxt_hwrm_ring_alloc(struct bnxt *bp,
 866                          struct bnxt_ring *ring,
 867                          uint32_t ring_type, uint32_t map_index,
 868                          uint32_t stats_ctx_id, uint32_t cmpl_ring_id)
 869 {
 870         int rc = 0;
 871         uint32_t enables = 0;
 872         struct hwrm_ring_alloc_input req = {.req_type = 0 };
 873         struct hwrm_ring_alloc_output *resp = bp->hwrm_cmd_resp_addr;
 874
 875         HWRM_PREP(req, RING_ALLOC);
 876
 877         req.page_tbl_addr = rte_cpu_to_le_64(ring->bd_dma);
 878         req.fbo = rte_cpu_to_le_32(0);
 879         /* Association of ring index with doorbell index */
 880         req.logical_id = rte_cpu_to_le_16(map_index);
 881         req.length = rte_cpu_to_le_32(ring->ring_size);
 882
 883         switch (ring_type) {
 884         case HWRM_RING_ALLOC_INPUT_RING_TYPE_TX:
 885                 req.queue_id = bp->cos_queue[0].id;
 886                 /* FALLTHROUGH */
 887         case HWRM_RING_ALLOC_INPUT_RING_TYPE_RX:
 888                 req.ring_type = ring_type;
 889                 req.cmpl_ring_id = rte_cpu_to_le_16(cmpl_ring_id);
 890                 req.stat_ctx_id = rte_cpu_to_le_16(stats_ctx_id);
 891                 if (stats_ctx_id != INVALID_STATS_CTX_ID)
 892                         enables |=
 893                         HWRM_RING_ALLOC_INPUT_ENABLES_STAT_CTX_ID_VALID;
 894                 break;
 895         case HWRM_RING_ALLOC_INPUT_RING_TYPE_L2_CMPL:
 896                 req.ring_type = ring_type;
 897                 /*
 898                  * TODO: Some HWRM versions crash with
 899                  * HWRM_RING_ALLOC_INPUT_INT_MODE_POLL
 900                  */
 901                 req.int_mode = HWRM_RING_ALLOC_INPUT_INT_MODE_MSIX;
 902                 break;
 903         default:
 904                 RTE_LOG(ERR, PMD, "hwrm alloc invalid ring type %d\n",
 905                         ring_type);
 906                 HWRM_UNLOCK();
 907                 return -1;
 908         }
 909         req.enables = rte_cpu_to_le_32(enables);
 910
 911         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
 912
 913         if (rc || resp->error_code) {
 914                 if (rc == 0 && resp->error_code)
 915                         rc = rte_le_to_cpu_16(resp->error_code);
 916                 switch (ring_type) {
 917                 case HWRM_RING_FREE_INPUT_RING_TYPE_L2_CMPL:
 918                         RTE_LOG(ERR, PMD,
 919                                 "hwrm_ring_alloc cp failed. rc:%d\n", rc);
 920                         HWRM_UNLOCK();
 921                         return rc;
 922                 case HWRM_RING_FREE_INPUT_RING_TYPE_RX:
 923                         RTE_LOG(ERR, PMD,
 924                                 "hwrm_ring_alloc rx failed. rc:%d\n", rc);
 925                         HWRM_UNLOCK();
 926                         return rc;
 927                 case HWRM_RING_FREE_INPUT_RING_TYPE_TX:
 928                         RTE_LOG(ERR, PMD,
 929                                 "hwrm_ring_alloc tx failed. rc:%d\n", rc);
 930                         HWRM_UNLOCK();
 931                         return rc;
 932                 default:
 933                         RTE_LOG(ERR, PMD, "Invalid ring. rc:%d\n", rc);
 934                         HWRM_UNLOCK();
 935                         return rc;
 936                 }
 937         }
 938
 939         ring->fw_ring_id = rte_le_to_cpu_16(resp->ring_id);
 940         HWRM_UNLOCK();
 941         return rc;
 942 }
 943
 944 int bnxt_hwrm_ring_free(struct bnxt *bp,
 945                         struct bnxt_ring *ring, uint32_t ring_type)
 946 {
 947         int rc;
 948         struct hwrm_ring_free_input req = {.req_type = 0 };
 949         struct hwrm_ring_free_output *resp = bp->hwrm_cmd_resp_addr;
 950
 951         HWRM_PREP(req, RING_FREE);
 952
 953         req.ring_type = ring_type;
 954         req.ring_id = rte_cpu_to_le_16(ring->fw_ring_id);
 955
 956         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
 957
 958         if (rc || resp->error_code) {
 959                 if (rc == 0 && resp->error_code)
 960                         rc = rte_le_to_cpu_16(resp->error_code);
 961                 HWRM_UNLOCK();
 962
 963                 switch (ring_type) {
 964                 case HWRM_RING_FREE_INPUT_RING_TYPE_L2_CMPL:
 965                         RTE_LOG(ERR, PMD, "hwrm_ring_free cp failed. rc:%d\n",
 966                                 rc);
 967                         return rc;
 968                 case HWRM_RING_FREE_INPUT_RING_TYPE_RX:
 969                         RTE_LOG(ERR, PMD, "hwrm_ring_free rx failed. rc:%d\n",
 970                                 rc);
 971                         return rc;
 972                 case HWRM_RING_FREE_INPUT_RING_TYPE_TX:
 973                         RTE_LOG(ERR, PMD, "hwrm_ring_free tx failed. rc:%d\n",
 974                                 rc);
 975                         return rc;
 976                 default:
 977                         RTE_LOG(ERR, PMD, "Invalid ring, rc:%d\n", rc);
 978                         return rc;
 979                 }
 980         }
 981         HWRM_UNLOCK();
 982         return 0;
 983 }
 984
 985 int bnxt_hwrm_ring_grp_alloc(struct bnxt *bp, unsigned int idx)
 986 {
 987         int rc = 0;
 988         struct hwrm_ring_grp_alloc_input req = {.req_type = 0 };
 989         struct hwrm_ring_grp_alloc_output *resp = bp->hwrm_cmd_resp_addr;
 990
 991         HWRM_PREP(req, RING_GRP_ALLOC);
 992
 993         req.cr = rte_cpu_to_le_16(bp->grp_info[idx].cp_fw_ring_id);
 994         req.rr = rte_cpu_to_le_16(bp->grp_info[idx].rx_fw_ring_id);
 995         req.ar = rte_cpu_to_le_16(bp->grp_info[idx].ag_fw_ring_id);
 996         req.sc = rte_cpu_to_le_16(bp->grp_info[idx].fw_stats_ctx);
 997
 998         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
 999
1000         HWRM_CHECK_RESULT();
1001
1002         bp->grp_info[idx].fw_grp_id =
1003             rte_le_to_cpu_16(resp->ring_group_id);
1004
1005         HWRM_UNLOCK();
1006
1007         return rc;
1008 }
1009
1010 int bnxt_hwrm_ring_grp_free(struct bnxt *bp, unsigned int idx)
1011 {
1012         int rc;
1013         struct hwrm_ring_grp_free_input req = {.req_type = 0 };
1014         struct hwrm_ring_grp_free_output *resp = bp->hwrm_cmd_resp_addr;
1015
1016         HWRM_PREP(req, RING_GRP_FREE);
1017
1018         req.ring_group_id = rte_cpu_to_le_16(bp->grp_info[idx].fw_grp_id);
1019
1020         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
1021
1022         HWRM_CHECK_RESULT();
1023         HWRM_UNLOCK();
1024
1025         bp->grp_info[idx].fw_grp_id = INVALID_HW_RING_ID;
1026         return rc;
1027 }
1028
1029 int bnxt_hwrm_stat_clear(struct bnxt *bp, struct bnxt_cp_ring_info *cpr)
1030 {
1031         int rc = 0;
1032         struct hwrm_stat_ctx_clr_stats_input req = {.req_type = 0 };
1033         struct hwrm_stat_ctx_clr_stats_output *resp = bp->hwrm_cmd_resp_addr;
1034
1035         if (cpr->hw_stats_ctx_id == (uint32_t)HWRM_NA_SIGNATURE)
1036                 return rc;
1037
1038         HWRM_PREP(req, STAT_CTX_CLR_STATS);
1039
1040         req.stat_ctx_id = rte_cpu_to_le_16(cpr->hw_stats_ctx_id);
1041
1042         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
1043
1044         HWRM_CHECK_RESULT();
1045         HWRM_UNLOCK();
1046
1047         return rc;
1048 }
1049
1050 int bnxt_hwrm_stat_ctx_alloc(struct bnxt *bp, struct bnxt_cp_ring_info *cpr,
1051                                 unsigned int idx __rte_unused)
1052 {
1053         int rc;
1054         struct hwrm_stat_ctx_alloc_input req = {.req_type = 0 };
1055         struct hwrm_stat_ctx_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1056
1057         HWRM_PREP(req, STAT_CTX_ALLOC);
1058
1059         req.update_period_ms = rte_cpu_to_le_32(0);
1060
1061         req.stats_dma_addr =
1062             rte_cpu_to_le_64(cpr->hw_stats_map);
1063
1064         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
1065
1066         HWRM_CHECK_RESULT();
1067
1068         cpr->hw_stats_ctx_id = rte_le_to_cpu_16(resp->stat_ctx_id);
1069
1070         HWRM_UNLOCK();
1071
1072         return rc;
1073 }
1074
1075 int bnxt_hwrm_stat_ctx_free(struct bnxt *bp, struct bnxt_cp_ring_info *cpr,
1076                                 unsigned int idx __rte_unused)
1077 {
1078         int rc;
1079         struct hwrm_stat_ctx_free_input req = {.req_type = 0 };
1080         struct hwrm_stat_ctx_free_output *resp = bp->hwrm_cmd_resp_addr;
1081
1082         HWRM_PREP(req, STAT_CTX_FREE);
1083
1084         req.stat_ctx_id = rte_cpu_to_le_16(cpr->hw_stats_ctx_id);
1085
1086         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
1087
1088         HWRM_CHECK_RESULT();
1089         HWRM_UNLOCK();
1090
1091         return rc;
1092 }
1093
1094 int bnxt_hwrm_vnic_alloc(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1095 {
1096         int rc = 0, i, j;
1097         struct hwrm_vnic_alloc_input req = { 0 };
1098         struct hwrm_vnic_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1099
1100         /* map ring groups to this vnic */
1101         RTE_LOG(DEBUG, PMD, "Alloc VNIC. Start %x, End %x\n",
1102                 vnic->start_grp_id, vnic->end_grp_id);
1103         for (i = vnic->start_grp_id, j = 0; i < vnic->end_grp_id; i++, j++)
1104                 vnic->fw_grp_ids[j] = bp->grp_info[i].fw_grp_id;
1105
1106         vnic->dflt_ring_grp = bp->grp_info[vnic->start_grp_id].fw_grp_id;
1107         vnic->rss_rule = (uint16_t)HWRM_NA_SIGNATURE;
1108         vnic->cos_rule = (uint16_t)HWRM_NA_SIGNATURE;
1109         vnic->lb_rule = (uint16_t)HWRM_NA_SIGNATURE;
1110         vnic->mru = bp->eth_dev->data->mtu + ETHER_HDR_LEN +
1111                                 ETHER_CRC_LEN + VLAN_TAG_SIZE;
1112         HWRM_PREP(req, VNIC_ALLOC);
1113
1114         if (vnic->func_default)
1115                 req.flags =
1116                         rte_cpu_to_le_32(HWRM_VNIC_ALLOC_INPUT_FLAGS_DEFAULT);
1117         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
1118
1119         HWRM_CHECK_RESULT();
1120
1121         vnic->fw_vnic_id = rte_le_to_cpu_16(resp->vnic_id);
1122         HWRM_UNLOCK();
1123         RTE_LOG(DEBUG, PMD, "VNIC ID %x\n", vnic->fw_vnic_id);
1124         return rc;
1125 }
1126
1127 static int bnxt_hwrm_vnic_plcmodes_qcfg(struct bnxt *bp,
1128                                         struct bnxt_vnic_info *vnic,
1129                                         struct bnxt_plcmodes_cfg *pmode)
1130 {
1131         int rc = 0;
1132         struct hwrm_vnic_plcmodes_qcfg_input req = {.req_type = 0 };
1133         struct hwrm_vnic_plcmodes_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
1134
1135         HWRM_PREP(req, VNIC_PLCMODES_QCFG);
1136
1137         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1138
1139         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
1140
1141         HWRM_CHECK_RESULT();
1142
1143         pmode->flags = rte_le_to_cpu_32(resp->flags);
1144         /* dflt_vnic bit doesn't exist in the _cfg command */
1145         pmode->flags &= ~(HWRM_VNIC_PLCMODES_QCFG_OUTPUT_FLAGS_DFLT_VNIC);
1146         pmode->jumbo_thresh = rte_le_to_cpu_16(resp->jumbo_thresh);
1147         pmode->hds_offset = rte_le_to_cpu_16(resp->hds_offset);
1148         pmode->hds_threshold = rte_le_to_cpu_16(resp->hds_threshold);
1149
1150         HWRM_UNLOCK();
1151
1152         return rc;
1153 }
1154
1155 static int bnxt_hwrm_vnic_plcmodes_cfg(struct bnxt *bp,
1156                                        struct bnxt_vnic_info *vnic,
1157                                        struct bnxt_plcmodes_cfg *pmode)
1158 {
1159         int rc = 0;
1160         struct hwrm_vnic_plcmodes_cfg_input req = {.req_type = 0 };
1161         struct hwrm_vnic_plcmodes_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1162
1163         HWRM_PREP(req, VNIC_PLCMODES_CFG);
1164
1165         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1166         req.flags = rte_cpu_to_le_32(pmode->flags);
1167         req.jumbo_thresh = rte_cpu_to_le_16(pmode->jumbo_thresh);
1168         req.hds_offset = rte_cpu_to_le_16(pmode->hds_offset);
1169         req.hds_threshold = rte_cpu_to_le_16(pmode->hds_threshold);
1170         req.enables = rte_cpu_to_le_32(
1171             HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_HDS_THRESHOLD_VALID |
1172             HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_HDS_OFFSET_VALID |
1173             HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_JUMBO_THRESH_VALID
1174         );
1175
1176         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
1177
1178         HWRM_CHECK_RESULT();
1179         HWRM_UNLOCK();
1180
1181         return rc;
1182 }
1183
1184 int bnxt_hwrm_vnic_cfg(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1185 {
1186         int rc = 0;
1187         struct hwrm_vnic_cfg_input req = {.req_type = 0 };
1188         struct hwrm_vnic_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1189         uint32_t ctx_enable_flag = 0;
1190         struct bnxt_plcmodes_cfg pmodes;
1191
1192         if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
1193                 RTE_LOG(DEBUG, PMD, "VNIC ID %x\n", vnic->fw_vnic_id);
1194                 return rc;
1195         }
1196
1197         rc = bnxt_hwrm_vnic_plcmodes_qcfg(bp, vnic, &pmodes);
1198         if (rc)
1199                 return rc;
1200
1201         HWRM_PREP(req, VNIC_CFG);
1202
1203         /* Only RSS support for now TBD: COS & LB */
1204         req.enables =
1205             rte_cpu_to_le_32(HWRM_VNIC_CFG_INPUT_ENABLES_DFLT_RING_GRP);
1206         if (vnic->lb_rule != 0xffff)
1207                 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_LB_RULE;
1208         if (vnic->cos_rule != 0xffff)
1209                 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_COS_RULE;
1210         if (vnic->rss_rule != 0xffff) {
1211                 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_MRU;
1212                 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_RSS_RULE;
1213         }
1214         req.enables |= rte_cpu_to_le_32(ctx_enable_flag);
1215         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1216         req.dflt_ring_grp = rte_cpu_to_le_16(vnic->dflt_ring_grp);
1217         req.rss_rule = rte_cpu_to_le_16(vnic->rss_rule);
1218         req.cos_rule = rte_cpu_to_le_16(vnic->cos_rule);
1219         req.lb_rule = rte_cpu_to_le_16(vnic->lb_rule);
1220         req.mru = rte_cpu_to_le_16(vnic->mru);
1221         if (vnic->func_default)
1222                 req.flags |=
1223                     rte_cpu_to_le_32(HWRM_VNIC_CFG_INPUT_FLAGS_DEFAULT);
1224         if (vnic->vlan_strip)
1225                 req.flags |=
1226                     rte_cpu_to_le_32(HWRM_VNIC_CFG_INPUT_FLAGS_VLAN_STRIP_MODE);
1227         if (vnic->bd_stall)
1228                 req.flags |=
1229                     rte_cpu_to_le_32(HWRM_VNIC_CFG_INPUT_FLAGS_BD_STALL_MODE);
1230         if (vnic->roce_dual)
1231                 req.flags |= rte_cpu_to_le_32(
1232                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_DUAL_VNIC_MODE);
1233         if (vnic->roce_only)
1234                 req.flags |= rte_cpu_to_le_32(
1235                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_ONLY_VNIC_MODE);
1236         if (vnic->rss_dflt_cr)
1237                 req.flags |= rte_cpu_to_le_32(
1238                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_RSS_DFLT_CR_MODE);
1239
1240         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
1241
1242         HWRM_CHECK_RESULT();
1243         HWRM_UNLOCK();
1244
1245         rc = bnxt_hwrm_vnic_plcmodes_cfg(bp, vnic, &pmodes);
1246
1247         return rc;
1248 }
1249
1250 int bnxt_hwrm_vnic_qcfg(struct bnxt *bp, struct bnxt_vnic_info *vnic,
1251                 int16_t fw_vf_id)
1252 {
1253         int rc = 0;
1254         struct hwrm_vnic_qcfg_input req = {.req_type = 0 };
1255         struct hwrm_vnic_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
1256
1257         if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
1258                 RTE_LOG(DEBUG, PMD, "VNIC QCFG ID %d\n", vnic->fw_vnic_id);
1259                 return rc;
1260         }
1261         HWRM_PREP(req, VNIC_QCFG);
1262
1263         req.enables =
1264                 rte_cpu_to_le_32(HWRM_VNIC_QCFG_INPUT_ENABLES_VF_ID_VALID);
1265         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1266         req.vf_id = rte_cpu_to_le_16(fw_vf_id);
1267
1268         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
1269
1270         HWRM_CHECK_RESULT();
1271
1272         vnic->dflt_ring_grp = rte_le_to_cpu_16(resp->dflt_ring_grp);
1273         vnic->rss_rule = rte_le_to_cpu_16(resp->rss_rule);
1274         vnic->cos_rule = rte_le_to_cpu_16(resp->cos_rule);
1275         vnic->lb_rule = rte_le_to_cpu_16(resp->lb_rule);
1276         vnic->mru = rte_le_to_cpu_16(resp->mru);
1277         vnic->func_default = rte_le_to_cpu_32(
1278                         resp->flags) & HWRM_VNIC_QCFG_OUTPUT_FLAGS_DEFAULT;
1279         vnic->vlan_strip = rte_le_to_cpu_32(resp->flags) &
1280                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_VLAN_STRIP_MODE;
1281         vnic->bd_stall = rte_le_to_cpu_32(resp->flags) &
1282                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_BD_STALL_MODE;
1283         vnic->roce_dual = rte_le_to_cpu_32(resp->flags) &
1284                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_DUAL_VNIC_MODE;
1285         vnic->roce_only = rte_le_to_cpu_32(resp->flags) &
1286                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_ONLY_VNIC_MODE;
1287         vnic->rss_dflt_cr = rte_le_to_cpu_32(resp->flags) &
1288                         HWRM_VNIC_QCFG_OUTPUT_FLAGS_RSS_DFLT_CR_MODE;
1289
1290         HWRM_UNLOCK();
1291
1292         return rc;
1293 }
1294
1295 int bnxt_hwrm_vnic_ctx_alloc(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1296 {
1297         int rc = 0;
1298         struct hwrm_vnic_rss_cos_lb_ctx_alloc_input req = {.req_type = 0 };
1299         struct hwrm_vnic_rss_cos_lb_ctx_alloc_output *resp =
1300                                                 bp->hwrm_cmd_resp_addr;
1301
1302         HWRM_PREP(req, VNIC_RSS_COS_LB_CTX_ALLOC);
1303
1304         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
1305
1306         HWRM_CHECK_RESULT();
1307
1308         vnic->rss_rule = rte_le_to_cpu_16(resp->rss_cos_lb_ctx_id);
1309         HWRM_UNLOCK();
1310         RTE_LOG(DEBUG, PMD, "VNIC RSS Rule %x\n", vnic->rss_rule);
1311
1312         return rc;
1313 }
1314
1315 int bnxt_hwrm_vnic_ctx_free(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1316 {
1317         int rc = 0;
1318         struct hwrm_vnic_rss_cos_lb_ctx_free_input req = {.req_type = 0 };
1319         struct hwrm_vnic_rss_cos_lb_ctx_free_output *resp =
1320                                                 bp->hwrm_cmd_resp_addr;
1321
1322         if (vnic->rss_rule == 0xffff) {
1323                 RTE_LOG(DEBUG, PMD, "VNIC RSS Rule %x\n", vnic->rss_rule);
1324                 return rc;
1325         }
1326         HWRM_PREP(req, VNIC_RSS_COS_LB_CTX_FREE);
1327
1328         req.rss_cos_lb_ctx_id = rte_cpu_to_le_16(vnic->rss_rule);
1329
1330         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
1331
1332         HWRM_CHECK_RESULT();
1333         HWRM_UNLOCK();
1334
1335         vnic->rss_rule = INVALID_HW_RING_ID;
1336
1337         return rc;
1338 }
1339
1340 int bnxt_hwrm_vnic_free(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1341 {
1342         int rc = 0;
1343         struct hwrm_vnic_free_input req = {.req_type = 0 };
1344         struct hwrm_vnic_free_output *resp = bp->hwrm_cmd_resp_addr;
1345
1346         if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
1347                 RTE_LOG(DEBUG, PMD, "VNIC FREE ID %x\n", vnic->fw_vnic_id);
1348                 return rc;
1349         }
1350
1351         HWRM_PREP(req, VNIC_FREE);
1352
1353         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1354
1355         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
1356
1357         HWRM_CHECK_RESULT();
1358         HWRM_UNLOCK();
1359
1360         vnic->fw_vnic_id = INVALID_HW_RING_ID;
1361         return rc;
1362 }
1363
1364 int bnxt_hwrm_vnic_rss_cfg(struct bnxt *bp,
1365                            struct bnxt_vnic_info *vnic)
1366 {
1367         int rc = 0;
1368         struct hwrm_vnic_rss_cfg_input req = {.req_type = 0 };
1369         struct hwrm_vnic_rss_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1370
1371         HWRM_PREP(req, VNIC_RSS_CFG);
1372
1373         req.hash_type = rte_cpu_to_le_32(vnic->hash_type);
1374
1375         req.ring_grp_tbl_addr =
1376             rte_cpu_to_le_64(vnic->rss_table_dma_addr);
1377         req.hash_key_tbl_addr =
1378             rte_cpu_to_le_64(vnic->rss_hash_key_dma_addr);
1379         req.rss_ctx_idx = rte_cpu_to_le_16(vnic->rss_rule);
1380
1381         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
1382
1383         HWRM_CHECK_RESULT();
1384         HWRM_UNLOCK();
1385
1386         return rc;
1387 }
1388
1389 int bnxt_hwrm_vnic_plcmode_cfg(struct bnxt *bp,
1390                         struct bnxt_vnic_info *vnic)
1391 {
1392         int rc = 0;
1393         struct hwrm_vnic_plcmodes_cfg_input req = {.req_type = 0 };
1394         struct hwrm_vnic_plcmodes_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1395         uint16_t size;
1396
1397         if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
1398                 RTE_LOG(DEBUG, PMD, "VNIC ID %x\n", vnic->fw_vnic_id);
1399                 return rc;
1400         }
1401
1402         HWRM_PREP(req, VNIC_PLCMODES_CFG);
1403
1404         req.flags = rte_cpu_to_le_32(
1405                         HWRM_VNIC_PLCMODES_CFG_INPUT_FLAGS_JUMBO_PLACEMENT);
1406
1407         req.enables = rte_cpu_to_le_32(
1408                 HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_JUMBO_THRESH_VALID);
1409
1410         size = rte_pktmbuf_data_room_size(bp->rx_queues[0]->mb_pool);
1411         size -= RTE_PKTMBUF_HEADROOM;
1412
1413         req.jumbo_thresh = rte_cpu_to_le_16(size);
1414         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1415
1416         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
1417
1418         HWRM_CHECK_RESULT();
1419         HWRM_UNLOCK();
1420
1421         return rc;
1422 }
1423
1424 int bnxt_hwrm_vnic_tpa_cfg(struct bnxt *bp,
1425                         struct bnxt_vnic_info *vnic, bool enable)
1426 {
1427         int rc = 0;
1428         struct hwrm_vnic_tpa_cfg_input req = {.req_type = 0 };
1429         struct hwrm_vnic_tpa_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1430
1431         HWRM_PREP(req, VNIC_TPA_CFG);
1432
1433         if (enable) {
1434                 req.enables = rte_cpu_to_le_32(
1435                                 HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MAX_AGG_SEGS |
1436                                 HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MAX_AGGS |
1437                                 HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MIN_AGG_LEN);
1438                 req.flags = rte_cpu_to_le_32(
1439                                 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_TPA |
1440                                 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_ENCAP_TPA |
1441                                 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_RSC_WND_UPDATE |
1442                                 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_GRO |
1443                                 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_AGG_WITH_ECN |
1444                         HWRM_VNIC_TPA_CFG_INPUT_FLAGS_AGG_WITH_SAME_GRE_SEQ);
1445                 req.max_agg_segs = rte_cpu_to_le_16(5);
1446                 req.max_aggs =
1447                         rte_cpu_to_le_16(HWRM_VNIC_TPA_CFG_INPUT_MAX_AGGS_MAX);
1448                 req.min_agg_len = rte_cpu_to_le_32(512);
1449         }
1450         req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1451
1452         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
1453
1454         HWRM_CHECK_RESULT();
1455         HWRM_UNLOCK();
1456
1457         return rc;
1458 }
1459
1460 int bnxt_hwrm_func_vf_mac(struct bnxt *bp, uint16_t vf, const uint8_t *mac_addr)
1461 {
1462         struct hwrm_func_cfg_input req = {0};
1463         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1464         int rc;
1465
1466         req.flags = rte_cpu_to_le_32(bp->pf.vf_info[vf].func_cfg_flags);
1467         req.enables = rte_cpu_to_le_32(
1468                         HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
1469         memcpy(req.dflt_mac_addr, mac_addr, sizeof(req.dflt_mac_addr));
1470         req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
1471
1472         HWRM_PREP(req, FUNC_CFG);
1473
1474         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
1475         HWRM_CHECK_RESULT();
1476         HWRM_UNLOCK();
1477
1478         bp->pf.vf_info[vf].random_mac = false;
1479
1480         return rc;
1481 }
1482
1483 int bnxt_hwrm_func_qstats_tx_drop(struct bnxt *bp, uint16_t fid,
1484                                   uint64_t *dropped)
1485 {
1486         int rc = 0;
1487         struct hwrm_func_qstats_input req = {.req_type = 0};
1488         struct hwrm_func_qstats_output *resp = bp->hwrm_cmd_resp_addr;
1489
1490         HWRM_PREP(req, FUNC_QSTATS);
1491
1492         req.fid = rte_cpu_to_le_16(fid);
1493
1494         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
1495
1496         HWRM_CHECK_RESULT();
1497
1498         if (dropped)
1499                 *dropped = rte_le_to_cpu_64(resp->tx_drop_pkts);
1500
1501         HWRM_UNLOCK();
1502
1503         return rc;
1504 }
1505
1506 int bnxt_hwrm_func_qstats(struct bnxt *bp, uint16_t fid,
1507                           struct rte_eth_stats *stats)
1508 {
1509         int rc = 0;
1510         struct hwrm_func_qstats_input req = {.req_type = 0};
1511         struct hwrm_func_qstats_output *resp = bp->hwrm_cmd_resp_addr;
1512
1513         HWRM_PREP(req, FUNC_QSTATS);
1514
1515         req.fid = rte_cpu_to_le_16(fid);
1516
1517         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
1518
1519         HWRM_CHECK_RESULT();
1520
1521         stats->ipackets = rte_le_to_cpu_64(resp->rx_ucast_pkts);
1522         stats->ipackets += rte_le_to_cpu_64(resp->rx_mcast_pkts);
1523         stats->ipackets += rte_le_to_cpu_64(resp->rx_bcast_pkts);
1524         stats->ibytes = rte_le_to_cpu_64(resp->rx_ucast_bytes);
1525         stats->ibytes += rte_le_to_cpu_64(resp->rx_mcast_bytes);
1526         stats->ibytes += rte_le_to_cpu_64(resp->rx_bcast_bytes);
1527
1528         stats->opackets = rte_le_to_cpu_64(resp->tx_ucast_pkts);
1529         stats->opackets += rte_le_to_cpu_64(resp->tx_mcast_pkts);
1530         stats->opackets += rte_le_to_cpu_64(resp->tx_bcast_pkts);
1531         stats->obytes = rte_le_to_cpu_64(resp->tx_ucast_bytes);
1532         stats->obytes += rte_le_to_cpu_64(resp->tx_mcast_bytes);
1533         stats->obytes += rte_le_to_cpu_64(resp->tx_bcast_bytes);
1534
1535         stats->ierrors = rte_le_to_cpu_64(resp->rx_err_pkts);
1536         stats->oerrors = rte_le_to_cpu_64(resp->tx_err_pkts);
1537
1538         stats->imissed = rte_le_to_cpu_64(resp->rx_drop_pkts);
1539
1540         HWRM_UNLOCK();
1541
1542         return rc;
1543 }
1544
1545 int bnxt_hwrm_func_clr_stats(struct bnxt *bp, uint16_t fid)
1546 {
1547         int rc = 0;
1548         struct hwrm_func_clr_stats_input req = {.req_type = 0};
1549         struct hwrm_func_clr_stats_output *resp = bp->hwrm_cmd_resp_addr;
1550
1551         HWRM_PREP(req, FUNC_CLR_STATS);
1552
1553         req.fid = rte_cpu_to_le_16(fid);
1554
1555         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
1556
1557         HWRM_CHECK_RESULT();
1558         HWRM_UNLOCK();
1559
1560         return rc;
1561 }
1562
1563 /*
1564  * HWRM utility functions
1565  */
1566
1567 int bnxt_clear_all_hwrm_stat_ctxs(struct bnxt *bp)
1568 {
1569         unsigned int i;
1570         int rc = 0;
1571
1572         for (i = 0; i < bp->rx_cp_nr_rings + bp->tx_cp_nr_rings; i++) {
1573                 struct bnxt_tx_queue *txq;
1574                 struct bnxt_rx_queue *rxq;
1575                 struct bnxt_cp_ring_info *cpr;
1576
1577                 if (i >= bp->rx_cp_nr_rings) {
1578                         txq = bp->tx_queues[i - bp->rx_cp_nr_rings];
1579                         cpr = txq->cp_ring;
1580                 } else {
1581                         rxq = bp->rx_queues[i];
1582                         cpr = rxq->cp_ring;
1583                 }
1584
1585                 rc = bnxt_hwrm_stat_clear(bp, cpr);
1586                 if (rc)
1587                         return rc;
1588         }
1589         return 0;
1590 }
1591
1592 int bnxt_free_all_hwrm_stat_ctxs(struct bnxt *bp)
1593 {
1594         int rc;
1595         unsigned int i;
1596         struct bnxt_cp_ring_info *cpr;
1597
1598         for (i = 0; i < bp->rx_cp_nr_rings + bp->tx_cp_nr_rings; i++) {
1599
1600                 if (i >= bp->rx_cp_nr_rings) {
1601                         cpr = bp->tx_queues[i - bp->rx_cp_nr_rings]->cp_ring;
1602                 } else {
1603                         cpr = bp->rx_queues[i]->cp_ring;
1604                         bp->grp_info[i].fw_stats_ctx = -1;
1605                 }
1606                 if (cpr->hw_stats_ctx_id != HWRM_NA_SIGNATURE) {
1607                         rc = bnxt_hwrm_stat_ctx_free(bp, cpr, i);
1608                         cpr->hw_stats_ctx_id = HWRM_NA_SIGNATURE;
1609                         if (rc)
1610                                 return rc;
1611                 }
1612         }
1613         return 0;
1614 }
1615
1616 int bnxt_alloc_all_hwrm_stat_ctxs(struct bnxt *bp)
1617 {
1618         unsigned int i;
1619         int rc = 0;
1620
1621         for (i = 0; i < bp->rx_cp_nr_rings + bp->tx_cp_nr_rings; i++) {
1622                 struct bnxt_tx_queue *txq;
1623                 struct bnxt_rx_queue *rxq;
1624                 struct bnxt_cp_ring_info *cpr;
1625
1626                 if (i >= bp->rx_cp_nr_rings) {
1627                         txq = bp->tx_queues[i - bp->rx_cp_nr_rings];
1628                         cpr = txq->cp_ring;
1629                 } else {
1630                         rxq = bp->rx_queues[i];
1631                         cpr = rxq->cp_ring;
1632                 }
1633
1634                 rc = bnxt_hwrm_stat_ctx_alloc(bp, cpr, i);
1635
1636                 if (rc)
1637                         return rc;
1638         }
1639         return rc;
1640 }
1641
1642 int bnxt_free_all_hwrm_ring_grps(struct bnxt *bp)
1643 {
1644         uint16_t idx;
1645         uint32_t rc = 0;
1646
1647         for (idx = 0; idx < bp->rx_cp_nr_rings; idx++) {
1648
1649                 if (bp->grp_info[idx].fw_grp_id == INVALID_HW_RING_ID)
1650                         continue;
1651
1652                 rc = bnxt_hwrm_ring_grp_free(bp, idx);
1653
1654                 if (rc)
1655                         return rc;
1656         }
1657         return rc;
1658 }
1659
1660 static void bnxt_free_cp_ring(struct bnxt *bp, struct bnxt_cp_ring_info *cpr,
1661                                 unsigned int idx __rte_unused)
1662 {
1663         struct bnxt_ring *cp_ring = cpr->cp_ring_struct;
1664
1665         bnxt_hwrm_ring_free(bp, cp_ring,
1666                         HWRM_RING_FREE_INPUT_RING_TYPE_L2_CMPL);
1667         cp_ring->fw_ring_id = INVALID_HW_RING_ID;
1668         memset(cpr->cp_desc_ring, 0, cpr->cp_ring_struct->ring_size *
1669                         sizeof(*cpr->cp_desc_ring));
1670         cpr->cp_raw_cons = 0;
1671 }
1672
1673 int bnxt_free_all_hwrm_rings(struct bnxt *bp)
1674 {
1675         unsigned int i;
1676         int rc = 0;
1677
1678         for (i = 0; i < bp->tx_cp_nr_rings; i++) {
1679                 struct bnxt_tx_queue *txq = bp->tx_queues[i];
1680                 struct bnxt_tx_ring_info *txr = txq->tx_ring;
1681                 struct bnxt_ring *ring = txr->tx_ring_struct;
1682                 struct bnxt_cp_ring_info *cpr = txq->cp_ring;
1683                 unsigned int idx = bp->rx_cp_nr_rings + i + 1;
1684
1685                 if (ring->fw_ring_id != INVALID_HW_RING_ID) {
1686                         bnxt_hwrm_ring_free(bp, ring,
1687                                         HWRM_RING_FREE_INPUT_RING_TYPE_TX);
1688                         ring->fw_ring_id = INVALID_HW_RING_ID;
1689                         memset(txr->tx_desc_ring, 0,
1690                                         txr->tx_ring_struct->ring_size *
1691                                         sizeof(*txr->tx_desc_ring));
1692                         memset(txr->tx_buf_ring, 0,
1693                                         txr->tx_ring_struct->ring_size *
1694                                         sizeof(*txr->tx_buf_ring));
1695                         txr->tx_prod = 0;
1696                         txr->tx_cons = 0;
1697                 }
1698                 if (cpr->cp_ring_struct->fw_ring_id != INVALID_HW_RING_ID) {
1699                         bnxt_free_cp_ring(bp, cpr, idx);
1700                         cpr->cp_ring_struct->fw_ring_id = INVALID_HW_RING_ID;
1701                 }
1702         }
1703
1704         for (i = 0; i < bp->rx_cp_nr_rings; i++) {
1705                 struct bnxt_rx_queue *rxq = bp->rx_queues[i];
1706                 struct bnxt_rx_ring_info *rxr = rxq->rx_ring;
1707                 struct bnxt_ring *ring = rxr->rx_ring_struct;
1708                 struct bnxt_cp_ring_info *cpr = rxq->cp_ring;
1709                 unsigned int idx = i + 1;
1710
1711                 if (ring->fw_ring_id != INVALID_HW_RING_ID) {
1712                         bnxt_hwrm_ring_free(bp, ring,
1713                                         HWRM_RING_FREE_INPUT_RING_TYPE_RX);
1714                         ring->fw_ring_id = INVALID_HW_RING_ID;
1715                         bp->grp_info[idx].rx_fw_ring_id = INVALID_HW_RING_ID;
1716                         memset(rxr->rx_desc_ring, 0,
1717                                         rxr->rx_ring_struct->ring_size *
1718                                         sizeof(*rxr->rx_desc_ring));
1719                         memset(rxr->rx_buf_ring, 0,
1720                                         rxr->rx_ring_struct->ring_size *
1721                                         sizeof(*rxr->rx_buf_ring));
1722                         rxr->rx_prod = 0;
1723                 }
1724                 ring = rxr->ag_ring_struct;
1725                 if (ring->fw_ring_id != INVALID_HW_RING_ID) {
1726                         bnxt_hwrm_ring_free(bp, ring,
1727                                             HWRM_RING_FREE_INPUT_RING_TYPE_RX);
1728                         ring->fw_ring_id = INVALID_HW_RING_ID;
1729                         memset(rxr->ag_buf_ring, 0,
1730                                rxr->ag_ring_struct->ring_size *
1731                                sizeof(*rxr->ag_buf_ring));
1732                         rxr->ag_prod = 0;
1733                         bp->grp_info[i].ag_fw_ring_id = INVALID_HW_RING_ID;
1734                 }
1735                 if (cpr->cp_ring_struct->fw_ring_id != INVALID_HW_RING_ID) {
1736                         bnxt_free_cp_ring(bp, cpr, idx);
1737                         bp->grp_info[i].cp_fw_ring_id = INVALID_HW_RING_ID;
1738                         cpr->cp_ring_struct->fw_ring_id = INVALID_HW_RING_ID;
1739                 }
1740         }
1741
1742         /* Default completion ring */
1743         {
1744                 struct bnxt_cp_ring_info *cpr = bp->def_cp_ring;
1745
1746                 if (cpr->cp_ring_struct->fw_ring_id != INVALID_HW_RING_ID) {
1747                         bnxt_free_cp_ring(bp, cpr, 0);
1748                         cpr->cp_ring_struct->fw_ring_id = INVALID_HW_RING_ID;
1749                 }
1750         }
1751
1752         return rc;
1753 }
1754
1755 int bnxt_alloc_all_hwrm_ring_grps(struct bnxt *bp)
1756 {
1757         uint16_t i;
1758         uint32_t rc = 0;
1759
1760         for (i = 0; i < bp->rx_cp_nr_rings; i++) {
1761                 rc = bnxt_hwrm_ring_grp_alloc(bp, i);
1762                 if (rc)
1763                         return rc;
1764         }
1765         return rc;
1766 }
1767
1768 void bnxt_free_hwrm_resources(struct bnxt *bp)
1769 {
1770         /* Release memzone */
1771         rte_free(bp->hwrm_cmd_resp_addr);
1772         rte_free(bp->hwrm_short_cmd_req_addr);
1773         bp->hwrm_cmd_resp_addr = NULL;
1774         bp->hwrm_short_cmd_req_addr = NULL;
1775         bp->hwrm_cmd_resp_dma_addr = 0;
1776         bp->hwrm_short_cmd_req_dma_addr = 0;
1777 }
1778
1779 int bnxt_alloc_hwrm_resources(struct bnxt *bp)
1780 {
1781         struct rte_pci_device *pdev = bp->pdev;
1782         char type[RTE_MEMZONE_NAMESIZE];
1783
1784         sprintf(type, "bnxt_hwrm_%04x:%02x:%02x:%02x", pdev->addr.domain,
1785                 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
1786         bp->max_resp_len = HWRM_MAX_RESP_LEN;
1787         bp->hwrm_cmd_resp_addr = rte_malloc(type, bp->max_resp_len, 0);
1788         rte_mem_lock_page(bp->hwrm_cmd_resp_addr);
1789         if (bp->hwrm_cmd_resp_addr == NULL)
1790                 return -ENOMEM;
1791         bp->hwrm_cmd_resp_dma_addr =
1792                 rte_mem_virt2iova(bp->hwrm_cmd_resp_addr);
1793         if (bp->hwrm_cmd_resp_dma_addr == 0) {
1794                 RTE_LOG(ERR, PMD,
1795                         "unable to map response address to physical memory\n");
1796                 return -ENOMEM;
1797         }
1798         rte_spinlock_init(&bp->hwrm_lock);
1799
1800         return 0;
1801 }
1802
1803 int bnxt_clear_hwrm_vnic_filters(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1804 {
1805         struct bnxt_filter_info *filter;
1806         int rc = 0;
1807
1808         STAILQ_FOREACH(filter, &vnic->filter, next) {
1809                 if (filter->filter_type == HWRM_CFA_EM_FILTER)
1810                         rc = bnxt_hwrm_clear_em_filter(bp, filter);
1811                 else if (filter->filter_type == HWRM_CFA_NTUPLE_FILTER)
1812                         rc = bnxt_hwrm_clear_ntuple_filter(bp, filter);
1813                 else
1814                         rc = bnxt_hwrm_clear_l2_filter(bp, filter);
1815                 STAILQ_REMOVE(&vnic->filter, filter, bnxt_filter_info, next);
1816                 //if (rc)
1817                         //break;
1818         }
1819         return rc;
1820 }
1821
1822 static int
1823 bnxt_clear_hwrm_vnic_flows(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1824 {
1825         struct bnxt_filter_info *filter;
1826         struct rte_flow *flow;
1827         int rc = 0;
1828
1829         STAILQ_FOREACH(flow, &vnic->flow_list, next) {
1830                 filter = flow->filter;
1831                 RTE_LOG(ERR, PMD, "filter type %d\n", filter->filter_type);
1832                 if (filter->filter_type == HWRM_CFA_EM_FILTER)
1833                         rc = bnxt_hwrm_clear_em_filter(bp, filter);
1834                 else if (filter->filter_type == HWRM_CFA_NTUPLE_FILTER)
1835                         rc = bnxt_hwrm_clear_ntuple_filter(bp, filter);
1836                 else
1837                         rc = bnxt_hwrm_clear_l2_filter(bp, filter);
1838
1839                 STAILQ_REMOVE(&vnic->flow_list, flow, rte_flow, next);
1840                 rte_free(flow);
1841                 //if (rc)
1842                         //break;
1843         }
1844         return rc;
1845 }
1846
1847 int bnxt_set_hwrm_vnic_filters(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1848 {
1849         struct bnxt_filter_info *filter;
1850         int rc = 0;
1851
1852         STAILQ_FOREACH(filter, &vnic->filter, next) {
1853                 if (filter->filter_type == HWRM_CFA_EM_FILTER)
1854                         rc = bnxt_hwrm_set_em_filter(bp, filter->dst_id,
1855                                                      filter);
1856                 else if (filter->filter_type == HWRM_CFA_NTUPLE_FILTER)
1857                         rc = bnxt_hwrm_set_ntuple_filter(bp, filter->dst_id,
1858                                                          filter);
1859                 else
1860                         rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id,
1861                                                      filter);
1862                 if (rc)
1863                         break;
1864         }
1865         return rc;
1866 }
1867
1868 void bnxt_free_tunnel_ports(struct bnxt *bp)
1869 {
1870         if (bp->vxlan_port_cnt)
1871                 bnxt_hwrm_tunnel_dst_port_free(bp, bp->vxlan_fw_dst_port_id,
1872                         HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN);
1873         bp->vxlan_port = 0;
1874         if (bp->geneve_port_cnt)
1875                 bnxt_hwrm_tunnel_dst_port_free(bp, bp->geneve_fw_dst_port_id,
1876                         HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE);
1877         bp->geneve_port = 0;
1878 }
1879
1880 void bnxt_free_all_hwrm_resources(struct bnxt *bp)
1881 {
1882         int i;
1883
1884         if (bp->vnic_info == NULL)
1885                 return;
1886
1887         /*
1888          * Cleanup VNICs in reverse order, to make sure the L2 filter
1889          * from vnic0 is last to be cleaned up.
1890          */
1891         for (i = bp->nr_vnics - 1; i >= 0; i--) {
1892                 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
1893
1894                 bnxt_clear_hwrm_vnic_flows(bp, vnic);
1895
1896                 bnxt_clear_hwrm_vnic_filters(bp, vnic);
1897
1898                 bnxt_hwrm_vnic_ctx_free(bp, vnic);
1899
1900                 bnxt_hwrm_vnic_tpa_cfg(bp, vnic, false);
1901
1902                 bnxt_hwrm_vnic_free(bp, vnic);
1903
1904                 rte_free(vnic->fw_grp_ids);
1905         }
1906         /* Ring resources */
1907         bnxt_free_all_hwrm_rings(bp);
1908         bnxt_free_all_hwrm_ring_grps(bp);
1909         bnxt_free_all_hwrm_stat_ctxs(bp);
1910         bnxt_free_tunnel_ports(bp);
1911 }
1912
1913 static uint16_t bnxt_parse_eth_link_duplex(uint32_t conf_link_speed)
1914 {
1915         uint8_t hw_link_duplex = HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH;
1916
1917         if ((conf_link_speed & ETH_LINK_SPEED_FIXED) == ETH_LINK_SPEED_AUTONEG)
1918                 return HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH;
1919
1920         switch (conf_link_speed) {
1921         case ETH_LINK_SPEED_10M_HD:
1922         case ETH_LINK_SPEED_100M_HD:
1923                 return HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_HALF;
1924         }
1925         return hw_link_duplex;
1926 }
1927
1928 static uint16_t bnxt_check_eth_link_autoneg(uint32_t conf_link)
1929 {
1930         return (conf_link & ETH_LINK_SPEED_FIXED) ? 0 : 1;
1931 }
1932
1933 static uint16_t bnxt_parse_eth_link_speed(uint32_t conf_link_speed)
1934 {
1935         uint16_t eth_link_speed = 0;
1936
1937         if (conf_link_speed == ETH_LINK_SPEED_AUTONEG)
1938                 return ETH_LINK_SPEED_AUTONEG;
1939
1940         switch (conf_link_speed & ~ETH_LINK_SPEED_FIXED) {
1941         case ETH_LINK_SPEED_100M:
1942         case ETH_LINK_SPEED_100M_HD:
1943                 eth_link_speed =
1944                         HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_100MB;
1945                 break;
1946         case ETH_LINK_SPEED_1G:
1947                 eth_link_speed =
1948                         HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_1GB;
1949                 break;
1950         case ETH_LINK_SPEED_2_5G:
1951                 eth_link_speed =
1952                         HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_2_5GB;
1953                 break;
1954         case ETH_LINK_SPEED_10G:
1955                 eth_link_speed =
1956                         HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_10GB;
1957                 break;
1958         case ETH_LINK_SPEED_20G:
1959                 eth_link_speed =
1960                         HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_20GB;
1961                 break;
1962         case ETH_LINK_SPEED_25G:
1963                 eth_link_speed =
1964                         HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_25GB;
1965                 break;
1966         case ETH_LINK_SPEED_40G:
1967                 eth_link_speed =
1968                         HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_40GB;
1969                 break;
1970         case ETH_LINK_SPEED_50G:
1971                 eth_link_speed =
1972                         HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_50GB;
1973                 break;
1974         default:
1975                 RTE_LOG(ERR, PMD,
1976                         "Unsupported link speed %d; default to AUTO\n",
1977                         conf_link_speed);
1978                 break;
1979         }
1980         return eth_link_speed;
1981 }
1982
1983 #define BNXT_SUPPORTED_SPEEDS (ETH_LINK_SPEED_100M | ETH_LINK_SPEED_100M_HD | \
1984                 ETH_LINK_SPEED_1G | ETH_LINK_SPEED_2_5G | \
1985                 ETH_LINK_SPEED_10G | ETH_LINK_SPEED_20G | ETH_LINK_SPEED_25G | \
1986                 ETH_LINK_SPEED_40G | ETH_LINK_SPEED_50G)
1987
1988 static int bnxt_valid_link_speed(uint32_t link_speed, uint16_t port_id)
1989 {
1990         uint32_t one_speed;
1991
1992         if (link_speed == ETH_LINK_SPEED_AUTONEG)
1993                 return 0;
1994
1995         if (link_speed & ETH_LINK_SPEED_FIXED) {
1996                 one_speed = link_speed & ~ETH_LINK_SPEED_FIXED;
1997
1998                 if (one_speed & (one_speed - 1)) {
1999                         RTE_LOG(ERR, PMD,
2000                                 "Invalid advertised speeds (%u) for port %u\n",
2001                                 link_speed, port_id);
2002                         return -EINVAL;
2003                 }
2004                 if ((one_speed & BNXT_SUPPORTED_SPEEDS) != one_speed) {
2005                         RTE_LOG(ERR, PMD,
2006                                 "Unsupported advertised speed (%u) for port %u\n",
2007                                 link_speed, port_id);
2008                         return -EINVAL;
2009                 }
2010         } else {
2011                 if (!(link_speed & BNXT_SUPPORTED_SPEEDS)) {
2012                         RTE_LOG(ERR, PMD,
2013                                 "Unsupported advertised speeds (%u) for port %u\n",
2014                                 link_speed, port_id);
2015                         return -EINVAL;
2016                 }
2017         }
2018         return 0;
2019 }
2020
2021 static uint16_t
2022 bnxt_parse_eth_link_speed_mask(struct bnxt *bp, uint32_t link_speed)
2023 {
2024         uint16_t ret = 0;
2025
2026         if (link_speed == ETH_LINK_SPEED_AUTONEG) {
2027                 if (bp->link_info.support_speeds)
2028                         return bp->link_info.support_speeds;
2029                 link_speed = BNXT_SUPPORTED_SPEEDS;
2030         }
2031
2032         if (link_speed & ETH_LINK_SPEED_100M)
2033                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100MB;
2034         if (link_speed & ETH_LINK_SPEED_100M_HD)
2035                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100MB;
2036         if (link_speed & ETH_LINK_SPEED_1G)
2037                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_1GB;
2038         if (link_speed & ETH_LINK_SPEED_2_5G)
2039                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_2_5GB;
2040         if (link_speed & ETH_LINK_SPEED_10G)
2041                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_10GB;
2042         if (link_speed & ETH_LINK_SPEED_20G)
2043                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_20GB;
2044         if (link_speed & ETH_LINK_SPEED_25G)
2045                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_25GB;
2046         if (link_speed & ETH_LINK_SPEED_40G)
2047                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_40GB;
2048         if (link_speed & ETH_LINK_SPEED_50G)
2049                 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_50GB;
2050         return ret;
2051 }
2052
2053 static uint32_t bnxt_parse_hw_link_speed(uint16_t hw_link_speed)
2054 {
2055         uint32_t eth_link_speed = ETH_SPEED_NUM_NONE;
2056
2057         switch (hw_link_speed) {
2058         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_100MB:
2059                 eth_link_speed = ETH_SPEED_NUM_100M;
2060                 break;
2061         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_1GB:
2062                 eth_link_speed = ETH_SPEED_NUM_1G;
2063                 break;
2064         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_2_5GB:
2065                 eth_link_speed = ETH_SPEED_NUM_2_5G;
2066                 break;
2067         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_10GB:
2068                 eth_link_speed = ETH_SPEED_NUM_10G;
2069                 break;
2070         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_20GB:
2071                 eth_link_speed = ETH_SPEED_NUM_20G;
2072                 break;
2073         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_25GB:
2074                 eth_link_speed = ETH_SPEED_NUM_25G;
2075                 break;
2076         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_40GB:
2077                 eth_link_speed = ETH_SPEED_NUM_40G;
2078                 break;
2079         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_50GB:
2080                 eth_link_speed = ETH_SPEED_NUM_50G;
2081                 break;
2082         case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_2GB:
2083         default:
2084                 RTE_LOG(ERR, PMD, "HWRM link speed %d not defined\n",
2085                         hw_link_speed);
2086                 break;
2087         }
2088         return eth_link_speed;
2089 }
2090
2091 static uint16_t bnxt_parse_hw_link_duplex(uint16_t hw_link_duplex)
2092 {
2093         uint16_t eth_link_duplex = ETH_LINK_FULL_DUPLEX;
2094
2095         switch (hw_link_duplex) {
2096         case HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH:
2097         case HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_FULL:
2098                 eth_link_duplex = ETH_LINK_FULL_DUPLEX;
2099                 break;
2100         case HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_HALF:
2101                 eth_link_duplex = ETH_LINK_HALF_DUPLEX;
2102                 break;
2103         default:
2104                 RTE_LOG(ERR, PMD, "HWRM link duplex %d not defined\n",
2105                         hw_link_duplex);
2106                 break;
2107         }
2108         return eth_link_duplex;
2109 }
2110
2111 int bnxt_get_hwrm_link_config(struct bnxt *bp, struct rte_eth_link *link)
2112 {
2113         int rc = 0;
2114         struct bnxt_link_info *link_info = &bp->link_info;
2115
2116         rc = bnxt_hwrm_port_phy_qcfg(bp, link_info);
2117         if (rc) {
2118                 RTE_LOG(ERR, PMD,
2119                         "Get link config failed with rc %d\n", rc);
2120                 goto exit;
2121         }
2122         if (link_info->link_speed)
2123                 link->link_speed =
2124                         bnxt_parse_hw_link_speed(link_info->link_speed);
2125         else
2126                 link->link_speed = ETH_SPEED_NUM_NONE;
2127         link->link_duplex = bnxt_parse_hw_link_duplex(link_info->duplex);
2128         link->link_status = link_info->link_up;
2129         link->link_autoneg = link_info->auto_mode ==
2130                 HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_MODE_NONE ?
2131                 ETH_LINK_FIXED : ETH_LINK_AUTONEG;
2132 exit:
2133         return rc;
2134 }
2135
2136 int bnxt_set_hwrm_link_config(struct bnxt *bp, bool link_up)
2137 {
2138         int rc = 0;
2139         struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
2140         struct bnxt_link_info link_req;
2141         uint16_t speed, autoneg;
2142
2143         if (BNXT_NPAR_PF(bp) || BNXT_VF(bp))
2144                 return 0;
2145
2146         rc = bnxt_valid_link_speed(dev_conf->link_speeds,
2147                         bp->eth_dev->data->port_id);
2148         if (rc)
2149                 goto error;
2150
2151         memset(&link_req, 0, sizeof(link_req));
2152         link_req.link_up = link_up;
2153         if (!link_up)
2154                 goto port_phy_cfg;
2155
2156         autoneg = bnxt_check_eth_link_autoneg(dev_conf->link_speeds);
2157         speed = bnxt_parse_eth_link_speed(dev_conf->link_speeds);
2158         link_req.phy_flags = HWRM_PORT_PHY_CFG_INPUT_FLAGS_RESET_PHY;
2159         /* Autoneg can be done only when the FW allows */
2160         if (autoneg == 1 && !(bp->link_info.auto_link_speed ||
2161                                 bp->link_info.force_link_speed)) {
2162                 link_req.phy_flags |=
2163                                 HWRM_PORT_PHY_CFG_INPUT_FLAGS_RESTART_AUTONEG;
2164                 link_req.auto_link_speed_mask =
2165                         bnxt_parse_eth_link_speed_mask(bp,
2166                                                        dev_conf->link_speeds);
2167         } else {
2168                 if (bp->link_info.phy_type ==
2169                     HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASET ||
2170                     bp->link_info.phy_type ==
2171                     HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASETE ||
2172                     bp->link_info.media_type ==
2173                     HWRM_PORT_PHY_QCFG_OUTPUT_MEDIA_TYPE_TP) {
2174                         RTE_LOG(ERR, PMD, "10GBase-T devices must autoneg\n");
2175                         return -EINVAL;
2176                 }
2177
2178                 link_req.phy_flags |= HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE;
2179                 /* If user wants a particular speed try that first. */
2180                 if (speed)
2181                         link_req.link_speed = speed;
2182                 else if (bp->link_info.force_link_speed)
2183                         link_req.link_speed = bp->link_info.force_link_speed;
2184                 else
2185                         link_req.link_speed = bp->link_info.auto_link_speed;
2186         }
2187         link_req.duplex = bnxt_parse_eth_link_duplex(dev_conf->link_speeds);
2188         link_req.auto_pause = bp->link_info.auto_pause;
2189         link_req.force_pause = bp->link_info.force_pause;
2190
2191 port_phy_cfg:
2192         rc = bnxt_hwrm_port_phy_cfg(bp, &link_req);
2193         if (rc) {
2194                 RTE_LOG(ERR, PMD,
2195                         "Set link config failed with rc %d\n", rc);
2196         }
2197
2198 error:
2199         return rc;
2200 }
2201
2202 /* JIRA 22088 */
2203 int bnxt_hwrm_func_qcfg(struct bnxt *bp)
2204 {
2205         struct hwrm_func_qcfg_input req = {0};
2206         struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
2207         int rc = 0;
2208
2209         HWRM_PREP(req, FUNC_QCFG);
2210         req.fid = rte_cpu_to_le_16(0xffff);
2211
2212         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2213
2214         HWRM_CHECK_RESULT();
2215
2216         /* Hard Coded.. 0xfff VLAN ID mask */
2217         bp->vlan = rte_le_to_cpu_16(resp->vlan) & 0xfff;
2218
2219         switch (resp->port_partition_type) {
2220         case HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR1_0:
2221         case HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR1_5:
2222         case HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR2_0:
2223                 bp->port_partition_type = resp->port_partition_type;
2224                 break;
2225         default:
2226                 bp->port_partition_type = 0;
2227                 break;
2228         }
2229
2230         HWRM_UNLOCK();
2231
2232         return rc;
2233 }
2234
2235 static void copy_func_cfg_to_qcaps(struct hwrm_func_cfg_input *fcfg,
2236                                    struct hwrm_func_qcaps_output *qcaps)
2237 {
2238         qcaps->max_rsscos_ctx = fcfg->num_rsscos_ctxs;
2239         memcpy(qcaps->mac_address, fcfg->dflt_mac_addr,
2240                sizeof(qcaps->mac_address));
2241         qcaps->max_l2_ctxs = fcfg->num_l2_ctxs;
2242         qcaps->max_rx_rings = fcfg->num_rx_rings;
2243         qcaps->max_tx_rings = fcfg->num_tx_rings;
2244         qcaps->max_cmpl_rings = fcfg->num_cmpl_rings;
2245         qcaps->max_stat_ctx = fcfg->num_stat_ctxs;
2246         qcaps->max_vfs = 0;
2247         qcaps->first_vf_id = 0;
2248         qcaps->max_vnics = fcfg->num_vnics;
2249         qcaps->max_decap_records = 0;
2250         qcaps->max_encap_records = 0;
2251         qcaps->max_tx_wm_flows = 0;
2252         qcaps->max_tx_em_flows = 0;
2253         qcaps->max_rx_wm_flows = 0;
2254         qcaps->max_rx_em_flows = 0;
2255         qcaps->max_flow_id = 0;
2256         qcaps->max_mcast_filters = fcfg->num_mcast_filters;
2257         qcaps->max_sp_tx_rings = 0;
2258         qcaps->max_hw_ring_grps = fcfg->num_hw_ring_grps;
2259 }
2260
2261 static int bnxt_hwrm_pf_func_cfg(struct bnxt *bp, int tx_rings)
2262 {
2263         struct hwrm_func_cfg_input req = {0};
2264         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2265         int rc;
2266
2267         req.enables = rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_MTU |
2268                         HWRM_FUNC_CFG_INPUT_ENABLES_MRU |
2269                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS |
2270                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_STAT_CTXS |
2271                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_CMPL_RINGS |
2272                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_TX_RINGS |
2273                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RX_RINGS |
2274                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_L2_CTXS |
2275                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_VNICS |
2276                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_HW_RING_GRPS);
2277         req.flags = rte_cpu_to_le_32(bp->pf.func_cfg_flags);
2278         req.mtu = rte_cpu_to_le_16(BNXT_MAX_MTU);
2279         req.mru = rte_cpu_to_le_16(bp->eth_dev->data->mtu + ETHER_HDR_LEN +
2280                                    ETHER_CRC_LEN + VLAN_TAG_SIZE);
2281         req.num_rsscos_ctxs = rte_cpu_to_le_16(bp->max_rsscos_ctx);
2282         req.num_stat_ctxs = rte_cpu_to_le_16(bp->max_stat_ctx);
2283         req.num_cmpl_rings = rte_cpu_to_le_16(bp->max_cp_rings);
2284         req.num_tx_rings = rte_cpu_to_le_16(tx_rings);
2285         req.num_rx_rings = rte_cpu_to_le_16(bp->max_rx_rings);
2286         req.num_l2_ctxs = rte_cpu_to_le_16(bp->max_l2_ctx);
2287         req.num_vnics = rte_cpu_to_le_16(bp->max_vnics);
2288         req.num_hw_ring_grps = rte_cpu_to_le_16(bp->max_ring_grps);
2289         req.fid = rte_cpu_to_le_16(0xffff);
2290
2291         HWRM_PREP(req, FUNC_CFG);
2292
2293         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2294
2295         HWRM_CHECK_RESULT();
2296         HWRM_UNLOCK();
2297
2298         return rc;
2299 }
2300
2301 static void populate_vf_func_cfg_req(struct bnxt *bp,
2302                                      struct hwrm_func_cfg_input *req,
2303                                      int num_vfs)
2304 {
2305         req->enables = rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_MTU |
2306                         HWRM_FUNC_CFG_INPUT_ENABLES_MRU |
2307                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS |
2308                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_STAT_CTXS |
2309                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_CMPL_RINGS |
2310                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_TX_RINGS |
2311                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RX_RINGS |
2312                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_L2_CTXS |
2313                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_VNICS |
2314                         HWRM_FUNC_CFG_INPUT_ENABLES_NUM_HW_RING_GRPS);
2315
2316         req->mtu = rte_cpu_to_le_16(bp->eth_dev->data->mtu + ETHER_HDR_LEN +
2317                                     ETHER_CRC_LEN + VLAN_TAG_SIZE);
2318         req->mru = rte_cpu_to_le_16(bp->eth_dev->data->mtu + ETHER_HDR_LEN +
2319                                     ETHER_CRC_LEN + VLAN_TAG_SIZE);
2320         req->num_rsscos_ctxs = rte_cpu_to_le_16(bp->max_rsscos_ctx /
2321                                                 (num_vfs + 1));
2322         req->num_stat_ctxs = rte_cpu_to_le_16(bp->max_stat_ctx / (num_vfs + 1));
2323         req->num_cmpl_rings = rte_cpu_to_le_16(bp->max_cp_rings /
2324                                                (num_vfs + 1));
2325         req->num_tx_rings = rte_cpu_to_le_16(bp->max_tx_rings / (num_vfs + 1));
2326         req->num_rx_rings = rte_cpu_to_le_16(bp->max_rx_rings / (num_vfs + 1));
2327         req->num_l2_ctxs = rte_cpu_to_le_16(bp->max_l2_ctx / (num_vfs + 1));
2328         /* TODO: For now, do not support VMDq/RFS on VFs. */
2329         req->num_vnics = rte_cpu_to_le_16(1);
2330         req->num_hw_ring_grps = rte_cpu_to_le_16(bp->max_ring_grps /
2331                                                  (num_vfs + 1));
2332 }
2333
2334 static void add_random_mac_if_needed(struct bnxt *bp,
2335                                      struct hwrm_func_cfg_input *cfg_req,
2336                                      int vf)
2337 {
2338         struct ether_addr mac;
2339
2340         if (bnxt_hwrm_func_qcfg_vf_default_mac(bp, vf, &mac))
2341                 return;
2342
2343         if (memcmp(mac.addr_bytes, "\x00\x00\x00\x00\x00", 6) == 0) {
2344                 cfg_req->enables |=
2345                 rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
2346                 eth_random_addr(cfg_req->dflt_mac_addr);
2347                 bp->pf.vf_info[vf].random_mac = true;
2348         } else {
2349                 memcpy(cfg_req->dflt_mac_addr, mac.addr_bytes, ETHER_ADDR_LEN);
2350         }
2351 }
2352
2353 static void reserve_resources_from_vf(struct bnxt *bp,
2354                                       struct hwrm_func_cfg_input *cfg_req,
2355                                       int vf)
2356 {
2357         struct hwrm_func_qcaps_input req = {0};
2358         struct hwrm_func_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
2359         int rc;
2360
2361         /* Get the actual allocated values now */
2362         HWRM_PREP(req, FUNC_QCAPS);
2363         req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
2364         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2365
2366         if (rc) {
2367                 RTE_LOG(ERR, PMD, "hwrm_func_qcaps failed rc:%d\n", rc);
2368                 copy_func_cfg_to_qcaps(cfg_req, resp);
2369         } else if (resp->error_code) {
2370                 rc = rte_le_to_cpu_16(resp->error_code);
2371                 RTE_LOG(ERR, PMD, "hwrm_func_qcaps error %d\n", rc);
2372                 copy_func_cfg_to_qcaps(cfg_req, resp);
2373         }
2374
2375         bp->max_rsscos_ctx -= rte_le_to_cpu_16(resp->max_rsscos_ctx);
2376         bp->max_stat_ctx -= rte_le_to_cpu_16(resp->max_stat_ctx);
2377         bp->max_cp_rings -= rte_le_to_cpu_16(resp->max_cmpl_rings);
2378         bp->max_tx_rings -= rte_le_to_cpu_16(resp->max_tx_rings);
2379         bp->max_rx_rings -= rte_le_to_cpu_16(resp->max_rx_rings);
2380         bp->max_l2_ctx -= rte_le_to_cpu_16(resp->max_l2_ctxs);
2381         /*
2382          * TODO: While not supporting VMDq with VFs, max_vnics is always
2383          * forced to 1 in this case
2384          */
2385         //bp->max_vnics -= rte_le_to_cpu_16(esp->max_vnics);
2386         bp->max_ring_grps -= rte_le_to_cpu_16(resp->max_hw_ring_grps);
2387
2388         HWRM_UNLOCK();
2389 }
2390
2391 int bnxt_hwrm_func_qcfg_current_vf_vlan(struct bnxt *bp, int vf)
2392 {
2393         struct hwrm_func_qcfg_input req = {0};
2394         struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
2395         int rc;
2396
2397         /* Check for zero MAC address */
2398         HWRM_PREP(req, FUNC_QCFG);
2399         req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
2400         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2401         if (rc) {
2402                 RTE_LOG(ERR, PMD, "hwrm_func_qcfg failed rc:%d\n", rc);
2403                 return -1;
2404         } else if (resp->error_code) {
2405                 rc = rte_le_to_cpu_16(resp->error_code);
2406                 RTE_LOG(ERR, PMD, "hwrm_func_qcfg error %d\n", rc);
2407                 return -1;
2408         }
2409         rc = rte_le_to_cpu_16(resp->vlan);
2410
2411         HWRM_UNLOCK();
2412
2413         return rc;
2414 }
2415
2416 static int update_pf_resource_max(struct bnxt *bp)
2417 {
2418         struct hwrm_func_qcfg_input req = {0};
2419         struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
2420         int rc;
2421
2422         /* And copy the allocated numbers into the pf struct */
2423         HWRM_PREP(req, FUNC_QCFG);
2424         req.fid = rte_cpu_to_le_16(0xffff);
2425         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2426         HWRM_CHECK_RESULT();
2427
2428         /* Only TX ring value reflects actual allocation? TODO */
2429         bp->max_tx_rings = rte_le_to_cpu_16(resp->alloc_tx_rings);
2430         bp->pf.evb_mode = resp->evb_mode;
2431
2432         HWRM_UNLOCK();
2433
2434         return rc;
2435 }
2436
2437 int bnxt_hwrm_allocate_pf_only(struct bnxt *bp)
2438 {
2439         int rc;
2440
2441         if (!BNXT_PF(bp)) {
2442                 RTE_LOG(ERR, PMD, "Attempt to allcoate VFs on a VF!\n");
2443                 return -1;
2444         }
2445
2446         rc = bnxt_hwrm_func_qcaps(bp);
2447         if (rc)
2448                 return rc;
2449
2450         bp->pf.func_cfg_flags &=
2451                 ~(HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_ENABLE |
2452                   HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_DISABLE);
2453         bp->pf.func_cfg_flags |=
2454                 HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_DISABLE;
2455         rc = bnxt_hwrm_pf_func_cfg(bp, bp->max_tx_rings);
2456         return rc;
2457 }
2458
2459 int bnxt_hwrm_allocate_vfs(struct bnxt *bp, int num_vfs)
2460 {
2461         struct hwrm_func_cfg_input req = {0};
2462         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2463         int i;
2464         size_t sz;
2465         int rc = 0;
2466         size_t req_buf_sz;
2467
2468         if (!BNXT_PF(bp)) {
2469                 RTE_LOG(ERR, PMD, "Attempt to allcoate VFs on a VF!\n");
2470                 return -1;
2471         }
2472
2473         rc = bnxt_hwrm_func_qcaps(bp);
2474
2475         if (rc)
2476                 return rc;
2477
2478         bp->pf.active_vfs = num_vfs;
2479
2480         /*
2481          * First, configure the PF to only use one TX ring.  This ensures that
2482          * there are enough rings for all VFs.
2483          *
2484          * If we don't do this, when we call func_alloc() later, we will lock
2485          * extra rings to the PF that won't be available during func_cfg() of
2486          * the VFs.
2487          *
2488          * This has been fixed with firmware versions above 20.6.54
2489          */
2490         bp->pf.func_cfg_flags &=
2491                 ~(HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_ENABLE |
2492                   HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_DISABLE);
2493         bp->pf.func_cfg_flags |=
2494                 HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_ENABLE;
2495         rc = bnxt_hwrm_pf_func_cfg(bp, 1);
2496         if (rc)
2497                 return rc;
2498
2499         /*
2500          * Now, create and register a buffer to hold forwarded VF requests
2501          */
2502         req_buf_sz = num_vfs * HWRM_MAX_REQ_LEN;
2503         bp->pf.vf_req_buf = rte_malloc("bnxt_vf_fwd", req_buf_sz,
2504                 page_roundup(num_vfs * HWRM_MAX_REQ_LEN));
2505         if (bp->pf.vf_req_buf == NULL) {
2506                 rc = -ENOMEM;
2507                 goto error_free;
2508         }
2509         for (sz = 0; sz < req_buf_sz; sz += getpagesize())
2510                 rte_mem_lock_page(((char *)bp->pf.vf_req_buf) + sz);
2511         for (i = 0; i < num_vfs; i++)
2512                 bp->pf.vf_info[i].req_buf = ((char *)bp->pf.vf_req_buf) +
2513                                         (i * HWRM_MAX_REQ_LEN);
2514
2515         rc = bnxt_hwrm_func_buf_rgtr(bp);
2516         if (rc)
2517                 goto error_free;
2518
2519         populate_vf_func_cfg_req(bp, &req, num_vfs);
2520
2521         bp->pf.active_vfs = 0;
2522         for (i = 0; i < num_vfs; i++) {
2523                 add_random_mac_if_needed(bp, &req, i);
2524
2525                 HWRM_PREP(req, FUNC_CFG);
2526                 req.flags = rte_cpu_to_le_32(bp->pf.vf_info[i].func_cfg_flags);
2527                 req.fid = rte_cpu_to_le_16(bp->pf.vf_info[i].fid);
2528                 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2529
2530                 /* Clear enable flag for next pass */
2531                 req.enables &= ~rte_cpu_to_le_32(
2532                                 HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
2533
2534                 if (rc || resp->error_code) {
2535                         RTE_LOG(ERR, PMD,
2536                                 "Failed to initizlie VF %d\n", i);
2537                         RTE_LOG(ERR, PMD,
2538                                 "Not all VFs available. (%d, %d)\n",
2539                                 rc, resp->error_code);
2540                         HWRM_UNLOCK();
2541                         break;
2542                 }
2543
2544                 HWRM_UNLOCK();
2545
2546                 reserve_resources_from_vf(bp, &req, i);
2547                 bp->pf.active_vfs++;
2548                 bnxt_hwrm_func_clr_stats(bp, bp->pf.vf_info[i].fid);
2549         }
2550
2551         /*
2552          * Now configure the PF to use "the rest" of the resources
2553          * We're using STD_TX_RING_MODE here though which will limit the TX
2554          * rings.  This will allow QoS to function properly.  Not setting this
2555          * will cause PF rings to break bandwidth settings.
2556          */
2557         rc = bnxt_hwrm_pf_func_cfg(bp, bp->max_tx_rings);
2558         if (rc)
2559                 goto error_free;
2560
2561         rc = update_pf_resource_max(bp);
2562         if (rc)
2563                 goto error_free;
2564
2565         return rc;
2566
2567 error_free:
2568         bnxt_hwrm_func_buf_unrgtr(bp);
2569         return rc;
2570 }
2571
2572 int bnxt_hwrm_pf_evb_mode(struct bnxt *bp)
2573 {
2574         struct hwrm_func_cfg_input req = {0};
2575         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2576         int rc;
2577
2578         HWRM_PREP(req, FUNC_CFG);
2579
2580         req.fid = rte_cpu_to_le_16(0xffff);
2581         req.enables = rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_EVB_MODE);
2582         req.evb_mode = bp->pf.evb_mode;
2583
2584         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2585         HWRM_CHECK_RESULT();
2586         HWRM_UNLOCK();
2587
2588         return rc;
2589 }
2590
2591 int bnxt_hwrm_tunnel_dst_port_alloc(struct bnxt *bp, uint16_t port,
2592                                 uint8_t tunnel_type)
2593 {
2594         struct hwrm_tunnel_dst_port_alloc_input req = {0};
2595         struct hwrm_tunnel_dst_port_alloc_output *resp = bp->hwrm_cmd_resp_addr;
2596         int rc = 0;
2597
2598         HWRM_PREP(req, TUNNEL_DST_PORT_ALLOC);
2599         req.tunnel_type = tunnel_type;
2600         req.tunnel_dst_port_val = port;
2601         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2602         HWRM_CHECK_RESULT();
2603
2604         switch (tunnel_type) {
2605         case HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN:
2606                 bp->vxlan_fw_dst_port_id = resp->tunnel_dst_port_id;
2607                 bp->vxlan_port = port;
2608                 break;
2609         case HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_GENEVE:
2610                 bp->geneve_fw_dst_port_id = resp->tunnel_dst_port_id;
2611                 bp->geneve_port = port;
2612                 break;
2613         default:
2614                 break;
2615         }
2616
2617         HWRM_UNLOCK();
2618
2619         return rc;
2620 }
2621
2622 int bnxt_hwrm_tunnel_dst_port_free(struct bnxt *bp, uint16_t port,
2623                                 uint8_t tunnel_type)
2624 {
2625         struct hwrm_tunnel_dst_port_free_input req = {0};
2626         struct hwrm_tunnel_dst_port_free_output *resp = bp->hwrm_cmd_resp_addr;
2627         int rc = 0;
2628
2629         HWRM_PREP(req, TUNNEL_DST_PORT_FREE);
2630
2631         req.tunnel_type = tunnel_type;
2632         req.tunnel_dst_port_id = rte_cpu_to_be_16(port);
2633         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2634
2635         HWRM_CHECK_RESULT();
2636         HWRM_UNLOCK();
2637
2638         return rc;
2639 }
2640
2641 int bnxt_hwrm_func_cfg_vf_set_flags(struct bnxt *bp, uint16_t vf,
2642                                         uint32_t flags)
2643 {
2644         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2645         struct hwrm_func_cfg_input req = {0};
2646         int rc;
2647
2648         HWRM_PREP(req, FUNC_CFG);
2649
2650         req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
2651         req.flags = rte_cpu_to_le_32(flags);
2652         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2653
2654         HWRM_CHECK_RESULT();
2655         HWRM_UNLOCK();
2656
2657         return rc;
2658 }
2659
2660 void vf_vnic_set_rxmask_cb(struct bnxt_vnic_info *vnic, void *flagp)
2661 {
2662         uint32_t *flag = flagp;
2663
2664         vnic->flags = *flag;
2665 }
2666
2667 int bnxt_set_rx_mask_no_vlan(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2668 {
2669         return bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
2670 }
2671
2672 int bnxt_hwrm_func_buf_rgtr(struct bnxt *bp)
2673 {
2674         int rc = 0;
2675         struct hwrm_func_buf_rgtr_input req = {.req_type = 0 };
2676         struct hwrm_func_buf_rgtr_output *resp = bp->hwrm_cmd_resp_addr;
2677
2678         HWRM_PREP(req, FUNC_BUF_RGTR);
2679
2680         req.req_buf_num_pages = rte_cpu_to_le_16(1);
2681         req.req_buf_page_size = rte_cpu_to_le_16(
2682                          page_getenum(bp->pf.active_vfs * HWRM_MAX_REQ_LEN));
2683         req.req_buf_len = rte_cpu_to_le_16(HWRM_MAX_REQ_LEN);
2684         req.req_buf_page_addr[0] =
2685                 rte_cpu_to_le_64(rte_mem_virt2iova(bp->pf.vf_req_buf));
2686         if (req.req_buf_page_addr[0] == 0) {
2687                 RTE_LOG(ERR, PMD,
2688                         "unable to map buffer address to physical memory\n");
2689                 return -ENOMEM;
2690         }
2691
2692         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2693
2694         HWRM_CHECK_RESULT();
2695         HWRM_UNLOCK();
2696
2697         return rc;
2698 }
2699
2700 int bnxt_hwrm_func_buf_unrgtr(struct bnxt *bp)
2701 {
2702         int rc = 0;
2703         struct hwrm_func_buf_unrgtr_input req = {.req_type = 0 };
2704         struct hwrm_func_buf_unrgtr_output *resp = bp->hwrm_cmd_resp_addr;
2705
2706         HWRM_PREP(req, FUNC_BUF_UNRGTR);
2707
2708         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2709
2710         HWRM_CHECK_RESULT();
2711         HWRM_UNLOCK();
2712
2713         return rc;
2714 }
2715
2716 int bnxt_hwrm_func_cfg_def_cp(struct bnxt *bp)
2717 {
2718         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2719         struct hwrm_func_cfg_input req = {0};
2720         int rc;
2721
2722         HWRM_PREP(req, FUNC_CFG);
2723
2724         req.fid = rte_cpu_to_le_16(0xffff);
2725         req.flags = rte_cpu_to_le_32(bp->pf.func_cfg_flags);
2726         req.enables = rte_cpu_to_le_32(
2727                         HWRM_FUNC_CFG_INPUT_ENABLES_ASYNC_EVENT_CR);
2728         req.async_event_cr = rte_cpu_to_le_16(
2729                         bp->def_cp_ring->cp_ring_struct->fw_ring_id);
2730         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2731
2732         HWRM_CHECK_RESULT();
2733         HWRM_UNLOCK();
2734
2735         return rc;
2736 }
2737
2738 int bnxt_hwrm_vf_func_cfg_def_cp(struct bnxt *bp)
2739 {
2740         struct hwrm_func_vf_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2741         struct hwrm_func_vf_cfg_input req = {0};
2742         int rc;
2743
2744         HWRM_PREP(req, FUNC_VF_CFG);
2745
2746         req.enables = rte_cpu_to_le_32(
2747                         HWRM_FUNC_CFG_INPUT_ENABLES_ASYNC_EVENT_CR);
2748         req.async_event_cr = rte_cpu_to_le_16(
2749                         bp->def_cp_ring->cp_ring_struct->fw_ring_id);
2750         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2751
2752         HWRM_CHECK_RESULT();
2753         HWRM_UNLOCK();
2754
2755         return rc;
2756 }
2757
2758 int bnxt_hwrm_set_default_vlan(struct bnxt *bp, int vf, uint8_t is_vf)
2759 {
2760         struct hwrm_func_cfg_input req = {0};
2761         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2762         uint16_t dflt_vlan, fid;
2763         uint32_t func_cfg_flags;
2764         int rc = 0;
2765
2766         HWRM_PREP(req, FUNC_CFG);
2767
2768         if (is_vf) {
2769                 dflt_vlan = bp->pf.vf_info[vf].dflt_vlan;
2770                 fid = bp->pf.vf_info[vf].fid;
2771                 func_cfg_flags = bp->pf.vf_info[vf].func_cfg_flags;
2772         } else {
2773                 fid = rte_cpu_to_le_16(0xffff);
2774                 func_cfg_flags = bp->pf.func_cfg_flags;
2775                 dflt_vlan = bp->vlan;
2776         }
2777
2778         req.flags = rte_cpu_to_le_32(func_cfg_flags);
2779         req.fid = rte_cpu_to_le_16(fid);
2780         req.enables |= rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_VLAN);
2781         req.dflt_vlan = rte_cpu_to_le_16(dflt_vlan);
2782
2783         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2784
2785         HWRM_CHECK_RESULT();
2786         HWRM_UNLOCK();
2787
2788         return rc;
2789 }
2790
2791 int bnxt_hwrm_func_bw_cfg(struct bnxt *bp, uint16_t vf,
2792                         uint16_t max_bw, uint16_t enables)
2793 {
2794         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2795         struct hwrm_func_cfg_input req = {0};
2796         int rc;
2797
2798         HWRM_PREP(req, FUNC_CFG);
2799
2800         req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
2801         req.enables |= rte_cpu_to_le_32(enables);
2802         req.flags = rte_cpu_to_le_32(bp->pf.vf_info[vf].func_cfg_flags);
2803         req.max_bw = rte_cpu_to_le_32(max_bw);
2804         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2805
2806         HWRM_CHECK_RESULT();
2807         HWRM_UNLOCK();
2808
2809         return rc;
2810 }
2811
2812 int bnxt_hwrm_set_vf_vlan(struct bnxt *bp, int vf)
2813 {
2814         struct hwrm_func_cfg_input req = {0};
2815         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2816         int rc = 0;
2817
2818         HWRM_PREP(req, FUNC_CFG);
2819
2820         req.flags = rte_cpu_to_le_32(bp->pf.vf_info[vf].func_cfg_flags);
2821         req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
2822         req.enables |= rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_VLAN);
2823         req.dflt_vlan = rte_cpu_to_le_16(bp->pf.vf_info[vf].dflt_vlan);
2824
2825         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2826
2827         HWRM_CHECK_RESULT();
2828         HWRM_UNLOCK();
2829
2830         return rc;
2831 }
2832
2833 int bnxt_hwrm_reject_fwd_resp(struct bnxt *bp, uint16_t target_id,
2834                               void *encaped, size_t ec_size)
2835 {
2836         int rc = 0;
2837         struct hwrm_reject_fwd_resp_input req = {.req_type = 0};
2838         struct hwrm_reject_fwd_resp_output *resp = bp->hwrm_cmd_resp_addr;
2839
2840         if (ec_size > sizeof(req.encap_request))
2841                 return -1;
2842
2843         HWRM_PREP(req, REJECT_FWD_RESP);
2844
2845         req.encap_resp_target_id = rte_cpu_to_le_16(target_id);
2846         memcpy(req.encap_request, encaped, ec_size);
2847
2848         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2849
2850         HWRM_CHECK_RESULT();
2851         HWRM_UNLOCK();
2852
2853         return rc;
2854 }
2855
2856 int bnxt_hwrm_func_qcfg_vf_default_mac(struct bnxt *bp, uint16_t vf,
2857                                        struct ether_addr *mac)
2858 {
2859         struct hwrm_func_qcfg_input req = {0};
2860         struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
2861         int rc;
2862
2863         HWRM_PREP(req, FUNC_QCFG);
2864
2865         req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
2866         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2867
2868         HWRM_CHECK_RESULT();
2869
2870         memcpy(mac->addr_bytes, resp->mac_address, ETHER_ADDR_LEN);
2871
2872         HWRM_UNLOCK();
2873
2874         return rc;
2875 }
2876
2877 int bnxt_hwrm_exec_fwd_resp(struct bnxt *bp, uint16_t target_id,
2878                             void *encaped, size_t ec_size)
2879 {
2880         int rc = 0;
2881         struct hwrm_exec_fwd_resp_input req = {.req_type = 0};
2882         struct hwrm_exec_fwd_resp_output *resp = bp->hwrm_cmd_resp_addr;
2883
2884         if (ec_size > sizeof(req.encap_request))
2885                 return -1;
2886
2887         HWRM_PREP(req, EXEC_FWD_RESP);
2888
2889         req.encap_resp_target_id = rte_cpu_to_le_16(target_id);
2890         memcpy(req.encap_request, encaped, ec_size);
2891
2892         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2893
2894         HWRM_CHECK_RESULT();
2895         HWRM_UNLOCK();
2896
2897         return rc;
2898 }
2899
2900 int bnxt_hwrm_ctx_qstats(struct bnxt *bp, uint32_t cid, int idx,
2901                          struct rte_eth_stats *stats, uint8_t rx)
2902 {
2903         int rc = 0;
2904         struct hwrm_stat_ctx_query_input req = {.req_type = 0};
2905         struct hwrm_stat_ctx_query_output *resp = bp->hwrm_cmd_resp_addr;
2906
2907         HWRM_PREP(req, STAT_CTX_QUERY);
2908
2909         req.stat_ctx_id = rte_cpu_to_le_32(cid);
2910
2911         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2912
2913         HWRM_CHECK_RESULT();
2914
2915         if (rx) {
2916                 stats->q_ipackets[idx] = rte_le_to_cpu_64(resp->rx_ucast_pkts);
2917                 stats->q_ipackets[idx] += rte_le_to_cpu_64(resp->rx_mcast_pkts);
2918                 stats->q_ipackets[idx] += rte_le_to_cpu_64(resp->rx_bcast_pkts);
2919                 stats->q_ibytes[idx] = rte_le_to_cpu_64(resp->rx_ucast_bytes);
2920                 stats->q_ibytes[idx] += rte_le_to_cpu_64(resp->rx_mcast_bytes);
2921                 stats->q_ibytes[idx] += rte_le_to_cpu_64(resp->rx_bcast_bytes);
2922                 stats->q_errors[idx] = rte_le_to_cpu_64(resp->rx_err_pkts);
2923                 stats->q_errors[idx] += rte_le_to_cpu_64(resp->rx_drop_pkts);
2924         } else {
2925                 stats->q_opackets[idx] = rte_le_to_cpu_64(resp->tx_ucast_pkts);
2926                 stats->q_opackets[idx] += rte_le_to_cpu_64(resp->tx_mcast_pkts);
2927                 stats->q_opackets[idx] += rte_le_to_cpu_64(resp->tx_bcast_pkts);
2928                 stats->q_obytes[idx] = rte_le_to_cpu_64(resp->tx_ucast_bytes);
2929                 stats->q_obytes[idx] += rte_le_to_cpu_64(resp->tx_mcast_bytes);
2930                 stats->q_obytes[idx] += rte_le_to_cpu_64(resp->tx_bcast_bytes);
2931                 stats->q_errors[idx] += rte_le_to_cpu_64(resp->tx_err_pkts);
2932         }
2933
2934
2935         HWRM_UNLOCK();
2936
2937         return rc;
2938 }
2939
2940 int bnxt_hwrm_port_qstats(struct bnxt *bp)
2941 {
2942         struct hwrm_port_qstats_input req = {0};
2943         struct hwrm_port_qstats_output *resp = bp->hwrm_cmd_resp_addr;
2944         struct bnxt_pf_info *pf = &bp->pf;
2945         int rc;
2946
2947         if (!(bp->flags & BNXT_FLAG_PORT_STATS))
2948                 return 0;
2949
2950         HWRM_PREP(req, PORT_QSTATS);
2951
2952         req.port_id = rte_cpu_to_le_16(pf->port_id);
2953         req.tx_stat_host_addr = rte_cpu_to_le_64(bp->hw_tx_port_stats_map);
2954         req.rx_stat_host_addr = rte_cpu_to_le_64(bp->hw_rx_port_stats_map);
2955         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2956
2957         HWRM_CHECK_RESULT();
2958         HWRM_UNLOCK();
2959
2960         return rc;
2961 }
2962
2963 int bnxt_hwrm_port_clr_stats(struct bnxt *bp)
2964 {
2965         struct hwrm_port_clr_stats_input req = {0};
2966         struct hwrm_port_clr_stats_output *resp = bp->hwrm_cmd_resp_addr;
2967         struct bnxt_pf_info *pf = &bp->pf;
2968         int rc;
2969
2970         if (!(bp->flags & BNXT_FLAG_PORT_STATS))
2971                 return 0;
2972
2973         HWRM_PREP(req, PORT_CLR_STATS);
2974
2975         req.port_id = rte_cpu_to_le_16(pf->port_id);
2976         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2977
2978         HWRM_CHECK_RESULT();
2979         HWRM_UNLOCK();
2980
2981         return rc;
2982 }
2983
2984 int bnxt_hwrm_port_led_qcaps(struct bnxt *bp)
2985 {
2986         struct hwrm_port_led_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
2987         struct hwrm_port_led_qcaps_input req = {0};
2988         int rc;
2989
2990         if (BNXT_VF(bp))
2991                 return 0;
2992
2993         HWRM_PREP(req, PORT_LED_QCAPS);
2994         req.port_id = bp->pf.port_id;
2995         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
2996
2997         HWRM_CHECK_RESULT();
2998
2999         if (resp->num_leds > 0 && resp->num_leds < BNXT_MAX_LED) {
3000                 unsigned int i;
3001
3002                 bp->num_leds = resp->num_leds;
3003                 memcpy(bp->leds, &resp->led0_id,
3004                         sizeof(bp->leds[0]) * bp->num_leds);
3005                 for (i = 0; i < bp->num_leds; i++) {
3006                         struct bnxt_led_info *led = &bp->leds[i];
3007
3008                         uint16_t caps = led->led_state_caps;
3009
3010                         if (!led->led_group_id ||
3011                                 !BNXT_LED_ALT_BLINK_CAP(caps)) {
3012                                 bp->num_leds = 0;
3013                                 break;
3014                         }
3015                 }
3016         }
3017
3018         HWRM_UNLOCK();
3019
3020         return rc;
3021 }
3022
3023 int bnxt_hwrm_port_led_cfg(struct bnxt *bp, bool led_on)
3024 {
3025         struct hwrm_port_led_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3026         struct hwrm_port_led_cfg_input req = {0};
3027         struct bnxt_led_cfg *led_cfg;
3028         uint8_t led_state = HWRM_PORT_LED_QCFG_OUTPUT_LED0_STATE_DEFAULT;
3029         uint16_t duration = 0;
3030         int rc, i;
3031
3032         if (!bp->num_leds || BNXT_VF(bp))
3033                 return -EOPNOTSUPP;
3034
3035         HWRM_PREP(req, PORT_LED_CFG);
3036
3037         if (led_on) {
3038                 led_state = HWRM_PORT_LED_CFG_INPUT_LED0_STATE_BLINKALT;
3039                 duration = rte_cpu_to_le_16(500);
3040         }
3041         req.port_id = bp->pf.port_id;
3042         req.num_leds = bp->num_leds;
3043         led_cfg = (struct bnxt_led_cfg *)&req.led0_id;
3044         for (i = 0; i < bp->num_leds; i++, led_cfg++) {
3045                 req.enables |= BNXT_LED_DFLT_ENABLES(i);
3046                 led_cfg->led_id = bp->leds[i].led_id;
3047                 led_cfg->led_state = led_state;
3048                 led_cfg->led_blink_on = duration;
3049                 led_cfg->led_blink_off = duration;
3050                 led_cfg->led_group_id = bp->leds[i].led_group_id;
3051         }
3052
3053         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
3054
3055         HWRM_CHECK_RESULT();
3056         HWRM_UNLOCK();
3057
3058         return rc;
3059 }
3060
3061 int bnxt_hwrm_nvm_get_dir_info(struct bnxt *bp, uint32_t *entries,
3062                                uint32_t *length)
3063 {
3064         int rc;
3065         struct hwrm_nvm_get_dir_info_input req = {0};
3066         struct hwrm_nvm_get_dir_info_output *resp = bp->hwrm_cmd_resp_addr;
3067
3068         HWRM_PREP(req, NVM_GET_DIR_INFO);
3069
3070         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
3071
3072         HWRM_CHECK_RESULT();
3073         HWRM_UNLOCK();
3074
3075         if (!rc) {
3076                 *entries = rte_le_to_cpu_32(resp->entries);
3077                 *length = rte_le_to_cpu_32(resp->entry_length);
3078         }
3079         return rc;
3080 }
3081
3082 int bnxt_get_nvram_directory(struct bnxt *bp, uint32_t len, uint8_t *data)
3083 {
3084         int rc;
3085         uint32_t dir_entries;
3086         uint32_t entry_length;
3087         uint8_t *buf;
3088         size_t buflen;
3089         rte_iova_t dma_handle;
3090         struct hwrm_nvm_get_dir_entries_input req = {0};
3091         struct hwrm_nvm_get_dir_entries_output *resp = bp->hwrm_cmd_resp_addr;
3092
3093         rc = bnxt_hwrm_nvm_get_dir_info(bp, &dir_entries, &entry_length);
3094         if (rc != 0)
3095                 return rc;
3096
3097         *data++ = dir_entries;
3098         *data++ = entry_length;
3099         len -= 2;
3100         memset(data, 0xff, len);
3101
3102         buflen = dir_entries * entry_length;
3103         buf = rte_malloc("nvm_dir", buflen, 0);
3104         rte_mem_lock_page(buf);
3105         if (buf == NULL)
3106                 return -ENOMEM;
3107         dma_handle = rte_mem_virt2iova(buf);
3108         if (dma_handle == 0) {
3109                 RTE_LOG(ERR, PMD,
3110                         "unable to map response address to physical memory\n");
3111                 return -ENOMEM;
3112         }
3113         HWRM_PREP(req, NVM_GET_DIR_ENTRIES);
3114         req.host_dest_addr = rte_cpu_to_le_64(dma_handle);
3115         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
3116
3117         if (rc == 0)
3118                 memcpy(data, buf, len > buflen ? buflen : len);
3119
3120         rte_free(buf);
3121         HWRM_CHECK_RESULT();
3122         HWRM_UNLOCK();
3123
3124         return rc;
3125 }
3126
3127 int bnxt_hwrm_get_nvram_item(struct bnxt *bp, uint32_t index,
3128                              uint32_t offset, uint32_t length,
3129                              uint8_t *data)
3130 {
3131         int rc;
3132         uint8_t *buf;
3133         rte_iova_t dma_handle;
3134         struct hwrm_nvm_read_input req = {0};
3135         struct hwrm_nvm_read_output *resp = bp->hwrm_cmd_resp_addr;
3136
3137         buf = rte_malloc("nvm_item", length, 0);
3138         rte_mem_lock_page(buf);
3139         if (!buf)
3140                 return -ENOMEM;
3141
3142         dma_handle = rte_mem_virt2iova(buf);
3143         if (dma_handle == 0) {
3144                 RTE_LOG(ERR, PMD,
3145                         "unable to map response address to physical memory\n");
3146                 return -ENOMEM;
3147         }
3148         HWRM_PREP(req, NVM_READ);
3149         req.host_dest_addr = rte_cpu_to_le_64(dma_handle);
3150         req.dir_idx = rte_cpu_to_le_16(index);
3151         req.offset = rte_cpu_to_le_32(offset);
3152         req.len = rte_cpu_to_le_32(length);
3153         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
3154         if (rc == 0)
3155                 memcpy(data, buf, length);
3156
3157         rte_free(buf);
3158         HWRM_CHECK_RESULT();
3159         HWRM_UNLOCK();
3160
3161         return rc;
3162 }
3163
3164 int bnxt_hwrm_erase_nvram_directory(struct bnxt *bp, uint8_t index)
3165 {
3166         int rc;
3167         struct hwrm_nvm_erase_dir_entry_input req = {0};
3168         struct hwrm_nvm_erase_dir_entry_output *resp = bp->hwrm_cmd_resp_addr;
3169
3170         HWRM_PREP(req, NVM_ERASE_DIR_ENTRY);
3171         req.dir_idx = rte_cpu_to_le_16(index);
3172         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
3173         HWRM_CHECK_RESULT();
3174         HWRM_UNLOCK();
3175
3176         return rc;
3177 }
3178
3179
3180 int bnxt_hwrm_flash_nvram(struct bnxt *bp, uint16_t dir_type,
3181                           uint16_t dir_ordinal, uint16_t dir_ext,
3182                           uint16_t dir_attr, const uint8_t *data,
3183                           size_t data_len)
3184 {
3185         int rc;
3186         struct hwrm_nvm_write_input req = {0};
3187         struct hwrm_nvm_write_output *resp = bp->hwrm_cmd_resp_addr;
3188         rte_iova_t dma_handle;
3189         uint8_t *buf;
3190
3191         buf = rte_malloc("nvm_write", data_len, 0);
3192         rte_mem_lock_page(buf);
3193         if (!buf)
3194                 return -ENOMEM;
3195
3196         dma_handle = rte_mem_virt2iova(buf);
3197         if (dma_handle == 0) {
3198                 RTE_LOG(ERR, PMD,
3199                         "unable to map response address to physical memory\n");
3200                 return -ENOMEM;
3201         }
3202         memcpy(buf, data, data_len);
3203
3204         HWRM_PREP(req, NVM_WRITE);
3205
3206         req.dir_type = rte_cpu_to_le_16(dir_type);
3207         req.dir_ordinal = rte_cpu_to_le_16(dir_ordinal);
3208         req.dir_ext = rte_cpu_to_le_16(dir_ext);
3209         req.dir_attr = rte_cpu_to_le_16(dir_attr);
3210         req.dir_data_length = rte_cpu_to_le_32(data_len);
3211         req.host_src_addr = rte_cpu_to_le_64(dma_handle);
3212
3213         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
3214
3215         rte_free(buf);
3216         HWRM_CHECK_RESULT();
3217         HWRM_UNLOCK();
3218
3219         return rc;
3220 }
3221
3222 static void
3223 bnxt_vnic_count(struct bnxt_vnic_info *vnic __rte_unused, void *cbdata)
3224 {
3225         uint32_t *count = cbdata;
3226
3227         *count = *count + 1;
3228 }
3229
3230 static int bnxt_vnic_count_hwrm_stub(struct bnxt *bp __rte_unused,
3231                                      struct bnxt_vnic_info *vnic __rte_unused)
3232 {
3233         return 0;
3234 }
3235
3236 int bnxt_vf_vnic_count(struct bnxt *bp, uint16_t vf)
3237 {
3238         uint32_t count = 0;
3239
3240         bnxt_hwrm_func_vf_vnic_query_and_config(bp, vf, bnxt_vnic_count,
3241             &count, bnxt_vnic_count_hwrm_stub);
3242
3243         return count;
3244 }
3245
3246 static int bnxt_hwrm_func_vf_vnic_query(struct bnxt *bp, uint16_t vf,
3247                                         uint16_t *vnic_ids)
3248 {
3249         struct hwrm_func_vf_vnic_ids_query_input req = {0};
3250         struct hwrm_func_vf_vnic_ids_query_output *resp =
3251                                                 bp->hwrm_cmd_resp_addr;
3252         int rc;
3253
3254         /* First query all VNIC ids */
3255         HWRM_PREP(req, FUNC_VF_VNIC_IDS_QUERY);
3256
3257         req.vf_id = rte_cpu_to_le_16(bp->pf.first_vf_id + vf);
3258         req.max_vnic_id_cnt = rte_cpu_to_le_32(bp->pf.total_vnics);
3259         req.vnic_id_tbl_addr = rte_cpu_to_le_64(rte_mem_virt2iova(vnic_ids));
3260
3261         if (req.vnic_id_tbl_addr == 0) {
3262                 HWRM_UNLOCK();
3263                 RTE_LOG(ERR, PMD,
3264                 "unable to map VNIC ID table address to physical memory\n");
3265                 return -ENOMEM;
3266         }
3267         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
3268         if (rc) {
3269                 HWRM_UNLOCK();
3270                 RTE_LOG(ERR, PMD, "hwrm_func_vf_vnic_query failed rc:%d\n", rc);
3271                 return -1;
3272         } else if (resp->error_code) {
3273                 rc = rte_le_to_cpu_16(resp->error_code);
3274                 HWRM_UNLOCK();
3275                 RTE_LOG(ERR, PMD, "hwrm_func_vf_vnic_query error %d\n", rc);
3276                 return -1;
3277         }
3278         rc = rte_le_to_cpu_32(resp->vnic_id_cnt);
3279
3280         HWRM_UNLOCK();
3281
3282         return rc;
3283 }
3284
3285 /*
3286  * This function queries the VNIC IDs  for a specified VF. It then calls
3287  * the vnic_cb to update the necessary field in vnic_info with cbdata.
3288  * Then it calls the hwrm_cb function to program this new vnic configuration.
3289  */
3290 int bnxt_hwrm_func_vf_vnic_query_and_config(struct bnxt *bp, uint16_t vf,
3291         void (*vnic_cb)(struct bnxt_vnic_info *, void *), void *cbdata,
3292         int (*hwrm_cb)(struct bnxt *bp, struct bnxt_vnic_info *vnic))
3293 {
3294         struct bnxt_vnic_info vnic;
3295         int rc = 0;
3296         int i, num_vnic_ids;
3297         uint16_t *vnic_ids;
3298         size_t vnic_id_sz;
3299         size_t sz;
3300
3301         /* First query all VNIC ids */
3302         vnic_id_sz = bp->pf.total_vnics * sizeof(*vnic_ids);
3303         vnic_ids = rte_malloc("bnxt_hwrm_vf_vnic_ids_query", vnic_id_sz,
3304                         RTE_CACHE_LINE_SIZE);
3305         if (vnic_ids == NULL) {
3306                 rc = -ENOMEM;
3307                 return rc;
3308         }
3309         for (sz = 0; sz < vnic_id_sz; sz += getpagesize())
3310                 rte_mem_lock_page(((char *)vnic_ids) + sz);
3311
3312         num_vnic_ids = bnxt_hwrm_func_vf_vnic_query(bp, vf, vnic_ids);
3313
3314         if (num_vnic_ids < 0)
3315                 return num_vnic_ids;
3316
3317         /* Retrieve VNIC, update bd_stall then update */
3318
3319         for (i = 0; i < num_vnic_ids; i++) {
3320                 memset(&vnic, 0, sizeof(struct bnxt_vnic_info));
3321                 vnic.fw_vnic_id = rte_le_to_cpu_16(vnic_ids[i]);
3322                 rc = bnxt_hwrm_vnic_qcfg(bp, &vnic, bp->pf.first_vf_id + vf);
3323                 if (rc)
3324                         break;
3325                 if (vnic.mru <= 4)      /* Indicates unallocated */
3326                         continue;
3327
3328                 vnic_cb(&vnic, cbdata);
3329
3330                 rc = hwrm_cb(bp, &vnic);
3331                 if (rc)
3332                         break;
3333         }
3334
3335         rte_free(vnic_ids);
3336
3337         return rc;
3338 }
3339
3340 int bnxt_hwrm_func_cfg_vf_set_vlan_anti_spoof(struct bnxt *bp, uint16_t vf,
3341                                               bool on)
3342 {
3343         struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3344         struct hwrm_func_cfg_input req = {0};
3345         int rc;
3346
3347         HWRM_PREP(req, FUNC_CFG);
3348
3349         req.fid = rte_cpu_to_le_16(bp->pf.vf_info[vf].fid);
3350         req.enables |= rte_cpu_to_le_32(
3351                         HWRM_FUNC_CFG_INPUT_ENABLES_VLAN_ANTISPOOF_MODE);
3352         req.vlan_antispoof_mode = on ?
3353                 HWRM_FUNC_CFG_INPUT_VLAN_ANTISPOOF_MODE_VALIDATE_VLAN :
3354                 HWRM_FUNC_CFG_INPUT_VLAN_ANTISPOOF_MODE_NOCHECK;
3355         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
3356
3357         HWRM_CHECK_RESULT();
3358         HWRM_UNLOCK();
3359
3360         return rc;
3361 }
3362
3363 int bnxt_hwrm_func_qcfg_vf_dflt_vnic_id(struct bnxt *bp, int vf)
3364 {
3365         struct bnxt_vnic_info vnic;
3366         uint16_t *vnic_ids;
3367         size_t vnic_id_sz;
3368         int num_vnic_ids, i;
3369         size_t sz;
3370         int rc;
3371
3372         vnic_id_sz = bp->pf.total_vnics * sizeof(*vnic_ids);
3373         vnic_ids = rte_malloc("bnxt_hwrm_vf_vnic_ids_query", vnic_id_sz,
3374                         RTE_CACHE_LINE_SIZE);
3375         if (vnic_ids == NULL) {
3376                 rc = -ENOMEM;
3377                 return rc;
3378         }
3379
3380         for (sz = 0; sz < vnic_id_sz; sz += getpagesize())
3381                 rte_mem_lock_page(((char *)vnic_ids) + sz);
3382
3383         rc = bnxt_hwrm_func_vf_vnic_query(bp, vf, vnic_ids);
3384         if (rc <= 0)
3385                 goto exit;
3386         num_vnic_ids = rc;
3387
3388         /*
3389          * Loop through to find the default VNIC ID.
3390          * TODO: The easier way would be to obtain the resp->dflt_vnic_id
3391          * by sending the hwrm_func_qcfg command to the firmware.
3392          */
3393         for (i = 0; i < num_vnic_ids; i++) {
3394                 memset(&vnic, 0, sizeof(struct bnxt_vnic_info));
3395                 vnic.fw_vnic_id = rte_le_to_cpu_16(vnic_ids[i]);
3396                 rc = bnxt_hwrm_vnic_qcfg(bp, &vnic,
3397                                         bp->pf.first_vf_id + vf);
3398                 if (rc)
3399                         goto exit;
3400                 if (vnic.func_default) {
3401                         rte_free(vnic_ids);
3402                         return vnic.fw_vnic_id;
3403                 }
3404         }
3405         /* Could not find a default VNIC. */
3406         RTE_LOG(ERR, PMD, "No default VNIC\n");
3407 exit:
3408         rte_free(vnic_ids);
3409         return -1;
3410 }
3411
3412 int bnxt_hwrm_set_em_filter(struct bnxt *bp,
3413                          uint16_t dst_id,
3414                          struct bnxt_filter_info *filter)
3415 {
3416         int rc = 0;
3417         struct hwrm_cfa_em_flow_alloc_input req = {.req_type = 0 };
3418         struct hwrm_cfa_em_flow_alloc_output *resp = bp->hwrm_cmd_resp_addr;
3419         uint32_t enables = 0;
3420
3421         if (filter->fw_em_filter_id != UINT64_MAX)
3422                 bnxt_hwrm_clear_em_filter(bp, filter);
3423
3424         HWRM_PREP(req, CFA_EM_FLOW_ALLOC);
3425
3426         req.flags = rte_cpu_to_le_32(filter->flags);
3427
3428         enables = filter->enables |
3429               HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_ID;
3430         req.dst_id = rte_cpu_to_le_16(dst_id);
3431
3432         if (filter->ip_addr_type) {
3433                 req.ip_addr_type = filter->ip_addr_type;
3434                 enables |= HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IPADDR_TYPE;
3435         }
3436         if (enables &
3437             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_L2_FILTER_ID)
3438                 req.l2_filter_id = rte_cpu_to_le_64(filter->fw_l2_filter_id);
3439         if (enables &
3440             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_MACADDR)
3441                 memcpy(req.src_macaddr, filter->src_macaddr,
3442                        ETHER_ADDR_LEN);
3443         if (enables &
3444             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_MACADDR)
3445                 memcpy(req.dst_macaddr, filter->dst_macaddr,
3446                        ETHER_ADDR_LEN);
3447         if (enables &
3448             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_OVLAN_VID)
3449                 req.ovlan_vid = filter->l2_ovlan;
3450         if (enables &
3451             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IVLAN_VID)
3452                 req.ivlan_vid = filter->l2_ivlan;
3453         if (enables &
3454             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_ETHERTYPE)
3455                 req.ethertype = rte_cpu_to_be_16(filter->ethertype);
3456         if (enables &
3457             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IP_PROTOCOL)
3458                 req.ip_protocol = filter->ip_protocol;
3459         if (enables &
3460             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_IPADDR)
3461                 req.src_ipaddr[0] = rte_cpu_to_be_32(filter->src_ipaddr[0]);
3462         if (enables &
3463             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_IPADDR)
3464                 req.dst_ipaddr[0] = rte_cpu_to_be_32(filter->dst_ipaddr[0]);
3465         if (enables &
3466             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_PORT)
3467                 req.src_port = rte_cpu_to_be_16(filter->src_port);
3468         if (enables &
3469             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_PORT)
3470                 req.dst_port = rte_cpu_to_be_16(filter->dst_port);
3471         if (enables &
3472             HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID)
3473                 req.mirror_vnic_id = filter->mirror_vnic_id;
3474
3475         req.enables = rte_cpu_to_le_32(enables);
3476
3477         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
3478
3479         HWRM_CHECK_RESULT();
3480
3481         filter->fw_em_filter_id = rte_le_to_cpu_64(resp->em_filter_id);
3482         HWRM_UNLOCK();
3483
3484         return rc;
3485 }
3486
3487 int bnxt_hwrm_clear_em_filter(struct bnxt *bp, struct bnxt_filter_info *filter)
3488 {
3489         int rc = 0;
3490         struct hwrm_cfa_em_flow_free_input req = {.req_type = 0 };
3491         struct hwrm_cfa_em_flow_free_output *resp = bp->hwrm_cmd_resp_addr;
3492
3493         if (filter->fw_em_filter_id == UINT64_MAX)
3494                 return 0;
3495
3496         RTE_LOG(ERR, PMD, "Clear EM filter\n");
3497         HWRM_PREP(req, CFA_EM_FLOW_FREE);
3498
3499         req.em_filter_id = rte_cpu_to_le_64(filter->fw_em_filter_id);
3500
3501         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
3502
3503         HWRM_CHECK_RESULT();
3504         HWRM_UNLOCK();
3505
3506         filter->fw_em_filter_id = -1;
3507         filter->fw_l2_filter_id = -1;
3508
3509         return 0;
3510 }
3511
3512 int bnxt_hwrm_set_ntuple_filter(struct bnxt *bp,
3513                          uint16_t dst_id,
3514                          struct bnxt_filter_info *filter)
3515 {
3516         int rc = 0;
3517         struct hwrm_cfa_ntuple_filter_alloc_input req = {.req_type = 0 };
3518         struct hwrm_cfa_ntuple_filter_alloc_output *resp =
3519                                                 bp->hwrm_cmd_resp_addr;
3520         uint32_t enables = 0;
3521
3522         if (filter->fw_ntuple_filter_id != UINT64_MAX)
3523                 bnxt_hwrm_clear_ntuple_filter(bp, filter);
3524
3525         HWRM_PREP(req, CFA_NTUPLE_FILTER_ALLOC);
3526
3527         req.flags = rte_cpu_to_le_32(filter->flags);
3528
3529         enables = filter->enables |
3530               HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_ID;
3531         req.dst_id = rte_cpu_to_le_16(dst_id);
3532
3533
3534         if (filter->ip_addr_type) {
3535                 req.ip_addr_type = filter->ip_addr_type;
3536                 enables |=
3537                         HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_IPADDR_TYPE;
3538         }
3539         if (enables &
3540             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID)
3541                 req.l2_filter_id = rte_cpu_to_le_64(filter->fw_l2_filter_id);
3542         if (enables &
3543             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_MACADDR)
3544                 memcpy(req.src_macaddr, filter->src_macaddr,
3545                        ETHER_ADDR_LEN);
3546         //if (enables &
3547             //HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_MACADDR)
3548                 //memcpy(req.dst_macaddr, filter->dst_macaddr,
3549                        //ETHER_ADDR_LEN);
3550         if (enables &
3551             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_ETHERTYPE)
3552                 req.ethertype = rte_cpu_to_be_16(filter->ethertype);
3553         if (enables &
3554             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_IP_PROTOCOL)
3555                 req.ip_protocol = filter->ip_protocol;
3556         if (enables &
3557             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_IPADDR)
3558                 req.src_ipaddr[0] = rte_cpu_to_le_32(filter->src_ipaddr[0]);
3559         if (enables &
3560             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_IPADDR_MASK)
3561                 req.src_ipaddr_mask[0] =
3562                         rte_cpu_to_le_32(filter->src_ipaddr_mask[0]);
3563         if (enables &
3564             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_IPADDR)
3565                 req.dst_ipaddr[0] = rte_cpu_to_le_32(filter->dst_ipaddr[0]);
3566         if (enables &
3567             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_IPADDR_MASK)
3568                 req.dst_ipaddr_mask[0] =
3569                         rte_cpu_to_be_32(filter->dst_ipaddr_mask[0]);
3570         if (enables &
3571             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_PORT)
3572                 req.src_port = rte_cpu_to_le_16(filter->src_port);
3573         if (enables &
3574             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_PORT_MASK)
3575                 req.src_port_mask = rte_cpu_to_le_16(filter->src_port_mask);
3576         if (enables &
3577             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_PORT)
3578                 req.dst_port = rte_cpu_to_le_16(filter->dst_port);
3579         if (enables &
3580             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_PORT_MASK)
3581                 req.dst_port_mask = rte_cpu_to_le_16(filter->dst_port_mask);
3582         if (enables &
3583             HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID)
3584                 req.mirror_vnic_id = filter->mirror_vnic_id;
3585
3586         req.enables = rte_cpu_to_le_32(enables);
3587
3588         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
3589
3590         HWRM_CHECK_RESULT();
3591
3592         filter->fw_ntuple_filter_id = rte_le_to_cpu_64(resp->ntuple_filter_id);
3593         HWRM_UNLOCK();
3594
3595         return rc;
3596 }
3597
3598 int bnxt_hwrm_clear_ntuple_filter(struct bnxt *bp,
3599                                 struct bnxt_filter_info *filter)
3600 {
3601         int rc = 0;
3602         struct hwrm_cfa_ntuple_filter_free_input req = {.req_type = 0 };
3603         struct hwrm_cfa_ntuple_filter_free_output *resp =
3604                                                 bp->hwrm_cmd_resp_addr;
3605
3606         if (filter->fw_ntuple_filter_id == UINT64_MAX)
3607                 return 0;
3608
3609         HWRM_PREP(req, CFA_NTUPLE_FILTER_FREE);
3610
3611         req.ntuple_filter_id = rte_cpu_to_le_64(filter->fw_ntuple_filter_id);
3612
3613         rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
3614
3615         HWRM_CHECK_RESULT();
3616         HWRM_UNLOCK();
3617
3618         filter->fw_ntuple_filter_id = -1;
3619
3620         return 0;
3621 }