drivers/net/cxgbe/base/t4_hw.c

   1 /*-
   2  *   BSD LICENSE
   3  *
   4  *   Copyright(c) 2014-2017 Chelsio Communications.
   5  *   All rights reserved.
   6  *
   7  *   Redistribution and use in source and binary forms, with or without
   8  *   modification, are permitted provided that the following conditions
   9  *   are met:
  10  *
  11  *     * Redistributions of source code must retain the above copyright
  12  *       notice, this list of conditions and the following disclaimer.
  13  *     * Redistributions in binary form must reproduce the above copyright
  14  *       notice, this list of conditions and the following disclaimer in
  15  *       the documentation and/or other materials provided with the
  16  *       distribution.
  17  *     * Neither the name of Chelsio Communications nor the names of its
  18  *       contributors may be used to endorse or promote products derived
  19  *       from this software without specific prior written permission.
  20  *
  21  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 #include <netinet/in.h>
  35
  36 #include <rte_interrupts.h>
  37 #include <rte_log.h>
  38 #include <rte_debug.h>
  39 #include <rte_pci.h>
  40 #include <rte_atomic.h>
  41 #include <rte_branch_prediction.h>
  42 #include <rte_memory.h>
  43 #include <rte_memzone.h>
  44 #include <rte_tailq.h>
  45 #include <rte_eal.h>
  46 #include <rte_alarm.h>
  47 #include <rte_ether.h>
  48 #include <rte_ethdev.h>
  49 #include <rte_malloc.h>
  50 #include <rte_random.h>
  51 #include <rte_dev.h>
  52 #include <rte_byteorder.h>
  53
  54 #include "common.h"
  55 #include "t4_regs.h"
  56 #include "t4_regs_values.h"
  57 #include "t4fw_interface.h"
  58
  59 static void init_link_config(struct link_config *lc, unsigned int pcaps,
  60                              unsigned int acaps);
  61
  62 /**
  63  * t4_read_mtu_tbl - returns the values in the HW path MTU table
  64  * @adap: the adapter
  65  * @mtus: where to store the MTU values
  66  * @mtu_log: where to store the MTU base-2 log (may be %NULL)
  67  *
  68  * Reads the HW path MTU table.
  69  */
  70 void t4_read_mtu_tbl(struct adapter *adap, u16 *mtus, u8 *mtu_log)
  71 {
  72         u32 v;
  73         int i;
  74
  75         for (i = 0; i < NMTUS; ++i) {
  76                 t4_write_reg(adap, A_TP_MTU_TABLE,
  77                              V_MTUINDEX(0xff) | V_MTUVALUE(i));
  78                 v = t4_read_reg(adap, A_TP_MTU_TABLE);
  79                 mtus[i] = G_MTUVALUE(v);
  80                 if (mtu_log)
  81                         mtu_log[i] = G_MTUWIDTH(v);
  82         }
  83 }
  84
  85 /**
  86  * t4_tp_wr_bits_indirect - set/clear bits in an indirect TP register
  87  * @adap: the adapter
  88  * @addr: the indirect TP register address
  89  * @mask: specifies the field within the register to modify
  90  * @val: new value for the field
  91  *
  92  * Sets a field of an indirect TP register to the given value.
  93  */
  94 void t4_tp_wr_bits_indirect(struct adapter *adap, unsigned int addr,
  95                             unsigned int mask, unsigned int val)
  96 {
  97         t4_write_reg(adap, A_TP_PIO_ADDR, addr);
  98         val |= t4_read_reg(adap, A_TP_PIO_DATA) & ~mask;
  99         t4_write_reg(adap, A_TP_PIO_DATA, val);
 100 }
 101
 102 /* The minimum additive increment value for the congestion control table */
 103 #define CC_MIN_INCR 2U
 104
 105 /**
 106  * t4_load_mtus - write the MTU and congestion control HW tables
 107  * @adap: the adapter
 108  * @mtus: the values for the MTU table
 109  * @alpha: the values for the congestion control alpha parameter
 110  * @beta: the values for the congestion control beta parameter
 111  *
 112  * Write the HW MTU table with the supplied MTUs and the high-speed
 113  * congestion control table with the supplied alpha, beta, and MTUs.
 114  * We write the two tables together because the additive increments
 115  * depend on the MTUs.
 116  */
 117 void t4_load_mtus(struct adapter *adap, const unsigned short *mtus,
 118                   const unsigned short *alpha, const unsigned short *beta)
 119 {
 120         static const unsigned int avg_pkts[NCCTRL_WIN] = {
 121                 2, 6, 10, 14, 20, 28, 40, 56, 80, 112, 160, 224, 320, 448, 640,
 122                 896, 1281, 1792, 2560, 3584, 5120, 7168, 10240, 14336, 20480,
 123                 28672, 40960, 57344, 81920, 114688, 163840, 229376
 124         };
 125
 126         unsigned int i, w;
 127
 128         for (i = 0; i < NMTUS; ++i) {
 129                 unsigned int mtu = mtus[i];
 130                 unsigned int log2 = cxgbe_fls(mtu);
 131
 132                 if (!(mtu & ((1 << log2) >> 2)))     /* round */
 133                         log2--;
 134                 t4_write_reg(adap, A_TP_MTU_TABLE, V_MTUINDEX(i) |
 135                              V_MTUWIDTH(log2) | V_MTUVALUE(mtu));
 136
 137                 for (w = 0; w < NCCTRL_WIN; ++w) {
 138                         unsigned int inc;
 139
 140                         inc = max(((mtu - 40) * alpha[w]) / avg_pkts[w],
 141                                   CC_MIN_INCR);
 142
 143                         t4_write_reg(adap, A_TP_CCTRL_TABLE, (i << 21) |
 144                                      (w << 16) | (beta[w] << 13) | inc);
 145                 }
 146         }
 147 }
 148
 149 /**
 150  * t4_wait_op_done_val - wait until an operation is completed
 151  * @adapter: the adapter performing the operation
 152  * @reg: the register to check for completion
 153  * @mask: a single-bit field within @reg that indicates completion
 154  * @polarity: the value of the field when the operation is completed
 155  * @attempts: number of check iterations
 156  * @delay: delay in usecs between iterations
 157  * @valp: where to store the value of the register at completion time
 158  *
 159  * Wait until an operation is completed by checking a bit in a register
 160  * up to @attempts times.  If @valp is not NULL the value of the register
 161  * at the time it indicated completion is stored there.  Returns 0 if the
 162  * operation completes and -EAGAIN otherwise.
 163  */
 164 int t4_wait_op_done_val(struct adapter *adapter, int reg, u32 mask,
 165                         int polarity, int attempts, int delay, u32 *valp)
 166 {
 167         while (1) {
 168                 u32 val = t4_read_reg(adapter, reg);
 169
 170                 if (!!(val & mask) == polarity) {
 171                         if (valp)
 172                                 *valp = val;
 173                         return 0;
 174                 }
 175                 if (--attempts == 0)
 176                         return -EAGAIN;
 177                 if (delay)
 178                         udelay(delay);
 179         }
 180 }
 181
 182 /**
 183  * t4_set_reg_field - set a register field to a value
 184  * @adapter: the adapter to program
 185  * @addr: the register address
 186  * @mask: specifies the portion of the register to modify
 187  * @val: the new value for the register field
 188  *
 189  * Sets a register field specified by the supplied mask to the
 190  * given value.
 191  */
 192 void t4_set_reg_field(struct adapter *adapter, unsigned int addr, u32 mask,
 193                       u32 val)
 194 {
 195         u32 v = t4_read_reg(adapter, addr) & ~mask;
 196
 197         t4_write_reg(adapter, addr, v | val);
 198         (void)t4_read_reg(adapter, addr);      /* flush */
 199 }
 200
 201 /**
 202  * t4_read_indirect - read indirectly addressed registers
 203  * @adap: the adapter
 204  * @addr_reg: register holding the indirect address
 205  * @data_reg: register holding the value of the indirect register
 206  * @vals: where the read register values are stored
 207  * @nregs: how many indirect registers to read
 208  * @start_idx: index of first indirect register to read
 209  *
 210  * Reads registers that are accessed indirectly through an address/data
 211  * register pair.
 212  */
 213 void t4_read_indirect(struct adapter *adap, unsigned int addr_reg,
 214                       unsigned int data_reg, u32 *vals, unsigned int nregs,
 215                       unsigned int start_idx)
 216 {
 217         while (nregs--) {
 218                 t4_write_reg(adap, addr_reg, start_idx);
 219                 *vals++ = t4_read_reg(adap, data_reg);
 220                 start_idx++;
 221         }
 222 }
 223
 224 /**
 225  * t4_write_indirect - write indirectly addressed registers
 226  * @adap: the adapter
 227  * @addr_reg: register holding the indirect addresses
 228  * @data_reg: register holding the value for the indirect registers
 229  * @vals: values to write
 230  * @nregs: how many indirect registers to write
 231  * @start_idx: address of first indirect register to write
 232  *
 233  * Writes a sequential block of registers that are accessed indirectly
 234  * through an address/data register pair.
 235  */
 236 void t4_write_indirect(struct adapter *adap, unsigned int addr_reg,
 237                        unsigned int data_reg, const u32 *vals,
 238                        unsigned int nregs, unsigned int start_idx)
 239 {
 240         while (nregs--) {
 241                 t4_write_reg(adap, addr_reg, start_idx++);
 242                 t4_write_reg(adap, data_reg, *vals++);
 243         }
 244 }
 245
 246 /**
 247  * t4_report_fw_error - report firmware error
 248  * @adap: the adapter
 249  *
 250  * The adapter firmware can indicate error conditions to the host.
 251  * If the firmware has indicated an error, print out the reason for
 252  * the firmware error.
 253  */
 254 static void t4_report_fw_error(struct adapter *adap)
 255 {
 256         static const char * const reason[] = {
 257                 "Crash",                        /* PCIE_FW_EVAL_CRASH */
 258                 "During Device Preparation",    /* PCIE_FW_EVAL_PREP */
 259                 "During Device Configuration",  /* PCIE_FW_EVAL_CONF */
 260                 "During Device Initialization", /* PCIE_FW_EVAL_INIT */
 261                 "Unexpected Event",     /* PCIE_FW_EVAL_UNEXPECTEDEVENT */
 262                 "Insufficient Airflow",         /* PCIE_FW_EVAL_OVERHEAT */
 263                 "Device Shutdown",      /* PCIE_FW_EVAL_DEVICESHUTDOWN */
 264                 "Reserved",                     /* reserved */
 265         };
 266         u32 pcie_fw;
 267
 268         pcie_fw = t4_read_reg(adap, A_PCIE_FW);
 269         if (pcie_fw & F_PCIE_FW_ERR)
 270                 pr_err("%s: Firmware reports adapter error: %s\n",
 271                        __func__, reason[G_PCIE_FW_EVAL(pcie_fw)]);
 272 }
 273
 274 /*
 275  * Get the reply to a mailbox command and store it in @rpl in big-endian order.
 276  */
 277 static void get_mbox_rpl(struct adapter *adap, __be64 *rpl, int nflit,
 278                          u32 mbox_addr)
 279 {
 280         for ( ; nflit; nflit--, mbox_addr += 8)
 281                 *rpl++ = htobe64(t4_read_reg64(adap, mbox_addr));
 282 }
 283
 284 /*
 285  * Handle a FW assertion reported in a mailbox.
 286  */
 287 static void fw_asrt(struct adapter *adap, u32 mbox_addr)
 288 {
 289         struct fw_debug_cmd asrt;
 290
 291         get_mbox_rpl(adap, (__be64 *)&asrt, sizeof(asrt) / 8, mbox_addr);
 292         pr_warn("FW assertion at %.16s:%u, val0 %#x, val1 %#x\n",
 293                 asrt.u.assert.filename_0_7, be32_to_cpu(asrt.u.assert.line),
 294                 be32_to_cpu(asrt.u.assert.x), be32_to_cpu(asrt.u.assert.y));
 295 }
 296
 297 #define X_CIM_PF_NOACCESS 0xeeeeeeee
 298
 299 /*
 300  * If the Host OS Driver needs locking arround accesses to the mailbox, this
 301  * can be turned on via the T4_OS_NEEDS_MBOX_LOCKING CPP define ...
 302  */
 303 /* makes single-statement usage a bit cleaner ... */
 304 #ifdef T4_OS_NEEDS_MBOX_LOCKING
 305 #define T4_OS_MBOX_LOCKING(x) x
 306 #else
 307 #define T4_OS_MBOX_LOCKING(x) do {} while (0)
 308 #endif
 309
 310 /**
 311  * t4_wr_mbox_meat_timeout - send a command to FW through the given mailbox
 312  * @adap: the adapter
 313  * @mbox: index of the mailbox to use
 314  * @cmd: the command to write
 315  * @size: command length in bytes
 316  * @rpl: where to optionally store the reply
 317  * @sleep_ok: if true we may sleep while awaiting command completion
 318  * @timeout: time to wait for command to finish before timing out
 319  *           (negative implies @sleep_ok=false)
 320  *
 321  * Sends the given command to FW through the selected mailbox and waits
 322  * for the FW to execute the command.  If @rpl is not %NULL it is used to
 323  * store the FW's reply to the command.  The command and its optional
 324  * reply are of the same length.  Some FW commands like RESET and
 325  * INITIALIZE can take a considerable amount of time to execute.
 326  * @sleep_ok determines whether we may sleep while awaiting the response.
 327  * If sleeping is allowed we use progressive backoff otherwise we spin.
 328  * Note that passing in a negative @timeout is an alternate mechanism
 329  * for specifying @sleep_ok=false.  This is useful when a higher level
 330  * interface allows for specification of @timeout but not @sleep_ok ...
 331  *
 332  * Returns 0 on success or a negative errno on failure.  A
 333  * failure can happen either because we are not able to execute the
 334  * command or FW executes it but signals an error.  In the latter case
 335  * the return value is the error code indicated by FW (negated).
 336  */
 337 int t4_wr_mbox_meat_timeout(struct adapter *adap, int mbox,
 338                             const void __attribute__((__may_alias__)) *cmd,
 339                             int size, void *rpl, bool sleep_ok, int timeout)
 340 {
 341         /*
 342          * We delay in small increments at first in an effort to maintain
 343          * responsiveness for simple, fast executing commands but then back
 344          * off to larger delays to a maximum retry delay.
 345          */
 346         static const int delay[] = {
 347                 1, 1, 3, 5, 10, 10, 20, 50, 100
 348         };
 349
 350         u32 v;
 351         u64 res;
 352         int i, ms;
 353         unsigned int delay_idx;
 354         __be64 *temp = (__be64 *)malloc(size * sizeof(char));
 355         __be64 *p = temp;
 356         u32 data_reg = PF_REG(mbox, A_CIM_PF_MAILBOX_DATA);
 357         u32 ctl_reg = PF_REG(mbox, A_CIM_PF_MAILBOX_CTRL);
 358         u32 ctl;
 359         struct mbox_entry entry;
 360         u32 pcie_fw = 0;
 361
 362         if (!temp)
 363                 return -ENOMEM;
 364
 365         if ((size & 15) || size > MBOX_LEN) {
 366                 free(temp);
 367                 return -EINVAL;
 368         }
 369
 370         bzero(p, size);
 371         memcpy(p, (const __be64 *)cmd, size);
 372
 373         /*
 374          * If we have a negative timeout, that implies that we can't sleep.
 375          */
 376         if (timeout < 0) {
 377                 sleep_ok = false;
 378                 timeout = -timeout;
 379         }
 380
 381 #ifdef T4_OS_NEEDS_MBOX_LOCKING
 382         /*
 383          * Queue ourselves onto the mailbox access list.  When our entry is at
 384          * the front of the list, we have rights to access the mailbox.  So we
 385          * wait [for a while] till we're at the front [or bail out with an
 386          * EBUSY] ...
 387          */
 388         t4_os_atomic_add_tail(&entry, &adap->mbox_list, &adap->mbox_lock);
 389
 390         delay_idx = 0;
 391         ms = delay[0];
 392
 393         for (i = 0; ; i += ms) {
 394                 /*
 395                  * If we've waited too long, return a busy indication.  This
 396                  * really ought to be based on our initial position in the
 397                  * mailbox access list but this is a start.  We very rarely
 398                  * contend on access to the mailbox ...  Also check for a
 399                  * firmware error which we'll report as a device error.
 400                  */
 401                 pcie_fw = t4_read_reg(adap, A_PCIE_FW);
 402                 if (i > 4 * timeout || (pcie_fw & F_PCIE_FW_ERR)) {
 403                         t4_os_atomic_list_del(&entry, &adap->mbox_list,
 404                                               &adap->mbox_lock);
 405                         t4_report_fw_error(adap);
 406                         return (pcie_fw & F_PCIE_FW_ERR) ? -ENXIO : -EBUSY;
 407                 }
 408
 409                 /*
 410                  * If we're at the head, break out and start the mailbox
 411                  * protocol.
 412                  */
 413                 if (t4_os_list_first_entry(&adap->mbox_list) == &entry)
 414                         break;
 415
 416                 /*
 417                  * Delay for a bit before checking again ...
 418                  */
 419                 if (sleep_ok) {
 420                         ms = delay[delay_idx];  /* last element may repeat */
 421                         if (delay_idx < ARRAY_SIZE(delay) - 1)
 422                                 delay_idx++;
 423                         msleep(ms);
 424                 } else {
 425                         rte_delay_ms(ms);
 426                 }
 427         }
 428 #endif /* T4_OS_NEEDS_MBOX_LOCKING */
 429
 430         /*
 431          * Attempt to gain access to the mailbox.
 432          */
 433         for (i = 0; i < 4; i++) {
 434                 ctl = t4_read_reg(adap, ctl_reg);
 435                 v = G_MBOWNER(ctl);
 436                 if (v != X_MBOWNER_NONE)
 437                         break;
 438         }
 439
 440         /*
 441          * If we were unable to gain access, dequeue ourselves from the
 442          * mailbox atomic access list and report the error to our caller.
 443          */
 444         if (v != X_MBOWNER_PL) {
 445                 T4_OS_MBOX_LOCKING(t4_os_atomic_list_del(&entry,
 446                                                          &adap->mbox_list,
 447                                                          &adap->mbox_lock));
 448                 t4_report_fw_error(adap);
 449                 return (v == X_MBOWNER_FW ? -EBUSY : -ETIMEDOUT);
 450         }
 451
 452         /*
 453          * If we gain ownership of the mailbox and there's a "valid" message
 454          * in it, this is likely an asynchronous error message from the
 455          * firmware.  So we'll report that and then proceed on with attempting
 456          * to issue our own command ... which may well fail if the error
 457          * presaged the firmware crashing ...
 458          */
 459         if (ctl & F_MBMSGVALID) {
 460                 dev_err(adap, "found VALID command in mbox %u: "
 461                         "%llx %llx %llx %llx %llx %llx %llx %llx\n", mbox,
 462                         (unsigned long long)t4_read_reg64(adap, data_reg),
 463                         (unsigned long long)t4_read_reg64(adap, data_reg + 8),
 464                         (unsigned long long)t4_read_reg64(adap, data_reg + 16),
 465                         (unsigned long long)t4_read_reg64(adap, data_reg + 24),
 466                         (unsigned long long)t4_read_reg64(adap, data_reg + 32),
 467                         (unsigned long long)t4_read_reg64(adap, data_reg + 40),
 468                         (unsigned long long)t4_read_reg64(adap, data_reg + 48),
 469                         (unsigned long long)t4_read_reg64(adap, data_reg + 56));
 470         }
 471
 472         /*
 473          * Copy in the new mailbox command and send it on its way ...
 474          */
 475         for (i = 0; i < size; i += 8, p++)
 476                 t4_write_reg64(adap, data_reg + i, be64_to_cpu(*p));
 477
 478         CXGBE_DEBUG_MBOX(adap, "%s: mbox %u: %016llx %016llx %016llx %016llx "
 479                         "%016llx %016llx %016llx %016llx\n", __func__,  (mbox),
 480                         (unsigned long long)t4_read_reg64(adap, data_reg),
 481                         (unsigned long long)t4_read_reg64(adap, data_reg + 8),
 482                         (unsigned long long)t4_read_reg64(adap, data_reg + 16),
 483                         (unsigned long long)t4_read_reg64(adap, data_reg + 24),
 484                         (unsigned long long)t4_read_reg64(adap, data_reg + 32),
 485                         (unsigned long long)t4_read_reg64(adap, data_reg + 40),
 486                         (unsigned long long)t4_read_reg64(adap, data_reg + 48),
 487                         (unsigned long long)t4_read_reg64(adap, data_reg + 56));
 488
 489         t4_write_reg(adap, ctl_reg, F_MBMSGVALID | V_MBOWNER(X_MBOWNER_FW));
 490         t4_read_reg(adap, ctl_reg);          /* flush write */
 491
 492         delay_idx = 0;
 493         ms = delay[0];
 494
 495         /*
 496          * Loop waiting for the reply; bail out if we time out or the firmware
 497          * reports an error.
 498          */
 499         pcie_fw = t4_read_reg(adap, A_PCIE_FW);
 500         for (i = 0; i < timeout && !(pcie_fw & F_PCIE_FW_ERR); i += ms) {
 501                 if (sleep_ok) {
 502                         ms = delay[delay_idx];  /* last element may repeat */
 503                         if (delay_idx < ARRAY_SIZE(delay) - 1)
 504                                 delay_idx++;
 505                         msleep(ms);
 506                 } else {
 507                         msleep(ms);
 508                 }
 509
 510                 pcie_fw = t4_read_reg(adap, A_PCIE_FW);
 511                 v = t4_read_reg(adap, ctl_reg);
 512                 if (v == X_CIM_PF_NOACCESS)
 513                         continue;
 514                 if (G_MBOWNER(v) == X_MBOWNER_PL) {
 515                         if (!(v & F_MBMSGVALID)) {
 516                                 t4_write_reg(adap, ctl_reg,
 517                                              V_MBOWNER(X_MBOWNER_NONE));
 518                                 continue;
 519                         }
 520
 521                         CXGBE_DEBUG_MBOX(adap,
 522                         "%s: mbox %u: %016llx %016llx %016llx %016llx "
 523                         "%016llx %016llx %016llx %016llx\n", __func__,  (mbox),
 524                         (unsigned long long)t4_read_reg64(adap, data_reg),
 525                         (unsigned long long)t4_read_reg64(adap, data_reg + 8),
 526                         (unsigned long long)t4_read_reg64(adap, data_reg + 16),
 527                         (unsigned long long)t4_read_reg64(adap, data_reg + 24),
 528                         (unsigned long long)t4_read_reg64(adap, data_reg + 32),
 529                         (unsigned long long)t4_read_reg64(adap, data_reg + 40),
 530                         (unsigned long long)t4_read_reg64(adap, data_reg + 48),
 531                         (unsigned long long)t4_read_reg64(adap, data_reg + 56));
 532
 533                         CXGBE_DEBUG_MBOX(adap,
 534                                 "command %#x completed in %d ms (%ssleeping)\n",
 535                                 *(const u8 *)cmd,
 536                                 i + ms, sleep_ok ? "" : "non-");
 537
 538                         res = t4_read_reg64(adap, data_reg);
 539                         if (G_FW_CMD_OP(res >> 32) == FW_DEBUG_CMD) {
 540                                 fw_asrt(adap, data_reg);
 541                                 res = V_FW_CMD_RETVAL(EIO);
 542                         } else if (rpl) {
 543                                 get_mbox_rpl(adap, rpl, size / 8, data_reg);
 544                         }
 545                         t4_write_reg(adap, ctl_reg, V_MBOWNER(X_MBOWNER_NONE));
 546                         T4_OS_MBOX_LOCKING(
 547                                 t4_os_atomic_list_del(&entry, &adap->mbox_list,
 548                                                       &adap->mbox_lock));
 549                         return -G_FW_CMD_RETVAL((int)res);
 550                 }
 551         }
 552
 553         /*
 554          * We timed out waiting for a reply to our mailbox command.  Report
 555          * the error and also check to see if the firmware reported any
 556          * errors ...
 557          */
 558         dev_err(adap, "command %#x in mailbox %d timed out\n",
 559                 *(const u8 *)cmd, mbox);
 560         T4_OS_MBOX_LOCKING(t4_os_atomic_list_del(&entry,
 561                                                  &adap->mbox_list,
 562                                                  &adap->mbox_lock));
 563         t4_report_fw_error(adap);
 564         free(temp);
 565         return (pcie_fw & F_PCIE_FW_ERR) ? -ENXIO : -ETIMEDOUT;
 566 }
 567
 568 int t4_wr_mbox_meat(struct adapter *adap, int mbox, const void *cmd, int size,
 569                     void *rpl, bool sleep_ok)
 570 {
 571         return t4_wr_mbox_meat_timeout(adap, mbox, cmd, size, rpl, sleep_ok,
 572                                        FW_CMD_MAX_TIMEOUT);
 573 }
 574
 575 /**
 576  * t4_get_regs_len - return the size of the chips register set
 577  * @adapter: the adapter
 578  *
 579  * Returns the size of the chip's BAR0 register space.
 580  */
 581 unsigned int t4_get_regs_len(struct adapter *adapter)
 582 {
 583         unsigned int chip_version = CHELSIO_CHIP_VERSION(adapter->params.chip);
 584
 585         switch (chip_version) {
 586         case CHELSIO_T5:
 587         case CHELSIO_T6:
 588                 return T5_REGMAP_SIZE;
 589         }
 590
 591         dev_err(adapter,
 592                 "Unsupported chip version %d\n", chip_version);
 593         return 0;
 594 }
 595
 596 /**
 597  * t4_get_regs - read chip registers into provided buffer
 598  * @adap: the adapter
 599  * @buf: register buffer
 600  * @buf_size: size (in bytes) of register buffer
 601  *
 602  * If the provided register buffer isn't large enough for the chip's
 603  * full register range, the register dump will be truncated to the
 604  * register buffer's size.
 605  */
 606 void t4_get_regs(struct adapter *adap, void *buf, size_t buf_size)
 607 {
 608         static const unsigned int t5_reg_ranges[] = {
 609                 0x1008, 0x10c0,
 610                 0x10cc, 0x10f8,
 611                 0x1100, 0x1100,
 612                 0x110c, 0x1148,
 613                 0x1180, 0x1184,
 614                 0x1190, 0x1194,
 615                 0x11a0, 0x11a4,
 616                 0x11b0, 0x11b4,
 617                 0x11fc, 0x123c,
 618                 0x1280, 0x173c,
 619                 0x1800, 0x18fc,
 620                 0x3000, 0x3028,
 621                 0x3060, 0x30b0,
 622                 0x30b8, 0x30d8,
 623                 0x30e0, 0x30fc,
 624                 0x3140, 0x357c,
 625                 0x35a8, 0x35cc,
 626                 0x35ec, 0x35ec,
 627                 0x3600, 0x5624,
 628                 0x56cc, 0x56ec,
 629                 0x56f4, 0x5720,
 630                 0x5728, 0x575c,
 631                 0x580c, 0x5814,
 632                 0x5890, 0x589c,
 633                 0x58a4, 0x58ac,
 634                 0x58b8, 0x58bc,
 635                 0x5940, 0x59c8,
 636                 0x59d0, 0x59dc,
 637                 0x59fc, 0x5a18,
 638                 0x5a60, 0x5a70,
 639                 0x5a80, 0x5a9c,
 640                 0x5b94, 0x5bfc,
 641                 0x6000, 0x6020,
 642                 0x6028, 0x6040,
 643                 0x6058, 0x609c,
 644                 0x60a8, 0x614c,
 645                 0x7700, 0x7798,
 646                 0x77c0, 0x78fc,
 647                 0x7b00, 0x7b58,
 648                 0x7b60, 0x7b84,
 649                 0x7b8c, 0x7c54,
 650                 0x7d00, 0x7d38,
 651                 0x7d40, 0x7d80,
 652                 0x7d8c, 0x7ddc,
 653                 0x7de4, 0x7e04,
 654                 0x7e10, 0x7e1c,
 655                 0x7e24, 0x7e38,
 656                 0x7e40, 0x7e44,
 657                 0x7e4c, 0x7e78,
 658                 0x7e80, 0x7edc,
 659                 0x7ee8, 0x7efc,
 660                 0x8dc0, 0x8de0,
 661                 0x8df8, 0x8e04,
 662                 0x8e10, 0x8e84,
 663                 0x8ea0, 0x8f84,
 664                 0x8fc0, 0x9058,
 665                 0x9060, 0x9060,
 666                 0x9068, 0x90f8,
 667                 0x9400, 0x9408,
 668                 0x9410, 0x9470,
 669                 0x9600, 0x9600,
 670                 0x9608, 0x9638,
 671                 0x9640, 0x96f4,
 672                 0x9800, 0x9808,
 673                 0x9820, 0x983c,
 674                 0x9850, 0x9864,
 675                 0x9c00, 0x9c6c,
 676                 0x9c80, 0x9cec,
 677                 0x9d00, 0x9d6c,
 678                 0x9d80, 0x9dec,
 679                 0x9e00, 0x9e6c,
 680                 0x9e80, 0x9eec,
 681                 0x9f00, 0x9f6c,
 682                 0x9f80, 0xa020,
 683                 0xd004, 0xd004,
 684                 0xd010, 0xd03c,
 685                 0xdfc0, 0xdfe0,
 686                 0xe000, 0x1106c,
 687                 0x11074, 0x11088,
 688                 0x1109c, 0x1117c,
 689                 0x11190, 0x11204,
 690                 0x19040, 0x1906c,
 691                 0x19078, 0x19080,
 692                 0x1908c, 0x190e8,
 693                 0x190f0, 0x190f8,
 694                 0x19100, 0x19110,
 695                 0x19120, 0x19124,
 696                 0x19150, 0x19194,
 697                 0x1919c, 0x191b0,
 698                 0x191d0, 0x191e8,
 699                 0x19238, 0x19290,
 700                 0x193f8, 0x19428,
 701                 0x19430, 0x19444,
 702                 0x1944c, 0x1946c,
 703                 0x19474, 0x19474,
 704                 0x19490, 0x194cc,
 705                 0x194f0, 0x194f8,
 706                 0x19c00, 0x19c08,
 707                 0x19c10, 0x19c60,
 708                 0x19c94, 0x19ce4,
 709                 0x19cf0, 0x19d40,
 710                 0x19d50, 0x19d94,
 711                 0x19da0, 0x19de8,
 712                 0x19df0, 0x19e10,
 713                 0x19e50, 0x19e90,
 714                 0x19ea0, 0x19f24,
 715                 0x19f34, 0x19f34,
 716                 0x19f40, 0x19f50,
 717                 0x19f90, 0x19fb4,
 718                 0x19fc4, 0x19fe4,
 719                 0x1a000, 0x1a004,
 720                 0x1a010, 0x1a06c,
 721                 0x1a0b0, 0x1a0e4,
 722                 0x1a0ec, 0x1a0f8,
 723                 0x1a100, 0x1a108,
 724                 0x1a114, 0x1a120,
 725                 0x1a128, 0x1a130,
 726                 0x1a138, 0x1a138,
 727                 0x1a190, 0x1a1c4,
 728                 0x1a1fc, 0x1a1fc,
 729                 0x1e008, 0x1e00c,
 730                 0x1e040, 0x1e044,
 731                 0x1e04c, 0x1e04c,
 732                 0x1e284, 0x1e290,
 733                 0x1e2c0, 0x1e2c0,
 734                 0x1e2e0, 0x1e2e0,
 735                 0x1e300, 0x1e384,
 736                 0x1e3c0, 0x1e3c8,
 737                 0x1e408, 0x1e40c,
 738                 0x1e440, 0x1e444,
 739                 0x1e44c, 0x1e44c,
 740                 0x1e684, 0x1e690,
 741                 0x1e6c0, 0x1e6c0,
 742                 0x1e6e0, 0x1e6e0,
 743                 0x1e700, 0x1e784,
 744                 0x1e7c0, 0x1e7c8,
 745                 0x1e808, 0x1e80c,
 746                 0x1e840, 0x1e844,
 747                 0x1e84c, 0x1e84c,
 748                 0x1ea84, 0x1ea90,
 749                 0x1eac0, 0x1eac0,
 750                 0x1eae0, 0x1eae0,
 751                 0x1eb00, 0x1eb84,
 752                 0x1ebc0, 0x1ebc8,
 753                 0x1ec08, 0x1ec0c,
 754                 0x1ec40, 0x1ec44,
 755                 0x1ec4c, 0x1ec4c,
 756                 0x1ee84, 0x1ee90,
 757                 0x1eec0, 0x1eec0,
 758                 0x1eee0, 0x1eee0,
 759                 0x1ef00, 0x1ef84,
 760                 0x1efc0, 0x1efc8,
 761                 0x1f008, 0x1f00c,
 762                 0x1f040, 0x1f044,
 763                 0x1f04c, 0x1f04c,
 764                 0x1f284, 0x1f290,
 765                 0x1f2c0, 0x1f2c0,
 766                 0x1f2e0, 0x1f2e0,
 767                 0x1f300, 0x1f384,
 768                 0x1f3c0, 0x1f3c8,
 769                 0x1f408, 0x1f40c,
 770                 0x1f440, 0x1f444,
 771                 0x1f44c, 0x1f44c,
 772                 0x1f684, 0x1f690,
 773                 0x1f6c0, 0x1f6c0,
 774                 0x1f6e0, 0x1f6e0,
 775                 0x1f700, 0x1f784,
 776                 0x1f7c0, 0x1f7c8,
 777                 0x1f808, 0x1f80c,
 778                 0x1f840, 0x1f844,
 779                 0x1f84c, 0x1f84c,
 780                 0x1fa84, 0x1fa90,
 781                 0x1fac0, 0x1fac0,
 782                 0x1fae0, 0x1fae0,
 783                 0x1fb00, 0x1fb84,
 784                 0x1fbc0, 0x1fbc8,
 785                 0x1fc08, 0x1fc0c,
 786                 0x1fc40, 0x1fc44,
 787                 0x1fc4c, 0x1fc4c,
 788                 0x1fe84, 0x1fe90,
 789                 0x1fec0, 0x1fec0,
 790                 0x1fee0, 0x1fee0,
 791                 0x1ff00, 0x1ff84,
 792                 0x1ffc0, 0x1ffc8,
 793                 0x30000, 0x30030,
 794                 0x30038, 0x30038,
 795                 0x30040, 0x30040,
 796                 0x30100, 0x30144,
 797                 0x30190, 0x301a0,
 798                 0x301a8, 0x301b8,
 799                 0x301c4, 0x301c8,
 800                 0x301d0, 0x301d0,
 801                 0x30200, 0x30318,
 802                 0x30400, 0x304b4,
 803                 0x304c0, 0x3052c,
 804                 0x30540, 0x3061c,
 805                 0x30800, 0x30828,
 806                 0x30834, 0x30834,
 807                 0x308c0, 0x30908,
 808                 0x30910, 0x309ac,
 809                 0x30a00, 0x30a14,
 810                 0x30a1c, 0x30a2c,
 811                 0x30a44, 0x30a50,
 812                 0x30a74, 0x30a74,
 813                 0x30a7c, 0x30afc,
 814                 0x30b08, 0x30c24,
 815                 0x30d00, 0x30d00,
 816                 0x30d08, 0x30d14,
 817                 0x30d1c, 0x30d20,
 818                 0x30d3c, 0x30d3c,
 819                 0x30d48, 0x30d50,
 820                 0x31200, 0x3120c,
 821                 0x31220, 0x31220,
 822                 0x31240, 0x31240,
 823                 0x31600, 0x3160c,
 824                 0x31a00, 0x31a1c,
 825                 0x31e00, 0x31e20,
 826                 0x31e38, 0x31e3c,
 827                 0x31e80, 0x31e80,
 828                 0x31e88, 0x31ea8,
 829                 0x31eb0, 0x31eb4,
 830                 0x31ec8, 0x31ed4,
 831                 0x31fb8, 0x32004,
 832                 0x32200, 0x32200,
 833                 0x32208, 0x32240,
 834                 0x32248, 0x32280,
 835                 0x32288, 0x322c0,
 836                 0x322c8, 0x322fc,
 837                 0x32600, 0x32630,
 838                 0x32a00, 0x32abc,
 839                 0x32b00, 0x32b10,
 840                 0x32b20, 0x32b30,
 841                 0x32b40, 0x32b50,
 842                 0x32b60, 0x32b70,
 843                 0x33000, 0x33028,
 844                 0x33030, 0x33048,
 845                 0x33060, 0x33068,
 846                 0x33070, 0x3309c,
 847                 0x330f0, 0x33128,
 848                 0x33130, 0x33148,
 849                 0x33160, 0x33168,
 850                 0x33170, 0x3319c,
 851                 0x331f0, 0x33238,
 852                 0x33240, 0x33240,
 853                 0x33248, 0x33250,
 854                 0x3325c, 0x33264,
 855                 0x33270, 0x332b8,
 856                 0x332c0, 0x332e4,
 857                 0x332f8, 0x33338,
 858                 0x33340, 0x33340,
 859                 0x33348, 0x33350,
 860                 0x3335c, 0x33364,
 861                 0x33370, 0x333b8,
 862                 0x333c0, 0x333e4,
 863                 0x333f8, 0x33428,
 864                 0x33430, 0x33448,
 865                 0x33460, 0x33468,
 866                 0x33470, 0x3349c,
 867                 0x334f0, 0x33528,
 868                 0x33530, 0x33548,
 869                 0x33560, 0x33568,
 870                 0x33570, 0x3359c,
 871                 0x335f0, 0x33638,
 872                 0x33640, 0x33640,
 873                 0x33648, 0x33650,
 874                 0x3365c, 0x33664,
 875                 0x33670, 0x336b8,
 876                 0x336c0, 0x336e4,
 877                 0x336f8, 0x33738,
 878                 0x33740, 0x33740,
 879                 0x33748, 0x33750,
 880                 0x3375c, 0x33764,
 881                 0x33770, 0x337b8,
 882                 0x337c0, 0x337e4,
 883                 0x337f8, 0x337fc,
 884                 0x33814, 0x33814,
 885                 0x3382c, 0x3382c,
 886                 0x33880, 0x3388c,
 887                 0x338e8, 0x338ec,
 888                 0x33900, 0x33928,
 889                 0x33930, 0x33948,
 890                 0x33960, 0x33968,
 891                 0x33970, 0x3399c,
 892                 0x339f0, 0x33a38,
 893                 0x33a40, 0x33a40,
 894                 0x33a48, 0x33a50,
 895                 0x33a5c, 0x33a64,
 896                 0x33a70, 0x33ab8,
 897                 0x33ac0, 0x33ae4,
 898                 0x33af8, 0x33b10,
 899                 0x33b28, 0x33b28,
 900                 0x33b3c, 0x33b50,
 901                 0x33bf0, 0x33c10,
 902                 0x33c28, 0x33c28,
 903                 0x33c3c, 0x33c50,
 904                 0x33cf0, 0x33cfc,
 905                 0x34000, 0x34030,
 906                 0x34038, 0x34038,
 907                 0x34040, 0x34040,
 908                 0x34100, 0x34144,
 909                 0x34190, 0x341a0,
 910                 0x341a8, 0x341b8,
 911                 0x341c4, 0x341c8,
 912                 0x341d0, 0x341d0,
 913                 0x34200, 0x34318,
 914                 0x34400, 0x344b4,
 915                 0x344c0, 0x3452c,
 916                 0x34540, 0x3461c,
 917                 0x34800, 0x34828,
 918                 0x34834, 0x34834,
 919                 0x348c0, 0x34908,
 920                 0x34910, 0x349ac,
 921                 0x34a00, 0x34a14,
 922                 0x34a1c, 0x34a2c,
 923                 0x34a44, 0x34a50,
 924                 0x34a74, 0x34a74,
 925                 0x34a7c, 0x34afc,
 926                 0x34b08, 0x34c24,
 927                 0x34d00, 0x34d00,
 928                 0x34d08, 0x34d14,
 929                 0x34d1c, 0x34d20,
 930                 0x34d3c, 0x34d3c,
 931                 0x34d48, 0x34d50,
 932                 0x35200, 0x3520c,
 933                 0x35220, 0x35220,
 934                 0x35240, 0x35240,
 935                 0x35600, 0x3560c,
 936                 0x35a00, 0x35a1c,
 937                 0x35e00, 0x35e20,
 938                 0x35e38, 0x35e3c,
 939                 0x35e80, 0x35e80,
 940                 0x35e88, 0x35ea8,
 941                 0x35eb0, 0x35eb4,
 942                 0x35ec8, 0x35ed4,
 943                 0x35fb8, 0x36004,
 944                 0x36200, 0x36200,
 945                 0x36208, 0x36240,
 946                 0x36248, 0x36280,
 947                 0x36288, 0x362c0,
 948                 0x362c8, 0x362fc,
 949                 0x36600, 0x36630,
 950                 0x36a00, 0x36abc,
 951                 0x36b00, 0x36b10,
 952                 0x36b20, 0x36b30,
 953                 0x36b40, 0x36b50,
 954                 0x36b60, 0x36b70,
 955                 0x37000, 0x37028,
 956                 0x37030, 0x37048,
 957                 0x37060, 0x37068,
 958                 0x37070, 0x3709c,
 959                 0x370f0, 0x37128,
 960                 0x37130, 0x37148,
 961                 0x37160, 0x37168,
 962                 0x37170, 0x3719c,
 963                 0x371f0, 0x37238,
 964                 0x37240, 0x37240,
 965                 0x37248, 0x37250,
 966                 0x3725c, 0x37264,
 967                 0x37270, 0x372b8,
 968                 0x372c0, 0x372e4,
 969                 0x372f8, 0x37338,
 970                 0x37340, 0x37340,
 971                 0x37348, 0x37350,
 972                 0x3735c, 0x37364,
 973                 0x37370, 0x373b8,
 974                 0x373c0, 0x373e4,
 975                 0x373f8, 0x37428,
 976                 0x37430, 0x37448,
 977                 0x37460, 0x37468,
 978                 0x37470, 0x3749c,
 979                 0x374f0, 0x37528,
 980                 0x37530, 0x37548,
 981                 0x37560, 0x37568,
 982                 0x37570, 0x3759c,
 983                 0x375f0, 0x37638,
 984                 0x37640, 0x37640,
 985                 0x37648, 0x37650,
 986                 0x3765c, 0x37664,
 987                 0x37670, 0x376b8,
 988                 0x376c0, 0x376e4,
 989                 0x376f8, 0x37738,
 990                 0x37740, 0x37740,
 991                 0x37748, 0x37750,
 992                 0x3775c, 0x37764,
 993                 0x37770, 0x377b8,
 994                 0x377c0, 0x377e4,
 995                 0x377f8, 0x377fc,
 996                 0x37814, 0x37814,
 997                 0x3782c, 0x3782c,
 998                 0x37880, 0x3788c,
 999                 0x378e8, 0x378ec,
1000                 0x37900, 0x37928,
1001                 0x37930, 0x37948,
1002                 0x37960, 0x37968,
1003                 0x37970, 0x3799c,
1004                 0x379f0, 0x37a38,
1005                 0x37a40, 0x37a40,
1006                 0x37a48, 0x37a50,
1007                 0x37a5c, 0x37a64,
1008                 0x37a70, 0x37ab8,
1009                 0x37ac0, 0x37ae4,
1010                 0x37af8, 0x37b10,
1011                 0x37b28, 0x37b28,
1012                 0x37b3c, 0x37b50,
1013                 0x37bf0, 0x37c10,
1014                 0x37c28, 0x37c28,
1015                 0x37c3c, 0x37c50,
1016                 0x37cf0, 0x37cfc,
1017                 0x38000, 0x38030,
1018                 0x38038, 0x38038,
1019                 0x38040, 0x38040,
1020                 0x38100, 0x38144,
1021                 0x38190, 0x381a0,
1022                 0x381a8, 0x381b8,
1023                 0x381c4, 0x381c8,
1024                 0x381d0, 0x381d0,
1025                 0x38200, 0x38318,
1026                 0x38400, 0x384b4,
1027                 0x384c0, 0x3852c,
1028                 0x38540, 0x3861c,
1029                 0x38800, 0x38828,
1030                 0x38834, 0x38834,
1031                 0x388c0, 0x38908,
1032                 0x38910, 0x389ac,
1033                 0x38a00, 0x38a14,
1034                 0x38a1c, 0x38a2c,
1035                 0x38a44, 0x38a50,
1036                 0x38a74, 0x38a74,
1037                 0x38a7c, 0x38afc,
1038                 0x38b08, 0x38c24,
1039                 0x38d00, 0x38d00,
1040                 0x38d08, 0x38d14,
1041                 0x38d1c, 0x38d20,
1042                 0x38d3c, 0x38d3c,
1043                 0x38d48, 0x38d50,
1044                 0x39200, 0x3920c,
1045                 0x39220, 0x39220,
1046                 0x39240, 0x39240,
1047                 0x39600, 0x3960c,
1048                 0x39a00, 0x39a1c,
1049                 0x39e00, 0x39e20,
1050                 0x39e38, 0x39e3c,
1051                 0x39e80, 0x39e80,
1052                 0x39e88, 0x39ea8,
1053                 0x39eb0, 0x39eb4,
1054                 0x39ec8, 0x39ed4,
1055                 0x39fb8, 0x3a004,
1056                 0x3a200, 0x3a200,
1057                 0x3a208, 0x3a240,
1058                 0x3a248, 0x3a280,
1059                 0x3a288, 0x3a2c0,
1060                 0x3a2c8, 0x3a2fc,
1061                 0x3a600, 0x3a630,
1062                 0x3aa00, 0x3aabc,
1063                 0x3ab00, 0x3ab10,
1064                 0x3ab20, 0x3ab30,
1065                 0x3ab40, 0x3ab50,
1066                 0x3ab60, 0x3ab70,
1067                 0x3b000, 0x3b028,
1068                 0x3b030, 0x3b048,
1069                 0x3b060, 0x3b068,
1070                 0x3b070, 0x3b09c,
1071                 0x3b0f0, 0x3b128,
1072                 0x3b130, 0x3b148,
1073                 0x3b160, 0x3b168,
1074                 0x3b170, 0x3b19c,
1075                 0x3b1f0, 0x3b238,
1076                 0x3b240, 0x3b240,
1077                 0x3b248, 0x3b250,
1078                 0x3b25c, 0x3b264,
1079                 0x3b270, 0x3b2b8,
1080                 0x3b2c0, 0x3b2e4,
1081                 0x3b2f8, 0x3b338,
1082                 0x3b340, 0x3b340,
1083                 0x3b348, 0x3b350,
1084                 0x3b35c, 0x3b364,
1085                 0x3b370, 0x3b3b8,
1086                 0x3b3c0, 0x3b3e4,
1087                 0x3b3f8, 0x3b428,
1088                 0x3b430, 0x3b448,
1089                 0x3b460, 0x3b468,
1090                 0x3b470, 0x3b49c,
1091                 0x3b4f0, 0x3b528,
1092                 0x3b530, 0x3b548,
1093                 0x3b560, 0x3b568,
1094                 0x3b570, 0x3b59c,
1095                 0x3b5f0, 0x3b638,
1096                 0x3b640, 0x3b640,
1097                 0x3b648, 0x3b650,
1098                 0x3b65c, 0x3b664,
1099                 0x3b670, 0x3b6b8,
1100                 0x3b6c0, 0x3b6e4,
1101                 0x3b6f8, 0x3b738,
1102                 0x3b740, 0x3b740,
1103                 0x3b748, 0x3b750,
1104                 0x3b75c, 0x3b764,
1105                 0x3b770, 0x3b7b8,
1106                 0x3b7c0, 0x3b7e4,
1107                 0x3b7f8, 0x3b7fc,
1108                 0x3b814, 0x3b814,
1109                 0x3b82c, 0x3b82c,
1110                 0x3b880, 0x3b88c,
1111                 0x3b8e8, 0x3b8ec,
1112                 0x3b900, 0x3b928,
1113                 0x3b930, 0x3b948,
1114                 0x3b960, 0x3b968,
1115                 0x3b970, 0x3b99c,
1116                 0x3b9f0, 0x3ba38,
1117                 0x3ba40, 0x3ba40,
1118                 0x3ba48, 0x3ba50,
1119                 0x3ba5c, 0x3ba64,
1120                 0x3ba70, 0x3bab8,
1121                 0x3bac0, 0x3bae4,
1122                 0x3baf8, 0x3bb10,
1123                 0x3bb28, 0x3bb28,
1124                 0x3bb3c, 0x3bb50,
1125                 0x3bbf0, 0x3bc10,
1126                 0x3bc28, 0x3bc28,
1127                 0x3bc3c, 0x3bc50,
1128                 0x3bcf0, 0x3bcfc,
1129                 0x3c000, 0x3c030,
1130                 0x3c038, 0x3c038,
1131                 0x3c040, 0x3c040,
1132                 0x3c100, 0x3c144,
1133                 0x3c190, 0x3c1a0,
1134                 0x3c1a8, 0x3c1b8,
1135                 0x3c1c4, 0x3c1c8,
1136                 0x3c1d0, 0x3c1d0,
1137                 0x3c200, 0x3c318,
1138                 0x3c400, 0x3c4b4,
1139                 0x3c4c0, 0x3c52c,
1140                 0x3c540, 0x3c61c,
1141                 0x3c800, 0x3c828,
1142                 0x3c834, 0x3c834,
1143                 0x3c8c0, 0x3c908,
1144                 0x3c910, 0x3c9ac,
1145                 0x3ca00, 0x3ca14,
1146                 0x3ca1c, 0x3ca2c,
1147                 0x3ca44, 0x3ca50,
1148                 0x3ca74, 0x3ca74,
1149                 0x3ca7c, 0x3cafc,
1150                 0x3cb08, 0x3cc24,
1151                 0x3cd00, 0x3cd00,
1152                 0x3cd08, 0x3cd14,
1153                 0x3cd1c, 0x3cd20,
1154                 0x3cd3c, 0x3cd3c,
1155                 0x3cd48, 0x3cd50,
1156                 0x3d200, 0x3d20c,
1157                 0x3d220, 0x3d220,
1158                 0x3d240, 0x3d240,
1159                 0x3d600, 0x3d60c,
1160                 0x3da00, 0x3da1c,
1161                 0x3de00, 0x3de20,
1162                 0x3de38, 0x3de3c,
1163                 0x3de80, 0x3de80,
1164                 0x3de88, 0x3dea8,
1165                 0x3deb0, 0x3deb4,
1166                 0x3dec8, 0x3ded4,
1167                 0x3dfb8, 0x3e004,
1168                 0x3e200, 0x3e200,
1169                 0x3e208, 0x3e240,
1170                 0x3e248, 0x3e280,
1171                 0x3e288, 0x3e2c0,
1172                 0x3e2c8, 0x3e2fc,
1173                 0x3e600, 0x3e630,
1174                 0x3ea00, 0x3eabc,
1175                 0x3eb00, 0x3eb10,
1176                 0x3eb20, 0x3eb30,
1177                 0x3eb40, 0x3eb50,
1178                 0x3eb60, 0x3eb70,
1179                 0x3f000, 0x3f028,
1180                 0x3f030, 0x3f048,
1181                 0x3f060, 0x3f068,
1182                 0x3f070, 0x3f09c,
1183                 0x3f0f0, 0x3f128,
1184                 0x3f130, 0x3f148,
1185                 0x3f160, 0x3f168,
1186                 0x3f170, 0x3f19c,
1187                 0x3f1f0, 0x3f238,
1188                 0x3f240, 0x3f240,
1189                 0x3f248, 0x3f250,
1190                 0x3f25c, 0x3f264,
1191                 0x3f270, 0x3f2b8,
1192                 0x3f2c0, 0x3f2e4,
1193                 0x3f2f8, 0x3f338,
1194                 0x3f340, 0x3f340,
1195                 0x3f348, 0x3f350,
1196                 0x3f35c, 0x3f364,
1197                 0x3f370, 0x3f3b8,
1198                 0x3f3c0, 0x3f3e4,
1199                 0x3f3f8, 0x3f428,
1200                 0x3f430, 0x3f448,
1201                 0x3f460, 0x3f468,
1202                 0x3f470, 0x3f49c,
1203                 0x3f4f0, 0x3f528,
1204                 0x3f530, 0x3f548,
1205                 0x3f560, 0x3f568,
1206                 0x3f570, 0x3f59c,
1207                 0x3f5f0, 0x3f638,
1208                 0x3f640, 0x3f640,
1209                 0x3f648, 0x3f650,
1210                 0x3f65c, 0x3f664,
1211                 0x3f670, 0x3f6b8,
1212                 0x3f6c0, 0x3f6e4,
1213                 0x3f6f8, 0x3f738,
1214                 0x3f740, 0x3f740,
1215                 0x3f748, 0x3f750,
1216                 0x3f75c, 0x3f764,
1217                 0x3f770, 0x3f7b8,
1218                 0x3f7c0, 0x3f7e4,
1219                 0x3f7f8, 0x3f7fc,
1220                 0x3f814, 0x3f814,
1221                 0x3f82c, 0x3f82c,
1222                 0x3f880, 0x3f88c,
1223                 0x3f8e8, 0x3f8ec,
1224                 0x3f900, 0x3f928,
1225                 0x3f930, 0x3f948,
1226                 0x3f960, 0x3f968,
1227                 0x3f970, 0x3f99c,
1228                 0x3f9f0, 0x3fa38,
1229                 0x3fa40, 0x3fa40,
1230                 0x3fa48, 0x3fa50,
1231                 0x3fa5c, 0x3fa64,
1232                 0x3fa70, 0x3fab8,
1233                 0x3fac0, 0x3fae4,
1234                 0x3faf8, 0x3fb10,
1235                 0x3fb28, 0x3fb28,
1236                 0x3fb3c, 0x3fb50,
1237                 0x3fbf0, 0x3fc10,
1238                 0x3fc28, 0x3fc28,
1239                 0x3fc3c, 0x3fc50,
1240                 0x3fcf0, 0x3fcfc,
1241                 0x40000, 0x4000c,
1242                 0x40040, 0x40050,
1243                 0x40060, 0x40068,
1244                 0x4007c, 0x4008c,
1245                 0x40094, 0x400b0,
1246                 0x400c0, 0x40144,
1247                 0x40180, 0x4018c,
1248                 0x40200, 0x40254,
1249                 0x40260, 0x40264,
1250                 0x40270, 0x40288,
1251                 0x40290, 0x40298,
1252                 0x402ac, 0x402c8,
1253                 0x402d0, 0x402e0,
1254                 0x402f0, 0x402f0,
1255                 0x40300, 0x4033c,
1256                 0x403f8, 0x403fc,
1257                 0x41304, 0x413c4,
1258                 0x41400, 0x4140c,
1259                 0x41414, 0x4141c,
1260                 0x41480, 0x414d0,
1261                 0x44000, 0x44054,
1262                 0x4405c, 0x44078,
1263                 0x440c0, 0x44174,
1264                 0x44180, 0x441ac,
1265                 0x441b4, 0x441b8,
1266                 0x441c0, 0x44254,
1267                 0x4425c, 0x44278,
1268                 0x442c0, 0x44374,
1269                 0x44380, 0x443ac,
1270                 0x443b4, 0x443b8,
1271                 0x443c0, 0x44454,
1272                 0x4445c, 0x44478,
1273                 0x444c0, 0x44574,
1274                 0x44580, 0x445ac,
1275                 0x445b4, 0x445b8,
1276                 0x445c0, 0x44654,
1277                 0x4465c, 0x44678,
1278                 0x446c0, 0x44774,
1279                 0x44780, 0x447ac,
1280                 0x447b4, 0x447b8,
1281                 0x447c0, 0x44854,
1282                 0x4485c, 0x44878,
1283                 0x448c0, 0x44974,
1284                 0x44980, 0x449ac,
1285                 0x449b4, 0x449b8,
1286                 0x449c0, 0x449fc,
1287                 0x45000, 0x45004,
1288                 0x45010, 0x45030,
1289                 0x45040, 0x45060,
1290                 0x45068, 0x45068,
1291                 0x45080, 0x45084,
1292                 0x450a0, 0x450b0,
1293                 0x45200, 0x45204,
1294                 0x45210, 0x45230,
1295                 0x45240, 0x45260,
1296                 0x45268, 0x45268,
1297                 0x45280, 0x45284,
1298                 0x452a0, 0x452b0,
1299                 0x460c0, 0x460e4,
1300                 0x47000, 0x4703c,
1301                 0x47044, 0x4708c,
1302                 0x47200, 0x47250,
1303                 0x47400, 0x47408,
1304                 0x47414, 0x47420,
1305                 0x47600, 0x47618,
1306                 0x47800, 0x47814,
1307                 0x48000, 0x4800c,
1308                 0x48040, 0x48050,
1309                 0x48060, 0x48068,
1310                 0x4807c, 0x4808c,
1311                 0x48094, 0x480b0,
1312                 0x480c0, 0x48144,
1313                 0x48180, 0x4818c,
1314                 0x48200, 0x48254,
1315                 0x48260, 0x48264,
1316                 0x48270, 0x48288,
1317                 0x48290, 0x48298,
1318                 0x482ac, 0x482c8,
1319                 0x482d0, 0x482e0,
1320                 0x482f0, 0x482f0,
1321                 0x48300, 0x4833c,
1322                 0x483f8, 0x483fc,
1323                 0x49304, 0x493c4,
1324                 0x49400, 0x4940c,
1325                 0x49414, 0x4941c,
1326                 0x49480, 0x494d0,
1327                 0x4c000, 0x4c054,
1328                 0x4c05c, 0x4c078,
1329                 0x4c0c0, 0x4c174,
1330                 0x4c180, 0x4c1ac,
1331                 0x4c1b4, 0x4c1b8,
1332                 0x4c1c0, 0x4c254,
1333                 0x4c25c, 0x4c278,
1334                 0x4c2c0, 0x4c374,
1335                 0x4c380, 0x4c3ac,
1336                 0x4c3b4, 0x4c3b8,
1337                 0x4c3c0, 0x4c454,
1338                 0x4c45c, 0x4c478,
1339                 0x4c4c0, 0x4c574,
1340                 0x4c580, 0x4c5ac,
1341                 0x4c5b4, 0x4c5b8,
1342                 0x4c5c0, 0x4c654,
1343                 0x4c65c, 0x4c678,
1344                 0x4c6c0, 0x4c774,
1345                 0x4c780, 0x4c7ac,
1346                 0x4c7b4, 0x4c7b8,
1347                 0x4c7c0, 0x4c854,
1348                 0x4c85c, 0x4c878,
1349                 0x4c8c0, 0x4c974,
1350                 0x4c980, 0x4c9ac,
1351                 0x4c9b4, 0x4c9b8,
1352                 0x4c9c0, 0x4c9fc,
1353                 0x4d000, 0x4d004,
1354                 0x4d010, 0x4d030,
1355                 0x4d040, 0x4d060,
1356                 0x4d068, 0x4d068,
1357                 0x4d080, 0x4d084,
1358                 0x4d0a0, 0x4d0b0,
1359                 0x4d200, 0x4d204,
1360                 0x4d210, 0x4d230,
1361                 0x4d240, 0x4d260,
1362                 0x4d268, 0x4d268,
1363                 0x4d280, 0x4d284,
1364                 0x4d2a0, 0x4d2b0,
1365                 0x4e0c0, 0x4e0e4,
1366                 0x4f000, 0x4f03c,
1367                 0x4f044, 0x4f08c,
1368                 0x4f200, 0x4f250,
1369                 0x4f400, 0x4f408,
1370                 0x4f414, 0x4f420,
1371                 0x4f600, 0x4f618,
1372                 0x4f800, 0x4f814,
1373                 0x50000, 0x50084,
1374                 0x50090, 0x500cc,
1375                 0x50400, 0x50400,
1376                 0x50800, 0x50884,
1377                 0x50890, 0x508cc,
1378                 0x50c00, 0x50c00,
1379                 0x51000, 0x5101c,
1380                 0x51300, 0x51308,
1381         };
1382
1383         static const unsigned int t6_reg_ranges[] = {
1384                 0x1008, 0x101c,
1385                 0x1024, 0x10a8,
1386                 0x10b4, 0x10f8,
1387                 0x1100, 0x1114,
1388                 0x111c, 0x112c,
1389                 0x1138, 0x113c,
1390                 0x1144, 0x114c,
1391                 0x1180, 0x1184,
1392                 0x1190, 0x1194,
1393                 0x11a0, 0x11a4,
1394                 0x11b0, 0x11b4,
1395                 0x11fc, 0x1274,
1396                 0x1280, 0x133c,
1397                 0x1800, 0x18fc,
1398                 0x3000, 0x302c,
1399                 0x3060, 0x30b0,
1400                 0x30b8, 0x30d8,
1401                 0x30e0, 0x30fc,
1402                 0x3140, 0x357c,
1403                 0x35a8, 0x35cc,
1404                 0x35ec, 0x35ec,
1405                 0x3600, 0x5624,
1406                 0x56cc, 0x56ec,
1407                 0x56f4, 0x5720,
1408                 0x5728, 0x575c,
1409                 0x580c, 0x5814,
1410                 0x5890, 0x589c,
1411                 0x58a4, 0x58ac,
1412                 0x58b8, 0x58bc,
1413                 0x5940, 0x595c,
1414                 0x5980, 0x598c,
1415                 0x59b0, 0x59c8,
1416                 0x59d0, 0x59dc,
1417                 0x59fc, 0x5a18,
1418                 0x5a60, 0x5a6c,
1419                 0x5a80, 0x5a8c,
1420                 0x5a94, 0x5a9c,
1421                 0x5b94, 0x5bfc,
1422                 0x5c10, 0x5e48,
1423                 0x5e50, 0x5e94,
1424                 0x5ea0, 0x5eb0,
1425                 0x5ec0, 0x5ec0,
1426                 0x5ec8, 0x5ed0,
1427                 0x5ee0, 0x5ee0,
1428                 0x5ef0, 0x5ef0,
1429                 0x5f00, 0x5f00,
1430                 0x6000, 0x6020,
1431                 0x6028, 0x6040,
1432                 0x6058, 0x609c,
1433                 0x60a8, 0x619c,
1434                 0x7700, 0x7798,
1435                 0x77c0, 0x7880,
1436                 0x78cc, 0x78fc,
1437                 0x7b00, 0x7b58,
1438                 0x7b60, 0x7b84,
1439                 0x7b8c, 0x7c54,
1440                 0x7d00, 0x7d38,
1441                 0x7d40, 0x7d84,
1442                 0x7d8c, 0x7ddc,
1443                 0x7de4, 0x7e04,
1444                 0x7e10, 0x7e1c,
1445                 0x7e24, 0x7e38,
1446                 0x7e40, 0x7e44,
1447                 0x7e4c, 0x7e78,
1448                 0x7e80, 0x7edc,
1449                 0x7ee8, 0x7efc,
1450                 0x8dc0, 0x8de4,
1451                 0x8df8, 0x8e04,
1452                 0x8e10, 0x8e84,
1453                 0x8ea0, 0x8f88,
1454                 0x8fb8, 0x9058,
1455                 0x9060, 0x9060,
1456                 0x9068, 0x90f8,
1457                 0x9100, 0x9124,
1458                 0x9400, 0x9470,
1459                 0x9600, 0x9600,
1460                 0x9608, 0x9638,
1461                 0x9640, 0x9704,
1462                 0x9710, 0x971c,
1463                 0x9800, 0x9808,
1464                 0x9820, 0x983c,
1465                 0x9850, 0x9864,
1466                 0x9c00, 0x9c6c,
1467                 0x9c80, 0x9cec,
1468                 0x9d00, 0x9d6c,
1469                 0x9d80, 0x9dec,
1470                 0x9e00, 0x9e6c,
1471                 0x9e80, 0x9eec,
1472                 0x9f00, 0x9f6c,
1473                 0x9f80, 0xa020,
1474                 0xd004, 0xd03c,
1475                 0xd100, 0xd118,
1476                 0xd200, 0xd214,
1477                 0xd220, 0xd234,
1478                 0xd240, 0xd254,
1479                 0xd260, 0xd274,
1480                 0xd280, 0xd294,
1481                 0xd2a0, 0xd2b4,
1482                 0xd2c0, 0xd2d4,
1483                 0xd2e0, 0xd2f4,
1484                 0xd300, 0xd31c,
1485                 0xdfc0, 0xdfe0,
1486                 0xe000, 0xf008,
1487                 0xf010, 0xf018,
1488                 0xf020, 0xf028,
1489                 0x11000, 0x11014,
1490                 0x11048, 0x1106c,
1491                 0x11074, 0x11088,
1492                 0x11098, 0x11120,
1493                 0x1112c, 0x1117c,
1494                 0x11190, 0x112e0,
1495                 0x11300, 0x1130c,
1496                 0x12000, 0x1206c,
1497                 0x19040, 0x1906c,
1498                 0x19078, 0x19080,
1499                 0x1908c, 0x190e8,
1500                 0x190f0, 0x190f8,
1501                 0x19100, 0x19110,
1502                 0x19120, 0x19124,
1503                 0x19150, 0x19194,
1504                 0x1919c, 0x191b0,
1505                 0x191d0, 0x191e8,
1506                 0x19238, 0x19290,
1507                 0x192a4, 0x192b0,
1508                 0x192bc, 0x192bc,
1509                 0x19348, 0x1934c,
1510                 0x193f8, 0x19418,
1511                 0x19420, 0x19428,
1512                 0x19430, 0x19444,
1513                 0x1944c, 0x1946c,
1514                 0x19474, 0x19474,
1515                 0x19490, 0x194cc,
1516                 0x194f0, 0x194f8,
1517                 0x19c00, 0x19c48,
1518                 0x19c50, 0x19c80,
1519                 0x19c94, 0x19c98,
1520                 0x19ca0, 0x19cbc,
1521                 0x19ce4, 0x19ce4,
1522                 0x19cf0, 0x19cf8,
1523                 0x19d00, 0x19d28,
1524                 0x19d50, 0x19d78,
1525                 0x19d94, 0x19d98,
1526                 0x19da0, 0x19dc8,
1527                 0x19df0, 0x19e10,
1528                 0x19e50, 0x19e6c,
1529                 0x19ea0, 0x19ebc,
1530                 0x19ec4, 0x19ef4,
1531                 0x19f04, 0x19f2c,
1532                 0x19f34, 0x19f34,
1533                 0x19f40, 0x19f50,
1534                 0x19f90, 0x19fac,
1535                 0x19fc4, 0x19fc8,
1536                 0x19fd0, 0x19fe4,
1537                 0x1a000, 0x1a004,
1538                 0x1a010, 0x1a06c,
1539                 0x1a0b0, 0x1a0e4,
1540                 0x1a0ec, 0x1a0f8,
1541                 0x1a100, 0x1a108,
1542                 0x1a114, 0x1a120,
1543                 0x1a128, 0x1a130,
1544                 0x1a138, 0x1a138,
1545                 0x1a190, 0x1a1c4,
1546                 0x1a1fc, 0x1a1fc,
1547                 0x1e008, 0x1e00c,
1548                 0x1e040, 0x1e044,
1549                 0x1e04c, 0x1e04c,
1550                 0x1e284, 0x1e290,
1551                 0x1e2c0, 0x1e2c0,
1552                 0x1e2e0, 0x1e2e0,
1553                 0x1e300, 0x1e384,
1554                 0x1e3c0, 0x1e3c8,
1555                 0x1e408, 0x1e40c,
1556                 0x1e440, 0x1e444,
1557                 0x1e44c, 0x1e44c,
1558                 0x1e684, 0x1e690,
1559                 0x1e6c0, 0x1e6c0,
1560                 0x1e6e0, 0x1e6e0,
1561                 0x1e700, 0x1e784,
1562                 0x1e7c0, 0x1e7c8,
1563                 0x1e808, 0x1e80c,
1564                 0x1e840, 0x1e844,
1565                 0x1e84c, 0x1e84c,
1566                 0x1ea84, 0x1ea90,
1567                 0x1eac0, 0x1eac0,
1568                 0x1eae0, 0x1eae0,
1569                 0x1eb00, 0x1eb84,
1570                 0x1ebc0, 0x1ebc8,
1571                 0x1ec08, 0x1ec0c,
1572                 0x1ec40, 0x1ec44,
1573                 0x1ec4c, 0x1ec4c,
1574                 0x1ee84, 0x1ee90,
1575                 0x1eec0, 0x1eec0,
1576                 0x1eee0, 0x1eee0,
1577                 0x1ef00, 0x1ef84,
1578                 0x1efc0, 0x1efc8,
1579                 0x1f008, 0x1f00c,
1580                 0x1f040, 0x1f044,
1581                 0x1f04c, 0x1f04c,
1582                 0x1f284, 0x1f290,
1583                 0x1f2c0, 0x1f2c0,
1584                 0x1f2e0, 0x1f2e0,
1585                 0x1f300, 0x1f384,
1586                 0x1f3c0, 0x1f3c8,
1587                 0x1f408, 0x1f40c,
1588                 0x1f440, 0x1f444,
1589                 0x1f44c, 0x1f44c,
1590                 0x1f684, 0x1f690,
1591                 0x1f6c0, 0x1f6c0,
1592                 0x1f6e0, 0x1f6e0,
1593                 0x1f700, 0x1f784,
1594                 0x1f7c0, 0x1f7c8,
1595                 0x1f808, 0x1f80c,
1596                 0x1f840, 0x1f844,
1597                 0x1f84c, 0x1f84c,
1598                 0x1fa84, 0x1fa90,
1599                 0x1fac0, 0x1fac0,
1600                 0x1fae0, 0x1fae0,
1601                 0x1fb00, 0x1fb84,
1602                 0x1fbc0, 0x1fbc8,
1603                 0x1fc08, 0x1fc0c,
1604                 0x1fc40, 0x1fc44,
1605                 0x1fc4c, 0x1fc4c,
1606                 0x1fe84, 0x1fe90,
1607                 0x1fec0, 0x1fec0,
1608                 0x1fee0, 0x1fee0,
1609                 0x1ff00, 0x1ff84,
1610                 0x1ffc0, 0x1ffc8,
1611                 0x30000, 0x30030,
1612                 0x30100, 0x30168,
1613                 0x30190, 0x301a0,
1614                 0x301a8, 0x301b8,
1615                 0x301c4, 0x301c8,
1616                 0x301d0, 0x301d0,
1617                 0x30200, 0x30320,
1618                 0x30400, 0x304b4,
1619                 0x304c0, 0x3052c,
1620                 0x30540, 0x3061c,
1621                 0x30800, 0x308a0,
1622                 0x308c0, 0x30908,
1623                 0x30910, 0x309b8,
1624                 0x30a00, 0x30a04,
1625                 0x30a0c, 0x30a14,
1626                 0x30a1c, 0x30a2c,
1627                 0x30a44, 0x30a50,
1628                 0x30a74, 0x30a74,
1629                 0x30a7c, 0x30afc,
1630                 0x30b08, 0x30c24,
1631                 0x30d00, 0x30d14,
1632                 0x30d1c, 0x30d3c,
1633                 0x30d44, 0x30d4c,
1634                 0x30d54, 0x30d74,
1635                 0x30d7c, 0x30d7c,
1636                 0x30de0, 0x30de0,
1637                 0x30e00, 0x30ed4,
1638                 0x30f00, 0x30fa4,
1639                 0x30fc0, 0x30fc4,
1640                 0x31000, 0x31004,
1641                 0x31080, 0x310fc,
1642                 0x31208, 0x31220,
1643                 0x3123c, 0x31254,
1644                 0x31300, 0x31300,
1645                 0x31308, 0x3131c,
1646                 0x31338, 0x3133c,
1647                 0x31380, 0x31380,
1648                 0x31388, 0x313a8,
1649                 0x313b4, 0x313b4,
1650                 0x31400, 0x31420,
1651                 0x31438, 0x3143c,
1652                 0x31480, 0x31480,
1653                 0x314a8, 0x314a8,
1654                 0x314b0, 0x314b4,
1655                 0x314c8, 0x314d4,
1656                 0x31a40, 0x31a4c,
1657                 0x31af0, 0x31b20,
1658                 0x31b38, 0x31b3c,
1659                 0x31b80, 0x31b80,
1660                 0x31ba8, 0x31ba8,
1661                 0x31bb0, 0x31bb4,
1662                 0x31bc8, 0x31bd4,
1663                 0x32140, 0x3218c,
1664                 0x321f0, 0x321f4,
1665                 0x32200, 0x32200,
1666                 0x32218, 0x32218,
1667                 0x32400, 0x32400,
1668                 0x32408, 0x3241c,
1669                 0x32618, 0x32620,
1670                 0x32664, 0x32664,
1671                 0x326a8, 0x326a8,
1672                 0x326ec, 0x326ec,
1673                 0x32a00, 0x32abc,
1674                 0x32b00, 0x32b38,
1675                 0x32b20, 0x32b38,
1676                 0x32b40, 0x32b58,
1677                 0x32b60, 0x32b78,
1678                 0x32c00, 0x32c00,
1679                 0x32c08, 0x32c3c,
1680                 0x33000, 0x3302c,
1681                 0x33034, 0x33050,
1682                 0x33058, 0x33058,
1683                 0x33060, 0x3308c,
1684                 0x3309c, 0x330ac,
1685                 0x330c0, 0x330c0,
1686                 0x330c8, 0x330d0,
1687                 0x330d8, 0x330e0,
1688                 0x330ec, 0x3312c,
1689                 0x33134, 0x33150,
1690                 0x33158, 0x33158,
1691                 0x33160, 0x3318c,
1692                 0x3319c, 0x331ac,
1693                 0x331c0, 0x331c0,
1694                 0x331c8, 0x331d0,
1695                 0x331d8, 0x331e0,
1696                 0x331ec, 0x33290,
1697                 0x33298, 0x332c4,
1698                 0x332e4, 0x33390,
1699                 0x33398, 0x333c4,
1700                 0x333e4, 0x3342c,
1701                 0x33434, 0x33450,
1702                 0x33458, 0x33458,
1703                 0x33460, 0x3348c,
1704                 0x3349c, 0x334ac,
1705                 0x334c0, 0x334c0,
1706                 0x334c8, 0x334d0,
1707                 0x334d8, 0x334e0,
1708                 0x334ec, 0x3352c,
1709                 0x33534, 0x33550,
1710                 0x33558, 0x33558,
1711                 0x33560, 0x3358c,
1712                 0x3359c, 0x335ac,
1713                 0x335c0, 0x335c0,
1714                 0x335c8, 0x335d0,
1715                 0x335d8, 0x335e0,
1716                 0x335ec, 0x33690,
1717                 0x33698, 0x336c4,
1718                 0x336e4, 0x33790,
1719                 0x33798, 0x337c4,
1720                 0x337e4, 0x337fc,
1721                 0x33814, 0x33814,
1722                 0x33854, 0x33868,
1723                 0x33880, 0x3388c,
1724                 0x338c0, 0x338d0,
1725                 0x338e8, 0x338ec,
1726                 0x33900, 0x3392c,
1727                 0x33934, 0x33950,
1728                 0x33958, 0x33958,
1729                 0x33960, 0x3398c,
1730                 0x3399c, 0x339ac,
1731                 0x339c0, 0x339c0,
1732                 0x339c8, 0x339d0,
1733                 0x339d8, 0x339e0,
1734                 0x339ec, 0x33a90,
1735                 0x33a98, 0x33ac4,
1736                 0x33ae4, 0x33b10,
1737                 0x33b24, 0x33b28,
1738                 0x33b38, 0x33b50,
1739                 0x33bf0, 0x33c10,
1740                 0x33c24, 0x33c28,
1741                 0x33c38, 0x33c50,
1742                 0x33cf0, 0x33cfc,
1743                 0x34000, 0x34030,
1744                 0x34100, 0x34168,
1745                 0x34190, 0x341a0,
1746                 0x341a8, 0x341b8,
1747                 0x341c4, 0x341c8,
1748                 0x341d0, 0x341d0,
1749                 0x34200, 0x34320,
1750                 0x34400, 0x344b4,
1751                 0x344c0, 0x3452c,
1752                 0x34540, 0x3461c,
1753                 0x34800, 0x348a0,
1754                 0x348c0, 0x34908,
1755                 0x34910, 0x349b8,
1756                 0x34a00, 0x34a04,
1757                 0x34a0c, 0x34a14,
1758                 0x34a1c, 0x34a2c,
1759                 0x34a44, 0x34a50,
1760                 0x34a74, 0x34a74,
1761                 0x34a7c, 0x34afc,
1762                 0x34b08, 0x34c24,
1763                 0x34d00, 0x34d14,
1764                 0x34d1c, 0x34d3c,
1765                 0x34d44, 0x34d4c,
1766                 0x34d54, 0x34d74,
1767                 0x34d7c, 0x34d7c,
1768                 0x34de0, 0x34de0,
1769                 0x34e00, 0x34ed4,
1770                 0x34f00, 0x34fa4,
1771                 0x34fc0, 0x34fc4,
1772                 0x35000, 0x35004,
1773                 0x35080, 0x350fc,
1774                 0x35208, 0x35220,
1775                 0x3523c, 0x35254,
1776                 0x35300, 0x35300,
1777                 0x35308, 0x3531c,
1778                 0x35338, 0x3533c,
1779                 0x35380, 0x35380,
1780                 0x35388, 0x353a8,
1781                 0x353b4, 0x353b4,
1782                 0x35400, 0x35420,
1783                 0x35438, 0x3543c,
1784                 0x35480, 0x35480,
1785                 0x354a8, 0x354a8,
1786                 0x354b0, 0x354b4,
1787                 0x354c8, 0x354d4,
1788                 0x35a40, 0x35a4c,
1789                 0x35af0, 0x35b20,
1790                 0x35b38, 0x35b3c,
1791                 0x35b80, 0x35b80,
1792                 0x35ba8, 0x35ba8,
1793                 0x35bb0, 0x35bb4,
1794                 0x35bc8, 0x35bd4,
1795                 0x36140, 0x3618c,
1796                 0x361f0, 0x361f4,
1797                 0x36200, 0x36200,
1798                 0x36218, 0x36218,
1799                 0x36400, 0x36400,
1800                 0x36408, 0x3641c,
1801                 0x36618, 0x36620,
1802                 0x36664, 0x36664,
1803                 0x366a8, 0x366a8,
1804                 0x366ec, 0x366ec,
1805                 0x36a00, 0x36abc,
1806                 0x36b00, 0x36b38,
1807                 0x36b20, 0x36b38,
1808                 0x36b40, 0x36b58,
1809                 0x36b60, 0x36b78,
1810                 0x36c00, 0x36c00,
1811                 0x36c08, 0x36c3c,
1812                 0x37000, 0x3702c,
1813                 0x37034, 0x37050,
1814                 0x37058, 0x37058,
1815                 0x37060, 0x3708c,
1816                 0x3709c, 0x370ac,
1817                 0x370c0, 0x370c0,
1818                 0x370c8, 0x370d0,
1819                 0x370d8, 0x370e0,
1820                 0x370ec, 0x3712c,
1821                 0x37134, 0x37150,
1822                 0x37158, 0x37158,
1823                 0x37160, 0x3718c,
1824                 0x3719c, 0x371ac,
1825                 0x371c0, 0x371c0,
1826                 0x371c8, 0x371d0,
1827                 0x371d8, 0x371e0,
1828                 0x371ec, 0x37290,
1829                 0x37298, 0x372c4,
1830                 0x372e4, 0x37390,
1831                 0x37398, 0x373c4,
1832                 0x373e4, 0x3742c,
1833                 0x37434, 0x37450,
1834                 0x37458, 0x37458,
1835                 0x37460, 0x3748c,
1836                 0x3749c, 0x374ac,
1837                 0x374c0, 0x374c0,
1838                 0x374c8, 0x374d0,
1839                 0x374d8, 0x374e0,
1840                 0x374ec, 0x3752c,
1841                 0x37534, 0x37550,
1842                 0x37558, 0x37558,
1843                 0x37560, 0x3758c,
1844                 0x3759c, 0x375ac,
1845                 0x375c0, 0x375c0,
1846                 0x375c8, 0x375d0,
1847                 0x375d8, 0x375e0,
1848                 0x375ec, 0x37690,
1849                 0x37698, 0x376c4,
1850                 0x376e4, 0x37790,
1851                 0x37798, 0x377c4,
1852                 0x377e4, 0x377fc,
1853                 0x37814, 0x37814,
1854                 0x37854, 0x37868,
1855                 0x37880, 0x3788c,
1856                 0x378c0, 0x378d0,
1857                 0x378e8, 0x378ec,
1858                 0x37900, 0x3792c,
1859                 0x37934, 0x37950,
1860                 0x37958, 0x37958,
1861                 0x37960, 0x3798c,
1862                 0x3799c, 0x379ac,
1863                 0x379c0, 0x379c0,
1864                 0x379c8, 0x379d0,
1865                 0x379d8, 0x379e0,
1866                 0x379ec, 0x37a90,
1867                 0x37a98, 0x37ac4,
1868                 0x37ae4, 0x37b10,
1869                 0x37b24, 0x37b28,
1870                 0x37b38, 0x37b50,
1871                 0x37bf0, 0x37c10,
1872                 0x37c24, 0x37c28,
1873                 0x37c38, 0x37c50,
1874                 0x37cf0, 0x37cfc,
1875                 0x40040, 0x40040,
1876                 0x40080, 0x40084,
1877                 0x40100, 0x40100,
1878                 0x40140, 0x401bc,
1879                 0x40200, 0x40214,
1880                 0x40228, 0x40228,
1881                 0x40240, 0x40258,
1882                 0x40280, 0x40280,
1883                 0x40304, 0x40304,
1884                 0x40330, 0x4033c,
1885                 0x41304, 0x413c8,
1886                 0x413d0, 0x413dc,
1887                 0x413f0, 0x413f0,
1888                 0x41400, 0x4140c,
1889                 0x41414, 0x4141c,
1890                 0x41480, 0x414d0,
1891                 0x44000, 0x4407c,
1892                 0x440c0, 0x441ac,
1893                 0x441b4, 0x4427c,
1894                 0x442c0, 0x443ac,
1895                 0x443b4, 0x4447c,
1896                 0x444c0, 0x445ac,
1897                 0x445b4, 0x4467c,
1898                 0x446c0, 0x447ac,
1899                 0x447b4, 0x4487c,
1900                 0x448c0, 0x449ac,
1901                 0x449b4, 0x44a7c,
1902                 0x44ac0, 0x44bac,
1903                 0x44bb4, 0x44c7c,
1904                 0x44cc0, 0x44dac,
1905                 0x44db4, 0x44e7c,
1906                 0x44ec0, 0x44fac,
1907                 0x44fb4, 0x4507c,
1908                 0x450c0, 0x451ac,
1909                 0x451b4, 0x451fc,
1910                 0x45800, 0x45804,
1911                 0x45810, 0x45830,
1912                 0x45840, 0x45860,
1913                 0x45868, 0x45868,
1914                 0x45880, 0x45884,
1915                 0x458a0, 0x458b0,
1916                 0x45a00, 0x45a04,
1917                 0x45a10, 0x45a30,
1918                 0x45a40, 0x45a60,
1919                 0x45a68, 0x45a68,
1920                 0x45a80, 0x45a84,
1921                 0x45aa0, 0x45ab0,
1922                 0x460c0, 0x460e4,
1923                 0x47000, 0x4703c,
1924                 0x47044, 0x4708c,
1925                 0x47200, 0x47250,
1926                 0x47400, 0x47408,
1927                 0x47414, 0x47420,
1928                 0x47600, 0x47618,
1929                 0x47800, 0x47814,
1930                 0x47820, 0x4782c,
1931                 0x50000, 0x50084,
1932                 0x50090, 0x500cc,
1933                 0x50300, 0x50384,
1934                 0x50400, 0x50400,
1935                 0x50800, 0x50884,
1936                 0x50890, 0x508cc,
1937                 0x50b00, 0x50b84,
1938                 0x50c00, 0x50c00,
1939                 0x51000, 0x51020,
1940                 0x51028, 0x510b0,
1941                 0x51300, 0x51324,
1942         };
1943
1944         u32 *buf_end = (u32 *)((char *)buf + buf_size);
1945         const unsigned int *reg_ranges;
1946         int reg_ranges_size, range;
1947         unsigned int chip_version = CHELSIO_CHIP_VERSION(adap->params.chip);
1948
1949         /* Select the right set of register ranges to dump depending on the
1950          * adapter chip type.
1951          */
1952         switch (chip_version) {
1953         case CHELSIO_T5:
1954                 reg_ranges = t5_reg_ranges;
1955                 reg_ranges_size = ARRAY_SIZE(t5_reg_ranges);
1956                 break;
1957
1958         case CHELSIO_T6:
1959                 reg_ranges = t6_reg_ranges;
1960                 reg_ranges_size = ARRAY_SIZE(t6_reg_ranges);
1961                 break;
1962
1963         default:
1964                 dev_err(adap,
1965                         "Unsupported chip version %d\n", chip_version);
1966                 return;
1967         }
1968
1969         /* Clear the register buffer and insert the appropriate register
1970          * values selected by the above register ranges.
1971          */
1972         memset(buf, 0, buf_size);
1973         for (range = 0; range < reg_ranges_size; range += 2) {
1974                 unsigned int reg = reg_ranges[range];
1975                 unsigned int last_reg = reg_ranges[range + 1];
1976                 u32 *bufp = (u32 *)((char *)buf + reg);
1977
1978                 /* Iterate across the register range filling in the register
1979                  * buffer but don't write past the end of the register buffer.
1980                  */
1981                 while (reg <= last_reg && bufp < buf_end) {
1982                         *bufp++ = t4_read_reg(adap, reg);
1983                         reg += sizeof(u32);
1984                 }
1985         }
1986 }
1987
1988 /* EEPROM reads take a few tens of us while writes can take a bit over 5 ms. */
1989 #define EEPROM_DELAY            10              /* 10us per poll spin */
1990 #define EEPROM_MAX_POLL         5000            /* x 5000 == 50ms */
1991
1992 #define EEPROM_STAT_ADDR        0x7bfc
1993
1994 /**
1995  * Small utility function to wait till any outstanding VPD Access is complete.
1996  * We have a per-adapter state variable "VPD Busy" to indicate when we have a
1997  * VPD Access in flight.  This allows us to handle the problem of having a
1998  * previous VPD Access time out and prevent an attempt to inject a new VPD
1999  * Request before any in-flight VPD request has completed.
2000  */
2001 static int t4_seeprom_wait(struct adapter *adapter)
2002 {
2003         unsigned int base = adapter->params.pci.vpd_cap_addr;
2004         int max_poll;
2005
2006         /* If no VPD Access is in flight, we can just return success right
2007          * away.
2008          */
2009         if (!adapter->vpd_busy)
2010                 return 0;
2011
2012         /* Poll the VPD Capability Address/Flag register waiting for it
2013          * to indicate that the operation is complete.
2014          */
2015         max_poll = EEPROM_MAX_POLL;
2016         do {
2017                 u16 val;
2018
2019                 udelay(EEPROM_DELAY);
2020                 t4_os_pci_read_cfg2(adapter, base + PCI_VPD_ADDR, &val);
2021
2022                 /* If the operation is complete, mark the VPD as no longer
2023                  * busy and return success.
2024                  */
2025                 if ((val & PCI_VPD_ADDR_F) == adapter->vpd_flag) {
2026                         adapter->vpd_busy = 0;
2027                         return 0;
2028                 }
2029         } while (--max_poll);
2030
2031         /* Failure!  Note that we leave the VPD Busy status set in order to
2032          * avoid pushing a new VPD Access request into the VPD Capability till
2033          * the current operation eventually succeeds.  It's a bug to issue a
2034          * new request when an existing request is in flight and will result
2035          * in corrupt hardware state.
2036          */
2037         return -ETIMEDOUT;
2038 }
2039
2040 /**
2041  * t4_seeprom_read - read a serial EEPROM location
2042  * @adapter: adapter to read
2043  * @addr: EEPROM virtual address
2044  * @data: where to store the read data
2045  *
2046  * Read a 32-bit word from a location in serial EEPROM using the card's PCI
2047  * VPD capability.  Note that this function must be called with a virtual
2048  * address.
2049  */
2050 int t4_seeprom_read(struct adapter *adapter, u32 addr, u32 *data)
2051 {
2052         unsigned int base = adapter->params.pci.vpd_cap_addr;
2053         int ret;
2054
2055         /* VPD Accesses must alway be 4-byte aligned!
2056          */
2057         if (addr >= EEPROMVSIZE || (addr & 3))
2058                 return -EINVAL;
2059
2060         /* Wait for any previous operation which may still be in flight to
2061          * complete.
2062          */
2063         ret = t4_seeprom_wait(adapter);
2064         if (ret) {
2065                 dev_err(adapter, "VPD still busy from previous operation\n");
2066                 return ret;
2067         }
2068
2069         /* Issue our new VPD Read request, mark the VPD as being busy and wait
2070          * for our request to complete.  If it doesn't complete, note the
2071          * error and return it to our caller.  Note that we do not reset the
2072          * VPD Busy status!
2073          */
2074         t4_os_pci_write_cfg2(adapter, base + PCI_VPD_ADDR, (u16)addr);
2075         adapter->vpd_busy = 1;
2076         adapter->vpd_flag = PCI_VPD_ADDR_F;
2077         ret = t4_seeprom_wait(adapter);
2078         if (ret) {
2079                 dev_err(adapter, "VPD read of address %#x failed\n", addr);
2080                 return ret;
2081         }
2082
2083         /* Grab the returned data, swizzle it into our endianness and
2084          * return success.
2085          */
2086         t4_os_pci_read_cfg4(adapter, base + PCI_VPD_DATA, data);
2087         *data = le32_to_cpu(*data);
2088         return 0;
2089 }
2090
2091 /**
2092  * t4_seeprom_write - write a serial EEPROM location
2093  * @adapter: adapter to write
2094  * @addr: virtual EEPROM address
2095  * @data: value to write
2096  *
2097  * Write a 32-bit word to a location in serial EEPROM using the card's PCI
2098  * VPD capability.  Note that this function must be called with a virtual
2099  * address.
2100  */
2101 int t4_seeprom_write(struct adapter *adapter, u32 addr, u32 data)
2102 {
2103         unsigned int base = adapter->params.pci.vpd_cap_addr;
2104         int ret;
2105         u32 stats_reg = 0;
2106         int max_poll;
2107
2108         /* VPD Accesses must alway be 4-byte aligned!
2109          */
2110         if (addr >= EEPROMVSIZE || (addr & 3))
2111                 return -EINVAL;
2112
2113         /* Wait for any previous operation which may still be in flight to
2114          * complete.
2115          */
2116         ret = t4_seeprom_wait(adapter);
2117         if (ret) {
2118                 dev_err(adapter, "VPD still busy from previous operation\n");
2119                 return ret;
2120         }
2121
2122         /* Issue our new VPD Read request, mark the VPD as being busy and wait
2123          * for our request to complete.  If it doesn't complete, note the
2124          * error and return it to our caller.  Note that we do not reset the
2125          * VPD Busy status!
2126          */
2127         t4_os_pci_write_cfg4(adapter, base + PCI_VPD_DATA,
2128                              cpu_to_le32(data));
2129         t4_os_pci_write_cfg2(adapter, base + PCI_VPD_ADDR,
2130                              (u16)addr | PCI_VPD_ADDR_F);
2131         adapter->vpd_busy = 1;
2132         adapter->vpd_flag = 0;
2133         ret = t4_seeprom_wait(adapter);
2134         if (ret) {
2135                 dev_err(adapter, "VPD write of address %#x failed\n", addr);
2136                 return ret;
2137         }
2138
2139         /* Reset PCI_VPD_DATA register after a transaction and wait for our
2140          * request to complete. If it doesn't complete, return error.
2141          */
2142         t4_os_pci_write_cfg4(adapter, base + PCI_VPD_DATA, 0);
2143         max_poll = EEPROM_MAX_POLL;
2144         do {
2145                 udelay(EEPROM_DELAY);
2146                 t4_seeprom_read(adapter, EEPROM_STAT_ADDR, &stats_reg);
2147         } while ((stats_reg & 0x1) && --max_poll);
2148         if (!max_poll)
2149                 return -ETIMEDOUT;
2150
2151         /* Return success! */
2152         return 0;
2153 }
2154
2155 /**
2156  * t4_seeprom_wp - enable/disable EEPROM write protection
2157  * @adapter: the adapter
2158  * @enable: whether to enable or disable write protection
2159  *
2160  * Enables or disables write protection on the serial EEPROM.
2161  */
2162 int t4_seeprom_wp(struct adapter *adapter, int enable)
2163 {
2164         return t4_seeprom_write(adapter, EEPROM_STAT_ADDR, enable ? 0xc : 0);
2165 }
2166
2167 /**
2168  * t4_config_rss_range - configure a portion of the RSS mapping table
2169  * @adapter: the adapter
2170  * @mbox: mbox to use for the FW command
2171  * @viid: virtual interface whose RSS subtable is to be written
2172  * @start: start entry in the table to write
2173  * @n: how many table entries to write
2174  * @rspq: values for the "response queue" (Ingress Queue) lookup table
2175  * @nrspq: number of values in @rspq
2176  *
2177  * Programs the selected part of the VI's RSS mapping table with the
2178  * provided values.  If @nrspq < @n the supplied values are used repeatedly
2179  * until the full table range is populated.
2180  *
2181  * The caller must ensure the values in @rspq are in the range allowed for
2182  * @viid.
2183  */
2184 int t4_config_rss_range(struct adapter *adapter, int mbox, unsigned int viid,
2185                         int start, int n, const u16 *rspq, unsigned int nrspq)
2186 {
2187         int ret;
2188         const u16 *rsp = rspq;
2189         const u16 *rsp_end = rspq + nrspq;
2190         struct fw_rss_ind_tbl_cmd cmd;
2191
2192         memset(&cmd, 0, sizeof(cmd));
2193         cmd.op_to_viid = cpu_to_be32(V_FW_CMD_OP(FW_RSS_IND_TBL_CMD) |
2194                                      F_FW_CMD_REQUEST | F_FW_CMD_WRITE |
2195                                      V_FW_RSS_IND_TBL_CMD_VIID(viid));
2196         cmd.retval_len16 = cpu_to_be32(FW_LEN16(cmd));
2197
2198         /*
2199          * Each firmware RSS command can accommodate up to 32 RSS Ingress
2200          * Queue Identifiers.  These Ingress Queue IDs are packed three to
2201          * a 32-bit word as 10-bit values with the upper remaining 2 bits
2202          * reserved.
2203          */
2204         while (n > 0) {
2205                 int nq = min(n, 32);
2206                 int nq_packed = 0;
2207                 __be32 *qp = &cmd.iq0_to_iq2;
2208
2209                 /*
2210                  * Set up the firmware RSS command header to send the next
2211                  * "nq" Ingress Queue IDs to the firmware.
2212                  */
2213                 cmd.niqid = cpu_to_be16(nq);
2214                 cmd.startidx = cpu_to_be16(start);
2215
2216                 /*
2217                  * "nq" more done for the start of the next loop.
2218                  */
2219                 start += nq;
2220                 n -= nq;
2221
2222                 /*
2223                  * While there are still Ingress Queue IDs to stuff into the
2224                  * current firmware RSS command, retrieve them from the
2225                  * Ingress Queue ID array and insert them into the command.
2226                  */
2227                 while (nq > 0) {
2228                         /*
2229                          * Grab up to the next 3 Ingress Queue IDs (wrapping
2230                          * around the Ingress Queue ID array if necessary) and
2231                          * insert them into the firmware RSS command at the
2232                          * current 3-tuple position within the commad.
2233                          */
2234                         u16 qbuf[3];
2235                         u16 *qbp = qbuf;
2236                         int nqbuf = min(3, nq);
2237
2238                         nq -= nqbuf;
2239                         qbuf[0] = 0;
2240                         qbuf[1] = 0;
2241                         qbuf[2] = 0;
2242                         while (nqbuf && nq_packed < 32) {
2243                                 nqbuf--;
2244                                 nq_packed++;
2245                                 *qbp++ = *rsp++;
2246                                 if (rsp >= rsp_end)
2247                                         rsp = rspq;
2248                         }
2249                         *qp++ = cpu_to_be32(V_FW_RSS_IND_TBL_CMD_IQ0(qbuf[0]) |
2250                                             V_FW_RSS_IND_TBL_CMD_IQ1(qbuf[1]) |
2251                                             V_FW_RSS_IND_TBL_CMD_IQ2(qbuf[2]));
2252                 }
2253
2254                 /*
2255                  * Send this portion of the RRS table update to the firmware;
2256                  * bail out on any errors.
2257                  */
2258                 ret = t4_wr_mbox(adapter, mbox, &cmd, sizeof(cmd), NULL);
2259                 if (ret)
2260                         return ret;
2261         }
2262
2263         return 0;
2264 }
2265
2266 /**
2267  * t4_config_vi_rss - configure per VI RSS settings
2268  * @adapter: the adapter
2269  * @mbox: mbox to use for the FW command
2270  * @viid: the VI id
2271  * @flags: RSS flags
2272  * @defq: id of the default RSS queue for the VI.
2273  *
2274  * Configures VI-specific RSS properties.
2275  */
2276 int t4_config_vi_rss(struct adapter *adapter, int mbox, unsigned int viid,
2277                      unsigned int flags, unsigned int defq)
2278 {
2279         struct fw_rss_vi_config_cmd c;
2280
2281         memset(&c, 0, sizeof(c));
2282         c.op_to_viid = cpu_to_be32(V_FW_CMD_OP(FW_RSS_VI_CONFIG_CMD) |
2283                                    F_FW_CMD_REQUEST | F_FW_CMD_WRITE |
2284                                    V_FW_RSS_VI_CONFIG_CMD_VIID(viid));
2285         c.retval_len16 = cpu_to_be32(FW_LEN16(c));
2286         c.u.basicvirtual.defaultq_to_udpen = cpu_to_be32(flags |
2287                         V_FW_RSS_VI_CONFIG_CMD_DEFAULTQ(defq));
2288         return t4_wr_mbox(adapter, mbox, &c, sizeof(c), NULL);
2289 }
2290
2291 /**
2292  * init_cong_ctrl - initialize congestion control parameters
2293  * @a: the alpha values for congestion control
2294  * @b: the beta values for congestion control
2295  *
2296  * Initialize the congestion control parameters.
2297  */
2298 static void init_cong_ctrl(unsigned short *a, unsigned short *b)
2299 {
2300         int i;
2301
2302         for (i = 0; i < 9; i++) {
2303                 a[i] = 1;
2304                 b[i] = 0;
2305         }
2306
2307         a[9] = 2;
2308         a[10] = 3;
2309         a[11] = 4;
2310         a[12] = 5;
2311         a[13] = 6;
2312         a[14] = 7;
2313         a[15] = 8;
2314         a[16] = 9;
2315         a[17] = 10;
2316         a[18] = 14;
2317         a[19] = 17;
2318         a[20] = 21;
2319         a[21] = 25;
2320         a[22] = 30;
2321         a[23] = 35;
2322         a[24] = 45;
2323         a[25] = 60;
2324         a[26] = 80;
2325         a[27] = 100;
2326         a[28] = 200;
2327         a[29] = 300;
2328         a[30] = 400;
2329         a[31] = 500;
2330
2331         b[9] = 1;
2332         b[10] = 1;
2333         b[11] = 2;
2334         b[12] = 2;
2335         b[13] = 3;
2336         b[14] = 3;
2337         b[15] = 3;
2338         b[16] = 3;
2339         b[17] = 4;
2340         b[18] = 4;
2341         b[19] = 4;
2342         b[20] = 4;
2343         b[21] = 4;
2344         b[22] = 5;
2345         b[23] = 5;
2346         b[24] = 5;
2347         b[25] = 5;
2348         b[26] = 5;
2349         b[27] = 5;
2350         b[28] = 6;
2351         b[29] = 6;
2352         b[30] = 7;
2353         b[31] = 7;
2354 }
2355
2356 #define INIT_CMD(var, cmd, rd_wr) do { \
2357         (var).op_to_write = cpu_to_be32(V_FW_CMD_OP(FW_##cmd##_CMD) | \
2358                         F_FW_CMD_REQUEST | F_FW_CMD_##rd_wr); \
2359         (var).retval_len16 = cpu_to_be32(FW_LEN16(var)); \
2360 } while (0)
2361
2362 int t4_get_core_clock(struct adapter *adapter, struct vpd_params *p)
2363 {
2364         u32 cclk_param, cclk_val;
2365         int ret;
2366
2367         /*
2368          * Ask firmware for the Core Clock since it knows how to translate the
2369          * Reference Clock ('V2') VPD field into a Core Clock value ...
2370          */
2371         cclk_param = (V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) |
2372                       V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_CCLK));
2373         ret = t4_query_params(adapter, adapter->mbox, adapter->pf, 0,
2374                               1, &cclk_param, &cclk_val);
2375         if (ret) {
2376                 dev_err(adapter, "%s: error in fetching from coreclock - %d\n",
2377                         __func__, ret);
2378                 return ret;
2379         }
2380
2381         p->cclk = cclk_val;
2382         dev_debug(adapter, "%s: p->cclk = %u\n", __func__, p->cclk);
2383         return 0;
2384 }
2385
2386 /* serial flash and firmware constants and flash config file constants */
2387 enum {
2388         SF_ATTEMPTS = 10,             /* max retries for SF operations */
2389
2390         /* flash command opcodes */
2391         SF_PROG_PAGE    = 2,          /* program page */
2392         SF_WR_DISABLE   = 4,          /* disable writes */
2393         SF_RD_STATUS    = 5,          /* read status register */
2394         SF_WR_ENABLE    = 6,          /* enable writes */
2395         SF_RD_DATA_FAST = 0xb,        /* read flash */
2396         SF_RD_ID        = 0x9f,       /* read ID */
2397         SF_ERASE_SECTOR = 0xd8,       /* erase sector */
2398 };
2399
2400 /**
2401  * sf1_read - read data from the serial flash
2402  * @adapter: the adapter
2403  * @byte_cnt: number of bytes to read
2404  * @cont: whether another operation will be chained
2405  * @lock: whether to lock SF for PL access only
2406  * @valp: where to store the read data
2407  *
2408  * Reads up to 4 bytes of data from the serial flash.  The location of
2409  * the read needs to be specified prior to calling this by issuing the
2410  * appropriate commands to the serial flash.
2411  */
2412 static int sf1_read(struct adapter *adapter, unsigned int byte_cnt, int cont,
2413                     int lock, u32 *valp)
2414 {
2415         int ret;
2416
2417         if (!byte_cnt || byte_cnt > 4)
2418                 return -EINVAL;
2419         if (t4_read_reg(adapter, A_SF_OP) & F_BUSY)
2420                 return -EBUSY;
2421         t4_write_reg(adapter, A_SF_OP,
2422                      V_SF_LOCK(lock) | V_CONT(cont) | V_BYTECNT(byte_cnt - 1));
2423         ret = t4_wait_op_done(adapter, A_SF_OP, F_BUSY, 0, SF_ATTEMPTS, 5);
2424         if (!ret)
2425                 *valp = t4_read_reg(adapter, A_SF_DATA);
2426         return ret;
2427 }
2428
2429 /**
2430  * sf1_write - write data to the serial flash
2431  * @adapter: the adapter
2432  * @byte_cnt: number of bytes to write
2433  * @cont: whether another operation will be chained
2434  * @lock: whether to lock SF for PL access only
2435  * @val: value to write
2436  *
2437  * Writes up to 4 bytes of data to the serial flash.  The location of
2438  * the write needs to be specified prior to calling this by issuing the
2439  * appropriate commands to the serial flash.
2440  */
2441 static int sf1_write(struct adapter *adapter, unsigned int byte_cnt, int cont,
2442                      int lock, u32 val)
2443 {
2444         if (!byte_cnt || byte_cnt > 4)
2445                 return -EINVAL;
2446         if (t4_read_reg(adapter, A_SF_OP) & F_BUSY)
2447                 return -EBUSY;
2448         t4_write_reg(adapter, A_SF_DATA, val);
2449         t4_write_reg(adapter, A_SF_OP, V_SF_LOCK(lock) |
2450                      V_CONT(cont) | V_BYTECNT(byte_cnt - 1) | V_OP(1));
2451         return t4_wait_op_done(adapter, A_SF_OP, F_BUSY, 0, SF_ATTEMPTS, 5);
2452 }
2453
2454 /**
2455  * t4_read_flash - read words from serial flash
2456  * @adapter: the adapter
2457  * @addr: the start address for the read
2458  * @nwords: how many 32-bit words to read
2459  * @data: where to store the read data
2460  * @byte_oriented: whether to store data as bytes or as words
2461  *
2462  * Read the specified number of 32-bit words from the serial flash.
2463  * If @byte_oriented is set the read data is stored as a byte array
2464  * (i.e., big-endian), otherwise as 32-bit words in the platform's
2465  * natural endianness.
2466  */
2467 int t4_read_flash(struct adapter *adapter, unsigned int addr,
2468                   unsigned int nwords, u32 *data, int byte_oriented)
2469 {
2470         int ret;
2471
2472         if (((addr + nwords * sizeof(u32)) > adapter->params.sf_size) ||
2473             (addr & 3))
2474                 return -EINVAL;
2475
2476         addr = rte_constant_bswap32(addr) | SF_RD_DATA_FAST;
2477
2478         ret = sf1_write(adapter, 4, 1, 0, addr);
2479         if (ret != 0)
2480                 return ret;
2481
2482         ret = sf1_read(adapter, 1, 1, 0, data);
2483         if (ret != 0)
2484                 return ret;
2485
2486         for ( ; nwords; nwords--, data++) {
2487                 ret = sf1_read(adapter, 4, nwords > 1, nwords == 1, data);
2488                 if (nwords == 1)
2489                         t4_write_reg(adapter, A_SF_OP, 0);    /* unlock SF */
2490                 if (ret)
2491                         return ret;
2492                 if (byte_oriented)
2493                         *data = cpu_to_be32(*data);
2494         }
2495         return 0;
2496 }
2497
2498 /**
2499  * t4_get_exprom_version - return the Expansion ROM version (if any)
2500  * @adapter: the adapter
2501  * @vers: where to place the version
2502  *
2503  * Reads the Expansion ROM header from FLASH and returns the version
2504  * number (if present) through the @vers return value pointer.  We return
2505  * this in the Firmware Version Format since it's convenient.  Return
2506  * 0 on success, -ENOENT if no Expansion ROM is present.
2507  */
2508 static int t4_get_exprom_version(struct adapter *adapter, u32 *vers)
2509 {
2510         struct exprom_header {
2511                 unsigned char hdr_arr[16];      /* must start with 0x55aa */
2512                 unsigned char hdr_ver[4];       /* Expansion ROM version */
2513         } *hdr;
2514         u32 exprom_header_buf[DIV_ROUND_UP(sizeof(struct exprom_header),
2515                                            sizeof(u32))];
2516         int ret;
2517
2518         ret = t4_read_flash(adapter, FLASH_EXP_ROM_START,
2519                             ARRAY_SIZE(exprom_header_buf),
2520                             exprom_header_buf, 0);
2521         if (ret)
2522                 return ret;
2523
2524         hdr = (struct exprom_header *)exprom_header_buf;
2525         if (hdr->hdr_arr[0] != 0x55 || hdr->hdr_arr[1] != 0xaa)
2526                 return -ENOENT;
2527
2528         *vers = (V_FW_HDR_FW_VER_MAJOR(hdr->hdr_ver[0]) |
2529                  V_FW_HDR_FW_VER_MINOR(hdr->hdr_ver[1]) |
2530                  V_FW_HDR_FW_VER_MICRO(hdr->hdr_ver[2]) |
2531                  V_FW_HDR_FW_VER_BUILD(hdr->hdr_ver[3]));
2532         return 0;
2533 }
2534
2535 /**
2536  * t4_get_fw_version - read the firmware version
2537  * @adapter: the adapter
2538  * @vers: where to place the version
2539  *
2540  * Reads the FW version from flash.
2541  */
2542 static int t4_get_fw_version(struct adapter *adapter, u32 *vers)
2543 {
2544         return t4_read_flash(adapter, FLASH_FW_START +
2545                              offsetof(struct fw_hdr, fw_ver), 1, vers, 0);
2546 }
2547
2548 /**
2549  *     t4_get_bs_version - read the firmware bootstrap version
2550  *     @adapter: the adapter
2551  *     @vers: where to place the version
2552  *
2553  *     Reads the FW Bootstrap version from flash.
2554  */
2555 static int t4_get_bs_version(struct adapter *adapter, u32 *vers)
2556 {
2557         return t4_read_flash(adapter, FLASH_FWBOOTSTRAP_START +
2558                              offsetof(struct fw_hdr, fw_ver), 1,
2559                              vers, 0);
2560 }
2561
2562 /**
2563  * t4_get_tp_version - read the TP microcode version
2564  * @adapter: the adapter
2565  * @vers: where to place the version
2566  *
2567  * Reads the TP microcode version from flash.
2568  */
2569 static int t4_get_tp_version(struct adapter *adapter, u32 *vers)
2570 {
2571         return t4_read_flash(adapter, FLASH_FW_START +
2572                              offsetof(struct fw_hdr, tp_microcode_ver),
2573                              1, vers, 0);
2574 }
2575
2576 /**
2577  * t4_get_version_info - extract various chip/firmware version information
2578  * @adapter: the adapter
2579  *
2580  * Reads various chip/firmware version numbers and stores them into the
2581  * adapter Adapter Parameters structure.  If any of the efforts fails
2582  * the first failure will be returned, but all of the version numbers
2583  * will be read.
2584  */
2585 int t4_get_version_info(struct adapter *adapter)
2586 {
2587         int ret = 0;
2588
2589 #define FIRST_RET(__getvinfo) \
2590         do { \
2591                 int __ret = __getvinfo; \
2592                 if (__ret && !ret) \
2593                         ret = __ret; \
2594         } while (0)
2595
2596         FIRST_RET(t4_get_fw_version(adapter, &adapter->params.fw_vers));
2597         FIRST_RET(t4_get_bs_version(adapter, &adapter->params.bs_vers));
2598         FIRST_RET(t4_get_tp_version(adapter, &adapter->params.tp_vers));
2599         FIRST_RET(t4_get_exprom_version(adapter, &adapter->params.er_vers));
2600
2601 #undef FIRST_RET
2602
2603         return ret;
2604 }
2605
2606 /**
2607  * t4_dump_version_info - dump all of the adapter configuration IDs
2608  * @adapter: the adapter
2609  *
2610  * Dumps all of the various bits of adapter configuration version/revision
2611  * IDs information.  This is typically called at some point after
2612  * t4_get_version_info() has been called.
2613  */
2614 void t4_dump_version_info(struct adapter *adapter)
2615 {
2616         /**
2617          * Device information.
2618          */
2619         dev_info(adapter, "Chelsio rev %d\n",
2620                  CHELSIO_CHIP_RELEASE(adapter->params.chip));
2621
2622         /**
2623          * Firmware Version.
2624          */
2625         if (!adapter->params.fw_vers)
2626                 dev_warn(adapter, "No firmware loaded\n");
2627         else
2628                 dev_info(adapter, "Firmware version: %u.%u.%u.%u\n",
2629                          G_FW_HDR_FW_VER_MAJOR(adapter->params.fw_vers),
2630                          G_FW_HDR_FW_VER_MINOR(adapter->params.fw_vers),
2631                          G_FW_HDR_FW_VER_MICRO(adapter->params.fw_vers),
2632                          G_FW_HDR_FW_VER_BUILD(adapter->params.fw_vers));
2633
2634         /**
2635          * Bootstrap Firmware Version.
2636          */
2637         if (!adapter->params.bs_vers)
2638                 dev_warn(adapter, "No bootstrap loaded\n");
2639         else
2640                 dev_info(adapter, "Bootstrap version: %u.%u.%u.%u\n",
2641                          G_FW_HDR_FW_VER_MAJOR(adapter->params.bs_vers),
2642                          G_FW_HDR_FW_VER_MINOR(adapter->params.bs_vers),
2643                          G_FW_HDR_FW_VER_MICRO(adapter->params.bs_vers),
2644                          G_FW_HDR_FW_VER_BUILD(adapter->params.bs_vers));
2645
2646         /**
2647          * TP Microcode Version.
2648          */
2649         if (!adapter->params.tp_vers)
2650                 dev_warn(adapter, "No TP Microcode loaded\n");
2651         else
2652                 dev_info(adapter, "TP Microcode version: %u.%u.%u.%u\n",
2653                          G_FW_HDR_FW_VER_MAJOR(adapter->params.tp_vers),
2654                          G_FW_HDR_FW_VER_MINOR(adapter->params.tp_vers),
2655                          G_FW_HDR_FW_VER_MICRO(adapter->params.tp_vers),
2656                          G_FW_HDR_FW_VER_BUILD(adapter->params.tp_vers));
2657
2658         /**
2659          * Expansion ROM version.
2660          */
2661         if (!adapter->params.er_vers)
2662                 dev_info(adapter, "No Expansion ROM loaded\n");
2663         else
2664                 dev_info(adapter, "Expansion ROM version: %u.%u.%u.%u\n",
2665                          G_FW_HDR_FW_VER_MAJOR(adapter->params.er_vers),
2666                          G_FW_HDR_FW_VER_MINOR(adapter->params.er_vers),
2667                          G_FW_HDR_FW_VER_MICRO(adapter->params.er_vers),
2668                          G_FW_HDR_FW_VER_BUILD(adapter->params.er_vers));
2669 }
2670
2671 #define ADVERT_MASK (V_FW_PORT_CAP_SPEED(M_FW_PORT_CAP_SPEED) | \
2672                      FW_PORT_CAP_ANEG)
2673
2674 /**
2675  * t4_link_l1cfg - apply link configuration to MAC/PHY
2676  * @phy: the PHY to setup
2677  * @mac: the MAC to setup
2678  * @lc: the requested link configuration
2679  *
2680  * Set up a port's MAC and PHY according to a desired link configuration.
2681  * - If the PHY can auto-negotiate first decide what to advertise, then
2682  *   enable/disable auto-negotiation as desired, and reset.
2683  * - If the PHY does not auto-negotiate just reset it.
2684  * - If auto-negotiation is off set the MAC to the proper speed/duplex/FC,
2685  *   otherwise do it later based on the outcome of auto-negotiation.
2686  */
2687 int t4_link_l1cfg(struct adapter *adap, unsigned int mbox, unsigned int port,
2688                   struct link_config *lc)
2689 {
2690         struct fw_port_cmd c;
2691         unsigned int mdi = V_FW_PORT_CAP_MDI(FW_PORT_CAP_MDI_AUTO);
2692         unsigned int fc, fec;
2693
2694         lc->link_ok = 0;
2695         fc = 0;
2696         if (lc->requested_fc & PAUSE_RX)
2697                 fc |= FW_PORT_CAP_FC_RX;
2698         if (lc->requested_fc & PAUSE_TX)
2699                 fc |= FW_PORT_CAP_FC_TX;
2700
2701         fec = 0;
2702         if (lc->requested_fec & FEC_RS)
2703                 fec |= FW_PORT_CAP_FEC_RS;
2704         if (lc->requested_fec & FEC_BASER_RS)
2705                 fec |= FW_PORT_CAP_FEC_BASER_RS;
2706         if (lc->requested_fec & FEC_RESERVED)
2707                 fec |= FW_PORT_CAP_FEC_RESERVED;
2708
2709         memset(&c, 0, sizeof(c));
2710         c.op_to_portid = cpu_to_be32(V_FW_CMD_OP(FW_PORT_CMD) |
2711                                      F_FW_CMD_REQUEST | F_FW_CMD_EXEC |
2712                                      V_FW_PORT_CMD_PORTID(port));
2713         c.action_to_len16 =
2714                 cpu_to_be32(V_FW_PORT_CMD_ACTION(FW_PORT_ACTION_L1_CFG) |
2715                             FW_LEN16(c));
2716
2717         if (!(lc->supported & FW_PORT_CAP_ANEG)) {
2718                 c.u.l1cfg.rcap = cpu_to_be32((lc->supported & ADVERT_MASK) |
2719                                              fc | fec);
2720                 lc->fc = lc->requested_fc & ~PAUSE_AUTONEG;
2721                 lc->fec = lc->requested_fec;
2722         } else if (lc->autoneg == AUTONEG_DISABLE) {
2723                 c.u.l1cfg.rcap = cpu_to_be32(lc->requested_speed | fc |
2724                                              fec | mdi);
2725                 lc->fc = lc->requested_fc & ~PAUSE_AUTONEG;
2726                 lc->fec = lc->requested_fec;
2727         } else {
2728                 c.u.l1cfg.rcap = cpu_to_be32(lc->advertising | fc | fec | mdi);
2729         }
2730
2731         return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
2732 }
2733
2734 /**
2735  * t4_flash_cfg_addr - return the address of the flash configuration file
2736  * @adapter: the adapter
2737  *
2738  * Return the address within the flash where the Firmware Configuration
2739  * File is stored, or an error if the device FLASH is too small to contain
2740  * a Firmware Configuration File.
2741  */
2742 int t4_flash_cfg_addr(struct adapter *adapter)
2743 {
2744         /*
2745          * If the device FLASH isn't large enough to hold a Firmware
2746          * Configuration File, return an error.
2747          */
2748         if (adapter->params.sf_size < FLASH_CFG_START + FLASH_CFG_MAX_SIZE)
2749                 return -ENOSPC;
2750
2751         return FLASH_CFG_START;
2752 }
2753
2754 #define PF_INTR_MASK (F_PFSW | F_PFCIM)
2755
2756 /**
2757  * t4_intr_enable - enable interrupts
2758  * @adapter: the adapter whose interrupts should be enabled
2759  *
2760  * Enable PF-specific interrupts for the calling function and the top-level
2761  * interrupt concentrator for global interrupts.  Interrupts are already
2762  * enabled at each module, here we just enable the roots of the interrupt
2763  * hierarchies.
2764  *
2765  * Note: this function should be called only when the driver manages
2766  * non PF-specific interrupts from the various HW modules.  Only one PCI
2767  * function at a time should be doing this.
2768  */
2769 void t4_intr_enable(struct adapter *adapter)
2770 {
2771         u32 val = 0;
2772         u32 whoami = t4_read_reg(adapter, A_PL_WHOAMI);
2773         u32 pf = CHELSIO_CHIP_VERSION(adapter->params.chip) <= CHELSIO_T5 ?
2774                  G_SOURCEPF(whoami) : G_T6_SOURCEPF(whoami);
2775
2776         if (CHELSIO_CHIP_VERSION(adapter->params.chip) <= CHELSIO_T5)
2777                 val = F_ERR_DROPPED_DB | F_ERR_EGR_CTXT_PRIO | F_DBFIFO_HP_INT;
2778         t4_write_reg(adapter, A_SGE_INT_ENABLE3, F_ERR_CPL_EXCEED_IQE_SIZE |
2779                      F_ERR_INVALID_CIDX_INC | F_ERR_CPL_OPCODE_0 |
2780                      F_ERR_DATA_CPL_ON_HIGH_QID1 | F_INGRESS_SIZE_ERR |
2781                      F_ERR_DATA_CPL_ON_HIGH_QID0 | F_ERR_BAD_DB_PIDX3 |
2782                      F_ERR_BAD_DB_PIDX2 | F_ERR_BAD_DB_PIDX1 |
2783                      F_ERR_BAD_DB_PIDX0 | F_ERR_ING_CTXT_PRIO |
2784                      F_DBFIFO_LP_INT | F_EGRESS_SIZE_ERR | val);
2785         t4_write_reg(adapter, MYPF_REG(A_PL_PF_INT_ENABLE), PF_INTR_MASK);
2786         t4_set_reg_field(adapter, A_PL_INT_MAP0, 0, 1 << pf);
2787 }
2788
2789 /**
2790  * t4_intr_disable - disable interrupts
2791  * @adapter: the adapter whose interrupts should be disabled
2792  *
2793  * Disable interrupts.  We only disable the top-level interrupt
2794  * concentrators.  The caller must be a PCI function managing global
2795  * interrupts.
2796  */
2797 void t4_intr_disable(struct adapter *adapter)
2798 {
2799         u32 whoami = t4_read_reg(adapter, A_PL_WHOAMI);
2800         u32 pf = CHELSIO_CHIP_VERSION(adapter->params.chip) <= CHELSIO_T5 ?
2801                  G_SOURCEPF(whoami) : G_T6_SOURCEPF(whoami);
2802
2803         t4_write_reg(adapter, MYPF_REG(A_PL_PF_INT_ENABLE), 0);
2804         t4_set_reg_field(adapter, A_PL_INT_MAP0, 1 << pf, 0);
2805 }
2806
2807 /**
2808  * t4_get_port_type_description - return Port Type string description
2809  * @port_type: firmware Port Type enumeration
2810  */
2811 const char *t4_get_port_type_description(enum fw_port_type port_type)
2812 {
2813         static const char * const port_type_description[] = {
2814                 "Fiber_XFI",
2815                 "Fiber_XAUI",
2816                 "BT_SGMII",
2817                 "BT_XFI",
2818                 "BT_XAUI",
2819                 "KX4",
2820                 "CX4",
2821                 "KX",
2822                 "KR",
2823                 "SFP",
2824                 "BP_AP",
2825                 "BP4_AP",
2826                 "QSFP_10G",
2827                 "QSA",
2828                 "QSFP",
2829                 "BP40_BA",
2830                 "KR4_100G",
2831                 "CR4_QSFP",
2832                 "CR_QSFP",
2833                 "CR2_QSFP",
2834                 "SFP28",
2835                 "KR_SFP28",
2836         };
2837
2838         if (port_type < ARRAY_SIZE(port_type_description))
2839                 return port_type_description[port_type];
2840         return "UNKNOWN";
2841 }
2842
2843 /**
2844  * t4_get_mps_bg_map - return the buffer groups associated with a port
2845  * @adap: the adapter
2846  * @pidx: the port index
2847  *
2848  * Returns a bitmap indicating which MPS buffer groups are associated
2849  * with the given port.  Bit i is set if buffer group i is used by the
2850  * port.
2851  */
2852 unsigned int t4_get_mps_bg_map(struct adapter *adap, unsigned int pidx)
2853 {
2854         unsigned int chip_version = CHELSIO_CHIP_VERSION(adap->params.chip);
2855         unsigned int nports = 1 << G_NUMPORTS(t4_read_reg(adap,
2856                                                           A_MPS_CMN_CTL));
2857
2858         if (pidx >= nports) {
2859                 dev_warn(adap, "MPS Port Index %d >= Nports %d\n",
2860                          pidx, nports);
2861                 return 0;
2862         }
2863
2864         switch (chip_version) {
2865         case CHELSIO_T4:
2866         case CHELSIO_T5:
2867                 switch (nports) {
2868                 case 1: return 0xf;
2869                 case 2: return 3 << (2 * pidx);
2870                 case 4: return 1 << pidx;
2871                 }
2872                 break;
2873
2874         case CHELSIO_T6:
2875                 switch (nports) {
2876                 case 2: return 1 << (2 * pidx);
2877                 }
2878                 break;
2879         }
2880
2881         dev_err(adap, "Need MPS Buffer Group Map for Chip %0x, Nports %d\n",
2882                 chip_version, nports);
2883         return 0;
2884 }
2885
2886 /**
2887  * t4_get_tp_ch_map - return TP ingress channels associated with a port
2888  * @adapter: the adapter
2889  * @pidx: the port index
2890  *
2891  * Returns a bitmap indicating which TP Ingress Channels are associated with
2892  * a given Port.  Bit i is set if TP Ingress Channel i is used by the Port.
2893  */
2894 unsigned int t4_get_tp_ch_map(struct adapter *adapter, unsigned int pidx)
2895 {
2896         unsigned int chip_version = CHELSIO_CHIP_VERSION(adapter->params.chip);
2897         unsigned int nports = 1 << G_NUMPORTS(t4_read_reg(adapter,
2898                                                           A_MPS_CMN_CTL));
2899
2900         if (pidx >= nports) {
2901                 dev_warn(adap, "TP Port Index %d >= Nports %d\n",
2902                          pidx, nports);
2903                 return 0;
2904         }
2905
2906         switch (chip_version) {
2907         case CHELSIO_T4:
2908         case CHELSIO_T5:
2909                 /* Note that this happens to be the same values as the MPS
2910                  * Buffer Group Map for these Chips.  But we replicate the code
2911                  * here because they're really separate concepts.
2912                  */
2913                 switch (nports) {
2914                 case 1: return 0xf;
2915                 case 2: return 3 << (2 * pidx);
2916                 case 4: return 1 << pidx;
2917                 }
2918                 break;
2919
2920         case CHELSIO_T6:
2921                 switch (nports) {
2922                 case 2: return 1 << pidx;
2923                 }
2924                 break;
2925         }
2926
2927         dev_err(adapter, "Need TP Channel Map for Chip %0x, Nports %d\n",
2928                 chip_version, nports);
2929         return 0;
2930 }
2931
2932 /**
2933  * t4_get_port_stats - collect port statistics
2934  * @adap: the adapter
2935  * @idx: the port index
2936  * @p: the stats structure to fill
2937  *
2938  * Collect statistics related to the given port from HW.
2939  */
2940 void t4_get_port_stats(struct adapter *adap, int idx, struct port_stats *p)
2941 {
2942         u32 bgmap = t4_get_mps_bg_map(adap, idx);
2943         u32 stat_ctl = t4_read_reg(adap, A_MPS_STAT_CTL);
2944
2945 #define GET_STAT(name) \
2946         t4_read_reg64(adap, \
2947                       (is_t4(adap->params.chip) ? \
2948                        PORT_REG(idx, A_MPS_PORT_STAT_##name##_L) :\
2949                        T5_PORT_REG(idx, A_MPS_PORT_STAT_##name##_L)))
2950 #define GET_STAT_COM(name) t4_read_reg64(adap, A_MPS_STAT_##name##_L)
2951
2952         p->tx_octets           = GET_STAT(TX_PORT_BYTES);
2953         p->tx_frames           = GET_STAT(TX_PORT_FRAMES);
2954         p->tx_bcast_frames     = GET_STAT(TX_PORT_BCAST);
2955         p->tx_mcast_frames     = GET_STAT(TX_PORT_MCAST);
2956         p->tx_ucast_frames     = GET_STAT(TX_PORT_UCAST);
2957         p->tx_error_frames     = GET_STAT(TX_PORT_ERROR);
2958         p->tx_frames_64        = GET_STAT(TX_PORT_64B);
2959         p->tx_frames_65_127    = GET_STAT(TX_PORT_65B_127B);
2960         p->tx_frames_128_255   = GET_STAT(TX_PORT_128B_255B);
2961         p->tx_frames_256_511   = GET_STAT(TX_PORT_256B_511B);
2962         p->tx_frames_512_1023  = GET_STAT(TX_PORT_512B_1023B);
2963         p->tx_frames_1024_1518 = GET_STAT(TX_PORT_1024B_1518B);
2964         p->tx_frames_1519_max  = GET_STAT(TX_PORT_1519B_MAX);
2965         p->tx_drop             = GET_STAT(TX_PORT_DROP);
2966         p->tx_pause            = GET_STAT(TX_PORT_PAUSE);
2967         p->tx_ppp0             = GET_STAT(TX_PORT_PPP0);
2968         p->tx_ppp1             = GET_STAT(TX_PORT_PPP1);
2969         p->tx_ppp2             = GET_STAT(TX_PORT_PPP2);
2970         p->tx_ppp3             = GET_STAT(TX_PORT_PPP3);
2971         p->tx_ppp4             = GET_STAT(TX_PORT_PPP4);
2972         p->tx_ppp5             = GET_STAT(TX_PORT_PPP5);
2973         p->tx_ppp6             = GET_STAT(TX_PORT_PPP6);
2974         p->tx_ppp7             = GET_STAT(TX_PORT_PPP7);
2975
2976         if (CHELSIO_CHIP_VERSION(adap->params.chip) >= CHELSIO_T5) {
2977                 if (stat_ctl & F_COUNTPAUSESTATTX) {
2978                         p->tx_frames -= p->tx_pause;
2979                         p->tx_octets -= p->tx_pause * 64;
2980                 }
2981                 if (stat_ctl & F_COUNTPAUSEMCTX)
2982                         p->tx_mcast_frames -= p->tx_pause;
2983         }
2984
2985         p->rx_octets           = GET_STAT(RX_PORT_BYTES);
2986         p->rx_frames           = GET_STAT(RX_PORT_FRAMES);
2987         p->rx_bcast_frames     = GET_STAT(RX_PORT_BCAST);
2988         p->rx_mcast_frames     = GET_STAT(RX_PORT_MCAST);
2989         p->rx_ucast_frames     = GET_STAT(RX_PORT_UCAST);
2990         p->rx_too_long         = GET_STAT(RX_PORT_MTU_ERROR);
2991         p->rx_jabber           = GET_STAT(RX_PORT_MTU_CRC_ERROR);
2992         p->rx_fcs_err          = GET_STAT(RX_PORT_CRC_ERROR);
2993         p->rx_len_err          = GET_STAT(RX_PORT_LEN_ERROR);
2994         p->rx_symbol_err       = GET_STAT(RX_PORT_SYM_ERROR);
2995         p->rx_runt             = GET_STAT(RX_PORT_LESS_64B);
2996         p->rx_frames_64        = GET_STAT(RX_PORT_64B);
2997         p->rx_frames_65_127    = GET_STAT(RX_PORT_65B_127B);
2998         p->rx_frames_128_255   = GET_STAT(RX_PORT_128B_255B);
2999         p->rx_frames_256_511   = GET_STAT(RX_PORT_256B_511B);
3000         p->rx_frames_512_1023  = GET_STAT(RX_PORT_512B_1023B);
3001         p->rx_frames_1024_1518 = GET_STAT(RX_PORT_1024B_1518B);
3002         p->rx_frames_1519_max  = GET_STAT(RX_PORT_1519B_MAX);
3003         p->rx_pause            = GET_STAT(RX_PORT_PAUSE);
3004         p->rx_ppp0             = GET_STAT(RX_PORT_PPP0);
3005         p->rx_ppp1             = GET_STAT(RX_PORT_PPP1);
3006         p->rx_ppp2             = GET_STAT(RX_PORT_PPP2);
3007         p->rx_ppp3             = GET_STAT(RX_PORT_PPP3);
3008         p->rx_ppp4             = GET_STAT(RX_PORT_PPP4);
3009         p->rx_ppp5             = GET_STAT(RX_PORT_PPP5);
3010         p->rx_ppp6             = GET_STAT(RX_PORT_PPP6);
3011         p->rx_ppp7             = GET_STAT(RX_PORT_PPP7);
3012
3013         if (CHELSIO_CHIP_VERSION(adap->params.chip) >= CHELSIO_T5) {
3014                 if (stat_ctl & F_COUNTPAUSESTATRX) {
3015                         p->rx_frames -= p->rx_pause;
3016                         p->rx_octets -= p->rx_pause * 64;
3017                 }
3018                 if (stat_ctl & F_COUNTPAUSEMCRX)
3019                         p->rx_mcast_frames -= p->rx_pause;
3020         }
3021
3022         p->rx_ovflow0 = (bgmap & 1) ? GET_STAT_COM(RX_BG_0_MAC_DROP_FRAME) : 0;
3023         p->rx_ovflow1 = (bgmap & 2) ? GET_STAT_COM(RX_BG_1_MAC_DROP_FRAME) : 0;
3024         p->rx_ovflow2 = (bgmap & 4) ? GET_STAT_COM(RX_BG_2_MAC_DROP_FRAME) : 0;
3025         p->rx_ovflow3 = (bgmap & 8) ? GET_STAT_COM(RX_BG_3_MAC_DROP_FRAME) : 0;
3026         p->rx_trunc0 = (bgmap & 1) ? GET_STAT_COM(RX_BG_0_MAC_TRUNC_FRAME) : 0;
3027         p->rx_trunc1 = (bgmap & 2) ? GET_STAT_COM(RX_BG_1_MAC_TRUNC_FRAME) : 0;
3028         p->rx_trunc2 = (bgmap & 4) ? GET_STAT_COM(RX_BG_2_MAC_TRUNC_FRAME) : 0;
3029         p->rx_trunc3 = (bgmap & 8) ? GET_STAT_COM(RX_BG_3_MAC_TRUNC_FRAME) : 0;
3030
3031 #undef GET_STAT
3032 #undef GET_STAT_COM
3033 }
3034
3035 /**
3036  * t4_get_port_stats_offset - collect port stats relative to a previous snapshot
3037  * @adap: The adapter
3038  * @idx: The port
3039  * @stats: Current stats to fill
3040  * @offset: Previous stats snapshot
3041  */
3042 void t4_get_port_stats_offset(struct adapter *adap, int idx,
3043                               struct port_stats *stats,
3044                               struct port_stats *offset)
3045 {
3046         u64 *s, *o;
3047         unsigned int i;
3048
3049         t4_get_port_stats(adap, idx, stats);
3050         for (i = 0, s = (u64 *)stats, o = (u64 *)offset;
3051              i < (sizeof(struct port_stats) / sizeof(u64));
3052              i++, s++, o++)
3053                 *s -= *o;
3054 }
3055
3056 /**
3057  * t4_clr_port_stats - clear port statistics
3058  * @adap: the adapter
3059  * @idx: the port index
3060  *
3061  * Clear HW statistics for the given port.
3062  */
3063 void t4_clr_port_stats(struct adapter *adap, int idx)
3064 {
3065         unsigned int i;
3066         u32 bgmap = t4_get_mps_bg_map(adap, idx);
3067         u32 port_base_addr;
3068
3069         if (is_t4(adap->params.chip))
3070                 port_base_addr = PORT_BASE(idx);
3071         else
3072                 port_base_addr = T5_PORT_BASE(idx);
3073
3074         for (i = A_MPS_PORT_STAT_TX_PORT_BYTES_L;
3075              i <= A_MPS_PORT_STAT_TX_PORT_PPP7_H; i += 8)
3076                 t4_write_reg(adap, port_base_addr + i, 0);
3077         for (i = A_MPS_PORT_STAT_RX_PORT_BYTES_L;
3078              i <= A_MPS_PORT_STAT_RX_PORT_LESS_64B_H; i += 8)
3079                 t4_write_reg(adap, port_base_addr + i, 0);
3080         for (i = 0; i < 4; i++)
3081                 if (bgmap & (1 << i)) {
3082                         t4_write_reg(adap,
3083                                      A_MPS_STAT_RX_BG_0_MAC_DROP_FRAME_L +
3084                                      i * 8, 0);
3085                         t4_write_reg(adap,
3086                                      A_MPS_STAT_RX_BG_0_MAC_TRUNC_FRAME_L +
3087                                      i * 8, 0);
3088                 }
3089 }
3090
3091 /**
3092  * t4_fw_hello - establish communication with FW
3093  * @adap: the adapter
3094  * @mbox: mailbox to use for the FW command
3095  * @evt_mbox: mailbox to receive async FW events
3096  * @master: specifies the caller's willingness to be the device master
3097  * @state: returns the current device state (if non-NULL)
3098  *
3099  * Issues a command to establish communication with FW.  Returns either
3100  * an error (negative integer) or the mailbox of the Master PF.
3101  */
3102 int t4_fw_hello(struct adapter *adap, unsigned int mbox, unsigned int evt_mbox,
3103                 enum dev_master master, enum dev_state *state)
3104 {
3105         int ret;
3106         struct fw_hello_cmd c;
3107         u32 v;
3108         unsigned int master_mbox;
3109         int retries = FW_CMD_HELLO_RETRIES;
3110
3111 retry:
3112         memset(&c, 0, sizeof(c));
3113         INIT_CMD(c, HELLO, WRITE);
3114         c.err_to_clearinit = cpu_to_be32(
3115                         V_FW_HELLO_CMD_MASTERDIS(master == MASTER_CANT) |
3116                         V_FW_HELLO_CMD_MASTERFORCE(master == MASTER_MUST) |
3117                         V_FW_HELLO_CMD_MBMASTER(master == MASTER_MUST ? mbox :
3118                                                 M_FW_HELLO_CMD_MBMASTER) |
3119                         V_FW_HELLO_CMD_MBASYNCNOT(evt_mbox) |
3120                         V_FW_HELLO_CMD_STAGE(FW_HELLO_CMD_STAGE_OS) |
3121                         F_FW_HELLO_CMD_CLEARINIT);
3122
3123         /*
3124          * Issue the HELLO command to the firmware.  If it's not successful
3125          * but indicates that we got a "busy" or "timeout" condition, retry
3126          * the HELLO until we exhaust our retry limit.  If we do exceed our
3127          * retry limit, check to see if the firmware left us any error
3128          * information and report that if so ...
3129          */
3130         ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
3131         if (ret != FW_SUCCESS) {
3132                 if ((ret == -EBUSY || ret == -ETIMEDOUT) && retries-- > 0)
3133                         goto retry;
3134                 if (t4_read_reg(adap, A_PCIE_FW) & F_PCIE_FW_ERR)
3135                         t4_report_fw_error(adap);
3136                 return ret;
3137         }
3138
3139         v = be32_to_cpu(c.err_to_clearinit);
3140         master_mbox = G_FW_HELLO_CMD_MBMASTER(v);
3141         if (state) {
3142                 if (v & F_FW_HELLO_CMD_ERR)
3143                         *state = DEV_STATE_ERR;
3144                 else if (v & F_FW_HELLO_CMD_INIT)
3145                         *state = DEV_STATE_INIT;
3146                 else
3147                         *state = DEV_STATE_UNINIT;
3148         }
3149
3150         /*
3151          * If we're not the Master PF then we need to wait around for the
3152          * Master PF Driver to finish setting up the adapter.
3153          *
3154          * Note that we also do this wait if we're a non-Master-capable PF and
3155          * there is no current Master PF; a Master PF may show up momentarily
3156          * and we wouldn't want to fail pointlessly.  (This can happen when an
3157          * OS loads lots of different drivers rapidly at the same time).  In
3158          * this case, the Master PF returned by the firmware will be
3159          * M_PCIE_FW_MASTER so the test below will work ...
3160          */
3161         if ((v & (F_FW_HELLO_CMD_ERR | F_FW_HELLO_CMD_INIT)) == 0 &&
3162             master_mbox != mbox) {
3163                 int waiting = FW_CMD_HELLO_TIMEOUT;
3164
3165                 /*
3166                  * Wait for the firmware to either indicate an error or
3167                  * initialized state.  If we see either of these we bail out
3168                  * and report the issue to the caller.  If we exhaust the
3169                  * "hello timeout" and we haven't exhausted our retries, try
3170                  * again.  Otherwise bail with a timeout error.
3171                  */
3172                 for (;;) {
3173                         u32 pcie_fw;
3174
3175                         msleep(50);
3176                         waiting -= 50;
3177
3178                         /*
3179                          * If neither Error nor Initialialized are indicated
3180                          * by the firmware keep waiting till we exaust our
3181                          * timeout ... and then retry if we haven't exhausted
3182                          * our retries ...
3183                          */
3184                         pcie_fw = t4_read_reg(adap, A_PCIE_FW);
3185                         if (!(pcie_fw & (F_PCIE_FW_ERR | F_PCIE_FW_INIT))) {
3186                                 if (waiting <= 0) {
3187                                         if (retries-- > 0)
3188                                                 goto retry;
3189
3190                                         return -ETIMEDOUT;
3191                                 }
3192                                 continue;
3193                         }
3194
3195                         /*
3196                          * We either have an Error or Initialized condition
3197                          * report errors preferentially.
3198                          */
3199                         if (state) {
3200                                 if (pcie_fw & F_PCIE_FW_ERR)
3201                                         *state = DEV_STATE_ERR;
3202                                 else if (pcie_fw & F_PCIE_FW_INIT)
3203                                         *state = DEV_STATE_INIT;
3204                         }
3205
3206                         /*
3207                          * If we arrived before a Master PF was selected and
3208                          * there's not a valid Master PF, grab its identity
3209                          * for our caller.
3210                          */
3211                         if (master_mbox == M_PCIE_FW_MASTER &&
3212                             (pcie_fw & F_PCIE_FW_MASTER_VLD))
3213                                 master_mbox = G_PCIE_FW_MASTER(pcie_fw);
3214                         break;
3215                 }
3216         }
3217
3218         return master_mbox;
3219 }
3220
3221 /**
3222  * t4_fw_bye - end communication with FW
3223  * @adap: the adapter
3224  * @mbox: mailbox to use for the FW command
3225  *
3226  * Issues a command to terminate communication with FW.
3227  */
3228 int t4_fw_bye(struct adapter *adap, unsigned int mbox)
3229 {
3230         struct fw_bye_cmd c;
3231
3232         memset(&c, 0, sizeof(c));
3233         INIT_CMD(c, BYE, WRITE);
3234         return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
3235 }
3236
3237 /**
3238  * t4_fw_reset - issue a reset to FW
3239  * @adap: the adapter
3240  * @mbox: mailbox to use for the FW command
3241  * @reset: specifies the type of reset to perform
3242  *
3243  * Issues a reset command of the specified type to FW.
3244  */
3245 int t4_fw_reset(struct adapter *adap, unsigned int mbox, int reset)
3246 {
3247         struct fw_reset_cmd c;
3248
3249         memset(&c, 0, sizeof(c));
3250         INIT_CMD(c, RESET, WRITE);
3251         c.val = cpu_to_be32(reset);
3252         return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
3253 }
3254
3255 /**
3256  * t4_fw_halt - issue a reset/halt to FW and put uP into RESET
3257  * @adap: the adapter
3258  * @mbox: mailbox to use for the FW RESET command (if desired)
3259  * @force: force uP into RESET even if FW RESET command fails
3260  *
3261  * Issues a RESET command to firmware (if desired) with a HALT indication
3262  * and then puts the microprocessor into RESET state.  The RESET command
3263  * will only be issued if a legitimate mailbox is provided (mbox <=
3264  * M_PCIE_FW_MASTER).
3265  *
3266  * This is generally used in order for the host to safely manipulate the
3267  * adapter without fear of conflicting with whatever the firmware might
3268  * be doing.  The only way out of this state is to RESTART the firmware
3269  * ...
3270  */
3271 int t4_fw_halt(struct adapter *adap, unsigned int mbox, int force)
3272 {
3273         int ret = 0;
3274
3275         /*
3276          * If a legitimate mailbox is provided, issue a RESET command
3277          * with a HALT indication.
3278          */
3279         if (mbox <= M_PCIE_FW_MASTER) {
3280                 struct fw_reset_cmd c;
3281
3282                 memset(&c, 0, sizeof(c));
3283                 INIT_CMD(c, RESET, WRITE);
3284                 c.val = cpu_to_be32(F_PIORST | F_PIORSTMODE);
3285                 c.halt_pkd = cpu_to_be32(F_FW_RESET_CMD_HALT);
3286                 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
3287         }
3288
3289         /*
3290          * Normally we won't complete the operation if the firmware RESET
3291          * command fails but if our caller insists we'll go ahead and put the
3292          * uP into RESET.  This can be useful if the firmware is hung or even
3293          * missing ...  We'll have to take the risk of putting the uP into
3294          * RESET without the cooperation of firmware in that case.
3295          *
3296          * We also force the firmware's HALT flag to be on in case we bypassed
3297          * the firmware RESET command above or we're dealing with old firmware
3298          * which doesn't have the HALT capability.  This will serve as a flag
3299          * for the incoming firmware to know that it's coming out of a HALT
3300          * rather than a RESET ... if it's new enough to understand that ...
3301          */
3302         if (ret == 0 || force) {
3303                 t4_set_reg_field(adap, A_CIM_BOOT_CFG, F_UPCRST, F_UPCRST);
3304                 t4_set_reg_field(adap, A_PCIE_FW, F_PCIE_FW_HALT,
3305                                  F_PCIE_FW_HALT);
3306         }
3307
3308         /*
3309          * And we always return the result of the firmware RESET command
3310          * even when we force the uP into RESET ...
3311          */
3312         return ret;
3313 }
3314
3315 /**
3316  * t4_fw_restart - restart the firmware by taking the uP out of RESET
3317  * @adap: the adapter
3318  * @mbox: mailbox to use for the FW RESET command (if desired)
3319  * @reset: if we want to do a RESET to restart things
3320  *
3321  * Restart firmware previously halted by t4_fw_halt().  On successful
3322  * return the previous PF Master remains as the new PF Master and there
3323  * is no need to issue a new HELLO command, etc.
3324  *
3325  * We do this in two ways:
3326  *
3327  * 1. If we're dealing with newer firmware we'll simply want to take
3328  *    the chip's microprocessor out of RESET.  This will cause the
3329  *    firmware to start up from its start vector.  And then we'll loop
3330  *    until the firmware indicates it's started again (PCIE_FW.HALT
3331  *    reset to 0) or we timeout.
3332  *
3333  * 2. If we're dealing with older firmware then we'll need to RESET
3334  *    the chip since older firmware won't recognize the PCIE_FW.HALT
3335  *    flag and automatically RESET itself on startup.
3336  */
3337 int t4_fw_restart(struct adapter *adap, unsigned int mbox, int reset)
3338 {
3339         if (reset) {
3340                 /*
3341                  * Since we're directing the RESET instead of the firmware
3342                  * doing it automatically, we need to clear the PCIE_FW.HALT
3343                  * bit.
3344                  */
3345                 t4_set_reg_field(adap, A_PCIE_FW, F_PCIE_FW_HALT, 0);
3346
3347                 /*
3348                  * If we've been given a valid mailbox, first try to get the
3349                  * firmware to do the RESET.  If that works, great and we can
3350                  * return success.  Otherwise, if we haven't been given a
3351                  * valid mailbox or the RESET command failed, fall back to
3352                  * hitting the chip with a hammer.
3353                  */
3354                 if (mbox <= M_PCIE_FW_MASTER) {
3355                         t4_set_reg_field(adap, A_CIM_BOOT_CFG, F_UPCRST, 0);
3356                         msleep(100);
3357                         if (t4_fw_reset(adap, mbox,
3358                                         F_PIORST | F_PIORSTMODE) == 0)
3359                                 return 0;
3360                 }
3361
3362                 t4_write_reg(adap, A_PL_RST, F_PIORST | F_PIORSTMODE);
3363                 msleep(2000);
3364         } else {
3365                 int ms;
3366
3367                 t4_set_reg_field(adap, A_CIM_BOOT_CFG, F_UPCRST, 0);
3368                 for (ms = 0; ms < FW_CMD_MAX_TIMEOUT; ) {
3369                         if (!(t4_read_reg(adap, A_PCIE_FW) & F_PCIE_FW_HALT))
3370                                 return FW_SUCCESS;
3371                         msleep(100);
3372                         ms += 100;
3373                 }
3374                 return -ETIMEDOUT;
3375         }
3376         return 0;
3377 }
3378
3379 /**
3380  * t4_fl_pkt_align - return the fl packet alignment
3381  * @adap: the adapter
3382  *
3383  * T4 has a single field to specify the packing and padding boundary.
3384  * T5 onwards has separate fields for this and hence the alignment for
3385  * next packet offset is maximum of these two.
3386  */
3387 int t4_fl_pkt_align(struct adapter *adap)
3388 {
3389         u32 sge_control, sge_control2;
3390         unsigned int ingpadboundary, ingpackboundary, fl_align, ingpad_shift;
3391
3392         sge_control = t4_read_reg(adap, A_SGE_CONTROL);
3393
3394         /* T4 uses a single control field to specify both the PCIe Padding and
3395          * Packing Boundary.  T5 introduced the ability to specify these
3396          * separately.  The actual Ingress Packet Data alignment boundary
3397          * within Packed Buffer Mode is the maximum of these two
3398          * specifications.
3399          */
3400         if (CHELSIO_CHIP_VERSION(adap->params.chip) <= CHELSIO_T5)
3401                 ingpad_shift = X_INGPADBOUNDARY_SHIFT;
3402         else
3403                 ingpad_shift = X_T6_INGPADBOUNDARY_SHIFT;
3404
3405         ingpadboundary = 1 << (G_INGPADBOUNDARY(sge_control) + ingpad_shift);
3406
3407         fl_align = ingpadboundary;
3408         if (!is_t4(adap->params.chip)) {
3409                 sge_control2 = t4_read_reg(adap, A_SGE_CONTROL2);
3410                 ingpackboundary = G_INGPACKBOUNDARY(sge_control2);
3411                 if (ingpackboundary == X_INGPACKBOUNDARY_16B)
3412                         ingpackboundary = 16;
3413                 else
3414                         ingpackboundary = 1 << (ingpackboundary +
3415                                         X_INGPACKBOUNDARY_SHIFT);
3416
3417                 fl_align = max(ingpadboundary, ingpackboundary);
3418         }
3419         return fl_align;
3420 }
3421
3422 /**
3423  * t4_fixup_host_params_compat - fix up host-dependent parameters
3424  * @adap: the adapter
3425  * @page_size: the host's Base Page Size
3426  * @cache_line_size: the host's Cache Line Size
3427  * @chip_compat: maintain compatibility with designated chip
3428  *
3429  * Various registers in the chip contain values which are dependent on the
3430  * host's Base Page and Cache Line Sizes.  This function will fix all of
3431  * those registers with the appropriate values as passed in ...
3432  *
3433  * @chip_compat is used to limit the set of changes that are made
3434  * to be compatible with the indicated chip release.  This is used by
3435  * drivers to maintain compatibility with chip register settings when
3436  * the drivers haven't [yet] been updated with new chip support.
3437  */
3438 int t4_fixup_host_params_compat(struct adapter *adap,
3439                                 unsigned int page_size,
3440                                 unsigned int cache_line_size,
3441                                 enum chip_type chip_compat)
3442 {
3443         unsigned int page_shift = cxgbe_fls(page_size) - 1;
3444         unsigned int sge_hps = page_shift - 10;
3445         unsigned int stat_len = cache_line_size > 64 ? 128 : 64;
3446         unsigned int fl_align = cache_line_size < 32 ? 32 : cache_line_size;
3447         unsigned int fl_align_log = cxgbe_fls(fl_align) - 1;
3448
3449         t4_write_reg(adap, A_SGE_HOST_PAGE_SIZE,
3450                      V_HOSTPAGESIZEPF0(sge_hps) |
3451                      V_HOSTPAGESIZEPF1(sge_hps) |
3452                      V_HOSTPAGESIZEPF2(sge_hps) |
3453                      V_HOSTPAGESIZEPF3(sge_hps) |
3454                      V_HOSTPAGESIZEPF4(sge_hps) |
3455                      V_HOSTPAGESIZEPF5(sge_hps) |
3456                      V_HOSTPAGESIZEPF6(sge_hps) |
3457                      V_HOSTPAGESIZEPF7(sge_hps));
3458
3459         if (is_t4(adap->params.chip) || is_t4(chip_compat))
3460                 t4_set_reg_field(adap, A_SGE_CONTROL,
3461                                  V_INGPADBOUNDARY(M_INGPADBOUNDARY) |
3462                                  F_EGRSTATUSPAGESIZE,
3463                                  V_INGPADBOUNDARY(fl_align_log -
3464                                                   X_INGPADBOUNDARY_SHIFT) |
3465                                 V_EGRSTATUSPAGESIZE(stat_len != 64));
3466         else {
3467                 unsigned int pack_align;
3468                 unsigned int ingpad, ingpack;
3469                 unsigned int pcie_cap;
3470
3471                 /*
3472                  * T5 introduced the separation of the Free List Padding and
3473                  * Packing Boundaries.  Thus, we can select a smaller Padding
3474                  * Boundary to avoid uselessly chewing up PCIe Link and Memory
3475                  * Bandwidth, and use a Packing Boundary which is large enough
3476                  * to avoid false sharing between CPUs, etc.
3477                  *
3478                  * For the PCI Link, the smaller the Padding Boundary the
3479                  * better.  For the Memory Controller, a smaller Padding
3480                  * Boundary is better until we cross under the Memory Line
3481                  * Size (the minimum unit of transfer to/from Memory).  If we
3482                  * have a Padding Boundary which is smaller than the Memory
3483                  * Line Size, that'll involve a Read-Modify-Write cycle on the
3484                  * Memory Controller which is never good.
3485                  */
3486
3487                 /* We want the Packing Boundary to be based on the Cache Line
3488                  * Size in order to help avoid False Sharing performance
3489                  * issues between CPUs, etc.  We also want the Packing
3490                  * Boundary to incorporate the PCI-E Maximum Payload Size.  We
3491                  * get best performance when the Packing Boundary is a
3492                  * multiple of the Maximum Payload Size.
3493                  */
3494                 pack_align = fl_align;
3495                 pcie_cap = t4_os_find_pci_capability(adap, PCI_CAP_ID_EXP);
3496                 if (pcie_cap) {
3497                         unsigned int mps, mps_log;
3498                         u16 devctl;
3499
3500                         /* The PCIe Device Control Maximum Payload Size field
3501                          * [bits 7:5] encodes sizes as powers of 2 starting at
3502                          * 128 bytes.
3503                          */
3504                         t4_os_pci_read_cfg2(adap, pcie_cap + PCI_EXP_DEVCTL,
3505                                             &devctl);
3506                         mps_log = ((devctl & PCI_EXP_DEVCTL_PAYLOAD) >> 5) + 7;
3507                         mps = 1 << mps_log;
3508                         if (mps > pack_align)
3509                                 pack_align = mps;
3510                 }
3511
3512                 /*
3513                  * N.B. T5 has a different interpretation of the "0" value for
3514                  * the Packing Boundary.  This corresponds to 16 bytes instead
3515                  * of the expected 32 bytes.  We never have a Packing Boundary
3516                  * less than 32 bytes so we can't use that special value but
3517                  * on the other hand, if we wanted 32 bytes, the best we can
3518                  * really do is 64 bytes ...
3519                  */
3520                 if (pack_align <= 16) {
3521                         ingpack = X_INGPACKBOUNDARY_16B;
3522                         fl_align = 16;
3523                 } else if (pack_align == 32) {
3524                         ingpack = X_INGPACKBOUNDARY_64B;
3525                         fl_align = 64;
3526                 } else {
3527                         unsigned int pack_align_log = cxgbe_fls(pack_align) - 1;
3528
3529                         ingpack = pack_align_log - X_INGPACKBOUNDARY_SHIFT;
3530                         fl_align = pack_align;
3531                 }
3532
3533                 /* Use the smallest Ingress Padding which isn't smaller than
3534                  * the Memory Controller Read/Write Size.  We'll take that as
3535                  * being 8 bytes since we don't know of any system with a
3536                  * wider Memory Controller Bus Width.
3537                  */
3538                 if (is_t5(adap->params.chip))
3539                         ingpad = X_INGPADBOUNDARY_32B;
3540                 else
3541                         ingpad = X_T6_INGPADBOUNDARY_8B;
3542                 t4_set_reg_field(adap, A_SGE_CONTROL,
3543                                  V_INGPADBOUNDARY(M_INGPADBOUNDARY) |
3544                                  F_EGRSTATUSPAGESIZE,
3545                                  V_INGPADBOUNDARY(ingpad) |
3546                                  V_EGRSTATUSPAGESIZE(stat_len != 64));
3547                 t4_set_reg_field(adap, A_SGE_CONTROL2,
3548                                  V_INGPACKBOUNDARY(M_INGPACKBOUNDARY),
3549                                  V_INGPACKBOUNDARY(ingpack));
3550         }
3551
3552         /*
3553          * Adjust various SGE Free List Host Buffer Sizes.
3554          *
3555          * The first four entries are:
3556          *
3557          *   0: Host Page Size
3558          *   1: 64KB
3559          *   2: Buffer size corresponding to 1500 byte MTU (unpacked mode)
3560          *   3: Buffer size corresponding to 9000 byte MTU (unpacked mode)
3561          *
3562          * For the single-MTU buffers in unpacked mode we need to include
3563          * space for the SGE Control Packet Shift, 14 byte Ethernet header,
3564          * possible 4 byte VLAN tag, all rounded up to the next Ingress Packet
3565          * Padding boundary.  All of these are accommodated in the Factory
3566          * Default Firmware Configuration File but we need to adjust it for
3567          * this host's cache line size.
3568          */
3569         t4_write_reg(adap, A_SGE_FL_BUFFER_SIZE0, page_size);
3570         t4_write_reg(adap, A_SGE_FL_BUFFER_SIZE2,
3571                      (t4_read_reg(adap, A_SGE_FL_BUFFER_SIZE2) + fl_align - 1)
3572                      & ~(fl_align - 1));
3573         t4_write_reg(adap, A_SGE_FL_BUFFER_SIZE3,
3574                      (t4_read_reg(adap, A_SGE_FL_BUFFER_SIZE3) + fl_align - 1)
3575                      & ~(fl_align - 1));
3576
3577         t4_write_reg(adap, A_ULP_RX_TDDP_PSZ, V_HPZ0(page_shift - 12));
3578
3579         return 0;
3580 }
3581
3582 /**
3583  * t4_fixup_host_params - fix up host-dependent parameters (T4 compatible)
3584  * @adap: the adapter
3585  * @page_size: the host's Base Page Size
3586  * @cache_line_size: the host's Cache Line Size
3587  *
3588  * Various registers in T4 contain values which are dependent on the
3589  * host's Base Page and Cache Line Sizes.  This function will fix all of
3590  * those registers with the appropriate values as passed in ...
3591  *
3592  * This routine makes changes which are compatible with T4 chips.
3593  */
3594 int t4_fixup_host_params(struct adapter *adap, unsigned int page_size,
3595                          unsigned int cache_line_size)
3596 {
3597         return t4_fixup_host_params_compat(adap, page_size, cache_line_size,
3598                                            T4_LAST_REV);
3599 }
3600
3601 /**
3602  * t4_fw_initialize - ask FW to initialize the device
3603  * @adap: the adapter
3604  * @mbox: mailbox to use for the FW command
3605  *
3606  * Issues a command to FW to partially initialize the device.  This
3607  * performs initialization that generally doesn't depend on user input.
3608  */
3609 int t4_fw_initialize(struct adapter *adap, unsigned int mbox)
3610 {
3611         struct fw_initialize_cmd c;
3612
3613         memset(&c, 0, sizeof(c));
3614         INIT_CMD(c, INITIALIZE, WRITE);
3615         return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
3616 }
3617
3618 /**
3619  * t4_query_params_rw - query FW or device parameters
3620  * @adap: the adapter
3621  * @mbox: mailbox to use for the FW command
3622  * @pf: the PF
3623  * @vf: the VF
3624  * @nparams: the number of parameters
3625  * @params: the parameter names
3626  * @val: the parameter values
3627  * @rw: Write and read flag
3628  *
3629  * Reads the value of FW or device parameters.  Up to 7 parameters can be
3630  * queried at once.
3631  */
3632 static int t4_query_params_rw(struct adapter *adap, unsigned int mbox,
3633                               unsigned int pf, unsigned int vf,
3634                               unsigned int nparams, const u32 *params,
3635                               u32 *val, int rw)
3636 {
3637         unsigned int i;
3638         int ret;
3639         struct fw_params_cmd c;
3640         __be32 *p = &c.param[0].mnem;
3641
3642         if (nparams > 7)
3643                 return -EINVAL;
3644
3645         memset(&c, 0, sizeof(c));
3646         c.op_to_vfn = cpu_to_be32(V_FW_CMD_OP(FW_PARAMS_CMD) |
3647                                   F_FW_CMD_REQUEST | F_FW_CMD_READ |
3648                                   V_FW_PARAMS_CMD_PFN(pf) |
3649                                   V_FW_PARAMS_CMD_VFN(vf));
3650         c.retval_len16 = cpu_to_be32(FW_LEN16(c));
3651
3652         for (i = 0; i < nparams; i++) {
3653                 *p++ = cpu_to_be32(*params++);
3654                 if (rw)
3655                         *p = cpu_to_be32(*(val + i));
3656                 p++;
3657         }
3658
3659         ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
3660         if (ret == 0)
3661                 for (i = 0, p = &c.param[0].val; i < nparams; i++, p += 2)
3662                         *val++ = be32_to_cpu(*p);
3663         return ret;
3664 }
3665
3666 int t4_query_params(struct adapter *adap, unsigned int mbox, unsigned int pf,
3667                     unsigned int vf, unsigned int nparams, const u32 *params,
3668                     u32 *val)
3669 {
3670         return t4_query_params_rw(adap, mbox, pf, vf, nparams, params, val, 0);
3671 }
3672
3673 /**
3674  * t4_set_params_timeout - sets FW or device parameters
3675  * @adap: the adapter
3676  * @mbox: mailbox to use for the FW command
3677  * @pf: the PF
3678  * @vf: the VF
3679  * @nparams: the number of parameters
3680  * @params: the parameter names
3681  * @val: the parameter values
3682  * @timeout: the timeout time
3683  *
3684  * Sets the value of FW or device parameters.  Up to 7 parameters can be
3685  * specified at once.
3686  */
3687 int t4_set_params_timeout(struct adapter *adap, unsigned int mbox,
3688                           unsigned int pf, unsigned int vf,
3689                           unsigned int nparams, const u32 *params,
3690                           const u32 *val, int timeout)
3691 {
3692         struct fw_params_cmd c;
3693         __be32 *p = &c.param[0].mnem;
3694
3695         if (nparams > 7)
3696                 return -EINVAL;
3697
3698         memset(&c, 0, sizeof(c));
3699         c.op_to_vfn = cpu_to_be32(V_FW_CMD_OP(FW_PARAMS_CMD) |
3700                                   F_FW_CMD_REQUEST | F_FW_CMD_WRITE |
3701                                   V_FW_PARAMS_CMD_PFN(pf) |
3702                                   V_FW_PARAMS_CMD_VFN(vf));
3703         c.retval_len16 = cpu_to_be32(FW_LEN16(c));
3704
3705         while (nparams--) {
3706                 *p++ = cpu_to_be32(*params++);
3707                 *p++ = cpu_to_be32(*val++);
3708         }
3709
3710         return t4_wr_mbox_timeout(adap, mbox, &c, sizeof(c), NULL, timeout);
3711 }
3712
3713 int t4_set_params(struct adapter *adap, unsigned int mbox, unsigned int pf,
3714                   unsigned int vf, unsigned int nparams, const u32 *params,
3715                   const u32 *val)
3716 {
3717         return t4_set_params_timeout(adap, mbox, pf, vf, nparams, params, val,
3718                                      FW_CMD_MAX_TIMEOUT);
3719 }
3720
3721 /**
3722  * t4_alloc_vi_func - allocate a virtual interface
3723  * @adap: the adapter
3724  * @mbox: mailbox to use for the FW command
3725  * @port: physical port associated with the VI
3726  * @pf: the PF owning the VI
3727  * @vf: the VF owning the VI
3728  * @nmac: number of MAC addresses needed (1 to 5)
3729  * @mac: the MAC addresses of the VI
3730  * @rss_size: size of RSS table slice associated with this VI
3731  * @portfunc: which Port Application Function MAC Address is desired
3732  * @idstype: Intrusion Detection Type
3733  *
3734  * Allocates a virtual interface for the given physical port.  If @mac is
3735  * not %NULL it contains the MAC addresses of the VI as assigned by FW.
3736  * @mac should be large enough to hold @nmac Ethernet addresses, they are
3737  * stored consecutively so the space needed is @nmac * 6 bytes.
3738  * Returns a negative error number or the non-negative VI id.
3739  */
3740 int t4_alloc_vi_func(struct adapter *adap, unsigned int mbox,
3741                      unsigned int port, unsigned int pf, unsigned int vf,
3742                      unsigned int nmac, u8 *mac, unsigned int *rss_size,
3743                      unsigned int portfunc, unsigned int idstype)
3744 {
3745         int ret;
3746         struct fw_vi_cmd c;
3747
3748         memset(&c, 0, sizeof(c));
3749         c.op_to_vfn = cpu_to_be32(V_FW_CMD_OP(FW_VI_CMD) | F_FW_CMD_REQUEST |
3750                                   F_FW_CMD_WRITE | F_FW_CMD_EXEC |
3751                                   V_FW_VI_CMD_PFN(pf) | V_FW_VI_CMD_VFN(vf));
3752         c.alloc_to_len16 = cpu_to_be32(F_FW_VI_CMD_ALLOC | FW_LEN16(c));
3753         c.type_to_viid = cpu_to_be16(V_FW_VI_CMD_TYPE(idstype) |
3754                                      V_FW_VI_CMD_FUNC(portfunc));
3755         c.portid_pkd = V_FW_VI_CMD_PORTID(port);
3756         c.nmac = nmac - 1;
3757
3758         ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
3759         if (ret)
3760                 return ret;
3761
3762         if (mac) {
3763                 memcpy(mac, c.mac, sizeof(c.mac));
3764                 switch (nmac) {
3765                 case 5:
3766                         memcpy(mac + 24, c.nmac3, sizeof(c.nmac3));
3767                         /* FALLTHROUGH */
3768                 case 4:
3769                         memcpy(mac + 18, c.nmac2, sizeof(c.nmac2));
3770                         /* FALLTHROUGH */
3771                 case 3:
3772                         memcpy(mac + 12, c.nmac1, sizeof(c.nmac1));
3773                         /* FALLTHROUGH */
3774                 case 2:
3775                         memcpy(mac + 6,  c.nmac0, sizeof(c.nmac0));
3776                         /* FALLTHROUGH */
3777                 }
3778         }
3779         if (rss_size)
3780                 *rss_size = G_FW_VI_CMD_RSSSIZE(be16_to_cpu(c.norss_rsssize));
3781         return G_FW_VI_CMD_VIID(cpu_to_be16(c.type_to_viid));
3782 }
3783
3784 /**
3785  * t4_alloc_vi - allocate an [Ethernet Function] virtual interface
3786  * @adap: the adapter
3787  * @mbox: mailbox to use for the FW command
3788  * @port: physical port associated with the VI
3789  * @pf: the PF owning the VI
3790  * @vf: the VF owning the VI
3791  * @nmac: number of MAC addresses needed (1 to 5)
3792  * @mac: the MAC addresses of the VI
3793  * @rss_size: size of RSS table slice associated with this VI
3794  *
3795  * Backwards compatible and convieniance routine to allocate a Virtual
3796  * Interface with a Ethernet Port Application Function and Intrustion
3797  * Detection System disabled.
3798  */
3799 int t4_alloc_vi(struct adapter *adap, unsigned int mbox, unsigned int port,
3800                 unsigned int pf, unsigned int vf, unsigned int nmac, u8 *mac,
3801                 unsigned int *rss_size)
3802 {
3803         return t4_alloc_vi_func(adap, mbox, port, pf, vf, nmac, mac, rss_size,
3804                                 FW_VI_FUNC_ETH, 0);
3805 }
3806
3807 /**
3808  * t4_free_vi - free a virtual interface
3809  * @adap: the adapter
3810  * @mbox: mailbox to use for the FW command
3811  * @pf: the PF owning the VI
3812  * @vf: the VF owning the VI
3813  * @viid: virtual interface identifiler
3814  *
3815  * Free a previously allocated virtual interface.
3816  */
3817 int t4_free_vi(struct adapter *adap, unsigned int mbox, unsigned int pf,
3818                unsigned int vf, unsigned int viid)
3819 {
3820         struct fw_vi_cmd c;
3821
3822         memset(&c, 0, sizeof(c));
3823         c.op_to_vfn = cpu_to_be32(V_FW_CMD_OP(FW_VI_CMD) | F_FW_CMD_REQUEST |
3824                                   F_FW_CMD_EXEC | V_FW_VI_CMD_PFN(pf) |
3825                                   V_FW_VI_CMD_VFN(vf));
3826         c.alloc_to_len16 = cpu_to_be32(F_FW_VI_CMD_FREE | FW_LEN16(c));
3827         c.type_to_viid = cpu_to_be16(V_FW_VI_CMD_VIID(viid));
3828
3829         return t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
3830 }
3831
3832 /**
3833  * t4_set_rxmode - set Rx properties of a virtual interface
3834  * @adap: the adapter
3835  * @mbox: mailbox to use for the FW command
3836  * @viid: the VI id
3837  * @mtu: the new MTU or -1
3838  * @promisc: 1 to enable promiscuous mode, 0 to disable it, -1 no change
3839  * @all_multi: 1 to enable all-multi mode, 0 to disable it, -1 no change
3840  * @bcast: 1 to enable broadcast Rx, 0 to disable it, -1 no change
3841  * @vlanex: 1 to enable hardware VLAN Tag extraction, 0 to disable it,
3842  *          -1 no change
3843  * @sleep_ok: if true we may sleep while awaiting command completion
3844  *
3845  * Sets Rx properties of a virtual interface.
3846  */
3847 int t4_set_rxmode(struct adapter *adap, unsigned int mbox, unsigned int viid,
3848                   int mtu, int promisc, int all_multi, int bcast, int vlanex,
3849                   bool sleep_ok)
3850 {
3851         struct fw_vi_rxmode_cmd c;
3852
3853         /* convert to FW values */
3854         if (mtu < 0)
3855                 mtu = M_FW_VI_RXMODE_CMD_MTU;
3856         if (promisc < 0)
3857                 promisc = M_FW_VI_RXMODE_CMD_PROMISCEN;
3858         if (all_multi < 0)
3859                 all_multi = M_FW_VI_RXMODE_CMD_ALLMULTIEN;
3860         if (bcast < 0)
3861                 bcast = M_FW_VI_RXMODE_CMD_BROADCASTEN;
3862         if (vlanex < 0)
3863                 vlanex = M_FW_VI_RXMODE_CMD_VLANEXEN;
3864
3865         memset(&c, 0, sizeof(c));
3866         c.op_to_viid = cpu_to_be32(V_FW_CMD_OP(FW_VI_RXMODE_CMD) |
3867                                    F_FW_CMD_REQUEST | F_FW_CMD_WRITE |
3868                                    V_FW_VI_RXMODE_CMD_VIID(viid));
3869         c.retval_len16 = cpu_to_be32(FW_LEN16(c));
3870         c.mtu_to_vlanexen = cpu_to_be32(V_FW_VI_RXMODE_CMD_MTU(mtu) |
3871                             V_FW_VI_RXMODE_CMD_PROMISCEN(promisc) |
3872                             V_FW_VI_RXMODE_CMD_ALLMULTIEN(all_multi) |
3873                             V_FW_VI_RXMODE_CMD_BROADCASTEN(bcast) |
3874                             V_FW_VI_RXMODE_CMD_VLANEXEN(vlanex));
3875         return t4_wr_mbox_meat(adap, mbox, &c, sizeof(c), NULL, sleep_ok);
3876 }
3877
3878 /**
3879  * t4_change_mac - modifies the exact-match filter for a MAC address
3880  * @adap: the adapter
3881  * @mbox: mailbox to use for the FW command
3882  * @viid: the VI id
3883  * @idx: index of existing filter for old value of MAC address, or -1
3884  * @addr: the new MAC address value
3885  * @persist: whether a new MAC allocation should be persistent
3886  * @add_smt: if true also add the address to the HW SMT
3887  *
3888  * Modifies an exact-match filter and sets it to the new MAC address if
3889  * @idx >= 0, or adds the MAC address to a new filter if @idx < 0.  In the
3890  * latter case the address is added persistently if @persist is %true.
3891  *
3892  * Note that in general it is not possible to modify the value of a given
3893  * filter so the generic way to modify an address filter is to free the one
3894  * being used by the old address value and allocate a new filter for the
3895  * new address value.
3896  *
3897  * Returns a negative error number or the index of the filter with the new
3898  * MAC value.  Note that this index may differ from @idx.
3899  */
3900 int t4_change_mac(struct adapter *adap, unsigned int mbox, unsigned int viid,
3901                   int idx, const u8 *addr, bool persist, bool add_smt)
3902 {
3903         int ret, mode;
3904         struct fw_vi_mac_cmd c;
3905         struct fw_vi_mac_exact *p = c.u.exact;
3906         int max_mac_addr = adap->params.arch.mps_tcam_size;
3907
3908         if (idx < 0)                             /* new allocation */
3909                 idx = persist ? FW_VI_MAC_ADD_PERSIST_MAC : FW_VI_MAC_ADD_MAC;
3910         mode = add_smt ? FW_VI_MAC_SMT_AND_MPSTCAM : FW_VI_MAC_MPS_TCAM_ENTRY;
3911
3912         memset(&c, 0, sizeof(c));
3913         c.op_to_viid = cpu_to_be32(V_FW_CMD_OP(FW_VI_MAC_CMD) |
3914                                    F_FW_CMD_REQUEST | F_FW_CMD_WRITE |
3915                                    V_FW_VI_MAC_CMD_VIID(viid));
3916         c.freemacs_to_len16 = cpu_to_be32(V_FW_CMD_LEN16(1));
3917         p->valid_to_idx = cpu_to_be16(F_FW_VI_MAC_CMD_VALID |
3918                                       V_FW_VI_MAC_CMD_SMAC_RESULT(mode) |
3919                                       V_FW_VI_MAC_CMD_IDX(idx));
3920         memcpy(p->macaddr, addr, sizeof(p->macaddr));
3921
3922         ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
3923         if (ret == 0) {
3924                 ret = G_FW_VI_MAC_CMD_IDX(be16_to_cpu(p->valid_to_idx));
3925                 if (ret >= max_mac_addr)
3926                         ret = -ENOMEM;
3927         }
3928         return ret;
3929 }
3930
3931 /**
3932  * t4_enable_vi_params - enable/disable a virtual interface
3933  * @adap: the adapter
3934  * @mbox: mailbox to use for the FW command
3935  * @viid: the VI id
3936  * @rx_en: 1=enable Rx, 0=disable Rx
3937  * @tx_en: 1=enable Tx, 0=disable Tx
3938  * @dcb_en: 1=enable delivery of Data Center Bridging messages.
3939  *
3940  * Enables/disables a virtual interface.  Note that setting DCB Enable
3941  * only makes sense when enabling a Virtual Interface ...
3942  */
3943 int t4_enable_vi_params(struct adapter *adap, unsigned int mbox,
3944                         unsigned int viid, bool rx_en, bool tx_en, bool dcb_en)
3945 {
3946         struct fw_vi_enable_cmd c;
3947
3948         memset(&c, 0, sizeof(c));
3949         c.op_to_viid = cpu_to_be32(V_FW_CMD_OP(FW_VI_ENABLE_CMD) |
3950                                    F_FW_CMD_REQUEST | F_FW_CMD_EXEC |
3951                                    V_FW_VI_ENABLE_CMD_VIID(viid));
3952         c.ien_to_len16 = cpu_to_be32(V_FW_VI_ENABLE_CMD_IEN(rx_en) |
3953                                      V_FW_VI_ENABLE_CMD_EEN(tx_en) |
3954                                      V_FW_VI_ENABLE_CMD_DCB_INFO(dcb_en) |
3955                                      FW_LEN16(c));
3956         return t4_wr_mbox_ns(adap, mbox, &c, sizeof(c), NULL);
3957 }
3958
3959 /**
3960  * t4_enable_vi - enable/disable a virtual interface
3961  * @adap: the adapter
3962  * @mbox: mailbox to use for the FW command
3963  * @viid: the VI id
3964  * @rx_en: 1=enable Rx, 0=disable Rx
3965  * @tx_en: 1=enable Tx, 0=disable Tx
3966  *
3967  * Enables/disables a virtual interface.  Note that setting DCB Enable
3968  * only makes sense when enabling a Virtual Interface ...
3969  */
3970 int t4_enable_vi(struct adapter *adap, unsigned int mbox, unsigned int viid,
3971                  bool rx_en, bool tx_en)
3972 {
3973         return t4_enable_vi_params(adap, mbox, viid, rx_en, tx_en, 0);
3974 }
3975
3976 /**
3977  * t4_iq_start_stop - enable/disable an ingress queue and its FLs
3978  * @adap: the adapter
3979  * @mbox: mailbox to use for the FW command
3980  * @start: %true to enable the queues, %false to disable them
3981  * @pf: the PF owning the queues
3982  * @vf: the VF owning the queues
3983  * @iqid: ingress queue id
3984  * @fl0id: FL0 queue id or 0xffff if no attached FL0
3985  * @fl1id: FL1 queue id or 0xffff if no attached FL1
3986  *
3987  * Starts or stops an ingress queue and its associated FLs, if any.
3988  */
3989 int t4_iq_start_stop(struct adapter *adap, unsigned int mbox, bool start,
3990                      unsigned int pf, unsigned int vf, unsigned int iqid,
3991                      unsigned int fl0id, unsigned int fl1id)
3992 {
3993         struct fw_iq_cmd c;
3994
3995         memset(&c, 0, sizeof(c));
3996         c.op_to_vfn = cpu_to_be32(V_FW_CMD_OP(FW_IQ_CMD) | F_FW_CMD_REQUEST |
3997                                   F_FW_CMD_EXEC | V_FW_IQ_CMD_PFN(pf) |
3998                                   V_FW_IQ_CMD_VFN(vf));
3999         c.alloc_to_len16 = cpu_to_be32(V_FW_IQ_CMD_IQSTART(start) |
4000                                        V_FW_IQ_CMD_IQSTOP(!start) |
4001                                        FW_LEN16(c));
4002         c.iqid = cpu_to_be16(iqid);
4003         c.fl0id = cpu_to_be16(fl0id);
4004         c.fl1id = cpu_to_be16(fl1id);
4005         return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
4006 }
4007
4008 /**
4009  * t4_iq_free - free an ingress queue and its FLs
4010  * @adap: the adapter
4011  * @mbox: mailbox to use for the FW command
4012  * @pf: the PF owning the queues
4013  * @vf: the VF owning the queues
4014  * @iqtype: the ingress queue type (FW_IQ_TYPE_FL_INT_CAP, etc.)
4015  * @iqid: ingress queue id
4016  * @fl0id: FL0 queue id or 0xffff if no attached FL0
4017  * @fl1id: FL1 queue id or 0xffff if no attached FL1
4018  *
4019  * Frees an ingress queue and its associated FLs, if any.
4020  */
4021 int t4_iq_free(struct adapter *adap, unsigned int mbox, unsigned int pf,
4022                unsigned int vf, unsigned int iqtype, unsigned int iqid,
4023                unsigned int fl0id, unsigned int fl1id)
4024 {
4025         struct fw_iq_cmd c;
4026
4027         memset(&c, 0, sizeof(c));
4028         c.op_to_vfn = cpu_to_be32(V_FW_CMD_OP(FW_IQ_CMD) | F_FW_CMD_REQUEST |
4029                                   F_FW_CMD_EXEC | V_FW_IQ_CMD_PFN(pf) |
4030                                   V_FW_IQ_CMD_VFN(vf));
4031         c.alloc_to_len16 = cpu_to_be32(F_FW_IQ_CMD_FREE | FW_LEN16(c));
4032         c.type_to_iqandstindex = cpu_to_be32(V_FW_IQ_CMD_TYPE(iqtype));
4033         c.iqid = cpu_to_be16(iqid);
4034         c.fl0id = cpu_to_be16(fl0id);
4035         c.fl1id = cpu_to_be16(fl1id);
4036         return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
4037 }
4038
4039 /**
4040  * t4_eth_eq_free - free an Ethernet egress queue
4041  * @adap: the adapter
4042  * @mbox: mailbox to use for the FW command
4043  * @pf: the PF owning the queue
4044  * @vf: the VF owning the queue
4045  * @eqid: egress queue id
4046  *
4047  * Frees an Ethernet egress queue.
4048  */
4049 int t4_eth_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf,
4050                    unsigned int vf, unsigned int eqid)
4051 {
4052         struct fw_eq_eth_cmd c;
4053
4054         memset(&c, 0, sizeof(c));
4055         c.op_to_vfn = cpu_to_be32(V_FW_CMD_OP(FW_EQ_ETH_CMD) |
4056                                   F_FW_CMD_REQUEST | F_FW_CMD_EXEC |
4057                                   V_FW_EQ_ETH_CMD_PFN(pf) |
4058                                   V_FW_EQ_ETH_CMD_VFN(vf));
4059         c.alloc_to_len16 = cpu_to_be32(F_FW_EQ_ETH_CMD_FREE | FW_LEN16(c));
4060         c.eqid_pkd = cpu_to_be32(V_FW_EQ_ETH_CMD_EQID(eqid));
4061         return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
4062 }
4063
4064 /**
4065  * t4_handle_fw_rpl - process a FW reply message
4066  * @adap: the adapter
4067  * @rpl: start of the FW message
4068  *
4069  * Processes a FW message, such as link state change messages.
4070  */
4071 int t4_handle_fw_rpl(struct adapter *adap, const __be64 *rpl)
4072 {
4073         u8 opcode = *(const u8 *)rpl;
4074
4075         /*
4076          * This might be a port command ... this simplifies the following
4077          * conditionals ...  We can get away with pre-dereferencing
4078          * action_to_len16 because it's in the first 16 bytes and all messages
4079          * will be at least that long.
4080          */
4081         const struct fw_port_cmd *p = (const void *)rpl;
4082         unsigned int action =
4083                 G_FW_PORT_CMD_ACTION(be32_to_cpu(p->action_to_len16));
4084
4085         if (opcode == FW_PORT_CMD && action == FW_PORT_ACTION_GET_PORT_INFO) {
4086                 /* link/module state change message */
4087                 unsigned int speed = 0, fc = 0, i;
4088                 int chan = G_FW_PORT_CMD_PORTID(be32_to_cpu(p->op_to_portid));
4089                 struct port_info *pi = NULL;
4090                 struct link_config *lc;
4091                 u32 stat = be32_to_cpu(p->u.info.lstatus_to_modtype);
4092                 int link_ok = (stat & F_FW_PORT_CMD_LSTATUS) != 0;
4093                 u32 mod = G_FW_PORT_CMD_MODTYPE(stat);
4094
4095                 if (stat & F_FW_PORT_CMD_RXPAUSE)
4096                         fc |= PAUSE_RX;
4097                 if (stat & F_FW_PORT_CMD_TXPAUSE)
4098                         fc |= PAUSE_TX;
4099                 if (stat & V_FW_PORT_CMD_LSPEED(FW_PORT_CAP_SPEED_100M))
4100                         speed = ETH_SPEED_NUM_100M;
4101                 else if (stat & V_FW_PORT_CMD_LSPEED(FW_PORT_CAP_SPEED_1G))
4102                         speed = ETH_SPEED_NUM_1G;
4103                 else if (stat & V_FW_PORT_CMD_LSPEED(FW_PORT_CAP_SPEED_10G))
4104                         speed = ETH_SPEED_NUM_10G;
4105                 else if (stat & V_FW_PORT_CMD_LSPEED(FW_PORT_CAP_SPEED_25G))
4106                         speed = ETH_SPEED_NUM_25G;
4107                 else if (stat & V_FW_PORT_CMD_LSPEED(FW_PORT_CAP_SPEED_40G))
4108                         speed = ETH_SPEED_NUM_40G;
4109                 else if (stat & V_FW_PORT_CMD_LSPEED(FW_PORT_CAP_SPEED_100G))
4110                         speed = ETH_SPEED_NUM_100G;
4111
4112                 for_each_port(adap, i) {
4113                         pi = adap2pinfo(adap, i);
4114                         if (pi->tx_chan == chan)
4115                                 break;
4116                 }
4117                 lc = &pi->link_cfg;
4118
4119                 if (mod != pi->mod_type) {
4120                         pi->mod_type = mod;
4121                         t4_os_portmod_changed(adap, i);
4122                 }
4123                 if (link_ok != lc->link_ok || speed != lc->speed ||
4124                     fc != lc->fc) {                    /* something changed */
4125                         if (!link_ok && lc->link_ok) {
4126                                 static const char * const reason[] = {
4127                                         "Link Down",
4128                                         "Remote Fault",
4129                                         "Auto-negotiation Failure",
4130                                         "Reserved",
4131                                         "Insufficient Airflow",
4132                                         "Unable To Determine Reason",
4133                                         "No RX Signal Detected",
4134                                         "Reserved",
4135                                 };
4136                                 unsigned int rc = G_FW_PORT_CMD_LINKDNRC(stat);
4137
4138                                 dev_warn(adap, "Port %d link down, reason: %s\n",
4139                                          chan, reason[rc]);
4140                         }
4141                         lc->link_ok = link_ok;
4142                         lc->speed = speed;
4143                         lc->fc = fc;
4144                         lc->supported = be16_to_cpu(p->u.info.pcap);
4145                 }
4146         } else {
4147                 dev_warn(adap, "Unknown firmware reply %d\n", opcode);
4148                 return -EINVAL;
4149         }
4150         return 0;
4151 }
4152
4153 void t4_reset_link_config(struct adapter *adap, int idx)
4154 {
4155         struct port_info *pi = adap2pinfo(adap, idx);
4156         struct link_config *lc = &pi->link_cfg;
4157
4158         lc->link_ok = 0;
4159         lc->requested_speed = 0;
4160         lc->requested_fc = 0;
4161         lc->speed = 0;
4162         lc->fc = 0;
4163 }
4164
4165 /**
4166  * init_link_config - initialize a link's SW state
4167  * @lc: structure holding the link state
4168  * @pcaps: link Port Capabilities
4169  * @acaps: link current Advertised Port Capabilities
4170  *
4171  * Initializes the SW state maintained for each link, including the link's
4172  * capabilities and default speed/flow-control/autonegotiation settings.
4173  */
4174 static void init_link_config(struct link_config *lc, unsigned int pcaps,
4175                              unsigned int acaps)
4176 {
4177         unsigned int fec;
4178
4179         lc->supported = pcaps;
4180         lc->requested_speed = 0;
4181         lc->speed = 0;
4182         lc->requested_fc = 0;
4183         lc->fc = 0;
4184
4185         /**
4186          * For Forward Error Control, we default to whatever the Firmware
4187          * tells us the Link is currently advertising.
4188          */
4189         fec = 0;
4190         if (acaps & FW_PORT_CAP_FEC_RS)
4191                 fec |= FEC_RS;
4192         if (acaps & FW_PORT_CAP_FEC_BASER_RS)
4193                 fec |= FEC_BASER_RS;
4194         if (acaps & FW_PORT_CAP_FEC_RESERVED)
4195                 fec |= FEC_RESERVED;
4196         lc->requested_fec = fec;
4197         lc->fec = fec;
4198
4199         if (lc->supported & FW_PORT_CAP_ANEG) {
4200                 lc->advertising = lc->supported & ADVERT_MASK;
4201                 lc->autoneg = AUTONEG_ENABLE;
4202         } else {
4203                 lc->advertising = 0;
4204                 lc->autoneg = AUTONEG_DISABLE;
4205         }
4206 }
4207
4208 /**
4209  * t4_wait_dev_ready - wait till to reads of registers work
4210  *
4211  * Right after the device is RESET is can take a small amount of time
4212  * for it to respond to register reads.  Until then, all reads will
4213  * return either 0xff...ff or 0xee...ee.  Return an error if reads
4214  * don't work within a reasonable time frame.
4215  */
4216 static int t4_wait_dev_ready(struct adapter *adapter)
4217 {
4218         u32 whoami;
4219
4220         whoami = t4_read_reg(adapter, A_PL_WHOAMI);
4221
4222         if (whoami != 0xffffffff && whoami != X_CIM_PF_NOACCESS)
4223                 return 0;
4224
4225         msleep(500);
4226         whoami = t4_read_reg(adapter, A_PL_WHOAMI);
4227         if (whoami != 0xffffffff && whoami != X_CIM_PF_NOACCESS)
4228                 return 0;
4229
4230         dev_err(adapter, "Device didn't become ready for access, whoami = %#x\n",
4231                 whoami);
4232         return -EIO;
4233 }
4234
4235 struct flash_desc {
4236         u32 vendor_and_model_id;
4237         u32 size_mb;
4238 };
4239
4240 int t4_get_flash_params(struct adapter *adapter)
4241 {
4242         /*
4243          * Table for non-Numonix supported flash parts.  Numonix parts are left
4244          * to the preexisting well-tested code.  All flash parts have 64KB
4245          * sectors.
4246          */
4247         static struct flash_desc supported_flash[] = {
4248                 { 0x00150201, 4 << 20 },       /* Spansion 4MB S25FL032P */
4249         };
4250
4251         int ret;
4252         u32 flashid = 0;
4253         unsigned int part, manufacturer;
4254         unsigned int density, size;
4255
4256         /**
4257          * Issue a Read ID Command to the Flash part.  We decode supported
4258          * Flash parts and their sizes from this.  There's a newer Query
4259          * Command which can retrieve detailed geometry information but
4260          * many Flash parts don't support it.
4261          */
4262         ret = sf1_write(adapter, 1, 1, 0, SF_RD_ID);
4263         if (!ret)
4264                 ret = sf1_read(adapter, 3, 0, 1, &flashid);
4265         t4_write_reg(adapter, A_SF_OP, 0);               /* unlock SF */
4266         if (ret < 0)
4267                 return ret;
4268
4269         for (part = 0; part < ARRAY_SIZE(supported_flash); part++) {
4270                 if (supported_flash[part].vendor_and_model_id == flashid) {
4271                         adapter->params.sf_size =
4272                                 supported_flash[part].size_mb;
4273                         adapter->params.sf_nsec =
4274                                 adapter->params.sf_size / SF_SEC_SIZE;
4275                         goto found;
4276                 }
4277         }
4278
4279         manufacturer = flashid & 0xff;
4280         switch (manufacturer) {
4281         case 0x20: { /* Micron/Numonix */
4282                 /**
4283                  * This Density -> Size decoding table is taken from Micron
4284                  * Data Sheets.
4285                  */
4286                 density = (flashid >> 16) & 0xff;
4287                 switch (density) {
4288                 case 0x14:
4289                         size = 1 << 20; /* 1MB */
4290                         break;
4291                 case 0x15:
4292                         size = 1 << 21; /* 2MB */
4293                         break;
4294                 case 0x16:
4295                         size = 1 << 22; /* 4MB */
4296                         break;
4297                 case 0x17:
4298                         size = 1 << 23; /* 8MB */
4299                         break;
4300                 case 0x18:
4301                         size = 1 << 24; /* 16MB */
4302                         break;
4303                 case 0x19:
4304                         size = 1 << 25; /* 32MB */
4305                         break;
4306                 case 0x20:
4307                         size = 1 << 26; /* 64MB */
4308                         break;
4309                 case 0x21:
4310                         size = 1 << 27; /* 128MB */
4311                         break;
4312                 case 0x22:
4313                         size = 1 << 28; /* 256MB */
4314                         break;
4315                 default:
4316                         dev_err(adapter, "Micron Flash Part has bad size, ID = %#x, Density code = %#x\n",
4317                                 flashid, density);
4318                         return -EINVAL;
4319                 }
4320
4321                 adapter->params.sf_size = size;
4322                 adapter->params.sf_nsec = size / SF_SEC_SIZE;
4323                 break;
4324         }
4325         default:
4326                 dev_err(adapter, "Unsupported Flash Part, ID = %#x\n", flashid);
4327                 return -EINVAL;
4328         }
4329
4330 found:
4331         /*
4332          * We should reject adapters with FLASHes which are too small. So, emit
4333          * a warning.
4334          */
4335         if (adapter->params.sf_size < FLASH_MIN_SIZE)
4336                 dev_warn(adapter, "WARNING: Flash Part ID %#x, size %#x < %#x\n",
4337                          flashid, adapter->params.sf_size, FLASH_MIN_SIZE);
4338
4339         return 0;
4340 }
4341
4342 static void set_pcie_completion_timeout(struct adapter *adapter,
4343                                         u8 range)
4344 {
4345         u32 pcie_cap;
4346         u16 val;
4347
4348         pcie_cap = t4_os_find_pci_capability(adapter, PCI_CAP_ID_EXP);
4349         if (pcie_cap) {
4350                 t4_os_pci_read_cfg2(adapter, pcie_cap + PCI_EXP_DEVCTL2, &val);
4351                 val &= 0xfff0;
4352                 val |= range;
4353                 t4_os_pci_write_cfg2(adapter, pcie_cap + PCI_EXP_DEVCTL2, val);
4354         }
4355 }
4356
4357 /**
4358  * t4_get_chip_type - Determine chip type from device ID
4359  * @adap: the adapter
4360  * @ver: adapter version
4361  */
4362 int t4_get_chip_type(struct adapter *adap, int ver)
4363 {
4364         enum chip_type chip = 0;
4365         u32 pl_rev = G_REV(t4_read_reg(adap, A_PL_REV));
4366
4367         /* Retrieve adapter's device ID */
4368         switch (ver) {
4369         case CHELSIO_T5:
4370                 chip |= CHELSIO_CHIP_CODE(CHELSIO_T5, pl_rev);
4371                 break;
4372         case CHELSIO_T6:
4373                 chip |= CHELSIO_CHIP_CODE(CHELSIO_T6, pl_rev);
4374                 break;
4375         default:
4376                 dev_err(adap, "Device %d is not supported\n",
4377                         adap->params.pci.device_id);
4378                 return -EINVAL;
4379         }
4380
4381         return chip;
4382 }
4383
4384 /**
4385  * t4_prep_adapter - prepare SW and HW for operation
4386  * @adapter: the adapter
4387  *
4388  * Initialize adapter SW state for the various HW modules, set initial
4389  * values for some adapter tunables, take PHYs out of reset, and
4390  * initialize the MDIO interface.
4391  */
4392 int t4_prep_adapter(struct adapter *adapter)
4393 {
4394         int ret, ver;
4395         u32 pl_rev;
4396
4397         ret = t4_wait_dev_ready(adapter);
4398         if (ret < 0)
4399                 return ret;
4400
4401         pl_rev = G_REV(t4_read_reg(adapter, A_PL_REV));
4402         adapter->params.pci.device_id = adapter->pdev->id.device_id;
4403         adapter->params.pci.vendor_id = adapter->pdev->id.vendor_id;
4404
4405         /*
4406          * WE DON'T NEED adapter->params.chip CODE ONCE PL_REV CONTAINS
4407          * ADAPTER (VERSION << 4 | REVISION)
4408          */
4409         ver = CHELSIO_PCI_ID_VER(adapter->params.pci.device_id);
4410         adapter->params.chip = 0;
4411         switch (ver) {
4412         case CHELSIO_T5:
4413                 adapter->params.chip |= CHELSIO_CHIP_CODE(CHELSIO_T5, pl_rev);
4414                 adapter->params.arch.sge_fl_db = F_DBPRIO | F_DBTYPE;
4415                 adapter->params.arch.mps_tcam_size =
4416                                                 NUM_MPS_T5_CLS_SRAM_L_INSTANCES;
4417                 adapter->params.arch.mps_rplc_size = 128;
4418                 adapter->params.arch.nchan = NCHAN;
4419                 adapter->params.arch.vfcount = 128;
4420                 break;
4421         case CHELSIO_T6:
4422                 adapter->params.chip |= CHELSIO_CHIP_CODE(CHELSIO_T6, pl_rev);
4423                 adapter->params.arch.sge_fl_db = 0;
4424                 adapter->params.arch.mps_tcam_size =
4425                                                 NUM_MPS_T5_CLS_SRAM_L_INSTANCES;
4426                 adapter->params.arch.mps_rplc_size = 256;
4427                 adapter->params.arch.nchan = 2;
4428                 adapter->params.arch.vfcount = 256;
4429                 break;
4430         default:
4431                 dev_err(adapter, "%s: Device %d is not supported\n",
4432                         __func__, adapter->params.pci.device_id);
4433                 return -EINVAL;
4434         }
4435
4436         adapter->params.pci.vpd_cap_addr =
4437                 t4_os_find_pci_capability(adapter, PCI_CAP_ID_VPD);
4438
4439         ret = t4_get_flash_params(adapter);
4440         if (ret < 0) {
4441                 dev_err(adapter, "Unable to retrieve Flash Parameters, ret = %d\n",
4442                         -ret);
4443                 return ret;
4444         }
4445
4446         adapter->params.cim_la_size = CIMLA_SIZE;
4447
4448         init_cong_ctrl(adapter->params.a_wnd, adapter->params.b_wnd);
4449
4450         /*
4451          * Default port and clock for debugging in case we can't reach FW.
4452          */
4453         adapter->params.nports = 1;
4454         adapter->params.portvec = 1;
4455         adapter->params.vpd.cclk = 50000;
4456
4457         /* Set pci completion timeout value to 4 seconds. */
4458         set_pcie_completion_timeout(adapter, 0xd);
4459         return 0;
4460 }
4461
4462 /**
4463  * t4_bar2_sge_qregs - return BAR2 SGE Queue register information
4464  * @adapter: the adapter
4465  * @qid: the Queue ID
4466  * @qtype: the Ingress or Egress type for @qid
4467  * @pbar2_qoffset: BAR2 Queue Offset
4468  * @pbar2_qid: BAR2 Queue ID or 0 for Queue ID inferred SGE Queues
4469  *
4470  * Returns the BAR2 SGE Queue Registers information associated with the
4471  * indicated Absolute Queue ID.  These are passed back in return value
4472  * pointers.  @qtype should be T4_BAR2_QTYPE_EGRESS for Egress Queue
4473  * and T4_BAR2_QTYPE_INGRESS for Ingress Queues.
4474  *
4475  * This may return an error which indicates that BAR2 SGE Queue
4476  * registers aren't available.  If an error is not returned, then the
4477  * following values are returned:
4478  *
4479  *   *@pbar2_qoffset: the BAR2 Offset of the @qid Registers
4480  *   *@pbar2_qid: the BAR2 SGE Queue ID or 0 of @qid
4481  *
4482  * If the returned BAR2 Queue ID is 0, then BAR2 SGE registers which
4483  * require the "Inferred Queue ID" ability may be used.  E.g. the
4484  * Write Combining Doorbell Buffer. If the BAR2 Queue ID is not 0,
4485  * then these "Inferred Queue ID" register may not be used.
4486  */
4487 int t4_bar2_sge_qregs(struct adapter *adapter, unsigned int qid,
4488                       enum t4_bar2_qtype qtype, u64 *pbar2_qoffset,
4489                       unsigned int *pbar2_qid)
4490 {
4491         unsigned int page_shift, page_size, qpp_shift, qpp_mask;
4492         u64 bar2_page_offset, bar2_qoffset;
4493         unsigned int bar2_qid, bar2_qid_offset, bar2_qinferred;
4494
4495         /*
4496          * T4 doesn't support BAR2 SGE Queue registers.
4497          */
4498         if (is_t4(adapter->params.chip))
4499                 return -EINVAL;
4500
4501         /*
4502          * Get our SGE Page Size parameters.
4503          */
4504         page_shift = adapter->params.sge.hps + 10;
4505         page_size = 1 << page_shift;
4506
4507         /*
4508          * Get the right Queues per Page parameters for our Queue.
4509          */
4510         qpp_shift = (qtype == T4_BAR2_QTYPE_EGRESS ?
4511                               adapter->params.sge.eq_qpp :
4512                               adapter->params.sge.iq_qpp);
4513         qpp_mask = (1 << qpp_shift) - 1;
4514
4515         /*
4516          * Calculate the basics of the BAR2 SGE Queue register area:
4517          *  o The BAR2 page the Queue registers will be in.
4518          *  o The BAR2 Queue ID.
4519          *  o The BAR2 Queue ID Offset into the BAR2 page.
4520          */
4521         bar2_page_offset = ((qid >> qpp_shift) << page_shift);
4522         bar2_qid = qid & qpp_mask;
4523         bar2_qid_offset = bar2_qid * SGE_UDB_SIZE;
4524
4525         /*
4526          * If the BAR2 Queue ID Offset is less than the Page Size, then the
4527          * hardware will infer the Absolute Queue ID simply from the writes to
4528          * the BAR2 Queue ID Offset within the BAR2 Page (and we need to use a
4529          * BAR2 Queue ID of 0 for those writes).  Otherwise, we'll simply
4530          * write to the first BAR2 SGE Queue Area within the BAR2 Page with
4531          * the BAR2 Queue ID and the hardware will infer the Absolute Queue ID
4532          * from the BAR2 Page and BAR2 Queue ID.
4533          *
4534          * One important censequence of this is that some BAR2 SGE registers
4535          * have a "Queue ID" field and we can write the BAR2 SGE Queue ID
4536          * there.  But other registers synthesize the SGE Queue ID purely
4537          * from the writes to the registers -- the Write Combined Doorbell
4538          * Buffer is a good example.  These BAR2 SGE Registers are only
4539          * available for those BAR2 SGE Register areas where the SGE Absolute
4540          * Queue ID can be inferred from simple writes.
4541          */
4542         bar2_qoffset = bar2_page_offset;
4543         bar2_qinferred = (bar2_qid_offset < page_size);
4544         if (bar2_qinferred) {
4545                 bar2_qoffset += bar2_qid_offset;
4546                 bar2_qid = 0;
4547         }
4548
4549         *pbar2_qoffset = bar2_qoffset;
4550         *pbar2_qid = bar2_qid;
4551         return 0;
4552 }
4553
4554 /**
4555  * t4_init_sge_params - initialize adap->params.sge
4556  * @adapter: the adapter
4557  *
4558  * Initialize various fields of the adapter's SGE Parameters structure.
4559  */
4560 int t4_init_sge_params(struct adapter *adapter)
4561 {
4562         struct sge_params *sge_params = &adapter->params.sge;
4563         u32 hps, qpp;
4564         unsigned int s_hps, s_qpp;
4565
4566         /*
4567          * Extract the SGE Page Size for our PF.
4568          */
4569         hps = t4_read_reg(adapter, A_SGE_HOST_PAGE_SIZE);
4570         s_hps = (S_HOSTPAGESIZEPF0 + (S_HOSTPAGESIZEPF1 - S_HOSTPAGESIZEPF0) *
4571                  adapter->pf);
4572         sge_params->hps = ((hps >> s_hps) & M_HOSTPAGESIZEPF0);
4573
4574         /*
4575          * Extract the SGE Egress and Ingess Queues Per Page for our PF.
4576          */
4577         s_qpp = (S_QUEUESPERPAGEPF0 +
4578                  (S_QUEUESPERPAGEPF1 - S_QUEUESPERPAGEPF0) * adapter->pf);
4579         qpp = t4_read_reg(adapter, A_SGE_EGRESS_QUEUES_PER_PAGE_PF);
4580         sge_params->eq_qpp = ((qpp >> s_qpp) & M_QUEUESPERPAGEPF0);
4581         qpp = t4_read_reg(adapter, A_SGE_INGRESS_QUEUES_PER_PAGE_PF);
4582         sge_params->iq_qpp = ((qpp >> s_qpp) & M_QUEUESPERPAGEPF0);
4583
4584         return 0;
4585 }
4586
4587 /**
4588  * t4_init_tp_params - initialize adap->params.tp
4589  * @adap: the adapter
4590  *
4591  * Initialize various fields of the adapter's TP Parameters structure.
4592  */
4593 int t4_init_tp_params(struct adapter *adap)
4594 {
4595         int chan;
4596         u32 v;
4597
4598         v = t4_read_reg(adap, A_TP_TIMER_RESOLUTION);
4599         adap->params.tp.tre = G_TIMERRESOLUTION(v);
4600         adap->params.tp.dack_re = G_DELAYEDACKRESOLUTION(v);
4601
4602         /* MODQ_REQ_MAP defaults to setting queues 0-3 to chan 0-3 */
4603         for (chan = 0; chan < NCHAN; chan++)
4604                 adap->params.tp.tx_modq[chan] = chan;
4605
4606         /*
4607          * Cache the adapter's Compressed Filter Mode and global Incress
4608          * Configuration.
4609          */
4610         t4_read_indirect(adap, A_TP_PIO_ADDR, A_TP_PIO_DATA,
4611                          &adap->params.tp.vlan_pri_map, 1, A_TP_VLAN_PRI_MAP);
4612         t4_read_indirect(adap, A_TP_PIO_ADDR, A_TP_PIO_DATA,
4613                          &adap->params.tp.ingress_config, 1,
4614                          A_TP_INGRESS_CONFIG);
4615
4616         /* For T6, cache the adapter's compressed error vector
4617          * and passing outer header info for encapsulated packets.
4618          */
4619         if (CHELSIO_CHIP_VERSION(adap->params.chip) > CHELSIO_T5) {
4620                 v = t4_read_reg(adap, A_TP_OUT_CONFIG);
4621                 adap->params.tp.rx_pkt_encap = (v & F_CRXPKTENC) ? 1 : 0;
4622         }
4623
4624         /*
4625          * Now that we have TP_VLAN_PRI_MAP cached, we can calculate the field
4626          * shift positions of several elements of the Compressed Filter Tuple
4627          * for this adapter which we need frequently ...
4628          */
4629         adap->params.tp.vlan_shift = t4_filter_field_shift(adap, F_VLAN);
4630         adap->params.tp.vnic_shift = t4_filter_field_shift(adap, F_VNIC_ID);
4631         adap->params.tp.port_shift = t4_filter_field_shift(adap, F_PORT);
4632         adap->params.tp.protocol_shift = t4_filter_field_shift(adap,
4633                                                                F_PROTOCOL);
4634
4635         /*
4636          * If TP_INGRESS_CONFIG.VNID == 0, then TP_VLAN_PRI_MAP.VNIC_ID
4637          * represents the presense of an Outer VLAN instead of a VNIC ID.
4638          */
4639         if ((adap->params.tp.ingress_config & F_VNIC) == 0)
4640                 adap->params.tp.vnic_shift = -1;
4641
4642         return 0;
4643 }
4644
4645 /**
4646  * t4_filter_field_shift - calculate filter field shift
4647  * @adap: the adapter
4648  * @filter_sel: the desired field (from TP_VLAN_PRI_MAP bits)
4649  *
4650  * Return the shift position of a filter field within the Compressed
4651  * Filter Tuple.  The filter field is specified via its selection bit
4652  * within TP_VLAN_PRI_MAL (filter mode).  E.g. F_VLAN.
4653  */
4654 int t4_filter_field_shift(const struct adapter *adap, unsigned int filter_sel)
4655 {
4656         unsigned int filter_mode = adap->params.tp.vlan_pri_map;
4657         unsigned int sel;
4658         int field_shift;
4659
4660         if ((filter_mode & filter_sel) == 0)
4661                 return -1;
4662
4663         for (sel = 1, field_shift = 0; sel < filter_sel; sel <<= 1) {
4664                 switch (filter_mode & sel) {
4665                 case F_FCOE:
4666                         field_shift += W_FT_FCOE;
4667                         break;
4668                 case F_PORT:
4669                         field_shift += W_FT_PORT;
4670                         break;
4671                 case F_VNIC_ID:
4672                         field_shift += W_FT_VNIC_ID;
4673                         break;
4674                 case F_VLAN:
4675                         field_shift += W_FT_VLAN;
4676                         break;
4677                 case F_TOS:
4678                         field_shift += W_FT_TOS;
4679                         break;
4680                 case F_PROTOCOL:
4681                         field_shift += W_FT_PROTOCOL;
4682                         break;
4683                 case F_ETHERTYPE:
4684                         field_shift += W_FT_ETHERTYPE;
4685                         break;
4686                 case F_MACMATCH:
4687                         field_shift += W_FT_MACMATCH;
4688                         break;
4689                 case F_MPSHITTYPE:
4690                         field_shift += W_FT_MPSHITTYPE;
4691                         break;
4692                 case F_FRAGMENTATION:
4693                         field_shift += W_FT_FRAGMENTATION;
4694                         break;
4695                 }
4696         }
4697         return field_shift;
4698 }
4699
4700 int t4_init_rss_mode(struct adapter *adap, int mbox)
4701 {
4702         int i, ret;
4703         struct fw_rss_vi_config_cmd rvc;
4704
4705         memset(&rvc, 0, sizeof(rvc));
4706
4707         for_each_port(adap, i) {
4708                 struct port_info *p = adap2pinfo(adap, i);
4709
4710                 rvc.op_to_viid = htonl(V_FW_CMD_OP(FW_RSS_VI_CONFIG_CMD) |
4711                                        F_FW_CMD_REQUEST | F_FW_CMD_READ |
4712                                        V_FW_RSS_VI_CONFIG_CMD_VIID(p->viid));
4713                 rvc.retval_len16 = htonl(FW_LEN16(rvc));
4714                 ret = t4_wr_mbox(adap, mbox, &rvc, sizeof(rvc), &rvc);
4715                 if (ret)
4716                         return ret;
4717                 p->rss_mode = ntohl(rvc.u.basicvirtual.defaultq_to_udpen);
4718         }
4719         return 0;
4720 }
4721
4722 int t4_port_init(struct adapter *adap, int mbox, int pf, int vf)
4723 {
4724         u8 addr[6];
4725         int ret, i, j = 0;
4726         struct fw_port_cmd c;
4727
4728         memset(&c, 0, sizeof(c));
4729
4730         for_each_port(adap, i) {
4731                 unsigned int rss_size = 0;
4732                 struct port_info *p = adap2pinfo(adap, i);
4733
4734                 while ((adap->params.portvec & (1 << j)) == 0)
4735                         j++;
4736
4737                 c.op_to_portid = cpu_to_be32(V_FW_CMD_OP(FW_PORT_CMD) |
4738                                              F_FW_CMD_REQUEST | F_FW_CMD_READ |
4739                                              V_FW_PORT_CMD_PORTID(j));
4740                 c.action_to_len16 = cpu_to_be32(V_FW_PORT_CMD_ACTION(
4741                                                 FW_PORT_ACTION_GET_PORT_INFO) |
4742                                                 FW_LEN16(c));
4743                 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
4744                 if (ret)
4745                         return ret;
4746
4747                 ret = t4_alloc_vi(adap, mbox, j, pf, vf, 1, addr, &rss_size);
4748                 if (ret < 0)
4749                         return ret;
4750
4751                 p->viid = ret;
4752                 p->tx_chan = j;
4753                 p->rss_size = rss_size;
4754                 t4_os_set_hw_addr(adap, i, addr);
4755
4756                 ret = be32_to_cpu(c.u.info.lstatus_to_modtype);
4757                 p->mdio_addr = (ret & F_FW_PORT_CMD_MDIOCAP) ?
4758                                 G_FW_PORT_CMD_MDIOADDR(ret) : -1;
4759                 p->port_type = G_FW_PORT_CMD_PTYPE(ret);
4760                 p->mod_type = FW_PORT_MOD_TYPE_NA;
4761
4762                 init_link_config(&p->link_cfg, be16_to_cpu(c.u.info.pcap),
4763                                  be16_to_cpu(c.u.info.acap));
4764                 j++;
4765         }
4766         return 0;
4767 }