drivers/net/cxgbe/cxgbe_main.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2014-2018 Chelsio Communications.
   3  * All rights reserved.
   4  */
   5
   6 #include <sys/queue.h>
   7 #include <stdio.h>
   8 #include <errno.h>
   9 #include <stdint.h>
  10 #include <string.h>
  11 #include <unistd.h>
  12 #include <stdarg.h>
  13 #include <inttypes.h>
  14 #include <netinet/in.h>
  15
  16 #include <rte_byteorder.h>
  17 #include <rte_common.h>
  18 #include <rte_cycles.h>
  19 #include <rte_interrupts.h>
  20 #include <rte_log.h>
  21 #include <rte_debug.h>
  22 #include <rte_pci.h>
  23 #include <rte_atomic.h>
  24 #include <rte_branch_prediction.h>
  25 #include <rte_memory.h>
  26 #include <rte_tailq.h>
  27 #include <rte_eal.h>
  28 #include <rte_alarm.h>
  29 #include <rte_ether.h>
  30 #include <rte_ethdev_driver.h>
  31 #include <rte_ethdev_pci.h>
  32 #include <rte_random.h>
  33 #include <rte_dev.h>
  34 #include <rte_kvargs.h>
  35
  36 #include "common.h"
  37 #include "t4_regs.h"
  38 #include "t4_msg.h"
  39 #include "cxgbe.h"
  40 #include "clip_tbl.h"
  41
  42 /**
  43  * Allocate a chunk of memory. The allocated memory is cleared.
  44  */
  45 void *t4_alloc_mem(size_t size)
  46 {
  47         return rte_zmalloc(NULL, size, 0);
  48 }
  49
  50 /**
  51  * Free memory allocated through t4_alloc_mem().
  52  */
  53 void t4_free_mem(void *addr)
  54 {
  55         rte_free(addr);
  56 }
  57
  58 /*
  59  * Response queue handler for the FW event queue.
  60  */
  61 static int fwevtq_handler(struct sge_rspq *q, const __be64 *rsp,
  62                           __rte_unused const struct pkt_gl *gl)
  63 {
  64         u8 opcode = ((const struct rss_header *)rsp)->opcode;
  65
  66         rsp++;                                          /* skip RSS header */
  67
  68         /*
  69          * FW can send EGR_UPDATEs encapsulated in a CPL_FW4_MSG.
  70          */
  71         if (unlikely(opcode == CPL_FW4_MSG &&
  72                      ((const struct cpl_fw4_msg *)rsp)->type ==
  73                       FW_TYPE_RSSCPL)) {
  74                 rsp++;
  75                 opcode = ((const struct rss_header *)rsp)->opcode;
  76                 rsp++;
  77                 if (opcode != CPL_SGE_EGR_UPDATE) {
  78                         dev_err(q->adapter, "unexpected FW4/CPL %#x on FW event queue\n",
  79                                 opcode);
  80                         goto out;
  81                 }
  82         }
  83
  84         if (likely(opcode == CPL_SGE_EGR_UPDATE)) {
  85                 /* do nothing */
  86         } else if (opcode == CPL_FW6_MSG || opcode == CPL_FW4_MSG) {
  87                 const struct cpl_fw6_msg *msg = (const void *)rsp;
  88
  89                 t4_handle_fw_rpl(q->adapter, msg->data);
  90         } else if (opcode == CPL_ABORT_RPL_RSS) {
  91                 const struct cpl_abort_rpl_rss *p = (const void *)rsp;
  92
  93                 hash_del_filter_rpl(q->adapter, p);
  94         } else if (opcode == CPL_SET_TCB_RPL) {
  95                 const struct cpl_set_tcb_rpl *p = (const void *)rsp;
  96
  97                 filter_rpl(q->adapter, p);
  98         } else if (opcode == CPL_ACT_OPEN_RPL) {
  99                 const struct cpl_act_open_rpl *p = (const void *)rsp;
 100
 101                 hash_filter_rpl(q->adapter, p);
 102         } else {
 103                 dev_err(adapter, "unexpected CPL %#x on FW event queue\n",
 104                         opcode);
 105         }
 106 out:
 107         return 0;
 108 }
 109
 110 /**
 111  * Setup sge control queues to pass control information.
 112  */
 113 int setup_sge_ctrl_txq(struct adapter *adapter)
 114 {
 115         struct sge *s = &adapter->sge;
 116         int err = 0, i = 0;
 117
 118         for_each_port(adapter, i) {
 119                 char name[RTE_ETH_NAME_MAX_LEN];
 120                 struct sge_ctrl_txq *q = &s->ctrlq[i];
 121
 122                 q->q.size = 1024;
 123                 err = t4_sge_alloc_ctrl_txq(adapter, q,
 124                                             adapter->eth_dev,  i,
 125                                             s->fw_evtq.cntxt_id,
 126                                             rte_socket_id());
 127                 if (err) {
 128                         dev_err(adapter, "Failed to alloc ctrl txq. Err: %d",
 129                                 err);
 130                         goto out;
 131                 }
 132                 snprintf(name, sizeof(name), "cxgbe_ctrl_pool_%d", i);
 133                 q->mb_pool = rte_pktmbuf_pool_create(name, s->ctrlq[i].q.size,
 134                                                      RTE_CACHE_LINE_SIZE,
 135                                                      RTE_MBUF_PRIV_ALIGN,
 136                                                      RTE_MBUF_DEFAULT_BUF_SIZE,
 137                                                      SOCKET_ID_ANY);
 138                 if (!q->mb_pool) {
 139                         dev_err(adapter, "Can't create ctrl pool for port: %d",
 140                                 i);
 141                         err = -ENOMEM;
 142                         goto out;
 143                 }
 144         }
 145         return 0;
 146 out:
 147         t4_free_sge_resources(adapter);
 148         return err;
 149 }
 150
 151 /**
 152  * cxgbe_poll_for_completion: Poll rxq for completion
 153  * @q: rxq to poll
 154  * @us: microseconds to delay
 155  * @cnt: number of times to poll
 156  * @c: completion to check for 'done' status
 157  *
 158  * Polls the rxq for reples until completion is done or the count
 159  * expires.
 160  */
 161 int cxgbe_poll_for_completion(struct sge_rspq *q, unsigned int us,
 162                               unsigned int cnt, struct t4_completion *c)
 163 {
 164         unsigned int i;
 165         unsigned int work_done, budget = 4;
 166
 167         if (!c)
 168                 return -EINVAL;
 169
 170         for (i = 0; i < cnt; i++) {
 171                 cxgbe_poll(q, NULL, budget, &work_done);
 172                 t4_os_lock(&c->lock);
 173                 if (c->done) {
 174                         t4_os_unlock(&c->lock);
 175                         return 0;
 176                 }
 177                 t4_os_unlock(&c->lock);
 178                 udelay(us);
 179         }
 180         return -ETIMEDOUT;
 181 }
 182
 183 int setup_sge_fwevtq(struct adapter *adapter)
 184 {
 185         struct sge *s = &adapter->sge;
 186         int err = 0;
 187         int msi_idx = 0;
 188
 189         err = t4_sge_alloc_rxq(adapter, &s->fw_evtq, true, adapter->eth_dev,
 190                                msi_idx, NULL, fwevtq_handler, -1, NULL, 0,
 191                                rte_socket_id());
 192         return err;
 193 }
 194
 195 static int closest_timer(const struct sge *s, int time)
 196 {
 197         unsigned int i, match = 0;
 198         int delta, min_delta = INT_MAX;
 199
 200         for (i = 0; i < ARRAY_SIZE(s->timer_val); i++) {
 201                 delta = time - s->timer_val[i];
 202                 if (delta < 0)
 203                         delta = -delta;
 204                 if (delta < min_delta) {
 205                         min_delta = delta;
 206                         match = i;
 207                 }
 208         }
 209         return match;
 210 }
 211
 212 static int closest_thres(const struct sge *s, int thres)
 213 {
 214         unsigned int i, match = 0;
 215         int delta, min_delta = INT_MAX;
 216
 217         for (i = 0; i < ARRAY_SIZE(s->counter_val); i++) {
 218                 delta = thres - s->counter_val[i];
 219                 if (delta < 0)
 220                         delta = -delta;
 221                 if (delta < min_delta) {
 222                         min_delta = delta;
 223                         match = i;
 224                 }
 225         }
 226         return match;
 227 }
 228
 229 /**
 230  * cxgb4_set_rspq_intr_params - set a queue's interrupt holdoff parameters
 231  * @q: the Rx queue
 232  * @us: the hold-off time in us, or 0 to disable timer
 233  * @cnt: the hold-off packet count, or 0 to disable counter
 234  *
 235  * Sets an Rx queue's interrupt hold-off time and packet count.  At least
 236  * one of the two needs to be enabled for the queue to generate interrupts.
 237  */
 238 int cxgb4_set_rspq_intr_params(struct sge_rspq *q, unsigned int us,
 239                                unsigned int cnt)
 240 {
 241         struct adapter *adap = q->adapter;
 242         unsigned int timer_val;
 243
 244         if (cnt) {
 245                 int err;
 246                 u32 v, new_idx;
 247
 248                 new_idx = closest_thres(&adap->sge, cnt);
 249                 if (q->desc && q->pktcnt_idx != new_idx) {
 250                         /* the queue has already been created, update it */
 251                         v = V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DMAQ) |
 252                             V_FW_PARAMS_PARAM_X(
 253                             FW_PARAMS_PARAM_DMAQ_IQ_INTCNTTHRESH) |
 254                             V_FW_PARAMS_PARAM_YZ(q->cntxt_id);
 255                         err = t4_set_params(adap, adap->mbox, adap->pf, 0, 1,
 256                                             &v, &new_idx);
 257                         if (err)
 258                                 return err;
 259                 }
 260                 q->pktcnt_idx = new_idx;
 261         }
 262
 263         timer_val = (us == 0) ? X_TIMERREG_RESTART_COUNTER :
 264                                 closest_timer(&adap->sge, us);
 265
 266         if ((us | cnt) == 0)
 267                 q->intr_params = V_QINTR_TIMER_IDX(X_TIMERREG_UPDATE_CIDX);
 268         else
 269                 q->intr_params = V_QINTR_TIMER_IDX(timer_val) |
 270                                  V_QINTR_CNT_EN(cnt > 0);
 271         return 0;
 272 }
 273
 274 /**
 275  * Allocate an active-open TID and set it to the supplied value.
 276  */
 277 int cxgbe_alloc_atid(struct tid_info *t, void *data)
 278 {
 279         int atid = -1;
 280
 281         t4_os_lock(&t->atid_lock);
 282         if (t->afree) {
 283                 union aopen_entry *p = t->afree;
 284
 285                 atid = p - t->atid_tab;
 286                 t->afree = p->next;
 287                 p->data = data;
 288                 t->atids_in_use++;
 289         }
 290         t4_os_unlock(&t->atid_lock);
 291         return atid;
 292 }
 293
 294 /**
 295  * Release an active-open TID.
 296  */
 297 void cxgbe_free_atid(struct tid_info *t, unsigned int atid)
 298 {
 299         union aopen_entry *p = &t->atid_tab[atid];
 300
 301         t4_os_lock(&t->atid_lock);
 302         p->next = t->afree;
 303         t->afree = p;
 304         t->atids_in_use--;
 305         t4_os_unlock(&t->atid_lock);
 306 }
 307
 308 /**
 309  * Populate a TID_RELEASE WR.  Caller must properly size the skb.
 310  */
 311 static void mk_tid_release(struct rte_mbuf *mbuf, unsigned int tid)
 312 {
 313         struct cpl_tid_release *req;
 314
 315         req = rte_pktmbuf_mtod(mbuf, struct cpl_tid_release *);
 316         INIT_TP_WR_MIT_CPL(req, CPL_TID_RELEASE, tid);
 317 }
 318
 319 /**
 320  * Release a TID and inform HW.  If we are unable to allocate the release
 321  * message we defer to a work queue.
 322  */
 323 void cxgbe_remove_tid(struct tid_info *t, unsigned int chan, unsigned int tid,
 324                       unsigned short family)
 325 {
 326         struct rte_mbuf *mbuf;
 327         struct adapter *adap = container_of(t, struct adapter, tids);
 328
 329         WARN_ON(tid >= t->ntids);
 330
 331         if (t->tid_tab[tid]) {
 332                 t->tid_tab[tid] = NULL;
 333                 rte_atomic32_dec(&t->conns_in_use);
 334                 if (t->hash_base && tid >= t->hash_base) {
 335                         if (family == FILTER_TYPE_IPV4)
 336                                 rte_atomic32_dec(&t->hash_tids_in_use);
 337                 } else {
 338                         if (family == FILTER_TYPE_IPV4)
 339                                 rte_atomic32_dec(&t->tids_in_use);
 340                 }
 341         }
 342
 343         mbuf = rte_pktmbuf_alloc((&adap->sge.ctrlq[chan])->mb_pool);
 344         if (mbuf) {
 345                 mbuf->data_len = sizeof(struct cpl_tid_release);
 346                 mbuf->pkt_len = mbuf->data_len;
 347                 mk_tid_release(mbuf, tid);
 348                 t4_mgmt_tx(&adap->sge.ctrlq[chan], mbuf);
 349         }
 350 }
 351
 352 /**
 353  * Insert a TID.
 354  */
 355 void cxgbe_insert_tid(struct tid_info *t, void *data, unsigned int tid,
 356                       unsigned short family)
 357 {
 358         t->tid_tab[tid] = data;
 359         if (t->hash_base && tid >= t->hash_base) {
 360                 if (family == FILTER_TYPE_IPV4)
 361                         rte_atomic32_inc(&t->hash_tids_in_use);
 362         } else {
 363                 if (family == FILTER_TYPE_IPV4)
 364                         rte_atomic32_inc(&t->tids_in_use);
 365         }
 366
 367         rte_atomic32_inc(&t->conns_in_use);
 368 }
 369
 370 /**
 371  * Free TID tables.
 372  */
 373 static void tid_free(struct tid_info *t)
 374 {
 375         if (t->tid_tab) {
 376                 if (t->ftid_bmap)
 377                         rte_bitmap_free(t->ftid_bmap);
 378
 379                 if (t->ftid_bmap_array)
 380                         t4_os_free(t->ftid_bmap_array);
 381
 382                 t4_os_free(t->tid_tab);
 383         }
 384
 385         memset(t, 0, sizeof(struct tid_info));
 386 }
 387
 388 /**
 389  * Allocate and initialize the TID tables.  Returns 0 on success.
 390  */
 391 static int tid_init(struct tid_info *t)
 392 {
 393         size_t size;
 394         unsigned int ftid_bmap_size;
 395         unsigned int natids = t->natids;
 396         unsigned int max_ftids = t->nftids;
 397
 398         ftid_bmap_size = rte_bitmap_get_memory_footprint(t->nftids);
 399         size = t->ntids * sizeof(*t->tid_tab) +
 400                 max_ftids * sizeof(*t->ftid_tab) +
 401                 natids * sizeof(*t->atid_tab);
 402
 403         t->tid_tab = t4_os_alloc(size);
 404         if (!t->tid_tab)
 405                 return -ENOMEM;
 406
 407         t->atid_tab = (union aopen_entry *)&t->tid_tab[t->ntids];
 408         t->ftid_tab = (struct filter_entry *)&t->tid_tab[t->natids];
 409         t->ftid_bmap_array = t4_os_alloc(ftid_bmap_size);
 410         if (!t->ftid_bmap_array) {
 411                 tid_free(t);
 412                 return -ENOMEM;
 413         }
 414
 415         t4_os_lock_init(&t->atid_lock);
 416         t4_os_lock_init(&t->ftid_lock);
 417
 418         t->afree = NULL;
 419         t->atids_in_use = 0;
 420         rte_atomic32_init(&t->tids_in_use);
 421         rte_atomic32_set(&t->tids_in_use, 0);
 422         rte_atomic32_init(&t->conns_in_use);
 423         rte_atomic32_set(&t->conns_in_use, 0);
 424
 425         /* Setup the free list for atid_tab and clear the stid bitmap. */
 426         if (natids) {
 427                 while (--natids)
 428                         t->atid_tab[natids - 1].next = &t->atid_tab[natids];
 429                 t->afree = t->atid_tab;
 430         }
 431
 432         t->ftid_bmap = rte_bitmap_init(t->nftids, t->ftid_bmap_array,
 433                                        ftid_bmap_size);
 434         if (!t->ftid_bmap) {
 435                 tid_free(t);
 436                 return -ENOMEM;
 437         }
 438
 439         return 0;
 440 }
 441
 442 static inline bool is_x_1g_port(const struct link_config *lc)
 443 {
 444         return (lc->pcaps & FW_PORT_CAP32_SPEED_1G) != 0;
 445 }
 446
 447 static inline bool is_x_10g_port(const struct link_config *lc)
 448 {
 449         unsigned int speeds, high_speeds;
 450
 451         speeds = V_FW_PORT_CAP32_SPEED(G_FW_PORT_CAP32_SPEED(lc->pcaps));
 452         high_speeds = speeds &
 453                       ~(FW_PORT_CAP32_SPEED_100M | FW_PORT_CAP32_SPEED_1G);
 454
 455         return high_speeds != 0;
 456 }
 457
 458 inline void init_rspq(struct adapter *adap, struct sge_rspq *q,
 459                       unsigned int us, unsigned int cnt,
 460                       unsigned int size, unsigned int iqe_size)
 461 {
 462         q->adapter = adap;
 463         cxgb4_set_rspq_intr_params(q, us, cnt);
 464         q->iqe_len = iqe_size;
 465         q->size = size;
 466 }
 467
 468 int cfg_queue_count(struct rte_eth_dev *eth_dev)
 469 {
 470         struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);
 471         struct adapter *adap = pi->adapter;
 472         struct sge *s = &adap->sge;
 473         unsigned int max_queues = s->max_ethqsets / adap->params.nports;
 474
 475         if ((eth_dev->data->nb_rx_queues < 1) ||
 476             (eth_dev->data->nb_tx_queues < 1))
 477                 return -EINVAL;
 478
 479         if ((eth_dev->data->nb_rx_queues > max_queues) ||
 480             (eth_dev->data->nb_tx_queues > max_queues))
 481                 return -EINVAL;
 482
 483         if (eth_dev->data->nb_rx_queues > pi->rss_size)
 484                 return -EINVAL;
 485
 486         /* We must configure RSS, since config has changed*/
 487         pi->flags &= ~PORT_RSS_DONE;
 488
 489         pi->n_rx_qsets = eth_dev->data->nb_rx_queues;
 490         pi->n_tx_qsets = eth_dev->data->nb_tx_queues;
 491
 492         return 0;
 493 }
 494
 495 void cfg_queues(struct rte_eth_dev *eth_dev)
 496 {
 497         struct rte_config *config = rte_eal_get_configuration();
 498         struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);
 499         struct adapter *adap = pi->adapter;
 500         struct sge *s = &adap->sge;
 501         unsigned int i, nb_ports = 0, qidx = 0;
 502         unsigned int q_per_port = 0;
 503
 504         if (!(adap->flags & CFG_QUEUES)) {
 505                 for_each_port(adap, i) {
 506                         struct port_info *tpi = adap2pinfo(adap, i);
 507
 508                         nb_ports += (is_x_10g_port(&tpi->link_cfg)) ||
 509                                      is_x_1g_port(&tpi->link_cfg) ? 1 : 0;
 510                 }
 511
 512                 /*
 513                  * We default up to # of cores queues per 1G/10G port.
 514                  */
 515                 if (nb_ports)
 516                         q_per_port = (s->max_ethqsets -
 517                                      (adap->params.nports - nb_ports)) /
 518                                      nb_ports;
 519
 520                 if (q_per_port > config->lcore_count)
 521                         q_per_port = config->lcore_count;
 522
 523                 for_each_port(adap, i) {
 524                         struct port_info *pi = adap2pinfo(adap, i);
 525
 526                         pi->first_qset = qidx;
 527
 528                         /* Initially n_rx_qsets == n_tx_qsets */
 529                         pi->n_rx_qsets = (is_x_10g_port(&pi->link_cfg) ||
 530                                           is_x_1g_port(&pi->link_cfg)) ?
 531                                           q_per_port : 1;
 532                         pi->n_tx_qsets = pi->n_rx_qsets;
 533
 534                         if (pi->n_rx_qsets > pi->rss_size)
 535                                 pi->n_rx_qsets = pi->rss_size;
 536
 537                         qidx += pi->n_rx_qsets;
 538                 }
 539
 540                 for (i = 0; i < ARRAY_SIZE(s->ethrxq); i++) {
 541                         struct sge_eth_rxq *r = &s->ethrxq[i];
 542
 543                         init_rspq(adap, &r->rspq, 5, 32, 1024, 64);
 544                         r->usembufs = 1;
 545                         r->fl.size = (r->usembufs ? 1024 : 72);
 546                 }
 547
 548                 for (i = 0; i < ARRAY_SIZE(s->ethtxq); i++)
 549                         s->ethtxq[i].q.size = 1024;
 550
 551                 init_rspq(adap, &adap->sge.fw_evtq, 0, 0, 1024, 64);
 552                 adap->flags |= CFG_QUEUES;
 553         }
 554 }
 555
 556 void cxgbe_stats_get(struct port_info *pi, struct port_stats *stats)
 557 {
 558         t4_get_port_stats_offset(pi->adapter, pi->tx_chan, stats,
 559                                  &pi->stats_base);
 560 }
 561
 562 void cxgbe_stats_reset(struct port_info *pi)
 563 {
 564         t4_clr_port_stats(pi->adapter, pi->tx_chan);
 565 }
 566
 567 static void setup_memwin(struct adapter *adap)
 568 {
 569         u32 mem_win0_base;
 570
 571         /* For T5, only relative offset inside the PCIe BAR is passed */
 572         mem_win0_base = MEMWIN0_BASE;
 573
 574         /*
 575          * Set up memory window for accessing adapter memory ranges.  (Read
 576          * back MA register to ensure that changes propagate before we attempt
 577          * to use the new values.)
 578          */
 579         t4_write_reg(adap,
 580                      PCIE_MEM_ACCESS_REG(A_PCIE_MEM_ACCESS_BASE_WIN,
 581                                          MEMWIN_NIC),
 582                      mem_win0_base | V_BIR(0) |
 583                      V_WINDOW(ilog2(MEMWIN0_APERTURE) - X_WINDOW_SHIFT));
 584         t4_read_reg(adap,
 585                     PCIE_MEM_ACCESS_REG(A_PCIE_MEM_ACCESS_BASE_WIN,
 586                                         MEMWIN_NIC));
 587 }
 588
 589 int init_rss(struct adapter *adap)
 590 {
 591         unsigned int i;
 592
 593         if (is_pf4(adap)) {
 594                 int err;
 595
 596                 err = t4_init_rss_mode(adap, adap->mbox);
 597                 if (err)
 598                         return err;
 599         }
 600
 601         for_each_port(adap, i) {
 602                 struct port_info *pi = adap2pinfo(adap, i);
 603
 604                 pi->rss = rte_zmalloc(NULL, pi->rss_size * sizeof(u16), 0);
 605                 if (!pi->rss)
 606                         return -ENOMEM;
 607
 608                 pi->rss_hf = CXGBE_RSS_HF_ALL;
 609         }
 610         return 0;
 611 }
 612
 613 /**
 614  * Dump basic information about the adapter.
 615  */
 616 void print_adapter_info(struct adapter *adap)
 617 {
 618         /**
 619          * Hardware/Firmware/etc. Version/Revision IDs.
 620          */
 621         t4_dump_version_info(adap);
 622 }
 623
 624 void print_port_info(struct adapter *adap)
 625 {
 626         int i;
 627         char buf[80];
 628         struct rte_pci_addr *loc = &adap->pdev->addr;
 629
 630         for_each_port(adap, i) {
 631                 const struct port_info *pi = adap2pinfo(adap, i);
 632                 char *bufp = buf;
 633
 634                 if (pi->link_cfg.pcaps & FW_PORT_CAP32_SPEED_100M)
 635                         bufp += sprintf(bufp, "100M/");
 636                 if (pi->link_cfg.pcaps & FW_PORT_CAP32_SPEED_1G)
 637                         bufp += sprintf(bufp, "1G/");
 638                 if (pi->link_cfg.pcaps & FW_PORT_CAP32_SPEED_10G)
 639                         bufp += sprintf(bufp, "10G/");
 640                 if (pi->link_cfg.pcaps & FW_PORT_CAP32_SPEED_25G)
 641                         bufp += sprintf(bufp, "25G/");
 642                 if (pi->link_cfg.pcaps & FW_PORT_CAP32_SPEED_40G)
 643                         bufp += sprintf(bufp, "40G/");
 644                 if (pi->link_cfg.pcaps & FW_PORT_CAP32_SPEED_50G)
 645                         bufp += sprintf(bufp, "50G/");
 646                 if (pi->link_cfg.pcaps & FW_PORT_CAP32_SPEED_100G)
 647                         bufp += sprintf(bufp, "100G/");
 648                 if (bufp != buf)
 649                         --bufp;
 650                 sprintf(bufp, "BASE-%s",
 651                         t4_get_port_type_description(
 652                                         (enum fw_port_type)pi->port_type));
 653
 654                 dev_info(adap,
 655                          " " PCI_PRI_FMT " Chelsio rev %d %s %s\n",
 656                          loc->domain, loc->bus, loc->devid, loc->function,
 657                          CHELSIO_CHIP_RELEASE(adap->params.chip), buf,
 658                          (adap->flags & USING_MSIX) ? " MSI-X" :
 659                          (adap->flags & USING_MSI) ? " MSI" : "");
 660         }
 661 }
 662
 663 static int
 664 check_devargs_handler(__rte_unused const char *key, const char *value,
 665                       __rte_unused void *opaque)
 666 {
 667         if (strcmp(value, "1"))
 668                 return -1;
 669
 670         return 0;
 671 }
 672
 673 int cxgbe_get_devargs(struct rte_devargs *devargs, const char *key)
 674 {
 675         struct rte_kvargs *kvlist;
 676
 677         if (!devargs)
 678                 return 0;
 679
 680         kvlist = rte_kvargs_parse(devargs->args, NULL);
 681         if (!kvlist)
 682                 return 0;
 683
 684         if (!rte_kvargs_count(kvlist, key)) {
 685                 rte_kvargs_free(kvlist);
 686                 return 0;
 687         }
 688
 689         if (rte_kvargs_process(kvlist, key,
 690                                check_devargs_handler, NULL) < 0) {
 691                 rte_kvargs_free(kvlist);
 692                 return 0;
 693         }
 694         rte_kvargs_free(kvlist);
 695
 696         return 1;
 697 }
 698
 699 static void configure_vlan_types(struct adapter *adapter)
 700 {
 701         struct rte_pci_device *pdev = adapter->pdev;
 702         int i;
 703
 704         for_each_port(adapter, i) {
 705                 /* OVLAN Type 0x88a8 */
 706                 t4_set_reg_field(adapter, MPS_PORT_RX_OVLAN_REG(i, A_RX_OVLAN0),
 707                                  V_OVLAN_MASK(M_OVLAN_MASK) |
 708                                  V_OVLAN_ETYPE(M_OVLAN_ETYPE),
 709                                  V_OVLAN_MASK(M_OVLAN_MASK) |
 710                                  V_OVLAN_ETYPE(0x88a8));
 711                 /* OVLAN Type 0x9100 */
 712                 t4_set_reg_field(adapter, MPS_PORT_RX_OVLAN_REG(i, A_RX_OVLAN1),
 713                                  V_OVLAN_MASK(M_OVLAN_MASK) |
 714                                  V_OVLAN_ETYPE(M_OVLAN_ETYPE),
 715                                  V_OVLAN_MASK(M_OVLAN_MASK) |
 716                                  V_OVLAN_ETYPE(0x9100));
 717                 /* OVLAN Type 0x8100 */
 718                 t4_set_reg_field(adapter, MPS_PORT_RX_OVLAN_REG(i, A_RX_OVLAN2),
 719                                  V_OVLAN_MASK(M_OVLAN_MASK) |
 720                                  V_OVLAN_ETYPE(M_OVLAN_ETYPE),
 721                                  V_OVLAN_MASK(M_OVLAN_MASK) |
 722                                  V_OVLAN_ETYPE(0x8100));
 723
 724                 /* IVLAN 0X8100 */
 725                 t4_set_reg_field(adapter, MPS_PORT_RX_IVLAN(i),
 726                                  V_IVLAN_ETYPE(M_IVLAN_ETYPE),
 727                                  V_IVLAN_ETYPE(0x8100));
 728
 729                 t4_set_reg_field(adapter, MPS_PORT_RX_CTL(i),
 730                                  F_OVLAN_EN0 | F_OVLAN_EN1 |
 731                                  F_OVLAN_EN2 | F_IVLAN_EN,
 732                                  F_OVLAN_EN0 | F_OVLAN_EN1 |
 733                                  F_OVLAN_EN2 | F_IVLAN_EN);
 734         }
 735
 736         if (cxgbe_get_devargs(pdev->device.devargs, CXGBE_DEVARG_KEEP_OVLAN))
 737                 t4_tp_wr_bits_indirect(adapter, A_TP_INGRESS_CONFIG,
 738                                        V_RM_OVLAN(1), V_RM_OVLAN(0));
 739 }
 740
 741 static void configure_pcie_ext_tag(struct adapter *adapter)
 742 {
 743         u16 v;
 744         int pos = t4_os_find_pci_capability(adapter, PCI_CAP_ID_EXP);
 745
 746         if (!pos)
 747                 return;
 748
 749         if (pos > 0) {
 750                 t4_os_pci_read_cfg2(adapter, pos + PCI_EXP_DEVCTL, &v);
 751                 v |= PCI_EXP_DEVCTL_EXT_TAG;
 752                 t4_os_pci_write_cfg2(adapter, pos + PCI_EXP_DEVCTL, v);
 753                 if (is_t6(adapter->params.chip)) {
 754                         t4_set_reg_field(adapter, A_PCIE_CFG2,
 755                                          V_T6_TOTMAXTAG(M_T6_TOTMAXTAG),
 756                                          V_T6_TOTMAXTAG(7));
 757                         t4_set_reg_field(adapter, A_PCIE_CMD_CFG,
 758                                          V_T6_MINTAG(M_T6_MINTAG),
 759                                          V_T6_MINTAG(8));
 760                 } else {
 761                         t4_set_reg_field(adapter, A_PCIE_CFG2,
 762                                          V_TOTMAXTAG(M_TOTMAXTAG),
 763                                          V_TOTMAXTAG(3));
 764                         t4_set_reg_field(adapter, A_PCIE_CMD_CFG,
 765                                          V_MINTAG(M_MINTAG),
 766                                          V_MINTAG(8));
 767                 }
 768         }
 769 }
 770
 771 /* Figure out how many Queue Sets we can support */
 772 void configure_max_ethqsets(struct adapter *adapter)
 773 {
 774         unsigned int ethqsets;
 775
 776         /*
 777          * We need to reserve an Ingress Queue for the Asynchronous Firmware
 778          * Event Queue.
 779          *
 780          * For each Queue Set, we'll need the ability to allocate two Egress
 781          * Contexts -- one for the Ingress Queue Free List and one for the TX
 782          * Ethernet Queue.
 783          */
 784         if (is_pf4(adapter)) {
 785                 struct pf_resources *pfres = &adapter->params.pfres;
 786
 787                 ethqsets = pfres->niqflint - 1;
 788                 if (pfres->neq < ethqsets * 2)
 789                         ethqsets = pfres->neq / 2;
 790         } else {
 791                 struct vf_resources *vfres = &adapter->params.vfres;
 792
 793                 ethqsets = vfres->niqflint - 1;
 794                 if (vfres->nethctrl != ethqsets)
 795                         ethqsets = min(vfres->nethctrl, ethqsets);
 796                 if (vfres->neq < ethqsets * 2)
 797                         ethqsets = vfres->neq / 2;
 798         }
 799
 800         if (ethqsets > MAX_ETH_QSETS)
 801                 ethqsets = MAX_ETH_QSETS;
 802         adapter->sge.max_ethqsets = ethqsets;
 803 }
 804
 805 /*
 806  * Tweak configuration based on system architecture, etc.  Most of these have
 807  * defaults assigned to them by Firmware Configuration Files (if we're using
 808  * them) but need to be explicitly set if we're using hard-coded
 809  * initialization. So these are essentially common tweaks/settings for
 810  * Configuration Files and hard-coded initialization ...
 811  */
 812 static int adap_init0_tweaks(struct adapter *adapter)
 813 {
 814         u8 rx_dma_offset;
 815
 816         /*
 817          * Fix up various Host-Dependent Parameters like Page Size, Cache
 818          * Line Size, etc.  The firmware default is for a 4KB Page Size and
 819          * 64B Cache Line Size ...
 820          */
 821         t4_fixup_host_params_compat(adapter, CXGBE_PAGE_SIZE, L1_CACHE_BYTES,
 822                                     T5_LAST_REV);
 823
 824         /*
 825          * Keep the chip default offset to deliver Ingress packets into our
 826          * DMA buffers to zero
 827          */
 828         rx_dma_offset = 0;
 829         t4_set_reg_field(adapter, A_SGE_CONTROL, V_PKTSHIFT(M_PKTSHIFT),
 830                          V_PKTSHIFT(rx_dma_offset));
 831
 832         t4_set_reg_field(adapter, A_SGE_FLM_CFG,
 833                          V_CREDITCNT(M_CREDITCNT) | M_CREDITCNTPACKING,
 834                          V_CREDITCNT(3) | V_CREDITCNTPACKING(1));
 835
 836         t4_set_reg_field(adapter, A_SGE_INGRESS_RX_THRESHOLD,
 837                          V_THRESHOLD_3(M_THRESHOLD_3), V_THRESHOLD_3(32U));
 838
 839         t4_set_reg_field(adapter, A_SGE_CONTROL2, V_IDMAARBROUNDROBIN(1U),
 840                          V_IDMAARBROUNDROBIN(1U));
 841
 842         /*
 843          * Don't include the "IP Pseudo Header" in CPL_RX_PKT checksums: Linux
 844          * adds the pseudo header itself.
 845          */
 846         t4_tp_wr_bits_indirect(adapter, A_TP_INGRESS_CONFIG,
 847                                F_CSUM_HAS_PSEUDO_HDR, 0);
 848
 849         return 0;
 850 }
 851
 852 /*
 853  * Attempt to initialize the adapter via a Firmware Configuration File.
 854  */
 855 static int adap_init0_config(struct adapter *adapter, int reset)
 856 {
 857         struct fw_caps_config_cmd caps_cmd;
 858         unsigned long mtype = 0, maddr = 0;
 859         u32 finiver, finicsum, cfcsum;
 860         int ret;
 861         int config_issued = 0;
 862         int cfg_addr;
 863         char config_name[20];
 864
 865         /*
 866          * Reset device if necessary.
 867          */
 868         if (reset) {
 869                 ret = t4_fw_reset(adapter, adapter->mbox,
 870                                   F_PIORSTMODE | F_PIORST);
 871                 if (ret < 0) {
 872                         dev_warn(adapter, "Firmware reset failed, error %d\n",
 873                                  -ret);
 874                         goto bye;
 875                 }
 876         }
 877
 878         cfg_addr = t4_flash_cfg_addr(adapter);
 879         if (cfg_addr < 0) {
 880                 ret = cfg_addr;
 881                 dev_warn(adapter, "Finding address for firmware config file in flash failed, error %d\n",
 882                          -ret);
 883                 goto bye;
 884         }
 885
 886         strcpy(config_name, "On Flash");
 887         mtype = FW_MEMTYPE_CF_FLASH;
 888         maddr = cfg_addr;
 889
 890         /*
 891          * Issue a Capability Configuration command to the firmware to get it
 892          * to parse the Configuration File.  We don't use t4_fw_config_file()
 893          * because we want the ability to modify various features after we've
 894          * processed the configuration file ...
 895          */
 896         memset(&caps_cmd, 0, sizeof(caps_cmd));
 897         caps_cmd.op_to_write = cpu_to_be32(V_FW_CMD_OP(FW_CAPS_CONFIG_CMD) |
 898                                            F_FW_CMD_REQUEST | F_FW_CMD_READ);
 899         caps_cmd.cfvalid_to_len16 =
 900                 cpu_to_be32(F_FW_CAPS_CONFIG_CMD_CFVALID |
 901                             V_FW_CAPS_CONFIG_CMD_MEMTYPE_CF(mtype) |
 902                             V_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF(maddr >> 16) |
 903                             FW_LEN16(caps_cmd));
 904         ret = t4_wr_mbox(adapter, adapter->mbox, &caps_cmd, sizeof(caps_cmd),
 905                          &caps_cmd);
 906         /*
 907          * If the CAPS_CONFIG failed with an ENOENT (for a Firmware
 908          * Configuration File in FLASH), our last gasp effort is to use the
 909          * Firmware Configuration File which is embedded in the firmware.  A
 910          * very few early versions of the firmware didn't have one embedded
 911          * but we can ignore those.
 912          */
 913         if (ret == -ENOENT) {
 914                 dev_info(adapter, "%s: Going for embedded config in firmware..\n",
 915                          __func__);
 916
 917                 memset(&caps_cmd, 0, sizeof(caps_cmd));
 918                 caps_cmd.op_to_write =
 919                         cpu_to_be32(V_FW_CMD_OP(FW_CAPS_CONFIG_CMD) |
 920                                     F_FW_CMD_REQUEST | F_FW_CMD_READ);
 921                 caps_cmd.cfvalid_to_len16 = cpu_to_be32(FW_LEN16(caps_cmd));
 922                 ret = t4_wr_mbox(adapter, adapter->mbox, &caps_cmd,
 923                                  sizeof(caps_cmd), &caps_cmd);
 924                 strcpy(config_name, "Firmware Default");
 925         }
 926
 927         config_issued = 1;
 928         if (ret < 0)
 929                 goto bye;
 930
 931         finiver = be32_to_cpu(caps_cmd.finiver);
 932         finicsum = be32_to_cpu(caps_cmd.finicsum);
 933         cfcsum = be32_to_cpu(caps_cmd.cfcsum);
 934         if (finicsum != cfcsum)
 935                 dev_warn(adapter, "Configuration File checksum mismatch: [fini] csum=%#x, computed csum=%#x\n",
 936                          finicsum, cfcsum);
 937
 938         /*
 939          * If we're a pure NIC driver then disable all offloading facilities.
 940          * This will allow the firmware to optimize aspects of the hardware
 941          * configuration which will result in improved performance.
 942          */
 943         caps_cmd.niccaps &= cpu_to_be16(~FW_CAPS_CONFIG_NIC_ETHOFLD);
 944         caps_cmd.toecaps = 0;
 945         caps_cmd.iscsicaps = 0;
 946         caps_cmd.rdmacaps = 0;
 947         caps_cmd.fcoecaps = 0;
 948
 949         /*
 950          * And now tell the firmware to use the configuration we just loaded.
 951          */
 952         caps_cmd.op_to_write = cpu_to_be32(V_FW_CMD_OP(FW_CAPS_CONFIG_CMD) |
 953                                            F_FW_CMD_REQUEST | F_FW_CMD_WRITE);
 954         caps_cmd.cfvalid_to_len16 = htonl(FW_LEN16(caps_cmd));
 955         ret = t4_wr_mbox(adapter, adapter->mbox, &caps_cmd, sizeof(caps_cmd),
 956                          NULL);
 957         if (ret < 0) {
 958                 dev_warn(adapter, "Unable to finalize Firmware Capabilities %d\n",
 959                          -ret);
 960                 goto bye;
 961         }
 962
 963         /*
 964          * Tweak configuration based on system architecture, etc.
 965          */
 966         ret = adap_init0_tweaks(adapter);
 967         if (ret < 0) {
 968                 dev_warn(adapter, "Unable to do init0-tweaks %d\n", -ret);
 969                 goto bye;
 970         }
 971
 972         /*
 973          * And finally tell the firmware to initialize itself using the
 974          * parameters from the Configuration File.
 975          */
 976         ret = t4_fw_initialize(adapter, adapter->mbox);
 977         if (ret < 0) {
 978                 dev_warn(adapter, "Initializing Firmware failed, error %d\n",
 979                          -ret);
 980                 goto bye;
 981         }
 982
 983         /*
 984          * Return successfully and note that we're operating with parameters
 985          * not supplied by the driver, rather than from hard-wired
 986          * initialization constants buried in the driver.
 987          */
 988         dev_info(adapter,
 989                  "Successfully configured using Firmware Configuration File \"%s\", version %#x, computed checksum %#x\n",
 990                  config_name, finiver, cfcsum);
 991
 992         return 0;
 993
 994         /*
 995          * Something bad happened.  Return the error ...  (If the "error"
 996          * is that there's no Configuration File on the adapter we don't
 997          * want to issue a warning since this is fairly common.)
 998          */
 999 bye:
1000         if (config_issued && ret != -ENOENT)
1001                 dev_warn(adapter, "\"%s\" configuration file error %d\n",
1002                          config_name, -ret);
1003
1004         dev_debug(adapter, "%s: returning ret = %d ..\n", __func__, ret);
1005         return ret;
1006 }
1007
1008 static int adap_init0(struct adapter *adap)
1009 {
1010         struct fw_caps_config_cmd caps_cmd;
1011         int ret = 0;
1012         u32 v, port_vec;
1013         enum dev_state state;
1014         u32 params[7], val[7];
1015         int reset = 1;
1016         int mbox = adap->mbox;
1017
1018         /*
1019          * Contact FW, advertising Master capability.
1020          */
1021         ret = t4_fw_hello(adap, adap->mbox, adap->mbox, MASTER_MAY, &state);
1022         if (ret < 0) {
1023                 dev_err(adap, "%s: could not connect to FW, error %d\n",
1024                         __func__, -ret);
1025                 goto bye;
1026         }
1027
1028         CXGBE_DEBUG_MBOX(adap, "%s: adap->mbox = %d; ret = %d\n", __func__,
1029                          adap->mbox, ret);
1030
1031         if (ret == mbox)
1032                 adap->flags |= MASTER_PF;
1033
1034         if (state == DEV_STATE_INIT) {
1035                 /*
1036                  * Force halt and reset FW because a previous instance may have
1037                  * exited abnormally without properly shutting down
1038                  */
1039                 ret = t4_fw_halt(adap, adap->mbox, reset);
1040                 if (ret < 0) {
1041                         dev_err(adap, "Failed to halt. Exit.\n");
1042                         goto bye;
1043                 }
1044
1045                 ret = t4_fw_restart(adap, adap->mbox, reset);
1046                 if (ret < 0) {
1047                         dev_err(adap, "Failed to restart. Exit.\n");
1048                         goto bye;
1049                 }
1050                 state = (enum dev_state)((unsigned)state & ~DEV_STATE_INIT);
1051         }
1052
1053         t4_get_version_info(adap);
1054
1055         ret = t4_get_core_clock(adap, &adap->params.vpd);
1056         if (ret < 0) {
1057                 dev_err(adap, "%s: could not get core clock, error %d\n",
1058                         __func__, -ret);
1059                 goto bye;
1060         }
1061
1062         /*
1063          * If the firmware is initialized already (and we're not forcing a
1064          * master initialization), note that we're living with existing
1065          * adapter parameters.  Otherwise, it's time to try initializing the
1066          * adapter ...
1067          */
1068         if (state == DEV_STATE_INIT) {
1069                 dev_info(adap, "Coming up as %s: Adapter already initialized\n",
1070                          adap->flags & MASTER_PF ? "MASTER" : "SLAVE");
1071         } else {
1072                 dev_info(adap, "Coming up as MASTER: Initializing adapter\n");
1073
1074                 ret = adap_init0_config(adap, reset);
1075                 if (ret == -ENOENT) {
1076                         dev_err(adap,
1077                                 "No Configuration File present on adapter. Using hard-wired configuration parameters.\n");
1078                         goto bye;
1079                 }
1080         }
1081         if (ret < 0) {
1082                 dev_err(adap, "could not initialize adapter, error %d\n", -ret);
1083                 goto bye;
1084         }
1085
1086         /* Now that we've successfully configured and initialized the adapter
1087          * (or found it already initialized), we can ask the Firmware what
1088          * resources it has provisioned for us.
1089          */
1090         ret = t4_get_pfres(adap);
1091         if (ret) {
1092                 dev_err(adap->pdev_dev,
1093                         "Unable to retrieve resource provisioning info\n");
1094                 goto bye;
1095         }
1096
1097         /* Find out what ports are available to us. */
1098         v = V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) |
1099             V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_PORTVEC);
1100         ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 1, &v, &port_vec);
1101         if (ret < 0) {
1102                 dev_err(adap, "%s: failure in t4_query_params; error = %d\n",
1103                         __func__, ret);
1104                 goto bye;
1105         }
1106
1107         adap->params.nports = hweight32(port_vec);
1108         adap->params.portvec = port_vec;
1109
1110         dev_debug(adap, "%s: adap->params.nports = %u\n", __func__,
1111                   adap->params.nports);
1112
1113         /*
1114          * Give the SGE code a chance to pull in anything that it needs ...
1115          * Note that this must be called after we retrieve our VPD parameters
1116          * in order to know how to convert core ticks to seconds, etc.
1117          */
1118         ret = t4_sge_init(adap);
1119         if (ret < 0) {
1120                 dev_err(adap, "t4_sge_init failed with error %d\n",
1121                         -ret);
1122                 goto bye;
1123         }
1124
1125         /*
1126          * Grab some of our basic fundamental operating parameters.
1127          */
1128 #define FW_PARAM_DEV(param) \
1129         (V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) | \
1130          V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_##param))
1131
1132 #define FW_PARAM_PFVF(param) \
1133         (V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_PFVF) | \
1134          V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_PFVF_##param) |  \
1135          V_FW_PARAMS_PARAM_Y(0) | \
1136          V_FW_PARAMS_PARAM_Z(0))
1137
1138         params[0] = FW_PARAM_PFVF(FILTER_START);
1139         params[1] = FW_PARAM_PFVF(FILTER_END);
1140         ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 2, params, val);
1141         if (ret < 0)
1142                 goto bye;
1143         adap->tids.ftid_base = val[0];
1144         adap->tids.nftids = val[1] - val[0] + 1;
1145
1146         params[0] = FW_PARAM_PFVF(CLIP_START);
1147         params[1] = FW_PARAM_PFVF(CLIP_END);
1148         ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 2, params, val);
1149         if (ret < 0)
1150                 goto bye;
1151         adap->clipt_start = val[0];
1152         adap->clipt_end = val[1];
1153
1154         /*
1155          * Get device capabilities so we can determine what resources we need
1156          * to manage.
1157          */
1158         memset(&caps_cmd, 0, sizeof(caps_cmd));
1159         caps_cmd.op_to_write = htonl(V_FW_CMD_OP(FW_CAPS_CONFIG_CMD) |
1160                                      F_FW_CMD_REQUEST | F_FW_CMD_READ);
1161         caps_cmd.cfvalid_to_len16 = htonl(FW_LEN16(caps_cmd));
1162         ret = t4_wr_mbox(adap, adap->mbox, &caps_cmd, sizeof(caps_cmd),
1163                          &caps_cmd);
1164         if (ret < 0)
1165                 goto bye;
1166
1167         if ((caps_cmd.niccaps & cpu_to_be16(FW_CAPS_CONFIG_NIC_HASHFILTER)) &&
1168             is_t6(adap->params.chip)) {
1169                 if (init_hash_filter(adap) < 0)
1170                         goto bye;
1171         }
1172
1173         /* query tid-related parameters */
1174         params[0] = FW_PARAM_DEV(NTID);
1175         ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 1,
1176                               params, val);
1177         if (ret < 0)
1178                 goto bye;
1179         adap->tids.ntids = val[0];
1180         adap->tids.natids = min(adap->tids.ntids / 2, MAX_ATIDS);
1181
1182         /* If we're running on newer firmware, let it know that we're
1183          * prepared to deal with encapsulated CPL messages.  Older
1184          * firmware won't understand this and we'll just get
1185          * unencapsulated messages ...
1186          */
1187         params[0] = FW_PARAM_PFVF(CPLFW4MSG_ENCAP);
1188         val[0] = 1;
1189         (void)t4_set_params(adap, adap->mbox, adap->pf, 0, 1, params, val);
1190
1191         /*
1192          * Find out whether we're allowed to use the T5+ ULPTX MEMWRITE DSGL
1193          * capability.  Earlier versions of the firmware didn't have the
1194          * ULPTX_MEMWRITE_DSGL so we'll interpret a query failure as no
1195          * permission to use ULPTX MEMWRITE DSGL.
1196          */
1197         if (is_t4(adap->params.chip)) {
1198                 adap->params.ulptx_memwrite_dsgl = false;
1199         } else {
1200                 params[0] = FW_PARAM_DEV(ULPTX_MEMWRITE_DSGL);
1201                 ret = t4_query_params(adap, adap->mbox, adap->pf, 0,
1202                                       1, params, val);
1203                 adap->params.ulptx_memwrite_dsgl = (ret == 0 && val[0] != 0);
1204         }
1205
1206         /*
1207          * The MTU/MSS Table is initialized by now, so load their values.  If
1208          * we're initializing the adapter, then we'll make any modifications
1209          * we want to the MTU/MSS Table and also initialize the congestion
1210          * parameters.
1211          */
1212         t4_read_mtu_tbl(adap, adap->params.mtus, NULL);
1213         if (state != DEV_STATE_INIT) {
1214                 int i;
1215
1216                 /*
1217                  * The default MTU Table contains values 1492 and 1500.
1218                  * However, for TCP, it's better to have two values which are
1219                  * a multiple of 8 +/- 4 bytes apart near this popular MTU.
1220                  * This allows us to have a TCP Data Payload which is a
1221                  * multiple of 8 regardless of what combination of TCP Options
1222                  * are in use (always a multiple of 4 bytes) which is
1223                  * important for performance reasons.  For instance, if no
1224                  * options are in use, then we have a 20-byte IP header and a
1225                  * 20-byte TCP header.  In this case, a 1500-byte MSS would
1226                  * result in a TCP Data Payload of 1500 - 40 == 1460 bytes
1227                  * which is not a multiple of 8.  So using an MSS of 1488 in
1228                  * this case results in a TCP Data Payload of 1448 bytes which
1229                  * is a multiple of 8.  On the other hand, if 12-byte TCP Time
1230                  * Stamps have been negotiated, then an MTU of 1500 bytes
1231                  * results in a TCP Data Payload of 1448 bytes which, as
1232                  * above, is a multiple of 8 bytes ...
1233                  */
1234                 for (i = 0; i < NMTUS; i++)
1235                         if (adap->params.mtus[i] == 1492) {
1236                                 adap->params.mtus[i] = 1488;
1237                                 break;
1238                         }
1239
1240                 t4_load_mtus(adap, adap->params.mtus, adap->params.a_wnd,
1241                              adap->params.b_wnd);
1242         }
1243         t4_init_sge_params(adap);
1244         t4_init_tp_params(adap);
1245         configure_pcie_ext_tag(adap);
1246         configure_vlan_types(adap);
1247         configure_max_ethqsets(adap);
1248
1249         adap->params.drv_memwin = MEMWIN_NIC;
1250         adap->flags |= FW_OK;
1251         dev_debug(adap, "%s: returning zero..\n", __func__);
1252         return 0;
1253
1254         /*
1255          * Something bad happened.  If a command timed out or failed with EIO
1256          * FW does not operate within its spec or something catastrophic
1257          * happened to HW/FW, stop issuing commands.
1258          */
1259 bye:
1260         if (ret != -ETIMEDOUT && ret != -EIO)
1261                 t4_fw_bye(adap, adap->mbox);
1262         return ret;
1263 }
1264
1265 /**
1266  * t4_os_portmod_changed - handle port module changes
1267  * @adap: the adapter associated with the module change
1268  * @port_id: the port index whose module status has changed
1269  *
1270  * This is the OS-dependent handler for port module changes.  It is
1271  * invoked when a port module is removed or inserted for any OS-specific
1272  * processing.
1273  */
1274 void t4_os_portmod_changed(const struct adapter *adap, int port_id)
1275 {
1276         static const char * const mod_str[] = {
1277                 NULL, "LR", "SR", "ER", "passive DA", "active DA", "LRM"
1278         };
1279
1280         const struct port_info *pi = adap2pinfo(adap, port_id);
1281
1282         if (pi->mod_type == FW_PORT_MOD_TYPE_NONE)
1283                 dev_info(adap, "Port%d: port module unplugged\n", pi->port_id);
1284         else if (pi->mod_type < ARRAY_SIZE(mod_str))
1285                 dev_info(adap, "Port%d: %s port module inserted\n", pi->port_id,
1286                          mod_str[pi->mod_type]);
1287         else if (pi->mod_type == FW_PORT_MOD_TYPE_NOTSUPPORTED)
1288                 dev_info(adap, "Port%d: unsupported port module inserted\n",
1289                          pi->port_id);
1290         else if (pi->mod_type == FW_PORT_MOD_TYPE_UNKNOWN)
1291                 dev_info(adap, "Port%d: unknown port module inserted\n",
1292                          pi->port_id);
1293         else if (pi->mod_type == FW_PORT_MOD_TYPE_ERROR)
1294                 dev_info(adap, "Port%d: transceiver module error\n",
1295                          pi->port_id);
1296         else
1297                 dev_info(adap, "Port%d: unknown module type %d inserted\n",
1298                          pi->port_id, pi->mod_type);
1299 }
1300
1301 inline bool force_linkup(struct adapter *adap)
1302 {
1303         struct rte_pci_device *pdev = adap->pdev;
1304
1305         if (is_pf4(adap))
1306                 return false;   /* force_linkup not required for pf driver*/
1307         if (!cxgbe_get_devargs(pdev->device.devargs,
1308                                CXGBE_DEVARG_FORCE_LINK_UP))
1309                 return false;
1310         return true;
1311 }
1312
1313 /**
1314  * link_start - enable a port
1315  * @dev: the port to enable
1316  *
1317  * Performs the MAC and PHY actions needed to enable a port.
1318  */
1319 int link_start(struct port_info *pi)
1320 {
1321         struct adapter *adapter = pi->adapter;
1322         int ret;
1323         unsigned int mtu;
1324
1325         mtu = pi->eth_dev->data->dev_conf.rxmode.max_rx_pkt_len -
1326               (ETHER_HDR_LEN + ETHER_CRC_LEN);
1327
1328         /*
1329          * We do not set address filters and promiscuity here, the stack does
1330          * that step explicitly.
1331          */
1332         ret = t4_set_rxmode(adapter, adapter->mbox, pi->viid, mtu, -1, -1,
1333                             -1, 1, true);
1334         if (ret == 0) {
1335                 ret = t4_change_mac(adapter, adapter->mbox, pi->viid,
1336                                     pi->xact_addr_filt,
1337                                     (u8 *)&pi->eth_dev->data->mac_addrs[0],
1338                                     true, true);
1339                 if (ret >= 0) {
1340                         pi->xact_addr_filt = ret;
1341                         ret = 0;
1342                 }
1343         }
1344         if (ret == 0 && is_pf4(adapter))
1345                 ret = t4_link_l1cfg(adapter, adapter->mbox, pi->tx_chan,
1346                                     &pi->link_cfg);
1347         if (ret == 0) {
1348                 /*
1349                  * Enabling a Virtual Interface can result in an interrupt
1350                  * during the processing of the VI Enable command and, in some
1351                  * paths, result in an attempt to issue another command in the
1352                  * interrupt context.  Thus, we disable interrupts during the
1353                  * course of the VI Enable command ...
1354                  */
1355                 ret = t4_enable_vi_params(adapter, adapter->mbox, pi->viid,
1356                                           true, true, false);
1357         }
1358
1359         if (ret == 0 && force_linkup(adapter))
1360                 pi->eth_dev->data->dev_link.link_status = ETH_LINK_UP;
1361         return ret;
1362 }
1363
1364 /**
1365  * cxgbe_write_rss_conf - flash the RSS configuration for a given port
1366  * @pi: the port
1367  * @rss_hf: Hash configuration to apply
1368  */
1369 int cxgbe_write_rss_conf(const struct port_info *pi, uint64_t rss_hf)
1370 {
1371         struct adapter *adapter = pi->adapter;
1372         const struct sge_eth_rxq *rxq;
1373         u64 flags = 0;
1374         u16 rss;
1375         int err;
1376
1377         /*  Should never be called before setting up sge eth rx queues */
1378         if (!(adapter->flags & FULL_INIT_DONE)) {
1379                 dev_err(adap, "%s No RXQs available on port %d\n",
1380                         __func__, pi->port_id);
1381                 return -EINVAL;
1382         }
1383
1384         /* Don't allow unsupported hash functions */
1385         if (rss_hf & ~CXGBE_RSS_HF_ALL)
1386                 return -EINVAL;
1387
1388         if (rss_hf & CXGBE_RSS_HF_IPV4_MASK)
1389                 flags |= F_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN;
1390
1391         if (rss_hf & ETH_RSS_NONFRAG_IPV4_TCP)
1392                 flags |= F_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN;
1393
1394         if (rss_hf & ETH_RSS_NONFRAG_IPV4_UDP)
1395                 flags |= F_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN |
1396                          F_FW_RSS_VI_CONFIG_CMD_UDPEN;
1397
1398         if (rss_hf & CXGBE_RSS_HF_IPV6_MASK)
1399                 flags |= F_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN;
1400
1401         if (rss_hf & CXGBE_RSS_HF_TCP_IPV6_MASK)
1402                 flags |= F_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN |
1403                          F_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN;
1404
1405         if (rss_hf & CXGBE_RSS_HF_UDP_IPV6_MASK)
1406                 flags |= F_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN |
1407                          F_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN |
1408                          F_FW_RSS_VI_CONFIG_CMD_UDPEN;
1409
1410         rxq = &adapter->sge.ethrxq[pi->first_qset];
1411         rss = rxq[0].rspq.abs_id;
1412
1413         /* If Tunnel All Lookup isn't specified in the global RSS
1414          * Configuration, then we need to specify a default Ingress
1415          * Queue for any ingress packets which aren't hashed.  We'll
1416          * use our first ingress queue ...
1417          */
1418         err = t4_config_vi_rss(adapter, adapter->mbox, pi->viid,
1419                                flags, rss);
1420         return err;
1421 }
1422
1423 /**
1424  * cxgbe_write_rss - write the RSS table for a given port
1425  * @pi: the port
1426  * @queues: array of queue indices for RSS
1427  *
1428  * Sets up the portion of the HW RSS table for the port's VI to distribute
1429  * packets to the Rx queues in @queues.
1430  */
1431 int cxgbe_write_rss(const struct port_info *pi, const u16 *queues)
1432 {
1433         u16 *rss;
1434         int i, err;
1435         struct adapter *adapter = pi->adapter;
1436         const struct sge_eth_rxq *rxq;
1437
1438         /*  Should never be called before setting up sge eth rx queues */
1439         BUG_ON(!(adapter->flags & FULL_INIT_DONE));
1440
1441         rxq = &adapter->sge.ethrxq[pi->first_qset];
1442         rss = rte_zmalloc(NULL, pi->rss_size * sizeof(u16), 0);
1443         if (!rss)
1444                 return -ENOMEM;
1445
1446         /* map the queue indices to queue ids */
1447         for (i = 0; i < pi->rss_size; i++, queues++)
1448                 rss[i] = rxq[*queues].rspq.abs_id;
1449
1450         err = t4_config_rss_range(adapter, adapter->pf, pi->viid, 0,
1451                                   pi->rss_size, rss, pi->rss_size);
1452         rte_free(rss);
1453         return err;
1454 }
1455
1456 /**
1457  * setup_rss - configure RSS
1458  * @adapter: the adapter
1459  *
1460  * Sets up RSS to distribute packets to multiple receive queues.  We
1461  * configure the RSS CPU lookup table to distribute to the number of HW
1462  * receive queues, and the response queue lookup table to narrow that
1463  * down to the response queues actually configured for each port.
1464  * We always configure the RSS mapping for all ports since the mapping
1465  * table has plenty of entries.
1466  */
1467 int setup_rss(struct port_info *pi)
1468 {
1469         int j, err;
1470         struct adapter *adapter = pi->adapter;
1471
1472         dev_debug(adapter, "%s:  pi->rss_size = %u; pi->n_rx_qsets = %u\n",
1473                   __func__, pi->rss_size, pi->n_rx_qsets);
1474
1475         if (!(pi->flags & PORT_RSS_DONE)) {
1476                 if (adapter->flags & FULL_INIT_DONE) {
1477                         /* Fill default values with equal distribution */
1478                         for (j = 0; j < pi->rss_size; j++)
1479                                 pi->rss[j] = j % pi->n_rx_qsets;
1480
1481                         err = cxgbe_write_rss(pi, pi->rss);
1482                         if (err)
1483                                 return err;
1484
1485                         err = cxgbe_write_rss_conf(pi, pi->rss_hf);
1486                         if (err)
1487                                 return err;
1488                         pi->flags |= PORT_RSS_DONE;
1489                 }
1490         }
1491         return 0;
1492 }
1493
1494 /*
1495  * Enable NAPI scheduling and interrupt generation for all Rx queues.
1496  */
1497 static void enable_rx(struct adapter *adap, struct sge_rspq *q)
1498 {
1499         /* 0-increment GTS to start the timer and enable interrupts */
1500         t4_write_reg(adap, is_pf4(adap) ? MYPF_REG(A_SGE_PF_GTS) :
1501                                           T4VF_SGE_BASE_ADDR + A_SGE_VF_GTS,
1502                      V_SEINTARM(q->intr_params) |
1503                      V_INGRESSQID(q->cntxt_id));
1504 }
1505
1506 void cxgbe_enable_rx_queues(struct port_info *pi)
1507 {
1508         struct adapter *adap = pi->adapter;
1509         struct sge *s = &adap->sge;
1510         unsigned int i;
1511
1512         for (i = 0; i < pi->n_rx_qsets; i++)
1513                 enable_rx(adap, &s->ethrxq[pi->first_qset + i].rspq);
1514 }
1515
1516 /**
1517  * fw_caps_to_speed_caps - translate Firmware Port Caps to Speed Caps.
1518  * @port_type: Firmware Port Type
1519  * @fw_caps: Firmware Port Capabilities
1520  * @speed_caps: Device Info Speed Capabilities
1521  *
1522  * Translate a Firmware Port Capabilities specification to Device Info
1523  * Speed Capabilities.
1524  */
1525 static void fw_caps_to_speed_caps(enum fw_port_type port_type,
1526                                   unsigned int fw_caps,
1527                                   u32 *speed_caps)
1528 {
1529 #define SET_SPEED(__speed_name) \
1530         do { \
1531                 *speed_caps |= ETH_LINK_ ## __speed_name; \
1532         } while (0)
1533
1534 #define FW_CAPS_TO_SPEED(__fw_name) \
1535         do { \
1536                 if (fw_caps & FW_PORT_CAP32_ ## __fw_name) \
1537                         SET_SPEED(__fw_name); \
1538         } while (0)
1539
1540         switch (port_type) {
1541         case FW_PORT_TYPE_BT_SGMII:
1542         case FW_PORT_TYPE_BT_XFI:
1543         case FW_PORT_TYPE_BT_XAUI:
1544                 FW_CAPS_TO_SPEED(SPEED_100M);
1545                 FW_CAPS_TO_SPEED(SPEED_1G);
1546                 FW_CAPS_TO_SPEED(SPEED_10G);
1547                 break;
1548
1549         case FW_PORT_TYPE_KX4:
1550         case FW_PORT_TYPE_KX:
1551         case FW_PORT_TYPE_FIBER_XFI:
1552         case FW_PORT_TYPE_FIBER_XAUI:
1553         case FW_PORT_TYPE_SFP:
1554         case FW_PORT_TYPE_QSFP_10G:
1555         case FW_PORT_TYPE_QSA:
1556                 FW_CAPS_TO_SPEED(SPEED_1G);
1557                 FW_CAPS_TO_SPEED(SPEED_10G);
1558                 break;
1559
1560         case FW_PORT_TYPE_KR:
1561                 SET_SPEED(SPEED_10G);
1562                 break;
1563
1564         case FW_PORT_TYPE_BP_AP:
1565         case FW_PORT_TYPE_BP4_AP:
1566                 SET_SPEED(SPEED_1G);
1567                 SET_SPEED(SPEED_10G);
1568                 break;
1569
1570         case FW_PORT_TYPE_BP40_BA:
1571         case FW_PORT_TYPE_QSFP:
1572                 SET_SPEED(SPEED_40G);
1573                 break;
1574
1575         case FW_PORT_TYPE_CR_QSFP:
1576         case FW_PORT_TYPE_SFP28:
1577         case FW_PORT_TYPE_KR_SFP28:
1578                 FW_CAPS_TO_SPEED(SPEED_1G);
1579                 FW_CAPS_TO_SPEED(SPEED_10G);
1580                 FW_CAPS_TO_SPEED(SPEED_25G);
1581                 break;
1582
1583         case FW_PORT_TYPE_CR2_QSFP:
1584                 SET_SPEED(SPEED_50G);
1585                 break;
1586
1587         case FW_PORT_TYPE_KR4_100G:
1588         case FW_PORT_TYPE_CR4_QSFP:
1589                 FW_CAPS_TO_SPEED(SPEED_25G);
1590                 FW_CAPS_TO_SPEED(SPEED_40G);
1591                 FW_CAPS_TO_SPEED(SPEED_50G);
1592                 FW_CAPS_TO_SPEED(SPEED_100G);
1593                 break;
1594
1595         default:
1596                 break;
1597         }
1598
1599 #undef FW_CAPS_TO_SPEED
1600 #undef SET_SPEED
1601 }
1602
1603 /**
1604  * cxgbe_get_speed_caps - Fetch supported speed capabilities
1605  * @pi: Underlying port's info
1606  * @speed_caps: Device Info speed capabilities
1607  *
1608  * Fetch supported speed capabilities of the underlying port.
1609  */
1610 void cxgbe_get_speed_caps(struct port_info *pi, u32 *speed_caps)
1611 {
1612         *speed_caps = 0;
1613
1614         fw_caps_to_speed_caps(pi->port_type, pi->link_cfg.pcaps,
1615                               speed_caps);
1616
1617         if (!(pi->link_cfg.pcaps & FW_PORT_CAP32_ANEG))
1618                 *speed_caps |= ETH_LINK_SPEED_FIXED;
1619 }
1620
1621 /**
1622  * cxgbe_set_link_status - Set device link up or down.
1623  * @pi: Underlying port's info
1624  * @status: 0 - down, 1 - up
1625  *
1626  * Set the device link up or down.
1627  */
1628 int cxgbe_set_link_status(struct port_info *pi, bool status)
1629 {
1630         struct adapter *adapter = pi->adapter;
1631         int err = 0;
1632
1633         err = t4_enable_vi(adapter, adapter->mbox, pi->viid, status, status);
1634         if (err) {
1635                 dev_err(adapter, "%s: disable_vi failed: %d\n", __func__, err);
1636                 return err;
1637         }
1638
1639         if (!status)
1640                 t4_reset_link_config(adapter, pi->pidx);
1641
1642         return 0;
1643 }
1644
1645 /**
1646  * cxgb_up - enable the adapter
1647  * @adap: adapter being enabled
1648  *
1649  * Called when the first port is enabled, this function performs the
1650  * actions necessary to make an adapter operational, such as completing
1651  * the initialization of HW modules, and enabling interrupts.
1652  */
1653 int cxgbe_up(struct adapter *adap)
1654 {
1655         enable_rx(adap, &adap->sge.fw_evtq);
1656         t4_sge_tx_monitor_start(adap);
1657         if (is_pf4(adap))
1658                 t4_intr_enable(adap);
1659         adap->flags |= FULL_INIT_DONE;
1660
1661         /* TODO: deadman watchdog ?? */
1662         return 0;
1663 }
1664
1665 /*
1666  * Close the port
1667  */
1668 int cxgbe_down(struct port_info *pi)
1669 {
1670         return cxgbe_set_link_status(pi, false);
1671 }
1672
1673 /*
1674  * Release resources when all the ports have been stopped.
1675  */
1676 void cxgbe_close(struct adapter *adapter)
1677 {
1678         struct port_info *pi;
1679         int i;
1680
1681         if (adapter->flags & FULL_INIT_DONE) {
1682                 if (is_pf4(adapter))
1683                         t4_intr_disable(adapter);
1684                 tid_free(&adapter->tids);
1685                 t4_cleanup_clip_tbl(adapter);
1686                 t4_sge_tx_monitor_stop(adapter);
1687                 t4_free_sge_resources(adapter);
1688                 for_each_port(adapter, i) {
1689                         pi = adap2pinfo(adapter, i);
1690                         if (pi->viid != 0)
1691                                 t4_free_vi(adapter, adapter->mbox,
1692                                            adapter->pf, 0, pi->viid);
1693                         rte_free(pi->eth_dev->data->mac_addrs);
1694                         /* Skip first port since it'll be freed by DPDK stack */
1695                         if (i) {
1696                                 rte_free(pi->eth_dev->data->dev_private);
1697                                 rte_eth_dev_release_port(pi->eth_dev);
1698                         }
1699                 }
1700                 adapter->flags &= ~FULL_INIT_DONE;
1701         }
1702
1703         if (is_pf4(adapter) && (adapter->flags & FW_OK))
1704                 t4_fw_bye(adapter, adapter->mbox);
1705 }
1706
1707 int cxgbe_probe(struct adapter *adapter)
1708 {
1709         struct port_info *pi;
1710         int chip;
1711         int func, i;
1712         int err = 0;
1713         u32 whoami;
1714
1715         whoami = t4_read_reg(adapter, A_PL_WHOAMI);
1716         chip = t4_get_chip_type(adapter,
1717                         CHELSIO_PCI_ID_VER(adapter->pdev->id.device_id));
1718         if (chip < 0)
1719                 return chip;
1720
1721         func = CHELSIO_CHIP_VERSION(chip) <= CHELSIO_T5 ?
1722                G_SOURCEPF(whoami) : G_T6_SOURCEPF(whoami);
1723
1724         adapter->mbox = func;
1725         adapter->pf = func;
1726
1727         t4_os_lock_init(&adapter->mbox_lock);
1728         TAILQ_INIT(&adapter->mbox_list);
1729         t4_os_lock_init(&adapter->win0_lock);
1730
1731         err = t4_prep_adapter(adapter);
1732         if (err)
1733                 return err;
1734
1735         setup_memwin(adapter);
1736         err = adap_init0(adapter);
1737         if (err) {
1738                 dev_err(adapter, "%s: Adapter initialization failed, error %d\n",
1739                         __func__, err);
1740                 goto out_free;
1741         }
1742
1743         if (!is_t4(adapter->params.chip)) {
1744                 /*
1745                  * The userspace doorbell BAR is split evenly into doorbell
1746                  * regions, each associated with an egress queue.  If this
1747                  * per-queue region is large enough (at least UDBS_SEG_SIZE)
1748                  * then it can be used to submit a tx work request with an
1749                  * implied doorbell.  Enable write combining on the BAR if
1750                  * there is room for such work requests.
1751                  */
1752                 int s_qpp, qpp, num_seg;
1753
1754                 s_qpp = (S_QUEUESPERPAGEPF0 +
1755                         (S_QUEUESPERPAGEPF1 - S_QUEUESPERPAGEPF0) *
1756                         adapter->pf);
1757                 qpp = 1 << ((t4_read_reg(adapter,
1758                                 A_SGE_EGRESS_QUEUES_PER_PAGE_PF) >> s_qpp)
1759                                 & M_QUEUESPERPAGEPF0);
1760                 num_seg = CXGBE_PAGE_SIZE / UDBS_SEG_SIZE;
1761                 if (qpp > num_seg)
1762                         dev_warn(adapter, "Incorrect SGE EGRESS QUEUES_PER_PAGE configuration, continuing in debug mode\n");
1763
1764                 adapter->bar2 = (void *)adapter->pdev->mem_resource[2].addr;
1765                 if (!adapter->bar2) {
1766                         dev_err(adapter, "cannot map device bar2 region\n");
1767                         err = -ENOMEM;
1768                         goto out_free;
1769                 }
1770                 t4_write_reg(adapter, A_SGE_STAT_CFG, V_STATSOURCE_T5(7) |
1771                              V_STATMODE(0));
1772         }
1773
1774         for_each_port(adapter, i) {
1775                 const unsigned int numa_node = rte_socket_id();
1776                 char name[RTE_ETH_NAME_MAX_LEN];
1777                 struct rte_eth_dev *eth_dev;
1778
1779                 snprintf(name, sizeof(name), "%s_%d",
1780                          adapter->pdev->device.name, i);
1781
1782                 if (i == 0) {
1783                         /* First port is already allocated by DPDK */
1784                         eth_dev = adapter->eth_dev;
1785                         goto allocate_mac;
1786                 }
1787
1788                 /*
1789                  * now do all data allocation - for eth_dev structure,
1790                  * and internal (private) data for the remaining ports
1791                  */
1792
1793                 /* reserve an ethdev entry */
1794                 eth_dev = rte_eth_dev_allocate(name);
1795                 if (!eth_dev)
1796                         goto out_free;
1797
1798                 eth_dev->data->dev_private =
1799                         rte_zmalloc_socket(name, sizeof(struct port_info),
1800                                            RTE_CACHE_LINE_SIZE, numa_node);
1801                 if (!eth_dev->data->dev_private)
1802                         goto out_free;
1803
1804 allocate_mac:
1805                 pi = (struct port_info *)eth_dev->data->dev_private;
1806                 adapter->port[i] = pi;
1807                 pi->eth_dev = eth_dev;
1808                 pi->adapter = adapter;
1809                 pi->xact_addr_filt = -1;
1810                 pi->port_id = i;
1811                 pi->pidx = i;
1812
1813                 pi->eth_dev->device = &adapter->pdev->device;
1814                 pi->eth_dev->dev_ops = adapter->eth_dev->dev_ops;
1815                 pi->eth_dev->tx_pkt_burst = adapter->eth_dev->tx_pkt_burst;
1816                 pi->eth_dev->rx_pkt_burst = adapter->eth_dev->rx_pkt_burst;
1817
1818                 rte_eth_copy_pci_info(pi->eth_dev, adapter->pdev);
1819
1820                 pi->eth_dev->data->mac_addrs = rte_zmalloc(name,
1821                                                            ETHER_ADDR_LEN, 0);
1822                 if (!pi->eth_dev->data->mac_addrs) {
1823                         dev_err(adapter, "%s: Mem allocation failed for storing mac addr, aborting\n",
1824                                 __func__);
1825                         err = -1;
1826                         goto out_free;
1827                 }
1828
1829                 if (i > 0) {
1830                         /* First port will be notified by upper layer */
1831                         rte_eth_dev_probing_finish(eth_dev);
1832                 }
1833         }
1834
1835         if (adapter->flags & FW_OK) {
1836                 err = t4_port_init(adapter, adapter->mbox, adapter->pf, 0);
1837                 if (err) {
1838                         dev_err(adapter, "%s: t4_port_init failed with err %d\n",
1839                                 __func__, err);
1840                         goto out_free;
1841                 }
1842         }
1843
1844         cfg_queues(adapter->eth_dev);
1845
1846         print_adapter_info(adapter);
1847         print_port_info(adapter);
1848
1849         adapter->clipt = t4_init_clip_tbl(adapter->clipt_start,
1850                                           adapter->clipt_end);
1851         if (!adapter->clipt) {
1852                 /* We tolerate a lack of clip_table, giving up some
1853                  * functionality
1854                  */
1855                 dev_warn(adapter, "could not allocate CLIP. Continuing\n");
1856         }
1857
1858         if (tid_init(&adapter->tids) < 0) {
1859                 /* Disable filtering support */
1860                 dev_warn(adapter, "could not allocate TID table, "
1861                          "filter support disabled. Continuing\n");
1862         }
1863
1864         if (is_hashfilter(adapter)) {
1865                 if (t4_read_reg(adapter, A_LE_DB_CONFIG) & F_HASHEN) {
1866                         u32 hash_base, hash_reg;
1867
1868                         hash_reg = A_LE_DB_TID_HASHBASE;
1869                         hash_base = t4_read_reg(adapter, hash_reg);
1870                         adapter->tids.hash_base = hash_base / 4;
1871                 }
1872         } else {
1873                 /* Disable hash filtering support */
1874                 dev_warn(adapter,
1875                          "Maskless filter support disabled. Continuing\n");
1876         }
1877
1878         err = init_rss(adapter);
1879         if (err)
1880                 goto out_free;
1881
1882         return 0;
1883
1884 out_free:
1885         for_each_port(adapter, i) {
1886                 pi = adap2pinfo(adapter, i);
1887                 if (pi->viid != 0)
1888                         t4_free_vi(adapter, adapter->mbox, adapter->pf,
1889                                    0, pi->viid);
1890                 /* Skip first port since it'll be de-allocated by DPDK */
1891                 if (i == 0)
1892                         continue;
1893                 if (pi->eth_dev) {
1894                         if (pi->eth_dev->data->dev_private)
1895                                 rte_free(pi->eth_dev->data->dev_private);
1896                         rte_eth_dev_release_port(pi->eth_dev);
1897                 }
1898         }
1899
1900         if (adapter->flags & FW_OK)
1901                 t4_fw_bye(adapter, adapter->mbox);
1902         return -err;
1903 }