drivers/net/dpaa2/dpaa2_ethdev.h

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  *
   3  *   Copyright (c) 2015-2016 Freescale Semiconductor, Inc. All rights reserved.
   4  *   Copyright 2016 NXP
   5  *
   6  */
   7
   8 #ifndef _DPAA2_ETHDEV_H
   9 #define _DPAA2_ETHDEV_H
  10
  11 #include <rte_event_eth_rx_adapter.h>
  12
  13 #include <mc/fsl_dpni.h>
  14 #include <mc/fsl_mc_sys.h>
  15
  16 #define DPAA2_MIN_RX_BUF_SIZE 512
  17 #define DPAA2_MAX_RX_PKT_LEN  10240 /*WRIOP support*/
  18
  19 #define MAX_TCS                 DPNI_MAX_TC
  20 #define MAX_RX_QUEUES           16
  21 #define MAX_TX_QUEUES           16
  22
  23 /*default tc to be used for ,congestion, distribution etc configuration. */
  24 #define DPAA2_DEF_TC            0
  25
  26 /* Threshold for a Tx queue to *Enter* Congestion state.
  27  */
  28 #define CONG_ENTER_TX_THRESHOLD   512
  29
  30 /* Threshold for a queue to *Exit* Congestion state.
  31  */
  32 #define CONG_EXIT_TX_THRESHOLD    480
  33
  34 #define CONG_RETRY_COUNT 18000
  35
  36 /* RX queue tail drop threshold
  37  * currently considering 32 KB packets
  38  */
  39 #define CONG_THRESHOLD_RX_Q  (64 * 1024)
  40 #define CONG_RX_OAL     128
  41
  42 /* Size of the input SMMU mapped memory required by MC */
  43 #define DIST_PARAM_IOVA_SIZE 256
  44
  45 /* Enable TX Congestion control support
  46  * default is disable
  47  */
  48 #define DPAA2_TX_CGR_OFF        0x01
  49
  50 /* Disable RX tail drop, default is enable */
  51 #define DPAA2_RX_TAILDROP_OFF   0x04
  52
  53 #define DPAA2_RSS_OFFLOAD_ALL ( \
  54         ETH_RSS_IP | \
  55         ETH_RSS_UDP | \
  56         ETH_RSS_TCP | \
  57         ETH_RSS_SCTP)
  58
  59 /* LX2 FRC Parsed values (Little Endian) */
  60 #define DPAA2_PKT_TYPE_ETHER            0x0060
  61 #define DPAA2_PKT_TYPE_IPV4             0x0000
  62 #define DPAA2_PKT_TYPE_IPV6             0x0020
  63 #define DPAA2_PKT_TYPE_IPV4_EXT \
  64                         (0x0001 | DPAA2_PKT_TYPE_IPV4)
  65 #define DPAA2_PKT_TYPE_IPV6_EXT \
  66                         (0x0001 | DPAA2_PKT_TYPE_IPV6)
  67 #define DPAA2_PKT_TYPE_IPV4_TCP \
  68                         (0x000e | DPAA2_PKT_TYPE_IPV4)
  69 #define DPAA2_PKT_TYPE_IPV6_TCP \
  70                         (0x000e | DPAA2_PKT_TYPE_IPV6)
  71 #define DPAA2_PKT_TYPE_IPV4_UDP \
  72                         (0x0010 | DPAA2_PKT_TYPE_IPV4)
  73 #define DPAA2_PKT_TYPE_IPV6_UDP \
  74                         (0x0010 | DPAA2_PKT_TYPE_IPV6)
  75 #define DPAA2_PKT_TYPE_IPV4_SCTP        \
  76                         (0x000f | DPAA2_PKT_TYPE_IPV4)
  77 #define DPAA2_PKT_TYPE_IPV6_SCTP        \
  78                         (0x000f | DPAA2_PKT_TYPE_IPV6)
  79 #define DPAA2_PKT_TYPE_IPV4_ICMP \
  80                         (0x0003 | DPAA2_PKT_TYPE_IPV4_EXT)
  81 #define DPAA2_PKT_TYPE_IPV6_ICMP \
  82                         (0x0003 | DPAA2_PKT_TYPE_IPV6_EXT)
  83 #define DPAA2_PKT_TYPE_VLAN_1           0x0160
  84 #define DPAA2_PKT_TYPE_VLAN_2           0x0260
  85
  86 struct dpaa2_dev_priv {
  87         void *hw;
  88         int32_t hw_id;
  89         int32_t qdid;
  90         uint16_t token;
  91         uint8_t nb_tx_queues;
  92         uint8_t nb_rx_queues;
  93         void *rx_vq[MAX_RX_QUEUES];
  94         void *tx_vq[MAX_TX_QUEUES];
  95
  96         struct dpaa2_bp_list *bp_list; /**<Attached buffer pool list */
  97         uint32_t options;
  98         uint8_t max_mac_filters;
  99         uint8_t max_vlan_filters;
 100         uint8_t num_rx_tc;
 101         uint8_t flags; /*dpaa2 config flags */
 102 };
 103
 104 int dpaa2_setup_flow_dist(struct rte_eth_dev *eth_dev,
 105                           uint64_t req_dist_set);
 106
 107 int dpaa2_remove_flow_dist(struct rte_eth_dev *eth_dev,
 108                            uint8_t tc_index);
 109
 110 int dpaa2_attach_bp_list(struct dpaa2_dev_priv *priv, void *blist);
 111
 112 int dpaa2_eth_eventq_attach(const struct rte_eth_dev *dev,
 113                 int eth_rx_queue_id,
 114                 uint16_t dpcon_id,
 115                 const struct rte_event_eth_rx_adapter_queue_conf *queue_conf);
 116
 117 int dpaa2_eth_eventq_detach(const struct rte_eth_dev *dev,
 118                 int eth_rx_queue_id);
 119
 120 uint16_t dpaa2_dev_prefetch_rx(void *queue, struct rte_mbuf **bufs,
 121                                uint16_t nb_pkts);
 122 void dpaa2_dev_process_parallel_event(struct qbman_swp *swp,
 123                                       const struct qbman_fd *fd,
 124                                       const struct qbman_result *dq,
 125                                       struct dpaa2_queue *rxq,
 126                                       struct rte_event *ev);
 127 void dpaa2_dev_process_atomic_event(struct qbman_swp *swp,
 128                                     const struct qbman_fd *fd,
 129                                     const struct qbman_result *dq,
 130                                     struct dpaa2_queue *rxq,
 131                                     struct rte_event *ev);
 132 uint16_t dpaa2_dev_tx(void *queue, struct rte_mbuf **bufs, uint16_t nb_pkts);
 133 uint16_t dummy_dev_tx(void *queue, struct rte_mbuf **bufs, uint16_t nb_pkts);
 134 #endif /* _DPAA2_ETHDEV_H */