drivers/net/dpaa2/dpaa2_rxtx.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  *
   3  *   Copyright (c) 2016 Freescale Semiconductor, Inc. All rights reserved.
   4  *   Copyright 2016 NXP
   5  *
   6  */
   7
   8 #include <time.h>
   9 #include <net/if.h>
  10
  11 #include <rte_mbuf.h>
  12 #include <rte_ethdev_driver.h>
  13 #include <rte_malloc.h>
  14 #include <rte_memcpy.h>
  15 #include <rte_string_fns.h>
  16 #include <rte_dev.h>
  17
  18 #include <rte_fslmc.h>
  19 #include <fslmc_logs.h>
  20 #include <fslmc_vfio.h>
  21 #include <dpaa2_hw_pvt.h>
  22 #include <dpaa2_hw_dpio.h>
  23 #include <dpaa2_hw_mempool.h>
  24 #include <dpaa2_eventdev.h>
  25
  26 #include "dpaa2_ethdev.h"
  27 #include "base/dpaa2_hw_dpni_annot.h"
  28
  29 #define DPAA2_MBUF_TO_CONTIG_FD(_mbuf, _fd, _bpid)  do { \
  30         DPAA2_SET_FD_ADDR(_fd, DPAA2_MBUF_VADDR_TO_IOVA(_mbuf)); \
  31         DPAA2_SET_FD_LEN(_fd, _mbuf->data_len); \
  32         DPAA2_SET_ONLY_FD_BPID(_fd, _bpid); \
  33         DPAA2_SET_FD_OFFSET(_fd, _mbuf->data_off); \
  34         DPAA2_SET_FD_ASAL(_fd, DPAA2_ASAL_VAL); \
  35 } while (0)
  36
  37 static inline void __attribute__((hot))
  38 dpaa2_dev_rx_parse_frc(struct rte_mbuf *m, uint16_t frc)
  39 {
  40         PMD_RX_LOG(DEBUG, "frc = 0x%x   ", frc);
  41
  42         m->packet_type = RTE_PTYPE_UNKNOWN;
  43         switch (frc) {
  44         case DPAA2_PKT_TYPE_ETHER:
  45                 m->packet_type = RTE_PTYPE_L2_ETHER;
  46                 break;
  47         case DPAA2_PKT_TYPE_IPV4:
  48                 m->packet_type = RTE_PTYPE_L2_ETHER |
  49                         RTE_PTYPE_L3_IPV4;
  50                 break;
  51         case DPAA2_PKT_TYPE_IPV6:
  52                 m->packet_type = RTE_PTYPE_L2_ETHER |
  53                         RTE_PTYPE_L3_IPV6;
  54                 break;
  55         case DPAA2_PKT_TYPE_IPV4_EXT:
  56                 m->packet_type = RTE_PTYPE_L2_ETHER |
  57                         RTE_PTYPE_L3_IPV4_EXT;
  58                 break;
  59         case DPAA2_PKT_TYPE_IPV6_EXT:
  60                 m->packet_type = RTE_PTYPE_L2_ETHER |
  61                         RTE_PTYPE_L3_IPV6_EXT;
  62                 break;
  63         case DPAA2_PKT_TYPE_IPV4_TCP:
  64                 m->packet_type = RTE_PTYPE_L2_ETHER |
  65                         RTE_PTYPE_L3_IPV4 | RTE_PTYPE_L4_TCP;
  66                 break;
  67         case DPAA2_PKT_TYPE_IPV6_TCP:
  68                 m->packet_type = RTE_PTYPE_L2_ETHER |
  69                         RTE_PTYPE_L3_IPV6 | RTE_PTYPE_L4_TCP;
  70                 break;
  71         case DPAA2_PKT_TYPE_IPV4_UDP:
  72                 m->packet_type = RTE_PTYPE_L2_ETHER |
  73                         RTE_PTYPE_L3_IPV4 | RTE_PTYPE_L4_UDP;
  74                 break;
  75         case DPAA2_PKT_TYPE_IPV6_UDP:
  76                 m->packet_type = RTE_PTYPE_L2_ETHER |
  77                         RTE_PTYPE_L3_IPV6 | RTE_PTYPE_L4_UDP;
  78                 break;
  79         case DPAA2_PKT_TYPE_IPV4_SCTP:
  80                 m->packet_type = RTE_PTYPE_L2_ETHER |
  81                         RTE_PTYPE_L3_IPV4 | RTE_PTYPE_L4_SCTP;
  82                 break;
  83         case DPAA2_PKT_TYPE_IPV6_SCTP:
  84                 m->packet_type = RTE_PTYPE_L2_ETHER |
  85                         RTE_PTYPE_L3_IPV6 | RTE_PTYPE_L4_SCTP;
  86                 break;
  87         case DPAA2_PKT_TYPE_IPV4_ICMP:
  88                 m->packet_type = RTE_PTYPE_L2_ETHER |
  89                         RTE_PTYPE_L3_IPV4 | RTE_PTYPE_L4_ICMP;
  90                 break;
  91         case DPAA2_PKT_TYPE_IPV6_ICMP:
  92                 m->packet_type = RTE_PTYPE_L2_ETHER |
  93                         RTE_PTYPE_L3_IPV6 | RTE_PTYPE_L4_ICMP;
  94                 break;
  95         case DPAA2_PKT_TYPE_VLAN_1:
  96         case DPAA2_PKT_TYPE_VLAN_2:
  97                 m->ol_flags |= PKT_RX_VLAN;
  98                 break;
  99         /* More switch cases can be added */
 100         /* TODO: Add handling for checksum error check from FRC */
 101         default:
 102                 m->packet_type = RTE_PTYPE_UNKNOWN;
 103         }
 104 }
 105
 106 static inline uint32_t __attribute__((hot))
 107 dpaa2_dev_rx_parse_slow(uint64_t hw_annot_addr)
 108 {
 109         uint32_t pkt_type = RTE_PTYPE_UNKNOWN;
 110         struct dpaa2_annot_hdr *annotation =
 111                         (struct dpaa2_annot_hdr *)hw_annot_addr;
 112
 113         PMD_RX_LOG(DEBUG, "annotation = 0x%lx   ", annotation->word4);
 114         if (BIT_ISSET_AT_POS(annotation->word3, L2_ARP_PRESENT)) {
 115                 pkt_type = RTE_PTYPE_L2_ETHER_ARP;
 116                 goto parse_done;
 117         } else if (BIT_ISSET_AT_POS(annotation->word3, L2_ETH_MAC_PRESENT)) {
 118                 pkt_type = RTE_PTYPE_L2_ETHER;
 119         } else {
 120                 goto parse_done;
 121         }
 122
 123         if (BIT_ISSET_AT_POS(annotation->word4, L3_IPV4_1_PRESENT |
 124                              L3_IPV4_N_PRESENT)) {
 125                 pkt_type |= RTE_PTYPE_L3_IPV4;
 126                 if (BIT_ISSET_AT_POS(annotation->word4, L3_IP_1_OPT_PRESENT |
 127                         L3_IP_N_OPT_PRESENT))
 128                         pkt_type |= RTE_PTYPE_L3_IPV4_EXT;
 129
 130         } else if (BIT_ISSET_AT_POS(annotation->word4, L3_IPV6_1_PRESENT |
 131                   L3_IPV6_N_PRESENT)) {
 132                 pkt_type |= RTE_PTYPE_L3_IPV6;
 133                 if (BIT_ISSET_AT_POS(annotation->word4, L3_IP_1_OPT_PRESENT |
 134                     L3_IP_N_OPT_PRESENT))
 135                         pkt_type |= RTE_PTYPE_L3_IPV6_EXT;
 136         } else {
 137                 goto parse_done;
 138         }
 139
 140         if (BIT_ISSET_AT_POS(annotation->word4, L3_IP_1_FIRST_FRAGMENT |
 141             L3_IP_1_MORE_FRAGMENT |
 142             L3_IP_N_FIRST_FRAGMENT |
 143             L3_IP_N_MORE_FRAGMENT)) {
 144                 pkt_type |= RTE_PTYPE_L4_FRAG;
 145                 goto parse_done;
 146         } else {
 147                 pkt_type |= RTE_PTYPE_L4_NONFRAG;
 148         }
 149
 150         if (BIT_ISSET_AT_POS(annotation->word4, L3_PROTO_UDP_PRESENT))
 151                 pkt_type |= RTE_PTYPE_L4_UDP;
 152
 153         else if (BIT_ISSET_AT_POS(annotation->word4, L3_PROTO_TCP_PRESENT))
 154                 pkt_type |= RTE_PTYPE_L4_TCP;
 155
 156         else if (BIT_ISSET_AT_POS(annotation->word4, L3_PROTO_SCTP_PRESENT))
 157                 pkt_type |= RTE_PTYPE_L4_SCTP;
 158
 159         else if (BIT_ISSET_AT_POS(annotation->word4, L3_PROTO_ICMP_PRESENT))
 160                 pkt_type |= RTE_PTYPE_L4_ICMP;
 161
 162         else if (BIT_ISSET_AT_POS(annotation->word4, L3_IP_UNKNOWN_PROTOCOL))
 163                 pkt_type |= RTE_PTYPE_UNKNOWN;
 164
 165 parse_done:
 166         return pkt_type;
 167 }
 168
 169 static inline uint32_t __attribute__((hot))
 170 dpaa2_dev_rx_parse(struct rte_mbuf *mbuf, uint64_t hw_annot_addr)
 171 {
 172         struct dpaa2_annot_hdr *annotation =
 173                         (struct dpaa2_annot_hdr *)hw_annot_addr;
 174
 175         PMD_RX_LOG(DEBUG, "annotation = 0x%lx   ", annotation->word4);
 176
 177         /* Check offloads first */
 178         if (BIT_ISSET_AT_POS(annotation->word3,
 179                              L2_VLAN_1_PRESENT | L2_VLAN_N_PRESENT))
 180                 mbuf->ol_flags |= PKT_RX_VLAN;
 181
 182         if (BIT_ISSET_AT_POS(annotation->word8, DPAA2_ETH_FAS_L3CE))
 183                 mbuf->ol_flags |= PKT_RX_IP_CKSUM_BAD;
 184         else if (BIT_ISSET_AT_POS(annotation->word8, DPAA2_ETH_FAS_L4CE))
 185                 mbuf->ol_flags |= PKT_RX_L4_CKSUM_BAD;
 186
 187         /* Return some common types from parse processing */
 188         switch (annotation->word4) {
 189         case DPAA2_L3_IPv4:
 190                 return RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4;
 191         case DPAA2_L3_IPv6:
 192                 return  RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6;
 193         case DPAA2_L3_IPv4_TCP:
 194                 return  RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4 |
 195                                 RTE_PTYPE_L4_TCP;
 196         case DPAA2_L3_IPv4_UDP:
 197                 return  RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4 |
 198                                 RTE_PTYPE_L4_UDP;
 199         case DPAA2_L3_IPv6_TCP:
 200                 return  RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6 |
 201                                 RTE_PTYPE_L4_TCP;
 202         case DPAA2_L3_IPv6_UDP:
 203                 return  RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6 |
 204                                 RTE_PTYPE_L4_UDP;
 205         default:
 206                 PMD_RX_LOG(DEBUG, "Slow parse the parsing results\n");
 207                 break;
 208         }
 209
 210         return dpaa2_dev_rx_parse_slow(hw_annot_addr);
 211 }
 212
 213 static inline struct rte_mbuf *__attribute__((hot))
 214 eth_sg_fd_to_mbuf(const struct qbman_fd *fd)
 215 {
 216         struct qbman_sge *sgt, *sge;
 217         dma_addr_t sg_addr;
 218         int i = 0;
 219         uint64_t fd_addr;
 220         struct rte_mbuf *first_seg, *next_seg, *cur_seg, *temp;
 221
 222         fd_addr = (uint64_t)DPAA2_IOVA_TO_VADDR(DPAA2_GET_FD_ADDR(fd));
 223
 224         /* Get Scatter gather table address */
 225         sgt = (struct qbman_sge *)(fd_addr + DPAA2_GET_FD_OFFSET(fd));
 226
 227         sge = &sgt[i++];
 228         sg_addr = (uint64_t)DPAA2_IOVA_TO_VADDR(DPAA2_GET_FLE_ADDR(sge));
 229
 230         /* First Scatter gather entry */
 231         first_seg = DPAA2_INLINE_MBUF_FROM_BUF(sg_addr,
 232                 rte_dpaa2_bpid_info[DPAA2_GET_FD_BPID(fd)].meta_data_size);
 233         /* Prepare all the metadata for first segment */
 234         first_seg->buf_addr = (uint8_t *)sg_addr;
 235         first_seg->ol_flags = 0;
 236         first_seg->data_off = DPAA2_GET_FLE_OFFSET(sge);
 237         first_seg->data_len = sge->length  & 0x1FFFF;
 238         first_seg->pkt_len = DPAA2_GET_FD_LEN(fd);
 239         first_seg->nb_segs = 1;
 240         first_seg->next = NULL;
 241         if (dpaa2_svr_family == SVR_LX2160A)
 242                 dpaa2_dev_rx_parse_frc(first_seg,
 243                                 DPAA2_GET_FD_FRC_PARSE_SUM(fd));
 244         else
 245                 first_seg->packet_type = dpaa2_dev_rx_parse(first_seg,
 246                          (uint64_t)DPAA2_IOVA_TO_VADDR(DPAA2_GET_FD_ADDR(fd))
 247                          + DPAA2_FD_PTA_SIZE);
 248
 249         rte_mbuf_refcnt_set(first_seg, 1);
 250         cur_seg = first_seg;
 251         while (!DPAA2_SG_IS_FINAL(sge)) {
 252                 sge = &sgt[i++];
 253                 sg_addr = (uint64_t)DPAA2_IOVA_TO_VADDR(
 254                                 DPAA2_GET_FLE_ADDR(sge));
 255                 next_seg = DPAA2_INLINE_MBUF_FROM_BUF(sg_addr,
 256                         rte_dpaa2_bpid_info[DPAA2_GET_FLE_BPID(sge)].meta_data_size);
 257                 next_seg->buf_addr  = (uint8_t *)sg_addr;
 258                 next_seg->data_off  = DPAA2_GET_FLE_OFFSET(sge);
 259                 next_seg->data_len  = sge->length  & 0x1FFFF;
 260                 first_seg->nb_segs += 1;
 261                 rte_mbuf_refcnt_set(next_seg, 1);
 262                 cur_seg->next = next_seg;
 263                 next_seg->next = NULL;
 264                 cur_seg = next_seg;
 265         }
 266         temp = DPAA2_INLINE_MBUF_FROM_BUF(fd_addr,
 267                 rte_dpaa2_bpid_info[DPAA2_GET_FD_BPID(fd)].meta_data_size);
 268         rte_mbuf_refcnt_set(temp, 1);
 269         rte_pktmbuf_free_seg(temp);
 270
 271         return (void *)first_seg;
 272 }
 273
 274 static inline struct rte_mbuf *__attribute__((hot))
 275 eth_fd_to_mbuf(const struct qbman_fd *fd)
 276 {
 277         struct rte_mbuf *mbuf = DPAA2_INLINE_MBUF_FROM_BUF(
 278                 DPAA2_IOVA_TO_VADDR(DPAA2_GET_FD_ADDR(fd)),
 279                      rte_dpaa2_bpid_info[DPAA2_GET_FD_BPID(fd)].meta_data_size);
 280
 281         /* need to repopulated some of the fields,
 282          * as they may have changed in last transmission
 283          */
 284         mbuf->nb_segs = 1;
 285         mbuf->ol_flags = 0;
 286         mbuf->data_off = DPAA2_GET_FD_OFFSET(fd);
 287         mbuf->data_len = DPAA2_GET_FD_LEN(fd);
 288         mbuf->pkt_len = mbuf->data_len;
 289         mbuf->next = NULL;
 290         rte_mbuf_refcnt_set(mbuf, 1);
 291
 292         /* Parse the packet */
 293         /* parse results for LX2 are there in FRC field of FD.
 294          * For other DPAA2 platforms , parse results are after
 295          * the private - sw annotation area
 296          */
 297
 298         if (dpaa2_svr_family == SVR_LX2160A)
 299                 dpaa2_dev_rx_parse_frc(mbuf, DPAA2_GET_FD_FRC_PARSE_SUM(fd));
 300         else
 301                 mbuf->packet_type = dpaa2_dev_rx_parse(mbuf,
 302                         (uint64_t)DPAA2_IOVA_TO_VADDR(DPAA2_GET_FD_ADDR(fd))
 303                          + DPAA2_FD_PTA_SIZE);
 304
 305         PMD_RX_LOG(DEBUG, "to mbuf - mbuf =%p, mbuf->buf_addr =%p, off = %d,"
 306                 "fd_off=%d fd =%lx, meta = %d  bpid =%d, len=%d\n",
 307                 mbuf, mbuf->buf_addr, mbuf->data_off,
 308                 DPAA2_GET_FD_OFFSET(fd), DPAA2_GET_FD_ADDR(fd),
 309                 rte_dpaa2_bpid_info[DPAA2_GET_FD_BPID(fd)].meta_data_size,
 310                 DPAA2_GET_FD_BPID(fd), DPAA2_GET_FD_LEN(fd));
 311
 312         return mbuf;
 313 }
 314
 315 static int __attribute__ ((noinline)) __attribute__((hot))
 316 eth_mbuf_to_sg_fd(struct rte_mbuf *mbuf,
 317                   struct qbman_fd *fd, uint16_t bpid)
 318 {
 319         struct rte_mbuf *cur_seg = mbuf, *prev_seg, *mi, *temp;
 320         struct qbman_sge *sgt, *sge = NULL;
 321         int i;
 322
 323         if (unlikely(mbuf->ol_flags & PKT_TX_VLAN_PKT)) {
 324                 int ret = rte_vlan_insert(&mbuf);
 325                 if (ret)
 326                         return ret;
 327         }
 328
 329         temp = rte_pktmbuf_alloc(mbuf->pool);
 330         if (temp == NULL) {
 331                 PMD_TX_LOG(ERR, "No memory to allocate S/G table");
 332                 return -ENOMEM;
 333         }
 334
 335         DPAA2_SET_FD_ADDR(fd, DPAA2_MBUF_VADDR_TO_IOVA(temp));
 336         DPAA2_SET_FD_LEN(fd, mbuf->pkt_len);
 337         DPAA2_SET_ONLY_FD_BPID(fd, bpid);
 338         DPAA2_SET_FD_OFFSET(fd, temp->data_off);
 339         DPAA2_SET_FD_ASAL(fd, DPAA2_ASAL_VAL);
 340         DPAA2_FD_SET_FORMAT(fd, qbman_fd_sg);
 341         /*Set Scatter gather table and Scatter gather entries*/
 342         sgt = (struct qbman_sge *)(
 343                         (uint64_t)DPAA2_IOVA_TO_VADDR(DPAA2_GET_FD_ADDR(fd))
 344                         + DPAA2_GET_FD_OFFSET(fd));
 345
 346         for (i = 0; i < mbuf->nb_segs; i++) {
 347                 sge = &sgt[i];
 348                 /*Resetting the buffer pool id and offset field*/
 349                 sge->fin_bpid_offset = 0;
 350                 DPAA2_SET_FLE_ADDR(sge, DPAA2_MBUF_VADDR_TO_IOVA(cur_seg));
 351                 DPAA2_SET_FLE_OFFSET(sge, cur_seg->data_off);
 352                 sge->length = cur_seg->data_len;
 353                 if (RTE_MBUF_DIRECT(cur_seg)) {
 354                         if (rte_mbuf_refcnt_read(cur_seg) > 1) {
 355                                 /* If refcnt > 1, invalid bpid is set to ensure
 356                                  * buffer is not freed by HW
 357                                  */
 358                                 DPAA2_SET_FLE_IVP(sge);
 359                                 rte_mbuf_refcnt_update(cur_seg, -1);
 360                         } else
 361                                 DPAA2_SET_FLE_BPID(sge,
 362                                                 mempool_to_bpid(cur_seg->pool));
 363                         cur_seg = cur_seg->next;
 364                 } else {
 365                         /* Get owner MBUF from indirect buffer */
 366                         mi = rte_mbuf_from_indirect(cur_seg);
 367                         if (rte_mbuf_refcnt_read(mi) > 1) {
 368                                 /* If refcnt > 1, invalid bpid is set to ensure
 369                                  * owner buffer is not freed by HW
 370                                  */
 371                                 DPAA2_SET_FLE_IVP(sge);
 372                         } else {
 373                                 DPAA2_SET_FLE_BPID(sge,
 374                                                    mempool_to_bpid(mi->pool));
 375                                 rte_mbuf_refcnt_update(mi, 1);
 376                         }
 377                         prev_seg = cur_seg;
 378                         cur_seg = cur_seg->next;
 379                         prev_seg->next = NULL;
 380                         rte_pktmbuf_free(prev_seg);
 381                 }
 382         }
 383         DPAA2_SG_SET_FINAL(sge, true);
 384         return 0;
 385 }
 386
 387 static void
 388 eth_mbuf_to_fd(struct rte_mbuf *mbuf,
 389                struct qbman_fd *fd, uint16_t bpid) __attribute__((unused));
 390
 391 static void __attribute__ ((noinline)) __attribute__((hot))
 392 eth_mbuf_to_fd(struct rte_mbuf *mbuf,
 393                struct qbman_fd *fd, uint16_t bpid)
 394 {
 395         if (unlikely(mbuf->ol_flags & PKT_TX_VLAN_PKT)) {
 396                 if (rte_vlan_insert(&mbuf)) {
 397                         rte_pktmbuf_free(mbuf);
 398                         return;
 399                 }
 400         }
 401
 402         DPAA2_MBUF_TO_CONTIG_FD(mbuf, fd, bpid);
 403
 404         PMD_TX_LOG(DEBUG, "mbuf =%p, mbuf->buf_addr =%p, off = %d,"
 405                 "fd_off=%d fd =%lx, meta = %d  bpid =%d, len=%d\n",
 406                 mbuf, mbuf->buf_addr, mbuf->data_off,
 407                 DPAA2_GET_FD_OFFSET(fd), DPAA2_GET_FD_ADDR(fd),
 408                 rte_dpaa2_bpid_info[DPAA2_GET_FD_BPID(fd)].meta_data_size,
 409                 DPAA2_GET_FD_BPID(fd), DPAA2_GET_FD_LEN(fd));
 410         if (RTE_MBUF_DIRECT(mbuf)) {
 411                 if (rte_mbuf_refcnt_read(mbuf) > 1) {
 412                         DPAA2_SET_FD_IVP(fd);
 413                         rte_mbuf_refcnt_update(mbuf, -1);
 414                 }
 415         } else {
 416                 struct rte_mbuf *mi;
 417
 418                 mi = rte_mbuf_from_indirect(mbuf);
 419                 if (rte_mbuf_refcnt_read(mi) > 1)
 420                         DPAA2_SET_FD_IVP(fd);
 421                 else
 422                         rte_mbuf_refcnt_update(mi, 1);
 423                 rte_pktmbuf_free(mbuf);
 424         }
 425 }
 426
 427 static inline int __attribute__((hot))
 428 eth_copy_mbuf_to_fd(struct rte_mbuf *mbuf,
 429                     struct qbman_fd *fd, uint16_t bpid)
 430 {
 431         struct rte_mbuf *m;
 432         void *mb = NULL;
 433
 434         if (unlikely(mbuf->ol_flags & PKT_TX_VLAN_PKT)) {
 435                 int ret = rte_vlan_insert(&mbuf);
 436                 if (ret)
 437                         return ret;
 438         }
 439
 440         if (rte_dpaa2_mbuf_alloc_bulk(
 441                 rte_dpaa2_bpid_info[bpid].bp_list->mp, &mb, 1)) {
 442                 PMD_TX_LOG(WARNING, "Unable to allocated DPAA2 buffer");
 443                 return -1;
 444         }
 445         m = (struct rte_mbuf *)mb;
 446         memcpy((char *)m->buf_addr + mbuf->data_off,
 447                (void *)((char *)mbuf->buf_addr + mbuf->data_off),
 448                 mbuf->pkt_len);
 449
 450         /* Copy required fields */
 451         m->data_off = mbuf->data_off;
 452         m->ol_flags = mbuf->ol_flags;
 453         m->packet_type = mbuf->packet_type;
 454         m->tx_offload = mbuf->tx_offload;
 455
 456         DPAA2_MBUF_TO_CONTIG_FD(m, fd, bpid);
 457
 458         PMD_TX_LOG(DEBUG, " mbuf %p BMAN buf addr %p",
 459                    (void *)mbuf, mbuf->buf_addr);
 460
 461         PMD_TX_LOG(DEBUG, " fdaddr =%lx bpid =%d meta =%d off =%d, len =%d",
 462                    DPAA2_GET_FD_ADDR(fd),
 463                 DPAA2_GET_FD_BPID(fd),
 464                 rte_dpaa2_bpid_info[DPAA2_GET_FD_BPID(fd)].meta_data_size,
 465                 DPAA2_GET_FD_OFFSET(fd),
 466                 DPAA2_GET_FD_LEN(fd));
 467
 468         return 0;
 469 }
 470
 471 uint16_t
 472 dpaa2_dev_prefetch_rx(void *queue, struct rte_mbuf **bufs, uint16_t nb_pkts)
 473 {
 474         /* Function receive frames for a given device and VQ*/
 475         struct dpaa2_queue *dpaa2_q = (struct dpaa2_queue *)queue;
 476         struct qbman_result *dq_storage, *dq_storage1 = NULL;
 477         uint32_t fqid = dpaa2_q->fqid;
 478         int ret, num_rx = 0;
 479         uint8_t pending, status;
 480         struct qbman_swp *swp;
 481         const struct qbman_fd *fd, *next_fd;
 482         struct qbman_pull_desc pulldesc;
 483         struct queue_storage_info_t *q_storage = dpaa2_q->q_storage;
 484         struct rte_eth_dev *dev = dpaa2_q->dev;
 485
 486         if (unlikely(!DPAA2_PER_LCORE_DPIO)) {
 487                 ret = dpaa2_affine_qbman_swp();
 488                 if (ret) {
 489                         RTE_LOG(ERR, PMD, "Failure in affining portal\n");
 490                         return 0;
 491                 }
 492         }
 493         swp = DPAA2_PER_LCORE_PORTAL;
 494         if (unlikely(!q_storage->active_dqs)) {
 495                 q_storage->toggle = 0;
 496                 dq_storage = q_storage->dq_storage[q_storage->toggle];
 497                 q_storage->last_num_pkts = (nb_pkts > DPAA2_DQRR_RING_SIZE) ?
 498                                                DPAA2_DQRR_RING_SIZE : nb_pkts;
 499                 qbman_pull_desc_clear(&pulldesc);
 500                 qbman_pull_desc_set_numframes(&pulldesc,
 501                                               q_storage->last_num_pkts);
 502                 qbman_pull_desc_set_fq(&pulldesc, fqid);
 503                 qbman_pull_desc_set_storage(&pulldesc, dq_storage,
 504                         (dma_addr_t)(DPAA2_VADDR_TO_IOVA(dq_storage)), 1);
 505                 if (check_swp_active_dqs(DPAA2_PER_LCORE_DPIO->index)) {
 506                         while (!qbman_check_command_complete(
 507                                get_swp_active_dqs(DPAA2_PER_LCORE_DPIO->index)))
 508                                 ;
 509                         clear_swp_active_dqs(DPAA2_PER_LCORE_DPIO->index);
 510                 }
 511                 while (1) {
 512                         if (qbman_swp_pull(swp, &pulldesc)) {
 513                                 PMD_RX_LOG(WARNING, "VDQ command is not issued."
 514                                            "QBMAN is busy\n");
 515                                 /* Portal was busy, try again */
 516                                 continue;
 517                         }
 518                         break;
 519                 }
 520                 q_storage->active_dqs = dq_storage;
 521                 q_storage->active_dpio_id = DPAA2_PER_LCORE_DPIO->index;
 522                 set_swp_active_dqs(DPAA2_PER_LCORE_DPIO->index, dq_storage);
 523         }
 524
 525         dq_storage = q_storage->active_dqs;
 526         rte_prefetch0((void *)((uint64_t)(dq_storage)));
 527         rte_prefetch0((void *)((uint64_t)(dq_storage + 1)));
 528
 529         /* Prepare next pull descriptor. This will give space for the
 530          * prefething done on DQRR entries
 531          */
 532         q_storage->toggle ^= 1;
 533         dq_storage1 = q_storage->dq_storage[q_storage->toggle];
 534         qbman_pull_desc_clear(&pulldesc);
 535         qbman_pull_desc_set_numframes(&pulldesc, DPAA2_DQRR_RING_SIZE);
 536         qbman_pull_desc_set_fq(&pulldesc, fqid);
 537         qbman_pull_desc_set_storage(&pulldesc, dq_storage1,
 538                 (dma_addr_t)(DPAA2_VADDR_TO_IOVA(dq_storage1)), 1);
 539
 540         /* Check if the previous issued command is completed.
 541          * Also seems like the SWP is shared between the Ethernet Driver
 542          * and the SEC driver.
 543          */
 544         while (!qbman_check_command_complete(dq_storage))
 545                 ;
 546         if (dq_storage == get_swp_active_dqs(q_storage->active_dpio_id))
 547                 clear_swp_active_dqs(q_storage->active_dpio_id);
 548
 549         pending = 1;
 550
 551         do {
 552                 /* Loop until the dq_storage is updated with
 553                  * new token by QBMAN
 554                  */
 555                 while (!qbman_check_new_result(dq_storage))
 556                         ;
 557                 rte_prefetch0((void *)((uint64_t)(dq_storage + 2)));
 558                 /* Check whether Last Pull command is Expired and
 559                  * setting Condition for Loop termination
 560                  */
 561                 if (qbman_result_DQ_is_pull_complete(dq_storage)) {
 562                         pending = 0;
 563                         /* Check for valid frame. */
 564                         status = qbman_result_DQ_flags(dq_storage);
 565                         if (unlikely((status & QBMAN_DQ_STAT_VALIDFRAME) == 0))
 566                                 continue;
 567                 }
 568                 fd = qbman_result_DQ_fd(dq_storage);
 569
 570                 next_fd = qbman_result_DQ_fd(dq_storage + 1);
 571                 /* Prefetch Annotation address for the parse results */
 572                 rte_prefetch0((void *)(DPAA2_GET_FD_ADDR(next_fd)
 573                                 + DPAA2_FD_PTA_SIZE + 16));
 574
 575                 if (unlikely(DPAA2_FD_GET_FORMAT(fd) == qbman_fd_sg))
 576                         bufs[num_rx] = eth_sg_fd_to_mbuf(fd);
 577                 else
 578                         bufs[num_rx] = eth_fd_to_mbuf(fd);
 579                 bufs[num_rx]->port = dev->data->port_id;
 580
 581                 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
 582                         rte_vlan_strip(bufs[num_rx]);
 583
 584                 dq_storage++;
 585                 num_rx++;
 586         } while (pending);
 587
 588         if (check_swp_active_dqs(DPAA2_PER_LCORE_DPIO->index)) {
 589                 while (!qbman_check_command_complete(
 590                        get_swp_active_dqs(DPAA2_PER_LCORE_DPIO->index)))
 591                         ;
 592                 clear_swp_active_dqs(DPAA2_PER_LCORE_DPIO->index);
 593         }
 594         /* issue a volatile dequeue command for next pull */
 595         while (1) {
 596                 if (qbman_swp_pull(swp, &pulldesc)) {
 597                         PMD_RX_LOG(WARNING, "VDQ command is not issued."
 598                                    "QBMAN is busy\n");
 599                         continue;
 600                 }
 601                 break;
 602         }
 603         q_storage->active_dqs = dq_storage1;
 604         q_storage->active_dpio_id = DPAA2_PER_LCORE_DPIO->index;
 605         set_swp_active_dqs(DPAA2_PER_LCORE_DPIO->index, dq_storage1);
 606
 607         dpaa2_q->rx_pkts += num_rx;
 608
 609         return num_rx;
 610 }
 611
 612 void __attribute__((hot))
 613 dpaa2_dev_process_parallel_event(struct qbman_swp *swp,
 614                                  const struct qbman_fd *fd,
 615                                  const struct qbman_result *dq,
 616                                  struct dpaa2_queue *rxq,
 617                                  struct rte_event *ev)
 618 {
 619         rte_prefetch0((void *)(DPAA2_GET_FD_ADDR(fd) +
 620                 DPAA2_FD_PTA_SIZE + 16));
 621
 622         ev->flow_id = rxq->ev.flow_id;
 623         ev->sub_event_type = rxq->ev.sub_event_type;
 624         ev->event_type = RTE_EVENT_TYPE_ETHDEV;
 625         ev->op = RTE_EVENT_OP_NEW;
 626         ev->sched_type = rxq->ev.sched_type;
 627         ev->queue_id = rxq->ev.queue_id;
 628         ev->priority = rxq->ev.priority;
 629
 630         ev->mbuf = eth_fd_to_mbuf(fd);
 631
 632         qbman_swp_dqrr_consume(swp, dq);
 633 }
 634
 635 void __attribute__((hot))
 636 dpaa2_dev_process_atomic_event(struct qbman_swp *swp __attribute__((unused)),
 637                                const struct qbman_fd *fd,
 638                                const struct qbman_result *dq,
 639                                struct dpaa2_queue *rxq,
 640                                struct rte_event *ev)
 641 {
 642         uint8_t dqrr_index;
 643
 644         rte_prefetch0((void *)(DPAA2_GET_FD_ADDR(fd) +
 645                 DPAA2_FD_PTA_SIZE + 16));
 646
 647         ev->flow_id = rxq->ev.flow_id;
 648         ev->sub_event_type = rxq->ev.sub_event_type;
 649         ev->event_type = RTE_EVENT_TYPE_ETHDEV;
 650         ev->op = RTE_EVENT_OP_NEW;
 651         ev->sched_type = rxq->ev.sched_type;
 652         ev->queue_id = rxq->ev.queue_id;
 653         ev->priority = rxq->ev.priority;
 654
 655         ev->mbuf = eth_fd_to_mbuf(fd);
 656
 657         dqrr_index = qbman_get_dqrr_idx(dq);
 658         ev->mbuf->seqn = dqrr_index + 1;
 659         DPAA2_PER_LCORE_DQRR_SIZE++;
 660         DPAA2_PER_LCORE_DQRR_HELD |= 1 << dqrr_index;
 661         DPAA2_PER_LCORE_DQRR_MBUF(dqrr_index) = ev->mbuf;
 662 }
 663
 664 /*
 665  * Callback to handle sending packets through WRIOP based interface
 666  */
 667 uint16_t
 668 dpaa2_dev_tx(void *queue, struct rte_mbuf **bufs, uint16_t nb_pkts)
 669 {
 670         /* Function to transmit the frames to given device and VQ*/
 671         uint32_t loop, retry_count;
 672         int32_t ret;
 673         struct qbman_fd fd_arr[MAX_TX_RING_SLOTS];
 674         struct rte_mbuf *mi;
 675         uint32_t frames_to_send;
 676         struct rte_mempool *mp;
 677         struct qbman_eq_desc eqdesc;
 678         struct dpaa2_queue *dpaa2_q = (struct dpaa2_queue *)queue;
 679         struct qbman_swp *swp;
 680         uint16_t num_tx = 0;
 681         uint16_t bpid;
 682         struct rte_eth_dev *dev = dpaa2_q->dev;
 683         struct dpaa2_dev_priv *priv = dev->data->dev_private;
 684         uint32_t flags[MAX_TX_RING_SLOTS] = {0};
 685
 686         if (unlikely(!DPAA2_PER_LCORE_DPIO)) {
 687                 ret = dpaa2_affine_qbman_swp();
 688                 if (ret) {
 689                         RTE_LOG(ERR, PMD, "Failure in affining portal\n");
 690                         return 0;
 691                 }
 692         }
 693         swp = DPAA2_PER_LCORE_PORTAL;
 694
 695         PMD_TX_LOG(DEBUG, "===> dev =%p, fqid =%d", dev, dpaa2_q->fqid);
 696
 697         /*Prepare enqueue descriptor*/
 698         qbman_eq_desc_clear(&eqdesc);
 699         qbman_eq_desc_set_no_orp(&eqdesc, DPAA2_EQ_RESP_ERR_FQ);
 700         qbman_eq_desc_set_response(&eqdesc, 0, 0);
 701         qbman_eq_desc_set_qd(&eqdesc, priv->qdid,
 702                              dpaa2_q->flow_id, dpaa2_q->tc_index);
 703         /*Clear the unused FD fields before sending*/
 704         while (nb_pkts) {
 705                 /*Check if the queue is congested*/
 706                 retry_count = 0;
 707                 while (qbman_result_SCN_state(dpaa2_q->cscn)) {
 708                         retry_count++;
 709                         /* Retry for some time before giving up */
 710                         if (retry_count > CONG_RETRY_COUNT)
 711                                 goto skip_tx;
 712                 }
 713
 714                 frames_to_send = (nb_pkts >> 3) ? MAX_TX_RING_SLOTS : nb_pkts;
 715
 716                 for (loop = 0; loop < frames_to_send; loop++) {
 717                         if ((*bufs)->seqn) {
 718                                 uint8_t dqrr_index = (*bufs)->seqn - 1;
 719
 720                                 flags[loop] = QBMAN_ENQUEUE_FLAG_DCA |
 721                                                 dqrr_index;
 722                                 DPAA2_PER_LCORE_DQRR_SIZE--;
 723                                 DPAA2_PER_LCORE_DQRR_HELD &= ~(1 << dqrr_index);
 724                                 (*bufs)->seqn = DPAA2_INVALID_MBUF_SEQN;
 725                         }
 726
 727                         fd_arr[loop].simple.frc = 0;
 728                         DPAA2_RESET_FD_CTRL((&fd_arr[loop]));
 729                         DPAA2_SET_FD_FLC((&fd_arr[loop]), NULL);
 730                         if (likely(RTE_MBUF_DIRECT(*bufs))) {
 731                                 mp = (*bufs)->pool;
 732                                 /* Check the basic scenario and set
 733                                  * the FD appropriately here itself.
 734                                  */
 735                                 if (likely(mp && mp->ops_index ==
 736                                     priv->bp_list->dpaa2_ops_index &&
 737                                     (*bufs)->nb_segs == 1 &&
 738                                     rte_mbuf_refcnt_read((*bufs)) == 1)) {
 739                                         if (unlikely((*bufs)->ol_flags
 740                                                 & PKT_TX_VLAN_PKT)) {
 741                                                 ret = rte_vlan_insert(bufs);
 742                                                 if (ret)
 743                                                         goto send_n_return;
 744                                         }
 745                                         DPAA2_MBUF_TO_CONTIG_FD((*bufs),
 746                                         &fd_arr[loop], mempool_to_bpid(mp));
 747                                         bufs++;
 748                                         continue;
 749                                 }
 750                         } else {
 751                                 mi = rte_mbuf_from_indirect(*bufs);
 752                                 mp = mi->pool;
 753                         }
 754                         /* Not a hw_pkt pool allocated frame */
 755                         if (unlikely(!mp || !priv->bp_list)) {
 756                                 PMD_TX_LOG(ERR, "err: no bpool attached");
 757                                 goto send_n_return;
 758                         }
 759
 760                         if (mp->ops_index != priv->bp_list->dpaa2_ops_index) {
 761                                 PMD_TX_LOG(ERR, "non hw offload bufffer ");
 762                                 /* alloc should be from the default buffer pool
 763                                  * attached to this interface
 764                                  */
 765                                 bpid = priv->bp_list->buf_pool.bpid;
 766
 767                                 if (unlikely((*bufs)->nb_segs > 1)) {
 768                                         PMD_TX_LOG(ERR, "S/G support not added"
 769                                                 " for non hw offload buffer");
 770                                         goto send_n_return;
 771                                 }
 772                                 if (eth_copy_mbuf_to_fd(*bufs,
 773                                                         &fd_arr[loop], bpid)) {
 774                                         goto send_n_return;
 775                                 }
 776                                 /* free the original packet */
 777                                 rte_pktmbuf_free(*bufs);
 778                         } else {
 779                                 bpid = mempool_to_bpid(mp);
 780                                 if (unlikely((*bufs)->nb_segs > 1)) {
 781                                         if (eth_mbuf_to_sg_fd(*bufs,
 782                                                         &fd_arr[loop], bpid))
 783                                                 goto send_n_return;
 784                                 } else {
 785                                         eth_mbuf_to_fd(*bufs,
 786                                                        &fd_arr[loop], bpid);
 787                                 }
 788                         }
 789                         bufs++;
 790                 }
 791                 loop = 0;
 792                 while (loop < frames_to_send) {
 793                         loop += qbman_swp_enqueue_multiple(swp, &eqdesc,
 794                                         &fd_arr[loop], &flags[loop],
 795                                         frames_to_send - loop);
 796                 }
 797
 798                 num_tx += frames_to_send;
 799                 nb_pkts -= frames_to_send;
 800         }
 801         dpaa2_q->tx_pkts += num_tx;
 802         return num_tx;
 803
 804 send_n_return:
 805         /* send any already prepared fd */
 806         if (loop) {
 807                 unsigned int i = 0;
 808
 809                 while (i < loop) {
 810                         i += qbman_swp_enqueue_multiple(swp, &eqdesc,
 811                                                         &fd_arr[i],
 812                                                         &flags[loop],
 813                                                         loop - i);
 814                 }
 815                 num_tx += loop;
 816         }
 817 skip_tx:
 818         dpaa2_q->tx_pkts += num_tx;
 819         return num_tx;
 820 }
 821
 822 /**
 823  * Dummy DPDK callback for TX.
 824  *
 825  * This function is used to temporarily replace the real callback during
 826  * unsafe control operations on the queue, or in case of error.
 827  *
 828  * @param dpdk_txq
 829  *   Generic pointer to TX queue structure.
 830  * @param[in] pkts
 831  *   Packets to transmit.
 832  * @param pkts_n
 833  *   Number of packets in array.
 834  *
 835  * @return
 836  *   Number of packets successfully transmitted (<= pkts_n).
 837  */
 838 uint16_t
 839 dummy_dev_tx(void *queue, struct rte_mbuf **bufs, uint16_t nb_pkts)
 840 {
 841         (void)queue;
 842         (void)bufs;
 843         (void)nb_pkts;
 844         return 0;
 845 }