drivers/net/e1000/base/e1000_82541.c

   1 /*******************************************************************************
   2
   3 Copyright (c) 2001-2015, Intel Corporation
   4 All rights reserved.
   5
   6 Redistribution and use in source and binary forms, with or without
   7 modification, are permitted provided that the following conditions are met:
   8
   9  1. Redistributions of source code must retain the above copyright notice,
  10     this list of conditions and the following disclaimer.
  11
  12  2. Redistributions in binary form must reproduce the above copyright
  13     notice, this list of conditions and the following disclaimer in the
  14     documentation and/or other materials provided with the distribution.
  15
  16  3. Neither the name of the Intel Corporation nor the names of its
  17     contributors may be used to endorse or promote products derived from
  18     this software without specific prior written permission.
  19
  20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
  24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  30 POSSIBILITY OF SUCH DAMAGE.
  31
  32 ***************************************************************************/
  33
  34 /*
  35  * 82541EI Gigabit Ethernet Controller
  36  * 82541ER Gigabit Ethernet Controller
  37  * 82541GI Gigabit Ethernet Controller
  38  * 82541PI Gigabit Ethernet Controller
  39  * 82547EI Gigabit Ethernet Controller
  40  * 82547GI Gigabit Ethernet Controller
  41  */
  42
  43 #include "e1000_api.h"
  44
  45 STATIC s32  e1000_init_phy_params_82541(struct e1000_hw *hw);
  46 STATIC s32  e1000_init_nvm_params_82541(struct e1000_hw *hw);
  47 STATIC s32  e1000_init_mac_params_82541(struct e1000_hw *hw);
  48 STATIC s32  e1000_reset_hw_82541(struct e1000_hw *hw);
  49 STATIC s32  e1000_init_hw_82541(struct e1000_hw *hw);
  50 STATIC s32  e1000_get_link_up_info_82541(struct e1000_hw *hw, u16 *speed,
  51                                          u16 *duplex);
  52 STATIC s32  e1000_phy_hw_reset_82541(struct e1000_hw *hw);
  53 STATIC s32  e1000_setup_copper_link_82541(struct e1000_hw *hw);
  54 STATIC s32  e1000_check_for_link_82541(struct e1000_hw *hw);
  55 STATIC s32  e1000_get_cable_length_igp_82541(struct e1000_hw *hw);
  56 STATIC s32  e1000_set_d3_lplu_state_82541(struct e1000_hw *hw,
  57                                           bool active);
  58 STATIC s32  e1000_setup_led_82541(struct e1000_hw *hw);
  59 STATIC s32  e1000_cleanup_led_82541(struct e1000_hw *hw);
  60 STATIC void e1000_clear_hw_cntrs_82541(struct e1000_hw *hw);
  61 STATIC s32  e1000_config_dsp_after_link_change_82541(struct e1000_hw *hw,
  62                                                      bool link_up);
  63 STATIC s32  e1000_phy_init_script_82541(struct e1000_hw *hw);
  64 STATIC void e1000_power_down_phy_copper_82541(struct e1000_hw *hw);
  65
  66 STATIC const u16 e1000_igp_cable_length_table[] = {
  67         5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 10, 10, 10, 10, 10,
  68         10, 10, 20, 20, 20, 20, 20, 25, 25, 25, 25, 25, 25, 25, 30, 30, 30, 30,
  69         40, 40, 40, 40, 40, 40, 40, 40, 40, 50, 50, 50, 50, 50, 50, 50, 60, 60,
  70         60, 60, 60, 60, 60, 60, 60, 70, 70, 70, 70, 70, 70, 80, 80, 80, 80, 80,
  71         80, 90, 90, 90, 90, 90, 90, 90, 90, 90, 100, 100, 100, 100, 100, 100,
  72         100, 100, 100, 100, 100, 100, 100, 100, 110, 110, 110, 110, 110, 110,
  73         110, 110, 110, 110, 110, 110, 110, 110, 110, 110, 110, 110, 120, 120,
  74         120, 120, 120, 120, 120, 120, 120, 120};
  75 #define IGP01E1000_AGC_LENGTH_TABLE_SIZE \
  76                 (sizeof(e1000_igp_cable_length_table) / \
  77                  sizeof(e1000_igp_cable_length_table[0]))
  78
  79 /**
  80  *  e1000_init_phy_params_82541 - Init PHY func ptrs.
  81  *  @hw: pointer to the HW structure
  82  **/
  83 STATIC s32 e1000_init_phy_params_82541(struct e1000_hw *hw)
  84 {
  85         struct e1000_phy_info *phy = &hw->phy;
  86         s32 ret_val;
  87
  88         DEBUGFUNC("e1000_init_phy_params_82541");
  89
  90         phy->addr               = 1;
  91         phy->autoneg_mask       = AUTONEG_ADVERTISE_SPEED_DEFAULT;
  92         phy->reset_delay_us     = 10000;
  93         phy->type               = e1000_phy_igp;
  94
  95         /* Function Pointers */
  96         phy->ops.check_polarity = e1000_check_polarity_igp;
  97         phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_igp;
  98         phy->ops.get_cable_length = e1000_get_cable_length_igp_82541;
  99         phy->ops.get_cfg_done   = e1000_get_cfg_done_generic;
 100         phy->ops.get_info       = e1000_get_phy_info_igp;
 101         phy->ops.read_reg       = e1000_read_phy_reg_igp;
 102         phy->ops.reset          = e1000_phy_hw_reset_82541;
 103         phy->ops.set_d3_lplu_state = e1000_set_d3_lplu_state_82541;
 104         phy->ops.write_reg      = e1000_write_phy_reg_igp;
 105         phy->ops.power_up       = e1000_power_up_phy_copper;
 106         phy->ops.power_down     = e1000_power_down_phy_copper_82541;
 107
 108         ret_val = e1000_get_phy_id(hw);
 109         if (ret_val)
 110                 goto out;
 111
 112         /* Verify phy id */
 113         if (phy->id != IGP01E1000_I_PHY_ID) {
 114                 ret_val = -E1000_ERR_PHY;
 115                 goto out;
 116         }
 117
 118 out:
 119         return ret_val;
 120 }
 121
 122 /**
 123  *  e1000_init_nvm_params_82541 - Init NVM func ptrs.
 124  *  @hw: pointer to the HW structure
 125  **/
 126 STATIC s32 e1000_init_nvm_params_82541(struct e1000_hw *hw)
 127 {
 128         struct e1000_nvm_info *nvm = &hw->nvm;
 129         s32 ret_val = E1000_SUCCESS;
 130         u32 eecd = E1000_READ_REG(hw, E1000_EECD);
 131         u16 size;
 132
 133         DEBUGFUNC("e1000_init_nvm_params_82541");
 134
 135         switch (nvm->override) {
 136         case e1000_nvm_override_spi_large:
 137                 nvm->type = e1000_nvm_eeprom_spi;
 138                 eecd |= E1000_EECD_ADDR_BITS;
 139                 break;
 140         case e1000_nvm_override_spi_small:
 141                 nvm->type = e1000_nvm_eeprom_spi;
 142                 eecd &= ~E1000_EECD_ADDR_BITS;
 143                 break;
 144         case e1000_nvm_override_microwire_large:
 145                 nvm->type = e1000_nvm_eeprom_microwire;
 146                 eecd |= E1000_EECD_SIZE;
 147                 break;
 148         case e1000_nvm_override_microwire_small:
 149                 nvm->type = e1000_nvm_eeprom_microwire;
 150                 eecd &= ~E1000_EECD_SIZE;
 151                 break;
 152         default:
 153                 nvm->type = eecd & E1000_EECD_TYPE ? e1000_nvm_eeprom_spi
 154                             : e1000_nvm_eeprom_microwire;
 155                 break;
 156         }
 157
 158         if (nvm->type == e1000_nvm_eeprom_spi) {
 159                 nvm->address_bits = (eecd & E1000_EECD_ADDR_BITS) ? 16 : 8;
 160                 nvm->delay_usec = 1;
 161                 nvm->opcode_bits = 8;
 162                 nvm->page_size = (eecd & E1000_EECD_ADDR_BITS) ? 32 : 8;
 163
 164                 /* Function Pointers */
 165                 nvm->ops.acquire        = e1000_acquire_nvm_generic;
 166                 nvm->ops.read           = e1000_read_nvm_spi;
 167                 nvm->ops.release        = e1000_release_nvm_generic;
 168                 nvm->ops.update         = e1000_update_nvm_checksum_generic;
 169                 nvm->ops.valid_led_default = e1000_valid_led_default_generic;
 170                 nvm->ops.validate       = e1000_validate_nvm_checksum_generic;
 171                 nvm->ops.write          = e1000_write_nvm_spi;
 172
 173                 /*
 174                  * nvm->word_size must be discovered after the pointers
 175                  * are set so we can verify the size from the nvm image
 176                  * itself.  Temporarily set it to a dummy value so the
 177                  * read will work.
 178                  */
 179                 nvm->word_size = 64;
 180                 ret_val = nvm->ops.read(hw, NVM_CFG, 1, &size);
 181                 if (ret_val)
 182                         goto out;
 183                 size = (size & NVM_SIZE_MASK) >> NVM_SIZE_SHIFT;
 184                 /*
 185                  * if size != 0, it can be added to a constant and become
 186                  * the left-shift value to set the word_size.  Otherwise,
 187                  * word_size stays at 64.
 188                  */
 189                 if (size) {
 190                         size += NVM_WORD_SIZE_BASE_SHIFT_82541;
 191                         nvm->word_size = 1 << size;
 192                 }
 193         } else {
 194                 nvm->address_bits = (eecd & E1000_EECD_ADDR_BITS) ? 8 : 6;
 195                 nvm->delay_usec = 50;
 196                 nvm->opcode_bits = 3;
 197                 nvm->word_size = (eecd & E1000_EECD_ADDR_BITS) ? 256 : 64;
 198
 199                 /* Function Pointers */
 200                 nvm->ops.acquire        = e1000_acquire_nvm_generic;
 201                 nvm->ops.read           = e1000_read_nvm_microwire;
 202                 nvm->ops.release        = e1000_release_nvm_generic;
 203                 nvm->ops.update         = e1000_update_nvm_checksum_generic;
 204                 nvm->ops.valid_led_default = e1000_valid_led_default_generic;
 205                 nvm->ops.validate       = e1000_validate_nvm_checksum_generic;
 206                 nvm->ops.write          = e1000_write_nvm_microwire;
 207         }
 208
 209 out:
 210         return ret_val;
 211 }
 212
 213 /**
 214  *  e1000_init_mac_params_82541 - Init MAC func ptrs.
 215  *  @hw: pointer to the HW structure
 216  **/
 217 STATIC s32 e1000_init_mac_params_82541(struct e1000_hw *hw)
 218 {
 219         struct e1000_mac_info *mac = &hw->mac;
 220
 221         DEBUGFUNC("e1000_init_mac_params_82541");
 222
 223         /* Set media type */
 224         hw->phy.media_type = e1000_media_type_copper;
 225         /* Set mta register count */
 226         mac->mta_reg_count = 128;
 227         /* Set rar entry count */
 228         mac->rar_entry_count = E1000_RAR_ENTRIES;
 229         /* Set if part includes ASF firmware */
 230         mac->asf_firmware_present = true;
 231
 232         /* Function Pointers */
 233
 234         /* bus type/speed/width */
 235         mac->ops.get_bus_info = e1000_get_bus_info_pci_generic;
 236         /* function id */
 237         mac->ops.set_lan_id = e1000_set_lan_id_single_port;
 238         /* reset */
 239         mac->ops.reset_hw = e1000_reset_hw_82541;
 240         /* hw initialization */
 241         mac->ops.init_hw = e1000_init_hw_82541;
 242         /* link setup */
 243         mac->ops.setup_link = e1000_setup_link_generic;
 244         /* physical interface link setup */
 245         mac->ops.setup_physical_interface = e1000_setup_copper_link_82541;
 246         /* check for link */
 247         mac->ops.check_for_link = e1000_check_for_link_82541;
 248         /* link info */
 249         mac->ops.get_link_up_info = e1000_get_link_up_info_82541;
 250         /* multicast address update */
 251         mac->ops.update_mc_addr_list = e1000_update_mc_addr_list_generic;
 252         /* writing VFTA */
 253         mac->ops.write_vfta = e1000_write_vfta_generic;
 254         /* clearing VFTA */
 255         mac->ops.clear_vfta = e1000_clear_vfta_generic;
 256         /* ID LED init */
 257         mac->ops.id_led_init = e1000_id_led_init_generic;
 258         /* setup LED */
 259         mac->ops.setup_led = e1000_setup_led_82541;
 260         /* cleanup LED */
 261         mac->ops.cleanup_led = e1000_cleanup_led_82541;
 262         /* turn on/off LED */
 263         mac->ops.led_on = e1000_led_on_generic;
 264         mac->ops.led_off = e1000_led_off_generic;
 265         /* clear hardware counters */
 266         mac->ops.clear_hw_cntrs = e1000_clear_hw_cntrs_82541;
 267
 268         return E1000_SUCCESS;
 269 }
 270
 271 /**
 272  *  e1000_init_function_pointers_82541 - Init func ptrs.
 273  *  @hw: pointer to the HW structure
 274  *
 275  *  Called to initialize all function pointers and parameters.
 276  **/
 277 void e1000_init_function_pointers_82541(struct e1000_hw *hw)
 278 {
 279         DEBUGFUNC("e1000_init_function_pointers_82541");
 280
 281         hw->mac.ops.init_params = e1000_init_mac_params_82541;
 282         hw->nvm.ops.init_params = e1000_init_nvm_params_82541;
 283         hw->phy.ops.init_params = e1000_init_phy_params_82541;
 284 }
 285
 286 /**
 287  *  e1000_reset_hw_82541 - Reset hardware
 288  *  @hw: pointer to the HW structure
 289  *
 290  *  This resets the hardware into a known state.
 291  **/
 292 STATIC s32 e1000_reset_hw_82541(struct e1000_hw *hw)
 293 {
 294         u32 ledctl, ctrl, manc;
 295
 296         DEBUGFUNC("e1000_reset_hw_82541");
 297
 298         DEBUGOUT("Masking off all interrupts\n");
 299         E1000_WRITE_REG(hw, E1000_IMC, 0xFFFFFFFF);
 300
 301         E1000_WRITE_REG(hw, E1000_RCTL, 0);
 302         E1000_WRITE_REG(hw, E1000_TCTL, E1000_TCTL_PSP);
 303         E1000_WRITE_FLUSH(hw);
 304
 305         /*
 306          * Delay to allow any outstanding PCI transactions to complete
 307          * before resetting the device.
 308          */
 309         msec_delay(10);
 310
 311         ctrl = E1000_READ_REG(hw, E1000_CTRL);
 312
 313         /* Must reset the Phy before resetting the MAC */
 314         if ((hw->mac.type == e1000_82541) || (hw->mac.type == e1000_82547)) {
 315                 E1000_WRITE_REG(hw, E1000_CTRL, (ctrl | E1000_CTRL_PHY_RST));
 316                 E1000_WRITE_FLUSH(hw);
 317                 msec_delay(5);
 318         }
 319
 320         DEBUGOUT("Issuing a global reset to 82541/82547 MAC\n");
 321         switch (hw->mac.type) {
 322         case e1000_82541:
 323         case e1000_82541_rev_2:
 324                 /*
 325                  * These controllers can't ack the 64-bit write when
 326                  * issuing the reset, so we use IO-mapping as a
 327                  * workaround to issue the reset.
 328                  */
 329                 E1000_WRITE_REG_IO(hw, E1000_CTRL, ctrl | E1000_CTRL_RST);
 330                 break;
 331         default:
 332                 E1000_WRITE_REG(hw, E1000_CTRL, ctrl | E1000_CTRL_RST);
 333                 break;
 334         }
 335
 336         /* Wait for NVM reload */
 337         msec_delay(20);
 338
 339         /* Disable HW ARPs on ASF enabled adapters */
 340         manc = E1000_READ_REG(hw, E1000_MANC);
 341         manc &= ~E1000_MANC_ARP_EN;
 342         E1000_WRITE_REG(hw, E1000_MANC, manc);
 343
 344         if ((hw->mac.type == e1000_82541) || (hw->mac.type == e1000_82547)) {
 345                 e1000_phy_init_script_82541(hw);
 346
 347                 /* Configure activity LED after Phy reset */
 348                 ledctl = E1000_READ_REG(hw, E1000_LEDCTL);
 349                 ledctl &= IGP_ACTIVITY_LED_MASK;
 350                 ledctl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE);
 351                 E1000_WRITE_REG(hw, E1000_LEDCTL, ledctl);
 352         }
 353
 354         /* Once again, mask the interrupts */
 355         DEBUGOUT("Masking off all interrupts\n");
 356         E1000_WRITE_REG(hw, E1000_IMC, 0xFFFFFFFF);
 357
 358         /* Clear any pending interrupt events. */
 359         E1000_READ_REG(hw, E1000_ICR);
 360
 361         return E1000_SUCCESS;
 362 }
 363
 364 /**
 365  *  e1000_init_hw_82541 - Initialize hardware
 366  *  @hw: pointer to the HW structure
 367  *
 368  *  This inits the hardware readying it for operation.
 369  **/
 370 STATIC s32 e1000_init_hw_82541(struct e1000_hw *hw)
 371 {
 372         struct e1000_mac_info *mac = &hw->mac;
 373         struct e1000_dev_spec_82541 *dev_spec = &hw->dev_spec._82541;
 374         u32 i, txdctl;
 375         s32 ret_val;
 376
 377         DEBUGFUNC("e1000_init_hw_82541");
 378
 379         /* Initialize identification LED */
 380         ret_val = mac->ops.id_led_init(hw);
 381         if (ret_val) {
 382                 DEBUGOUT("Error initializing identification LED\n");
 383                 /* This is not fatal and we should not stop init due to this */
 384         }
 385
 386         /* Storing the Speed Power Down  value for later use */
 387         ret_val = hw->phy.ops.read_reg(hw, IGP01E1000_GMII_FIFO,
 388                                        &dev_spec->spd_default);
 389         if (ret_val)
 390                 goto out;
 391
 392         /* Disabling VLAN filtering */
 393         DEBUGOUT("Initializing the IEEE VLAN\n");
 394         mac->ops.clear_vfta(hw);
 395
 396         /* Setup the receive address. */
 397         e1000_init_rx_addrs_generic(hw, mac->rar_entry_count);
 398
 399         /* Zero out the Multicast HASH table */
 400         DEBUGOUT("Zeroing the MTA\n");
 401         for (i = 0; i < mac->mta_reg_count; i++) {
 402                 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0);
 403                 /*
 404                  * Avoid back to back register writes by adding the register
 405                  * read (flush).  This is to protect against some strange
 406                  * bridge configurations that may issue Memory Write Block
 407                  * (MWB) to our register space.
 408                  */
 409                 E1000_WRITE_FLUSH(hw);
 410         }
 411
 412         /* Setup link and flow control */
 413         ret_val = mac->ops.setup_link(hw);
 414
 415         txdctl = E1000_READ_REG(hw, E1000_TXDCTL(0));
 416         txdctl = (txdctl & ~E1000_TXDCTL_WTHRESH) |
 417                   E1000_TXDCTL_FULL_TX_DESC_WB;
 418         E1000_WRITE_REG(hw, E1000_TXDCTL(0), txdctl);
 419
 420         /*
 421          * Clear all of the statistics registers (clear on read).  It is
 422          * important that we do this after we have tried to establish link
 423          * because the symbol error count will increment wildly if there
 424          * is no link.
 425          */
 426         e1000_clear_hw_cntrs_82541(hw);
 427
 428 out:
 429         return ret_val;
 430 }
 431
 432 /**
 433  * e1000_get_link_up_info_82541 - Report speed and duplex
 434  * @hw: pointer to the HW structure
 435  * @speed: pointer to speed buffer
 436  * @duplex: pointer to duplex buffer
 437  *
 438  * Retrieve the current speed and duplex configuration.
 439  **/
 440 STATIC s32 e1000_get_link_up_info_82541(struct e1000_hw *hw, u16 *speed,
 441                                         u16 *duplex)
 442 {
 443         struct e1000_phy_info *phy = &hw->phy;
 444         s32 ret_val;
 445         u16 data;
 446
 447         DEBUGFUNC("e1000_get_link_up_info_82541");
 448
 449         ret_val = e1000_get_speed_and_duplex_copper_generic(hw, speed, duplex);
 450         if (ret_val)
 451                 goto out;
 452
 453         if (!phy->speed_downgraded)
 454                 goto out;
 455
 456         /*
 457          * IGP01 PHY may advertise full duplex operation after speed
 458          * downgrade even if it is operating at half duplex.
 459          * Here we set the duplex settings to match the duplex in the
 460          * link partner's capabilities.
 461          */
 462         ret_val = phy->ops.read_reg(hw, PHY_AUTONEG_EXP, &data);
 463         if (ret_val)
 464                 goto out;
 465
 466         if (!(data & NWAY_ER_LP_NWAY_CAPS)) {
 467                 *duplex = HALF_DUPLEX;
 468         } else {
 469                 ret_val = phy->ops.read_reg(hw, PHY_LP_ABILITY, &data);
 470                 if (ret_val)
 471                         goto out;
 472
 473                 if (*speed == SPEED_100) {
 474                         if (!(data & NWAY_LPAR_100TX_FD_CAPS))
 475                                 *duplex = HALF_DUPLEX;
 476                 } else if (*speed == SPEED_10) {
 477                         if (!(data & NWAY_LPAR_10T_FD_CAPS))
 478                                 *duplex = HALF_DUPLEX;
 479                 }
 480         }
 481
 482 out:
 483         return ret_val;
 484 }
 485
 486 /**
 487  *  e1000_phy_hw_reset_82541 - PHY hardware reset
 488  *  @hw: pointer to the HW structure
 489  *
 490  *  Verify the reset block is not blocking us from resetting.  Acquire
 491  *  semaphore (if necessary) and read/set/write the device control reset
 492  *  bit in the PHY.  Wait the appropriate delay time for the device to
 493  *  reset and release the semaphore (if necessary).
 494  **/
 495 STATIC s32 e1000_phy_hw_reset_82541(struct e1000_hw *hw)
 496 {
 497         s32 ret_val;
 498         u32 ledctl;
 499
 500         DEBUGFUNC("e1000_phy_hw_reset_82541");
 501
 502         ret_val = e1000_phy_hw_reset_generic(hw);
 503         if (ret_val)
 504                 goto out;
 505
 506         e1000_phy_init_script_82541(hw);
 507
 508         if ((hw->mac.type == e1000_82541) || (hw->mac.type == e1000_82547)) {
 509                 /* Configure activity LED after PHY reset */
 510                 ledctl = E1000_READ_REG(hw, E1000_LEDCTL);
 511                 ledctl &= IGP_ACTIVITY_LED_MASK;
 512                 ledctl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE);
 513                 E1000_WRITE_REG(hw, E1000_LEDCTL, ledctl);
 514         }
 515
 516 out:
 517         return ret_val;
 518 }
 519
 520 /**
 521  *  e1000_setup_copper_link_82541 - Configure copper link settings
 522  *  @hw: pointer to the HW structure
 523  *
 524  *  Calls the appropriate function to configure the link for auto-neg or forced
 525  *  speed and duplex.  Then we check for link, once link is established calls
 526  *  to configure collision distance and flow control are called.  If link is
 527  *  not established, we return -E1000_ERR_PHY (-2).
 528  **/
 529 STATIC s32 e1000_setup_copper_link_82541(struct e1000_hw *hw)
 530 {
 531         struct e1000_phy_info *phy = &hw->phy;
 532         struct e1000_dev_spec_82541 *dev_spec = &hw->dev_spec._82541;
 533         s32  ret_val;
 534         u32 ctrl, ledctl;
 535
 536         DEBUGFUNC("e1000_setup_copper_link_82541");
 537
 538         ctrl = E1000_READ_REG(hw, E1000_CTRL);
 539         ctrl |= E1000_CTRL_SLU;
 540         ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
 541         E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
 542
 543
 544         /* Earlier revs of the IGP phy require us to force MDI. */
 545         if (hw->mac.type == e1000_82541 || hw->mac.type == e1000_82547) {
 546                 dev_spec->dsp_config = e1000_dsp_config_disabled;
 547                 phy->mdix = 1;
 548         } else {
 549                 dev_spec->dsp_config = e1000_dsp_config_enabled;
 550         }
 551
 552         ret_val = e1000_copper_link_setup_igp(hw);
 553         if (ret_val)
 554                 goto out;
 555
 556         if (hw->mac.autoneg) {
 557                 if (dev_spec->ffe_config == e1000_ffe_config_active)
 558                         dev_spec->ffe_config = e1000_ffe_config_enabled;
 559         }
 560
 561         /* Configure activity LED after Phy reset */
 562         ledctl = E1000_READ_REG(hw, E1000_LEDCTL);
 563         ledctl &= IGP_ACTIVITY_LED_MASK;
 564         ledctl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE);
 565         E1000_WRITE_REG(hw, E1000_LEDCTL, ledctl);
 566
 567         ret_val = e1000_setup_copper_link_generic(hw);
 568
 569 out:
 570         return ret_val;
 571 }
 572
 573 /**
 574  *  e1000_check_for_link_82541 - Check/Store link connection
 575  *  @hw: pointer to the HW structure
 576  *
 577  *  This checks the link condition of the adapter and stores the
 578  *  results in the hw->mac structure.
 579  **/
 580 STATIC s32 e1000_check_for_link_82541(struct e1000_hw *hw)
 581 {
 582         struct e1000_mac_info *mac = &hw->mac;
 583         s32 ret_val;
 584         bool link;
 585
 586         DEBUGFUNC("e1000_check_for_link_82541");
 587
 588         /*
 589          * We only want to go out to the PHY registers to see if Auto-Neg
 590          * has completed and/or if our link status has changed.  The
 591          * get_link_status flag is set upon receiving a Link Status
 592          * Change or Rx Sequence Error interrupt.
 593          */
 594         if (!mac->get_link_status) {
 595                 ret_val = E1000_SUCCESS;
 596                 goto out;
 597         }
 598
 599         /*
 600          * First we want to see if the MII Status Register reports
 601          * link.  If so, then we want to get the current speed/duplex
 602          * of the PHY.
 603          */
 604         ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link);
 605         if (ret_val)
 606                 goto out;
 607
 608         if (!link) {
 609                 ret_val = e1000_config_dsp_after_link_change_82541(hw, false);
 610                 goto out; /* No link detected */
 611         }
 612
 613         mac->get_link_status = false;
 614
 615         /*
 616          * Check if there was DownShift, must be checked
 617          * immediately after link-up
 618          */
 619         e1000_check_downshift_generic(hw);
 620
 621         /*
 622          * If we are forcing speed/duplex, then we simply return since
 623          * we have already determined whether we have link or not.
 624          */
 625         if (!mac->autoneg) {
 626                 ret_val = -E1000_ERR_CONFIG;
 627                 goto out;
 628         }
 629
 630         ret_val = e1000_config_dsp_after_link_change_82541(hw, true);
 631
 632         /*
 633          * Auto-Neg is enabled.  Auto Speed Detection takes care
 634          * of MAC speed/duplex configuration.  So we only need to
 635          * configure Collision Distance in the MAC.
 636          */
 637         mac->ops.config_collision_dist(hw);
 638
 639         /*
 640          * Configure Flow Control now that Auto-Neg has completed.
 641          * First, we need to restore the desired flow control
 642          * settings because we may have had to re-autoneg with a
 643          * different link partner.
 644          */
 645         ret_val = e1000_config_fc_after_link_up_generic(hw);
 646         if (ret_val)
 647                 DEBUGOUT("Error configuring flow control\n");
 648
 649 out:
 650         return ret_val;
 651 }
 652
 653 /**
 654  *  e1000_config_dsp_after_link_change_82541 - Config DSP after link
 655  *  @hw: pointer to the HW structure
 656  *  @link_up: boolean flag for link up status
 657  *
 658  *  Return E1000_ERR_PHY when failing to read/write the PHY, else E1000_SUCCESS
 659  *  at any other case.
 660  *
 661  *  82541_rev_2 & 82547_rev_2 have the capability to configure the DSP when a
 662  *  gigabit link is achieved to improve link quality.
 663  **/
 664 STATIC s32 e1000_config_dsp_after_link_change_82541(struct e1000_hw *hw,
 665                                                     bool link_up)
 666 {
 667         struct e1000_phy_info *phy = &hw->phy;
 668         struct e1000_dev_spec_82541 *dev_spec = &hw->dev_spec._82541;
 669         s32 ret_val;
 670         u32 idle_errs = 0;
 671         u16 phy_data, phy_saved_data, speed, duplex, i;
 672         u16 ffe_idle_err_timeout = FFE_IDLE_ERR_COUNT_TIMEOUT_20;
 673         u16 dsp_reg_array[IGP01E1000_PHY_CHANNEL_NUM] = {
 674                                                 IGP01E1000_PHY_AGC_PARAM_A,
 675                                                 IGP01E1000_PHY_AGC_PARAM_B,
 676                                                 IGP01E1000_PHY_AGC_PARAM_C,
 677                                                 IGP01E1000_PHY_AGC_PARAM_D};
 678
 679         DEBUGFUNC("e1000_config_dsp_after_link_change_82541");
 680
 681         if (link_up) {
 682                 ret_val = hw->mac.ops.get_link_up_info(hw, &speed, &duplex);
 683                 if (ret_val) {
 684                         DEBUGOUT("Error getting link speed and duplex\n");
 685                         goto out;
 686                 }
 687
 688                 if (speed != SPEED_1000) {
 689                         ret_val = E1000_SUCCESS;
 690                         goto out;
 691                 }
 692
 693                 ret_val = phy->ops.get_cable_length(hw);
 694                 if (ret_val)
 695                         goto out;
 696
 697                 if ((dev_spec->dsp_config == e1000_dsp_config_enabled) &&
 698                     phy->min_cable_length >= 50) {
 699
 700                         for (i = 0; i < IGP01E1000_PHY_CHANNEL_NUM; i++) {
 701                                 ret_val = phy->ops.read_reg(hw,
 702                                                             dsp_reg_array[i],
 703                                                             &phy_data);
 704                                 if (ret_val)
 705                                         goto out;
 706
 707                                 phy_data &= ~IGP01E1000_PHY_EDAC_MU_INDEX;
 708
 709                                 ret_val = phy->ops.write_reg(hw,
 710                                                              dsp_reg_array[i],
 711                                                              phy_data);
 712                                 if (ret_val)
 713                                         goto out;
 714                         }
 715                         dev_spec->dsp_config = e1000_dsp_config_activated;
 716                 }
 717
 718                 if ((dev_spec->ffe_config != e1000_ffe_config_enabled) ||
 719                     (phy->min_cable_length >= 50)) {
 720                         ret_val = E1000_SUCCESS;
 721                         goto out;
 722                 }
 723
 724                 /* clear previous idle error counts */
 725                 ret_val = phy->ops.read_reg(hw, PHY_1000T_STATUS, &phy_data);
 726                 if (ret_val)
 727                         goto out;
 728
 729                 for (i = 0; i < ffe_idle_err_timeout; i++) {
 730                         usec_delay(1000);
 731                         ret_val = phy->ops.read_reg(hw, PHY_1000T_STATUS,
 732                                                     &phy_data);
 733                         if (ret_val)
 734                                 goto out;
 735
 736                         idle_errs += (phy_data & SR_1000T_IDLE_ERROR_CNT);
 737                         if (idle_errs > SR_1000T_PHY_EXCESSIVE_IDLE_ERR_COUNT) {
 738                                 dev_spec->ffe_config = e1000_ffe_config_active;
 739
 740                                 ret_val = phy->ops.write_reg(hw,
 741                                                   IGP01E1000_PHY_DSP_FFE,
 742                                                   IGP01E1000_PHY_DSP_FFE_CM_CP);
 743                                 if (ret_val)
 744                                         goto out;
 745                                 break;
 746                         }
 747
 748                         if (idle_errs)
 749                                 ffe_idle_err_timeout =
 750                                                  FFE_IDLE_ERR_COUNT_TIMEOUT_100;
 751                 }
 752         } else {
 753                 if (dev_spec->dsp_config == e1000_dsp_config_activated) {
 754                         /*
 755                          * Save off the current value of register 0x2F5B
 756                          * to be restored at the end of the routines.
 757                          */
 758                         ret_val = phy->ops.read_reg(hw, 0x2F5B,
 759                                                     &phy_saved_data);
 760                         if (ret_val)
 761                                 goto out;
 762
 763                         /* Disable the PHY transmitter */
 764                         ret_val = phy->ops.write_reg(hw, 0x2F5B, 0x0003);
 765                         if (ret_val)
 766                                 goto out;
 767
 768                         msec_delay_irq(20);
 769
 770                         ret_val = phy->ops.write_reg(hw, 0x0000,
 771                                                      IGP01E1000_IEEE_FORCE_GIG);
 772                         if (ret_val)
 773                                 goto out;
 774                         for (i = 0; i < IGP01E1000_PHY_CHANNEL_NUM; i++) {
 775                                 ret_val = phy->ops.read_reg(hw,
 776                                                             dsp_reg_array[i],
 777                                                             &phy_data);
 778                                 if (ret_val)
 779                                         goto out;
 780
 781                                 phy_data &= ~IGP01E1000_PHY_EDAC_MU_INDEX;
 782                                 phy_data |= IGP01E1000_PHY_EDAC_SIGN_EXT_9_BITS;
 783
 784                                 ret_val = phy->ops.write_reg(hw,
 785                                                              dsp_reg_array[i],
 786                                                              phy_data);
 787                                 if (ret_val)
 788                                         goto out;
 789                         }
 790
 791                         ret_val = phy->ops.write_reg(hw, 0x0000,
 792                                                IGP01E1000_IEEE_RESTART_AUTONEG);
 793                         if (ret_val)
 794                                 goto out;
 795
 796                         msec_delay_irq(20);
 797
 798                         /* Now enable the transmitter */
 799                         ret_val = phy->ops.write_reg(hw, 0x2F5B,
 800                                                      phy_saved_data);
 801                         if (ret_val)
 802                                 goto out;
 803
 804                         dev_spec->dsp_config = e1000_dsp_config_enabled;
 805                 }
 806
 807                 if (dev_spec->ffe_config != e1000_ffe_config_active) {
 808                         ret_val = E1000_SUCCESS;
 809                         goto out;
 810                 }
 811
 812                 /*
 813                  * Save off the current value of register 0x2F5B
 814                  * to be restored at the end of the routines.
 815                  */
 816                 ret_val = phy->ops.read_reg(hw, 0x2F5B, &phy_saved_data);
 817                 if (ret_val)
 818                         goto out;
 819
 820                 /* Disable the PHY transmitter */
 821                 ret_val = phy->ops.write_reg(hw, 0x2F5B, 0x0003);
 822                 if (ret_val)
 823                         goto out;
 824
 825                 msec_delay_irq(20);
 826
 827                 ret_val = phy->ops.write_reg(hw, 0x0000,
 828                                              IGP01E1000_IEEE_FORCE_GIG);
 829                 if (ret_val)
 830                         goto out;
 831
 832                 ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_DSP_FFE,
 833                                              IGP01E1000_PHY_DSP_FFE_DEFAULT);
 834                 if (ret_val)
 835                         goto out;
 836
 837                 ret_val = phy->ops.write_reg(hw, 0x0000,
 838                                              IGP01E1000_IEEE_RESTART_AUTONEG);
 839                 if (ret_val)
 840                         goto out;
 841
 842                 msec_delay_irq(20);
 843
 844                 /* Now enable the transmitter */
 845                 ret_val = phy->ops.write_reg(hw, 0x2F5B, phy_saved_data);
 846
 847                 if (ret_val)
 848                         goto out;
 849
 850                 dev_spec->ffe_config = e1000_ffe_config_enabled;
 851         }
 852
 853 out:
 854         return ret_val;
 855 }
 856
 857 /**
 858  *  e1000_get_cable_length_igp_82541 - Determine cable length for igp PHY
 859  *  @hw: pointer to the HW structure
 860  *
 861  *  The automatic gain control (agc) normalizes the amplitude of the
 862  *  received signal, adjusting for the attenuation produced by the
 863  *  cable.  By reading the AGC registers, which represent the
 864  *  combination of coarse and fine gain value, the value can be put
 865  *  into a lookup table to obtain the approximate cable length
 866  *  for each channel.
 867  **/
 868 STATIC s32 e1000_get_cable_length_igp_82541(struct e1000_hw *hw)
 869 {
 870         struct e1000_phy_info *phy = &hw->phy;
 871         s32 ret_val = E1000_SUCCESS;
 872         u16 i, data;
 873         u16 cur_agc_value, agc_value = 0;
 874         u16 min_agc_value = IGP01E1000_AGC_LENGTH_TABLE_SIZE;
 875         u16 agc_reg_array[IGP01E1000_PHY_CHANNEL_NUM] = {IGP01E1000_PHY_AGC_A,
 876                                                          IGP01E1000_PHY_AGC_B,
 877                                                          IGP01E1000_PHY_AGC_C,
 878                                                          IGP01E1000_PHY_AGC_D};
 879
 880         DEBUGFUNC("e1000_get_cable_length_igp_82541");
 881
 882         /* Read the AGC registers for all channels */
 883         for (i = 0; i < IGP01E1000_PHY_CHANNEL_NUM; i++) {
 884                 ret_val = phy->ops.read_reg(hw, agc_reg_array[i], &data);
 885                 if (ret_val)
 886                         goto out;
 887
 888                 cur_agc_value = data >> IGP01E1000_AGC_LENGTH_SHIFT;
 889
 890                 /* Bounds checking */
 891                 if ((cur_agc_value >= IGP01E1000_AGC_LENGTH_TABLE_SIZE - 1) ||
 892                     (cur_agc_value == 0)) {
 893                         ret_val = -E1000_ERR_PHY;
 894                         goto out;
 895                 }
 896
 897                 agc_value += cur_agc_value;
 898
 899                 if (min_agc_value > cur_agc_value)
 900                         min_agc_value = cur_agc_value;
 901         }
 902
 903         /* Remove the minimal AGC result for length < 50m */
 904         if (agc_value < IGP01E1000_PHY_CHANNEL_NUM * 50) {
 905                 agc_value -= min_agc_value;
 906                 /* Average the three remaining channels for the length. */
 907                 agc_value /= (IGP01E1000_PHY_CHANNEL_NUM - 1);
 908         } else {
 909                 /* Average the channels for the length. */
 910                 agc_value /= IGP01E1000_PHY_CHANNEL_NUM;
 911         }
 912
 913         phy->min_cable_length = (e1000_igp_cable_length_table[agc_value] >
 914                                  IGP01E1000_AGC_RANGE)
 915                                 ? (e1000_igp_cable_length_table[agc_value] -
 916                                    IGP01E1000_AGC_RANGE)
 917                                 : 0;
 918         phy->max_cable_length = e1000_igp_cable_length_table[agc_value] +
 919                                 IGP01E1000_AGC_RANGE;
 920
 921         phy->cable_length = (phy->min_cable_length + phy->max_cable_length) / 2;
 922
 923 out:
 924         return ret_val;
 925 }
 926
 927 /**
 928  *  e1000_set_d3_lplu_state_82541 - Sets low power link up state for D3
 929  *  @hw: pointer to the HW structure
 930  *  @active: boolean used to enable/disable lplu
 931  *
 932  *  Success returns 0, Failure returns 1
 933  *
 934  *  The low power link up (lplu) state is set to the power management level D3
 935  *  and SmartSpeed is disabled when active is true, else clear lplu for D3
 936  *  and enable Smartspeed.  LPLU and Smartspeed are mutually exclusive.  LPLU
 937  *  is used during Dx states where the power conservation is most important.
 938  *  During driver activity, SmartSpeed should be enabled so performance is
 939  *  maintained.
 940  **/
 941 STATIC s32 e1000_set_d3_lplu_state_82541(struct e1000_hw *hw, bool active)
 942 {
 943         struct e1000_phy_info *phy = &hw->phy;
 944         s32 ret_val;
 945         u16 data;
 946
 947         DEBUGFUNC("e1000_set_d3_lplu_state_82541");
 948
 949         switch (hw->mac.type) {
 950         case e1000_82541_rev_2:
 951         case e1000_82547_rev_2:
 952                 break;
 953         default:
 954                 ret_val = e1000_set_d3_lplu_state_generic(hw, active);
 955                 goto out;
 956                 break;
 957         }
 958
 959         ret_val = phy->ops.read_reg(hw, IGP01E1000_GMII_FIFO, &data);
 960         if (ret_val)
 961                 goto out;
 962
 963         if (!active) {
 964                 data &= ~IGP01E1000_GMII_FLEX_SPD;
 965                 ret_val = phy->ops.write_reg(hw, IGP01E1000_GMII_FIFO, data);
 966                 if (ret_val)
 967                         goto out;
 968
 969                 /*
 970                  * LPLU and SmartSpeed are mutually exclusive.  LPLU is used
 971                  * during Dx states where the power conservation is most
 972                  * important.  During driver activity we should enable
 973                  * SmartSpeed, so performance is maintained.
 974                  */
 975                 if (phy->smart_speed == e1000_smart_speed_on) {
 976                         ret_val = phy->ops.read_reg(hw,
 977                                                     IGP01E1000_PHY_PORT_CONFIG,
 978                                                     &data);
 979                         if (ret_val)
 980                                 goto out;
 981
 982                         data |= IGP01E1000_PSCFR_SMART_SPEED;
 983                         ret_val = phy->ops.write_reg(hw,
 984                                                      IGP01E1000_PHY_PORT_CONFIG,
 985                                                      data);
 986                         if (ret_val)
 987                                 goto out;
 988                 } else if (phy->smart_speed == e1000_smart_speed_off) {
 989                         ret_val = phy->ops.read_reg(hw,
 990                                                     IGP01E1000_PHY_PORT_CONFIG,
 991                                                     &data);
 992                         if (ret_val)
 993                                 goto out;
 994
 995                         data &= ~IGP01E1000_PSCFR_SMART_SPEED;
 996                         ret_val = phy->ops.write_reg(hw,
 997                                                      IGP01E1000_PHY_PORT_CONFIG,
 998                                                      data);
 999                         if (ret_val)
1000                                 goto out;
1001                 }
1002         } else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) ||
1003                    (phy->autoneg_advertised == E1000_ALL_NOT_GIG) ||
1004                    (phy->autoneg_advertised == E1000_ALL_10_SPEED)) {
1005                 data |= IGP01E1000_GMII_FLEX_SPD;
1006                 ret_val = phy->ops.write_reg(hw, IGP01E1000_GMII_FIFO, data);
1007                 if (ret_val)
1008                         goto out;
1009
1010                 /* When LPLU is enabled, we should disable SmartSpeed */
1011                 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
1012                                             &data);
1013                 if (ret_val)
1014                         goto out;
1015
1016                 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
1017                 ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
1018                                              data);
1019         }
1020
1021 out:
1022         return ret_val;
1023 }
1024
1025 /**
1026  *  e1000_setup_led_82541 - Configures SW controllable LED
1027  *  @hw: pointer to the HW structure
1028  *
1029  *  This prepares the SW controllable LED for use and saves the current state
1030  *  of the LED so it can be later restored.
1031  **/
1032 STATIC s32 e1000_setup_led_82541(struct e1000_hw *hw)
1033 {
1034         struct e1000_dev_spec_82541 *dev_spec = &hw->dev_spec._82541;
1035         s32 ret_val;
1036
1037         DEBUGFUNC("e1000_setup_led_82541");
1038
1039         ret_val = hw->phy.ops.read_reg(hw, IGP01E1000_GMII_FIFO,
1040                                        &dev_spec->spd_default);
1041         if (ret_val)
1042                 goto out;
1043
1044         ret_val = hw->phy.ops.write_reg(hw, IGP01E1000_GMII_FIFO,
1045                                         (u16)(dev_spec->spd_default &
1046                                         ~IGP01E1000_GMII_SPD));
1047         if (ret_val)
1048                 goto out;
1049
1050         E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_mode1);
1051
1052 out:
1053         return ret_val;
1054 }
1055
1056 /**
1057  *  e1000_cleanup_led_82541 - Set LED config to default operation
1058  *  @hw: pointer to the HW structure
1059  *
1060  *  Remove the current LED configuration and set the LED configuration
1061  *  to the default value, saved from the EEPROM.
1062  **/
1063 STATIC s32 e1000_cleanup_led_82541(struct e1000_hw *hw)
1064 {
1065         struct e1000_dev_spec_82541 *dev_spec = &hw->dev_spec._82541;
1066         s32 ret_val;
1067
1068         DEBUGFUNC("e1000_cleanup_led_82541");
1069
1070         ret_val = hw->phy.ops.write_reg(hw, IGP01E1000_GMII_FIFO,
1071                                         dev_spec->spd_default);
1072         if (ret_val)
1073                 goto out;
1074
1075         E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_default);
1076
1077 out:
1078         return ret_val;
1079 }
1080
1081 /**
1082  *  e1000_phy_init_script_82541 - Initialize GbE PHY
1083  *  @hw: pointer to the HW structure
1084  *
1085  *  Initializes the IGP PHY.
1086  **/
1087 STATIC s32 e1000_phy_init_script_82541(struct e1000_hw *hw)
1088 {
1089         struct e1000_dev_spec_82541 *dev_spec = &hw->dev_spec._82541;
1090         u32 ret_val;
1091         u16 phy_saved_data;
1092
1093         DEBUGFUNC("e1000_phy_init_script_82541");
1094
1095         if (!dev_spec->phy_init_script) {
1096                 ret_val = E1000_SUCCESS;
1097                 goto out;
1098         }
1099
1100         /* Delay after phy reset to enable NVM configuration to load */
1101         msec_delay(20);
1102
1103         /*
1104          * Save off the current value of register 0x2F5B to be restored at
1105          * the end of this routine.
1106          */
1107         ret_val = hw->phy.ops.read_reg(hw, 0x2F5B, &phy_saved_data);
1108
1109         /* Disabled the PHY transmitter */
1110         hw->phy.ops.write_reg(hw, 0x2F5B, 0x0003);
1111
1112         msec_delay(20);
1113
1114         hw->phy.ops.write_reg(hw, 0x0000, 0x0140);
1115
1116         msec_delay(5);
1117
1118         switch (hw->mac.type) {
1119         case e1000_82541:
1120         case e1000_82547:
1121                 hw->phy.ops.write_reg(hw, 0x1F95, 0x0001);
1122
1123                 hw->phy.ops.write_reg(hw, 0x1F71, 0xBD21);
1124
1125                 hw->phy.ops.write_reg(hw, 0x1F79, 0x0018);
1126
1127                 hw->phy.ops.write_reg(hw, 0x1F30, 0x1600);
1128
1129                 hw->phy.ops.write_reg(hw, 0x1F31, 0x0014);
1130
1131                 hw->phy.ops.write_reg(hw, 0x1F32, 0x161C);
1132
1133                 hw->phy.ops.write_reg(hw, 0x1F94, 0x0003);
1134
1135                 hw->phy.ops.write_reg(hw, 0x1F96, 0x003F);
1136
1137                 hw->phy.ops.write_reg(hw, 0x2010, 0x0008);
1138                 break;
1139         case e1000_82541_rev_2:
1140         case e1000_82547_rev_2:
1141                 hw->phy.ops.write_reg(hw, 0x1F73, 0x0099);
1142                 break;
1143         default:
1144                 break;
1145         }
1146
1147         hw->phy.ops.write_reg(hw, 0x0000, 0x3300);
1148
1149         msec_delay(20);
1150
1151         /* Now enable the transmitter */
1152         hw->phy.ops.write_reg(hw, 0x2F5B, phy_saved_data);
1153
1154         if (hw->mac.type == e1000_82547) {
1155                 u16 fused, fine, coarse;
1156
1157                 /* Move to analog registers page */
1158                 hw->phy.ops.read_reg(hw, IGP01E1000_ANALOG_SPARE_FUSE_STATUS,
1159                                      &fused);
1160
1161                 if (!(fused & IGP01E1000_ANALOG_SPARE_FUSE_ENABLED)) {
1162                         hw->phy.ops.read_reg(hw, IGP01E1000_ANALOG_FUSE_STATUS,
1163                                              &fused);
1164
1165                         fine = fused & IGP01E1000_ANALOG_FUSE_FINE_MASK;
1166                         coarse = fused & IGP01E1000_ANALOG_FUSE_COARSE_MASK;
1167
1168                         if (coarse > IGP01E1000_ANALOG_FUSE_COARSE_THRESH) {
1169                                 coarse -= IGP01E1000_ANALOG_FUSE_COARSE_10;
1170                                 fine -= IGP01E1000_ANALOG_FUSE_FINE_1;
1171                         } else if (coarse ==
1172                                    IGP01E1000_ANALOG_FUSE_COARSE_THRESH)
1173                                 fine -= IGP01E1000_ANALOG_FUSE_FINE_10;
1174
1175                         fused = (fused & IGP01E1000_ANALOG_FUSE_POLY_MASK) |
1176                                 (fine & IGP01E1000_ANALOG_FUSE_FINE_MASK) |
1177                                 (coarse & IGP01E1000_ANALOG_FUSE_COARSE_MASK);
1178
1179                         hw->phy.ops.write_reg(hw,
1180                                               IGP01E1000_ANALOG_FUSE_CONTROL,
1181                                               fused);
1182                         hw->phy.ops.write_reg(hw,
1183                                       IGP01E1000_ANALOG_FUSE_BYPASS,
1184                                       IGP01E1000_ANALOG_FUSE_ENABLE_SW_CONTROL);
1185                 }
1186         }
1187
1188 out:
1189         return ret_val;
1190 }
1191
1192 /**
1193  *  e1000_init_script_state_82541 - Enable/Disable PHY init script
1194  *  @hw: pointer to the HW structure
1195  *  @state: boolean value used to enable/disable PHY init script
1196  *
1197  *  Allows the driver to enable/disable the PHY init script, if the PHY is an
1198  *  IGP PHY.
1199  **/
1200 void e1000_init_script_state_82541(struct e1000_hw *hw, bool state)
1201 {
1202         struct e1000_dev_spec_82541 *dev_spec = &hw->dev_spec._82541;
1203
1204         DEBUGFUNC("e1000_init_script_state_82541");
1205
1206         if (hw->phy.type != e1000_phy_igp) {
1207                 DEBUGOUT("Initialization script not necessary.\n");
1208                 goto out;
1209         }
1210
1211         dev_spec->phy_init_script = state;
1212
1213 out:
1214         return;
1215 }
1216
1217 /**
1218  * e1000_power_down_phy_copper_82541 - Remove link in case of PHY power down
1219  * @hw: pointer to the HW structure
1220  *
1221  * In the case of a PHY power down to save power, or to turn off link during a
1222  * driver unload, or wake on lan is not enabled, remove the link.
1223  **/
1224 STATIC void e1000_power_down_phy_copper_82541(struct e1000_hw *hw)
1225 {
1226         /* If the management interface is not enabled, then power down */
1227         if (!(E1000_READ_REG(hw, E1000_MANC) & E1000_MANC_SMBUS_EN))
1228                 e1000_power_down_phy_copper(hw);
1229
1230         return;
1231 }
1232
1233 /**
1234  *  e1000_clear_hw_cntrs_82541 - Clear device specific hardware counters
1235  *  @hw: pointer to the HW structure
1236  *
1237  *  Clears the hardware counters by reading the counter registers.
1238  **/
1239 STATIC void e1000_clear_hw_cntrs_82541(struct e1000_hw *hw)
1240 {
1241         DEBUGFUNC("e1000_clear_hw_cntrs_82541");
1242
1243         e1000_clear_hw_cntrs_base_generic(hw);
1244
1245         E1000_READ_REG(hw, E1000_PRC64);
1246         E1000_READ_REG(hw, E1000_PRC127);
1247         E1000_READ_REG(hw, E1000_PRC255);
1248         E1000_READ_REG(hw, E1000_PRC511);
1249         E1000_READ_REG(hw, E1000_PRC1023);
1250         E1000_READ_REG(hw, E1000_PRC1522);
1251         E1000_READ_REG(hw, E1000_PTC64);
1252         E1000_READ_REG(hw, E1000_PTC127);
1253         E1000_READ_REG(hw, E1000_PTC255);
1254         E1000_READ_REG(hw, E1000_PTC511);
1255         E1000_READ_REG(hw, E1000_PTC1023);
1256         E1000_READ_REG(hw, E1000_PTC1522);
1257
1258         E1000_READ_REG(hw, E1000_ALGNERRC);
1259         E1000_READ_REG(hw, E1000_RXERRC);
1260         E1000_READ_REG(hw, E1000_TNCRS);
1261         E1000_READ_REG(hw, E1000_CEXTERR);
1262         E1000_READ_REG(hw, E1000_TSCTC);
1263         E1000_READ_REG(hw, E1000_TSCTFC);
1264
1265         E1000_READ_REG(hw, E1000_MGTPRC);
1266         E1000_READ_REG(hw, E1000_MGTPDC);
1267         E1000_READ_REG(hw, E1000_MGTPTC);
1268 }