drivers/net/e1000/base/e1000_82575.c

   1 /*******************************************************************************
   2
   3 Copyright (c) 2001-2015, Intel Corporation
   4 All rights reserved.
   5
   6 Redistribution and use in source and binary forms, with or without
   7 modification, are permitted provided that the following conditions are met:
   8
   9  1. Redistributions of source code must retain the above copyright notice,
  10     this list of conditions and the following disclaimer.
  11
  12  2. Redistributions in binary form must reproduce the above copyright
  13     notice, this list of conditions and the following disclaimer in the
  14     documentation and/or other materials provided with the distribution.
  15
  16  3. Neither the name of the Intel Corporation nor the names of its
  17     contributors may be used to endorse or promote products derived from
  18     this software without specific prior written permission.
  19
  20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
  24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  30 POSSIBILITY OF SUCH DAMAGE.
  31
  32 ***************************************************************************/
  33
  34 /*
  35  * 82575EB Gigabit Network Connection
  36  * 82575EB Gigabit Backplane Connection
  37  * 82575GB Gigabit Network Connection
  38  * 82576 Gigabit Network Connection
  39  * 82576 Quad Port Gigabit Mezzanine Adapter
  40  * 82580 Gigabit Network Connection
  41  * I350 Gigabit Network Connection
  42  */
  43
  44 #include "e1000_api.h"
  45 #include "e1000_i210.h"
  46
  47 STATIC s32  e1000_init_phy_params_82575(struct e1000_hw *hw);
  48 STATIC s32  e1000_init_mac_params_82575(struct e1000_hw *hw);
  49 STATIC s32  e1000_acquire_phy_82575(struct e1000_hw *hw);
  50 STATIC void e1000_release_phy_82575(struct e1000_hw *hw);
  51 STATIC s32  e1000_acquire_nvm_82575(struct e1000_hw *hw);
  52 STATIC void e1000_release_nvm_82575(struct e1000_hw *hw);
  53 STATIC s32  e1000_check_for_link_82575(struct e1000_hw *hw);
  54 STATIC s32  e1000_check_for_link_media_swap(struct e1000_hw *hw);
  55 STATIC s32  e1000_get_cfg_done_82575(struct e1000_hw *hw);
  56 STATIC s32  e1000_get_link_up_info_82575(struct e1000_hw *hw, u16 *speed,
  57                                          u16 *duplex);
  58 STATIC s32  e1000_phy_hw_reset_sgmii_82575(struct e1000_hw *hw);
  59 STATIC s32  e1000_read_phy_reg_sgmii_82575(struct e1000_hw *hw, u32 offset,
  60                                            u16 *data);
  61 STATIC s32  e1000_reset_hw_82575(struct e1000_hw *hw);
  62 STATIC s32  e1000_reset_hw_82580(struct e1000_hw *hw);
  63 STATIC s32  e1000_read_phy_reg_82580(struct e1000_hw *hw,
  64                                      u32 offset, u16 *data);
  65 STATIC s32  e1000_write_phy_reg_82580(struct e1000_hw *hw,
  66                                       u32 offset, u16 data);
  67 STATIC s32  e1000_set_d0_lplu_state_82580(struct e1000_hw *hw,
  68                                           bool active);
  69 STATIC s32  e1000_set_d3_lplu_state_82580(struct e1000_hw *hw,
  70                                           bool active);
  71 STATIC s32  e1000_set_d0_lplu_state_82575(struct e1000_hw *hw,
  72                                           bool active);
  73 STATIC s32  e1000_setup_copper_link_82575(struct e1000_hw *hw);
  74 STATIC s32  e1000_setup_serdes_link_82575(struct e1000_hw *hw);
  75 STATIC s32  e1000_get_media_type_82575(struct e1000_hw *hw);
  76 STATIC s32  e1000_set_sfp_media_type_82575(struct e1000_hw *hw);
  77 STATIC s32  e1000_valid_led_default_82575(struct e1000_hw *hw, u16 *data);
  78 STATIC s32  e1000_write_phy_reg_sgmii_82575(struct e1000_hw *hw,
  79                                             u32 offset, u16 data);
  80 STATIC void e1000_clear_hw_cntrs_82575(struct e1000_hw *hw);
  81 STATIC s32  e1000_acquire_swfw_sync_82575(struct e1000_hw *hw, u16 mask);
  82 STATIC s32  e1000_get_pcs_speed_and_duplex_82575(struct e1000_hw *hw,
  83                                                  u16 *speed, u16 *duplex);
  84 STATIC s32  e1000_get_phy_id_82575(struct e1000_hw *hw);
  85 STATIC void e1000_release_swfw_sync_82575(struct e1000_hw *hw, u16 mask);
  86 STATIC bool e1000_sgmii_active_82575(struct e1000_hw *hw);
  87 STATIC s32  e1000_reset_init_script_82575(struct e1000_hw *hw);
  88 STATIC s32  e1000_read_mac_addr_82575(struct e1000_hw *hw);
  89 STATIC void e1000_config_collision_dist_82575(struct e1000_hw *hw);
  90 STATIC void e1000_power_down_phy_copper_82575(struct e1000_hw *hw);
  91 STATIC void e1000_shutdown_serdes_link_82575(struct e1000_hw *hw);
  92 STATIC void e1000_power_up_serdes_link_82575(struct e1000_hw *hw);
  93 STATIC s32 e1000_set_pcie_completion_timeout(struct e1000_hw *hw);
  94 STATIC s32 e1000_reset_mdicnfg_82580(struct e1000_hw *hw);
  95 STATIC s32 e1000_validate_nvm_checksum_82580(struct e1000_hw *hw);
  96 STATIC s32 e1000_update_nvm_checksum_82580(struct e1000_hw *hw);
  97 STATIC s32 e1000_update_nvm_checksum_with_offset(struct e1000_hw *hw,
  98                                                  u16 offset);
  99 STATIC s32 e1000_validate_nvm_checksum_with_offset(struct e1000_hw *hw,
 100                                                    u16 offset);
 101 STATIC s32 e1000_validate_nvm_checksum_i350(struct e1000_hw *hw);
 102 STATIC s32 e1000_update_nvm_checksum_i350(struct e1000_hw *hw);
 103 STATIC void e1000_write_vfta_i350(struct e1000_hw *hw, u32 offset, u32 value);
 104 STATIC void e1000_clear_vfta_i350(struct e1000_hw *hw);
 105
 106 STATIC void e1000_i2c_start(struct e1000_hw *hw);
 107 STATIC void e1000_i2c_stop(struct e1000_hw *hw);
 108 STATIC s32 e1000_clock_in_i2c_byte(struct e1000_hw *hw, u8 *data);
 109 STATIC s32 e1000_clock_out_i2c_byte(struct e1000_hw *hw, u8 data);
 110 STATIC s32 e1000_get_i2c_ack(struct e1000_hw *hw);
 111 STATIC s32 e1000_clock_in_i2c_bit(struct e1000_hw *hw, bool *data);
 112 STATIC s32 e1000_clock_out_i2c_bit(struct e1000_hw *hw, bool data);
 113 STATIC void e1000_raise_i2c_clk(struct e1000_hw *hw, u32 *i2cctl);
 114 STATIC void e1000_lower_i2c_clk(struct e1000_hw *hw, u32 *i2cctl);
 115 STATIC s32 e1000_set_i2c_data(struct e1000_hw *hw, u32 *i2cctl, bool data);
 116 STATIC bool e1000_get_i2c_data(u32 *i2cctl);
 117
 118 STATIC const u16 e1000_82580_rxpbs_table[] = {
 119         36, 72, 144, 1, 2, 4, 8, 16, 35, 70, 140 };
 120 #define E1000_82580_RXPBS_TABLE_SIZE \
 121         (sizeof(e1000_82580_rxpbs_table) / \
 122          sizeof(e1000_82580_rxpbs_table[0]))
 123
 124
 125 /**
 126  *  e1000_sgmii_uses_mdio_82575 - Determine if I2C pins are for external MDIO
 127  *  @hw: pointer to the HW structure
 128  *
 129  *  Called to determine if the I2C pins are being used for I2C or as an
 130  *  external MDIO interface since the two options are mutually exclusive.
 131  **/
 132 STATIC bool e1000_sgmii_uses_mdio_82575(struct e1000_hw *hw)
 133 {
 134         u32 reg = 0;
 135         bool ext_mdio = false;
 136
 137         DEBUGFUNC("e1000_sgmii_uses_mdio_82575");
 138
 139         switch (hw->mac.type) {
 140         case e1000_82575:
 141         case e1000_82576:
 142                 reg = E1000_READ_REG(hw, E1000_MDIC);
 143                 ext_mdio = !!(reg & E1000_MDIC_DEST);
 144                 break;
 145         case e1000_82580:
 146         case e1000_i350:
 147         case e1000_i354:
 148         case e1000_i210:
 149         case e1000_i211:
 150                 reg = E1000_READ_REG(hw, E1000_MDICNFG);
 151                 ext_mdio = !!(reg & E1000_MDICNFG_EXT_MDIO);
 152                 break;
 153         default:
 154                 break;
 155         }
 156         return ext_mdio;
 157 }
 158
 159 /**
 160  *  e1000_init_phy_params_82575 - Init PHY func ptrs.
 161  *  @hw: pointer to the HW structure
 162  **/
 163 STATIC s32 e1000_init_phy_params_82575(struct e1000_hw *hw)
 164 {
 165         struct e1000_phy_info *phy = &hw->phy;
 166         s32 ret_val = E1000_SUCCESS;
 167         u32 ctrl_ext;
 168
 169         DEBUGFUNC("e1000_init_phy_params_82575");
 170
 171         phy->ops.read_i2c_byte = e1000_read_i2c_byte_generic;
 172         phy->ops.write_i2c_byte = e1000_write_i2c_byte_generic;
 173
 174         if (hw->phy.media_type != e1000_media_type_copper) {
 175                 phy->type = e1000_phy_none;
 176                 goto out;
 177         }
 178
 179         phy->ops.power_up   = e1000_power_up_phy_copper;
 180         phy->ops.power_down = e1000_power_down_phy_copper_82575;
 181
 182         phy->autoneg_mask       = AUTONEG_ADVERTISE_SPEED_DEFAULT;
 183         phy->reset_delay_us     = 100;
 184
 185         phy->ops.acquire        = e1000_acquire_phy_82575;
 186         phy->ops.check_reset_block = e1000_check_reset_block_generic;
 187         phy->ops.commit         = e1000_phy_sw_reset_generic;
 188         phy->ops.get_cfg_done   = e1000_get_cfg_done_82575;
 189         phy->ops.release        = e1000_release_phy_82575;
 190
 191         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
 192
 193         if (e1000_sgmii_active_82575(hw)) {
 194                 phy->ops.reset = e1000_phy_hw_reset_sgmii_82575;
 195                 ctrl_ext |= E1000_CTRL_I2C_ENA;
 196         } else {
 197                 phy->ops.reset = e1000_phy_hw_reset_generic;
 198                 ctrl_ext &= ~E1000_CTRL_I2C_ENA;
 199         }
 200
 201         E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
 202         e1000_reset_mdicnfg_82580(hw);
 203
 204         if (e1000_sgmii_active_82575(hw) && !e1000_sgmii_uses_mdio_82575(hw)) {
 205                 phy->ops.read_reg = e1000_read_phy_reg_sgmii_82575;
 206                 phy->ops.write_reg = e1000_write_phy_reg_sgmii_82575;
 207         } else {
 208                 switch (hw->mac.type) {
 209                 case e1000_82580:
 210                 case e1000_i350:
 211                 case e1000_i354:
 212                         phy->ops.read_reg = e1000_read_phy_reg_82580;
 213                         phy->ops.write_reg = e1000_write_phy_reg_82580;
 214                         break;
 215                 case e1000_i210:
 216                 case e1000_i211:
 217                         phy->ops.read_reg = e1000_read_phy_reg_gs40g;
 218                         phy->ops.write_reg = e1000_write_phy_reg_gs40g;
 219                         break;
 220                 default:
 221                         phy->ops.read_reg = e1000_read_phy_reg_igp;
 222                         phy->ops.write_reg = e1000_write_phy_reg_igp;
 223                 }
 224         }
 225
 226         /* Set phy->phy_addr and phy->id. */
 227         ret_val = e1000_get_phy_id_82575(hw);
 228
 229         /* Verify phy id and set remaining function pointers */
 230         switch (phy->id) {
 231         case M88E1543_E_PHY_ID:
 232         case M88E1512_E_PHY_ID:
 233         case I347AT4_E_PHY_ID:
 234         case M88E1112_E_PHY_ID:
 235         case M88E1340M_E_PHY_ID:
 236         case M88E1111_I_PHY_ID:
 237                 phy->type               = e1000_phy_m88;
 238                 phy->ops.check_polarity = e1000_check_polarity_m88;
 239                 phy->ops.get_info       = e1000_get_phy_info_m88;
 240                 if (phy->id == I347AT4_E_PHY_ID ||
 241                     phy->id == M88E1112_E_PHY_ID ||
 242                     phy->id == M88E1340M_E_PHY_ID)
 243                         phy->ops.get_cable_length =
 244                                          e1000_get_cable_length_m88_gen2;
 245                 else if (phy->id == M88E1543_E_PHY_ID ||
 246                          phy->id == M88E1512_E_PHY_ID)
 247                         phy->ops.get_cable_length =
 248                                          e1000_get_cable_length_m88_gen2;
 249                 else
 250                         phy->ops.get_cable_length = e1000_get_cable_length_m88;
 251                 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_m88;
 252                 /* Check if this PHY is confgured for media swap. */
 253                 if (phy->id == M88E1112_E_PHY_ID) {
 254                         u16 data;
 255
 256                         ret_val = phy->ops.write_reg(hw,
 257                                                      E1000_M88E1112_PAGE_ADDR,
 258                                                      2);
 259                         if (ret_val)
 260                                 goto out;
 261
 262                         ret_val = phy->ops.read_reg(hw,
 263                                                     E1000_M88E1112_MAC_CTRL_1,
 264                                                     &data);
 265                         if (ret_val)
 266                                 goto out;
 267
 268                         data = (data & E1000_M88E1112_MAC_CTRL_1_MODE_MASK) >>
 269                                E1000_M88E1112_MAC_CTRL_1_MODE_SHIFT;
 270                         if (data == E1000_M88E1112_AUTO_COPPER_SGMII ||
 271                             data == E1000_M88E1112_AUTO_COPPER_BASEX)
 272                                 hw->mac.ops.check_for_link =
 273                                                 e1000_check_for_link_media_swap;
 274                 }
 275                 if (phy->id == M88E1512_E_PHY_ID) {
 276                         ret_val = e1000_initialize_M88E1512_phy(hw);
 277                         if (ret_val)
 278                                 goto out;
 279                 }
 280                 if (phy->id == M88E1543_E_PHY_ID) {
 281                         ret_val = e1000_initialize_M88E1543_phy(hw);
 282                         if (ret_val)
 283                                 goto out;
 284                 }
 285                 break;
 286         case IGP03E1000_E_PHY_ID:
 287         case IGP04E1000_E_PHY_ID:
 288                 phy->type = e1000_phy_igp_3;
 289                 phy->ops.check_polarity = e1000_check_polarity_igp;
 290                 phy->ops.get_info = e1000_get_phy_info_igp;
 291                 phy->ops.get_cable_length = e1000_get_cable_length_igp_2;
 292                 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_igp;
 293                 phy->ops.set_d0_lplu_state = e1000_set_d0_lplu_state_82575;
 294                 phy->ops.set_d3_lplu_state = e1000_set_d3_lplu_state_generic;
 295                 break;
 296         case I82580_I_PHY_ID:
 297         case I350_I_PHY_ID:
 298                 phy->type = e1000_phy_82580;
 299                 phy->ops.check_polarity = e1000_check_polarity_82577;
 300                 phy->ops.force_speed_duplex =
 301                                          e1000_phy_force_speed_duplex_82577;
 302                 phy->ops.get_cable_length = e1000_get_cable_length_82577;
 303                 phy->ops.get_info = e1000_get_phy_info_82577;
 304                 phy->ops.set_d0_lplu_state = e1000_set_d0_lplu_state_82580;
 305                 phy->ops.set_d3_lplu_state = e1000_set_d3_lplu_state_82580;
 306                 break;
 307         case I210_I_PHY_ID:
 308                 phy->type               = e1000_phy_i210;
 309                 phy->ops.check_polarity = e1000_check_polarity_m88;
 310                 phy->ops.get_info       = e1000_get_phy_info_m88;
 311                 phy->ops.get_cable_length = e1000_get_cable_length_m88_gen2;
 312                 phy->ops.set_d0_lplu_state = e1000_set_d0_lplu_state_82580;
 313                 phy->ops.set_d3_lplu_state = e1000_set_d3_lplu_state_82580;
 314                 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_m88;
 315                 break;
 316         default:
 317                 ret_val = -E1000_ERR_PHY;
 318                 goto out;
 319         }
 320
 321 out:
 322         return ret_val;
 323 }
 324
 325 /**
 326  *  e1000_init_nvm_params_82575 - Init NVM func ptrs.
 327  *  @hw: pointer to the HW structure
 328  **/
 329 s32 e1000_init_nvm_params_82575(struct e1000_hw *hw)
 330 {
 331         struct e1000_nvm_info *nvm = &hw->nvm;
 332         u32 eecd = E1000_READ_REG(hw, E1000_EECD);
 333         u16 size;
 334
 335         DEBUGFUNC("e1000_init_nvm_params_82575");
 336
 337         size = (u16)((eecd & E1000_EECD_SIZE_EX_MASK) >>
 338                      E1000_EECD_SIZE_EX_SHIFT);
 339         /*
 340          * Added to a constant, "size" becomes the left-shift value
 341          * for setting word_size.
 342          */
 343         size += NVM_WORD_SIZE_BASE_SHIFT;
 344
 345         /* Just in case size is out of range, cap it to the largest
 346          * EEPROM size supported
 347          */
 348         if (size > 15)
 349                 size = 15;
 350
 351         nvm->word_size = 1 << size;
 352         if (hw->mac.type < e1000_i210) {
 353                 nvm->opcode_bits = 8;
 354                 nvm->delay_usec = 1;
 355
 356                 switch (nvm->override) {
 357                 case e1000_nvm_override_spi_large:
 358                         nvm->page_size = 32;
 359                         nvm->address_bits = 16;
 360                         break;
 361                 case e1000_nvm_override_spi_small:
 362                         nvm->page_size = 8;
 363                         nvm->address_bits = 8;
 364                         break;
 365                 default:
 366                         nvm->page_size = eecd & E1000_EECD_ADDR_BITS ? 32 : 8;
 367                         nvm->address_bits = eecd & E1000_EECD_ADDR_BITS ?
 368                                             16 : 8;
 369                         break;
 370                 }
 371                 if (nvm->word_size == (1 << 15))
 372                         nvm->page_size = 128;
 373
 374                 nvm->type = e1000_nvm_eeprom_spi;
 375         } else {
 376                 nvm->type = e1000_nvm_flash_hw;
 377         }
 378
 379         /* Function Pointers */
 380         nvm->ops.acquire = e1000_acquire_nvm_82575;
 381         nvm->ops.release = e1000_release_nvm_82575;
 382         if (nvm->word_size < (1 << 15))
 383                 nvm->ops.read = e1000_read_nvm_eerd;
 384         else
 385                 nvm->ops.read = e1000_read_nvm_spi;
 386
 387         nvm->ops.write = e1000_write_nvm_spi;
 388         nvm->ops.validate = e1000_validate_nvm_checksum_generic;
 389         nvm->ops.update = e1000_update_nvm_checksum_generic;
 390         nvm->ops.valid_led_default = e1000_valid_led_default_82575;
 391
 392         /* override generic family function pointers for specific descendants */
 393         switch (hw->mac.type) {
 394         case e1000_82580:
 395                 nvm->ops.validate = e1000_validate_nvm_checksum_82580;
 396                 nvm->ops.update = e1000_update_nvm_checksum_82580;
 397                 break;
 398         case e1000_i350:
 399         case e1000_i354:
 400                 nvm->ops.validate = e1000_validate_nvm_checksum_i350;
 401                 nvm->ops.update = e1000_update_nvm_checksum_i350;
 402                 break;
 403         default:
 404                 break;
 405         }
 406
 407         return E1000_SUCCESS;
 408 }
 409
 410 /**
 411  *  e1000_init_mac_params_82575 - Init MAC func ptrs.
 412  *  @hw: pointer to the HW structure
 413  **/
 414 STATIC s32 e1000_init_mac_params_82575(struct e1000_hw *hw)
 415 {
 416         struct e1000_mac_info *mac = &hw->mac;
 417         struct e1000_dev_spec_82575 *dev_spec = &hw->dev_spec._82575;
 418
 419         DEBUGFUNC("e1000_init_mac_params_82575");
 420
 421         /* Derives media type */
 422         e1000_get_media_type_82575(hw);
 423         /* Set mta register count */
 424         mac->mta_reg_count = 128;
 425         /* Set uta register count */
 426         mac->uta_reg_count = (hw->mac.type == e1000_82575) ? 0 : 128;
 427         /* Set rar entry count */
 428         mac->rar_entry_count = E1000_RAR_ENTRIES_82575;
 429         if (mac->type == e1000_82576)
 430                 mac->rar_entry_count = E1000_RAR_ENTRIES_82576;
 431         if (mac->type == e1000_82580)
 432                 mac->rar_entry_count = E1000_RAR_ENTRIES_82580;
 433         if (mac->type == e1000_i350 || mac->type == e1000_i354)
 434                 mac->rar_entry_count = E1000_RAR_ENTRIES_I350;
 435
 436         /* Enable EEE default settings for EEE supported devices */
 437         if (mac->type >= e1000_i350)
 438                 dev_spec->eee_disable = false;
 439
 440         /* Allow a single clear of the SW semaphore on I210 and newer */
 441         if (mac->type >= e1000_i210)
 442                 dev_spec->clear_semaphore_once = true;
 443
 444         /* Set if part includes ASF firmware */
 445         mac->asf_firmware_present = true;
 446         /* FWSM register */
 447         mac->has_fwsm = true;
 448         /* ARC supported; valid only if manageability features are enabled. */
 449         mac->arc_subsystem_valid =
 450                 !!(E1000_READ_REG(hw, E1000_FWSM) & E1000_FWSM_MODE_MASK);
 451
 452         /* Function pointers */
 453
 454         /* bus type/speed/width */
 455         mac->ops.get_bus_info = e1000_get_bus_info_pcie_generic;
 456         /* reset */
 457         if (mac->type >= e1000_82580)
 458                 mac->ops.reset_hw = e1000_reset_hw_82580;
 459         else
 460         mac->ops.reset_hw = e1000_reset_hw_82575;
 461         /* hw initialization */
 462         if ((mac->type == e1000_i210) || (mac->type == e1000_i211))
 463                 mac->ops.init_hw = e1000_init_hw_i210;
 464         else
 465         mac->ops.init_hw = e1000_init_hw_82575;
 466         /* link setup */
 467         mac->ops.setup_link = e1000_setup_link_generic;
 468         /* physical interface link setup */
 469         mac->ops.setup_physical_interface =
 470                 (hw->phy.media_type == e1000_media_type_copper)
 471                 ? e1000_setup_copper_link_82575 : e1000_setup_serdes_link_82575;
 472         /* physical interface shutdown */
 473         mac->ops.shutdown_serdes = e1000_shutdown_serdes_link_82575;
 474         /* physical interface power up */
 475         mac->ops.power_up_serdes = e1000_power_up_serdes_link_82575;
 476         /* check for link */
 477         mac->ops.check_for_link = e1000_check_for_link_82575;
 478         /* read mac address */
 479         mac->ops.read_mac_addr = e1000_read_mac_addr_82575;
 480         /* configure collision distance */
 481         mac->ops.config_collision_dist = e1000_config_collision_dist_82575;
 482         /* multicast address update */
 483         mac->ops.update_mc_addr_list = e1000_update_mc_addr_list_generic;
 484         if (hw->mac.type == e1000_i350 || mac->type == e1000_i354) {
 485                 /* writing VFTA */
 486                 mac->ops.write_vfta = e1000_write_vfta_i350;
 487                 /* clearing VFTA */
 488                 mac->ops.clear_vfta = e1000_clear_vfta_i350;
 489         } else {
 490                 /* writing VFTA */
 491                 mac->ops.write_vfta = e1000_write_vfta_generic;
 492                 /* clearing VFTA */
 493                 mac->ops.clear_vfta = e1000_clear_vfta_generic;
 494         }
 495         if (hw->mac.type >= e1000_82580)
 496                 mac->ops.validate_mdi_setting =
 497                                 e1000_validate_mdi_setting_crossover_generic;
 498         /* ID LED init */
 499         mac->ops.id_led_init = e1000_id_led_init_generic;
 500         /* blink LED */
 501         mac->ops.blink_led = e1000_blink_led_generic;
 502         /* setup LED */
 503         mac->ops.setup_led = e1000_setup_led_generic;
 504         /* cleanup LED */
 505         mac->ops.cleanup_led = e1000_cleanup_led_generic;
 506         /* turn on/off LED */
 507         mac->ops.led_on = e1000_led_on_generic;
 508         mac->ops.led_off = e1000_led_off_generic;
 509         /* clear hardware counters */
 510         mac->ops.clear_hw_cntrs = e1000_clear_hw_cntrs_82575;
 511         /* link info */
 512         mac->ops.get_link_up_info = e1000_get_link_up_info_82575;
 513         /* acquire SW_FW sync */
 514         mac->ops.acquire_swfw_sync = e1000_acquire_swfw_sync_82575;
 515         mac->ops.release_swfw_sync = e1000_release_swfw_sync_82575;
 516         if (mac->type >= e1000_i210) {
 517                 mac->ops.acquire_swfw_sync = e1000_acquire_swfw_sync_i210;
 518                 mac->ops.release_swfw_sync = e1000_release_swfw_sync_i210;
 519         }
 520
 521         /* set lan id for port to determine which phy lock to use */
 522         hw->mac.ops.set_lan_id(hw);
 523
 524         return E1000_SUCCESS;
 525 }
 526
 527 /**
 528  *  e1000_init_function_pointers_82575 - Init func ptrs.
 529  *  @hw: pointer to the HW structure
 530  *
 531  *  Called to initialize all function pointers and parameters.
 532  **/
 533 void e1000_init_function_pointers_82575(struct e1000_hw *hw)
 534 {
 535         DEBUGFUNC("e1000_init_function_pointers_82575");
 536
 537         hw->mac.ops.init_params = e1000_init_mac_params_82575;
 538         hw->nvm.ops.init_params = e1000_init_nvm_params_82575;
 539         hw->phy.ops.init_params = e1000_init_phy_params_82575;
 540         hw->mbx.ops.init_params = e1000_init_mbx_params_pf;
 541 }
 542
 543 /**
 544  *  e1000_acquire_phy_82575 - Acquire rights to access PHY
 545  *  @hw: pointer to the HW structure
 546  *
 547  *  Acquire access rights to the correct PHY.
 548  **/
 549 STATIC s32 e1000_acquire_phy_82575(struct e1000_hw *hw)
 550 {
 551         u16 mask = E1000_SWFW_PHY0_SM;
 552
 553         DEBUGFUNC("e1000_acquire_phy_82575");
 554
 555         if (hw->bus.func == E1000_FUNC_1)
 556                 mask = E1000_SWFW_PHY1_SM;
 557         else if (hw->bus.func == E1000_FUNC_2)
 558                 mask = E1000_SWFW_PHY2_SM;
 559         else if (hw->bus.func == E1000_FUNC_3)
 560                 mask = E1000_SWFW_PHY3_SM;
 561
 562         return hw->mac.ops.acquire_swfw_sync(hw, mask);
 563 }
 564
 565 /**
 566  *  e1000_release_phy_82575 - Release rights to access PHY
 567  *  @hw: pointer to the HW structure
 568  *
 569  *  A wrapper to release access rights to the correct PHY.
 570  **/
 571 STATIC void e1000_release_phy_82575(struct e1000_hw *hw)
 572 {
 573         u16 mask = E1000_SWFW_PHY0_SM;
 574
 575         DEBUGFUNC("e1000_release_phy_82575");
 576
 577         if (hw->bus.func == E1000_FUNC_1)
 578                 mask = E1000_SWFW_PHY1_SM;
 579         else if (hw->bus.func == E1000_FUNC_2)
 580                 mask = E1000_SWFW_PHY2_SM;
 581         else if (hw->bus.func == E1000_FUNC_3)
 582                 mask = E1000_SWFW_PHY3_SM;
 583
 584         hw->mac.ops.release_swfw_sync(hw, mask);
 585 }
 586
 587 /**
 588  *  e1000_read_phy_reg_sgmii_82575 - Read PHY register using sgmii
 589  *  @hw: pointer to the HW structure
 590  *  @offset: register offset to be read
 591  *  @data: pointer to the read data
 592  *
 593  *  Reads the PHY register at offset using the serial gigabit media independent
 594  *  interface and stores the retrieved information in data.
 595  **/
 596 STATIC s32 e1000_read_phy_reg_sgmii_82575(struct e1000_hw *hw, u32 offset,
 597                                           u16 *data)
 598 {
 599         s32 ret_val = -E1000_ERR_PARAM;
 600
 601         DEBUGFUNC("e1000_read_phy_reg_sgmii_82575");
 602
 603         if (offset > E1000_MAX_SGMII_PHY_REG_ADDR) {
 604                 DEBUGOUT1("PHY Address %u is out of range\n", offset);
 605                 goto out;
 606         }
 607
 608         ret_val = hw->phy.ops.acquire(hw);
 609         if (ret_val)
 610                 goto out;
 611
 612         ret_val = e1000_read_phy_reg_i2c(hw, offset, data);
 613
 614         hw->phy.ops.release(hw);
 615
 616 out:
 617         return ret_val;
 618 }
 619
 620 /**
 621  *  e1000_write_phy_reg_sgmii_82575 - Write PHY register using sgmii
 622  *  @hw: pointer to the HW structure
 623  *  @offset: register offset to write to
 624  *  @data: data to write at register offset
 625  *
 626  *  Writes the data to PHY register at the offset using the serial gigabit
 627  *  media independent interface.
 628  **/
 629 STATIC s32 e1000_write_phy_reg_sgmii_82575(struct e1000_hw *hw, u32 offset,
 630                                            u16 data)
 631 {
 632         s32 ret_val = -E1000_ERR_PARAM;
 633
 634         DEBUGFUNC("e1000_write_phy_reg_sgmii_82575");
 635
 636         if (offset > E1000_MAX_SGMII_PHY_REG_ADDR) {
 637                 DEBUGOUT1("PHY Address %d is out of range\n", offset);
 638                 goto out;
 639         }
 640
 641         ret_val = hw->phy.ops.acquire(hw);
 642         if (ret_val)
 643                 goto out;
 644
 645         ret_val = e1000_write_phy_reg_i2c(hw, offset, data);
 646
 647         hw->phy.ops.release(hw);
 648
 649 out:
 650         return ret_val;
 651 }
 652
 653 /**
 654  *  e1000_get_phy_id_82575 - Retrieve PHY addr and id
 655  *  @hw: pointer to the HW structure
 656  *
 657  *  Retrieves the PHY address and ID for both PHY's which do and do not use
 658  *  sgmi interface.
 659  **/
 660 STATIC s32 e1000_get_phy_id_82575(struct e1000_hw *hw)
 661 {
 662         struct e1000_phy_info *phy = &hw->phy;
 663         s32  ret_val = E1000_SUCCESS;
 664         u16 phy_id;
 665         u32 ctrl_ext;
 666         u32 mdic;
 667
 668         DEBUGFUNC("e1000_get_phy_id_82575");
 669
 670         /* some i354 devices need an extra read for phy id */
 671         if (hw->mac.type == e1000_i354)
 672                 e1000_get_phy_id(hw);
 673
 674         /*
 675          * For SGMII PHYs, we try the list of possible addresses until
 676          * we find one that works.  For non-SGMII PHYs
 677          * (e.g. integrated copper PHYs), an address of 1 should
 678          * work.  The result of this function should mean phy->phy_addr
 679          * and phy->id are set correctly.
 680          */
 681         if (!e1000_sgmii_active_82575(hw)) {
 682                 phy->addr = 1;
 683                 ret_val = e1000_get_phy_id(hw);
 684                 goto out;
 685         }
 686
 687         if (e1000_sgmii_uses_mdio_82575(hw)) {
 688                 switch (hw->mac.type) {
 689                 case e1000_82575:
 690                 case e1000_82576:
 691                         mdic = E1000_READ_REG(hw, E1000_MDIC);
 692                         mdic &= E1000_MDIC_PHY_MASK;
 693                         phy->addr = mdic >> E1000_MDIC_PHY_SHIFT;
 694                         break;
 695                 case e1000_82580:
 696                 case e1000_i350:
 697                 case e1000_i354:
 698                 case e1000_i210:
 699                 case e1000_i211:
 700                         mdic = E1000_READ_REG(hw, E1000_MDICNFG);
 701                         mdic &= E1000_MDICNFG_PHY_MASK;
 702                         phy->addr = mdic >> E1000_MDICNFG_PHY_SHIFT;
 703                         break;
 704                 default:
 705                         ret_val = -E1000_ERR_PHY;
 706                         goto out;
 707                         break;
 708                 }
 709                 ret_val = e1000_get_phy_id(hw);
 710                 goto out;
 711         }
 712
 713         /* Power on sgmii phy if it is disabled */
 714         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
 715         E1000_WRITE_REG(hw, E1000_CTRL_EXT,
 716                         ctrl_ext & ~E1000_CTRL_EXT_SDP3_DATA);
 717         E1000_WRITE_FLUSH(hw);
 718         msec_delay(300);
 719
 720         /*
 721          * The address field in the I2CCMD register is 3 bits and 0 is invalid.
 722          * Therefore, we need to test 1-7
 723          */
 724         for (phy->addr = 1; phy->addr < 8; phy->addr++) {
 725                 ret_val = e1000_read_phy_reg_sgmii_82575(hw, PHY_ID1, &phy_id);
 726                 if (ret_val == E1000_SUCCESS) {
 727                         DEBUGOUT2("Vendor ID 0x%08X read at address %u\n",
 728                                   phy_id, phy->addr);
 729                         /*
 730                          * At the time of this writing, The M88 part is
 731                          * the only supported SGMII PHY product.
 732                          */
 733                         if (phy_id == M88_VENDOR)
 734                                 break;
 735                 } else {
 736                         DEBUGOUT1("PHY address %u was unreadable\n",
 737                                   phy->addr);
 738                 }
 739         }
 740
 741         /* A valid PHY type couldn't be found. */
 742         if (phy->addr == 8) {
 743                 phy->addr = 0;
 744                 ret_val = -E1000_ERR_PHY;
 745         } else {
 746                 ret_val = e1000_get_phy_id(hw);
 747         }
 748
 749         /* restore previous sfp cage power state */
 750         E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
 751
 752 out:
 753         return ret_val;
 754 }
 755
 756 /**
 757  *  e1000_phy_hw_reset_sgmii_82575 - Performs a PHY reset
 758  *  @hw: pointer to the HW structure
 759  *
 760  *  Resets the PHY using the serial gigabit media independent interface.
 761  **/
 762 STATIC s32 e1000_phy_hw_reset_sgmii_82575(struct e1000_hw *hw)
 763 {
 764         s32 ret_val = E1000_SUCCESS;
 765         struct e1000_phy_info *phy = &hw->phy;
 766
 767         DEBUGFUNC("e1000_phy_hw_reset_sgmii_82575");
 768
 769         /*
 770          * This isn't a true "hard" reset, but is the only reset
 771          * available to us at this time.
 772          */
 773
 774         DEBUGOUT("Soft resetting SGMII attached PHY...\n");
 775
 776         if (!(hw->phy.ops.write_reg))
 777                 goto out;
 778
 779         /*
 780          * SFP documentation requires the following to configure the SPF module
 781          * to work on SGMII.  No further documentation is given.
 782          */
 783         ret_val = hw->phy.ops.write_reg(hw, 0x1B, 0x8084);
 784         if (ret_val)
 785                 goto out;
 786
 787         ret_val = hw->phy.ops.commit(hw);
 788         if (ret_val)
 789                 goto out;
 790
 791         if (phy->id == M88E1512_E_PHY_ID)
 792                 ret_val = e1000_initialize_M88E1512_phy(hw);
 793 out:
 794         return ret_val;
 795 }
 796
 797 /**
 798  *  e1000_set_d0_lplu_state_82575 - Set Low Power Linkup D0 state
 799  *  @hw: pointer to the HW structure
 800  *  @active: true to enable LPLU, false to disable
 801  *
 802  *  Sets the LPLU D0 state according to the active flag.  When
 803  *  activating LPLU this function also disables smart speed
 804  *  and vice versa.  LPLU will not be activated unless the
 805  *  device autonegotiation advertisement meets standards of
 806  *  either 10 or 10/100 or 10/100/1000 at all duplexes.
 807  *  This is a function pointer entry point only called by
 808  *  PHY setup routines.
 809  **/
 810 STATIC s32 e1000_set_d0_lplu_state_82575(struct e1000_hw *hw, bool active)
 811 {
 812         struct e1000_phy_info *phy = &hw->phy;
 813         s32 ret_val = E1000_SUCCESS;
 814         u16 data;
 815
 816         DEBUGFUNC("e1000_set_d0_lplu_state_82575");
 817
 818         if (!(hw->phy.ops.read_reg))
 819                 goto out;
 820
 821         ret_val = phy->ops.read_reg(hw, IGP02E1000_PHY_POWER_MGMT, &data);
 822         if (ret_val)
 823                 goto out;
 824
 825         if (active) {
 826                 data |= IGP02E1000_PM_D0_LPLU;
 827                 ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT,
 828                                              data);
 829                 if (ret_val)
 830                         goto out;
 831
 832                 /* When LPLU is enabled, we should disable SmartSpeed */
 833                 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
 834                                             &data);
 835                 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
 836                 ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
 837                                              data);
 838                 if (ret_val)
 839                         goto out;
 840         } else {
 841                 data &= ~IGP02E1000_PM_D0_LPLU;
 842                 ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT,
 843                                              data);
 844                 /*
 845                  * LPLU and SmartSpeed are mutually exclusive.  LPLU is used
 846                  * during Dx states where the power conservation is most
 847                  * important.  During driver activity we should enable
 848                  * SmartSpeed, so performance is maintained.
 849                  */
 850                 if (phy->smart_speed == e1000_smart_speed_on) {
 851                         ret_val = phy->ops.read_reg(hw,
 852                                                     IGP01E1000_PHY_PORT_CONFIG,
 853                                                     &data);
 854                         if (ret_val)
 855                                 goto out;
 856
 857                         data |= IGP01E1000_PSCFR_SMART_SPEED;
 858                         ret_val = phy->ops.write_reg(hw,
 859                                                      IGP01E1000_PHY_PORT_CONFIG,
 860                                                      data);
 861                         if (ret_val)
 862                                 goto out;
 863                 } else if (phy->smart_speed == e1000_smart_speed_off) {
 864                         ret_val = phy->ops.read_reg(hw,
 865                                                     IGP01E1000_PHY_PORT_CONFIG,
 866                                                     &data);
 867                         if (ret_val)
 868                                 goto out;
 869
 870                         data &= ~IGP01E1000_PSCFR_SMART_SPEED;
 871                         ret_val = phy->ops.write_reg(hw,
 872                                                      IGP01E1000_PHY_PORT_CONFIG,
 873                                                      data);
 874                         if (ret_val)
 875                                 goto out;
 876                 }
 877         }
 878
 879 out:
 880         return ret_val;
 881 }
 882
 883 /**
 884  *  e1000_set_d0_lplu_state_82580 - Set Low Power Linkup D0 state
 885  *  @hw: pointer to the HW structure
 886  *  @active: true to enable LPLU, false to disable
 887  *
 888  *  Sets the LPLU D0 state according to the active flag.  When
 889  *  activating LPLU this function also disables smart speed
 890  *  and vice versa.  LPLU will not be activated unless the
 891  *  device autonegotiation advertisement meets standards of
 892  *  either 10 or 10/100 or 10/100/1000 at all duplexes.
 893  *  This is a function pointer entry point only called by
 894  *  PHY setup routines.
 895  **/
 896 STATIC s32 e1000_set_d0_lplu_state_82580(struct e1000_hw *hw, bool active)
 897 {
 898         struct e1000_phy_info *phy = &hw->phy;
 899         u32 data;
 900
 901         DEBUGFUNC("e1000_set_d0_lplu_state_82580");
 902
 903         data = E1000_READ_REG(hw, E1000_82580_PHY_POWER_MGMT);
 904
 905         if (active) {
 906                 data |= E1000_82580_PM_D0_LPLU;
 907
 908                 /* When LPLU is enabled, we should disable SmartSpeed */
 909                 data &= ~E1000_82580_PM_SPD;
 910         } else {
 911                 data &= ~E1000_82580_PM_D0_LPLU;
 912
 913                 /*
 914                  * LPLU and SmartSpeed are mutually exclusive.  LPLU is used
 915                  * during Dx states where the power conservation is most
 916                  * important.  During driver activity we should enable
 917                  * SmartSpeed, so performance is maintained.
 918                  */
 919                 if (phy->smart_speed == e1000_smart_speed_on)
 920                         data |= E1000_82580_PM_SPD;
 921                 else if (phy->smart_speed == e1000_smart_speed_off)
 922                         data &= ~E1000_82580_PM_SPD;
 923         }
 924
 925         E1000_WRITE_REG(hw, E1000_82580_PHY_POWER_MGMT, data);
 926         return E1000_SUCCESS;
 927 }
 928
 929 /**
 930  *  e1000_set_d3_lplu_state_82580 - Sets low power link up state for D3
 931  *  @hw: pointer to the HW structure
 932  *  @active: boolean used to enable/disable lplu
 933  *
 934  *  Success returns 0, Failure returns 1
 935  *
 936  *  The low power link up (lplu) state is set to the power management level D3
 937  *  and SmartSpeed is disabled when active is true, else clear lplu for D3
 938  *  and enable Smartspeed.  LPLU and Smartspeed are mutually exclusive.  LPLU
 939  *  is used during Dx states where the power conservation is most important.
 940  *  During driver activity, SmartSpeed should be enabled so performance is
 941  *  maintained.
 942  **/
 943 s32 e1000_set_d3_lplu_state_82580(struct e1000_hw *hw, bool active)
 944 {
 945         struct e1000_phy_info *phy = &hw->phy;
 946         u32 data;
 947
 948         DEBUGFUNC("e1000_set_d3_lplu_state_82580");
 949
 950         data = E1000_READ_REG(hw, E1000_82580_PHY_POWER_MGMT);
 951
 952         if (!active) {
 953                 data &= ~E1000_82580_PM_D3_LPLU;
 954                 /*
 955                  * LPLU and SmartSpeed are mutually exclusive.  LPLU is used
 956                  * during Dx states where the power conservation is most
 957                  * important.  During driver activity we should enable
 958                  * SmartSpeed, so performance is maintained.
 959                  */
 960                 if (phy->smart_speed == e1000_smart_speed_on)
 961                         data |= E1000_82580_PM_SPD;
 962                 else if (phy->smart_speed == e1000_smart_speed_off)
 963                         data &= ~E1000_82580_PM_SPD;
 964         } else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) ||
 965                    (phy->autoneg_advertised == E1000_ALL_NOT_GIG) ||
 966                    (phy->autoneg_advertised == E1000_ALL_10_SPEED)) {
 967                 data |= E1000_82580_PM_D3_LPLU;
 968                 /* When LPLU is enabled, we should disable SmartSpeed */
 969                 data &= ~E1000_82580_PM_SPD;
 970         }
 971
 972         E1000_WRITE_REG(hw, E1000_82580_PHY_POWER_MGMT, data);
 973         return E1000_SUCCESS;
 974 }
 975
 976 /**
 977  *  e1000_acquire_nvm_82575 - Request for access to EEPROM
 978  *  @hw: pointer to the HW structure
 979  *
 980  *  Acquire the necessary semaphores for exclusive access to the EEPROM.
 981  *  Set the EEPROM access request bit and wait for EEPROM access grant bit.
 982  *  Return successful if access grant bit set, else clear the request for
 983  *  EEPROM access and return -E1000_ERR_NVM (-1).
 984  **/
 985 STATIC s32 e1000_acquire_nvm_82575(struct e1000_hw *hw)
 986 {
 987         s32 ret_val = E1000_SUCCESS;
 988
 989         DEBUGFUNC("e1000_acquire_nvm_82575");
 990
 991         ret_val = e1000_acquire_swfw_sync_82575(hw, E1000_SWFW_EEP_SM);
 992         if (ret_val)
 993                 goto out;
 994
 995         /*
 996          * Check if there is some access
 997          * error this access may hook on
 998          */
 999         if (hw->mac.type == e1000_i350) {
1000                 u32 eecd = E1000_READ_REG(hw, E1000_EECD);
1001                 if (eecd & (E1000_EECD_BLOCKED | E1000_EECD_ABORT |
1002                     E1000_EECD_TIMEOUT)) {
1003                         /* Clear all access error flags */
1004                         E1000_WRITE_REG(hw, E1000_EECD, eecd |
1005                                         E1000_EECD_ERROR_CLR);
1006                         DEBUGOUT("Nvm bit banging access error detected and cleared.\n");
1007                 }
1008         }
1009
1010         if (hw->mac.type == e1000_82580) {
1011                 u32 eecd = E1000_READ_REG(hw, E1000_EECD);
1012                 if (eecd & E1000_EECD_BLOCKED) {
1013                         /* Clear access error flag */
1014                         E1000_WRITE_REG(hw, E1000_EECD, eecd |
1015                                         E1000_EECD_BLOCKED);
1016                         DEBUGOUT("Nvm bit banging access error detected and cleared.\n");
1017                 }
1018         }
1019
1020         ret_val = e1000_acquire_nvm_generic(hw);
1021         if (ret_val)
1022                 e1000_release_swfw_sync_82575(hw, E1000_SWFW_EEP_SM);
1023
1024 out:
1025         return ret_val;
1026 }
1027
1028 /**
1029  *  e1000_release_nvm_82575 - Release exclusive access to EEPROM
1030  *  @hw: pointer to the HW structure
1031  *
1032  *  Stop any current commands to the EEPROM and clear the EEPROM request bit,
1033  *  then release the semaphores acquired.
1034  **/
1035 STATIC void e1000_release_nvm_82575(struct e1000_hw *hw)
1036 {
1037         DEBUGFUNC("e1000_release_nvm_82575");
1038
1039         e1000_release_nvm_generic(hw);
1040
1041         e1000_release_swfw_sync_82575(hw, E1000_SWFW_EEP_SM);
1042 }
1043
1044 /**
1045  *  e1000_acquire_swfw_sync_82575 - Acquire SW/FW semaphore
1046  *  @hw: pointer to the HW structure
1047  *  @mask: specifies which semaphore to acquire
1048  *
1049  *  Acquire the SW/FW semaphore to access the PHY or NVM.  The mask
1050  *  will also specify which port we're acquiring the lock for.
1051  **/
1052 STATIC s32 e1000_acquire_swfw_sync_82575(struct e1000_hw *hw, u16 mask)
1053 {
1054         u32 swfw_sync;
1055         u32 swmask = mask;
1056         u32 fwmask = mask << 16;
1057         s32 ret_val = E1000_SUCCESS;
1058         s32 i = 0, timeout = 200;
1059
1060         DEBUGFUNC("e1000_acquire_swfw_sync_82575");
1061
1062         while (i < timeout) {
1063                 if (e1000_get_hw_semaphore_generic(hw)) {
1064                         ret_val = -E1000_ERR_SWFW_SYNC;
1065                         goto out;
1066                 }
1067
1068                 swfw_sync = E1000_READ_REG(hw, E1000_SW_FW_SYNC);
1069                 if (!(swfw_sync & (fwmask | swmask)))
1070                         break;
1071
1072                 /*
1073                  * Firmware currently using resource (fwmask)
1074                  * or other software thread using resource (swmask)
1075                  */
1076                 e1000_put_hw_semaphore_generic(hw);
1077                 msec_delay_irq(5);
1078                 i++;
1079         }
1080
1081         if (i == timeout) {
1082                 DEBUGOUT("Driver can't access resource, SW_FW_SYNC timeout.\n");
1083                 ret_val = -E1000_ERR_SWFW_SYNC;
1084                 goto out;
1085         }
1086
1087         swfw_sync |= swmask;
1088         E1000_WRITE_REG(hw, E1000_SW_FW_SYNC, swfw_sync);
1089
1090         e1000_put_hw_semaphore_generic(hw);
1091
1092 out:
1093         return ret_val;
1094 }
1095
1096 /**
1097  *  e1000_release_swfw_sync_82575 - Release SW/FW semaphore
1098  *  @hw: pointer to the HW structure
1099  *  @mask: specifies which semaphore to acquire
1100  *
1101  *  Release the SW/FW semaphore used to access the PHY or NVM.  The mask
1102  *  will also specify which port we're releasing the lock for.
1103  **/
1104 STATIC void e1000_release_swfw_sync_82575(struct e1000_hw *hw, u16 mask)
1105 {
1106         u32 swfw_sync;
1107
1108         DEBUGFUNC("e1000_release_swfw_sync_82575");
1109
1110         while (e1000_get_hw_semaphore_generic(hw) != E1000_SUCCESS)
1111                 ; /* Empty */
1112
1113         swfw_sync = E1000_READ_REG(hw, E1000_SW_FW_SYNC);
1114         swfw_sync &= ~mask;
1115         E1000_WRITE_REG(hw, E1000_SW_FW_SYNC, swfw_sync);
1116
1117         e1000_put_hw_semaphore_generic(hw);
1118 }
1119
1120 /**
1121  *  e1000_get_cfg_done_82575 - Read config done bit
1122  *  @hw: pointer to the HW structure
1123  *
1124  *  Read the management control register for the config done bit for
1125  *  completion status.  NOTE: silicon which is EEPROM-less will fail trying
1126  *  to read the config done bit, so an error is *ONLY* logged and returns
1127  *  E1000_SUCCESS.  If we were to return with error, EEPROM-less silicon
1128  *  would not be able to be reset or change link.
1129  **/
1130 STATIC s32 e1000_get_cfg_done_82575(struct e1000_hw *hw)
1131 {
1132         s32 timeout = PHY_CFG_TIMEOUT;
1133         u32 mask = E1000_NVM_CFG_DONE_PORT_0;
1134
1135         DEBUGFUNC("e1000_get_cfg_done_82575");
1136
1137         if (hw->bus.func == E1000_FUNC_1)
1138                 mask = E1000_NVM_CFG_DONE_PORT_1;
1139         else if (hw->bus.func == E1000_FUNC_2)
1140                 mask = E1000_NVM_CFG_DONE_PORT_2;
1141         else if (hw->bus.func == E1000_FUNC_3)
1142                 mask = E1000_NVM_CFG_DONE_PORT_3;
1143         while (timeout) {
1144                 if (E1000_READ_REG(hw, E1000_EEMNGCTL) & mask)
1145                         break;
1146                 msec_delay(1);
1147                 timeout--;
1148         }
1149         if (!timeout)
1150                 DEBUGOUT("MNG configuration cycle has not completed.\n");
1151
1152         /* If EEPROM is not marked present, init the PHY manually */
1153         if (!(E1000_READ_REG(hw, E1000_EECD) & E1000_EECD_PRES) &&
1154             (hw->phy.type == e1000_phy_igp_3))
1155                 e1000_phy_init_script_igp3(hw);
1156
1157         return E1000_SUCCESS;
1158 }
1159
1160 /**
1161  *  e1000_get_link_up_info_82575 - Get link speed/duplex info
1162  *  @hw: pointer to the HW structure
1163  *  @speed: stores the current speed
1164  *  @duplex: stores the current duplex
1165  *
1166  *  This is a wrapper function, if using the serial gigabit media independent
1167  *  interface, use PCS to retrieve the link speed and duplex information.
1168  *  Otherwise, use the generic function to get the link speed and duplex info.
1169  **/
1170 STATIC s32 e1000_get_link_up_info_82575(struct e1000_hw *hw, u16 *speed,
1171                                         u16 *duplex)
1172 {
1173         s32 ret_val;
1174
1175         DEBUGFUNC("e1000_get_link_up_info_82575");
1176
1177         if (hw->phy.media_type != e1000_media_type_copper)
1178                 ret_val = e1000_get_pcs_speed_and_duplex_82575(hw, speed,
1179                                                                duplex);
1180         else
1181                 ret_val = e1000_get_speed_and_duplex_copper_generic(hw, speed,
1182                                                                     duplex);
1183
1184         return ret_val;
1185 }
1186
1187 /**
1188  *  e1000_check_for_link_82575 - Check for link
1189  *  @hw: pointer to the HW structure
1190  *
1191  *  If sgmii is enabled, then use the pcs register to determine link, otherwise
1192  *  use the generic interface for determining link.
1193  **/
1194 STATIC s32 e1000_check_for_link_82575(struct e1000_hw *hw)
1195 {
1196         s32 ret_val;
1197         u16 speed, duplex;
1198
1199         DEBUGFUNC("e1000_check_for_link_82575");
1200
1201         if (hw->phy.media_type != e1000_media_type_copper) {
1202                 ret_val = e1000_get_pcs_speed_and_duplex_82575(hw, &speed,
1203                                                                &duplex);
1204                 /*
1205                  * Use this flag to determine if link needs to be checked or
1206                  * not.  If we have link clear the flag so that we do not
1207                  * continue to check for link.
1208                  */
1209                 hw->mac.get_link_status = !hw->mac.serdes_has_link;
1210
1211                 /*
1212                  * Configure Flow Control now that Auto-Neg has completed.
1213                  * First, we need to restore the desired flow control
1214                  * settings because we may have had to re-autoneg with a
1215                  * different link partner.
1216                  */
1217                 ret_val = e1000_config_fc_after_link_up_generic(hw);
1218                 if (ret_val)
1219                         DEBUGOUT("Error configuring flow control\n");
1220         } else {
1221                 ret_val = e1000_check_for_copper_link_generic(hw);
1222         }
1223
1224         return ret_val;
1225 }
1226
1227 /**
1228  *  e1000_check_for_link_media_swap - Check which M88E1112 interface linked
1229  *  @hw: pointer to the HW structure
1230  *
1231  *  Poll the M88E1112 interfaces to see which interface achieved link.
1232  */
1233 STATIC s32 e1000_check_for_link_media_swap(struct e1000_hw *hw)
1234 {
1235         struct e1000_phy_info *phy = &hw->phy;
1236         s32 ret_val;
1237         u16 data;
1238         u8 port = 0;
1239
1240         DEBUGFUNC("e1000_check_for_link_media_swap");
1241
1242         /* Check for copper. */
1243         ret_val = phy->ops.write_reg(hw, E1000_M88E1112_PAGE_ADDR, 0);
1244         if (ret_val)
1245                 return ret_val;
1246
1247         ret_val = phy->ops.read_reg(hw, E1000_M88E1112_STATUS, &data);
1248         if (ret_val)
1249                 return ret_val;
1250
1251         if (data & E1000_M88E1112_STATUS_LINK)
1252                 port = E1000_MEDIA_PORT_COPPER;
1253
1254         /* Check for other. */
1255         ret_val = phy->ops.write_reg(hw, E1000_M88E1112_PAGE_ADDR, 1);
1256         if (ret_val)
1257                 return ret_val;
1258
1259         ret_val = phy->ops.read_reg(hw, E1000_M88E1112_STATUS, &data);
1260         if (ret_val)
1261                 return ret_val;
1262
1263         if (data & E1000_M88E1112_STATUS_LINK)
1264                 port = E1000_MEDIA_PORT_OTHER;
1265
1266         /* Determine if a swap needs to happen. */
1267         if (port && (hw->dev_spec._82575.media_port != port)) {
1268                 hw->dev_spec._82575.media_port = port;
1269                 hw->dev_spec._82575.media_changed = true;
1270         }
1271
1272         if (port == E1000_MEDIA_PORT_COPPER) {
1273                 /* reset page to 0 */
1274                 ret_val = phy->ops.write_reg(hw, E1000_M88E1112_PAGE_ADDR, 0);
1275                 if (ret_val)
1276                         return ret_val;
1277                 e1000_check_for_link_82575(hw);
1278         } else {
1279                 e1000_check_for_link_82575(hw);
1280                 /* reset page to 0 */
1281                 ret_val = phy->ops.write_reg(hw, E1000_M88E1112_PAGE_ADDR, 0);
1282                 if (ret_val)
1283                         return ret_val;
1284         }
1285
1286         return E1000_SUCCESS;
1287 }
1288
1289 /**
1290  *  e1000_power_up_serdes_link_82575 - Power up the serdes link after shutdown
1291  *  @hw: pointer to the HW structure
1292  **/
1293 STATIC void e1000_power_up_serdes_link_82575(struct e1000_hw *hw)
1294 {
1295         u32 reg;
1296
1297         DEBUGFUNC("e1000_power_up_serdes_link_82575");
1298
1299         if ((hw->phy.media_type != e1000_media_type_internal_serdes) &&
1300             !e1000_sgmii_active_82575(hw))
1301                 return;
1302
1303         /* Enable PCS to turn on link */
1304         reg = E1000_READ_REG(hw, E1000_PCS_CFG0);
1305         reg |= E1000_PCS_CFG_PCS_EN;
1306         E1000_WRITE_REG(hw, E1000_PCS_CFG0, reg);
1307
1308         /* Power up the laser */
1309         reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
1310         reg &= ~E1000_CTRL_EXT_SDP3_DATA;
1311         E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg);
1312
1313         /* flush the write to verify completion */
1314         E1000_WRITE_FLUSH(hw);
1315         msec_delay(1);
1316 }
1317
1318 /**
1319  *  e1000_get_pcs_speed_and_duplex_82575 - Retrieve current speed/duplex
1320  *  @hw: pointer to the HW structure
1321  *  @speed: stores the current speed
1322  *  @duplex: stores the current duplex
1323  *
1324  *  Using the physical coding sub-layer (PCS), retrieve the current speed and
1325  *  duplex, then store the values in the pointers provided.
1326  **/
1327 STATIC s32 e1000_get_pcs_speed_and_duplex_82575(struct e1000_hw *hw,
1328                                                 u16 *speed, u16 *duplex)
1329 {
1330         struct e1000_mac_info *mac = &hw->mac;
1331         u32 pcs;
1332         u32 status;
1333
1334         DEBUGFUNC("e1000_get_pcs_speed_and_duplex_82575");
1335
1336         /*
1337          * Read the PCS Status register for link state. For non-copper mode,
1338          * the status register is not accurate. The PCS status register is
1339          * used instead.
1340          */
1341         pcs = E1000_READ_REG(hw, E1000_PCS_LSTAT);
1342
1343         /*
1344          * The link up bit determines when link is up on autoneg.
1345          */
1346         if (pcs & E1000_PCS_LSTS_LINK_OK) {
1347                 mac->serdes_has_link = true;
1348
1349                 /* Detect and store PCS speed */
1350                 if (pcs & E1000_PCS_LSTS_SPEED_1000)
1351                         *speed = SPEED_1000;
1352                 else if (pcs & E1000_PCS_LSTS_SPEED_100)
1353                         *speed = SPEED_100;
1354                 else
1355                         *speed = SPEED_10;
1356
1357                 /* Detect and store PCS duplex */
1358                 if (pcs & E1000_PCS_LSTS_DUPLEX_FULL)
1359                         *duplex = FULL_DUPLEX;
1360                 else
1361                         *duplex = HALF_DUPLEX;
1362
1363                 /* Check if it is an I354 2.5Gb backplane connection. */
1364                 if (mac->type == e1000_i354) {
1365                         status = E1000_READ_REG(hw, E1000_STATUS);
1366                         if ((status & E1000_STATUS_2P5_SKU) &&
1367                             !(status & E1000_STATUS_2P5_SKU_OVER)) {
1368                                 *speed = SPEED_2500;
1369                                 *duplex = FULL_DUPLEX;
1370                                 DEBUGOUT("2500 Mbs, ");
1371                                 DEBUGOUT("Full Duplex\n");
1372                         }
1373                 }
1374
1375         } else {
1376                 mac->serdes_has_link = false;
1377                 *speed = 0;
1378                 *duplex = 0;
1379         }
1380
1381         return E1000_SUCCESS;
1382 }
1383
1384 /**
1385  *  e1000_shutdown_serdes_link_82575 - Remove link during power down
1386  *  @hw: pointer to the HW structure
1387  *
1388  *  In the case of serdes shut down sfp and PCS on driver unload
1389  *  when management pass thru is not enabled.
1390  **/
1391 void e1000_shutdown_serdes_link_82575(struct e1000_hw *hw)
1392 {
1393         u32 reg;
1394
1395         DEBUGFUNC("e1000_shutdown_serdes_link_82575");
1396
1397         if ((hw->phy.media_type != e1000_media_type_internal_serdes) &&
1398             !e1000_sgmii_active_82575(hw))
1399                 return;
1400
1401         if (!e1000_enable_mng_pass_thru(hw)) {
1402                 /* Disable PCS to turn off link */
1403                 reg = E1000_READ_REG(hw, E1000_PCS_CFG0);
1404                 reg &= ~E1000_PCS_CFG_PCS_EN;
1405                 E1000_WRITE_REG(hw, E1000_PCS_CFG0, reg);
1406
1407                 /* shutdown the laser */
1408                 reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
1409                 reg |= E1000_CTRL_EXT_SDP3_DATA;
1410                 E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg);
1411
1412                 /* flush the write to verify completion */
1413                 E1000_WRITE_FLUSH(hw);
1414                 msec_delay(1);
1415         }
1416
1417         return;
1418 }
1419
1420 /**
1421  *  e1000_reset_hw_82575 - Reset hardware
1422  *  @hw: pointer to the HW structure
1423  *
1424  *  This resets the hardware into a known state.
1425  **/
1426 STATIC s32 e1000_reset_hw_82575(struct e1000_hw *hw)
1427 {
1428         u32 ctrl;
1429         s32 ret_val;
1430
1431         DEBUGFUNC("e1000_reset_hw_82575");
1432
1433         /*
1434          * Prevent the PCI-E bus from sticking if there is no TLP connection
1435          * on the last TLP read/write transaction when MAC is reset.
1436          */
1437         ret_val = e1000_disable_pcie_master_generic(hw);
1438         if (ret_val)
1439                 DEBUGOUT("PCI-E Master disable polling has failed.\n");
1440
1441         /* set the completion timeout for interface */
1442         ret_val = e1000_set_pcie_completion_timeout(hw);
1443         if (ret_val)
1444                 DEBUGOUT("PCI-E Set completion timeout has failed.\n");
1445
1446         DEBUGOUT("Masking off all interrupts\n");
1447         E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff);
1448
1449         E1000_WRITE_REG(hw, E1000_RCTL, 0);
1450         E1000_WRITE_REG(hw, E1000_TCTL, E1000_TCTL_PSP);
1451         E1000_WRITE_FLUSH(hw);
1452
1453         msec_delay(10);
1454
1455         ctrl = E1000_READ_REG(hw, E1000_CTRL);
1456
1457         DEBUGOUT("Issuing a global reset to MAC\n");
1458         E1000_WRITE_REG(hw, E1000_CTRL, ctrl | E1000_CTRL_RST);
1459
1460         ret_val = e1000_get_auto_rd_done_generic(hw);
1461         if (ret_val) {
1462                 /*
1463                  * When auto config read does not complete, do not
1464                  * return with an error. This can happen in situations
1465                  * where there is no eeprom and prevents getting link.
1466                  */
1467                 DEBUGOUT("Auto Read Done did not complete\n");
1468         }
1469
1470         /* If EEPROM is not present, run manual init scripts */
1471         if (!(E1000_READ_REG(hw, E1000_EECD) & E1000_EECD_PRES))
1472                 e1000_reset_init_script_82575(hw);
1473
1474         /* Clear any pending interrupt events. */
1475         E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff);
1476         E1000_READ_REG(hw, E1000_ICR);
1477
1478         /* Install any alternate MAC address into RAR0 */
1479         ret_val = e1000_check_alt_mac_addr_generic(hw);
1480
1481         return ret_val;
1482 }
1483
1484 /**
1485  *  e1000_init_hw_82575 - Initialize hardware
1486  *  @hw: pointer to the HW structure
1487  *
1488  *  This inits the hardware readying it for operation.
1489  **/
1490 s32 e1000_init_hw_82575(struct e1000_hw *hw)
1491 {
1492         struct e1000_mac_info *mac = &hw->mac;
1493         s32 ret_val;
1494         u16 i, rar_count = mac->rar_entry_count;
1495
1496         DEBUGFUNC("e1000_init_hw_82575");
1497
1498         /* Initialize identification LED */
1499         ret_val = mac->ops.id_led_init(hw);
1500         if (ret_val) {
1501                 DEBUGOUT("Error initializing identification LED\n");
1502                 /* This is not fatal and we should not stop init due to this */
1503         }
1504
1505         /* Disabling VLAN filtering */
1506         DEBUGOUT("Initializing the IEEE VLAN\n");
1507         mac->ops.clear_vfta(hw);
1508
1509         /* Setup the receive address */
1510         e1000_init_rx_addrs_generic(hw, rar_count);
1511
1512         /* Zero out the Multicast HASH table */
1513         DEBUGOUT("Zeroing the MTA\n");
1514         for (i = 0; i < mac->mta_reg_count; i++)
1515                 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0);
1516
1517         /* Zero out the Unicast HASH table */
1518         DEBUGOUT("Zeroing the UTA\n");
1519         for (i = 0; i < mac->uta_reg_count; i++)
1520                 E1000_WRITE_REG_ARRAY(hw, E1000_UTA, i, 0);
1521
1522         /* Setup link and flow control */
1523         ret_val = mac->ops.setup_link(hw);
1524
1525         /* Set the default MTU size */
1526         hw->dev_spec._82575.mtu = 1500;
1527
1528         /*
1529          * Clear all of the statistics registers (clear on read).  It is
1530          * important that we do this after we have tried to establish link
1531          * because the symbol error count will increment wildly if there
1532          * is no link.
1533          */
1534         e1000_clear_hw_cntrs_82575(hw);
1535
1536         return ret_val;
1537 }
1538
1539 /**
1540  *  e1000_setup_copper_link_82575 - Configure copper link settings
1541  *  @hw: pointer to the HW structure
1542  *
1543  *  Configures the link for auto-neg or forced speed and duplex.  Then we check
1544  *  for link, once link is established calls to configure collision distance
1545  *  and flow control are called.
1546  **/
1547 STATIC s32 e1000_setup_copper_link_82575(struct e1000_hw *hw)
1548 {
1549         u32 ctrl;
1550         s32 ret_val;
1551         u32 phpm_reg;
1552
1553         DEBUGFUNC("e1000_setup_copper_link_82575");
1554
1555         ctrl = E1000_READ_REG(hw, E1000_CTRL);
1556         ctrl |= E1000_CTRL_SLU;
1557         ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
1558         E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
1559
1560         /* Clear Go Link Disconnect bit on supported devices */
1561         switch (hw->mac.type) {
1562         case e1000_82580:
1563         case e1000_i350:
1564         case e1000_i210:
1565         case e1000_i211:
1566                 phpm_reg = E1000_READ_REG(hw, E1000_82580_PHY_POWER_MGMT);
1567                 phpm_reg &= ~E1000_82580_PM_GO_LINKD;
1568                 E1000_WRITE_REG(hw, E1000_82580_PHY_POWER_MGMT, phpm_reg);
1569                 break;
1570         default:
1571                 break;
1572         }
1573
1574         ret_val = e1000_setup_serdes_link_82575(hw);
1575         if (ret_val)
1576                 goto out;
1577
1578         if (e1000_sgmii_active_82575(hw)) {
1579                 /* allow time for SFP cage time to power up phy */
1580                 msec_delay(300);
1581
1582                 ret_val = hw->phy.ops.reset(hw);
1583                 if (ret_val) {
1584                         DEBUGOUT("Error resetting the PHY.\n");
1585                         goto out;
1586                 }
1587         }
1588         switch (hw->phy.type) {
1589         case e1000_phy_i210:
1590         case e1000_phy_m88:
1591                 switch (hw->phy.id) {
1592                 case I347AT4_E_PHY_ID:
1593                 case M88E1112_E_PHY_ID:
1594                 case M88E1340M_E_PHY_ID:
1595                 case M88E1543_E_PHY_ID:
1596                 case M88E1512_E_PHY_ID:
1597                 case I210_I_PHY_ID:
1598                         ret_val = e1000_copper_link_setup_m88_gen2(hw);
1599                         break;
1600                 default:
1601                         ret_val = e1000_copper_link_setup_m88(hw);
1602                         break;
1603                 }
1604                 break;
1605         case e1000_phy_igp_3:
1606                 ret_val = e1000_copper_link_setup_igp(hw);
1607                 break;
1608         case e1000_phy_82580:
1609                 ret_val = e1000_copper_link_setup_82577(hw);
1610                 break;
1611         default:
1612                 ret_val = -E1000_ERR_PHY;
1613                 break;
1614         }
1615
1616         if (ret_val)
1617                 goto out;
1618
1619         ret_val = e1000_setup_copper_link_generic(hw);
1620 out:
1621         return ret_val;
1622 }
1623
1624 /**
1625  *  e1000_setup_serdes_link_82575 - Setup link for serdes
1626  *  @hw: pointer to the HW structure
1627  *
1628  *  Configure the physical coding sub-layer (PCS) link.  The PCS link is
1629  *  used on copper connections where the serialized gigabit media independent
1630  *  interface (sgmii), or serdes fiber is being used.  Configures the link
1631  *  for auto-negotiation or forces speed/duplex.
1632  **/
1633 STATIC s32 e1000_setup_serdes_link_82575(struct e1000_hw *hw)
1634 {
1635         u32 ctrl_ext, ctrl_reg, reg, anadv_reg;
1636         bool pcs_autoneg;
1637         s32 ret_val = E1000_SUCCESS;
1638         u16 data;
1639
1640         DEBUGFUNC("e1000_setup_serdes_link_82575");
1641
1642         if ((hw->phy.media_type != e1000_media_type_internal_serdes) &&
1643             !e1000_sgmii_active_82575(hw))
1644                 return ret_val;
1645
1646         /*
1647          * On the 82575, SerDes loopback mode persists until it is
1648          * explicitly turned off or a power cycle is performed.  A read to
1649          * the register does not indicate its status.  Therefore, we ensure
1650          * loopback mode is disabled during initialization.
1651          */
1652         E1000_WRITE_REG(hw, E1000_SCTL, E1000_SCTL_DISABLE_SERDES_LOOPBACK);
1653
1654         /* power on the sfp cage if present */
1655         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
1656         ctrl_ext &= ~E1000_CTRL_EXT_SDP3_DATA;
1657         E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
1658
1659         ctrl_reg = E1000_READ_REG(hw, E1000_CTRL);
1660         ctrl_reg |= E1000_CTRL_SLU;
1661
1662         /* set both sw defined pins on 82575/82576*/
1663         if (hw->mac.type == e1000_82575 || hw->mac.type == e1000_82576)
1664                 ctrl_reg |= E1000_CTRL_SWDPIN0 | E1000_CTRL_SWDPIN1;
1665
1666         reg = E1000_READ_REG(hw, E1000_PCS_LCTL);
1667
1668         /* default pcs_autoneg to the same setting as mac autoneg */
1669         pcs_autoneg = hw->mac.autoneg;
1670
1671         switch (ctrl_ext & E1000_CTRL_EXT_LINK_MODE_MASK) {
1672         case E1000_CTRL_EXT_LINK_MODE_SGMII:
1673                 /* sgmii mode lets the phy handle forcing speed/duplex */
1674                 pcs_autoneg = true;
1675                 /* autoneg time out should be disabled for SGMII mode */
1676                 reg &= ~(E1000_PCS_LCTL_AN_TIMEOUT);
1677                 break;
1678         case E1000_CTRL_EXT_LINK_MODE_1000BASE_KX:
1679                 /* disable PCS autoneg and support parallel detect only */
1680                 pcs_autoneg = false;
1681                 /* fall through to default case */
1682         default:
1683                 if (hw->mac.type == e1000_82575 ||
1684                     hw->mac.type == e1000_82576) {
1685                         ret_val = hw->nvm.ops.read(hw, NVM_COMPAT, 1, &data);
1686                         if (ret_val) {
1687                                 DEBUGOUT("NVM Read Error\n");
1688                                 return ret_val;
1689                         }
1690
1691                         if (data & E1000_EEPROM_PCS_AUTONEG_DISABLE_BIT)
1692                                 pcs_autoneg = false;
1693                 }
1694
1695                 /*
1696                  * non-SGMII modes only supports a speed of 1000/Full for the
1697                  * link so it is best to just force the MAC and let the pcs
1698                  * link either autoneg or be forced to 1000/Full
1699                  */
1700                 ctrl_reg |= E1000_CTRL_SPD_1000 | E1000_CTRL_FRCSPD |
1701                             E1000_CTRL_FD | E1000_CTRL_FRCDPX;
1702
1703                 /* set speed of 1000/Full if speed/duplex is forced */
1704                 reg |= E1000_PCS_LCTL_FSV_1000 | E1000_PCS_LCTL_FDV_FULL;
1705                 break;
1706         }
1707
1708         E1000_WRITE_REG(hw, E1000_CTRL, ctrl_reg);
1709
1710         /*
1711          * New SerDes mode allows for forcing speed or autonegotiating speed
1712          * at 1gb. Autoneg should be default set by most drivers. This is the
1713          * mode that will be compatible with older link partners and switches.
1714          * However, both are supported by the hardware and some drivers/tools.
1715          */
1716         reg &= ~(E1000_PCS_LCTL_AN_ENABLE | E1000_PCS_LCTL_FLV_LINK_UP |
1717                  E1000_PCS_LCTL_FSD | E1000_PCS_LCTL_FORCE_LINK);
1718
1719         if (pcs_autoneg) {
1720                 /* Set PCS register for autoneg */
1721                 reg |= E1000_PCS_LCTL_AN_ENABLE | /* Enable Autoneg */
1722                        E1000_PCS_LCTL_AN_RESTART; /* Restart autoneg */
1723
1724                 /* Disable force flow control for autoneg */
1725                 reg &= ~E1000_PCS_LCTL_FORCE_FCTRL;
1726
1727                 /* Configure flow control advertisement for autoneg */
1728                 anadv_reg = E1000_READ_REG(hw, E1000_PCS_ANADV);
1729                 anadv_reg &= ~(E1000_TXCW_ASM_DIR | E1000_TXCW_PAUSE);
1730
1731                 switch (hw->fc.requested_mode) {
1732                 case e1000_fc_full:
1733                 case e1000_fc_rx_pause:
1734                         anadv_reg |= E1000_TXCW_ASM_DIR;
1735                         anadv_reg |= E1000_TXCW_PAUSE;
1736                         break;
1737                 case e1000_fc_tx_pause:
1738                         anadv_reg |= E1000_TXCW_ASM_DIR;
1739                         break;
1740                 default:
1741                         break;
1742                 }
1743
1744                 E1000_WRITE_REG(hw, E1000_PCS_ANADV, anadv_reg);
1745
1746                 DEBUGOUT1("Configuring Autoneg:PCS_LCTL=0x%08X\n", reg);
1747         } else {
1748                 /* Set PCS register for forced link */
1749                 reg |= E1000_PCS_LCTL_FSD;      /* Force Speed */
1750
1751                 /* Force flow control for forced link */
1752                 reg |= E1000_PCS_LCTL_FORCE_FCTRL;
1753
1754                 DEBUGOUT1("Configuring Forced Link:PCS_LCTL=0x%08X\n", reg);
1755         }
1756
1757         E1000_WRITE_REG(hw, E1000_PCS_LCTL, reg);
1758
1759         if (!pcs_autoneg && !e1000_sgmii_active_82575(hw))
1760                 e1000_force_mac_fc_generic(hw);
1761
1762         return ret_val;
1763 }
1764
1765 /**
1766  *  e1000_get_media_type_82575 - derives current media type.
1767  *  @hw: pointer to the HW structure
1768  *
1769  *  The media type is chosen reflecting few settings.
1770  *  The following are taken into account:
1771  *  - link mode set in the current port Init Control Word #3
1772  *  - current link mode settings in CSR register
1773  *  - MDIO vs. I2C PHY control interface chosen
1774  *  - SFP module media type
1775  **/
1776 STATIC s32 e1000_get_media_type_82575(struct e1000_hw *hw)
1777 {
1778         struct e1000_dev_spec_82575 *dev_spec = &hw->dev_spec._82575;
1779         s32 ret_val = E1000_SUCCESS;
1780         u32 ctrl_ext = 0;
1781         u32 link_mode = 0;
1782
1783         /* Set internal phy as default */
1784         dev_spec->sgmii_active = false;
1785         dev_spec->module_plugged = false;
1786
1787         /* Get CSR setting */
1788         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
1789
1790         /* extract link mode setting */
1791         link_mode = ctrl_ext & E1000_CTRL_EXT_LINK_MODE_MASK;
1792
1793         switch (link_mode) {
1794         case E1000_CTRL_EXT_LINK_MODE_1000BASE_KX:
1795                 hw->phy.media_type = e1000_media_type_internal_serdes;
1796                 break;
1797         case E1000_CTRL_EXT_LINK_MODE_GMII:
1798                 hw->phy.media_type = e1000_media_type_copper;
1799                 break;
1800         case E1000_CTRL_EXT_LINK_MODE_SGMII:
1801                 /* Get phy control interface type set (MDIO vs. I2C)*/
1802                 if (e1000_sgmii_uses_mdio_82575(hw)) {
1803                         hw->phy.media_type = e1000_media_type_copper;
1804                         dev_spec->sgmii_active = true;
1805                         break;
1806                 }
1807                 /* fall through for I2C based SGMII */
1808         case E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES:
1809                 /* read media type from SFP EEPROM */
1810                 ret_val = e1000_set_sfp_media_type_82575(hw);
1811                 if ((ret_val != E1000_SUCCESS) ||
1812                     (hw->phy.media_type == e1000_media_type_unknown)) {
1813                         /*
1814                          * If media type was not identified then return media
1815                          * type defined by the CTRL_EXT settings.
1816                          */
1817                         hw->phy.media_type = e1000_media_type_internal_serdes;
1818
1819                         if (link_mode == E1000_CTRL_EXT_LINK_MODE_SGMII) {
1820                                 hw->phy.media_type = e1000_media_type_copper;
1821                                 dev_spec->sgmii_active = true;
1822                         }
1823
1824                         break;
1825                 }
1826
1827                 /* do not change link mode for 100BaseFX */
1828                 if (dev_spec->eth_flags.e100_base_fx)
1829                         break;
1830
1831                 /* change current link mode setting */
1832                 ctrl_ext &= ~E1000_CTRL_EXT_LINK_MODE_MASK;
1833
1834                 if (hw->phy.media_type == e1000_media_type_copper)
1835                         ctrl_ext |= E1000_CTRL_EXT_LINK_MODE_SGMII;
1836                 else
1837                         ctrl_ext |= E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES;
1838
1839                 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
1840
1841                 break;
1842         }
1843
1844         return ret_val;
1845 }
1846
1847 /**
1848  *  e1000_set_sfp_media_type_82575 - derives SFP module media type.
1849  *  @hw: pointer to the HW structure
1850  *
1851  *  The media type is chosen based on SFP module.
1852  *  compatibility flags retrieved from SFP ID EEPROM.
1853  **/
1854 STATIC s32 e1000_set_sfp_media_type_82575(struct e1000_hw *hw)
1855 {
1856         s32 ret_val = E1000_ERR_CONFIG;
1857         u32 ctrl_ext = 0;
1858         struct e1000_dev_spec_82575 *dev_spec = &hw->dev_spec._82575;
1859         struct sfp_e1000_flags *eth_flags = &dev_spec->eth_flags;
1860         u8 tranceiver_type = 0;
1861         s32 timeout = 3;
1862
1863         /* Turn I2C interface ON and power on sfp cage */
1864         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
1865         ctrl_ext &= ~E1000_CTRL_EXT_SDP3_DATA;
1866         E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext | E1000_CTRL_I2C_ENA);
1867
1868         E1000_WRITE_FLUSH(hw);
1869
1870         /* Read SFP module data */
1871         while (timeout) {
1872                 ret_val = e1000_read_sfp_data_byte(hw,
1873                         E1000_I2CCMD_SFP_DATA_ADDR(E1000_SFF_IDENTIFIER_OFFSET),
1874                         &tranceiver_type);
1875                 if (ret_val == E1000_SUCCESS)
1876                         break;
1877                 msec_delay(100);
1878                 timeout--;
1879         }
1880         if (ret_val != E1000_SUCCESS)
1881                 goto out;
1882
1883         ret_val = e1000_read_sfp_data_byte(hw,
1884                         E1000_I2CCMD_SFP_DATA_ADDR(E1000_SFF_ETH_FLAGS_OFFSET),
1885                         (u8 *)eth_flags);
1886         if (ret_val != E1000_SUCCESS)
1887                 goto out;
1888
1889         /* Check if there is some SFP module plugged and powered */
1890         if ((tranceiver_type == E1000_SFF_IDENTIFIER_SFP) ||
1891             (tranceiver_type == E1000_SFF_IDENTIFIER_SFF)) {
1892                 dev_spec->module_plugged = true;
1893                 if (eth_flags->e1000_base_lx || eth_flags->e1000_base_sx) {
1894                         hw->phy.media_type = e1000_media_type_internal_serdes;
1895                 } else if (eth_flags->e100_base_fx) {
1896                         dev_spec->sgmii_active = true;
1897                         hw->phy.media_type = e1000_media_type_internal_serdes;
1898                 } else if (eth_flags->e1000_base_t) {
1899                         dev_spec->sgmii_active = true;
1900                         hw->phy.media_type = e1000_media_type_copper;
1901                 } else {
1902                         hw->phy.media_type = e1000_media_type_unknown;
1903                         DEBUGOUT("PHY module has not been recognized\n");
1904                         goto out;
1905                 }
1906         } else {
1907                 hw->phy.media_type = e1000_media_type_unknown;
1908         }
1909         ret_val = E1000_SUCCESS;
1910 out:
1911         /* Restore I2C interface setting */
1912         E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
1913         return ret_val;
1914 }
1915
1916 /**
1917  *  e1000_valid_led_default_82575 - Verify a valid default LED config
1918  *  @hw: pointer to the HW structure
1919  *  @data: pointer to the NVM (EEPROM)
1920  *
1921  *  Read the EEPROM for the current default LED configuration.  If the
1922  *  LED configuration is not valid, set to a valid LED configuration.
1923  **/
1924 STATIC s32 e1000_valid_led_default_82575(struct e1000_hw *hw, u16 *data)
1925 {
1926         s32 ret_val;
1927
1928         DEBUGFUNC("e1000_valid_led_default_82575");
1929
1930         ret_val = hw->nvm.ops.read(hw, NVM_ID_LED_SETTINGS, 1, data);
1931         if (ret_val) {
1932                 DEBUGOUT("NVM Read Error\n");
1933                 goto out;
1934         }
1935
1936         if (*data == ID_LED_RESERVED_0000 || *data == ID_LED_RESERVED_FFFF) {
1937                 switch (hw->phy.media_type) {
1938                 case e1000_media_type_internal_serdes:
1939                         *data = ID_LED_DEFAULT_82575_SERDES;
1940                         break;
1941                 case e1000_media_type_copper:
1942                 default:
1943                         *data = ID_LED_DEFAULT;
1944                         break;
1945                 }
1946         }
1947 out:
1948         return ret_val;
1949 }
1950
1951 /**
1952  *  e1000_sgmii_active_82575 - Return sgmii state
1953  *  @hw: pointer to the HW structure
1954  *
1955  *  82575 silicon has a serialized gigabit media independent interface (sgmii)
1956  *  which can be enabled for use in the embedded applications.  Simply
1957  *  return the current state of the sgmii interface.
1958  **/
1959 STATIC bool e1000_sgmii_active_82575(struct e1000_hw *hw)
1960 {
1961         struct e1000_dev_spec_82575 *dev_spec = &hw->dev_spec._82575;
1962         return dev_spec->sgmii_active;
1963 }
1964
1965 /**
1966  *  e1000_reset_init_script_82575 - Inits HW defaults after reset
1967  *  @hw: pointer to the HW structure
1968  *
1969  *  Inits recommended HW defaults after a reset when there is no EEPROM
1970  *  detected. This is only for the 82575.
1971  **/
1972 STATIC s32 e1000_reset_init_script_82575(struct e1000_hw *hw)
1973 {
1974         DEBUGFUNC("e1000_reset_init_script_82575");
1975
1976         if (hw->mac.type == e1000_82575) {
1977                 DEBUGOUT("Running reset init script for 82575\n");
1978                 /* SerDes configuration via SERDESCTRL */
1979                 e1000_write_8bit_ctrl_reg_generic(hw, E1000_SCTL, 0x00, 0x0C);
1980                 e1000_write_8bit_ctrl_reg_generic(hw, E1000_SCTL, 0x01, 0x78);
1981                 e1000_write_8bit_ctrl_reg_generic(hw, E1000_SCTL, 0x1B, 0x23);
1982                 e1000_write_8bit_ctrl_reg_generic(hw, E1000_SCTL, 0x23, 0x15);
1983
1984                 /* CCM configuration via CCMCTL register */
1985                 e1000_write_8bit_ctrl_reg_generic(hw, E1000_CCMCTL, 0x14, 0x00);
1986                 e1000_write_8bit_ctrl_reg_generic(hw, E1000_CCMCTL, 0x10, 0x00);
1987
1988                 /* PCIe lanes configuration */
1989                 e1000_write_8bit_ctrl_reg_generic(hw, E1000_GIOCTL, 0x00, 0xEC);
1990                 e1000_write_8bit_ctrl_reg_generic(hw, E1000_GIOCTL, 0x61, 0xDF);
1991                 e1000_write_8bit_ctrl_reg_generic(hw, E1000_GIOCTL, 0x34, 0x05);
1992                 e1000_write_8bit_ctrl_reg_generic(hw, E1000_GIOCTL, 0x2F, 0x81);
1993
1994                 /* PCIe PLL Configuration */
1995                 e1000_write_8bit_ctrl_reg_generic(hw, E1000_SCCTL, 0x02, 0x47);
1996                 e1000_write_8bit_ctrl_reg_generic(hw, E1000_SCCTL, 0x14, 0x00);
1997                 e1000_write_8bit_ctrl_reg_generic(hw, E1000_SCCTL, 0x10, 0x00);
1998         }
1999
2000         return E1000_SUCCESS;
2001 }
2002
2003 /**
2004  *  e1000_read_mac_addr_82575 - Read device MAC address
2005  *  @hw: pointer to the HW structure
2006  **/
2007 STATIC s32 e1000_read_mac_addr_82575(struct e1000_hw *hw)
2008 {
2009         s32 ret_val;
2010
2011         DEBUGFUNC("e1000_read_mac_addr_82575");
2012
2013         /*
2014          * If there's an alternate MAC address place it in RAR0
2015          * so that it will override the Si installed default perm
2016          * address.
2017          */
2018         ret_val = e1000_check_alt_mac_addr_generic(hw);
2019         if (ret_val)
2020                 goto out;
2021
2022         ret_val = e1000_read_mac_addr_generic(hw);
2023
2024 out:
2025         return ret_val;
2026 }
2027
2028 /**
2029  *  e1000_config_collision_dist_82575 - Configure collision distance
2030  *  @hw: pointer to the HW structure
2031  *
2032  *  Configures the collision distance to the default value and is used
2033  *  during link setup.
2034  **/
2035 STATIC void e1000_config_collision_dist_82575(struct e1000_hw *hw)
2036 {
2037         u32 tctl_ext;
2038
2039         DEBUGFUNC("e1000_config_collision_dist_82575");
2040
2041         tctl_ext = E1000_READ_REG(hw, E1000_TCTL_EXT);
2042
2043         tctl_ext &= ~E1000_TCTL_EXT_COLD;
2044         tctl_ext |= E1000_COLLISION_DISTANCE << E1000_TCTL_EXT_COLD_SHIFT;
2045
2046         E1000_WRITE_REG(hw, E1000_TCTL_EXT, tctl_ext);
2047         E1000_WRITE_FLUSH(hw);
2048 }
2049
2050 /**
2051  * e1000_power_down_phy_copper_82575 - Remove link during PHY power down
2052  * @hw: pointer to the HW structure
2053  *
2054  * In the case of a PHY power down to save power, or to turn off link during a
2055  * driver unload, or wake on lan is not enabled, remove the link.
2056  **/
2057 STATIC void e1000_power_down_phy_copper_82575(struct e1000_hw *hw)
2058 {
2059         struct e1000_phy_info *phy = &hw->phy;
2060
2061         if (!(phy->ops.check_reset_block))
2062                 return;
2063
2064         /* If the management interface is not enabled, then power down */
2065         if (!(e1000_enable_mng_pass_thru(hw) || phy->ops.check_reset_block(hw)))
2066                 e1000_power_down_phy_copper(hw);
2067
2068         return;
2069 }
2070
2071 /**
2072  *  e1000_clear_hw_cntrs_82575 - Clear device specific hardware counters
2073  *  @hw: pointer to the HW structure
2074  *
2075  *  Clears the hardware counters by reading the counter registers.
2076  **/
2077 STATIC void e1000_clear_hw_cntrs_82575(struct e1000_hw *hw)
2078 {
2079         DEBUGFUNC("e1000_clear_hw_cntrs_82575");
2080
2081         e1000_clear_hw_cntrs_base_generic(hw);
2082
2083         E1000_READ_REG(hw, E1000_PRC64);
2084         E1000_READ_REG(hw, E1000_PRC127);
2085         E1000_READ_REG(hw, E1000_PRC255);
2086         E1000_READ_REG(hw, E1000_PRC511);
2087         E1000_READ_REG(hw, E1000_PRC1023);
2088         E1000_READ_REG(hw, E1000_PRC1522);
2089         E1000_READ_REG(hw, E1000_PTC64);
2090         E1000_READ_REG(hw, E1000_PTC127);
2091         E1000_READ_REG(hw, E1000_PTC255);
2092         E1000_READ_REG(hw, E1000_PTC511);
2093         E1000_READ_REG(hw, E1000_PTC1023);
2094         E1000_READ_REG(hw, E1000_PTC1522);
2095
2096         E1000_READ_REG(hw, E1000_ALGNERRC);
2097         E1000_READ_REG(hw, E1000_RXERRC);
2098         E1000_READ_REG(hw, E1000_TNCRS);
2099         E1000_READ_REG(hw, E1000_CEXTERR);
2100         E1000_READ_REG(hw, E1000_TSCTC);
2101         E1000_READ_REG(hw, E1000_TSCTFC);
2102
2103         E1000_READ_REG(hw, E1000_MGTPRC);
2104         E1000_READ_REG(hw, E1000_MGTPDC);
2105         E1000_READ_REG(hw, E1000_MGTPTC);
2106
2107         E1000_READ_REG(hw, E1000_IAC);
2108         E1000_READ_REG(hw, E1000_ICRXOC);
2109
2110         E1000_READ_REG(hw, E1000_ICRXPTC);
2111         E1000_READ_REG(hw, E1000_ICRXATC);
2112         E1000_READ_REG(hw, E1000_ICTXPTC);
2113         E1000_READ_REG(hw, E1000_ICTXATC);
2114         E1000_READ_REG(hw, E1000_ICTXQEC);
2115         E1000_READ_REG(hw, E1000_ICTXQMTC);
2116         E1000_READ_REG(hw, E1000_ICRXDMTC);
2117
2118         E1000_READ_REG(hw, E1000_CBTMPC);
2119         E1000_READ_REG(hw, E1000_HTDPMC);
2120         E1000_READ_REG(hw, E1000_CBRMPC);
2121         E1000_READ_REG(hw, E1000_RPTHC);
2122         E1000_READ_REG(hw, E1000_HGPTC);
2123         E1000_READ_REG(hw, E1000_HTCBDPC);
2124         E1000_READ_REG(hw, E1000_HGORCL);
2125         E1000_READ_REG(hw, E1000_HGORCH);
2126         E1000_READ_REG(hw, E1000_HGOTCL);
2127         E1000_READ_REG(hw, E1000_HGOTCH);
2128         E1000_READ_REG(hw, E1000_LENERRS);
2129
2130         /* This register should not be read in copper configurations */
2131         if ((hw->phy.media_type == e1000_media_type_internal_serdes) ||
2132             e1000_sgmii_active_82575(hw))
2133                 E1000_READ_REG(hw, E1000_SCVPC);
2134 }
2135
2136 /**
2137  *  e1000_rx_fifo_flush_82575 - Clean rx fifo after Rx enable
2138  *  @hw: pointer to the HW structure
2139  *
2140  *  After Rx enable, if manageability is enabled then there is likely some
2141  *  bad data at the start of the fifo and possibly in the DMA fifo.  This
2142  *  function clears the fifos and flushes any packets that came in as rx was
2143  *  being enabled.
2144  **/
2145 void e1000_rx_fifo_flush_82575(struct e1000_hw *hw)
2146 {
2147         u32 rctl, rlpml, rxdctl[4], rfctl, temp_rctl, rx_enabled;
2148         int i, ms_wait;
2149
2150         DEBUGFUNC("e1000_rx_fifo_flush_82575");
2151
2152         /* disable IPv6 options as per hardware errata */
2153         rfctl = E1000_READ_REG(hw, E1000_RFCTL);
2154         rfctl |= E1000_RFCTL_IPV6_EX_DIS;
2155         E1000_WRITE_REG(hw, E1000_RFCTL, rfctl);
2156
2157         if (hw->mac.type != e1000_82575 ||
2158             !(E1000_READ_REG(hw, E1000_MANC) & E1000_MANC_RCV_TCO_EN))
2159                 return;
2160
2161         /* Disable all Rx queues */
2162         for (i = 0; i < 4; i++) {
2163                 rxdctl[i] = E1000_READ_REG(hw, E1000_RXDCTL(i));
2164                 E1000_WRITE_REG(hw, E1000_RXDCTL(i),
2165                                 rxdctl[i] & ~E1000_RXDCTL_QUEUE_ENABLE);
2166         }
2167         /* Poll all queues to verify they have shut down */
2168         for (ms_wait = 0; ms_wait < 10; ms_wait++) {
2169                 msec_delay(1);
2170                 rx_enabled = 0;
2171                 for (i = 0; i < 4; i++)
2172                         rx_enabled |= E1000_READ_REG(hw, E1000_RXDCTL(i));
2173                 if (!(rx_enabled & E1000_RXDCTL_QUEUE_ENABLE))
2174                         break;
2175         }
2176
2177         if (ms_wait == 10)
2178                 DEBUGOUT("Queue disable timed out after 10ms\n");
2179
2180         /* Clear RLPML, RCTL.SBP, RFCTL.LEF, and set RCTL.LPE so that all
2181          * incoming packets are rejected.  Set enable and wait 2ms so that
2182          * any packet that was coming in as RCTL.EN was set is flushed
2183          */
2184         E1000_WRITE_REG(hw, E1000_RFCTL, rfctl & ~E1000_RFCTL_LEF);
2185
2186         rlpml = E1000_READ_REG(hw, E1000_RLPML);
2187         E1000_WRITE_REG(hw, E1000_RLPML, 0);
2188
2189         rctl = E1000_READ_REG(hw, E1000_RCTL);
2190         temp_rctl = rctl & ~(E1000_RCTL_EN | E1000_RCTL_SBP);
2191         temp_rctl |= E1000_RCTL_LPE;
2192
2193         E1000_WRITE_REG(hw, E1000_RCTL, temp_rctl);
2194         E1000_WRITE_REG(hw, E1000_RCTL, temp_rctl | E1000_RCTL_EN);
2195         E1000_WRITE_FLUSH(hw);
2196         msec_delay(2);
2197
2198         /* Enable Rx queues that were previously enabled and restore our
2199          * previous state
2200          */
2201         for (i = 0; i < 4; i++)
2202                 E1000_WRITE_REG(hw, E1000_RXDCTL(i), rxdctl[i]);
2203         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2204         E1000_WRITE_FLUSH(hw);
2205
2206         E1000_WRITE_REG(hw, E1000_RLPML, rlpml);
2207         E1000_WRITE_REG(hw, E1000_RFCTL, rfctl);
2208
2209         /* Flush receive errors generated by workaround */
2210         E1000_READ_REG(hw, E1000_ROC);
2211         E1000_READ_REG(hw, E1000_RNBC);
2212         E1000_READ_REG(hw, E1000_MPC);
2213 }
2214
2215 /**
2216  *  e1000_set_pcie_completion_timeout - set pci-e completion timeout
2217  *  @hw: pointer to the HW structure
2218  *
2219  *  The defaults for 82575 and 82576 should be in the range of 50us to 50ms,
2220  *  however the hardware default for these parts is 500us to 1ms which is less
2221  *  than the 10ms recommended by the pci-e spec.  To address this we need to
2222  *  increase the value to either 10ms to 200ms for capability version 1 config,
2223  *  or 16ms to 55ms for version 2.
2224  **/
2225 STATIC s32 e1000_set_pcie_completion_timeout(struct e1000_hw *hw)
2226 {
2227         u32 gcr = E1000_READ_REG(hw, E1000_GCR);
2228         s32 ret_val = E1000_SUCCESS;
2229         u16 pcie_devctl2;
2230
2231         /* only take action if timeout value is defaulted to 0 */
2232         if (gcr & E1000_GCR_CMPL_TMOUT_MASK)
2233                 goto out;
2234
2235         /*
2236          * if capababilities version is type 1 we can write the
2237          * timeout of 10ms to 200ms through the GCR register
2238          */
2239         if (!(gcr & E1000_GCR_CAP_VER2)) {
2240                 gcr |= E1000_GCR_CMPL_TMOUT_10ms;
2241                 goto out;
2242         }
2243
2244         /*
2245          * for version 2 capabilities we need to write the config space
2246          * directly in order to set the completion timeout value for
2247          * 16ms to 55ms
2248          */
2249         ret_val = e1000_read_pcie_cap_reg(hw, PCIE_DEVICE_CONTROL2,
2250                                           &pcie_devctl2);
2251         if (ret_val)
2252                 goto out;
2253
2254         pcie_devctl2 |= PCIE_DEVICE_CONTROL2_16ms;
2255
2256         ret_val = e1000_write_pcie_cap_reg(hw, PCIE_DEVICE_CONTROL2,
2257                                            &pcie_devctl2);
2258 out:
2259         /* disable completion timeout resend */
2260         gcr &= ~E1000_GCR_CMPL_TMOUT_RESEND;
2261
2262         E1000_WRITE_REG(hw, E1000_GCR, gcr);
2263         return ret_val;
2264 }
2265
2266 /**
2267  *  e1000_vmdq_set_anti_spoofing_pf - enable or disable anti-spoofing
2268  *  @hw: pointer to the hardware struct
2269  *  @enable: state to enter, either enabled or disabled
2270  *  @pf: Physical Function pool - do not set anti-spoofing for the PF
2271  *
2272  *  enables/disables L2 switch anti-spoofing functionality.
2273  **/
2274 void e1000_vmdq_set_anti_spoofing_pf(struct e1000_hw *hw, bool enable, int pf)
2275 {
2276         u32 reg_val, reg_offset;
2277
2278         switch (hw->mac.type) {
2279         case e1000_82576:
2280                 reg_offset = E1000_DTXSWC;
2281                 break;
2282         case e1000_i350:
2283         case e1000_i354:
2284                 reg_offset = E1000_TXSWC;
2285                 break;
2286         default:
2287                 return;
2288         }
2289
2290         reg_val = E1000_READ_REG(hw, reg_offset);
2291         if (enable) {
2292                 reg_val |= (E1000_DTXSWC_MAC_SPOOF_MASK |
2293                              E1000_DTXSWC_VLAN_SPOOF_MASK);
2294                 /* The PF can spoof - it has to in order to
2295                  * support emulation mode NICs
2296                  */
2297                 reg_val ^= (1 << pf | 1 << (pf + MAX_NUM_VFS));
2298         } else {
2299                 reg_val &= ~(E1000_DTXSWC_MAC_SPOOF_MASK |
2300                              E1000_DTXSWC_VLAN_SPOOF_MASK);
2301         }
2302         E1000_WRITE_REG(hw, reg_offset, reg_val);
2303 }
2304
2305 /**
2306  *  e1000_vmdq_set_loopback_pf - enable or disable vmdq loopback
2307  *  @hw: pointer to the hardware struct
2308  *  @enable: state to enter, either enabled or disabled
2309  *
2310  *  enables/disables L2 switch loopback functionality.
2311  **/
2312 void e1000_vmdq_set_loopback_pf(struct e1000_hw *hw, bool enable)
2313 {
2314         u32 dtxswc;
2315
2316         switch (hw->mac.type) {
2317         case e1000_82576:
2318                 dtxswc = E1000_READ_REG(hw, E1000_DTXSWC);
2319                 if (enable)
2320                         dtxswc |= E1000_DTXSWC_VMDQ_LOOPBACK_EN;
2321                 else
2322                         dtxswc &= ~E1000_DTXSWC_VMDQ_LOOPBACK_EN;
2323                 E1000_WRITE_REG(hw, E1000_DTXSWC, dtxswc);
2324                 break;
2325         case e1000_i350:
2326         case e1000_i354:
2327                 dtxswc = E1000_READ_REG(hw, E1000_TXSWC);
2328                 if (enable)
2329                         dtxswc |= E1000_DTXSWC_VMDQ_LOOPBACK_EN;
2330                 else
2331                         dtxswc &= ~E1000_DTXSWC_VMDQ_LOOPBACK_EN;
2332                 E1000_WRITE_REG(hw, E1000_TXSWC, dtxswc);
2333                 break;
2334         default:
2335                 /* Currently no other hardware supports loopback */
2336                 break;
2337         }
2338
2339
2340 }
2341
2342 /**
2343  *  e1000_vmdq_set_replication_pf - enable or disable vmdq replication
2344  *  @hw: pointer to the hardware struct
2345  *  @enable: state to enter, either enabled or disabled
2346  *
2347  *  enables/disables replication of packets across multiple pools.
2348  **/
2349 void e1000_vmdq_set_replication_pf(struct e1000_hw *hw, bool enable)
2350 {
2351         u32 vt_ctl = E1000_READ_REG(hw, E1000_VT_CTL);
2352
2353         if (enable)
2354                 vt_ctl |= E1000_VT_CTL_VM_REPL_EN;
2355         else
2356                 vt_ctl &= ~E1000_VT_CTL_VM_REPL_EN;
2357
2358         E1000_WRITE_REG(hw, E1000_VT_CTL, vt_ctl);
2359 }
2360
2361 /**
2362  *  e1000_read_phy_reg_82580 - Read 82580 MDI control register
2363  *  @hw: pointer to the HW structure
2364  *  @offset: register offset to be read
2365  *  @data: pointer to the read data
2366  *
2367  *  Reads the MDI control register in the PHY at offset and stores the
2368  *  information read to data.
2369  **/
2370 STATIC s32 e1000_read_phy_reg_82580(struct e1000_hw *hw, u32 offset, u16 *data)
2371 {
2372         s32 ret_val;
2373
2374         DEBUGFUNC("e1000_read_phy_reg_82580");
2375
2376         ret_val = hw->phy.ops.acquire(hw);
2377         if (ret_val)
2378                 goto out;
2379
2380         ret_val = e1000_read_phy_reg_mdic(hw, offset, data);
2381
2382         hw->phy.ops.release(hw);
2383
2384 out:
2385         return ret_val;
2386 }
2387
2388 /**
2389  *  e1000_write_phy_reg_82580 - Write 82580 MDI control register
2390  *  @hw: pointer to the HW structure
2391  *  @offset: register offset to write to
2392  *  @data: data to write to register at offset
2393  *
2394  *  Writes data to MDI control register in the PHY at offset.
2395  **/
2396 STATIC s32 e1000_write_phy_reg_82580(struct e1000_hw *hw, u32 offset, u16 data)
2397 {
2398         s32 ret_val;
2399
2400         DEBUGFUNC("e1000_write_phy_reg_82580");
2401
2402         ret_val = hw->phy.ops.acquire(hw);
2403         if (ret_val)
2404                 goto out;
2405
2406         ret_val = e1000_write_phy_reg_mdic(hw, offset, data);
2407
2408         hw->phy.ops.release(hw);
2409
2410 out:
2411         return ret_val;
2412 }
2413
2414 /**
2415  *  e1000_reset_mdicnfg_82580 - Reset MDICNFG destination and com_mdio bits
2416  *  @hw: pointer to the HW structure
2417  *
2418  *  This resets the the MDICNFG.Destination and MDICNFG.Com_MDIO bits based on
2419  *  the values found in the EEPROM.  This addresses an issue in which these
2420  *  bits are not restored from EEPROM after reset.
2421  **/
2422 STATIC s32 e1000_reset_mdicnfg_82580(struct e1000_hw *hw)
2423 {
2424         s32 ret_val = E1000_SUCCESS;
2425         u32 mdicnfg;
2426         u16 nvm_data = 0;
2427
2428         DEBUGFUNC("e1000_reset_mdicnfg_82580");
2429
2430         if (hw->mac.type != e1000_82580)
2431                 goto out;
2432         if (!e1000_sgmii_active_82575(hw))
2433                 goto out;
2434
2435         ret_val = hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_A +
2436                                    NVM_82580_LAN_FUNC_OFFSET(hw->bus.func), 1,
2437                                    &nvm_data);
2438         if (ret_val) {
2439                 DEBUGOUT("NVM Read Error\n");
2440                 goto out;
2441         }
2442
2443         mdicnfg = E1000_READ_REG(hw, E1000_MDICNFG);
2444         if (nvm_data & NVM_WORD24_EXT_MDIO)
2445                 mdicnfg |= E1000_MDICNFG_EXT_MDIO;
2446         if (nvm_data & NVM_WORD24_COM_MDIO)
2447                 mdicnfg |= E1000_MDICNFG_COM_MDIO;
2448         E1000_WRITE_REG(hw, E1000_MDICNFG, mdicnfg);
2449 out:
2450         return ret_val;
2451 }
2452
2453 /**
2454  *  e1000_reset_hw_82580 - Reset hardware
2455  *  @hw: pointer to the HW structure
2456  *
2457  *  This resets function or entire device (all ports, etc.)
2458  *  to a known state.
2459  **/
2460 STATIC s32 e1000_reset_hw_82580(struct e1000_hw *hw)
2461 {
2462         s32 ret_val = E1000_SUCCESS;
2463         /* BH SW mailbox bit in SW_FW_SYNC */
2464         u16 swmbsw_mask = E1000_SW_SYNCH_MB;
2465         u32 ctrl;
2466         bool global_device_reset = hw->dev_spec._82575.global_device_reset;
2467
2468         DEBUGFUNC("e1000_reset_hw_82580");
2469
2470         hw->dev_spec._82575.global_device_reset = false;
2471
2472         /* 82580 does not reliably do global_device_reset due to hw errata */
2473         if (hw->mac.type == e1000_82580)
2474                 global_device_reset = false;
2475
2476         /* Get current control state. */
2477         ctrl = E1000_READ_REG(hw, E1000_CTRL);
2478
2479         /*
2480          * Prevent the PCI-E bus from sticking if there is no TLP connection
2481          * on the last TLP read/write transaction when MAC is reset.
2482          */
2483         ret_val = e1000_disable_pcie_master_generic(hw);
2484         if (ret_val)
2485                 DEBUGOUT("PCI-E Master disable polling has failed.\n");
2486
2487         DEBUGOUT("Masking off all interrupts\n");
2488         E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff);
2489         E1000_WRITE_REG(hw, E1000_RCTL, 0);
2490         E1000_WRITE_REG(hw, E1000_TCTL, E1000_TCTL_PSP);
2491         E1000_WRITE_FLUSH(hw);
2492
2493         msec_delay(10);
2494
2495         /* Determine whether or not a global dev reset is requested */
2496         if (global_device_reset && hw->mac.ops.acquire_swfw_sync(hw,
2497             swmbsw_mask))
2498                         global_device_reset = false;
2499
2500         if (global_device_reset && !(E1000_READ_REG(hw, E1000_STATUS) &
2501             E1000_STAT_DEV_RST_SET))
2502                 ctrl |= E1000_CTRL_DEV_RST;
2503         else
2504                 ctrl |= E1000_CTRL_RST;
2505
2506         E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
2507
2508         switch (hw->device_id) {
2509         case E1000_DEV_ID_DH89XXCC_SGMII:
2510                 break;
2511         default:
2512                 E1000_WRITE_FLUSH(hw);
2513                 break;
2514         }
2515
2516         /* Add delay to insure DEV_RST or RST has time to complete */
2517         msec_delay(5);
2518
2519         ret_val = e1000_get_auto_rd_done_generic(hw);
2520         if (ret_val) {
2521                 /*
2522                  * When auto config read does not complete, do not
2523                  * return with an error. This can happen in situations
2524                  * where there is no eeprom and prevents getting link.
2525                  */
2526                 DEBUGOUT("Auto Read Done did not complete\n");
2527         }
2528
2529         /* clear global device reset status bit */
2530         E1000_WRITE_REG(hw, E1000_STATUS, E1000_STAT_DEV_RST_SET);
2531
2532         /* Clear any pending interrupt events. */
2533         E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff);
2534         E1000_READ_REG(hw, E1000_ICR);
2535
2536         ret_val = e1000_reset_mdicnfg_82580(hw);
2537         if (ret_val)
2538                 DEBUGOUT("Could not reset MDICNFG based on EEPROM\n");
2539
2540         /* Install any alternate MAC address into RAR0 */
2541         ret_val = e1000_check_alt_mac_addr_generic(hw);
2542
2543         /* Release semaphore */
2544         if (global_device_reset)
2545                 hw->mac.ops.release_swfw_sync(hw, swmbsw_mask);
2546
2547         return ret_val;
2548 }
2549
2550 /**
2551  *  e1000_rxpbs_adjust_82580 - adjust RXPBS value to reflect actual Rx PBA size
2552  *  @data: data received by reading RXPBS register
2553  *
2554  *  The 82580 uses a table based approach for packet buffer allocation sizes.
2555  *  This function converts the retrieved value into the correct table value
2556  *     0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7
2557  *  0x0 36  72 144   1   2   4   8  16
2558  *  0x8 35  70 140 rsv rsv rsv rsv rsv
2559  */
2560 u16 e1000_rxpbs_adjust_82580(u32 data)
2561 {
2562         u16 ret_val = 0;
2563
2564         if (data < E1000_82580_RXPBS_TABLE_SIZE)
2565                 ret_val = e1000_82580_rxpbs_table[data];
2566
2567         return ret_val;
2568 }
2569
2570 /**
2571  *  e1000_validate_nvm_checksum_with_offset - Validate EEPROM
2572  *  checksum
2573  *  @hw: pointer to the HW structure
2574  *  @offset: offset in words of the checksum protected region
2575  *
2576  *  Calculates the EEPROM checksum by reading/adding each word of the EEPROM
2577  *  and then verifies that the sum of the EEPROM is equal to 0xBABA.
2578  **/
2579 s32 e1000_validate_nvm_checksum_with_offset(struct e1000_hw *hw, u16 offset)
2580 {
2581         s32 ret_val = E1000_SUCCESS;
2582         u16 checksum = 0;
2583         u16 i, nvm_data;
2584
2585         DEBUGFUNC("e1000_validate_nvm_checksum_with_offset");
2586
2587         for (i = offset; i < ((NVM_CHECKSUM_REG + offset) + 1); i++) {
2588                 ret_val = hw->nvm.ops.read(hw, i, 1, &nvm_data);
2589                 if (ret_val) {
2590                         DEBUGOUT("NVM Read Error\n");
2591                         goto out;
2592                 }
2593                 checksum += nvm_data;
2594         }
2595
2596         if (checksum != (u16) NVM_SUM) {
2597                 DEBUGOUT("NVM Checksum Invalid\n");
2598                 ret_val = -E1000_ERR_NVM;
2599                 goto out;
2600         }
2601
2602 out:
2603         return ret_val;
2604 }
2605
2606 /**
2607  *  e1000_update_nvm_checksum_with_offset - Update EEPROM
2608  *  checksum
2609  *  @hw: pointer to the HW structure
2610  *  @offset: offset in words of the checksum protected region
2611  *
2612  *  Updates the EEPROM checksum by reading/adding each word of the EEPROM
2613  *  up to the checksum.  Then calculates the EEPROM checksum and writes the
2614  *  value to the EEPROM.
2615  **/
2616 s32 e1000_update_nvm_checksum_with_offset(struct e1000_hw *hw, u16 offset)
2617 {
2618         s32 ret_val;
2619         u16 checksum = 0;
2620         u16 i, nvm_data;
2621
2622         DEBUGFUNC("e1000_update_nvm_checksum_with_offset");
2623
2624         for (i = offset; i < (NVM_CHECKSUM_REG + offset); i++) {
2625                 ret_val = hw->nvm.ops.read(hw, i, 1, &nvm_data);
2626                 if (ret_val) {
2627                         DEBUGOUT("NVM Read Error while updating checksum.\n");
2628                         goto out;
2629                 }
2630                 checksum += nvm_data;
2631         }
2632         checksum = (u16) NVM_SUM - checksum;
2633         ret_val = hw->nvm.ops.write(hw, (NVM_CHECKSUM_REG + offset), 1,
2634                                     &checksum);
2635         if (ret_val)
2636                 DEBUGOUT("NVM Write Error while updating checksum.\n");
2637
2638 out:
2639         return ret_val;
2640 }
2641
2642 /**
2643  *  e1000_validate_nvm_checksum_82580 - Validate EEPROM checksum
2644  *  @hw: pointer to the HW structure
2645  *
2646  *  Calculates the EEPROM section checksum by reading/adding each word of
2647  *  the EEPROM and then verifies that the sum of the EEPROM is
2648  *  equal to 0xBABA.
2649  **/
2650 STATIC s32 e1000_validate_nvm_checksum_82580(struct e1000_hw *hw)
2651 {
2652         s32 ret_val;
2653         u16 eeprom_regions_count = 1;
2654         u16 j, nvm_data;
2655         u16 nvm_offset;
2656
2657         DEBUGFUNC("e1000_validate_nvm_checksum_82580");
2658
2659         ret_val = hw->nvm.ops.read(hw, NVM_COMPATIBILITY_REG_3, 1, &nvm_data);
2660         if (ret_val) {
2661                 DEBUGOUT("NVM Read Error\n");
2662                 goto out;
2663         }
2664
2665         if (nvm_data & NVM_COMPATIBILITY_BIT_MASK) {
2666                 /* if chekcsums compatibility bit is set validate checksums
2667                  * for all 4 ports. */
2668                 eeprom_regions_count = 4;
2669         }
2670
2671         for (j = 0; j < eeprom_regions_count; j++) {
2672                 nvm_offset = NVM_82580_LAN_FUNC_OFFSET(j);
2673                 ret_val = e1000_validate_nvm_checksum_with_offset(hw,
2674                                                                   nvm_offset);
2675                 if (ret_val != E1000_SUCCESS)
2676                         goto out;
2677         }
2678
2679 out:
2680         return ret_val;
2681 }
2682
2683 /**
2684  *  e1000_update_nvm_checksum_82580 - Update EEPROM checksum
2685  *  @hw: pointer to the HW structure
2686  *
2687  *  Updates the EEPROM section checksums for all 4 ports by reading/adding
2688  *  each word of the EEPROM up to the checksum.  Then calculates the EEPROM
2689  *  checksum and writes the value to the EEPROM.
2690  **/
2691 STATIC s32 e1000_update_nvm_checksum_82580(struct e1000_hw *hw)
2692 {
2693         s32 ret_val;
2694         u16 j, nvm_data;
2695         u16 nvm_offset;
2696
2697         DEBUGFUNC("e1000_update_nvm_checksum_82580");
2698
2699         ret_val = hw->nvm.ops.read(hw, NVM_COMPATIBILITY_REG_3, 1, &nvm_data);
2700         if (ret_val) {
2701                 DEBUGOUT("NVM Read Error while updating checksum compatibility bit.\n");
2702                 goto out;
2703         }
2704
2705         if (!(nvm_data & NVM_COMPATIBILITY_BIT_MASK)) {
2706                 /* set compatibility bit to validate checksums appropriately */
2707                 nvm_data = nvm_data | NVM_COMPATIBILITY_BIT_MASK;
2708                 ret_val = hw->nvm.ops.write(hw, NVM_COMPATIBILITY_REG_3, 1,
2709                                             &nvm_data);
2710                 if (ret_val) {
2711                         DEBUGOUT("NVM Write Error while updating checksum compatibility bit.\n");
2712                         goto out;
2713                 }
2714         }
2715
2716         for (j = 0; j < 4; j++) {
2717                 nvm_offset = NVM_82580_LAN_FUNC_OFFSET(j);
2718                 ret_val = e1000_update_nvm_checksum_with_offset(hw, nvm_offset);
2719                 if (ret_val)
2720                         goto out;
2721         }
2722
2723 out:
2724         return ret_val;
2725 }
2726
2727 /**
2728  *  e1000_validate_nvm_checksum_i350 - Validate EEPROM checksum
2729  *  @hw: pointer to the HW structure
2730  *
2731  *  Calculates the EEPROM section checksum by reading/adding each word of
2732  *  the EEPROM and then verifies that the sum of the EEPROM is
2733  *  equal to 0xBABA.
2734  **/
2735 STATIC s32 e1000_validate_nvm_checksum_i350(struct e1000_hw *hw)
2736 {
2737         s32 ret_val = E1000_SUCCESS;
2738         u16 j;
2739         u16 nvm_offset;
2740
2741         DEBUGFUNC("e1000_validate_nvm_checksum_i350");
2742
2743         for (j = 0; j < 4; j++) {
2744                 nvm_offset = NVM_82580_LAN_FUNC_OFFSET(j);
2745                 ret_val = e1000_validate_nvm_checksum_with_offset(hw,
2746                                                                   nvm_offset);
2747                 if (ret_val != E1000_SUCCESS)
2748                         goto out;
2749         }
2750
2751 out:
2752         return ret_val;
2753 }
2754
2755 /**
2756  *  e1000_update_nvm_checksum_i350 - Update EEPROM checksum
2757  *  @hw: pointer to the HW structure
2758  *
2759  *  Updates the EEPROM section checksums for all 4 ports by reading/adding
2760  *  each word of the EEPROM up to the checksum.  Then calculates the EEPROM
2761  *  checksum and writes the value to the EEPROM.
2762  **/
2763 STATIC s32 e1000_update_nvm_checksum_i350(struct e1000_hw *hw)
2764 {
2765         s32 ret_val = E1000_SUCCESS;
2766         u16 j;
2767         u16 nvm_offset;
2768
2769         DEBUGFUNC("e1000_update_nvm_checksum_i350");
2770
2771         for (j = 0; j < 4; j++) {
2772                 nvm_offset = NVM_82580_LAN_FUNC_OFFSET(j);
2773                 ret_val = e1000_update_nvm_checksum_with_offset(hw, nvm_offset);
2774                 if (ret_val != E1000_SUCCESS)
2775                         goto out;
2776         }
2777
2778 out:
2779         return ret_val;
2780 }
2781
2782 /**
2783  *  __e1000_access_emi_reg - Read/write EMI register
2784  *  @hw: pointer to the HW structure
2785  *  @addr: EMI address to program
2786  *  @data: pointer to value to read/write from/to the EMI address
2787  *  @read: boolean flag to indicate read or write
2788  **/
2789 STATIC s32 __e1000_access_emi_reg(struct e1000_hw *hw, u16 address,
2790                                   u16 *data, bool read)
2791 {
2792         s32 ret_val;
2793
2794         DEBUGFUNC("__e1000_access_emi_reg");
2795
2796         ret_val = hw->phy.ops.write_reg(hw, E1000_EMIADD, address);
2797         if (ret_val)
2798                 return ret_val;
2799
2800         if (read)
2801                 ret_val = hw->phy.ops.read_reg(hw, E1000_EMIDATA, data);
2802         else
2803                 ret_val = hw->phy.ops.write_reg(hw, E1000_EMIDATA, *data);
2804
2805         return ret_val;
2806 }
2807
2808 /**
2809  *  e1000_read_emi_reg - Read Extended Management Interface register
2810  *  @hw: pointer to the HW structure
2811  *  @addr: EMI address to program
2812  *  @data: value to be read from the EMI address
2813  **/
2814 s32 e1000_read_emi_reg(struct e1000_hw *hw, u16 addr, u16 *data)
2815 {
2816         DEBUGFUNC("e1000_read_emi_reg");
2817
2818         return __e1000_access_emi_reg(hw, addr, data, true);
2819 }
2820
2821 /**
2822  *  e1000_initialize_M88E1512_phy - Initialize M88E1512 PHY
2823  *  @hw: pointer to the HW structure
2824  *
2825  *  Initialize Marvell 1512 to work correctly with Avoton.
2826  **/
2827 s32 e1000_initialize_M88E1512_phy(struct e1000_hw *hw)
2828 {
2829         struct e1000_phy_info *phy = &hw->phy;
2830         s32 ret_val = E1000_SUCCESS;
2831
2832         DEBUGFUNC("e1000_initialize_M88E1512_phy");
2833
2834         /* Check if this is correct PHY. */
2835         if (phy->id != M88E1512_E_PHY_ID)
2836                 goto out;
2837
2838         /* Switch to PHY page 0xFF. */
2839         ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 0x00FF);
2840         if (ret_val)
2841                 goto out;
2842
2843         ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_2, 0x214B);
2844         if (ret_val)
2845                 goto out;
2846
2847         ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_1, 0x2144);
2848         if (ret_val)
2849                 goto out;
2850
2851         ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_2, 0x0C28);
2852         if (ret_val)
2853                 goto out;
2854
2855         ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_1, 0x2146);
2856         if (ret_val)
2857                 goto out;
2858
2859         ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_2, 0xB233);
2860         if (ret_val)
2861                 goto out;
2862
2863         ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_1, 0x214D);
2864         if (ret_val)
2865                 goto out;
2866
2867         ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_2, 0xCC0C);
2868         if (ret_val)
2869                 goto out;
2870
2871         ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_1, 0x2159);
2872         if (ret_val)
2873                 goto out;
2874
2875         /* Switch to PHY page 0xFB. */
2876         ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 0x00FB);
2877         if (ret_val)
2878                 goto out;
2879
2880         ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_3, 0x000D);
2881         if (ret_val)
2882                 goto out;
2883
2884         /* Switch to PHY page 0x12. */
2885         ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 0x12);
2886         if (ret_val)
2887                 goto out;
2888
2889         /* Change mode to SGMII-to-Copper */
2890         ret_val = phy->ops.write_reg(hw, E1000_M88E1512_MODE, 0x8001);
2891         if (ret_val)
2892                 goto out;
2893
2894         /* Return the PHY to page 0. */
2895         ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 0);
2896         if (ret_val)
2897                 goto out;
2898
2899         ret_val = phy->ops.commit(hw);
2900         if (ret_val) {
2901                 DEBUGOUT("Error committing the PHY changes\n");
2902                 return ret_val;
2903         }
2904
2905         msec_delay(1000);
2906 out:
2907         return ret_val;
2908 }
2909
2910 /**
2911  *  e1000_initialize_M88E1543_phy - Initialize M88E1543 PHY
2912  *  @hw: pointer to the HW structure
2913  *
2914  *  Initialize Marvell 1543 to work correctly with Avoton.
2915  **/
2916 s32 e1000_initialize_M88E1543_phy(struct e1000_hw *hw)
2917 {
2918         struct e1000_phy_info *phy = &hw->phy;
2919         s32 ret_val = E1000_SUCCESS;
2920
2921         DEBUGFUNC("e1000_initialize_M88E1543_phy");
2922
2923         /* Check if this is correct PHY. */
2924         if (phy->id != M88E1543_E_PHY_ID)
2925                 goto out;
2926
2927         /* Switch to PHY page 0xFF. */
2928         ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 0x00FF);
2929         if (ret_val)
2930                 goto out;
2931
2932         ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_2, 0x214B);
2933         if (ret_val)
2934                 goto out;
2935
2936         ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_1, 0x2144);
2937         if (ret_val)
2938                 goto out;
2939
2940         ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_2, 0x0C28);
2941         if (ret_val)
2942                 goto out;
2943
2944         ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_1, 0x2146);
2945         if (ret_val)
2946                 goto out;
2947
2948         ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_2, 0xB233);
2949         if (ret_val)
2950                 goto out;
2951
2952         ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_1, 0x214D);
2953         if (ret_val)
2954                 goto out;
2955
2956         ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_2, 0xDC0C);
2957         if (ret_val)
2958                 goto out;
2959
2960         ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_1, 0x2159);
2961         if (ret_val)
2962                 goto out;
2963
2964         /* Switch to PHY page 0xFB. */
2965         ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 0x00FB);
2966         if (ret_val)
2967                 goto out;
2968
2969         ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_3, 0xC00D);
2970         if (ret_val)
2971                 goto out;
2972
2973         /* Switch to PHY page 0x12. */
2974         ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 0x12);
2975         if (ret_val)
2976                 goto out;
2977
2978         /* Change mode to SGMII-to-Copper */
2979         ret_val = phy->ops.write_reg(hw, E1000_M88E1512_MODE, 0x8001);
2980         if (ret_val)
2981                 goto out;
2982
2983         /* Switch to PHY page 1. */
2984         ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 0x1);
2985         if (ret_val)
2986                 goto out;
2987
2988         /* Change mode to 1000BASE-X/SGMII and autoneg enable; reset */
2989         ret_val = phy->ops.write_reg(hw, E1000_M88E1543_FIBER_CTRL, 0x9140);
2990         if (ret_val)
2991                 goto out;
2992
2993         /* Return the PHY to page 0. */
2994         ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 0);
2995         if (ret_val)
2996                 goto out;
2997
2998         ret_val = phy->ops.commit(hw);
2999         if (ret_val) {
3000                 DEBUGOUT("Error committing the PHY changes\n");
3001                 return ret_val;
3002         }
3003
3004         msec_delay(1000);
3005 out:
3006         return ret_val;
3007 }
3008
3009 /**
3010  *  e1000_set_eee_i350 - Enable/disable EEE support
3011  *  @hw: pointer to the HW structure
3012  *  @adv1g: boolean flag enabling 1G EEE advertisement
3013  *  @adv100m: boolean flag enabling 100M EEE advertisement
3014  *
3015  *  Enable/disable EEE based on setting in dev_spec structure.
3016  *
3017  **/
3018 s32 e1000_set_eee_i350(struct e1000_hw *hw, bool adv1G, bool adv100M)
3019 {
3020         u32 ipcnfg, eeer;
3021
3022         DEBUGFUNC("e1000_set_eee_i350");
3023
3024         if ((hw->mac.type < e1000_i350) ||
3025             (hw->phy.media_type != e1000_media_type_copper))
3026                 goto out;
3027         ipcnfg = E1000_READ_REG(hw, E1000_IPCNFG);
3028         eeer = E1000_READ_REG(hw, E1000_EEER);
3029
3030         /* enable or disable per user setting */
3031         if (!(hw->dev_spec._82575.eee_disable)) {
3032                 u32 eee_su = E1000_READ_REG(hw, E1000_EEE_SU);
3033
3034                 if (adv100M)
3035                         ipcnfg |= E1000_IPCNFG_EEE_100M_AN;
3036                 else
3037                         ipcnfg &= ~E1000_IPCNFG_EEE_100M_AN;
3038
3039                 if (adv1G)
3040                         ipcnfg |= E1000_IPCNFG_EEE_1G_AN;
3041                 else
3042                         ipcnfg &= ~E1000_IPCNFG_EEE_1G_AN;
3043
3044                 eeer |= (E1000_EEER_TX_LPI_EN | E1000_EEER_RX_LPI_EN |
3045                          E1000_EEER_LPI_FC);
3046
3047                 /* This bit should not be set in normal operation. */
3048                 if (eee_su & E1000_EEE_SU_LPI_CLK_STP)
3049                         DEBUGOUT("LPI Clock Stop Bit should not be set!\n");
3050         } else {
3051                 ipcnfg &= ~(E1000_IPCNFG_EEE_1G_AN | E1000_IPCNFG_EEE_100M_AN);
3052                 eeer &= ~(E1000_EEER_TX_LPI_EN | E1000_EEER_RX_LPI_EN |
3053                           E1000_EEER_LPI_FC);
3054         }
3055         E1000_WRITE_REG(hw, E1000_IPCNFG, ipcnfg);
3056         E1000_WRITE_REG(hw, E1000_EEER, eeer);
3057         E1000_READ_REG(hw, E1000_IPCNFG);
3058         E1000_READ_REG(hw, E1000_EEER);
3059 out:
3060
3061         return E1000_SUCCESS;
3062 }
3063
3064 /**
3065  *  e1000_set_eee_i354 - Enable/disable EEE support
3066  *  @hw: pointer to the HW structure
3067  *  @adv1g: boolean flag enabling 1G EEE advertisement
3068  *  @adv100m: boolean flag enabling 100M EEE advertisement
3069  *
3070  *  Enable/disable EEE legacy mode based on setting in dev_spec structure.
3071  *
3072  **/
3073 s32 e1000_set_eee_i354(struct e1000_hw *hw, bool adv1G, bool adv100M)
3074 {
3075         struct e1000_phy_info *phy = &hw->phy;
3076         s32 ret_val = E1000_SUCCESS;
3077         u16 phy_data;
3078
3079         DEBUGFUNC("e1000_set_eee_i354");
3080
3081         if ((hw->phy.media_type != e1000_media_type_copper) ||
3082             ((phy->id != M88E1543_E_PHY_ID) &&
3083             (phy->id != M88E1512_E_PHY_ID)))
3084                 goto out;
3085
3086         if (!hw->dev_spec._82575.eee_disable) {
3087                 /* Switch to PHY page 18. */
3088                 ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 18);
3089                 if (ret_val)
3090                         goto out;
3091
3092                 ret_val = phy->ops.read_reg(hw, E1000_M88E1543_EEE_CTRL_1,
3093                                             &phy_data);
3094                 if (ret_val)
3095                         goto out;
3096
3097                 phy_data |= E1000_M88E1543_EEE_CTRL_1_MS;
3098                 ret_val = phy->ops.write_reg(hw, E1000_M88E1543_EEE_CTRL_1,
3099                                              phy_data);
3100                 if (ret_val)
3101                         goto out;
3102
3103                 /* Return the PHY to page 0. */
3104                 ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 0);
3105                 if (ret_val)
3106                         goto out;
3107
3108                 /* Turn on EEE advertisement. */
3109                 ret_val = e1000_read_xmdio_reg(hw, E1000_EEE_ADV_ADDR_I354,
3110                                                E1000_EEE_ADV_DEV_I354,
3111                                                &phy_data);
3112                 if (ret_val)
3113                         goto out;
3114
3115                 if (adv100M)
3116                         phy_data |= E1000_EEE_ADV_100_SUPPORTED;
3117                 else
3118                         phy_data &= ~E1000_EEE_ADV_100_SUPPORTED;
3119
3120                 if (adv1G)
3121                         phy_data |= E1000_EEE_ADV_1000_SUPPORTED;
3122                 else
3123                         phy_data &= ~E1000_EEE_ADV_1000_SUPPORTED;
3124
3125                 ret_val = e1000_write_xmdio_reg(hw, E1000_EEE_ADV_ADDR_I354,
3126                                                 E1000_EEE_ADV_DEV_I354,
3127                                                 phy_data);
3128         } else {
3129                 /* Turn off EEE advertisement. */
3130                 ret_val = e1000_read_xmdio_reg(hw, E1000_EEE_ADV_ADDR_I354,
3131                                                E1000_EEE_ADV_DEV_I354,
3132                                                &phy_data);
3133                 if (ret_val)
3134                         goto out;
3135
3136                 phy_data &= ~(E1000_EEE_ADV_100_SUPPORTED |
3137                               E1000_EEE_ADV_1000_SUPPORTED);
3138                 ret_val = e1000_write_xmdio_reg(hw, E1000_EEE_ADV_ADDR_I354,
3139                                                 E1000_EEE_ADV_DEV_I354,
3140                                                 phy_data);
3141         }
3142
3143 out:
3144         return ret_val;
3145 }
3146
3147 /**
3148  *  e1000_get_eee_status_i354 - Get EEE status
3149  *  @hw: pointer to the HW structure
3150  *  @status: EEE status
3151  *
3152  *  Get EEE status by guessing based on whether Tx or Rx LPI indications have
3153  *  been received.
3154  **/
3155 s32 e1000_get_eee_status_i354(struct e1000_hw *hw, bool *status)
3156 {
3157         struct e1000_phy_info *phy = &hw->phy;
3158         s32 ret_val = E1000_SUCCESS;
3159         u16 phy_data;
3160
3161         DEBUGFUNC("e1000_get_eee_status_i354");
3162
3163         /* Check if EEE is supported on this device. */
3164         if ((hw->phy.media_type != e1000_media_type_copper) ||
3165             ((phy->id != M88E1543_E_PHY_ID) &&
3166             (phy->id != M88E1512_E_PHY_ID)))
3167                 goto out;
3168
3169         ret_val = e1000_read_xmdio_reg(hw, E1000_PCS_STATUS_ADDR_I354,
3170                                        E1000_PCS_STATUS_DEV_I354,
3171                                        &phy_data);
3172         if (ret_val)
3173                 goto out;
3174
3175         *status = phy_data & (E1000_PCS_STATUS_TX_LPI_RCVD |
3176                               E1000_PCS_STATUS_RX_LPI_RCVD) ? true : false;
3177
3178 out:
3179         return ret_val;
3180 }
3181
3182 /* Due to a hw errata, if the host tries to  configure the VFTA register
3183  * while performing queries from the BMC or DMA, then the VFTA in some
3184  * cases won't be written.
3185  */
3186
3187 /**
3188  *  e1000_clear_vfta_i350 - Clear VLAN filter table
3189  *  @hw: pointer to the HW structure
3190  *
3191  *  Clears the register array which contains the VLAN filter table by
3192  *  setting all the values to 0.
3193  **/
3194 void e1000_clear_vfta_i350(struct e1000_hw *hw)
3195 {
3196         u32 offset;
3197         int i;
3198
3199         DEBUGFUNC("e1000_clear_vfta_350");
3200
3201         for (offset = 0; offset < E1000_VLAN_FILTER_TBL_SIZE; offset++) {
3202                 for (i = 0; i < 10; i++)
3203                         E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, offset, 0);
3204
3205                 E1000_WRITE_FLUSH(hw);
3206         }
3207 }
3208
3209 /**
3210  *  e1000_write_vfta_i350 - Write value to VLAN filter table
3211  *  @hw: pointer to the HW structure
3212  *  @offset: register offset in VLAN filter table
3213  *  @value: register value written to VLAN filter table
3214  *
3215  *  Writes value at the given offset in the register array which stores
3216  *  the VLAN filter table.
3217  **/
3218 void e1000_write_vfta_i350(struct e1000_hw *hw, u32 offset, u32 value)
3219 {
3220         int i;
3221
3222         DEBUGFUNC("e1000_write_vfta_350");
3223
3224         for (i = 0; i < 10; i++)
3225                 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, offset, value);
3226
3227         E1000_WRITE_FLUSH(hw);
3228 }
3229
3230
3231 /**
3232  *  e1000_set_i2c_bb - Enable I2C bit-bang
3233  *  @hw: pointer to the HW structure
3234  *
3235  *  Enable I2C bit-bang interface
3236  *
3237  **/
3238 s32 e1000_set_i2c_bb(struct e1000_hw *hw)
3239 {
3240         s32 ret_val = E1000_SUCCESS;
3241         u32 ctrl_ext, i2cparams;
3242
3243         DEBUGFUNC("e1000_set_i2c_bb");
3244
3245         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
3246         ctrl_ext |= E1000_CTRL_I2C_ENA;
3247         E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
3248         E1000_WRITE_FLUSH(hw);
3249
3250         i2cparams = E1000_READ_REG(hw, E1000_I2CPARAMS);
3251         i2cparams |= E1000_I2CBB_EN;
3252         i2cparams |= E1000_I2C_DATA_OE_N;
3253         i2cparams |= E1000_I2C_CLK_OE_N;
3254         E1000_WRITE_REG(hw, E1000_I2CPARAMS, i2cparams);
3255         E1000_WRITE_FLUSH(hw);
3256
3257         return ret_val;
3258 }
3259
3260 /**
3261  *  e1000_read_i2c_byte_generic - Reads 8 bit word over I2C
3262  *  @hw: pointer to hardware structure
3263  *  @byte_offset: byte offset to read
3264  *  @dev_addr: device address
3265  *  @data: value read
3266  *
3267  *  Performs byte read operation over I2C interface at
3268  *  a specified device address.
3269  **/
3270 s32 e1000_read_i2c_byte_generic(struct e1000_hw *hw, u8 byte_offset,
3271                                 u8 dev_addr, u8 *data)
3272 {
3273         s32 status = E1000_SUCCESS;
3274         u32 max_retry = 10;
3275         u32 retry = 1;
3276         u16 swfw_mask = 0;
3277
3278         bool nack = true;
3279
3280         DEBUGFUNC("e1000_read_i2c_byte_generic");
3281
3282         swfw_mask = E1000_SWFW_PHY0_SM;
3283
3284         do {
3285                 if (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask)
3286                     != E1000_SUCCESS) {
3287                         status = E1000_ERR_SWFW_SYNC;
3288                         goto read_byte_out;
3289                 }
3290
3291                 e1000_i2c_start(hw);
3292
3293                 /* Device Address and write indication */
3294                 status = e1000_clock_out_i2c_byte(hw, dev_addr);
3295                 if (status != E1000_SUCCESS)
3296                         goto fail;
3297
3298                 status = e1000_get_i2c_ack(hw);
3299                 if (status != E1000_SUCCESS)
3300                         goto fail;
3301
3302                 status = e1000_clock_out_i2c_byte(hw, byte_offset);
3303                 if (status != E1000_SUCCESS)
3304                         goto fail;
3305
3306                 status = e1000_get_i2c_ack(hw);
3307                 if (status != E1000_SUCCESS)
3308                         goto fail;
3309
3310                 e1000_i2c_start(hw);
3311
3312                 /* Device Address and read indication */
3313                 status = e1000_clock_out_i2c_byte(hw, (dev_addr | 0x1));
3314                 if (status != E1000_SUCCESS)
3315                         goto fail;
3316
3317                 status = e1000_get_i2c_ack(hw);
3318                 if (status != E1000_SUCCESS)
3319                         goto fail;
3320
3321                 status = e1000_clock_in_i2c_byte(hw, data);
3322                 if (status != E1000_SUCCESS)
3323                         goto fail;
3324
3325                 status = e1000_clock_out_i2c_bit(hw, nack);
3326                 if (status != E1000_SUCCESS)
3327                         goto fail;
3328
3329                 e1000_i2c_stop(hw);
3330                 break;
3331
3332 fail:
3333                 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
3334                 msec_delay(100);
3335                 e1000_i2c_bus_clear(hw);
3336                 retry++;
3337                 if (retry < max_retry)
3338                         DEBUGOUT("I2C byte read error - Retrying.\n");
3339                 else
3340                         DEBUGOUT("I2C byte read error.\n");
3341
3342         } while (retry < max_retry);
3343
3344         hw->mac.ops.release_swfw_sync(hw, swfw_mask);
3345
3346 read_byte_out:
3347
3348         return status;
3349 }
3350
3351 /**
3352  *  e1000_write_i2c_byte_generic - Writes 8 bit word over I2C
3353  *  @hw: pointer to hardware structure
3354  *  @byte_offset: byte offset to write
3355  *  @dev_addr: device address
3356  *  @data: value to write
3357  *
3358  *  Performs byte write operation over I2C interface at
3359  *  a specified device address.
3360  **/
3361 s32 e1000_write_i2c_byte_generic(struct e1000_hw *hw, u8 byte_offset,
3362                                  u8 dev_addr, u8 data)
3363 {
3364         s32 status = E1000_SUCCESS;
3365         u32 max_retry = 1;
3366         u32 retry = 0;
3367         u16 swfw_mask = 0;
3368
3369         DEBUGFUNC("e1000_write_i2c_byte_generic");
3370
3371         swfw_mask = E1000_SWFW_PHY0_SM;
3372
3373         if (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask) != E1000_SUCCESS) {
3374                 status = E1000_ERR_SWFW_SYNC;
3375                 goto write_byte_out;
3376         }
3377
3378         do {
3379                 e1000_i2c_start(hw);
3380
3381                 status = e1000_clock_out_i2c_byte(hw, dev_addr);
3382                 if (status != E1000_SUCCESS)
3383                         goto fail;
3384
3385                 status = e1000_get_i2c_ack(hw);
3386                 if (status != E1000_SUCCESS)
3387                         goto fail;
3388
3389                 status = e1000_clock_out_i2c_byte(hw, byte_offset);
3390                 if (status != E1000_SUCCESS)
3391                         goto fail;
3392
3393                 status = e1000_get_i2c_ack(hw);
3394                 if (status != E1000_SUCCESS)
3395                         goto fail;
3396
3397                 status = e1000_clock_out_i2c_byte(hw, data);
3398                 if (status != E1000_SUCCESS)
3399                         goto fail;
3400
3401                 status = e1000_get_i2c_ack(hw);
3402                 if (status != E1000_SUCCESS)
3403                         goto fail;
3404
3405                 e1000_i2c_stop(hw);
3406                 break;
3407
3408 fail:
3409                 e1000_i2c_bus_clear(hw);
3410                 retry++;
3411                 if (retry < max_retry)
3412                         DEBUGOUT("I2C byte write error - Retrying.\n");
3413                 else
3414                         DEBUGOUT("I2C byte write error.\n");
3415         } while (retry < max_retry);
3416
3417         hw->mac.ops.release_swfw_sync(hw, swfw_mask);
3418
3419 write_byte_out:
3420
3421         return status;
3422 }
3423
3424 /**
3425  *  e1000_i2c_start - Sets I2C start condition
3426  *  @hw: pointer to hardware structure
3427  *
3428  *  Sets I2C start condition (High -> Low on SDA while SCL is High)
3429  **/
3430 STATIC void e1000_i2c_start(struct e1000_hw *hw)
3431 {
3432         u32 i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS);
3433
3434         DEBUGFUNC("e1000_i2c_start");
3435
3436         /* Start condition must begin with data and clock high */
3437         e1000_set_i2c_data(hw, &i2cctl, 1);
3438         e1000_raise_i2c_clk(hw, &i2cctl);
3439
3440         /* Setup time for start condition (4.7us) */
3441         usec_delay(E1000_I2C_T_SU_STA);
3442
3443         e1000_set_i2c_data(hw, &i2cctl, 0);
3444
3445         /* Hold time for start condition (4us) */
3446         usec_delay(E1000_I2C_T_HD_STA);
3447
3448         e1000_lower_i2c_clk(hw, &i2cctl);
3449
3450         /* Minimum low period of clock is 4.7 us */
3451         usec_delay(E1000_I2C_T_LOW);
3452
3453 }
3454
3455 /**
3456  *  e1000_i2c_stop - Sets I2C stop condition
3457  *  @hw: pointer to hardware structure
3458  *
3459  *  Sets I2C stop condition (Low -> High on SDA while SCL is High)
3460  **/
3461 STATIC void e1000_i2c_stop(struct e1000_hw *hw)
3462 {
3463         u32 i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS);
3464
3465         DEBUGFUNC("e1000_i2c_stop");
3466
3467         /* Stop condition must begin with data low and clock high */
3468         e1000_set_i2c_data(hw, &i2cctl, 0);
3469         e1000_raise_i2c_clk(hw, &i2cctl);
3470
3471         /* Setup time for stop condition (4us) */
3472         usec_delay(E1000_I2C_T_SU_STO);
3473
3474         e1000_set_i2c_data(hw, &i2cctl, 1);
3475
3476         /* bus free time between stop and start (4.7us)*/
3477         usec_delay(E1000_I2C_T_BUF);
3478 }
3479
3480 /**
3481  *  e1000_clock_in_i2c_byte - Clocks in one byte via I2C
3482  *  @hw: pointer to hardware structure
3483  *  @data: data byte to clock in
3484  *
3485  *  Clocks in one byte data via I2C data/clock
3486  **/
3487 STATIC s32 e1000_clock_in_i2c_byte(struct e1000_hw *hw, u8 *data)
3488 {
3489         s32 i;
3490         bool bit = 0;
3491
3492         DEBUGFUNC("e1000_clock_in_i2c_byte");
3493
3494         *data = 0;
3495         for (i = 7; i >= 0; i--) {
3496                 e1000_clock_in_i2c_bit(hw, &bit);
3497                 *data |= bit << i;
3498         }
3499
3500         return E1000_SUCCESS;
3501 }
3502
3503 /**
3504  *  e1000_clock_out_i2c_byte - Clocks out one byte via I2C
3505  *  @hw: pointer to hardware structure
3506  *  @data: data byte clocked out
3507  *
3508  *  Clocks out one byte data via I2C data/clock
3509  **/
3510 STATIC s32 e1000_clock_out_i2c_byte(struct e1000_hw *hw, u8 data)
3511 {
3512         s32 status = E1000_SUCCESS;
3513         s32 i;
3514         u32 i2cctl;
3515         bool bit = 0;
3516
3517         DEBUGFUNC("e1000_clock_out_i2c_byte");
3518
3519         for (i = 7; i >= 0; i--) {
3520                 bit = (data >> i) & 0x1;
3521                 status = e1000_clock_out_i2c_bit(hw, bit);
3522
3523                 if (status != E1000_SUCCESS)
3524                         break;
3525         }
3526
3527         /* Release SDA line (set high) */
3528         i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS);
3529
3530         i2cctl |= E1000_I2C_DATA_OE_N;
3531         E1000_WRITE_REG(hw, E1000_I2CPARAMS, i2cctl);
3532         E1000_WRITE_FLUSH(hw);
3533
3534         return status;
3535 }
3536
3537 /**
3538  *  e1000_get_i2c_ack - Polls for I2C ACK
3539  *  @hw: pointer to hardware structure
3540  *
3541  *  Clocks in/out one bit via I2C data/clock
3542  **/
3543 STATIC s32 e1000_get_i2c_ack(struct e1000_hw *hw)
3544 {
3545         s32 status = E1000_SUCCESS;
3546         u32 i = 0;
3547         u32 i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS);
3548         u32 timeout = 10;
3549         bool ack = true;
3550
3551         DEBUGFUNC("e1000_get_i2c_ack");
3552
3553         e1000_raise_i2c_clk(hw, &i2cctl);
3554
3555         /* Minimum high period of clock is 4us */
3556         usec_delay(E1000_I2C_T_HIGH);
3557
3558         /* Wait until SCL returns high */
3559         for (i = 0; i < timeout; i++) {
3560                 usec_delay(1);
3561                 i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS);
3562                 if (i2cctl & E1000_I2C_CLK_IN)
3563                         break;
3564         }
3565         if (!(i2cctl & E1000_I2C_CLK_IN))
3566                 return E1000_ERR_I2C;
3567
3568         ack = e1000_get_i2c_data(&i2cctl);
3569         if (ack) {
3570                 DEBUGOUT("I2C ack was not received.\n");
3571                 status = E1000_ERR_I2C;
3572         }
3573
3574         e1000_lower_i2c_clk(hw, &i2cctl);
3575
3576         /* Minimum low period of clock is 4.7 us */
3577         usec_delay(E1000_I2C_T_LOW);
3578
3579         return status;
3580 }
3581
3582 /**
3583  *  e1000_clock_in_i2c_bit - Clocks in one bit via I2C data/clock
3584  *  @hw: pointer to hardware structure
3585  *  @data: read data value
3586  *
3587  *  Clocks in one bit via I2C data/clock
3588  **/
3589 STATIC s32 e1000_clock_in_i2c_bit(struct e1000_hw *hw, bool *data)
3590 {
3591         u32 i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS);
3592
3593         DEBUGFUNC("e1000_clock_in_i2c_bit");
3594
3595         e1000_raise_i2c_clk(hw, &i2cctl);
3596
3597         /* Minimum high period of clock is 4us */
3598         usec_delay(E1000_I2C_T_HIGH);
3599
3600         i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS);
3601         *data = e1000_get_i2c_data(&i2cctl);
3602
3603         e1000_lower_i2c_clk(hw, &i2cctl);
3604
3605         /* Minimum low period of clock is 4.7 us */
3606         usec_delay(E1000_I2C_T_LOW);
3607
3608         return E1000_SUCCESS;
3609 }
3610
3611 /**
3612  *  e1000_clock_out_i2c_bit - Clocks in/out one bit via I2C data/clock
3613  *  @hw: pointer to hardware structure
3614  *  @data: data value to write
3615  *
3616  *  Clocks out one bit via I2C data/clock
3617  **/
3618 STATIC s32 e1000_clock_out_i2c_bit(struct e1000_hw *hw, bool data)
3619 {
3620         s32 status;
3621         u32 i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS);
3622
3623         DEBUGFUNC("e1000_clock_out_i2c_bit");
3624
3625         status = e1000_set_i2c_data(hw, &i2cctl, data);
3626         if (status == E1000_SUCCESS) {
3627                 e1000_raise_i2c_clk(hw, &i2cctl);
3628
3629                 /* Minimum high period of clock is 4us */
3630                 usec_delay(E1000_I2C_T_HIGH);
3631
3632                 e1000_lower_i2c_clk(hw, &i2cctl);
3633
3634                 /* Minimum low period of clock is 4.7 us.
3635                  * This also takes care of the data hold time.
3636                  */
3637                 usec_delay(E1000_I2C_T_LOW);
3638         } else {
3639                 status = E1000_ERR_I2C;
3640                 DEBUGOUT1("I2C data was not set to %X\n", data);
3641         }
3642
3643         return status;
3644 }
3645 /**
3646  *  e1000_raise_i2c_clk - Raises the I2C SCL clock
3647  *  @hw: pointer to hardware structure
3648  *  @i2cctl: Current value of I2CCTL register
3649  *
3650  *  Raises the I2C clock line '0'->'1'
3651  **/
3652 STATIC void e1000_raise_i2c_clk(struct e1000_hw *hw, u32 *i2cctl)
3653 {
3654         DEBUGFUNC("e1000_raise_i2c_clk");
3655
3656         *i2cctl |= E1000_I2C_CLK_OUT;
3657         *i2cctl &= ~E1000_I2C_CLK_OE_N;
3658         E1000_WRITE_REG(hw, E1000_I2CPARAMS, *i2cctl);
3659         E1000_WRITE_FLUSH(hw);
3660
3661         /* SCL rise time (1000ns) */
3662         usec_delay(E1000_I2C_T_RISE);
3663 }
3664
3665 /**
3666  *  e1000_lower_i2c_clk - Lowers the I2C SCL clock
3667  *  @hw: pointer to hardware structure
3668  *  @i2cctl: Current value of I2CCTL register
3669  *
3670  *  Lowers the I2C clock line '1'->'0'
3671  **/
3672 STATIC void e1000_lower_i2c_clk(struct e1000_hw *hw, u32 *i2cctl)
3673 {
3674
3675         DEBUGFUNC("e1000_lower_i2c_clk");
3676
3677         *i2cctl &= ~E1000_I2C_CLK_OUT;
3678         *i2cctl &= ~E1000_I2C_CLK_OE_N;
3679         E1000_WRITE_REG(hw, E1000_I2CPARAMS, *i2cctl);
3680         E1000_WRITE_FLUSH(hw);
3681
3682         /* SCL fall time (300ns) */
3683         usec_delay(E1000_I2C_T_FALL);
3684 }
3685
3686 /**
3687  *  e1000_set_i2c_data - Sets the I2C data bit
3688  *  @hw: pointer to hardware structure
3689  *  @i2cctl: Current value of I2CCTL register
3690  *  @data: I2C data value (0 or 1) to set
3691  *
3692  *  Sets the I2C data bit
3693  **/
3694 STATIC s32 e1000_set_i2c_data(struct e1000_hw *hw, u32 *i2cctl, bool data)
3695 {
3696         s32 status = E1000_SUCCESS;
3697
3698         DEBUGFUNC("e1000_set_i2c_data");
3699
3700         if (data)
3701                 *i2cctl |= E1000_I2C_DATA_OUT;
3702         else
3703                 *i2cctl &= ~E1000_I2C_DATA_OUT;
3704
3705         *i2cctl &= ~E1000_I2C_DATA_OE_N;
3706         *i2cctl |= E1000_I2C_CLK_OE_N;
3707         E1000_WRITE_REG(hw, E1000_I2CPARAMS, *i2cctl);
3708         E1000_WRITE_FLUSH(hw);
3709
3710         /* Data rise/fall (1000ns/300ns) and set-up time (250ns) */
3711         usec_delay(E1000_I2C_T_RISE + E1000_I2C_T_FALL + E1000_I2C_T_SU_DATA);
3712
3713         *i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS);
3714         if (data != e1000_get_i2c_data(i2cctl)) {
3715                 status = E1000_ERR_I2C;
3716                 DEBUGOUT1("Error - I2C data was not set to %X.\n", data);
3717         }
3718
3719         return status;
3720 }
3721
3722 /**
3723  *  e1000_get_i2c_data - Reads the I2C SDA data bit
3724  *  @hw: pointer to hardware structure
3725  *  @i2cctl: Current value of I2CCTL register
3726  *
3727  *  Returns the I2C data bit value
3728  **/
3729 STATIC bool e1000_get_i2c_data(u32 *i2cctl)
3730 {
3731         bool data;
3732
3733         DEBUGFUNC("e1000_get_i2c_data");
3734
3735         if (*i2cctl & E1000_I2C_DATA_IN)
3736                 data = 1;
3737         else
3738                 data = 0;
3739
3740         return data;
3741 }
3742
3743 /**
3744  *  e1000_i2c_bus_clear - Clears the I2C bus
3745  *  @hw: pointer to hardware structure
3746  *
3747  *  Clears the I2C bus by sending nine clock pulses.
3748  *  Used when data line is stuck low.
3749  **/
3750 void e1000_i2c_bus_clear(struct e1000_hw *hw)
3751 {
3752         u32 i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS);
3753         u32 i;
3754
3755         DEBUGFUNC("e1000_i2c_bus_clear");
3756
3757         e1000_i2c_start(hw);
3758
3759         e1000_set_i2c_data(hw, &i2cctl, 1);
3760
3761         for (i = 0; i < 9; i++) {
3762                 e1000_raise_i2c_clk(hw, &i2cctl);
3763
3764                 /* Min high period of clock is 4us */
3765                 usec_delay(E1000_I2C_T_HIGH);
3766
3767                 e1000_lower_i2c_clk(hw, &i2cctl);
3768
3769                 /* Min low period of clock is 4.7us*/
3770                 usec_delay(E1000_I2C_T_LOW);
3771         }
3772
3773         e1000_i2c_start(hw);
3774
3775         /* Put the i2c bus back to default state */
3776         e1000_i2c_stop(hw);
3777 }
3778