drivers/net/e1000/base/e1000_82575.c

   1 /*******************************************************************************
   2
   3 Copyright (c) 2001-2015, Intel Corporation
   4 All rights reserved.
   5
   6 Redistribution and use in source and binary forms, with or without
   7 modification, are permitted provided that the following conditions are met:
   8
   9  1. Redistributions of source code must retain the above copyright notice,
  10     this list of conditions and the following disclaimer.
  11
  12  2. Redistributions in binary form must reproduce the above copyright
  13     notice, this list of conditions and the following disclaimer in the
  14     documentation and/or other materials provided with the distribution.
  15
  16  3. Neither the name of the Intel Corporation nor the names of its
  17     contributors may be used to endorse or promote products derived from
  18     this software without specific prior written permission.
  19
  20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
  24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  30 POSSIBILITY OF SUCH DAMAGE.
  31
  32 ***************************************************************************/
  33
  34 /*
  35  * 82575EB Gigabit Network Connection
  36  * 82575EB Gigabit Backplane Connection
  37  * 82575GB Gigabit Network Connection
  38  * 82576 Gigabit Network Connection
  39  * 82576 Quad Port Gigabit Mezzanine Adapter
  40  * 82580 Gigabit Network Connection
  41  * I350 Gigabit Network Connection
  42  */
  43
  44 #include "e1000_api.h"
  45 #include "e1000_i210.h"
  46
  47 STATIC s32  e1000_init_phy_params_82575(struct e1000_hw *hw);
  48 STATIC s32  e1000_init_mac_params_82575(struct e1000_hw *hw);
  49 STATIC s32  e1000_acquire_phy_82575(struct e1000_hw *hw);
  50 STATIC void e1000_release_phy_82575(struct e1000_hw *hw);
  51 STATIC s32  e1000_acquire_nvm_82575(struct e1000_hw *hw);
  52 STATIC void e1000_release_nvm_82575(struct e1000_hw *hw);
  53 STATIC s32  e1000_check_for_link_82575(struct e1000_hw *hw);
  54 STATIC s32  e1000_check_for_link_media_swap(struct e1000_hw *hw);
  55 STATIC s32  e1000_get_cfg_done_82575(struct e1000_hw *hw);
  56 STATIC s32  e1000_get_link_up_info_82575(struct e1000_hw *hw, u16 *speed,
  57                                          u16 *duplex);
  58 STATIC s32  e1000_phy_hw_reset_sgmii_82575(struct e1000_hw *hw);
  59 STATIC s32  e1000_read_phy_reg_sgmii_82575(struct e1000_hw *hw, u32 offset,
  60                                            u16 *data);
  61 STATIC s32  e1000_reset_hw_82575(struct e1000_hw *hw);
  62 STATIC s32  e1000_reset_hw_82580(struct e1000_hw *hw);
  63 STATIC s32  e1000_read_phy_reg_82580(struct e1000_hw *hw,
  64                                      u32 offset, u16 *data);
  65 STATIC s32  e1000_write_phy_reg_82580(struct e1000_hw *hw,
  66                                       u32 offset, u16 data);
  67 STATIC s32  e1000_set_d0_lplu_state_82580(struct e1000_hw *hw,
  68                                           bool active);
  69 STATIC s32  e1000_set_d3_lplu_state_82580(struct e1000_hw *hw,
  70                                           bool active);
  71 STATIC s32  e1000_set_d0_lplu_state_82575(struct e1000_hw *hw,
  72                                           bool active);
  73 STATIC s32  e1000_setup_copper_link_82575(struct e1000_hw *hw);
  74 STATIC s32  e1000_setup_serdes_link_82575(struct e1000_hw *hw);
  75 STATIC s32  e1000_get_media_type_82575(struct e1000_hw *hw);
  76 STATIC s32  e1000_set_sfp_media_type_82575(struct e1000_hw *hw);
  77 STATIC s32  e1000_valid_led_default_82575(struct e1000_hw *hw, u16 *data);
  78 STATIC s32  e1000_write_phy_reg_sgmii_82575(struct e1000_hw *hw,
  79                                             u32 offset, u16 data);
  80 STATIC void e1000_clear_hw_cntrs_82575(struct e1000_hw *hw);
  81 STATIC s32  e1000_acquire_swfw_sync_82575(struct e1000_hw *hw, u16 mask);
  82 STATIC s32  e1000_get_pcs_speed_and_duplex_82575(struct e1000_hw *hw,
  83                                                  u16 *speed, u16 *duplex);
  84 STATIC s32  e1000_get_phy_id_82575(struct e1000_hw *hw);
  85 STATIC void e1000_release_swfw_sync_82575(struct e1000_hw *hw, u16 mask);
  86 STATIC bool e1000_sgmii_active_82575(struct e1000_hw *hw);
  87 STATIC s32  e1000_reset_init_script_82575(struct e1000_hw *hw);
  88 STATIC s32  e1000_read_mac_addr_82575(struct e1000_hw *hw);
  89 STATIC void e1000_config_collision_dist_82575(struct e1000_hw *hw);
  90 STATIC void e1000_power_down_phy_copper_82575(struct e1000_hw *hw);
  91 STATIC void e1000_shutdown_serdes_link_82575(struct e1000_hw *hw);
  92 STATIC void e1000_power_up_serdes_link_82575(struct e1000_hw *hw);
  93 STATIC s32 e1000_set_pcie_completion_timeout(struct e1000_hw *hw);
  94 STATIC s32 e1000_reset_mdicnfg_82580(struct e1000_hw *hw);
  95 STATIC s32 e1000_validate_nvm_checksum_82580(struct e1000_hw *hw);
  96 STATIC s32 e1000_update_nvm_checksum_82580(struct e1000_hw *hw);
  97 STATIC s32 e1000_update_nvm_checksum_with_offset(struct e1000_hw *hw,
  98                                                  u16 offset);
  99 STATIC s32 e1000_validate_nvm_checksum_with_offset(struct e1000_hw *hw,
 100                                                    u16 offset);
 101 STATIC s32 e1000_validate_nvm_checksum_i350(struct e1000_hw *hw);
 102 STATIC s32 e1000_update_nvm_checksum_i350(struct e1000_hw *hw);
 103 STATIC void e1000_clear_vfta_i350(struct e1000_hw *hw);
 104
 105 STATIC void e1000_i2c_start(struct e1000_hw *hw);
 106 STATIC void e1000_i2c_stop(struct e1000_hw *hw);
 107 STATIC s32 e1000_clock_in_i2c_byte(struct e1000_hw *hw, u8 *data);
 108 STATIC s32 e1000_clock_out_i2c_byte(struct e1000_hw *hw, u8 data);
 109 STATIC s32 e1000_get_i2c_ack(struct e1000_hw *hw);
 110 STATIC s32 e1000_clock_in_i2c_bit(struct e1000_hw *hw, bool *data);
 111 STATIC s32 e1000_clock_out_i2c_bit(struct e1000_hw *hw, bool data);
 112 STATIC void e1000_raise_i2c_clk(struct e1000_hw *hw, u32 *i2cctl);
 113 STATIC void e1000_lower_i2c_clk(struct e1000_hw *hw, u32 *i2cctl);
 114 STATIC s32 e1000_set_i2c_data(struct e1000_hw *hw, u32 *i2cctl, bool data);
 115 STATIC bool e1000_get_i2c_data(u32 *i2cctl);
 116
 117 STATIC const u16 e1000_82580_rxpbs_table[] = {
 118         36, 72, 144, 1, 2, 4, 8, 16, 35, 70, 140 };
 119 #define E1000_82580_RXPBS_TABLE_SIZE \
 120         (sizeof(e1000_82580_rxpbs_table) / \
 121          sizeof(e1000_82580_rxpbs_table[0]))
 122
 123
 124 /**
 125  *  e1000_sgmii_uses_mdio_82575 - Determine if I2C pins are for external MDIO
 126  *  @hw: pointer to the HW structure
 127  *
 128  *  Called to determine if the I2C pins are being used for I2C or as an
 129  *  external MDIO interface since the two options are mutually exclusive.
 130  **/
 131 STATIC bool e1000_sgmii_uses_mdio_82575(struct e1000_hw *hw)
 132 {
 133         u32 reg = 0;
 134         bool ext_mdio = false;
 135
 136         DEBUGFUNC("e1000_sgmii_uses_mdio_82575");
 137
 138         switch (hw->mac.type) {
 139         case e1000_82575:
 140         case e1000_82576:
 141                 reg = E1000_READ_REG(hw, E1000_MDIC);
 142                 ext_mdio = !!(reg & E1000_MDIC_DEST);
 143                 break;
 144         case e1000_82580:
 145         case e1000_i350:
 146         case e1000_i354:
 147         case e1000_i210:
 148         case e1000_i211:
 149                 reg = E1000_READ_REG(hw, E1000_MDICNFG);
 150                 ext_mdio = !!(reg & E1000_MDICNFG_EXT_MDIO);
 151                 break;
 152         default:
 153                 break;
 154         }
 155         return ext_mdio;
 156 }
 157
 158 /**
 159  *  e1000_init_phy_params_82575 - Init PHY func ptrs.
 160  *  @hw: pointer to the HW structure
 161  **/
 162 STATIC s32 e1000_init_phy_params_82575(struct e1000_hw *hw)
 163 {
 164         struct e1000_phy_info *phy = &hw->phy;
 165         s32 ret_val = E1000_SUCCESS;
 166         u32 ctrl_ext;
 167
 168         DEBUGFUNC("e1000_init_phy_params_82575");
 169
 170         phy->ops.read_i2c_byte = e1000_read_i2c_byte_generic;
 171         phy->ops.write_i2c_byte = e1000_write_i2c_byte_generic;
 172
 173         if (hw->phy.media_type != e1000_media_type_copper) {
 174                 phy->type = e1000_phy_none;
 175                 goto out;
 176         }
 177
 178         phy->ops.power_up   = e1000_power_up_phy_copper;
 179         phy->ops.power_down = e1000_power_down_phy_copper_82575;
 180
 181         phy->autoneg_mask       = AUTONEG_ADVERTISE_SPEED_DEFAULT;
 182         phy->reset_delay_us     = 100;
 183
 184         phy->ops.acquire        = e1000_acquire_phy_82575;
 185         phy->ops.check_reset_block = e1000_check_reset_block_generic;
 186         phy->ops.commit         = e1000_phy_sw_reset_generic;
 187         phy->ops.get_cfg_done   = e1000_get_cfg_done_82575;
 188         phy->ops.release        = e1000_release_phy_82575;
 189
 190         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
 191
 192         if (e1000_sgmii_active_82575(hw)) {
 193                 phy->ops.reset = e1000_phy_hw_reset_sgmii_82575;
 194                 ctrl_ext |= E1000_CTRL_I2C_ENA;
 195         } else {
 196                 phy->ops.reset = e1000_phy_hw_reset_generic;
 197                 ctrl_ext &= ~E1000_CTRL_I2C_ENA;
 198         }
 199
 200         E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
 201         e1000_reset_mdicnfg_82580(hw);
 202
 203         if (e1000_sgmii_active_82575(hw) && !e1000_sgmii_uses_mdio_82575(hw)) {
 204                 phy->ops.read_reg = e1000_read_phy_reg_sgmii_82575;
 205                 phy->ops.write_reg = e1000_write_phy_reg_sgmii_82575;
 206         } else {
 207                 switch (hw->mac.type) {
 208                 case e1000_82580:
 209                 case e1000_i350:
 210                 case e1000_i354:
 211                         phy->ops.read_reg = e1000_read_phy_reg_82580;
 212                         phy->ops.write_reg = e1000_write_phy_reg_82580;
 213                         break;
 214                 case e1000_i210:
 215                 case e1000_i211:
 216                         phy->ops.read_reg = e1000_read_phy_reg_gs40g;
 217                         phy->ops.write_reg = e1000_write_phy_reg_gs40g;
 218                         break;
 219                 default:
 220                         phy->ops.read_reg = e1000_read_phy_reg_igp;
 221                         phy->ops.write_reg = e1000_write_phy_reg_igp;
 222                 }
 223         }
 224
 225         /* Set phy->phy_addr and phy->id. */
 226         ret_val = e1000_get_phy_id_82575(hw);
 227
 228         /* Verify phy id and set remaining function pointers */
 229         switch (phy->id) {
 230         case M88E1543_E_PHY_ID:
 231         case M88E1512_E_PHY_ID:
 232         case I347AT4_E_PHY_ID:
 233         case M88E1112_E_PHY_ID:
 234         case M88E1340M_E_PHY_ID:
 235         case M88E1111_I_PHY_ID:
 236                 phy->type               = e1000_phy_m88;
 237                 phy->ops.check_polarity = e1000_check_polarity_m88;
 238                 phy->ops.get_info       = e1000_get_phy_info_m88;
 239                 if (phy->id == I347AT4_E_PHY_ID ||
 240                     phy->id == M88E1112_E_PHY_ID ||
 241                     phy->id == M88E1340M_E_PHY_ID)
 242                         phy->ops.get_cable_length =
 243                                          e1000_get_cable_length_m88_gen2;
 244                 else if (phy->id == M88E1543_E_PHY_ID ||
 245                          phy->id == M88E1512_E_PHY_ID)
 246                         phy->ops.get_cable_length =
 247                                          e1000_get_cable_length_m88_gen2;
 248                 else
 249                         phy->ops.get_cable_length = e1000_get_cable_length_m88;
 250                 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_m88;
 251                 /* Check if this PHY is confgured for media swap. */
 252                 if (phy->id == M88E1112_E_PHY_ID) {
 253                         u16 data;
 254
 255                         ret_val = phy->ops.write_reg(hw,
 256                                                      E1000_M88E1112_PAGE_ADDR,
 257                                                      2);
 258                         if (ret_val)
 259                                 goto out;
 260
 261                         ret_val = phy->ops.read_reg(hw,
 262                                                     E1000_M88E1112_MAC_CTRL_1,
 263                                                     &data);
 264                         if (ret_val)
 265                                 goto out;
 266
 267                         data = (data & E1000_M88E1112_MAC_CTRL_1_MODE_MASK) >>
 268                                E1000_M88E1112_MAC_CTRL_1_MODE_SHIFT;
 269                         if (data == E1000_M88E1112_AUTO_COPPER_SGMII ||
 270                             data == E1000_M88E1112_AUTO_COPPER_BASEX)
 271                                 hw->mac.ops.check_for_link =
 272                                                 e1000_check_for_link_media_swap;
 273                 }
 274                 if (phy->id == M88E1512_E_PHY_ID) {
 275                         ret_val = e1000_initialize_M88E1512_phy(hw);
 276                         if (ret_val)
 277                                 goto out;
 278                 }
 279                 if (phy->id == M88E1543_E_PHY_ID) {
 280                         ret_val = e1000_initialize_M88E1543_phy(hw);
 281                         if (ret_val)
 282                                 goto out;
 283                 }
 284                 break;
 285         case IGP03E1000_E_PHY_ID:
 286         case IGP04E1000_E_PHY_ID:
 287                 phy->type = e1000_phy_igp_3;
 288                 phy->ops.check_polarity = e1000_check_polarity_igp;
 289                 phy->ops.get_info = e1000_get_phy_info_igp;
 290                 phy->ops.get_cable_length = e1000_get_cable_length_igp_2;
 291                 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_igp;
 292                 phy->ops.set_d0_lplu_state = e1000_set_d0_lplu_state_82575;
 293                 phy->ops.set_d3_lplu_state = e1000_set_d3_lplu_state_generic;
 294                 break;
 295         case I82580_I_PHY_ID:
 296         case I350_I_PHY_ID:
 297                 phy->type = e1000_phy_82580;
 298                 phy->ops.check_polarity = e1000_check_polarity_82577;
 299                 phy->ops.force_speed_duplex =
 300                                          e1000_phy_force_speed_duplex_82577;
 301                 phy->ops.get_cable_length = e1000_get_cable_length_82577;
 302                 phy->ops.get_info = e1000_get_phy_info_82577;
 303                 phy->ops.set_d0_lplu_state = e1000_set_d0_lplu_state_82580;
 304                 phy->ops.set_d3_lplu_state = e1000_set_d3_lplu_state_82580;
 305                 break;
 306         case I210_I_PHY_ID:
 307                 phy->type               = e1000_phy_i210;
 308                 phy->ops.check_polarity = e1000_check_polarity_m88;
 309                 phy->ops.get_info       = e1000_get_phy_info_m88;
 310                 phy->ops.get_cable_length = e1000_get_cable_length_m88_gen2;
 311                 phy->ops.set_d0_lplu_state = e1000_set_d0_lplu_state_82580;
 312                 phy->ops.set_d3_lplu_state = e1000_set_d3_lplu_state_82580;
 313                 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_m88;
 314                 break;
 315         case BCM54616_E_PHY_ID:
 316                 phy->type               = e1000_phy_none;
 317                 break;
 318         default:
 319                 ret_val = -E1000_ERR_PHY;
 320                 goto out;
 321         }
 322
 323 out:
 324         return ret_val;
 325 }
 326
 327 /**
 328  *  e1000_init_nvm_params_82575 - Init NVM func ptrs.
 329  *  @hw: pointer to the HW structure
 330  **/
 331 s32 e1000_init_nvm_params_82575(struct e1000_hw *hw)
 332 {
 333         struct e1000_nvm_info *nvm = &hw->nvm;
 334         u32 eecd = E1000_READ_REG(hw, E1000_EECD);
 335         u16 size;
 336
 337         DEBUGFUNC("e1000_init_nvm_params_82575");
 338
 339         size = (u16)((eecd & E1000_EECD_SIZE_EX_MASK) >>
 340                      E1000_EECD_SIZE_EX_SHIFT);
 341         /*
 342          * Added to a constant, "size" becomes the left-shift value
 343          * for setting word_size.
 344          */
 345         size += NVM_WORD_SIZE_BASE_SHIFT;
 346
 347         /* Just in case size is out of range, cap it to the largest
 348          * EEPROM size supported
 349          */
 350         if (size > 15)
 351                 size = 15;
 352
 353         nvm->word_size = 1 << size;
 354         if (hw->mac.type < e1000_i210) {
 355                 nvm->opcode_bits = 8;
 356                 nvm->delay_usec = 1;
 357
 358                 switch (nvm->override) {
 359                 case e1000_nvm_override_spi_large:
 360                         nvm->page_size = 32;
 361                         nvm->address_bits = 16;
 362                         break;
 363                 case e1000_nvm_override_spi_small:
 364                         nvm->page_size = 8;
 365                         nvm->address_bits = 8;
 366                         break;
 367                 default:
 368                         nvm->page_size = eecd & E1000_EECD_ADDR_BITS ? 32 : 8;
 369                         nvm->address_bits = eecd & E1000_EECD_ADDR_BITS ?
 370                                             16 : 8;
 371                         break;
 372                 }
 373                 if (nvm->word_size == (1 << 15))
 374                         nvm->page_size = 128;
 375
 376                 nvm->type = e1000_nvm_eeprom_spi;
 377         } else {
 378                 nvm->type = e1000_nvm_flash_hw;
 379         }
 380
 381         /* Function Pointers */
 382         nvm->ops.acquire = e1000_acquire_nvm_82575;
 383         nvm->ops.release = e1000_release_nvm_82575;
 384         if (nvm->word_size < (1 << 15))
 385                 nvm->ops.read = e1000_read_nvm_eerd;
 386         else
 387                 nvm->ops.read = e1000_read_nvm_spi;
 388
 389         nvm->ops.write = e1000_write_nvm_spi;
 390         nvm->ops.validate = e1000_validate_nvm_checksum_generic;
 391         nvm->ops.update = e1000_update_nvm_checksum_generic;
 392         nvm->ops.valid_led_default = e1000_valid_led_default_82575;
 393
 394         /* override generic family function pointers for specific descendants */
 395         switch (hw->mac.type) {
 396         case e1000_82580:
 397                 nvm->ops.validate = e1000_validate_nvm_checksum_82580;
 398                 nvm->ops.update = e1000_update_nvm_checksum_82580;
 399                 break;
 400         case e1000_i350:
 401         case e1000_i354:
 402                 nvm->ops.validate = e1000_validate_nvm_checksum_i350;
 403                 nvm->ops.update = e1000_update_nvm_checksum_i350;
 404                 break;
 405         default:
 406                 break;
 407         }
 408
 409         return E1000_SUCCESS;
 410 }
 411
 412 /**
 413  *  e1000_init_mac_params_82575 - Init MAC func ptrs.
 414  *  @hw: pointer to the HW structure
 415  **/
 416 STATIC s32 e1000_init_mac_params_82575(struct e1000_hw *hw)
 417 {
 418         struct e1000_mac_info *mac = &hw->mac;
 419         struct e1000_dev_spec_82575 *dev_spec = &hw->dev_spec._82575;
 420
 421         DEBUGFUNC("e1000_init_mac_params_82575");
 422
 423         /* Derives media type */
 424         e1000_get_media_type_82575(hw);
 425         /* Set mta register count */
 426         mac->mta_reg_count = 128;
 427         /* Set uta register count */
 428         mac->uta_reg_count = (hw->mac.type == e1000_82575) ? 0 : 128;
 429         /* Set rar entry count */
 430         mac->rar_entry_count = E1000_RAR_ENTRIES_82575;
 431         if (mac->type == e1000_82576)
 432                 mac->rar_entry_count = E1000_RAR_ENTRIES_82576;
 433         if (mac->type == e1000_82580)
 434                 mac->rar_entry_count = E1000_RAR_ENTRIES_82580;
 435         if (mac->type == e1000_i350 || mac->type == e1000_i354)
 436                 mac->rar_entry_count = E1000_RAR_ENTRIES_I350;
 437
 438         /* Enable EEE default settings for EEE supported devices */
 439         if (mac->type >= e1000_i350)
 440                 dev_spec->eee_disable = false;
 441
 442         /* Allow a single clear of the SW semaphore on I210 and newer */
 443         if (mac->type >= e1000_i210)
 444                 dev_spec->clear_semaphore_once = true;
 445
 446         /* Set if part includes ASF firmware */
 447         mac->asf_firmware_present = true;
 448         /* FWSM register */
 449         mac->has_fwsm = true;
 450         /* ARC supported; valid only if manageability features are enabled. */
 451         mac->arc_subsystem_valid =
 452                 !!(E1000_READ_REG(hw, E1000_FWSM) & E1000_FWSM_MODE_MASK);
 453
 454         /* Function pointers */
 455
 456         /* bus type/speed/width */
 457         mac->ops.get_bus_info = e1000_get_bus_info_pcie_generic;
 458         /* reset */
 459         if (mac->type >= e1000_82580)
 460                 mac->ops.reset_hw = e1000_reset_hw_82580;
 461         else
 462         mac->ops.reset_hw = e1000_reset_hw_82575;
 463         /* hw initialization */
 464         if ((mac->type == e1000_i210) || (mac->type == e1000_i211))
 465                 mac->ops.init_hw = e1000_init_hw_i210;
 466         else
 467         mac->ops.init_hw = e1000_init_hw_82575;
 468         /* link setup */
 469         mac->ops.setup_link = e1000_setup_link_generic;
 470         /* physical interface link setup */
 471         mac->ops.setup_physical_interface =
 472                 (hw->phy.media_type == e1000_media_type_copper)
 473                 ? e1000_setup_copper_link_82575 : e1000_setup_serdes_link_82575;
 474         /* physical interface shutdown */
 475         mac->ops.shutdown_serdes = e1000_shutdown_serdes_link_82575;
 476         /* physical interface power up */
 477         mac->ops.power_up_serdes = e1000_power_up_serdes_link_82575;
 478         /* check for link */
 479         mac->ops.check_for_link = e1000_check_for_link_82575;
 480         /* read mac address */
 481         mac->ops.read_mac_addr = e1000_read_mac_addr_82575;
 482         /* configure collision distance */
 483         mac->ops.config_collision_dist = e1000_config_collision_dist_82575;
 484         /* multicast address update */
 485         mac->ops.update_mc_addr_list = e1000_update_mc_addr_list_generic;
 486         if (hw->mac.type == e1000_i350 || mac->type == e1000_i354) {
 487                 /* writing VFTA */
 488                 mac->ops.write_vfta = e1000_write_vfta_i350;
 489                 /* clearing VFTA */
 490                 mac->ops.clear_vfta = e1000_clear_vfta_i350;
 491         } else {
 492                 /* writing VFTA */
 493                 mac->ops.write_vfta = e1000_write_vfta_generic;
 494                 /* clearing VFTA */
 495                 mac->ops.clear_vfta = e1000_clear_vfta_generic;
 496         }
 497         if (hw->mac.type >= e1000_82580)
 498                 mac->ops.validate_mdi_setting =
 499                                 e1000_validate_mdi_setting_crossover_generic;
 500         /* ID LED init */
 501         mac->ops.id_led_init = e1000_id_led_init_generic;
 502         /* blink LED */
 503         mac->ops.blink_led = e1000_blink_led_generic;
 504         /* setup LED */
 505         mac->ops.setup_led = e1000_setup_led_generic;
 506         /* cleanup LED */
 507         mac->ops.cleanup_led = e1000_cleanup_led_generic;
 508         /* turn on/off LED */
 509         mac->ops.led_on = e1000_led_on_generic;
 510         mac->ops.led_off = e1000_led_off_generic;
 511         /* clear hardware counters */
 512         mac->ops.clear_hw_cntrs = e1000_clear_hw_cntrs_82575;
 513         /* link info */
 514         mac->ops.get_link_up_info = e1000_get_link_up_info_82575;
 515         /* acquire SW_FW sync */
 516         mac->ops.acquire_swfw_sync = e1000_acquire_swfw_sync_82575;
 517         mac->ops.release_swfw_sync = e1000_release_swfw_sync_82575;
 518         if (mac->type >= e1000_i210) {
 519                 mac->ops.acquire_swfw_sync = e1000_acquire_swfw_sync_i210;
 520                 mac->ops.release_swfw_sync = e1000_release_swfw_sync_i210;
 521         }
 522
 523         /* set lan id for port to determine which phy lock to use */
 524         hw->mac.ops.set_lan_id(hw);
 525
 526         return E1000_SUCCESS;
 527 }
 528
 529 /**
 530  *  e1000_init_function_pointers_82575 - Init func ptrs.
 531  *  @hw: pointer to the HW structure
 532  *
 533  *  Called to initialize all function pointers and parameters.
 534  **/
 535 void e1000_init_function_pointers_82575(struct e1000_hw *hw)
 536 {
 537         DEBUGFUNC("e1000_init_function_pointers_82575");
 538
 539         hw->mac.ops.init_params = e1000_init_mac_params_82575;
 540         hw->nvm.ops.init_params = e1000_init_nvm_params_82575;
 541         hw->phy.ops.init_params = e1000_init_phy_params_82575;
 542         hw->mbx.ops.init_params = e1000_init_mbx_params_pf;
 543 }
 544
 545 /**
 546  *  e1000_acquire_phy_82575 - Acquire rights to access PHY
 547  *  @hw: pointer to the HW structure
 548  *
 549  *  Acquire access rights to the correct PHY.
 550  **/
 551 STATIC s32 e1000_acquire_phy_82575(struct e1000_hw *hw)
 552 {
 553         u16 mask = E1000_SWFW_PHY0_SM;
 554
 555         DEBUGFUNC("e1000_acquire_phy_82575");
 556
 557         if (hw->bus.func == E1000_FUNC_1)
 558                 mask = E1000_SWFW_PHY1_SM;
 559         else if (hw->bus.func == E1000_FUNC_2)
 560                 mask = E1000_SWFW_PHY2_SM;
 561         else if (hw->bus.func == E1000_FUNC_3)
 562                 mask = E1000_SWFW_PHY3_SM;
 563
 564         return hw->mac.ops.acquire_swfw_sync(hw, mask);
 565 }
 566
 567 /**
 568  *  e1000_release_phy_82575 - Release rights to access PHY
 569  *  @hw: pointer to the HW structure
 570  *
 571  *  A wrapper to release access rights to the correct PHY.
 572  **/
 573 STATIC void e1000_release_phy_82575(struct e1000_hw *hw)
 574 {
 575         u16 mask = E1000_SWFW_PHY0_SM;
 576
 577         DEBUGFUNC("e1000_release_phy_82575");
 578
 579         if (hw->bus.func == E1000_FUNC_1)
 580                 mask = E1000_SWFW_PHY1_SM;
 581         else if (hw->bus.func == E1000_FUNC_2)
 582                 mask = E1000_SWFW_PHY2_SM;
 583         else if (hw->bus.func == E1000_FUNC_3)
 584                 mask = E1000_SWFW_PHY3_SM;
 585
 586         hw->mac.ops.release_swfw_sync(hw, mask);
 587 }
 588
 589 /**
 590  *  e1000_read_phy_reg_sgmii_82575 - Read PHY register using sgmii
 591  *  @hw: pointer to the HW structure
 592  *  @offset: register offset to be read
 593  *  @data: pointer to the read data
 594  *
 595  *  Reads the PHY register at offset using the serial gigabit media independent
 596  *  interface and stores the retrieved information in data.
 597  **/
 598 STATIC s32 e1000_read_phy_reg_sgmii_82575(struct e1000_hw *hw, u32 offset,
 599                                           u16 *data)
 600 {
 601         s32 ret_val = -E1000_ERR_PARAM;
 602
 603         DEBUGFUNC("e1000_read_phy_reg_sgmii_82575");
 604
 605         if (offset > E1000_MAX_SGMII_PHY_REG_ADDR) {
 606                 DEBUGOUT1("PHY Address %u is out of range\n", offset);
 607                 goto out;
 608         }
 609
 610         ret_val = hw->phy.ops.acquire(hw);
 611         if (ret_val)
 612                 goto out;
 613
 614         ret_val = e1000_read_phy_reg_i2c(hw, offset, data);
 615
 616         hw->phy.ops.release(hw);
 617
 618 out:
 619         return ret_val;
 620 }
 621
 622 /**
 623  *  e1000_write_phy_reg_sgmii_82575 - Write PHY register using sgmii
 624  *  @hw: pointer to the HW structure
 625  *  @offset: register offset to write to
 626  *  @data: data to write at register offset
 627  *
 628  *  Writes the data to PHY register at the offset using the serial gigabit
 629  *  media independent interface.
 630  **/
 631 STATIC s32 e1000_write_phy_reg_sgmii_82575(struct e1000_hw *hw, u32 offset,
 632                                            u16 data)
 633 {
 634         s32 ret_val = -E1000_ERR_PARAM;
 635
 636         DEBUGFUNC("e1000_write_phy_reg_sgmii_82575");
 637
 638         if (offset > E1000_MAX_SGMII_PHY_REG_ADDR) {
 639                 DEBUGOUT1("PHY Address %d is out of range\n", offset);
 640                 goto out;
 641         }
 642
 643         ret_val = hw->phy.ops.acquire(hw);
 644         if (ret_val)
 645                 goto out;
 646
 647         ret_val = e1000_write_phy_reg_i2c(hw, offset, data);
 648
 649         hw->phy.ops.release(hw);
 650
 651 out:
 652         return ret_val;
 653 }
 654
 655 /**
 656  *  e1000_get_phy_id_82575 - Retrieve PHY addr and id
 657  *  @hw: pointer to the HW structure
 658  *
 659  *  Retrieves the PHY address and ID for both PHY's which do and do not use
 660  *  sgmi interface.
 661  **/
 662 STATIC s32 e1000_get_phy_id_82575(struct e1000_hw *hw)
 663 {
 664         struct e1000_phy_info *phy = &hw->phy;
 665         s32  ret_val = E1000_SUCCESS;
 666         u16 phy_id;
 667         u32 ctrl_ext;
 668         u32 mdic;
 669
 670         DEBUGFUNC("e1000_get_phy_id_82575");
 671
 672         /* some i354 devices need an extra read for phy id */
 673         if (hw->mac.type == e1000_i354)
 674                 e1000_get_phy_id(hw);
 675
 676         /*
 677          * For SGMII PHYs, we try the list of possible addresses until
 678          * we find one that works.  For non-SGMII PHYs
 679          * (e.g. integrated copper PHYs), an address of 1 should
 680          * work.  The result of this function should mean phy->phy_addr
 681          * and phy->id are set correctly.
 682          */
 683         if (!e1000_sgmii_active_82575(hw)) {
 684                 phy->addr = 1;
 685                 ret_val = e1000_get_phy_id(hw);
 686                 goto out;
 687         }
 688
 689         if (e1000_sgmii_uses_mdio_82575(hw)) {
 690                 switch (hw->mac.type) {
 691                 case e1000_82575:
 692                 case e1000_82576:
 693                         mdic = E1000_READ_REG(hw, E1000_MDIC);
 694                         mdic &= E1000_MDIC_PHY_MASK;
 695                         phy->addr = mdic >> E1000_MDIC_PHY_SHIFT;
 696                         break;
 697                 case e1000_82580:
 698                 case e1000_i350:
 699                 case e1000_i354:
 700                 case e1000_i210:
 701                 case e1000_i211:
 702                         mdic = E1000_READ_REG(hw, E1000_MDICNFG);
 703                         mdic &= E1000_MDICNFG_PHY_MASK;
 704                         phy->addr = mdic >> E1000_MDICNFG_PHY_SHIFT;
 705                         break;
 706                 default:
 707                         ret_val = -E1000_ERR_PHY;
 708                         goto out;
 709                         break;
 710                 }
 711                 ret_val = e1000_get_phy_id(hw);
 712                 goto out;
 713         }
 714
 715         /* Power on sgmii phy if it is disabled */
 716         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
 717         E1000_WRITE_REG(hw, E1000_CTRL_EXT,
 718                         ctrl_ext & ~E1000_CTRL_EXT_SDP3_DATA);
 719         E1000_WRITE_FLUSH(hw);
 720         msec_delay(300);
 721
 722         /*
 723          * The address field in the I2CCMD register is 3 bits and 0 is invalid.
 724          * Therefore, we need to test 1-7
 725          */
 726         for (phy->addr = 1; phy->addr < 8; phy->addr++) {
 727                 ret_val = e1000_read_phy_reg_sgmii_82575(hw, PHY_ID1, &phy_id);
 728                 if (ret_val == E1000_SUCCESS) {
 729                         DEBUGOUT2("Vendor ID 0x%08X read at address %u\n",
 730                                   phy_id, phy->addr);
 731                         /*
 732                          * At the time of this writing, The M88 part is
 733                          * the only supported SGMII PHY product.
 734                          */
 735                         if (phy_id == M88_VENDOR)
 736                                 break;
 737                 } else {
 738                         DEBUGOUT1("PHY address %u was unreadable\n",
 739                                   phy->addr);
 740                 }
 741         }
 742
 743         /* A valid PHY type couldn't be found. */
 744         if (phy->addr == 8) {
 745                 phy->addr = 0;
 746                 ret_val = -E1000_ERR_PHY;
 747         } else {
 748                 ret_val = e1000_get_phy_id(hw);
 749         }
 750
 751         /* restore previous sfp cage power state */
 752         E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
 753
 754 out:
 755         return ret_val;
 756 }
 757
 758 /**
 759  *  e1000_phy_hw_reset_sgmii_82575 - Performs a PHY reset
 760  *  @hw: pointer to the HW structure
 761  *
 762  *  Resets the PHY using the serial gigabit media independent interface.
 763  **/
 764 STATIC s32 e1000_phy_hw_reset_sgmii_82575(struct e1000_hw *hw)
 765 {
 766         s32 ret_val = E1000_SUCCESS;
 767         struct e1000_phy_info *phy = &hw->phy;
 768
 769         DEBUGFUNC("e1000_phy_hw_reset_sgmii_82575");
 770
 771         /*
 772          * This isn't a true "hard" reset, but is the only reset
 773          * available to us at this time.
 774          */
 775
 776         DEBUGOUT("Soft resetting SGMII attached PHY...\n");
 777
 778         if (!(hw->phy.ops.write_reg))
 779                 goto out;
 780
 781         /*
 782          * SFP documentation requires the following to configure the SPF module
 783          * to work on SGMII.  No further documentation is given.
 784          */
 785         ret_val = hw->phy.ops.write_reg(hw, 0x1B, 0x8084);
 786         if (ret_val)
 787                 goto out;
 788
 789         ret_val = hw->phy.ops.commit(hw);
 790         if (ret_val)
 791                 goto out;
 792
 793         if (phy->id == M88E1512_E_PHY_ID)
 794                 ret_val = e1000_initialize_M88E1512_phy(hw);
 795 out:
 796         return ret_val;
 797 }
 798
 799 /**
 800  *  e1000_set_d0_lplu_state_82575 - Set Low Power Linkup D0 state
 801  *  @hw: pointer to the HW structure
 802  *  @active: true to enable LPLU, false to disable
 803  *
 804  *  Sets the LPLU D0 state according to the active flag.  When
 805  *  activating LPLU this function also disables smart speed
 806  *  and vice versa.  LPLU will not be activated unless the
 807  *  device autonegotiation advertisement meets standards of
 808  *  either 10 or 10/100 or 10/100/1000 at all duplexes.
 809  *  This is a function pointer entry point only called by
 810  *  PHY setup routines.
 811  **/
 812 STATIC s32 e1000_set_d0_lplu_state_82575(struct e1000_hw *hw, bool active)
 813 {
 814         struct e1000_phy_info *phy = &hw->phy;
 815         s32 ret_val = E1000_SUCCESS;
 816         u16 data;
 817
 818         DEBUGFUNC("e1000_set_d0_lplu_state_82575");
 819
 820         if (!(hw->phy.ops.read_reg))
 821                 goto out;
 822
 823         ret_val = phy->ops.read_reg(hw, IGP02E1000_PHY_POWER_MGMT, &data);
 824         if (ret_val)
 825                 goto out;
 826
 827         if (active) {
 828                 data |= IGP02E1000_PM_D0_LPLU;
 829                 ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT,
 830                                              data);
 831                 if (ret_val)
 832                         goto out;
 833
 834                 /* When LPLU is enabled, we should disable SmartSpeed */
 835                 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
 836                                             &data);
 837                 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
 838                 ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
 839                                              data);
 840                 if (ret_val)
 841                         goto out;
 842         } else {
 843                 data &= ~IGP02E1000_PM_D0_LPLU;
 844                 ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT,
 845                                              data);
 846                 /*
 847                  * LPLU and SmartSpeed are mutually exclusive.  LPLU is used
 848                  * during Dx states where the power conservation is most
 849                  * important.  During driver activity we should enable
 850                  * SmartSpeed, so performance is maintained.
 851                  */
 852                 if (phy->smart_speed == e1000_smart_speed_on) {
 853                         ret_val = phy->ops.read_reg(hw,
 854                                                     IGP01E1000_PHY_PORT_CONFIG,
 855                                                     &data);
 856                         if (ret_val)
 857                                 goto out;
 858
 859                         data |= IGP01E1000_PSCFR_SMART_SPEED;
 860                         ret_val = phy->ops.write_reg(hw,
 861                                                      IGP01E1000_PHY_PORT_CONFIG,
 862                                                      data);
 863                         if (ret_val)
 864                                 goto out;
 865                 } else if (phy->smart_speed == e1000_smart_speed_off) {
 866                         ret_val = phy->ops.read_reg(hw,
 867                                                     IGP01E1000_PHY_PORT_CONFIG,
 868                                                     &data);
 869                         if (ret_val)
 870                                 goto out;
 871
 872                         data &= ~IGP01E1000_PSCFR_SMART_SPEED;
 873                         ret_val = phy->ops.write_reg(hw,
 874                                                      IGP01E1000_PHY_PORT_CONFIG,
 875                                                      data);
 876                         if (ret_val)
 877                                 goto out;
 878                 }
 879         }
 880
 881 out:
 882         return ret_val;
 883 }
 884
 885 /**
 886  *  e1000_set_d0_lplu_state_82580 - Set Low Power Linkup D0 state
 887  *  @hw: pointer to the HW structure
 888  *  @active: true to enable LPLU, false to disable
 889  *
 890  *  Sets the LPLU D0 state according to the active flag.  When
 891  *  activating LPLU this function also disables smart speed
 892  *  and vice versa.  LPLU will not be activated unless the
 893  *  device autonegotiation advertisement meets standards of
 894  *  either 10 or 10/100 or 10/100/1000 at all duplexes.
 895  *  This is a function pointer entry point only called by
 896  *  PHY setup routines.
 897  **/
 898 STATIC s32 e1000_set_d0_lplu_state_82580(struct e1000_hw *hw, bool active)
 899 {
 900         struct e1000_phy_info *phy = &hw->phy;
 901         u32 data;
 902
 903         DEBUGFUNC("e1000_set_d0_lplu_state_82580");
 904
 905         data = E1000_READ_REG(hw, E1000_82580_PHY_POWER_MGMT);
 906
 907         if (active) {
 908                 data |= E1000_82580_PM_D0_LPLU;
 909
 910                 /* When LPLU is enabled, we should disable SmartSpeed */
 911                 data &= ~E1000_82580_PM_SPD;
 912         } else {
 913                 data &= ~E1000_82580_PM_D0_LPLU;
 914
 915                 /*
 916                  * LPLU and SmartSpeed are mutually exclusive.  LPLU is used
 917                  * during Dx states where the power conservation is most
 918                  * important.  During driver activity we should enable
 919                  * SmartSpeed, so performance is maintained.
 920                  */
 921                 if (phy->smart_speed == e1000_smart_speed_on)
 922                         data |= E1000_82580_PM_SPD;
 923                 else if (phy->smart_speed == e1000_smart_speed_off)
 924                         data &= ~E1000_82580_PM_SPD;
 925         }
 926
 927         E1000_WRITE_REG(hw, E1000_82580_PHY_POWER_MGMT, data);
 928         return E1000_SUCCESS;
 929 }
 930
 931 /**
 932  *  e1000_set_d3_lplu_state_82580 - Sets low power link up state for D3
 933  *  @hw: pointer to the HW structure
 934  *  @active: boolean used to enable/disable lplu
 935  *
 936  *  Success returns 0, Failure returns 1
 937  *
 938  *  The low power link up (lplu) state is set to the power management level D3
 939  *  and SmartSpeed is disabled when active is true, else clear lplu for D3
 940  *  and enable Smartspeed.  LPLU and Smartspeed are mutually exclusive.  LPLU
 941  *  is used during Dx states where the power conservation is most important.
 942  *  During driver activity, SmartSpeed should be enabled so performance is
 943  *  maintained.
 944  **/
 945 s32 e1000_set_d3_lplu_state_82580(struct e1000_hw *hw, bool active)
 946 {
 947         struct e1000_phy_info *phy = &hw->phy;
 948         u32 data;
 949
 950         DEBUGFUNC("e1000_set_d3_lplu_state_82580");
 951
 952         data = E1000_READ_REG(hw, E1000_82580_PHY_POWER_MGMT);
 953
 954         if (!active) {
 955                 data &= ~E1000_82580_PM_D3_LPLU;
 956                 /*
 957                  * LPLU and SmartSpeed are mutually exclusive.  LPLU is used
 958                  * during Dx states where the power conservation is most
 959                  * important.  During driver activity we should enable
 960                  * SmartSpeed, so performance is maintained.
 961                  */
 962                 if (phy->smart_speed == e1000_smart_speed_on)
 963                         data |= E1000_82580_PM_SPD;
 964                 else if (phy->smart_speed == e1000_smart_speed_off)
 965                         data &= ~E1000_82580_PM_SPD;
 966         } else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) ||
 967                    (phy->autoneg_advertised == E1000_ALL_NOT_GIG) ||
 968                    (phy->autoneg_advertised == E1000_ALL_10_SPEED)) {
 969                 data |= E1000_82580_PM_D3_LPLU;
 970                 /* When LPLU is enabled, we should disable SmartSpeed */
 971                 data &= ~E1000_82580_PM_SPD;
 972         }
 973
 974         E1000_WRITE_REG(hw, E1000_82580_PHY_POWER_MGMT, data);
 975         return E1000_SUCCESS;
 976 }
 977
 978 /**
 979  *  e1000_acquire_nvm_82575 - Request for access to EEPROM
 980  *  @hw: pointer to the HW structure
 981  *
 982  *  Acquire the necessary semaphores for exclusive access to the EEPROM.
 983  *  Set the EEPROM access request bit and wait for EEPROM access grant bit.
 984  *  Return successful if access grant bit set, else clear the request for
 985  *  EEPROM access and return -E1000_ERR_NVM (-1).
 986  **/
 987 STATIC s32 e1000_acquire_nvm_82575(struct e1000_hw *hw)
 988 {
 989         s32 ret_val = E1000_SUCCESS;
 990
 991         DEBUGFUNC("e1000_acquire_nvm_82575");
 992
 993         ret_val = e1000_acquire_swfw_sync_82575(hw, E1000_SWFW_EEP_SM);
 994         if (ret_val)
 995                 goto out;
 996
 997         /*
 998          * Check if there is some access
 999          * error this access may hook on
1000          */
1001         if (hw->mac.type == e1000_i350) {
1002                 u32 eecd = E1000_READ_REG(hw, E1000_EECD);
1003                 if (eecd & (E1000_EECD_BLOCKED | E1000_EECD_ABORT |
1004                     E1000_EECD_TIMEOUT)) {
1005                         /* Clear all access error flags */
1006                         E1000_WRITE_REG(hw, E1000_EECD, eecd |
1007                                         E1000_EECD_ERROR_CLR);
1008                         DEBUGOUT("Nvm bit banging access error detected and cleared.\n");
1009                 }
1010         }
1011
1012         if (hw->mac.type == e1000_82580) {
1013                 u32 eecd = E1000_READ_REG(hw, E1000_EECD);
1014                 if (eecd & E1000_EECD_BLOCKED) {
1015                         /* Clear access error flag */
1016                         E1000_WRITE_REG(hw, E1000_EECD, eecd |
1017                                         E1000_EECD_BLOCKED);
1018                         DEBUGOUT("Nvm bit banging access error detected and cleared.\n");
1019                 }
1020         }
1021
1022         ret_val = e1000_acquire_nvm_generic(hw);
1023         if (ret_val)
1024                 e1000_release_swfw_sync_82575(hw, E1000_SWFW_EEP_SM);
1025
1026 out:
1027         return ret_val;
1028 }
1029
1030 /**
1031  *  e1000_release_nvm_82575 - Release exclusive access to EEPROM
1032  *  @hw: pointer to the HW structure
1033  *
1034  *  Stop any current commands to the EEPROM and clear the EEPROM request bit,
1035  *  then release the semaphores acquired.
1036  **/
1037 STATIC void e1000_release_nvm_82575(struct e1000_hw *hw)
1038 {
1039         DEBUGFUNC("e1000_release_nvm_82575");
1040
1041         e1000_release_nvm_generic(hw);
1042
1043         e1000_release_swfw_sync_82575(hw, E1000_SWFW_EEP_SM);
1044 }
1045
1046 /**
1047  *  e1000_acquire_swfw_sync_82575 - Acquire SW/FW semaphore
1048  *  @hw: pointer to the HW structure
1049  *  @mask: specifies which semaphore to acquire
1050  *
1051  *  Acquire the SW/FW semaphore to access the PHY or NVM.  The mask
1052  *  will also specify which port we're acquiring the lock for.
1053  **/
1054 STATIC s32 e1000_acquire_swfw_sync_82575(struct e1000_hw *hw, u16 mask)
1055 {
1056         u32 swfw_sync;
1057         u32 swmask = mask;
1058         u32 fwmask = mask << 16;
1059         s32 ret_val = E1000_SUCCESS;
1060         s32 i = 0, timeout = 200;
1061
1062         DEBUGFUNC("e1000_acquire_swfw_sync_82575");
1063
1064         while (i < timeout) {
1065                 if (e1000_get_hw_semaphore_generic(hw)) {
1066                         ret_val = -E1000_ERR_SWFW_SYNC;
1067                         goto out;
1068                 }
1069
1070                 swfw_sync = E1000_READ_REG(hw, E1000_SW_FW_SYNC);
1071                 if (!(swfw_sync & (fwmask | swmask)))
1072                         break;
1073
1074                 /*
1075                  * Firmware currently using resource (fwmask)
1076                  * or other software thread using resource (swmask)
1077                  */
1078                 e1000_put_hw_semaphore_generic(hw);
1079                 msec_delay_irq(5);
1080                 i++;
1081         }
1082
1083         if (i == timeout) {
1084                 DEBUGOUT("Driver can't access resource, SW_FW_SYNC timeout.\n");
1085                 ret_val = -E1000_ERR_SWFW_SYNC;
1086                 goto out;
1087         }
1088
1089         swfw_sync |= swmask;
1090         E1000_WRITE_REG(hw, E1000_SW_FW_SYNC, swfw_sync);
1091
1092         e1000_put_hw_semaphore_generic(hw);
1093
1094 out:
1095         return ret_val;
1096 }
1097
1098 /**
1099  *  e1000_release_swfw_sync_82575 - Release SW/FW semaphore
1100  *  @hw: pointer to the HW structure
1101  *  @mask: specifies which semaphore to acquire
1102  *
1103  *  Release the SW/FW semaphore used to access the PHY or NVM.  The mask
1104  *  will also specify which port we're releasing the lock for.
1105  **/
1106 STATIC void e1000_release_swfw_sync_82575(struct e1000_hw *hw, u16 mask)
1107 {
1108         u32 swfw_sync;
1109
1110         DEBUGFUNC("e1000_release_swfw_sync_82575");
1111
1112         while (e1000_get_hw_semaphore_generic(hw) != E1000_SUCCESS)
1113                 ; /* Empty */
1114
1115         swfw_sync = E1000_READ_REG(hw, E1000_SW_FW_SYNC);
1116         swfw_sync &= ~mask;
1117         E1000_WRITE_REG(hw, E1000_SW_FW_SYNC, swfw_sync);
1118
1119         e1000_put_hw_semaphore_generic(hw);
1120 }
1121
1122 /**
1123  *  e1000_get_cfg_done_82575 - Read config done bit
1124  *  @hw: pointer to the HW structure
1125  *
1126  *  Read the management control register for the config done bit for
1127  *  completion status.  NOTE: silicon which is EEPROM-less will fail trying
1128  *  to read the config done bit, so an error is *ONLY* logged and returns
1129  *  E1000_SUCCESS.  If we were to return with error, EEPROM-less silicon
1130  *  would not be able to be reset or change link.
1131  **/
1132 STATIC s32 e1000_get_cfg_done_82575(struct e1000_hw *hw)
1133 {
1134         s32 timeout = PHY_CFG_TIMEOUT;
1135         u32 mask = E1000_NVM_CFG_DONE_PORT_0;
1136
1137         DEBUGFUNC("e1000_get_cfg_done_82575");
1138
1139         if (hw->bus.func == E1000_FUNC_1)
1140                 mask = E1000_NVM_CFG_DONE_PORT_1;
1141         else if (hw->bus.func == E1000_FUNC_2)
1142                 mask = E1000_NVM_CFG_DONE_PORT_2;
1143         else if (hw->bus.func == E1000_FUNC_3)
1144                 mask = E1000_NVM_CFG_DONE_PORT_3;
1145         while (timeout) {
1146                 if (E1000_READ_REG(hw, E1000_EEMNGCTL) & mask)
1147                         break;
1148                 msec_delay(1);
1149                 timeout--;
1150         }
1151         if (!timeout)
1152                 DEBUGOUT("MNG configuration cycle has not completed.\n");
1153
1154         /* If EEPROM is not marked present, init the PHY manually */
1155         if (!(E1000_READ_REG(hw, E1000_EECD) & E1000_EECD_PRES) &&
1156             (hw->phy.type == e1000_phy_igp_3))
1157                 e1000_phy_init_script_igp3(hw);
1158
1159         return E1000_SUCCESS;
1160 }
1161
1162 /**
1163  *  e1000_get_link_up_info_82575 - Get link speed/duplex info
1164  *  @hw: pointer to the HW structure
1165  *  @speed: stores the current speed
1166  *  @duplex: stores the current duplex
1167  *
1168  *  This is a wrapper function, if using the serial gigabit media independent
1169  *  interface, use PCS to retrieve the link speed and duplex information.
1170  *  Otherwise, use the generic function to get the link speed and duplex info.
1171  **/
1172 STATIC s32 e1000_get_link_up_info_82575(struct e1000_hw *hw, u16 *speed,
1173                                         u16 *duplex)
1174 {
1175         s32 ret_val;
1176
1177         DEBUGFUNC("e1000_get_link_up_info_82575");
1178
1179         if (hw->phy.media_type != e1000_media_type_copper)
1180                 ret_val = e1000_get_pcs_speed_and_duplex_82575(hw, speed,
1181                                                                duplex);
1182         else
1183                 ret_val = e1000_get_speed_and_duplex_copper_generic(hw, speed,
1184                                                                     duplex);
1185
1186         return ret_val;
1187 }
1188
1189 /**
1190  *  e1000_check_for_link_82575 - Check for link
1191  *  @hw: pointer to the HW structure
1192  *
1193  *  If sgmii is enabled, then use the pcs register to determine link, otherwise
1194  *  use the generic interface for determining link.
1195  **/
1196 STATIC s32 e1000_check_for_link_82575(struct e1000_hw *hw)
1197 {
1198         s32 ret_val;
1199         u16 speed, duplex;
1200
1201         DEBUGFUNC("e1000_check_for_link_82575");
1202
1203         if (hw->phy.media_type != e1000_media_type_copper) {
1204                 ret_val = e1000_get_pcs_speed_and_duplex_82575(hw, &speed,
1205                                                                &duplex);
1206                 /*
1207                  * Use this flag to determine if link needs to be checked or
1208                  * not.  If we have link clear the flag so that we do not
1209                  * continue to check for link.
1210                  */
1211                 hw->mac.get_link_status = !hw->mac.serdes_has_link;
1212
1213                 /*
1214                  * Configure Flow Control now that Auto-Neg has completed.
1215                  * First, we need to restore the desired flow control
1216                  * settings because we may have had to re-autoneg with a
1217                  * different link partner.
1218                  */
1219                 ret_val = e1000_config_fc_after_link_up_generic(hw);
1220                 if (ret_val)
1221                         DEBUGOUT("Error configuring flow control\n");
1222         } else {
1223                 ret_val = e1000_check_for_copper_link_generic(hw);
1224         }
1225
1226         return ret_val;
1227 }
1228
1229 /**
1230  *  e1000_check_for_link_media_swap - Check which M88E1112 interface linked
1231  *  @hw: pointer to the HW structure
1232  *
1233  *  Poll the M88E1112 interfaces to see which interface achieved link.
1234  */
1235 STATIC s32 e1000_check_for_link_media_swap(struct e1000_hw *hw)
1236 {
1237         struct e1000_phy_info *phy = &hw->phy;
1238         s32 ret_val;
1239         u16 data;
1240         u8 port = 0;
1241
1242         DEBUGFUNC("e1000_check_for_link_media_swap");
1243
1244         /* Check for copper. */
1245         ret_val = phy->ops.write_reg(hw, E1000_M88E1112_PAGE_ADDR, 0);
1246         if (ret_val)
1247                 return ret_val;
1248
1249         ret_val = phy->ops.read_reg(hw, E1000_M88E1112_STATUS, &data);
1250         if (ret_val)
1251                 return ret_val;
1252
1253         if (data & E1000_M88E1112_STATUS_LINK)
1254                 port = E1000_MEDIA_PORT_COPPER;
1255
1256         /* Check for other. */
1257         ret_val = phy->ops.write_reg(hw, E1000_M88E1112_PAGE_ADDR, 1);
1258         if (ret_val)
1259                 return ret_val;
1260
1261         ret_val = phy->ops.read_reg(hw, E1000_M88E1112_STATUS, &data);
1262         if (ret_val)
1263                 return ret_val;
1264
1265         if (data & E1000_M88E1112_STATUS_LINK)
1266                 port = E1000_MEDIA_PORT_OTHER;
1267
1268         /* Determine if a swap needs to happen. */
1269         if (port && (hw->dev_spec._82575.media_port != port)) {
1270                 hw->dev_spec._82575.media_port = port;
1271                 hw->dev_spec._82575.media_changed = true;
1272         }
1273
1274         if (port == E1000_MEDIA_PORT_COPPER) {
1275                 /* reset page to 0 */
1276                 ret_val = phy->ops.write_reg(hw, E1000_M88E1112_PAGE_ADDR, 0);
1277                 if (ret_val)
1278                         return ret_val;
1279                 e1000_check_for_link_82575(hw);
1280         } else {
1281                 e1000_check_for_link_82575(hw);
1282                 /* reset page to 0 */
1283                 ret_val = phy->ops.write_reg(hw, E1000_M88E1112_PAGE_ADDR, 0);
1284                 if (ret_val)
1285                         return ret_val;
1286         }
1287
1288         return E1000_SUCCESS;
1289 }
1290
1291 /**
1292  *  e1000_power_up_serdes_link_82575 - Power up the serdes link after shutdown
1293  *  @hw: pointer to the HW structure
1294  **/
1295 STATIC void e1000_power_up_serdes_link_82575(struct e1000_hw *hw)
1296 {
1297         u32 reg;
1298
1299         DEBUGFUNC("e1000_power_up_serdes_link_82575");
1300
1301         if ((hw->phy.media_type != e1000_media_type_internal_serdes) &&
1302             !e1000_sgmii_active_82575(hw))
1303                 return;
1304
1305         /* Enable PCS to turn on link */
1306         reg = E1000_READ_REG(hw, E1000_PCS_CFG0);
1307         reg |= E1000_PCS_CFG_PCS_EN;
1308         E1000_WRITE_REG(hw, E1000_PCS_CFG0, reg);
1309
1310         /* Power up the laser */
1311         reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
1312         reg &= ~E1000_CTRL_EXT_SDP3_DATA;
1313         E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg);
1314
1315         /* flush the write to verify completion */
1316         E1000_WRITE_FLUSH(hw);
1317         msec_delay(1);
1318 }
1319
1320 /**
1321  *  e1000_get_pcs_speed_and_duplex_82575 - Retrieve current speed/duplex
1322  *  @hw: pointer to the HW structure
1323  *  @speed: stores the current speed
1324  *  @duplex: stores the current duplex
1325  *
1326  *  Using the physical coding sub-layer (PCS), retrieve the current speed and
1327  *  duplex, then store the values in the pointers provided.
1328  **/
1329 STATIC s32 e1000_get_pcs_speed_and_duplex_82575(struct e1000_hw *hw,
1330                                                 u16 *speed, u16 *duplex)
1331 {
1332         struct e1000_mac_info *mac = &hw->mac;
1333         u32 pcs;
1334         u32 status;
1335
1336         DEBUGFUNC("e1000_get_pcs_speed_and_duplex_82575");
1337
1338         /*
1339          * Read the PCS Status register for link state. For non-copper mode,
1340          * the status register is not accurate. The PCS status register is
1341          * used instead.
1342          */
1343         pcs = E1000_READ_REG(hw, E1000_PCS_LSTAT);
1344
1345         /*
1346          * The link up bit determines when link is up on autoneg.
1347          */
1348         if (pcs & E1000_PCS_LSTS_LINK_OK) {
1349                 mac->serdes_has_link = true;
1350
1351                 /* Detect and store PCS speed */
1352                 if (pcs & E1000_PCS_LSTS_SPEED_1000)
1353                         *speed = SPEED_1000;
1354                 else if (pcs & E1000_PCS_LSTS_SPEED_100)
1355                         *speed = SPEED_100;
1356                 else
1357                         *speed = SPEED_10;
1358
1359                 /* Detect and store PCS duplex */
1360                 if (pcs & E1000_PCS_LSTS_DUPLEX_FULL)
1361                         *duplex = FULL_DUPLEX;
1362                 else
1363                         *duplex = HALF_DUPLEX;
1364
1365                 /* Check if it is an I354 2.5Gb backplane connection. */
1366                 if (mac->type == e1000_i354) {
1367                         status = E1000_READ_REG(hw, E1000_STATUS);
1368                         if ((status & E1000_STATUS_2P5_SKU) &&
1369                             !(status & E1000_STATUS_2P5_SKU_OVER)) {
1370                                 *speed = SPEED_2500;
1371                                 *duplex = FULL_DUPLEX;
1372                                 DEBUGOUT("2500 Mbs, ");
1373                                 DEBUGOUT("Full Duplex\n");
1374                         }
1375                 }
1376
1377         } else {
1378                 mac->serdes_has_link = false;
1379                 *speed = 0;
1380                 *duplex = 0;
1381         }
1382
1383         return E1000_SUCCESS;
1384 }
1385
1386 /**
1387  *  e1000_shutdown_serdes_link_82575 - Remove link during power down
1388  *  @hw: pointer to the HW structure
1389  *
1390  *  In the case of serdes shut down sfp and PCS on driver unload
1391  *  when management pass thru is not enabled.
1392  **/
1393 void e1000_shutdown_serdes_link_82575(struct e1000_hw *hw)
1394 {
1395         u32 reg;
1396
1397         DEBUGFUNC("e1000_shutdown_serdes_link_82575");
1398
1399         if ((hw->phy.media_type != e1000_media_type_internal_serdes) &&
1400             !e1000_sgmii_active_82575(hw))
1401                 return;
1402
1403         if (!e1000_enable_mng_pass_thru(hw)) {
1404                 /* Disable PCS to turn off link */
1405                 reg = E1000_READ_REG(hw, E1000_PCS_CFG0);
1406                 reg &= ~E1000_PCS_CFG_PCS_EN;
1407                 E1000_WRITE_REG(hw, E1000_PCS_CFG0, reg);
1408
1409                 /* shutdown the laser */
1410                 reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
1411                 reg |= E1000_CTRL_EXT_SDP3_DATA;
1412                 E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg);
1413
1414                 /* flush the write to verify completion */
1415                 E1000_WRITE_FLUSH(hw);
1416                 msec_delay(1);
1417         }
1418
1419         return;
1420 }
1421
1422 /**
1423  *  e1000_reset_hw_82575 - Reset hardware
1424  *  @hw: pointer to the HW structure
1425  *
1426  *  This resets the hardware into a known state.
1427  **/
1428 STATIC s32 e1000_reset_hw_82575(struct e1000_hw *hw)
1429 {
1430         u32 ctrl;
1431         s32 ret_val;
1432
1433         DEBUGFUNC("e1000_reset_hw_82575");
1434
1435         /*
1436          * Prevent the PCI-E bus from sticking if there is no TLP connection
1437          * on the last TLP read/write transaction when MAC is reset.
1438          */
1439         ret_val = e1000_disable_pcie_master_generic(hw);
1440         if (ret_val)
1441                 DEBUGOUT("PCI-E Master disable polling has failed.\n");
1442
1443         /* set the completion timeout for interface */
1444         ret_val = e1000_set_pcie_completion_timeout(hw);
1445         if (ret_val)
1446                 DEBUGOUT("PCI-E Set completion timeout has failed.\n");
1447
1448         DEBUGOUT("Masking off all interrupts\n");
1449         E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff);
1450
1451         E1000_WRITE_REG(hw, E1000_RCTL, 0);
1452         E1000_WRITE_REG(hw, E1000_TCTL, E1000_TCTL_PSP);
1453         E1000_WRITE_FLUSH(hw);
1454
1455         msec_delay(10);
1456
1457         ctrl = E1000_READ_REG(hw, E1000_CTRL);
1458
1459         DEBUGOUT("Issuing a global reset to MAC\n");
1460         E1000_WRITE_REG(hw, E1000_CTRL, ctrl | E1000_CTRL_RST);
1461
1462         ret_val = e1000_get_auto_rd_done_generic(hw);
1463         if (ret_val) {
1464                 /*
1465                  * When auto config read does not complete, do not
1466                  * return with an error. This can happen in situations
1467                  * where there is no eeprom and prevents getting link.
1468                  */
1469                 DEBUGOUT("Auto Read Done did not complete\n");
1470         }
1471
1472         /* If EEPROM is not present, run manual init scripts */
1473         if (!(E1000_READ_REG(hw, E1000_EECD) & E1000_EECD_PRES))
1474                 e1000_reset_init_script_82575(hw);
1475
1476         /* Clear any pending interrupt events. */
1477         E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff);
1478         E1000_READ_REG(hw, E1000_ICR);
1479
1480         /* Install any alternate MAC address into RAR0 */
1481         ret_val = e1000_check_alt_mac_addr_generic(hw);
1482
1483         return ret_val;
1484 }
1485
1486 /**
1487  *  e1000_init_hw_82575 - Initialize hardware
1488  *  @hw: pointer to the HW structure
1489  *
1490  *  This inits the hardware readying it for operation.
1491  **/
1492 s32 e1000_init_hw_82575(struct e1000_hw *hw)
1493 {
1494         struct e1000_mac_info *mac = &hw->mac;
1495         s32 ret_val;
1496         u16 i, rar_count = mac->rar_entry_count;
1497
1498         DEBUGFUNC("e1000_init_hw_82575");
1499
1500         /* Initialize identification LED */
1501         ret_val = mac->ops.id_led_init(hw);
1502         if (ret_val) {
1503                 DEBUGOUT("Error initializing identification LED\n");
1504                 /* This is not fatal and we should not stop init due to this */
1505         }
1506
1507         /* Disabling VLAN filtering */
1508         DEBUGOUT("Initializing the IEEE VLAN\n");
1509         mac->ops.clear_vfta(hw);
1510
1511         /* Setup the receive address */
1512         e1000_init_rx_addrs_generic(hw, rar_count);
1513
1514         /* Zero out the Multicast HASH table */
1515         DEBUGOUT("Zeroing the MTA\n");
1516         for (i = 0; i < mac->mta_reg_count; i++)
1517                 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0);
1518
1519         /* Zero out the Unicast HASH table */
1520         DEBUGOUT("Zeroing the UTA\n");
1521         for (i = 0; i < mac->uta_reg_count; i++)
1522                 E1000_WRITE_REG_ARRAY(hw, E1000_UTA, i, 0);
1523
1524         /* Setup link and flow control */
1525         ret_val = mac->ops.setup_link(hw);
1526
1527         /* Set the default MTU size */
1528         hw->dev_spec._82575.mtu = 1500;
1529
1530         /*
1531          * Clear all of the statistics registers (clear on read).  It is
1532          * important that we do this after we have tried to establish link
1533          * because the symbol error count will increment wildly if there
1534          * is no link.
1535          */
1536         e1000_clear_hw_cntrs_82575(hw);
1537
1538         return ret_val;
1539 }
1540
1541 /**
1542  *  e1000_setup_copper_link_82575 - Configure copper link settings
1543  *  @hw: pointer to the HW structure
1544  *
1545  *  Configures the link for auto-neg or forced speed and duplex.  Then we check
1546  *  for link, once link is established calls to configure collision distance
1547  *  and flow control are called.
1548  **/
1549 STATIC s32 e1000_setup_copper_link_82575(struct e1000_hw *hw)
1550 {
1551         u32 ctrl;
1552         s32 ret_val;
1553         u32 phpm_reg;
1554
1555         DEBUGFUNC("e1000_setup_copper_link_82575");
1556
1557         ctrl = E1000_READ_REG(hw, E1000_CTRL);
1558         ctrl |= E1000_CTRL_SLU;
1559         ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
1560         E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
1561
1562         /* Clear Go Link Disconnect bit on supported devices */
1563         switch (hw->mac.type) {
1564         case e1000_82580:
1565         case e1000_i350:
1566         case e1000_i210:
1567         case e1000_i211:
1568                 phpm_reg = E1000_READ_REG(hw, E1000_82580_PHY_POWER_MGMT);
1569                 phpm_reg &= ~E1000_82580_PM_GO_LINKD;
1570                 E1000_WRITE_REG(hw, E1000_82580_PHY_POWER_MGMT, phpm_reg);
1571                 break;
1572         default:
1573                 break;
1574         }
1575
1576         ret_val = e1000_setup_serdes_link_82575(hw);
1577         if (ret_val)
1578                 goto out;
1579
1580         if (e1000_sgmii_active_82575(hw)) {
1581                 /* allow time for SFP cage time to power up phy */
1582                 msec_delay(300);
1583
1584                 ret_val = hw->phy.ops.reset(hw);
1585                 if (ret_val) {
1586                         DEBUGOUT("Error resetting the PHY.\n");
1587                         goto out;
1588                 }
1589         }
1590         switch (hw->phy.type) {
1591         case e1000_phy_i210:
1592         case e1000_phy_m88:
1593                 switch (hw->phy.id) {
1594                 case I347AT4_E_PHY_ID:
1595                 case M88E1112_E_PHY_ID:
1596                 case M88E1340M_E_PHY_ID:
1597                 case M88E1543_E_PHY_ID:
1598                 case M88E1512_E_PHY_ID:
1599                 case I210_I_PHY_ID:
1600                         ret_val = e1000_copper_link_setup_m88_gen2(hw);
1601                         break;
1602                 default:
1603                         ret_val = e1000_copper_link_setup_m88(hw);
1604                         break;
1605                 }
1606                 break;
1607         case e1000_phy_igp_3:
1608                 ret_val = e1000_copper_link_setup_igp(hw);
1609                 break;
1610         case e1000_phy_82580:
1611                 ret_val = e1000_copper_link_setup_82577(hw);
1612                 break;
1613         case e1000_phy_none:
1614                 break;
1615         default:
1616                 ret_val = -E1000_ERR_PHY;
1617                 break;
1618         }
1619
1620         if (ret_val)
1621                 goto out;
1622
1623         ret_val = e1000_setup_copper_link_generic(hw);
1624 out:
1625         return ret_val;
1626 }
1627
1628 /**
1629  *  e1000_setup_serdes_link_82575 - Setup link for serdes
1630  *  @hw: pointer to the HW structure
1631  *
1632  *  Configure the physical coding sub-layer (PCS) link.  The PCS link is
1633  *  used on copper connections where the serialized gigabit media independent
1634  *  interface (sgmii), or serdes fiber is being used.  Configures the link
1635  *  for auto-negotiation or forces speed/duplex.
1636  **/
1637 STATIC s32 e1000_setup_serdes_link_82575(struct e1000_hw *hw)
1638 {
1639         u32 ctrl_ext, ctrl_reg, reg, anadv_reg;
1640         bool pcs_autoneg;
1641         s32 ret_val = E1000_SUCCESS;
1642         u16 data;
1643
1644         DEBUGFUNC("e1000_setup_serdes_link_82575");
1645
1646         if ((hw->phy.media_type != e1000_media_type_internal_serdes) &&
1647             !e1000_sgmii_active_82575(hw))
1648                 return ret_val;
1649
1650         /*
1651          * On the 82575, SerDes loopback mode persists until it is
1652          * explicitly turned off or a power cycle is performed.  A read to
1653          * the register does not indicate its status.  Therefore, we ensure
1654          * loopback mode is disabled during initialization.
1655          */
1656         E1000_WRITE_REG(hw, E1000_SCTL, E1000_SCTL_DISABLE_SERDES_LOOPBACK);
1657
1658         /* power on the sfp cage if present */
1659         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
1660         ctrl_ext &= ~E1000_CTRL_EXT_SDP3_DATA;
1661         E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
1662
1663         ctrl_reg = E1000_READ_REG(hw, E1000_CTRL);
1664         ctrl_reg |= E1000_CTRL_SLU;
1665
1666         /* set both sw defined pins on 82575/82576*/
1667         if (hw->mac.type == e1000_82575 || hw->mac.type == e1000_82576)
1668                 ctrl_reg |= E1000_CTRL_SWDPIN0 | E1000_CTRL_SWDPIN1;
1669
1670         reg = E1000_READ_REG(hw, E1000_PCS_LCTL);
1671
1672         /* default pcs_autoneg to the same setting as mac autoneg */
1673         pcs_autoneg = hw->mac.autoneg;
1674
1675         switch (ctrl_ext & E1000_CTRL_EXT_LINK_MODE_MASK) {
1676         case E1000_CTRL_EXT_LINK_MODE_SGMII:
1677                 /* sgmii mode lets the phy handle forcing speed/duplex */
1678                 pcs_autoneg = true;
1679                 /* autoneg time out should be disabled for SGMII mode */
1680                 reg &= ~(E1000_PCS_LCTL_AN_TIMEOUT);
1681                 break;
1682         case E1000_CTRL_EXT_LINK_MODE_1000BASE_KX:
1683                 /* disable PCS autoneg and support parallel detect only */
1684                 pcs_autoneg = false;
1685                 /* fall through to default case */
1686         default:
1687                 if (hw->mac.type == e1000_82575 ||
1688                     hw->mac.type == e1000_82576) {
1689                         ret_val = hw->nvm.ops.read(hw, NVM_COMPAT, 1, &data);
1690                         if (ret_val) {
1691                                 DEBUGOUT("NVM Read Error\n");
1692                                 return ret_val;
1693                         }
1694
1695                         if (data & E1000_EEPROM_PCS_AUTONEG_DISABLE_BIT)
1696                                 pcs_autoneg = false;
1697                 }
1698
1699                 /*
1700                  * non-SGMII modes only supports a speed of 1000/Full for the
1701                  * link so it is best to just force the MAC and let the pcs
1702                  * link either autoneg or be forced to 1000/Full
1703                  */
1704                 ctrl_reg |= E1000_CTRL_SPD_1000 | E1000_CTRL_FRCSPD |
1705                             E1000_CTRL_FD | E1000_CTRL_FRCDPX;
1706
1707                 /* set speed of 1000/Full if speed/duplex is forced */
1708                 reg |= E1000_PCS_LCTL_FSV_1000 | E1000_PCS_LCTL_FDV_FULL;
1709                 break;
1710         }
1711
1712         E1000_WRITE_REG(hw, E1000_CTRL, ctrl_reg);
1713
1714         /*
1715          * New SerDes mode allows for forcing speed or autonegotiating speed
1716          * at 1gb. Autoneg should be default set by most drivers. This is the
1717          * mode that will be compatible with older link partners and switches.
1718          * However, both are supported by the hardware and some drivers/tools.
1719          */
1720         reg &= ~(E1000_PCS_LCTL_AN_ENABLE | E1000_PCS_LCTL_FLV_LINK_UP |
1721                  E1000_PCS_LCTL_FSD | E1000_PCS_LCTL_FORCE_LINK);
1722
1723         if (pcs_autoneg) {
1724                 /* Set PCS register for autoneg */
1725                 reg |= E1000_PCS_LCTL_AN_ENABLE | /* Enable Autoneg */
1726                        E1000_PCS_LCTL_AN_RESTART; /* Restart autoneg */
1727
1728                 /* Disable force flow control for autoneg */
1729                 reg &= ~E1000_PCS_LCTL_FORCE_FCTRL;
1730
1731                 /* Configure flow control advertisement for autoneg */
1732                 anadv_reg = E1000_READ_REG(hw, E1000_PCS_ANADV);
1733                 anadv_reg &= ~(E1000_TXCW_ASM_DIR | E1000_TXCW_PAUSE);
1734
1735                 switch (hw->fc.requested_mode) {
1736                 case e1000_fc_full:
1737                 case e1000_fc_rx_pause:
1738                         anadv_reg |= E1000_TXCW_ASM_DIR;
1739                         anadv_reg |= E1000_TXCW_PAUSE;
1740                         break;
1741                 case e1000_fc_tx_pause:
1742                         anadv_reg |= E1000_TXCW_ASM_DIR;
1743                         break;
1744                 default:
1745                         break;
1746                 }
1747
1748                 E1000_WRITE_REG(hw, E1000_PCS_ANADV, anadv_reg);
1749
1750                 DEBUGOUT1("Configuring Autoneg:PCS_LCTL=0x%08X\n", reg);
1751         } else {
1752                 /* Set PCS register for forced link */
1753                 reg |= E1000_PCS_LCTL_FSD;      /* Force Speed */
1754
1755                 /* Force flow control for forced link */
1756                 reg |= E1000_PCS_LCTL_FORCE_FCTRL;
1757
1758                 DEBUGOUT1("Configuring Forced Link:PCS_LCTL=0x%08X\n", reg);
1759         }
1760
1761         E1000_WRITE_REG(hw, E1000_PCS_LCTL, reg);
1762
1763         if (!pcs_autoneg && !e1000_sgmii_active_82575(hw))
1764                 e1000_force_mac_fc_generic(hw);
1765
1766         return ret_val;
1767 }
1768
1769 /**
1770  *  e1000_get_media_type_82575 - derives current media type.
1771  *  @hw: pointer to the HW structure
1772  *
1773  *  The media type is chosen reflecting few settings.
1774  *  The following are taken into account:
1775  *  - link mode set in the current port Init Control Word #3
1776  *  - current link mode settings in CSR register
1777  *  - MDIO vs. I2C PHY control interface chosen
1778  *  - SFP module media type
1779  **/
1780 STATIC s32 e1000_get_media_type_82575(struct e1000_hw *hw)
1781 {
1782         struct e1000_dev_spec_82575 *dev_spec = &hw->dev_spec._82575;
1783         s32 ret_val = E1000_SUCCESS;
1784         u32 ctrl_ext = 0;
1785         u32 link_mode = 0;
1786
1787         /* Set internal phy as default */
1788         dev_spec->sgmii_active = false;
1789         dev_spec->module_plugged = false;
1790
1791         /* Get CSR setting */
1792         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
1793
1794         /* extract link mode setting */
1795         link_mode = ctrl_ext & E1000_CTRL_EXT_LINK_MODE_MASK;
1796
1797         switch (link_mode) {
1798         case E1000_CTRL_EXT_LINK_MODE_1000BASE_KX:
1799                 hw->phy.media_type = e1000_media_type_internal_serdes;
1800                 break;
1801         case E1000_CTRL_EXT_LINK_MODE_GMII:
1802                 hw->phy.media_type = e1000_media_type_copper;
1803                 break;
1804         case E1000_CTRL_EXT_LINK_MODE_SGMII:
1805                 /* Get phy control interface type set (MDIO vs. I2C)*/
1806                 if (e1000_sgmii_uses_mdio_82575(hw)) {
1807                         hw->phy.media_type = e1000_media_type_copper;
1808                         dev_spec->sgmii_active = true;
1809                         break;
1810                 }
1811                 /* fall through for I2C based SGMII */
1812         case E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES:
1813                 /* read media type from SFP EEPROM */
1814                 ret_val = e1000_set_sfp_media_type_82575(hw);
1815                 if ((ret_val != E1000_SUCCESS) ||
1816                     (hw->phy.media_type == e1000_media_type_unknown)) {
1817                         /*
1818                          * If media type was not identified then return media
1819                          * type defined by the CTRL_EXT settings.
1820                          */
1821                         hw->phy.media_type = e1000_media_type_internal_serdes;
1822
1823                         if (link_mode == E1000_CTRL_EXT_LINK_MODE_SGMII) {
1824                                 hw->phy.media_type = e1000_media_type_copper;
1825                                 dev_spec->sgmii_active = true;
1826                         }
1827
1828                         break;
1829                 }
1830
1831                 /* do not change link mode for 100BaseFX */
1832                 if (dev_spec->eth_flags.e100_base_fx)
1833                         break;
1834
1835                 /* change current link mode setting */
1836                 ctrl_ext &= ~E1000_CTRL_EXT_LINK_MODE_MASK;
1837
1838                 if (hw->phy.media_type == e1000_media_type_copper)
1839                         ctrl_ext |= E1000_CTRL_EXT_LINK_MODE_SGMII;
1840                 else
1841                         ctrl_ext |= E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES;
1842
1843                 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
1844
1845                 break;
1846         }
1847
1848         return ret_val;
1849 }
1850
1851 /**
1852  *  e1000_set_sfp_media_type_82575 - derives SFP module media type.
1853  *  @hw: pointer to the HW structure
1854  *
1855  *  The media type is chosen based on SFP module.
1856  *  compatibility flags retrieved from SFP ID EEPROM.
1857  **/
1858 STATIC s32 e1000_set_sfp_media_type_82575(struct e1000_hw *hw)
1859 {
1860         s32 ret_val = E1000_ERR_CONFIG;
1861         u32 ctrl_ext = 0;
1862         struct e1000_dev_spec_82575 *dev_spec = &hw->dev_spec._82575;
1863         struct sfp_e1000_flags *eth_flags = &dev_spec->eth_flags;
1864         u8 tranceiver_type = 0;
1865         s32 timeout = 3;
1866
1867         /* Turn I2C interface ON and power on sfp cage */
1868         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
1869         ctrl_ext &= ~E1000_CTRL_EXT_SDP3_DATA;
1870         E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext | E1000_CTRL_I2C_ENA);
1871
1872         E1000_WRITE_FLUSH(hw);
1873
1874         /* Read SFP module data */
1875         while (timeout) {
1876                 ret_val = e1000_read_sfp_data_byte(hw,
1877                         E1000_I2CCMD_SFP_DATA_ADDR(E1000_SFF_IDENTIFIER_OFFSET),
1878                         &tranceiver_type);
1879                 if (ret_val == E1000_SUCCESS)
1880                         break;
1881                 msec_delay(100);
1882                 timeout--;
1883         }
1884         if (ret_val != E1000_SUCCESS)
1885                 goto out;
1886
1887         ret_val = e1000_read_sfp_data_byte(hw,
1888                         E1000_I2CCMD_SFP_DATA_ADDR(E1000_SFF_ETH_FLAGS_OFFSET),
1889                         (u8 *)eth_flags);
1890         if (ret_val != E1000_SUCCESS)
1891                 goto out;
1892
1893         /* Check if there is some SFP module plugged and powered */
1894         if ((tranceiver_type == E1000_SFF_IDENTIFIER_SFP) ||
1895             (tranceiver_type == E1000_SFF_IDENTIFIER_SFF)) {
1896                 dev_spec->module_plugged = true;
1897                 if (eth_flags->e1000_base_lx || eth_flags->e1000_base_sx) {
1898                         hw->phy.media_type = e1000_media_type_internal_serdes;
1899                 } else if (eth_flags->e100_base_fx) {
1900                         dev_spec->sgmii_active = true;
1901                         hw->phy.media_type = e1000_media_type_internal_serdes;
1902                 } else if (eth_flags->e1000_base_t) {
1903                         dev_spec->sgmii_active = true;
1904                         hw->phy.media_type = e1000_media_type_copper;
1905                 } else {
1906                         hw->phy.media_type = e1000_media_type_unknown;
1907                         DEBUGOUT("PHY module has not been recognized\n");
1908                         goto out;
1909                 }
1910         } else {
1911                 hw->phy.media_type = e1000_media_type_unknown;
1912         }
1913         ret_val = E1000_SUCCESS;
1914 out:
1915         /* Restore I2C interface setting */
1916         E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
1917         return ret_val;
1918 }
1919
1920 /**
1921  *  e1000_valid_led_default_82575 - Verify a valid default LED config
1922  *  @hw: pointer to the HW structure
1923  *  @data: pointer to the NVM (EEPROM)
1924  *
1925  *  Read the EEPROM for the current default LED configuration.  If the
1926  *  LED configuration is not valid, set to a valid LED configuration.
1927  **/
1928 STATIC s32 e1000_valid_led_default_82575(struct e1000_hw *hw, u16 *data)
1929 {
1930         s32 ret_val;
1931
1932         DEBUGFUNC("e1000_valid_led_default_82575");
1933
1934         ret_val = hw->nvm.ops.read(hw, NVM_ID_LED_SETTINGS, 1, data);
1935         if (ret_val) {
1936                 DEBUGOUT("NVM Read Error\n");
1937                 goto out;
1938         }
1939
1940         if (*data == ID_LED_RESERVED_0000 || *data == ID_LED_RESERVED_FFFF) {
1941                 switch (hw->phy.media_type) {
1942                 case e1000_media_type_internal_serdes:
1943                         *data = ID_LED_DEFAULT_82575_SERDES;
1944                         break;
1945                 case e1000_media_type_copper:
1946                 default:
1947                         *data = ID_LED_DEFAULT;
1948                         break;
1949                 }
1950         }
1951 out:
1952         return ret_val;
1953 }
1954
1955 /**
1956  *  e1000_sgmii_active_82575 - Return sgmii state
1957  *  @hw: pointer to the HW structure
1958  *
1959  *  82575 silicon has a serialized gigabit media independent interface (sgmii)
1960  *  which can be enabled for use in the embedded applications.  Simply
1961  *  return the current state of the sgmii interface.
1962  **/
1963 STATIC bool e1000_sgmii_active_82575(struct e1000_hw *hw)
1964 {
1965         struct e1000_dev_spec_82575 *dev_spec = &hw->dev_spec._82575;
1966         return dev_spec->sgmii_active;
1967 }
1968
1969 /**
1970  *  e1000_reset_init_script_82575 - Inits HW defaults after reset
1971  *  @hw: pointer to the HW structure
1972  *
1973  *  Inits recommended HW defaults after a reset when there is no EEPROM
1974  *  detected. This is only for the 82575.
1975  **/
1976 STATIC s32 e1000_reset_init_script_82575(struct e1000_hw *hw)
1977 {
1978         DEBUGFUNC("e1000_reset_init_script_82575");
1979
1980         if (hw->mac.type == e1000_82575) {
1981                 DEBUGOUT("Running reset init script for 82575\n");
1982                 /* SerDes configuration via SERDESCTRL */
1983                 e1000_write_8bit_ctrl_reg_generic(hw, E1000_SCTL, 0x00, 0x0C);
1984                 e1000_write_8bit_ctrl_reg_generic(hw, E1000_SCTL, 0x01, 0x78);
1985                 e1000_write_8bit_ctrl_reg_generic(hw, E1000_SCTL, 0x1B, 0x23);
1986                 e1000_write_8bit_ctrl_reg_generic(hw, E1000_SCTL, 0x23, 0x15);
1987
1988                 /* CCM configuration via CCMCTL register */
1989                 e1000_write_8bit_ctrl_reg_generic(hw, E1000_CCMCTL, 0x14, 0x00);
1990                 e1000_write_8bit_ctrl_reg_generic(hw, E1000_CCMCTL, 0x10, 0x00);
1991
1992                 /* PCIe lanes configuration */
1993                 e1000_write_8bit_ctrl_reg_generic(hw, E1000_GIOCTL, 0x00, 0xEC);
1994                 e1000_write_8bit_ctrl_reg_generic(hw, E1000_GIOCTL, 0x61, 0xDF);
1995                 e1000_write_8bit_ctrl_reg_generic(hw, E1000_GIOCTL, 0x34, 0x05);
1996                 e1000_write_8bit_ctrl_reg_generic(hw, E1000_GIOCTL, 0x2F, 0x81);
1997
1998                 /* PCIe PLL Configuration */
1999                 e1000_write_8bit_ctrl_reg_generic(hw, E1000_SCCTL, 0x02, 0x47);
2000                 e1000_write_8bit_ctrl_reg_generic(hw, E1000_SCCTL, 0x14, 0x00);
2001                 e1000_write_8bit_ctrl_reg_generic(hw, E1000_SCCTL, 0x10, 0x00);
2002         }
2003
2004         return E1000_SUCCESS;
2005 }
2006
2007 /**
2008  *  e1000_read_mac_addr_82575 - Read device MAC address
2009  *  @hw: pointer to the HW structure
2010  **/
2011 STATIC s32 e1000_read_mac_addr_82575(struct e1000_hw *hw)
2012 {
2013         s32 ret_val;
2014
2015         DEBUGFUNC("e1000_read_mac_addr_82575");
2016
2017         /*
2018          * If there's an alternate MAC address place it in RAR0
2019          * so that it will override the Si installed default perm
2020          * address.
2021          */
2022         ret_val = e1000_check_alt_mac_addr_generic(hw);
2023         if (ret_val)
2024                 goto out;
2025
2026         ret_val = e1000_read_mac_addr_generic(hw);
2027
2028 out:
2029         return ret_val;
2030 }
2031
2032 /**
2033  *  e1000_config_collision_dist_82575 - Configure collision distance
2034  *  @hw: pointer to the HW structure
2035  *
2036  *  Configures the collision distance to the default value and is used
2037  *  during link setup.
2038  **/
2039 STATIC void e1000_config_collision_dist_82575(struct e1000_hw *hw)
2040 {
2041         u32 tctl_ext;
2042
2043         DEBUGFUNC("e1000_config_collision_dist_82575");
2044
2045         tctl_ext = E1000_READ_REG(hw, E1000_TCTL_EXT);
2046
2047         tctl_ext &= ~E1000_TCTL_EXT_COLD;
2048         tctl_ext |= E1000_COLLISION_DISTANCE << E1000_TCTL_EXT_COLD_SHIFT;
2049
2050         E1000_WRITE_REG(hw, E1000_TCTL_EXT, tctl_ext);
2051         E1000_WRITE_FLUSH(hw);
2052 }
2053
2054 /**
2055  * e1000_power_down_phy_copper_82575 - Remove link during PHY power down
2056  * @hw: pointer to the HW structure
2057  *
2058  * In the case of a PHY power down to save power, or to turn off link during a
2059  * driver unload, or wake on lan is not enabled, remove the link.
2060  **/
2061 STATIC void e1000_power_down_phy_copper_82575(struct e1000_hw *hw)
2062 {
2063         struct e1000_phy_info *phy = &hw->phy;
2064
2065         if (!(phy->ops.check_reset_block))
2066                 return;
2067
2068         /* If the management interface is not enabled, then power down */
2069         if (!(e1000_enable_mng_pass_thru(hw) || phy->ops.check_reset_block(hw)))
2070                 e1000_power_down_phy_copper(hw);
2071
2072         return;
2073 }
2074
2075 /**
2076  *  e1000_clear_hw_cntrs_82575 - Clear device specific hardware counters
2077  *  @hw: pointer to the HW structure
2078  *
2079  *  Clears the hardware counters by reading the counter registers.
2080  **/
2081 STATIC void e1000_clear_hw_cntrs_82575(struct e1000_hw *hw)
2082 {
2083         DEBUGFUNC("e1000_clear_hw_cntrs_82575");
2084
2085         e1000_clear_hw_cntrs_base_generic(hw);
2086
2087         E1000_READ_REG(hw, E1000_PRC64);
2088         E1000_READ_REG(hw, E1000_PRC127);
2089         E1000_READ_REG(hw, E1000_PRC255);
2090         E1000_READ_REG(hw, E1000_PRC511);
2091         E1000_READ_REG(hw, E1000_PRC1023);
2092         E1000_READ_REG(hw, E1000_PRC1522);
2093         E1000_READ_REG(hw, E1000_PTC64);
2094         E1000_READ_REG(hw, E1000_PTC127);
2095         E1000_READ_REG(hw, E1000_PTC255);
2096         E1000_READ_REG(hw, E1000_PTC511);
2097         E1000_READ_REG(hw, E1000_PTC1023);
2098         E1000_READ_REG(hw, E1000_PTC1522);
2099
2100         E1000_READ_REG(hw, E1000_ALGNERRC);
2101         E1000_READ_REG(hw, E1000_RXERRC);
2102         E1000_READ_REG(hw, E1000_TNCRS);
2103         E1000_READ_REG(hw, E1000_CEXTERR);
2104         E1000_READ_REG(hw, E1000_TSCTC);
2105         E1000_READ_REG(hw, E1000_TSCTFC);
2106
2107         E1000_READ_REG(hw, E1000_MGTPRC);
2108         E1000_READ_REG(hw, E1000_MGTPDC);
2109         E1000_READ_REG(hw, E1000_MGTPTC);
2110
2111         E1000_READ_REG(hw, E1000_IAC);
2112         E1000_READ_REG(hw, E1000_ICRXOC);
2113
2114         E1000_READ_REG(hw, E1000_ICRXPTC);
2115         E1000_READ_REG(hw, E1000_ICRXATC);
2116         E1000_READ_REG(hw, E1000_ICTXPTC);
2117         E1000_READ_REG(hw, E1000_ICTXATC);
2118         E1000_READ_REG(hw, E1000_ICTXQEC);
2119         E1000_READ_REG(hw, E1000_ICTXQMTC);
2120         E1000_READ_REG(hw, E1000_ICRXDMTC);
2121
2122         E1000_READ_REG(hw, E1000_CBTMPC);
2123         E1000_READ_REG(hw, E1000_HTDPMC);
2124         E1000_READ_REG(hw, E1000_CBRMPC);
2125         E1000_READ_REG(hw, E1000_RPTHC);
2126         E1000_READ_REG(hw, E1000_HGPTC);
2127         E1000_READ_REG(hw, E1000_HTCBDPC);
2128         E1000_READ_REG(hw, E1000_HGORCL);
2129         E1000_READ_REG(hw, E1000_HGORCH);
2130         E1000_READ_REG(hw, E1000_HGOTCL);
2131         E1000_READ_REG(hw, E1000_HGOTCH);
2132         E1000_READ_REG(hw, E1000_LENERRS);
2133
2134         /* This register should not be read in copper configurations */
2135         if ((hw->phy.media_type == e1000_media_type_internal_serdes) ||
2136             e1000_sgmii_active_82575(hw))
2137                 E1000_READ_REG(hw, E1000_SCVPC);
2138 }
2139
2140 /**
2141  *  e1000_rx_fifo_flush_82575 - Clean rx fifo after Rx enable
2142  *  @hw: pointer to the HW structure
2143  *
2144  *  After Rx enable, if manageability is enabled then there is likely some
2145  *  bad data at the start of the fifo and possibly in the DMA fifo.  This
2146  *  function clears the fifos and flushes any packets that came in as rx was
2147  *  being enabled.
2148  **/
2149 void e1000_rx_fifo_flush_82575(struct e1000_hw *hw)
2150 {
2151         u32 rctl, rlpml, rxdctl[4], rfctl, temp_rctl, rx_enabled;
2152         int i, ms_wait;
2153
2154         DEBUGFUNC("e1000_rx_fifo_flush_82575");
2155
2156         /* disable IPv6 options as per hardware errata */
2157         rfctl = E1000_READ_REG(hw, E1000_RFCTL);
2158         rfctl |= E1000_RFCTL_IPV6_EX_DIS;
2159         E1000_WRITE_REG(hw, E1000_RFCTL, rfctl);
2160
2161         if (hw->mac.type != e1000_82575 ||
2162             !(E1000_READ_REG(hw, E1000_MANC) & E1000_MANC_RCV_TCO_EN))
2163                 return;
2164
2165         /* Disable all Rx queues */
2166         for (i = 0; i < 4; i++) {
2167                 rxdctl[i] = E1000_READ_REG(hw, E1000_RXDCTL(i));
2168                 E1000_WRITE_REG(hw, E1000_RXDCTL(i),
2169                                 rxdctl[i] & ~E1000_RXDCTL_QUEUE_ENABLE);
2170         }
2171         /* Poll all queues to verify they have shut down */
2172         for (ms_wait = 0; ms_wait < 10; ms_wait++) {
2173                 msec_delay(1);
2174                 rx_enabled = 0;
2175                 for (i = 0; i < 4; i++)
2176                         rx_enabled |= E1000_READ_REG(hw, E1000_RXDCTL(i));
2177                 if (!(rx_enabled & E1000_RXDCTL_QUEUE_ENABLE))
2178                         break;
2179         }
2180
2181         if (ms_wait == 10)
2182                 DEBUGOUT("Queue disable timed out after 10ms\n");
2183
2184         /* Clear RLPML, RCTL.SBP, RFCTL.LEF, and set RCTL.LPE so that all
2185          * incoming packets are rejected.  Set enable and wait 2ms so that
2186          * any packet that was coming in as RCTL.EN was set is flushed
2187          */
2188         E1000_WRITE_REG(hw, E1000_RFCTL, rfctl & ~E1000_RFCTL_LEF);
2189
2190         rlpml = E1000_READ_REG(hw, E1000_RLPML);
2191         E1000_WRITE_REG(hw, E1000_RLPML, 0);
2192
2193         rctl = E1000_READ_REG(hw, E1000_RCTL);
2194         temp_rctl = rctl & ~(E1000_RCTL_EN | E1000_RCTL_SBP);
2195         temp_rctl |= E1000_RCTL_LPE;
2196
2197         E1000_WRITE_REG(hw, E1000_RCTL, temp_rctl);
2198         E1000_WRITE_REG(hw, E1000_RCTL, temp_rctl | E1000_RCTL_EN);
2199         E1000_WRITE_FLUSH(hw);
2200         msec_delay(2);
2201
2202         /* Enable Rx queues that were previously enabled and restore our
2203          * previous state
2204          */
2205         for (i = 0; i < 4; i++)
2206                 E1000_WRITE_REG(hw, E1000_RXDCTL(i), rxdctl[i]);
2207         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2208         E1000_WRITE_FLUSH(hw);
2209
2210         E1000_WRITE_REG(hw, E1000_RLPML, rlpml);
2211         E1000_WRITE_REG(hw, E1000_RFCTL, rfctl);
2212
2213         /* Flush receive errors generated by workaround */
2214         E1000_READ_REG(hw, E1000_ROC);
2215         E1000_READ_REG(hw, E1000_RNBC);
2216         E1000_READ_REG(hw, E1000_MPC);
2217 }
2218
2219 /**
2220  *  e1000_set_pcie_completion_timeout - set pci-e completion timeout
2221  *  @hw: pointer to the HW structure
2222  *
2223  *  The defaults for 82575 and 82576 should be in the range of 50us to 50ms,
2224  *  however the hardware default for these parts is 500us to 1ms which is less
2225  *  than the 10ms recommended by the pci-e spec.  To address this we need to
2226  *  increase the value to either 10ms to 200ms for capability version 1 config,
2227  *  or 16ms to 55ms for version 2.
2228  **/
2229 STATIC s32 e1000_set_pcie_completion_timeout(struct e1000_hw *hw)
2230 {
2231         u32 gcr = E1000_READ_REG(hw, E1000_GCR);
2232         s32 ret_val = E1000_SUCCESS;
2233         u16 pcie_devctl2;
2234
2235         /* only take action if timeout value is defaulted to 0 */
2236         if (gcr & E1000_GCR_CMPL_TMOUT_MASK)
2237                 goto out;
2238
2239         /*
2240          * if capababilities version is type 1 we can write the
2241          * timeout of 10ms to 200ms through the GCR register
2242          */
2243         if (!(gcr & E1000_GCR_CAP_VER2)) {
2244                 gcr |= E1000_GCR_CMPL_TMOUT_10ms;
2245                 goto out;
2246         }
2247
2248         /*
2249          * for version 2 capabilities we need to write the config space
2250          * directly in order to set the completion timeout value for
2251          * 16ms to 55ms
2252          */
2253         ret_val = e1000_read_pcie_cap_reg(hw, PCIE_DEVICE_CONTROL2,
2254                                           &pcie_devctl2);
2255         if (ret_val)
2256                 goto out;
2257
2258         pcie_devctl2 |= PCIE_DEVICE_CONTROL2_16ms;
2259
2260         ret_val = e1000_write_pcie_cap_reg(hw, PCIE_DEVICE_CONTROL2,
2261                                            &pcie_devctl2);
2262 out:
2263         /* disable completion timeout resend */
2264         gcr &= ~E1000_GCR_CMPL_TMOUT_RESEND;
2265
2266         E1000_WRITE_REG(hw, E1000_GCR, gcr);
2267         return ret_val;
2268 }
2269
2270 /**
2271  *  e1000_vmdq_set_anti_spoofing_pf - enable or disable anti-spoofing
2272  *  @hw: pointer to the hardware struct
2273  *  @enable: state to enter, either enabled or disabled
2274  *  @pf: Physical Function pool - do not set anti-spoofing for the PF
2275  *
2276  *  enables/disables L2 switch anti-spoofing functionality.
2277  **/
2278 void e1000_vmdq_set_anti_spoofing_pf(struct e1000_hw *hw, bool enable, int pf)
2279 {
2280         u32 reg_val, reg_offset;
2281
2282         switch (hw->mac.type) {
2283         case e1000_82576:
2284                 reg_offset = E1000_DTXSWC;
2285                 break;
2286         case e1000_i350:
2287         case e1000_i354:
2288                 reg_offset = E1000_TXSWC;
2289                 break;
2290         default:
2291                 return;
2292         }
2293
2294         reg_val = E1000_READ_REG(hw, reg_offset);
2295         if (enable) {
2296                 reg_val |= (E1000_DTXSWC_MAC_SPOOF_MASK |
2297                              E1000_DTXSWC_VLAN_SPOOF_MASK);
2298                 /* The PF can spoof - it has to in order to
2299                  * support emulation mode NICs
2300                  */
2301                 reg_val ^= (1 << pf | 1 << (pf + MAX_NUM_VFS));
2302         } else {
2303                 reg_val &= ~(E1000_DTXSWC_MAC_SPOOF_MASK |
2304                              E1000_DTXSWC_VLAN_SPOOF_MASK);
2305         }
2306         E1000_WRITE_REG(hw, reg_offset, reg_val);
2307 }
2308
2309 /**
2310  *  e1000_vmdq_set_loopback_pf - enable or disable vmdq loopback
2311  *  @hw: pointer to the hardware struct
2312  *  @enable: state to enter, either enabled or disabled
2313  *
2314  *  enables/disables L2 switch loopback functionality.
2315  **/
2316 void e1000_vmdq_set_loopback_pf(struct e1000_hw *hw, bool enable)
2317 {
2318         u32 dtxswc;
2319
2320         switch (hw->mac.type) {
2321         case e1000_82576:
2322                 dtxswc = E1000_READ_REG(hw, E1000_DTXSWC);
2323                 if (enable)
2324                         dtxswc |= E1000_DTXSWC_VMDQ_LOOPBACK_EN;
2325                 else
2326                         dtxswc &= ~E1000_DTXSWC_VMDQ_LOOPBACK_EN;
2327                 E1000_WRITE_REG(hw, E1000_DTXSWC, dtxswc);
2328                 break;
2329         case e1000_i350:
2330         case e1000_i354:
2331                 dtxswc = E1000_READ_REG(hw, E1000_TXSWC);
2332                 if (enable)
2333                         dtxswc |= E1000_DTXSWC_VMDQ_LOOPBACK_EN;
2334                 else
2335                         dtxswc &= ~E1000_DTXSWC_VMDQ_LOOPBACK_EN;
2336                 E1000_WRITE_REG(hw, E1000_TXSWC, dtxswc);
2337                 break;
2338         default:
2339                 /* Currently no other hardware supports loopback */
2340                 break;
2341         }
2342
2343
2344 }
2345
2346 /**
2347  *  e1000_vmdq_set_replication_pf - enable or disable vmdq replication
2348  *  @hw: pointer to the hardware struct
2349  *  @enable: state to enter, either enabled or disabled
2350  *
2351  *  enables/disables replication of packets across multiple pools.
2352  **/
2353 void e1000_vmdq_set_replication_pf(struct e1000_hw *hw, bool enable)
2354 {
2355         u32 vt_ctl = E1000_READ_REG(hw, E1000_VT_CTL);
2356
2357         if (enable)
2358                 vt_ctl |= E1000_VT_CTL_VM_REPL_EN;
2359         else
2360                 vt_ctl &= ~E1000_VT_CTL_VM_REPL_EN;
2361
2362         E1000_WRITE_REG(hw, E1000_VT_CTL, vt_ctl);
2363 }
2364
2365 /**
2366  *  e1000_read_phy_reg_82580 - Read 82580 MDI control register
2367  *  @hw: pointer to the HW structure
2368  *  @offset: register offset to be read
2369  *  @data: pointer to the read data
2370  *
2371  *  Reads the MDI control register in the PHY at offset and stores the
2372  *  information read to data.
2373  **/
2374 STATIC s32 e1000_read_phy_reg_82580(struct e1000_hw *hw, u32 offset, u16 *data)
2375 {
2376         s32 ret_val;
2377
2378         DEBUGFUNC("e1000_read_phy_reg_82580");
2379
2380         ret_val = hw->phy.ops.acquire(hw);
2381         if (ret_val)
2382                 goto out;
2383
2384         ret_val = e1000_read_phy_reg_mdic(hw, offset, data);
2385
2386         hw->phy.ops.release(hw);
2387
2388 out:
2389         return ret_val;
2390 }
2391
2392 /**
2393  *  e1000_write_phy_reg_82580 - Write 82580 MDI control register
2394  *  @hw: pointer to the HW structure
2395  *  @offset: register offset to write to
2396  *  @data: data to write to register at offset
2397  *
2398  *  Writes data to MDI control register in the PHY at offset.
2399  **/
2400 STATIC s32 e1000_write_phy_reg_82580(struct e1000_hw *hw, u32 offset, u16 data)
2401 {
2402         s32 ret_val;
2403
2404         DEBUGFUNC("e1000_write_phy_reg_82580");
2405
2406         ret_val = hw->phy.ops.acquire(hw);
2407         if (ret_val)
2408                 goto out;
2409
2410         ret_val = e1000_write_phy_reg_mdic(hw, offset, data);
2411
2412         hw->phy.ops.release(hw);
2413
2414 out:
2415         return ret_val;
2416 }
2417
2418 /**
2419  *  e1000_reset_mdicnfg_82580 - Reset MDICNFG destination and com_mdio bits
2420  *  @hw: pointer to the HW structure
2421  *
2422  *  This resets the MDICNFG.Destination and MDICNFG.Com_MDIO bits based on
2423  *  the values found in the EEPROM.  This addresses an issue in which these
2424  *  bits are not restored from EEPROM after reset.
2425  **/
2426 STATIC s32 e1000_reset_mdicnfg_82580(struct e1000_hw *hw)
2427 {
2428         s32 ret_val = E1000_SUCCESS;
2429         u32 mdicnfg;
2430         u16 nvm_data = 0;
2431
2432         DEBUGFUNC("e1000_reset_mdicnfg_82580");
2433
2434         if (hw->mac.type != e1000_82580)
2435                 goto out;
2436         if (!e1000_sgmii_active_82575(hw))
2437                 goto out;
2438
2439         ret_val = hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_A +
2440                                    NVM_82580_LAN_FUNC_OFFSET(hw->bus.func), 1,
2441                                    &nvm_data);
2442         if (ret_val) {
2443                 DEBUGOUT("NVM Read Error\n");
2444                 goto out;
2445         }
2446
2447         mdicnfg = E1000_READ_REG(hw, E1000_MDICNFG);
2448         if (nvm_data & NVM_WORD24_EXT_MDIO)
2449                 mdicnfg |= E1000_MDICNFG_EXT_MDIO;
2450         if (nvm_data & NVM_WORD24_COM_MDIO)
2451                 mdicnfg |= E1000_MDICNFG_COM_MDIO;
2452         E1000_WRITE_REG(hw, E1000_MDICNFG, mdicnfg);
2453 out:
2454         return ret_val;
2455 }
2456
2457 /**
2458  *  e1000_reset_hw_82580 - Reset hardware
2459  *  @hw: pointer to the HW structure
2460  *
2461  *  This resets function or entire device (all ports, etc.)
2462  *  to a known state.
2463  **/
2464 STATIC s32 e1000_reset_hw_82580(struct e1000_hw *hw)
2465 {
2466         s32 ret_val = E1000_SUCCESS;
2467         /* BH SW mailbox bit in SW_FW_SYNC */
2468         u16 swmbsw_mask = E1000_SW_SYNCH_MB;
2469         u32 ctrl;
2470         bool global_device_reset = hw->dev_spec._82575.global_device_reset;
2471
2472         DEBUGFUNC("e1000_reset_hw_82580");
2473
2474         hw->dev_spec._82575.global_device_reset = false;
2475
2476         /* 82580 does not reliably do global_device_reset due to hw errata */
2477         if (hw->mac.type == e1000_82580)
2478                 global_device_reset = false;
2479
2480         /* Get current control state. */
2481         ctrl = E1000_READ_REG(hw, E1000_CTRL);
2482
2483         /*
2484          * Prevent the PCI-E bus from sticking if there is no TLP connection
2485          * on the last TLP read/write transaction when MAC is reset.
2486          */
2487         ret_val = e1000_disable_pcie_master_generic(hw);
2488         if (ret_val)
2489                 DEBUGOUT("PCI-E Master disable polling has failed.\n");
2490
2491         DEBUGOUT("Masking off all interrupts\n");
2492         E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff);
2493         E1000_WRITE_REG(hw, E1000_RCTL, 0);
2494         E1000_WRITE_REG(hw, E1000_TCTL, E1000_TCTL_PSP);
2495         E1000_WRITE_FLUSH(hw);
2496
2497         msec_delay(10);
2498
2499         /* Determine whether or not a global dev reset is requested */
2500         if (global_device_reset && hw->mac.ops.acquire_swfw_sync(hw,
2501             swmbsw_mask))
2502                         global_device_reset = false;
2503
2504         if (global_device_reset && !(E1000_READ_REG(hw, E1000_STATUS) &
2505             E1000_STAT_DEV_RST_SET))
2506                 ctrl |= E1000_CTRL_DEV_RST;
2507         else
2508                 ctrl |= E1000_CTRL_RST;
2509
2510         E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
2511
2512         switch (hw->device_id) {
2513         case E1000_DEV_ID_DH89XXCC_SGMII:
2514                 break;
2515         default:
2516                 E1000_WRITE_FLUSH(hw);
2517                 break;
2518         }
2519
2520         /* Add delay to insure DEV_RST or RST has time to complete */
2521         msec_delay(5);
2522
2523         ret_val = e1000_get_auto_rd_done_generic(hw);
2524         if (ret_val) {
2525                 /*
2526                  * When auto config read does not complete, do not
2527                  * return with an error. This can happen in situations
2528                  * where there is no eeprom and prevents getting link.
2529                  */
2530                 DEBUGOUT("Auto Read Done did not complete\n");
2531         }
2532
2533         /* clear global device reset status bit */
2534         E1000_WRITE_REG(hw, E1000_STATUS, E1000_STAT_DEV_RST_SET);
2535
2536         /* Clear any pending interrupt events. */
2537         E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff);
2538         E1000_READ_REG(hw, E1000_ICR);
2539
2540         ret_val = e1000_reset_mdicnfg_82580(hw);
2541         if (ret_val)
2542                 DEBUGOUT("Could not reset MDICNFG based on EEPROM\n");
2543
2544         /* Install any alternate MAC address into RAR0 */
2545         ret_val = e1000_check_alt_mac_addr_generic(hw);
2546
2547         /* Release semaphore */
2548         if (global_device_reset)
2549                 hw->mac.ops.release_swfw_sync(hw, swmbsw_mask);
2550
2551         return ret_val;
2552 }
2553
2554 /**
2555  *  e1000_rxpbs_adjust_82580 - adjust RXPBS value to reflect actual Rx PBA size
2556  *  @data: data received by reading RXPBS register
2557  *
2558  *  The 82580 uses a table based approach for packet buffer allocation sizes.
2559  *  This function converts the retrieved value into the correct table value
2560  *     0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7
2561  *  0x0 36  72 144   1   2   4   8  16
2562  *  0x8 35  70 140 rsv rsv rsv rsv rsv
2563  */
2564 u16 e1000_rxpbs_adjust_82580(u32 data)
2565 {
2566         u16 ret_val = 0;
2567
2568         if (data < E1000_82580_RXPBS_TABLE_SIZE)
2569                 ret_val = e1000_82580_rxpbs_table[data];
2570
2571         return ret_val;
2572 }
2573
2574 /**
2575  *  e1000_validate_nvm_checksum_with_offset - Validate EEPROM
2576  *  checksum
2577  *  @hw: pointer to the HW structure
2578  *  @offset: offset in words of the checksum protected region
2579  *
2580  *  Calculates the EEPROM checksum by reading/adding each word of the EEPROM
2581  *  and then verifies that the sum of the EEPROM is equal to 0xBABA.
2582  **/
2583 s32 e1000_validate_nvm_checksum_with_offset(struct e1000_hw *hw, u16 offset)
2584 {
2585         s32 ret_val = E1000_SUCCESS;
2586         u16 checksum = 0;
2587         u16 i, nvm_data;
2588
2589         DEBUGFUNC("e1000_validate_nvm_checksum_with_offset");
2590
2591         for (i = offset; i < ((NVM_CHECKSUM_REG + offset) + 1); i++) {
2592                 ret_val = hw->nvm.ops.read(hw, i, 1, &nvm_data);
2593                 if (ret_val) {
2594                         DEBUGOUT("NVM Read Error\n");
2595                         goto out;
2596                 }
2597                 checksum += nvm_data;
2598         }
2599
2600         if (checksum != (u16) NVM_SUM) {
2601                 DEBUGOUT("NVM Checksum Invalid\n");
2602                 ret_val = -E1000_ERR_NVM;
2603                 goto out;
2604         }
2605
2606 out:
2607         return ret_val;
2608 }
2609
2610 /**
2611  *  e1000_update_nvm_checksum_with_offset - Update EEPROM
2612  *  checksum
2613  *  @hw: pointer to the HW structure
2614  *  @offset: offset in words of the checksum protected region
2615  *
2616  *  Updates the EEPROM checksum by reading/adding each word of the EEPROM
2617  *  up to the checksum.  Then calculates the EEPROM checksum and writes the
2618  *  value to the EEPROM.
2619  **/
2620 s32 e1000_update_nvm_checksum_with_offset(struct e1000_hw *hw, u16 offset)
2621 {
2622         s32 ret_val;
2623         u16 checksum = 0;
2624         u16 i, nvm_data;
2625
2626         DEBUGFUNC("e1000_update_nvm_checksum_with_offset");
2627
2628         for (i = offset; i < (NVM_CHECKSUM_REG + offset); i++) {
2629                 ret_val = hw->nvm.ops.read(hw, i, 1, &nvm_data);
2630                 if (ret_val) {
2631                         DEBUGOUT("NVM Read Error while updating checksum.\n");
2632                         goto out;
2633                 }
2634                 checksum += nvm_data;
2635         }
2636         checksum = (u16) NVM_SUM - checksum;
2637         ret_val = hw->nvm.ops.write(hw, (NVM_CHECKSUM_REG + offset), 1,
2638                                     &checksum);
2639         if (ret_val)
2640                 DEBUGOUT("NVM Write Error while updating checksum.\n");
2641
2642 out:
2643         return ret_val;
2644 }
2645
2646 /**
2647  *  e1000_validate_nvm_checksum_82580 - Validate EEPROM checksum
2648  *  @hw: pointer to the HW structure
2649  *
2650  *  Calculates the EEPROM section checksum by reading/adding each word of
2651  *  the EEPROM and then verifies that the sum of the EEPROM is
2652  *  equal to 0xBABA.
2653  **/
2654 STATIC s32 e1000_validate_nvm_checksum_82580(struct e1000_hw *hw)
2655 {
2656         s32 ret_val;
2657         u16 eeprom_regions_count = 1;
2658         u16 j, nvm_data;
2659         u16 nvm_offset;
2660
2661         DEBUGFUNC("e1000_validate_nvm_checksum_82580");
2662
2663         ret_val = hw->nvm.ops.read(hw, NVM_COMPATIBILITY_REG_3, 1, &nvm_data);
2664         if (ret_val) {
2665                 DEBUGOUT("NVM Read Error\n");
2666                 goto out;
2667         }
2668
2669         if (nvm_data & NVM_COMPATIBILITY_BIT_MASK) {
2670                 /* if chekcsums compatibility bit is set validate checksums
2671                  * for all 4 ports. */
2672                 eeprom_regions_count = 4;
2673         }
2674
2675         for (j = 0; j < eeprom_regions_count; j++) {
2676                 nvm_offset = NVM_82580_LAN_FUNC_OFFSET(j);
2677                 ret_val = e1000_validate_nvm_checksum_with_offset(hw,
2678                                                                   nvm_offset);
2679                 if (ret_val != E1000_SUCCESS)
2680                         goto out;
2681         }
2682
2683 out:
2684         return ret_val;
2685 }
2686
2687 /**
2688  *  e1000_update_nvm_checksum_82580 - Update EEPROM checksum
2689  *  @hw: pointer to the HW structure
2690  *
2691  *  Updates the EEPROM section checksums for all 4 ports by reading/adding
2692  *  each word of the EEPROM up to the checksum.  Then calculates the EEPROM
2693  *  checksum and writes the value to the EEPROM.
2694  **/
2695 STATIC s32 e1000_update_nvm_checksum_82580(struct e1000_hw *hw)
2696 {
2697         s32 ret_val;
2698         u16 j, nvm_data;
2699         u16 nvm_offset;
2700
2701         DEBUGFUNC("e1000_update_nvm_checksum_82580");
2702
2703         ret_val = hw->nvm.ops.read(hw, NVM_COMPATIBILITY_REG_3, 1, &nvm_data);
2704         if (ret_val) {
2705                 DEBUGOUT("NVM Read Error while updating checksum compatibility bit.\n");
2706                 goto out;
2707         }
2708
2709         if (!(nvm_data & NVM_COMPATIBILITY_BIT_MASK)) {
2710                 /* set compatibility bit to validate checksums appropriately */
2711                 nvm_data = nvm_data | NVM_COMPATIBILITY_BIT_MASK;
2712                 ret_val = hw->nvm.ops.write(hw, NVM_COMPATIBILITY_REG_3, 1,
2713                                             &nvm_data);
2714                 if (ret_val) {
2715                         DEBUGOUT("NVM Write Error while updating checksum compatibility bit.\n");
2716                         goto out;
2717                 }
2718         }
2719
2720         for (j = 0; j < 4; j++) {
2721                 nvm_offset = NVM_82580_LAN_FUNC_OFFSET(j);
2722                 ret_val = e1000_update_nvm_checksum_with_offset(hw, nvm_offset);
2723                 if (ret_val)
2724                         goto out;
2725         }
2726
2727 out:
2728         return ret_val;
2729 }
2730
2731 /**
2732  *  e1000_validate_nvm_checksum_i350 - Validate EEPROM checksum
2733  *  @hw: pointer to the HW structure
2734  *
2735  *  Calculates the EEPROM section checksum by reading/adding each word of
2736  *  the EEPROM and then verifies that the sum of the EEPROM is
2737  *  equal to 0xBABA.
2738  **/
2739 STATIC s32 e1000_validate_nvm_checksum_i350(struct e1000_hw *hw)
2740 {
2741         s32 ret_val = E1000_SUCCESS;
2742         u16 j;
2743         u16 nvm_offset;
2744
2745         DEBUGFUNC("e1000_validate_nvm_checksum_i350");
2746
2747         for (j = 0; j < 4; j++) {
2748                 nvm_offset = NVM_82580_LAN_FUNC_OFFSET(j);
2749                 ret_val = e1000_validate_nvm_checksum_with_offset(hw,
2750                                                                   nvm_offset);
2751                 if (ret_val != E1000_SUCCESS)
2752                         goto out;
2753         }
2754
2755 out:
2756         return ret_val;
2757 }
2758
2759 /**
2760  *  e1000_update_nvm_checksum_i350 - Update EEPROM checksum
2761  *  @hw: pointer to the HW structure
2762  *
2763  *  Updates the EEPROM section checksums for all 4 ports by reading/adding
2764  *  each word of the EEPROM up to the checksum.  Then calculates the EEPROM
2765  *  checksum and writes the value to the EEPROM.
2766  **/
2767 STATIC s32 e1000_update_nvm_checksum_i350(struct e1000_hw *hw)
2768 {
2769         s32 ret_val = E1000_SUCCESS;
2770         u16 j;
2771         u16 nvm_offset;
2772
2773         DEBUGFUNC("e1000_update_nvm_checksum_i350");
2774
2775         for (j = 0; j < 4; j++) {
2776                 nvm_offset = NVM_82580_LAN_FUNC_OFFSET(j);
2777                 ret_val = e1000_update_nvm_checksum_with_offset(hw, nvm_offset);
2778                 if (ret_val != E1000_SUCCESS)
2779                         goto out;
2780         }
2781
2782 out:
2783         return ret_val;
2784 }
2785
2786 /**
2787  *  __e1000_access_emi_reg - Read/write EMI register
2788  *  @hw: pointer to the HW structure
2789  *  @addr: EMI address to program
2790  *  @data: pointer to value to read/write from/to the EMI address
2791  *  @read: boolean flag to indicate read or write
2792  **/
2793 STATIC s32 __e1000_access_emi_reg(struct e1000_hw *hw, u16 address,
2794                                   u16 *data, bool read)
2795 {
2796         s32 ret_val;
2797
2798         DEBUGFUNC("__e1000_access_emi_reg");
2799
2800         ret_val = hw->phy.ops.write_reg(hw, E1000_EMIADD, address);
2801         if (ret_val)
2802                 return ret_val;
2803
2804         if (read)
2805                 ret_val = hw->phy.ops.read_reg(hw, E1000_EMIDATA, data);
2806         else
2807                 ret_val = hw->phy.ops.write_reg(hw, E1000_EMIDATA, *data);
2808
2809         return ret_val;
2810 }
2811
2812 /**
2813  *  e1000_read_emi_reg - Read Extended Management Interface register
2814  *  @hw: pointer to the HW structure
2815  *  @addr: EMI address to program
2816  *  @data: value to be read from the EMI address
2817  **/
2818 s32 e1000_read_emi_reg(struct e1000_hw *hw, u16 addr, u16 *data)
2819 {
2820         DEBUGFUNC("e1000_read_emi_reg");
2821
2822         return __e1000_access_emi_reg(hw, addr, data, true);
2823 }
2824
2825 /**
2826  *  e1000_initialize_M88E1512_phy - Initialize M88E1512 PHY
2827  *  @hw: pointer to the HW structure
2828  *
2829  *  Initialize Marvell 1512 to work correctly with Avoton.
2830  **/
2831 s32 e1000_initialize_M88E1512_phy(struct e1000_hw *hw)
2832 {
2833         struct e1000_phy_info *phy = &hw->phy;
2834         s32 ret_val = E1000_SUCCESS;
2835
2836         DEBUGFUNC("e1000_initialize_M88E1512_phy");
2837
2838         /* Check if this is correct PHY. */
2839         if (phy->id != M88E1512_E_PHY_ID)
2840                 goto out;
2841
2842         /* Switch to PHY page 0xFF. */
2843         ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 0x00FF);
2844         if (ret_val)
2845                 goto out;
2846
2847         ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_2, 0x214B);
2848         if (ret_val)
2849                 goto out;
2850
2851         ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_1, 0x2144);
2852         if (ret_val)
2853                 goto out;
2854
2855         ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_2, 0x0C28);
2856         if (ret_val)
2857                 goto out;
2858
2859         ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_1, 0x2146);
2860         if (ret_val)
2861                 goto out;
2862
2863         ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_2, 0xB233);
2864         if (ret_val)
2865                 goto out;
2866
2867         ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_1, 0x214D);
2868         if (ret_val)
2869                 goto out;
2870
2871         ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_2, 0xCC0C);
2872         if (ret_val)
2873                 goto out;
2874
2875         ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_1, 0x2159);
2876         if (ret_val)
2877                 goto out;
2878
2879         /* Switch to PHY page 0xFB. */
2880         ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 0x00FB);
2881         if (ret_val)
2882                 goto out;
2883
2884         ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_3, 0x000D);
2885         if (ret_val)
2886                 goto out;
2887
2888         /* Switch to PHY page 0x12. */
2889         ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 0x12);
2890         if (ret_val)
2891                 goto out;
2892
2893         /* Change mode to SGMII-to-Copper */
2894         ret_val = phy->ops.write_reg(hw, E1000_M88E1512_MODE, 0x8001);
2895         if (ret_val)
2896                 goto out;
2897
2898         /* Return the PHY to page 0. */
2899         ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 0);
2900         if (ret_val)
2901                 goto out;
2902
2903         ret_val = phy->ops.commit(hw);
2904         if (ret_val) {
2905                 DEBUGOUT("Error committing the PHY changes\n");
2906                 return ret_val;
2907         }
2908
2909         msec_delay(1000);
2910 out:
2911         return ret_val;
2912 }
2913
2914 /**
2915  *  e1000_initialize_M88E1543_phy - Initialize M88E1543 PHY
2916  *  @hw: pointer to the HW structure
2917  *
2918  *  Initialize Marvell 1543 to work correctly with Avoton.
2919  **/
2920 s32 e1000_initialize_M88E1543_phy(struct e1000_hw *hw)
2921 {
2922         struct e1000_phy_info *phy = &hw->phy;
2923         s32 ret_val = E1000_SUCCESS;
2924
2925         DEBUGFUNC("e1000_initialize_M88E1543_phy");
2926
2927         /* Check if this is correct PHY. */
2928         if (phy->id != M88E1543_E_PHY_ID)
2929                 goto out;
2930
2931         /* Switch to PHY page 0xFF. */
2932         ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 0x00FF);
2933         if (ret_val)
2934                 goto out;
2935
2936         ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_2, 0x214B);
2937         if (ret_val)
2938                 goto out;
2939
2940         ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_1, 0x2144);
2941         if (ret_val)
2942                 goto out;
2943
2944         ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_2, 0x0C28);
2945         if (ret_val)
2946                 goto out;
2947
2948         ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_1, 0x2146);
2949         if (ret_val)
2950                 goto out;
2951
2952         ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_2, 0xB233);
2953         if (ret_val)
2954                 goto out;
2955
2956         ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_1, 0x214D);
2957         if (ret_val)
2958                 goto out;
2959
2960         ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_2, 0xDC0C);
2961         if (ret_val)
2962                 goto out;
2963
2964         ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_1, 0x2159);
2965         if (ret_val)
2966                 goto out;
2967
2968         /* Switch to PHY page 0xFB. */
2969         ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 0x00FB);
2970         if (ret_val)
2971                 goto out;
2972
2973         ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_3, 0xC00D);
2974         if (ret_val)
2975                 goto out;
2976
2977         /* Switch to PHY page 0x12. */
2978         ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 0x12);
2979         if (ret_val)
2980                 goto out;
2981
2982         /* Change mode to SGMII-to-Copper */
2983         ret_val = phy->ops.write_reg(hw, E1000_M88E1512_MODE, 0x8001);
2984         if (ret_val)
2985                 goto out;
2986
2987         /* Switch to PHY page 1. */
2988         ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 0x1);
2989         if (ret_val)
2990                 goto out;
2991
2992         /* Change mode to 1000BASE-X/SGMII and autoneg enable; reset */
2993         ret_val = phy->ops.write_reg(hw, E1000_M88E1543_FIBER_CTRL, 0x9140);
2994         if (ret_val)
2995                 goto out;
2996
2997         /* Return the PHY to page 0. */
2998         ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 0);
2999         if (ret_val)
3000                 goto out;
3001
3002         ret_val = phy->ops.commit(hw);
3003         if (ret_val) {
3004                 DEBUGOUT("Error committing the PHY changes\n");
3005                 return ret_val;
3006         }
3007
3008         msec_delay(1000);
3009 out:
3010         return ret_val;
3011 }
3012
3013 /**
3014  *  e1000_set_eee_i350 - Enable/disable EEE support
3015  *  @hw: pointer to the HW structure
3016  *  @adv1g: boolean flag enabling 1G EEE advertisement
3017  *  @adv100m: boolean flag enabling 100M EEE advertisement
3018  *
3019  *  Enable/disable EEE based on setting in dev_spec structure.
3020  *
3021  **/
3022 s32 e1000_set_eee_i350(struct e1000_hw *hw, bool adv1G, bool adv100M)
3023 {
3024         u32 ipcnfg, eeer;
3025
3026         DEBUGFUNC("e1000_set_eee_i350");
3027
3028         if ((hw->mac.type < e1000_i350) ||
3029             (hw->phy.media_type != e1000_media_type_copper))
3030                 goto out;
3031         ipcnfg = E1000_READ_REG(hw, E1000_IPCNFG);
3032         eeer = E1000_READ_REG(hw, E1000_EEER);
3033
3034         /* enable or disable per user setting */
3035         if (!(hw->dev_spec._82575.eee_disable)) {
3036                 u32 eee_su = E1000_READ_REG(hw, E1000_EEE_SU);
3037
3038                 if (adv100M)
3039                         ipcnfg |= E1000_IPCNFG_EEE_100M_AN;
3040                 else
3041                         ipcnfg &= ~E1000_IPCNFG_EEE_100M_AN;
3042
3043                 if (adv1G)
3044                         ipcnfg |= E1000_IPCNFG_EEE_1G_AN;
3045                 else
3046                         ipcnfg &= ~E1000_IPCNFG_EEE_1G_AN;
3047
3048                 eeer |= (E1000_EEER_TX_LPI_EN | E1000_EEER_RX_LPI_EN |
3049                          E1000_EEER_LPI_FC);
3050
3051                 /* This bit should not be set in normal operation. */
3052                 if (eee_su & E1000_EEE_SU_LPI_CLK_STP)
3053                         DEBUGOUT("LPI Clock Stop Bit should not be set!\n");
3054         } else {
3055                 ipcnfg &= ~(E1000_IPCNFG_EEE_1G_AN | E1000_IPCNFG_EEE_100M_AN);
3056                 eeer &= ~(E1000_EEER_TX_LPI_EN | E1000_EEER_RX_LPI_EN |
3057                           E1000_EEER_LPI_FC);
3058         }
3059         E1000_WRITE_REG(hw, E1000_IPCNFG, ipcnfg);
3060         E1000_WRITE_REG(hw, E1000_EEER, eeer);
3061         E1000_READ_REG(hw, E1000_IPCNFG);
3062         E1000_READ_REG(hw, E1000_EEER);
3063 out:
3064
3065         return E1000_SUCCESS;
3066 }
3067
3068 /**
3069  *  e1000_set_eee_i354 - Enable/disable EEE support
3070  *  @hw: pointer to the HW structure
3071  *  @adv1g: boolean flag enabling 1G EEE advertisement
3072  *  @adv100m: boolean flag enabling 100M EEE advertisement
3073  *
3074  *  Enable/disable EEE legacy mode based on setting in dev_spec structure.
3075  *
3076  **/
3077 s32 e1000_set_eee_i354(struct e1000_hw *hw, bool adv1G, bool adv100M)
3078 {
3079         struct e1000_phy_info *phy = &hw->phy;
3080         s32 ret_val = E1000_SUCCESS;
3081         u16 phy_data;
3082
3083         DEBUGFUNC("e1000_set_eee_i354");
3084
3085         if ((hw->phy.media_type != e1000_media_type_copper) ||
3086             ((phy->id != M88E1543_E_PHY_ID) &&
3087             (phy->id != M88E1512_E_PHY_ID)))
3088                 goto out;
3089
3090         if (!hw->dev_spec._82575.eee_disable) {
3091                 /* Switch to PHY page 18. */
3092                 ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 18);
3093                 if (ret_val)
3094                         goto out;
3095
3096                 ret_val = phy->ops.read_reg(hw, E1000_M88E1543_EEE_CTRL_1,
3097                                             &phy_data);
3098                 if (ret_val)
3099                         goto out;
3100
3101                 phy_data |= E1000_M88E1543_EEE_CTRL_1_MS;
3102                 ret_val = phy->ops.write_reg(hw, E1000_M88E1543_EEE_CTRL_1,
3103                                              phy_data);
3104                 if (ret_val)
3105                         goto out;
3106
3107                 /* Return the PHY to page 0. */
3108                 ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 0);
3109                 if (ret_val)
3110                         goto out;
3111
3112                 /* Turn on EEE advertisement. */
3113                 ret_val = e1000_read_xmdio_reg(hw, E1000_EEE_ADV_ADDR_I354,
3114                                                E1000_EEE_ADV_DEV_I354,
3115                                                &phy_data);
3116                 if (ret_val)
3117                         goto out;
3118
3119                 if (adv100M)
3120                         phy_data |= E1000_EEE_ADV_100_SUPPORTED;
3121                 else
3122                         phy_data &= ~E1000_EEE_ADV_100_SUPPORTED;
3123
3124                 if (adv1G)
3125                         phy_data |= E1000_EEE_ADV_1000_SUPPORTED;
3126                 else
3127                         phy_data &= ~E1000_EEE_ADV_1000_SUPPORTED;
3128
3129                 ret_val = e1000_write_xmdio_reg(hw, E1000_EEE_ADV_ADDR_I354,
3130                                                 E1000_EEE_ADV_DEV_I354,
3131                                                 phy_data);
3132         } else {
3133                 /* Turn off EEE advertisement. */
3134                 ret_val = e1000_read_xmdio_reg(hw, E1000_EEE_ADV_ADDR_I354,
3135                                                E1000_EEE_ADV_DEV_I354,
3136                                                &phy_data);
3137                 if (ret_val)
3138                         goto out;
3139
3140                 phy_data &= ~(E1000_EEE_ADV_100_SUPPORTED |
3141                               E1000_EEE_ADV_1000_SUPPORTED);
3142                 ret_val = e1000_write_xmdio_reg(hw, E1000_EEE_ADV_ADDR_I354,
3143                                                 E1000_EEE_ADV_DEV_I354,
3144                                                 phy_data);
3145         }
3146
3147 out:
3148         return ret_val;
3149 }
3150
3151 /**
3152  *  e1000_get_eee_status_i354 - Get EEE status
3153  *  @hw: pointer to the HW structure
3154  *  @status: EEE status
3155  *
3156  *  Get EEE status by guessing based on whether Tx or Rx LPI indications have
3157  *  been received.
3158  **/
3159 s32 e1000_get_eee_status_i354(struct e1000_hw *hw, bool *status)
3160 {
3161         struct e1000_phy_info *phy = &hw->phy;
3162         s32 ret_val = E1000_SUCCESS;
3163         u16 phy_data;
3164
3165         DEBUGFUNC("e1000_get_eee_status_i354");
3166
3167         /* Check if EEE is supported on this device. */
3168         if ((hw->phy.media_type != e1000_media_type_copper) ||
3169             ((phy->id != M88E1543_E_PHY_ID) &&
3170             (phy->id != M88E1512_E_PHY_ID)))
3171                 goto out;
3172
3173         ret_val = e1000_read_xmdio_reg(hw, E1000_PCS_STATUS_ADDR_I354,
3174                                        E1000_PCS_STATUS_DEV_I354,
3175                                        &phy_data);
3176         if (ret_val)
3177                 goto out;
3178
3179         *status = phy_data & (E1000_PCS_STATUS_TX_LPI_RCVD |
3180                               E1000_PCS_STATUS_RX_LPI_RCVD) ? true : false;
3181
3182 out:
3183         return ret_val;
3184 }
3185
3186 /* Due to a hw errata, if the host tries to  configure the VFTA register
3187  * while performing queries from the BMC or DMA, then the VFTA in some
3188  * cases won't be written.
3189  */
3190
3191 /**
3192  *  e1000_clear_vfta_i350 - Clear VLAN filter table
3193  *  @hw: pointer to the HW structure
3194  *
3195  *  Clears the register array which contains the VLAN filter table by
3196  *  setting all the values to 0.
3197  **/
3198 void e1000_clear_vfta_i350(struct e1000_hw *hw)
3199 {
3200         u32 offset;
3201         int i;
3202
3203         DEBUGFUNC("e1000_clear_vfta_350");
3204
3205         for (offset = 0; offset < E1000_VLAN_FILTER_TBL_SIZE; offset++) {
3206                 for (i = 0; i < 10; i++)
3207                         E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, offset, 0);
3208
3209                 E1000_WRITE_FLUSH(hw);
3210         }
3211 }
3212
3213 /**
3214  *  e1000_write_vfta_i350 - Write value to VLAN filter table
3215  *  @hw: pointer to the HW structure
3216  *  @offset: register offset in VLAN filter table
3217  *  @value: register value written to VLAN filter table
3218  *
3219  *  Writes value at the given offset in the register array which stores
3220  *  the VLAN filter table.
3221  **/
3222 void e1000_write_vfta_i350(struct e1000_hw *hw, u32 offset, u32 value)
3223 {
3224         int i;
3225
3226         DEBUGFUNC("e1000_write_vfta_350");
3227
3228         for (i = 0; i < 10; i++)
3229                 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, offset, value);
3230
3231         E1000_WRITE_FLUSH(hw);
3232 }
3233
3234
3235 /**
3236  *  e1000_set_i2c_bb - Enable I2C bit-bang
3237  *  @hw: pointer to the HW structure
3238  *
3239  *  Enable I2C bit-bang interface
3240  *
3241  **/
3242 s32 e1000_set_i2c_bb(struct e1000_hw *hw)
3243 {
3244         s32 ret_val = E1000_SUCCESS;
3245         u32 ctrl_ext, i2cparams;
3246
3247         DEBUGFUNC("e1000_set_i2c_bb");
3248
3249         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
3250         ctrl_ext |= E1000_CTRL_I2C_ENA;
3251         E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
3252         E1000_WRITE_FLUSH(hw);
3253
3254         i2cparams = E1000_READ_REG(hw, E1000_I2CPARAMS);
3255         i2cparams |= E1000_I2CBB_EN;
3256         i2cparams |= E1000_I2C_DATA_OE_N;
3257         i2cparams |= E1000_I2C_CLK_OE_N;
3258         E1000_WRITE_REG(hw, E1000_I2CPARAMS, i2cparams);
3259         E1000_WRITE_FLUSH(hw);
3260
3261         return ret_val;
3262 }
3263
3264 /**
3265  *  e1000_read_i2c_byte_generic - Reads 8 bit word over I2C
3266  *  @hw: pointer to hardware structure
3267  *  @byte_offset: byte offset to read
3268  *  @dev_addr: device address
3269  *  @data: value read
3270  *
3271  *  Performs byte read operation over I2C interface at
3272  *  a specified device address.
3273  **/
3274 s32 e1000_read_i2c_byte_generic(struct e1000_hw *hw, u8 byte_offset,
3275                                 u8 dev_addr, u8 *data)
3276 {
3277         s32 status = E1000_SUCCESS;
3278         u32 max_retry = 10;
3279         u32 retry = 1;
3280         u16 swfw_mask = 0;
3281
3282         bool nack = true;
3283
3284         DEBUGFUNC("e1000_read_i2c_byte_generic");
3285
3286         swfw_mask = E1000_SWFW_PHY0_SM;
3287
3288         do {
3289                 if (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask)
3290                     != E1000_SUCCESS) {
3291                         status = E1000_ERR_SWFW_SYNC;
3292                         goto read_byte_out;
3293                 }
3294
3295                 e1000_i2c_start(hw);
3296
3297                 /* Device Address and write indication */
3298                 status = e1000_clock_out_i2c_byte(hw, dev_addr);
3299                 if (status != E1000_SUCCESS)
3300                         goto fail;
3301
3302                 status = e1000_get_i2c_ack(hw);
3303                 if (status != E1000_SUCCESS)
3304                         goto fail;
3305
3306                 status = e1000_clock_out_i2c_byte(hw, byte_offset);
3307                 if (status != E1000_SUCCESS)
3308                         goto fail;
3309
3310                 status = e1000_get_i2c_ack(hw);
3311                 if (status != E1000_SUCCESS)
3312                         goto fail;
3313
3314                 e1000_i2c_start(hw);
3315
3316                 /* Device Address and read indication */
3317                 status = e1000_clock_out_i2c_byte(hw, (dev_addr | 0x1));
3318                 if (status != E1000_SUCCESS)
3319                         goto fail;
3320
3321                 status = e1000_get_i2c_ack(hw);
3322                 if (status != E1000_SUCCESS)
3323                         goto fail;
3324
3325                 status = e1000_clock_in_i2c_byte(hw, data);
3326                 if (status != E1000_SUCCESS)
3327                         goto fail;
3328
3329                 status = e1000_clock_out_i2c_bit(hw, nack);
3330                 if (status != E1000_SUCCESS)
3331                         goto fail;
3332
3333                 e1000_i2c_stop(hw);
3334                 break;
3335
3336 fail:
3337                 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
3338                 msec_delay(100);
3339                 e1000_i2c_bus_clear(hw);
3340                 retry++;
3341                 if (retry < max_retry)
3342                         DEBUGOUT("I2C byte read error - Retrying.\n");
3343                 else
3344                         DEBUGOUT("I2C byte read error.\n");
3345
3346         } while (retry < max_retry);
3347
3348         hw->mac.ops.release_swfw_sync(hw, swfw_mask);
3349
3350 read_byte_out:
3351
3352         return status;
3353 }
3354
3355 /**
3356  *  e1000_write_i2c_byte_generic - Writes 8 bit word over I2C
3357  *  @hw: pointer to hardware structure
3358  *  @byte_offset: byte offset to write
3359  *  @dev_addr: device address
3360  *  @data: value to write
3361  *
3362  *  Performs byte write operation over I2C interface at
3363  *  a specified device address.
3364  **/
3365 s32 e1000_write_i2c_byte_generic(struct e1000_hw *hw, u8 byte_offset,
3366                                  u8 dev_addr, u8 data)
3367 {
3368         s32 status = E1000_SUCCESS;
3369         u32 max_retry = 1;
3370         u32 retry = 0;
3371         u16 swfw_mask = 0;
3372
3373         DEBUGFUNC("e1000_write_i2c_byte_generic");
3374
3375         swfw_mask = E1000_SWFW_PHY0_SM;
3376
3377         if (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask) != E1000_SUCCESS) {
3378                 status = E1000_ERR_SWFW_SYNC;
3379                 goto write_byte_out;
3380         }
3381
3382         do {
3383                 e1000_i2c_start(hw);
3384
3385                 status = e1000_clock_out_i2c_byte(hw, dev_addr);
3386                 if (status != E1000_SUCCESS)
3387                         goto fail;
3388
3389                 status = e1000_get_i2c_ack(hw);
3390                 if (status != E1000_SUCCESS)
3391                         goto fail;
3392
3393                 status = e1000_clock_out_i2c_byte(hw, byte_offset);
3394                 if (status != E1000_SUCCESS)
3395                         goto fail;
3396
3397                 status = e1000_get_i2c_ack(hw);
3398                 if (status != E1000_SUCCESS)
3399                         goto fail;
3400
3401                 status = e1000_clock_out_i2c_byte(hw, data);
3402                 if (status != E1000_SUCCESS)
3403                         goto fail;
3404
3405                 status = e1000_get_i2c_ack(hw);
3406                 if (status != E1000_SUCCESS)
3407                         goto fail;
3408
3409                 e1000_i2c_stop(hw);
3410                 break;
3411
3412 fail:
3413                 e1000_i2c_bus_clear(hw);
3414                 retry++;
3415                 if (retry < max_retry)
3416                         DEBUGOUT("I2C byte write error - Retrying.\n");
3417                 else
3418                         DEBUGOUT("I2C byte write error.\n");
3419         } while (retry < max_retry);
3420
3421         hw->mac.ops.release_swfw_sync(hw, swfw_mask);
3422
3423 write_byte_out:
3424
3425         return status;
3426 }
3427
3428 /**
3429  *  e1000_i2c_start - Sets I2C start condition
3430  *  @hw: pointer to hardware structure
3431  *
3432  *  Sets I2C start condition (High -> Low on SDA while SCL is High)
3433  **/
3434 STATIC void e1000_i2c_start(struct e1000_hw *hw)
3435 {
3436         u32 i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS);
3437
3438         DEBUGFUNC("e1000_i2c_start");
3439
3440         /* Start condition must begin with data and clock high */
3441         e1000_set_i2c_data(hw, &i2cctl, 1);
3442         e1000_raise_i2c_clk(hw, &i2cctl);
3443
3444         /* Setup time for start condition (4.7us) */
3445         usec_delay(E1000_I2C_T_SU_STA);
3446
3447         e1000_set_i2c_data(hw, &i2cctl, 0);
3448
3449         /* Hold time for start condition (4us) */
3450         usec_delay(E1000_I2C_T_HD_STA);
3451
3452         e1000_lower_i2c_clk(hw, &i2cctl);
3453
3454         /* Minimum low period of clock is 4.7 us */
3455         usec_delay(E1000_I2C_T_LOW);
3456
3457 }
3458
3459 /**
3460  *  e1000_i2c_stop - Sets I2C stop condition
3461  *  @hw: pointer to hardware structure
3462  *
3463  *  Sets I2C stop condition (Low -> High on SDA while SCL is High)
3464  **/
3465 STATIC void e1000_i2c_stop(struct e1000_hw *hw)
3466 {
3467         u32 i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS);
3468
3469         DEBUGFUNC("e1000_i2c_stop");
3470
3471         /* Stop condition must begin with data low and clock high */
3472         e1000_set_i2c_data(hw, &i2cctl, 0);
3473         e1000_raise_i2c_clk(hw, &i2cctl);
3474
3475         /* Setup time for stop condition (4us) */
3476         usec_delay(E1000_I2C_T_SU_STO);
3477
3478         e1000_set_i2c_data(hw, &i2cctl, 1);
3479
3480         /* bus free time between stop and start (4.7us)*/
3481         usec_delay(E1000_I2C_T_BUF);
3482 }
3483
3484 /**
3485  *  e1000_clock_in_i2c_byte - Clocks in one byte via I2C
3486  *  @hw: pointer to hardware structure
3487  *  @data: data byte to clock in
3488  *
3489  *  Clocks in one byte data via I2C data/clock
3490  **/
3491 STATIC s32 e1000_clock_in_i2c_byte(struct e1000_hw *hw, u8 *data)
3492 {
3493         s32 i;
3494         bool bit = 0;
3495
3496         DEBUGFUNC("e1000_clock_in_i2c_byte");
3497
3498         *data = 0;
3499         for (i = 7; i >= 0; i--) {
3500                 e1000_clock_in_i2c_bit(hw, &bit);
3501                 *data |= bit << i;
3502         }
3503
3504         return E1000_SUCCESS;
3505 }
3506
3507 /**
3508  *  e1000_clock_out_i2c_byte - Clocks out one byte via I2C
3509  *  @hw: pointer to hardware structure
3510  *  @data: data byte clocked out
3511  *
3512  *  Clocks out one byte data via I2C data/clock
3513  **/
3514 STATIC s32 e1000_clock_out_i2c_byte(struct e1000_hw *hw, u8 data)
3515 {
3516         s32 status = E1000_SUCCESS;
3517         s32 i;
3518         u32 i2cctl;
3519         bool bit = 0;
3520
3521         DEBUGFUNC("e1000_clock_out_i2c_byte");
3522
3523         for (i = 7; i >= 0; i--) {
3524                 bit = (data >> i) & 0x1;
3525                 status = e1000_clock_out_i2c_bit(hw, bit);
3526
3527                 if (status != E1000_SUCCESS)
3528                         break;
3529         }
3530
3531         /* Release SDA line (set high) */
3532         i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS);
3533
3534         i2cctl |= E1000_I2C_DATA_OE_N;
3535         E1000_WRITE_REG(hw, E1000_I2CPARAMS, i2cctl);
3536         E1000_WRITE_FLUSH(hw);
3537
3538         return status;
3539 }
3540
3541 /**
3542  *  e1000_get_i2c_ack - Polls for I2C ACK
3543  *  @hw: pointer to hardware structure
3544  *
3545  *  Clocks in/out one bit via I2C data/clock
3546  **/
3547 STATIC s32 e1000_get_i2c_ack(struct e1000_hw *hw)
3548 {
3549         s32 status = E1000_SUCCESS;
3550         u32 i = 0;
3551         u32 i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS);
3552         u32 timeout = 10;
3553         bool ack = true;
3554
3555         DEBUGFUNC("e1000_get_i2c_ack");
3556
3557         e1000_raise_i2c_clk(hw, &i2cctl);
3558
3559         /* Minimum high period of clock is 4us */
3560         usec_delay(E1000_I2C_T_HIGH);
3561
3562         /* Wait until SCL returns high */
3563         for (i = 0; i < timeout; i++) {
3564                 usec_delay(1);
3565                 i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS);
3566                 if (i2cctl & E1000_I2C_CLK_IN)
3567                         break;
3568         }
3569         if (!(i2cctl & E1000_I2C_CLK_IN))
3570                 return E1000_ERR_I2C;
3571
3572         ack = e1000_get_i2c_data(&i2cctl);
3573         if (ack) {
3574                 DEBUGOUT("I2C ack was not received.\n");
3575                 status = E1000_ERR_I2C;
3576         }
3577
3578         e1000_lower_i2c_clk(hw, &i2cctl);
3579
3580         /* Minimum low period of clock is 4.7 us */
3581         usec_delay(E1000_I2C_T_LOW);
3582
3583         return status;
3584 }
3585
3586 /**
3587  *  e1000_clock_in_i2c_bit - Clocks in one bit via I2C data/clock
3588  *  @hw: pointer to hardware structure
3589  *  @data: read data value
3590  *
3591  *  Clocks in one bit via I2C data/clock
3592  **/
3593 STATIC s32 e1000_clock_in_i2c_bit(struct e1000_hw *hw, bool *data)
3594 {
3595         u32 i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS);
3596
3597         DEBUGFUNC("e1000_clock_in_i2c_bit");
3598
3599         e1000_raise_i2c_clk(hw, &i2cctl);
3600
3601         /* Minimum high period of clock is 4us */
3602         usec_delay(E1000_I2C_T_HIGH);
3603
3604         i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS);
3605         *data = e1000_get_i2c_data(&i2cctl);
3606
3607         e1000_lower_i2c_clk(hw, &i2cctl);
3608
3609         /* Minimum low period of clock is 4.7 us */
3610         usec_delay(E1000_I2C_T_LOW);
3611
3612         return E1000_SUCCESS;
3613 }
3614
3615 /**
3616  *  e1000_clock_out_i2c_bit - Clocks in/out one bit via I2C data/clock
3617  *  @hw: pointer to hardware structure
3618  *  @data: data value to write
3619  *
3620  *  Clocks out one bit via I2C data/clock
3621  **/
3622 STATIC s32 e1000_clock_out_i2c_bit(struct e1000_hw *hw, bool data)
3623 {
3624         s32 status;
3625         u32 i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS);
3626
3627         DEBUGFUNC("e1000_clock_out_i2c_bit");
3628
3629         status = e1000_set_i2c_data(hw, &i2cctl, data);
3630         if (status == E1000_SUCCESS) {
3631                 e1000_raise_i2c_clk(hw, &i2cctl);
3632
3633                 /* Minimum high period of clock is 4us */
3634                 usec_delay(E1000_I2C_T_HIGH);
3635
3636                 e1000_lower_i2c_clk(hw, &i2cctl);
3637
3638                 /* Minimum low period of clock is 4.7 us.
3639                  * This also takes care of the data hold time.
3640                  */
3641                 usec_delay(E1000_I2C_T_LOW);
3642         } else {
3643                 status = E1000_ERR_I2C;
3644                 DEBUGOUT1("I2C data was not set to %X\n", data);
3645         }
3646
3647         return status;
3648 }
3649 /**
3650  *  e1000_raise_i2c_clk - Raises the I2C SCL clock
3651  *  @hw: pointer to hardware structure
3652  *  @i2cctl: Current value of I2CCTL register
3653  *
3654  *  Raises the I2C clock line '0'->'1'
3655  **/
3656 STATIC void e1000_raise_i2c_clk(struct e1000_hw *hw, u32 *i2cctl)
3657 {
3658         DEBUGFUNC("e1000_raise_i2c_clk");
3659
3660         *i2cctl |= E1000_I2C_CLK_OUT;
3661         *i2cctl &= ~E1000_I2C_CLK_OE_N;
3662         E1000_WRITE_REG(hw, E1000_I2CPARAMS, *i2cctl);
3663         E1000_WRITE_FLUSH(hw);
3664
3665         /* SCL rise time (1000ns) */
3666         usec_delay(E1000_I2C_T_RISE);
3667 }
3668
3669 /**
3670  *  e1000_lower_i2c_clk - Lowers the I2C SCL clock
3671  *  @hw: pointer to hardware structure
3672  *  @i2cctl: Current value of I2CCTL register
3673  *
3674  *  Lowers the I2C clock line '1'->'0'
3675  **/
3676 STATIC void e1000_lower_i2c_clk(struct e1000_hw *hw, u32 *i2cctl)
3677 {
3678
3679         DEBUGFUNC("e1000_lower_i2c_clk");
3680
3681         *i2cctl &= ~E1000_I2C_CLK_OUT;
3682         *i2cctl &= ~E1000_I2C_CLK_OE_N;
3683         E1000_WRITE_REG(hw, E1000_I2CPARAMS, *i2cctl);
3684         E1000_WRITE_FLUSH(hw);
3685
3686         /* SCL fall time (300ns) */
3687         usec_delay(E1000_I2C_T_FALL);
3688 }
3689
3690 /**
3691  *  e1000_set_i2c_data - Sets the I2C data bit
3692  *  @hw: pointer to hardware structure
3693  *  @i2cctl: Current value of I2CCTL register
3694  *  @data: I2C data value (0 or 1) to set
3695  *
3696  *  Sets the I2C data bit
3697  **/
3698 STATIC s32 e1000_set_i2c_data(struct e1000_hw *hw, u32 *i2cctl, bool data)
3699 {
3700         s32 status = E1000_SUCCESS;
3701
3702         DEBUGFUNC("e1000_set_i2c_data");
3703
3704         if (data)
3705                 *i2cctl |= E1000_I2C_DATA_OUT;
3706         else
3707                 *i2cctl &= ~E1000_I2C_DATA_OUT;
3708
3709         *i2cctl &= ~E1000_I2C_DATA_OE_N;
3710         *i2cctl |= E1000_I2C_CLK_OE_N;
3711         E1000_WRITE_REG(hw, E1000_I2CPARAMS, *i2cctl);
3712         E1000_WRITE_FLUSH(hw);
3713
3714         /* Data rise/fall (1000ns/300ns) and set-up time (250ns) */
3715         usec_delay(E1000_I2C_T_RISE + E1000_I2C_T_FALL + E1000_I2C_T_SU_DATA);
3716
3717         *i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS);
3718         if (data != e1000_get_i2c_data(i2cctl)) {
3719                 status = E1000_ERR_I2C;
3720                 DEBUGOUT1("Error - I2C data was not set to %X.\n", data);
3721         }
3722
3723         return status;
3724 }
3725
3726 /**
3727  *  e1000_get_i2c_data - Reads the I2C SDA data bit
3728  *  @hw: pointer to hardware structure
3729  *  @i2cctl: Current value of I2CCTL register
3730  *
3731  *  Returns the I2C data bit value
3732  **/
3733 STATIC bool e1000_get_i2c_data(u32 *i2cctl)
3734 {
3735         bool data;
3736
3737         DEBUGFUNC("e1000_get_i2c_data");
3738
3739         if (*i2cctl & E1000_I2C_DATA_IN)
3740                 data = 1;
3741         else
3742                 data = 0;
3743
3744         return data;
3745 }
3746
3747 /**
3748  *  e1000_i2c_bus_clear - Clears the I2C bus
3749  *  @hw: pointer to hardware structure
3750  *
3751  *  Clears the I2C bus by sending nine clock pulses.
3752  *  Used when data line is stuck low.
3753  **/
3754 void e1000_i2c_bus_clear(struct e1000_hw *hw)
3755 {
3756         u32 i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS);
3757         u32 i;
3758
3759         DEBUGFUNC("e1000_i2c_bus_clear");
3760
3761         e1000_i2c_start(hw);
3762
3763         e1000_set_i2c_data(hw, &i2cctl, 1);
3764
3765         for (i = 0; i < 9; i++) {
3766                 e1000_raise_i2c_clk(hw, &i2cctl);
3767
3768                 /* Min high period of clock is 4us */
3769                 usec_delay(E1000_I2C_T_HIGH);
3770
3771                 e1000_lower_i2c_clk(hw, &i2cctl);
3772
3773                 /* Min low period of clock is 4.7us*/
3774                 usec_delay(E1000_I2C_T_LOW);
3775         }
3776
3777         e1000_i2c_start(hw);
3778
3779         /* Put the i2c bus back to default state */
3780         e1000_i2c_stop(hw);
3781 }
3782