drivers/net/e1000/base/e1000_hw.h

   1 /*******************************************************************************
   2
   3 Copyright (c) 2001-2015, Intel Corporation
   4 All rights reserved.
   5
   6 Redistribution and use in source and binary forms, with or without
   7 modification, are permitted provided that the following conditions are met:
   8
   9  1. Redistributions of source code must retain the above copyright notice,
  10     this list of conditions and the following disclaimer.
  11
  12  2. Redistributions in binary form must reproduce the above copyright
  13     notice, this list of conditions and the following disclaimer in the
  14     documentation and/or other materials provided with the distribution.
  15
  16  3. Neither the name of the Intel Corporation nor the names of its
  17     contributors may be used to endorse or promote products derived from
  18     this software without specific prior written permission.
  19
  20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
  24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  30 POSSIBILITY OF SUCH DAMAGE.
  31
  32 ***************************************************************************/
  33
  34 #ifndef _E1000_HW_H_
  35 #define _E1000_HW_H_
  36
  37 #include "e1000_osdep.h"
  38 #include "e1000_regs.h"
  39 #include "e1000_defines.h"
  40
  41 struct e1000_hw;
  42
  43 #define E1000_DEV_ID_82542                      0x1000
  44 #define E1000_DEV_ID_82543GC_FIBER              0x1001
  45 #define E1000_DEV_ID_82543GC_COPPER             0x1004
  46 #define E1000_DEV_ID_82544EI_COPPER             0x1008
  47 #define E1000_DEV_ID_82544EI_FIBER              0x1009
  48 #define E1000_DEV_ID_82544GC_COPPER             0x100C
  49 #define E1000_DEV_ID_82544GC_LOM                0x100D
  50 #define E1000_DEV_ID_82540EM                    0x100E
  51 #define E1000_DEV_ID_82540EM_LOM                0x1015
  52 #define E1000_DEV_ID_82540EP_LOM                0x1016
  53 #define E1000_DEV_ID_82540EP                    0x1017
  54 #define E1000_DEV_ID_82540EP_LP                 0x101E
  55 #define E1000_DEV_ID_82545EM_COPPER             0x100F
  56 #define E1000_DEV_ID_82545EM_FIBER              0x1011
  57 #define E1000_DEV_ID_82545GM_COPPER             0x1026
  58 #define E1000_DEV_ID_82545GM_FIBER              0x1027
  59 #define E1000_DEV_ID_82545GM_SERDES             0x1028
  60 #define E1000_DEV_ID_82546EB_COPPER             0x1010
  61 #define E1000_DEV_ID_82546EB_FIBER              0x1012
  62 #define E1000_DEV_ID_82546EB_QUAD_COPPER        0x101D
  63 #define E1000_DEV_ID_82546GB_COPPER             0x1079
  64 #define E1000_DEV_ID_82546GB_FIBER              0x107A
  65 #define E1000_DEV_ID_82546GB_SERDES             0x107B
  66 #define E1000_DEV_ID_82546GB_PCIE               0x108A
  67 #define E1000_DEV_ID_82546GB_QUAD_COPPER        0x1099
  68 #define E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3   0x10B5
  69 #define E1000_DEV_ID_82541EI                    0x1013
  70 #define E1000_DEV_ID_82541EI_MOBILE             0x1018
  71 #define E1000_DEV_ID_82541ER_LOM                0x1014
  72 #define E1000_DEV_ID_82541ER                    0x1078
  73 #define E1000_DEV_ID_82541GI                    0x1076
  74 #define E1000_DEV_ID_82541GI_LF                 0x107C
  75 #define E1000_DEV_ID_82541GI_MOBILE             0x1077
  76 #define E1000_DEV_ID_82547EI                    0x1019
  77 #define E1000_DEV_ID_82547EI_MOBILE             0x101A
  78 #define E1000_DEV_ID_82547GI                    0x1075
  79 #define E1000_DEV_ID_82571EB_COPPER             0x105E
  80 #define E1000_DEV_ID_82571EB_FIBER              0x105F
  81 #define E1000_DEV_ID_82571EB_SERDES             0x1060
  82 #define E1000_DEV_ID_82571EB_SERDES_DUAL        0x10D9
  83 #define E1000_DEV_ID_82571EB_SERDES_QUAD        0x10DA
  84 #define E1000_DEV_ID_82571EB_QUAD_COPPER        0x10A4
  85 #define E1000_DEV_ID_82571PT_QUAD_COPPER        0x10D5
  86 #define E1000_DEV_ID_82571EB_QUAD_FIBER         0x10A5
  87 #define E1000_DEV_ID_82571EB_QUAD_COPPER_LP     0x10BC
  88 #define E1000_DEV_ID_82572EI_COPPER             0x107D
  89 #define E1000_DEV_ID_82572EI_FIBER              0x107E
  90 #define E1000_DEV_ID_82572EI_SERDES             0x107F
  91 #define E1000_DEV_ID_82572EI                    0x10B9
  92 #define E1000_DEV_ID_82573E                     0x108B
  93 #define E1000_DEV_ID_82573E_IAMT                0x108C
  94 #define E1000_DEV_ID_82573L                     0x109A
  95 #define E1000_DEV_ID_82574L                     0x10D3
  96 #define E1000_DEV_ID_82574LA                    0x10F6
  97 #define E1000_DEV_ID_82583V                     0x150C
  98 #define E1000_DEV_ID_80003ES2LAN_COPPER_DPT     0x1096
  99 #define E1000_DEV_ID_80003ES2LAN_SERDES_DPT     0x1098
 100 #define E1000_DEV_ID_80003ES2LAN_COPPER_SPT     0x10BA
 101 #define E1000_DEV_ID_80003ES2LAN_SERDES_SPT     0x10BB
 102 #define E1000_DEV_ID_ICH8_82567V_3              0x1501
 103 #define E1000_DEV_ID_ICH8_IGP_M_AMT             0x1049
 104 #define E1000_DEV_ID_ICH8_IGP_AMT               0x104A
 105 #define E1000_DEV_ID_ICH8_IGP_C                 0x104B
 106 #define E1000_DEV_ID_ICH8_IFE                   0x104C
 107 #define E1000_DEV_ID_ICH8_IFE_GT                0x10C4
 108 #define E1000_DEV_ID_ICH8_IFE_G                 0x10C5
 109 #define E1000_DEV_ID_ICH8_IGP_M                 0x104D
 110 #define E1000_DEV_ID_ICH9_IGP_M                 0x10BF
 111 #define E1000_DEV_ID_ICH9_IGP_M_AMT             0x10F5
 112 #define E1000_DEV_ID_ICH9_IGP_M_V               0x10CB
 113 #define E1000_DEV_ID_ICH9_IGP_AMT               0x10BD
 114 #define E1000_DEV_ID_ICH9_BM                    0x10E5
 115 #define E1000_DEV_ID_ICH9_IGP_C                 0x294C
 116 #define E1000_DEV_ID_ICH9_IFE                   0x10C0
 117 #define E1000_DEV_ID_ICH9_IFE_GT                0x10C3
 118 #define E1000_DEV_ID_ICH9_IFE_G                 0x10C2
 119 #define E1000_DEV_ID_ICH10_R_BM_LM              0x10CC
 120 #define E1000_DEV_ID_ICH10_R_BM_LF              0x10CD
 121 #define E1000_DEV_ID_ICH10_R_BM_V               0x10CE
 122 #define E1000_DEV_ID_ICH10_D_BM_LM              0x10DE
 123 #define E1000_DEV_ID_ICH10_D_BM_LF              0x10DF
 124 #define E1000_DEV_ID_ICH10_D_BM_V               0x1525
 125 #define E1000_DEV_ID_PCH_M_HV_LM                0x10EA
 126 #define E1000_DEV_ID_PCH_M_HV_LC                0x10EB
 127 #define E1000_DEV_ID_PCH_D_HV_DM                0x10EF
 128 #define E1000_DEV_ID_PCH_D_HV_DC                0x10F0
 129 #define E1000_DEV_ID_PCH2_LV_LM                 0x1502
 130 #define E1000_DEV_ID_PCH2_LV_V                  0x1503
 131 #define E1000_DEV_ID_PCH_LPT_I217_LM            0x153A
 132 #define E1000_DEV_ID_PCH_LPT_I217_V             0x153B
 133 #define E1000_DEV_ID_PCH_LPTLP_I218_LM          0x155A
 134 #define E1000_DEV_ID_PCH_LPTLP_I218_V           0x1559
 135 #define E1000_DEV_ID_PCH_I218_LM2               0x15A0
 136 #define E1000_DEV_ID_PCH_I218_V2                0x15A1
 137 #define E1000_DEV_ID_PCH_I218_LM3               0x15A2 /* Wildcat Point PCH */
 138 #define E1000_DEV_ID_PCH_I218_V3                0x15A3 /* Wildcat Point PCH */
 139 #define E1000_DEV_ID_PCH_SPT_I219_LM            0x156F /* Sunrise Point PCH */
 140 #define E1000_DEV_ID_PCH_SPT_I219_V             0x1570 /* Sunrise Point PCH */
 141 #define E1000_DEV_ID_PCH_SPT_I219_LM2           0x15B7 /* Sunrise Point-H PCH */
 142 #define E1000_DEV_ID_PCH_SPT_I219_V2            0x15B8 /* Sunrise Point-H PCH */
 143 #define E1000_DEV_ID_PCH_LBG_I219_LM3           0x15B9 /* LEWISBURG PCH */
 144 #define E1000_DEV_ID_PCH_SPT_I219_LM4           0x15D7
 145 #define E1000_DEV_ID_PCH_SPT_I219_V4            0x15D8
 146 #define E1000_DEV_ID_PCH_SPT_I219_LM5           0x15E3
 147 #define E1000_DEV_ID_PCH_SPT_I219_V5            0x15D6
 148 #define E1000_DEV_ID_PCH_CNP_I219_LM6           0x15BD
 149 #define E1000_DEV_ID_PCH_CNP_I219_V6            0x15BE
 150 #define E1000_DEV_ID_PCH_CNP_I219_LM7           0x15BB
 151 #define E1000_DEV_ID_PCH_CNP_I219_V7            0x15BC
 152 #define E1000_DEV_ID_82576                      0x10C9
 153 #define E1000_DEV_ID_82576_FIBER                0x10E6
 154 #define E1000_DEV_ID_82576_SERDES               0x10E7
 155 #define E1000_DEV_ID_82576_QUAD_COPPER          0x10E8
 156 #define E1000_DEV_ID_82576_QUAD_COPPER_ET2      0x1526
 157 #define E1000_DEV_ID_82576_NS                   0x150A
 158 #define E1000_DEV_ID_82576_NS_SERDES            0x1518
 159 #define E1000_DEV_ID_82576_SERDES_QUAD          0x150D
 160 #define E1000_DEV_ID_82576_VF                   0x10CA
 161 #define E1000_DEV_ID_82576_VF_HV                0x152D
 162 #define E1000_DEV_ID_I350_VF                    0x1520
 163 #define E1000_DEV_ID_I350_VF_HV                 0x152F
 164 #define E1000_DEV_ID_82575EB_COPPER             0x10A7
 165 #define E1000_DEV_ID_82575EB_FIBER_SERDES       0x10A9
 166 #define E1000_DEV_ID_82575GB_QUAD_COPPER        0x10D6
 167 #define E1000_DEV_ID_82580_COPPER               0x150E
 168 #define E1000_DEV_ID_82580_FIBER                0x150F
 169 #define E1000_DEV_ID_82580_SERDES               0x1510
 170 #define E1000_DEV_ID_82580_SGMII                0x1511
 171 #define E1000_DEV_ID_82580_COPPER_DUAL          0x1516
 172 #define E1000_DEV_ID_82580_QUAD_FIBER           0x1527
 173 #define E1000_DEV_ID_I350_COPPER                0x1521
 174 #define E1000_DEV_ID_I350_FIBER                 0x1522
 175 #define E1000_DEV_ID_I350_SERDES                0x1523
 176 #define E1000_DEV_ID_I350_SGMII                 0x1524
 177 #define E1000_DEV_ID_I350_DA4                   0x1546
 178 #define E1000_DEV_ID_I210_COPPER                0x1533
 179 #define E1000_DEV_ID_I210_COPPER_OEM1           0x1534
 180 #define E1000_DEV_ID_I210_COPPER_IT             0x1535
 181 #define E1000_DEV_ID_I210_FIBER                 0x1536
 182 #define E1000_DEV_ID_I210_SERDES                0x1537
 183 #define E1000_DEV_ID_I210_SGMII                 0x1538
 184 #define E1000_DEV_ID_I210_COPPER_FLASHLESS      0x157B
 185 #define E1000_DEV_ID_I210_SERDES_FLASHLESS      0x157C
 186 #define E1000_DEV_ID_I211_COPPER                0x1539
 187 #define E1000_DEV_ID_I354_BACKPLANE_1GBPS       0x1F40
 188 #define E1000_DEV_ID_I354_SGMII                 0x1F41
 189 #define E1000_DEV_ID_I354_BACKPLANE_2_5GBPS     0x1F45
 190 #define E1000_DEV_ID_DH89XXCC_SGMII             0x0438
 191 #define E1000_DEV_ID_DH89XXCC_SERDES            0x043A
 192 #define E1000_DEV_ID_DH89XXCC_BACKPLANE         0x043C
 193 #define E1000_DEV_ID_DH89XXCC_SFP               0x0440
 194
 195 #define E1000_REVISION_0        0
 196 #define E1000_REVISION_1        1
 197 #define E1000_REVISION_2        2
 198 #define E1000_REVISION_3        3
 199 #define E1000_REVISION_4        4
 200
 201 #define E1000_FUNC_0            0
 202 #define E1000_FUNC_1            1
 203 #define E1000_FUNC_2            2
 204 #define E1000_FUNC_3            3
 205
 206 #define E1000_ALT_MAC_ADDRESS_OFFSET_LAN0       0
 207 #define E1000_ALT_MAC_ADDRESS_OFFSET_LAN1       3
 208 #define E1000_ALT_MAC_ADDRESS_OFFSET_LAN2       6
 209 #define E1000_ALT_MAC_ADDRESS_OFFSET_LAN3       9
 210
 211 enum e1000_mac_type {
 212         e1000_undefined = 0,
 213         e1000_82542,
 214         e1000_82543,
 215         e1000_82544,
 216         e1000_82540,
 217         e1000_82545,
 218         e1000_82545_rev_3,
 219         e1000_82546,
 220         e1000_82546_rev_3,
 221         e1000_82541,
 222         e1000_82541_rev_2,
 223         e1000_82547,
 224         e1000_82547_rev_2,
 225         e1000_82571,
 226         e1000_82572,
 227         e1000_82573,
 228         e1000_82574,
 229         e1000_82583,
 230         e1000_80003es2lan,
 231         e1000_ich8lan,
 232         e1000_ich9lan,
 233         e1000_ich10lan,
 234         e1000_pchlan,
 235         e1000_pch2lan,
 236         e1000_pch_lpt,
 237         e1000_pch_spt,
 238         e1000_pch_cnp,
 239         e1000_82575,
 240         e1000_82576,
 241         e1000_82580,
 242         e1000_i350,
 243         e1000_i354,
 244         e1000_i210,
 245         e1000_i211,
 246         e1000_vfadapt,
 247         e1000_vfadapt_i350,
 248         e1000_num_macs  /* List is 1-based, so subtract 1 for true count. */
 249 };
 250
 251 enum e1000_media_type {
 252         e1000_media_type_unknown = 0,
 253         e1000_media_type_copper = 1,
 254         e1000_media_type_fiber = 2,
 255         e1000_media_type_internal_serdes = 3,
 256         e1000_num_media_types
 257 };
 258
 259 enum e1000_nvm_type {
 260         e1000_nvm_unknown = 0,
 261         e1000_nvm_none,
 262         e1000_nvm_eeprom_spi,
 263         e1000_nvm_eeprom_microwire,
 264         e1000_nvm_flash_hw,
 265         e1000_nvm_invm,
 266         e1000_nvm_flash_sw
 267 };
 268
 269 enum e1000_nvm_override {
 270         e1000_nvm_override_none = 0,
 271         e1000_nvm_override_spi_small,
 272         e1000_nvm_override_spi_large,
 273         e1000_nvm_override_microwire_small,
 274         e1000_nvm_override_microwire_large
 275 };
 276
 277 enum e1000_phy_type {
 278         e1000_phy_unknown = 0,
 279         e1000_phy_none,
 280         e1000_phy_m88,
 281         e1000_phy_igp,
 282         e1000_phy_igp_2,
 283         e1000_phy_gg82563,
 284         e1000_phy_igp_3,
 285         e1000_phy_ife,
 286         e1000_phy_bm,
 287         e1000_phy_82578,
 288         e1000_phy_82577,
 289         e1000_phy_82579,
 290         e1000_phy_i217,
 291         e1000_phy_82580,
 292         e1000_phy_vf,
 293         e1000_phy_i210,
 294 };
 295
 296 enum e1000_bus_type {
 297         e1000_bus_type_unknown = 0,
 298         e1000_bus_type_pci,
 299         e1000_bus_type_pcix,
 300         e1000_bus_type_pci_express,
 301         e1000_bus_type_reserved
 302 };
 303
 304 enum e1000_bus_speed {
 305         e1000_bus_speed_unknown = 0,
 306         e1000_bus_speed_33,
 307         e1000_bus_speed_66,
 308         e1000_bus_speed_100,
 309         e1000_bus_speed_120,
 310         e1000_bus_speed_133,
 311         e1000_bus_speed_2500,
 312         e1000_bus_speed_5000,
 313         e1000_bus_speed_reserved
 314 };
 315
 316 enum e1000_bus_width {
 317         e1000_bus_width_unknown = 0,
 318         e1000_bus_width_pcie_x1,
 319         e1000_bus_width_pcie_x2,
 320         e1000_bus_width_pcie_x4 = 4,
 321         e1000_bus_width_pcie_x8 = 8,
 322         e1000_bus_width_32,
 323         e1000_bus_width_64,
 324         e1000_bus_width_reserved
 325 };
 326
 327 enum e1000_1000t_rx_status {
 328         e1000_1000t_rx_status_not_ok = 0,
 329         e1000_1000t_rx_status_ok,
 330         e1000_1000t_rx_status_undefined = 0xFF
 331 };
 332
 333 enum e1000_rev_polarity {
 334         e1000_rev_polarity_normal = 0,
 335         e1000_rev_polarity_reversed,
 336         e1000_rev_polarity_undefined = 0xFF
 337 };
 338
 339 enum e1000_fc_mode {
 340         e1000_fc_none = 0,
 341         e1000_fc_rx_pause,
 342         e1000_fc_tx_pause,
 343         e1000_fc_full,
 344         e1000_fc_default = 0xFF
 345 };
 346
 347 enum e1000_ffe_config {
 348         e1000_ffe_config_enabled = 0,
 349         e1000_ffe_config_active,
 350         e1000_ffe_config_blocked
 351 };
 352
 353 enum e1000_dsp_config {
 354         e1000_dsp_config_disabled = 0,
 355         e1000_dsp_config_enabled,
 356         e1000_dsp_config_activated,
 357         e1000_dsp_config_undefined = 0xFF
 358 };
 359
 360 enum e1000_ms_type {
 361         e1000_ms_hw_default = 0,
 362         e1000_ms_force_master,
 363         e1000_ms_force_slave,
 364         e1000_ms_auto
 365 };
 366
 367 enum e1000_smart_speed {
 368         e1000_smart_speed_default = 0,
 369         e1000_smart_speed_on,
 370         e1000_smart_speed_off
 371 };
 372
 373 enum e1000_serdes_link_state {
 374         e1000_serdes_link_down = 0,
 375         e1000_serdes_link_autoneg_progress,
 376         e1000_serdes_link_autoneg_complete,
 377         e1000_serdes_link_forced_up
 378 };
 379
 380 #define __le16 u16
 381 #define __le32 u32
 382 #define __le64 u64
 383 /* Receive Descriptor */
 384 struct e1000_rx_desc {
 385         __le64 buffer_addr; /* Address of the descriptor's data buffer */
 386         __le16 length;      /* Length of data DMAed into data buffer */
 387         __le16 csum; /* Packet checksum */
 388         u8  status;  /* Descriptor status */
 389         u8  errors;  /* Descriptor Errors */
 390         __le16 special;
 391 };
 392
 393 /* Receive Descriptor - Extended */
 394 union e1000_rx_desc_extended {
 395         struct {
 396                 __le64 buffer_addr;
 397                 __le64 reserved;
 398         } read;
 399         struct {
 400                 struct {
 401                         __le32 mrq; /* Multiple Rx Queues */
 402                         union {
 403                                 __le32 rss; /* RSS Hash */
 404                                 struct {
 405                                         __le16 ip_id;  /* IP id */
 406                                         __le16 csum;   /* Packet Checksum */
 407                                 } csum_ip;
 408                         } hi_dword;
 409                 } lower;
 410                 struct {
 411                         __le32 status_error;  /* ext status/error */
 412                         __le16 length;
 413                         __le16 vlan; /* VLAN tag */
 414                 } upper;
 415         } wb;  /* writeback */
 416 };
 417
 418 #define MAX_PS_BUFFERS 4
 419
 420 /* Number of packet split data buffers (not including the header buffer) */
 421 #define PS_PAGE_BUFFERS (MAX_PS_BUFFERS - 1)
 422
 423 /* Receive Descriptor - Packet Split */
 424 union e1000_rx_desc_packet_split {
 425         struct {
 426                 /* one buffer for protocol header(s), three data buffers */
 427                 __le64 buffer_addr[MAX_PS_BUFFERS];
 428         } read;
 429         struct {
 430                 struct {
 431                         __le32 mrq;  /* Multiple Rx Queues */
 432                         union {
 433                                 __le32 rss; /* RSS Hash */
 434                                 struct {
 435                                         __le16 ip_id;    /* IP id */
 436                                         __le16 csum;     /* Packet Checksum */
 437                                 } csum_ip;
 438                         } hi_dword;
 439                 } lower;
 440                 struct {
 441                         __le32 status_error;  /* ext status/error */
 442                         __le16 length0;  /* length of buffer 0 */
 443                         __le16 vlan;  /* VLAN tag */
 444                 } middle;
 445                 struct {
 446                         __le16 header_status;
 447                         /* length of buffers 1-3 */
 448                         __le16 length[PS_PAGE_BUFFERS];
 449                 } upper;
 450                 __le64 reserved;
 451         } wb; /* writeback */
 452 };
 453
 454 /* Transmit Descriptor */
 455 struct e1000_tx_desc {
 456         __le64 buffer_addr;   /* Address of the descriptor's data buffer */
 457         union {
 458                 __le32 data;
 459                 struct {
 460                         __le16 length;  /* Data buffer length */
 461                         u8 cso;  /* Checksum offset */
 462                         u8 cmd;  /* Descriptor control */
 463                 } flags;
 464         } lower;
 465         union {
 466                 __le32 data;
 467                 struct {
 468                         u8 status; /* Descriptor status */
 469                         u8 css;  /* Checksum start */
 470                         __le16 special;
 471                 } fields;
 472         } upper;
 473 };
 474
 475 /* Offload Context Descriptor */
 476 struct e1000_context_desc {
 477         union {
 478                 __le32 ip_config;
 479                 struct {
 480                         u8 ipcss;  /* IP checksum start */
 481                         u8 ipcso;  /* IP checksum offset */
 482                         __le16 ipcse;  /* IP checksum end */
 483                 } ip_fields;
 484         } lower_setup;
 485         union {
 486                 __le32 tcp_config;
 487                 struct {
 488                         u8 tucss;  /* TCP checksum start */
 489                         u8 tucso;  /* TCP checksum offset */
 490                         __le16 tucse;  /* TCP checksum end */
 491                 } tcp_fields;
 492         } upper_setup;
 493         __le32 cmd_and_length;
 494         union {
 495                 __le32 data;
 496                 struct {
 497                         u8 status;  /* Descriptor status */
 498                         u8 hdr_len;  /* Header length */
 499                         __le16 mss;  /* Maximum segment size */
 500                 } fields;
 501         } tcp_seg_setup;
 502 };
 503
 504 /* Offload data descriptor */
 505 struct e1000_data_desc {
 506         __le64 buffer_addr;  /* Address of the descriptor's buffer address */
 507         union {
 508                 __le32 data;
 509                 struct {
 510                         __le16 length;  /* Data buffer length */
 511                         u8 typ_len_ext;
 512                         u8 cmd;
 513                 } flags;
 514         } lower;
 515         union {
 516                 __le32 data;
 517                 struct {
 518                         u8 status;  /* Descriptor status */
 519                         u8 popts;  /* Packet Options */
 520                         __le16 special;
 521                 } fields;
 522         } upper;
 523 };
 524
 525 /* Statistics counters collected by the MAC */
 526 struct e1000_hw_stats {
 527         u64 crcerrs;
 528         u64 algnerrc;
 529         u64 symerrs;
 530         u64 rxerrc;
 531         u64 mpc;
 532         u64 scc;
 533         u64 ecol;
 534         u64 mcc;
 535         u64 latecol;
 536         u64 colc;
 537         u64 dc;
 538         u64 tncrs;
 539         u64 sec;
 540         u64 cexterr;
 541         u64 rlec;
 542         u64 xonrxc;
 543         u64 xontxc;
 544         u64 xoffrxc;
 545         u64 xofftxc;
 546         u64 fcruc;
 547         u64 prc64;
 548         u64 prc127;
 549         u64 prc255;
 550         u64 prc511;
 551         u64 prc1023;
 552         u64 prc1522;
 553         u64 gprc;
 554         u64 bprc;
 555         u64 mprc;
 556         u64 gptc;
 557         u64 gorc;
 558         u64 gotc;
 559         u64 rnbc;
 560         u64 ruc;
 561         u64 rfc;
 562         u64 roc;
 563         u64 rjc;
 564         u64 mgprc;
 565         u64 mgpdc;
 566         u64 mgptc;
 567         u64 tor;
 568         u64 tot;
 569         u64 tpr;
 570         u64 tpt;
 571         u64 ptc64;
 572         u64 ptc127;
 573         u64 ptc255;
 574         u64 ptc511;
 575         u64 ptc1023;
 576         u64 ptc1522;
 577         u64 mptc;
 578         u64 bptc;
 579         u64 tsctc;
 580         u64 tsctfc;
 581         u64 iac;
 582         u64 icrxptc;
 583         u64 icrxatc;
 584         u64 ictxptc;
 585         u64 ictxatc;
 586         u64 ictxqec;
 587         u64 ictxqmtc;
 588         u64 icrxdmtc;
 589         u64 icrxoc;
 590         u64 cbtmpc;
 591         u64 htdpmc;
 592         u64 cbrdpc;
 593         u64 cbrmpc;
 594         u64 rpthc;
 595         u64 hgptc;
 596         u64 htcbdpc;
 597         u64 hgorc;
 598         u64 hgotc;
 599         u64 lenerrs;
 600         u64 scvpc;
 601         u64 hrmpc;
 602         u64 doosync;
 603         u64 o2bgptc;
 604         u64 o2bspc;
 605         u64 b2ospc;
 606         u64 b2ogprc;
 607 };
 608
 609 struct e1000_vf_stats {
 610         u64 base_gprc;
 611         u64 base_gptc;
 612         u64 base_gorc;
 613         u64 base_gotc;
 614         u64 base_mprc;
 615         u64 base_gotlbc;
 616         u64 base_gptlbc;
 617         u64 base_gorlbc;
 618         u64 base_gprlbc;
 619
 620         u32 last_gprc;
 621         u32 last_gptc;
 622         u32 last_gorc;
 623         u32 last_gotc;
 624         u32 last_mprc;
 625         u32 last_gotlbc;
 626         u32 last_gptlbc;
 627         u32 last_gorlbc;
 628         u32 last_gprlbc;
 629
 630         u64 gprc;
 631         u64 gptc;
 632         u64 gorc;
 633         u64 gotc;
 634         u64 mprc;
 635         u64 gotlbc;
 636         u64 gptlbc;
 637         u64 gorlbc;
 638         u64 gprlbc;
 639 };
 640
 641 struct e1000_phy_stats {
 642         u32 idle_errors;
 643         u32 receive_errors;
 644 };
 645
 646 struct e1000_host_mng_dhcp_cookie {
 647         u32 signature;
 648         u8  status;
 649         u8  reserved0;
 650         u16 vlan_id;
 651         u32 reserved1;
 652         u16 reserved2;
 653         u8  reserved3;
 654         u8  checksum;
 655 };
 656
 657 /* Host Interface "Rev 1" */
 658 struct e1000_host_command_header {
 659         u8 command_id;
 660         u8 command_length;
 661         u8 command_options;
 662         u8 checksum;
 663 };
 664
 665 #define E1000_HI_MAX_DATA_LENGTH        252
 666 struct e1000_host_command_info {
 667         struct e1000_host_command_header command_header;
 668         u8 command_data[E1000_HI_MAX_DATA_LENGTH];
 669 };
 670
 671 /* Host Interface "Rev 2" */
 672 struct e1000_host_mng_command_header {
 673         u8  command_id;
 674         u8  checksum;
 675         u16 reserved1;
 676         u16 reserved2;
 677         u16 command_length;
 678 };
 679
 680 #define E1000_HI_MAX_MNG_DATA_LENGTH    0x6F8
 681 struct e1000_host_mng_command_info {
 682         struct e1000_host_mng_command_header command_header;
 683         u8 command_data[E1000_HI_MAX_MNG_DATA_LENGTH];
 684 };
 685
 686 #include "e1000_mac.h"
 687 #include "e1000_phy.h"
 688 #include "e1000_nvm.h"
 689 #include "e1000_manage.h"
 690 #include "e1000_mbx.h"
 691
 692 /* Function pointers for the MAC. */
 693 struct e1000_mac_operations {
 694         s32  (*init_params)(struct e1000_hw *);
 695         s32  (*id_led_init)(struct e1000_hw *);
 696         s32  (*blink_led)(struct e1000_hw *);
 697         bool (*check_mng_mode)(struct e1000_hw *);
 698         s32  (*check_for_link)(struct e1000_hw *);
 699         s32  (*cleanup_led)(struct e1000_hw *);
 700         void (*clear_hw_cntrs)(struct e1000_hw *);
 701         void (*clear_vfta)(struct e1000_hw *);
 702         s32  (*get_bus_info)(struct e1000_hw *);
 703         void (*set_lan_id)(struct e1000_hw *);
 704         s32  (*get_link_up_info)(struct e1000_hw *, u16 *, u16 *);
 705         s32  (*led_on)(struct e1000_hw *);
 706         s32  (*led_off)(struct e1000_hw *);
 707         void (*update_mc_addr_list)(struct e1000_hw *, u8 *, u32);
 708         s32  (*reset_hw)(struct e1000_hw *);
 709         s32  (*init_hw)(struct e1000_hw *);
 710         void (*shutdown_serdes)(struct e1000_hw *);
 711         void (*power_up_serdes)(struct e1000_hw *);
 712         s32  (*setup_link)(struct e1000_hw *);
 713         s32  (*setup_physical_interface)(struct e1000_hw *);
 714         s32  (*setup_led)(struct e1000_hw *);
 715         void (*write_vfta)(struct e1000_hw *, u32, u32);
 716         void (*config_collision_dist)(struct e1000_hw *);
 717         int  (*rar_set)(struct e1000_hw *, u8*, u32);
 718         s32  (*read_mac_addr)(struct e1000_hw *);
 719         s32  (*validate_mdi_setting)(struct e1000_hw *);
 720         s32  (*acquire_swfw_sync)(struct e1000_hw *, u16);
 721         void (*release_swfw_sync)(struct e1000_hw *, u16);
 722 };
 723
 724 /* When to use various PHY register access functions:
 725  *
 726  *                 Func   Caller
 727  *   Function      Does   Does    When to use
 728  *   ~~~~~~~~~~~~  ~~~~~  ~~~~~~  ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 729  *   X_reg         L,P,A  n/a     for simple PHY reg accesses
 730  *   X_reg_locked  P,A    L       for multiple accesses of different regs
 731  *                                on different pages
 732  *   X_reg_page    A      L,P     for multiple accesses of different regs
 733  *                                on the same page
 734  *
 735  * Where X=[read|write], L=locking, P=sets page, A=register access
 736  *
 737  */
 738 struct e1000_phy_operations {
 739         s32  (*init_params)(struct e1000_hw *);
 740         s32  (*acquire)(struct e1000_hw *);
 741         s32  (*cfg_on_link_up)(struct e1000_hw *);
 742         s32  (*check_polarity)(struct e1000_hw *);
 743         s32  (*check_reset_block)(struct e1000_hw *);
 744         s32  (*commit)(struct e1000_hw *);
 745         s32  (*force_speed_duplex)(struct e1000_hw *);
 746         s32  (*get_cfg_done)(struct e1000_hw *hw);
 747         s32  (*get_cable_length)(struct e1000_hw *);
 748         s32  (*get_info)(struct e1000_hw *);
 749         s32  (*set_page)(struct e1000_hw *, u16);
 750         s32  (*read_reg)(struct e1000_hw *, u32, u16 *);
 751         s32  (*read_reg_locked)(struct e1000_hw *, u32, u16 *);
 752         s32  (*read_reg_page)(struct e1000_hw *, u32, u16 *);
 753         void (*release)(struct e1000_hw *);
 754         s32  (*reset)(struct e1000_hw *);
 755         s32  (*set_d0_lplu_state)(struct e1000_hw *, bool);
 756         s32  (*set_d3_lplu_state)(struct e1000_hw *, bool);
 757         s32  (*write_reg)(struct e1000_hw *, u32, u16);
 758         s32  (*write_reg_locked)(struct e1000_hw *, u32, u16);
 759         s32  (*write_reg_page)(struct e1000_hw *, u32, u16);
 760         void (*power_up)(struct e1000_hw *);
 761         void (*power_down)(struct e1000_hw *);
 762         s32 (*read_i2c_byte)(struct e1000_hw *, u8, u8, u8 *);
 763         s32 (*write_i2c_byte)(struct e1000_hw *, u8, u8, u8);
 764 };
 765
 766 /* Function pointers for the NVM. */
 767 struct e1000_nvm_operations {
 768         s32  (*init_params)(struct e1000_hw *);
 769         s32  (*acquire)(struct e1000_hw *);
 770         s32  (*read)(struct e1000_hw *, u16, u16, u16 *);
 771         void (*release)(struct e1000_hw *);
 772         void (*reload)(struct e1000_hw *);
 773         s32  (*update)(struct e1000_hw *);
 774         s32  (*valid_led_default)(struct e1000_hw *, u16 *);
 775         s32  (*validate)(struct e1000_hw *);
 776         s32  (*write)(struct e1000_hw *, u16, u16, u16 *);
 777 };
 778
 779 struct e1000_mac_info {
 780         struct e1000_mac_operations ops;
 781         u8 addr[ETH_ADDR_LEN];
 782         u8 perm_addr[ETH_ADDR_LEN];
 783
 784         enum e1000_mac_type type;
 785
 786         u32 collision_delta;
 787         u32 ledctl_default;
 788         u32 ledctl_mode1;
 789         u32 ledctl_mode2;
 790         u32 mc_filter_type;
 791         u32 tx_packet_delta;
 792         u32 txcw;
 793
 794         u16 current_ifs_val;
 795         u16 ifs_max_val;
 796         u16 ifs_min_val;
 797         u16 ifs_ratio;
 798         u16 ifs_step_size;
 799         u16 mta_reg_count;
 800         u16 uta_reg_count;
 801
 802         /* Maximum size of the MTA register table in all supported adapters */
 803 #define MAX_MTA_REG 128
 804         u32 mta_shadow[MAX_MTA_REG];
 805         u16 rar_entry_count;
 806
 807         u8  forced_speed_duplex;
 808
 809         bool adaptive_ifs;
 810         bool has_fwsm;
 811         bool arc_subsystem_valid;
 812         bool asf_firmware_present;
 813         bool autoneg;
 814         bool autoneg_failed;
 815         bool get_link_status;
 816         bool in_ifs_mode;
 817         bool report_tx_early;
 818         enum e1000_serdes_link_state serdes_link_state;
 819         bool serdes_has_link;
 820         bool tx_pkt_filtering;
 821 };
 822
 823 struct e1000_phy_info {
 824         struct e1000_phy_operations ops;
 825         enum e1000_phy_type type;
 826
 827         enum e1000_1000t_rx_status local_rx;
 828         enum e1000_1000t_rx_status remote_rx;
 829         enum e1000_ms_type ms_type;
 830         enum e1000_ms_type original_ms_type;
 831         enum e1000_rev_polarity cable_polarity;
 832         enum e1000_smart_speed smart_speed;
 833
 834         u32 addr;
 835         u32 id;
 836         u32 reset_delay_us; /* in usec */
 837         u32 revision;
 838
 839         enum e1000_media_type media_type;
 840
 841         u16 autoneg_advertised;
 842         u16 autoneg_mask;
 843         u16 cable_length;
 844         u16 max_cable_length;
 845         u16 min_cable_length;
 846
 847         u8 mdix;
 848
 849         bool disable_polarity_correction;
 850         bool is_mdix;
 851         bool polarity_correction;
 852         bool speed_downgraded;
 853         bool autoneg_wait_to_complete;
 854 };
 855
 856 struct e1000_nvm_info {
 857         struct e1000_nvm_operations ops;
 858         enum e1000_nvm_type type;
 859         enum e1000_nvm_override override;
 860
 861         u32 flash_bank_size;
 862         u32 flash_base_addr;
 863
 864         u16 word_size;
 865         u16 delay_usec;
 866         u16 address_bits;
 867         u16 opcode_bits;
 868         u16 page_size;
 869 };
 870
 871 struct e1000_bus_info {
 872         enum e1000_bus_type type;
 873         enum e1000_bus_speed speed;
 874         enum e1000_bus_width width;
 875
 876         u16 func;
 877         u16 pci_cmd_word;
 878 };
 879
 880 struct e1000_fc_info {
 881         u32 high_water;  /* Flow control high-water mark */
 882         u32 low_water;  /* Flow control low-water mark */
 883         u16 pause_time;  /* Flow control pause timer */
 884         u16 refresh_time;  /* Flow control refresh timer */
 885         bool send_xon;  /* Flow control send XON */
 886         bool strict_ieee;  /* Strict IEEE mode */
 887         enum e1000_fc_mode current_mode;  /* FC mode in effect */
 888         enum e1000_fc_mode requested_mode;  /* FC mode requested by caller */
 889 };
 890
 891 struct e1000_mbx_operations {
 892         s32 (*init_params)(struct e1000_hw *hw);
 893         s32 (*read)(struct e1000_hw *, u32 *, u16,  u16);
 894         s32 (*write)(struct e1000_hw *, u32 *, u16, u16);
 895         s32 (*read_posted)(struct e1000_hw *, u32 *, u16,  u16);
 896         s32 (*write_posted)(struct e1000_hw *, u32 *, u16, u16);
 897         s32 (*check_for_msg)(struct e1000_hw *, u16);
 898         s32 (*check_for_ack)(struct e1000_hw *, u16);
 899         s32 (*check_for_rst)(struct e1000_hw *, u16);
 900 };
 901
 902 struct e1000_mbx_stats {
 903         u32 msgs_tx;
 904         u32 msgs_rx;
 905
 906         u32 acks;
 907         u32 reqs;
 908         u32 rsts;
 909 };
 910
 911 struct e1000_mbx_info {
 912         struct e1000_mbx_operations ops;
 913         struct e1000_mbx_stats stats;
 914         u32 timeout;
 915         u32 usec_delay;
 916         u16 size;
 917 };
 918
 919 struct e1000_dev_spec_82541 {
 920         enum e1000_dsp_config dsp_config;
 921         enum e1000_ffe_config ffe_config;
 922         u16 spd_default;
 923         bool phy_init_script;
 924 };
 925
 926 struct e1000_dev_spec_82542 {
 927         bool dma_fairness;
 928 };
 929
 930 struct e1000_dev_spec_82543 {
 931         u32  tbi_compatibility;
 932         bool dma_fairness;
 933         bool init_phy_disabled;
 934 };
 935
 936 struct e1000_dev_spec_82571 {
 937         bool laa_is_present;
 938         u32 smb_counter;
 939         E1000_MUTEX swflag_mutex;
 940 };
 941
 942 struct e1000_dev_spec_80003es2lan {
 943         bool  mdic_wa_enable;
 944 };
 945
 946 struct e1000_shadow_ram {
 947         u16  value;
 948         bool modified;
 949 };
 950
 951 #define E1000_SHADOW_RAM_WORDS          2048
 952
 953 #ifdef ULP_SUPPORT
 954 /* I218 PHY Ultra Low Power (ULP) states */
 955 enum e1000_ulp_state {
 956         e1000_ulp_state_unknown,
 957         e1000_ulp_state_off,
 958         e1000_ulp_state_on,
 959 };
 960
 961 #endif /* ULP_SUPPORT */
 962 struct e1000_dev_spec_ich8lan {
 963         bool kmrn_lock_loss_workaround_enabled;
 964         struct e1000_shadow_ram shadow_ram[E1000_SHADOW_RAM_WORDS];
 965         E1000_MUTEX nvm_mutex;
 966         E1000_MUTEX swflag_mutex;
 967         bool nvm_k1_enabled;
 968         bool disable_k1_off;
 969         bool eee_disable;
 970         u16 eee_lp_ability;
 971 #ifdef ULP_SUPPORT
 972         enum e1000_ulp_state ulp_state;
 973         bool ulp_capability_disabled;
 974         bool during_suspend_flow;
 975         bool during_dpg_exit;
 976 #endif /* ULP_SUPPORT */
 977         u16 lat_enc;
 978         u16 max_ltr_enc;
 979         bool smbus_disable;
 980 };
 981
 982 struct e1000_dev_spec_82575 {
 983         bool sgmii_active;
 984         bool global_device_reset;
 985         bool eee_disable;
 986         bool module_plugged;
 987         bool clear_semaphore_once;
 988         u32 mtu;
 989         struct sfp_e1000_flags eth_flags;
 990         u8 media_port;
 991         bool media_changed;
 992 };
 993
 994 struct e1000_dev_spec_vf {
 995         u32 vf_number;
 996         u32 v2p_mailbox;
 997 };
 998
 999 struct e1000_hw {
1000         void *back;
1001
1002         u8 *hw_addr;
1003         u8 *flash_address;
1004         unsigned long io_base;
1005
1006         struct e1000_mac_info  mac;
1007         struct e1000_fc_info   fc;
1008         struct e1000_phy_info  phy;
1009         struct e1000_nvm_info  nvm;
1010         struct e1000_bus_info  bus;
1011         struct e1000_mbx_info mbx;
1012         struct e1000_host_mng_dhcp_cookie mng_cookie;
1013
1014         union {
1015                 struct e1000_dev_spec_82541 _82541;
1016                 struct e1000_dev_spec_82542 _82542;
1017                 struct e1000_dev_spec_82543 _82543;
1018                 struct e1000_dev_spec_82571 _82571;
1019                 struct e1000_dev_spec_80003es2lan _80003es2lan;
1020                 struct e1000_dev_spec_ich8lan ich8lan;
1021                 struct e1000_dev_spec_82575 _82575;
1022                 struct e1000_dev_spec_vf vf;
1023         } dev_spec;
1024
1025         u16 device_id;
1026         u16 subsystem_vendor_id;
1027         u16 subsystem_device_id;
1028         u16 vendor_id;
1029
1030         u8  revision_id;
1031 };
1032
1033 #include "e1000_82541.h"
1034 #include "e1000_82543.h"
1035 #include "e1000_82571.h"
1036 #include "e1000_80003es2lan.h"
1037 #include "e1000_ich8lan.h"
1038 #include "e1000_82575.h"
1039 #include "e1000_i210.h"
1040
1041 /* These functions must be implemented by drivers */
1042 void e1000_pci_clear_mwi(struct e1000_hw *hw);
1043 void e1000_pci_set_mwi(struct e1000_hw *hw);
1044 s32  e1000_read_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value);
1045 s32  e1000_write_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value);
1046 void e1000_read_pci_cfg(struct e1000_hw *hw, u32 reg, u16 *value);
1047 void e1000_write_pci_cfg(struct e1000_hw *hw, u32 reg, u16 *value);
1048
1049 #endif