drivers/net/e1000/base/e1000_ich8lan.c

   1 /*******************************************************************************
   2
   3 Copyright (c) 2001-2015, Intel Corporation
   4 All rights reserved.
   5
   6 Redistribution and use in source and binary forms, with or without
   7 modification, are permitted provided that the following conditions are met:
   8
   9  1. Redistributions of source code must retain the above copyright notice,
  10     this list of conditions and the following disclaimer.
  11
  12  2. Redistributions in binary form must reproduce the above copyright
  13     notice, this list of conditions and the following disclaimer in the
  14     documentation and/or other materials provided with the distribution.
  15
  16  3. Neither the name of the Intel Corporation nor the names of its
  17     contributors may be used to endorse or promote products derived from
  18     this software without specific prior written permission.
  19
  20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
  24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  30 POSSIBILITY OF SUCH DAMAGE.
  31
  32 ***************************************************************************/
  33
  34 /* 82562G 10/100 Network Connection
  35  * 82562G-2 10/100 Network Connection
  36  * 82562GT 10/100 Network Connection
  37  * 82562GT-2 10/100 Network Connection
  38  * 82562V 10/100 Network Connection
  39  * 82562V-2 10/100 Network Connection
  40  * 82566DC-2 Gigabit Network Connection
  41  * 82566DC Gigabit Network Connection
  42  * 82566DM-2 Gigabit Network Connection
  43  * 82566DM Gigabit Network Connection
  44  * 82566MC Gigabit Network Connection
  45  * 82566MM Gigabit Network Connection
  46  * 82567LM Gigabit Network Connection
  47  * 82567LF Gigabit Network Connection
  48  * 82567V Gigabit Network Connection
  49  * 82567LM-2 Gigabit Network Connection
  50  * 82567LF-2 Gigabit Network Connection
  51  * 82567V-2 Gigabit Network Connection
  52  * 82567LF-3 Gigabit Network Connection
  53  * 82567LM-3 Gigabit Network Connection
  54  * 82567LM-4 Gigabit Network Connection
  55  * 82577LM Gigabit Network Connection
  56  * 82577LC Gigabit Network Connection
  57  * 82578DM Gigabit Network Connection
  58  * 82578DC Gigabit Network Connection
  59  * 82579LM Gigabit Network Connection
  60  * 82579V Gigabit Network Connection
  61  * Ethernet Connection I217-LM
  62  * Ethernet Connection I217-V
  63  * Ethernet Connection I218-V
  64  * Ethernet Connection I218-LM
  65  * Ethernet Connection (2) I218-LM
  66  * Ethernet Connection (2) I218-V
  67  * Ethernet Connection (3) I218-LM
  68  * Ethernet Connection (3) I218-V
  69  */
  70
  71 #include "e1000_api.h"
  72
  73 STATIC s32 e1000_oem_bits_config_ich8lan(struct e1000_hw *hw, bool d0_state);
  74 STATIC s32  e1000_acquire_swflag_ich8lan(struct e1000_hw *hw);
  75 STATIC void e1000_release_swflag_ich8lan(struct e1000_hw *hw);
  76 STATIC s32  e1000_acquire_nvm_ich8lan(struct e1000_hw *hw);
  77 STATIC void e1000_release_nvm_ich8lan(struct e1000_hw *hw);
  78 STATIC bool e1000_check_mng_mode_ich8lan(struct e1000_hw *hw);
  79 STATIC bool e1000_check_mng_mode_pchlan(struct e1000_hw *hw);
  80 STATIC int  e1000_rar_set_pch2lan(struct e1000_hw *hw, u8 *addr, u32 index);
  81 STATIC int  e1000_rar_set_pch_lpt(struct e1000_hw *hw, u8 *addr, u32 index);
  82 STATIC s32 e1000_sw_lcd_config_ich8lan(struct e1000_hw *hw);
  83 #ifndef NO_NON_BLOCKING_PHY_MTA_UPDATE_SUPPORT
  84 STATIC void e1000_update_mc_addr_list_pch2lan(struct e1000_hw *hw,
  85                                               u8 *mc_addr_list,
  86                                               u32 mc_addr_count);
  87 #endif /* NO_NON_BLOCKING_PHY_MTA_UPDATE_SUPPORT */
  88 STATIC s32  e1000_check_reset_block_ich8lan(struct e1000_hw *hw);
  89 STATIC s32  e1000_phy_hw_reset_ich8lan(struct e1000_hw *hw);
  90 STATIC s32  e1000_set_lplu_state_pchlan(struct e1000_hw *hw, bool active);
  91 STATIC s32  e1000_set_d0_lplu_state_ich8lan(struct e1000_hw *hw,
  92                                             bool active);
  93 STATIC s32  e1000_set_d3_lplu_state_ich8lan(struct e1000_hw *hw,
  94                                             bool active);
  95 STATIC s32  e1000_read_nvm_ich8lan(struct e1000_hw *hw, u16 offset,
  96                                    u16 words, u16 *data);
  97 STATIC s32  e1000_write_nvm_ich8lan(struct e1000_hw *hw, u16 offset,
  98                                     u16 words, u16 *data);
  99 STATIC s32  e1000_validate_nvm_checksum_ich8lan(struct e1000_hw *hw);
 100 STATIC s32  e1000_update_nvm_checksum_ich8lan(struct e1000_hw *hw);
 101 STATIC s32  e1000_valid_led_default_ich8lan(struct e1000_hw *hw,
 102                                             u16 *data);
 103 STATIC s32 e1000_id_led_init_pchlan(struct e1000_hw *hw);
 104 STATIC s32  e1000_get_bus_info_ich8lan(struct e1000_hw *hw);
 105 STATIC s32  e1000_reset_hw_ich8lan(struct e1000_hw *hw);
 106 STATIC s32  e1000_init_hw_ich8lan(struct e1000_hw *hw);
 107 STATIC s32  e1000_setup_link_ich8lan(struct e1000_hw *hw);
 108 STATIC s32  e1000_setup_copper_link_ich8lan(struct e1000_hw *hw);
 109 STATIC s32  e1000_setup_copper_link_pch_lpt(struct e1000_hw *hw);
 110 STATIC s32  e1000_get_link_up_info_ich8lan(struct e1000_hw *hw,
 111                                            u16 *speed, u16 *duplex);
 112 STATIC s32  e1000_cleanup_led_ich8lan(struct e1000_hw *hw);
 113 STATIC s32  e1000_led_on_ich8lan(struct e1000_hw *hw);
 114 STATIC s32  e1000_led_off_ich8lan(struct e1000_hw *hw);
 115 STATIC s32  e1000_k1_gig_workaround_hv(struct e1000_hw *hw, bool link);
 116 STATIC s32  e1000_setup_led_pchlan(struct e1000_hw *hw);
 117 STATIC s32  e1000_cleanup_led_pchlan(struct e1000_hw *hw);
 118 STATIC s32  e1000_led_on_pchlan(struct e1000_hw *hw);
 119 STATIC s32  e1000_led_off_pchlan(struct e1000_hw *hw);
 120 STATIC void e1000_clear_hw_cntrs_ich8lan(struct e1000_hw *hw);
 121 STATIC s32  e1000_erase_flash_bank_ich8lan(struct e1000_hw *hw, u32 bank);
 122 STATIC void e1000_initialize_hw_bits_ich8lan(struct e1000_hw *hw);
 123 STATIC s32  e1000_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw);
 124 STATIC s32  e1000_read_flash_byte_ich8lan(struct e1000_hw *hw,
 125                                           u32 offset, u8 *data);
 126 STATIC s32  e1000_read_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
 127                                           u8 size, u16 *data);
 128 STATIC s32  e1000_read_flash_word_ich8lan(struct e1000_hw *hw,
 129                                           u32 offset, u16 *data);
 130 STATIC s32  e1000_retry_write_flash_byte_ich8lan(struct e1000_hw *hw,
 131                                                  u32 offset, u8 byte);
 132 STATIC s32 e1000_get_cfg_done_ich8lan(struct e1000_hw *hw);
 133 STATIC void e1000_power_down_phy_copper_ich8lan(struct e1000_hw *hw);
 134 STATIC s32 e1000_check_for_copper_link_ich8lan(struct e1000_hw *hw);
 135 STATIC s32 e1000_set_mdio_slow_mode_hv(struct e1000_hw *hw);
 136 STATIC s32 e1000_k1_workaround_lv(struct e1000_hw *hw);
 137 STATIC void e1000_gate_hw_phy_config_ich8lan(struct e1000_hw *hw, bool gate);
 138
 139 /* ICH GbE Flash Hardware Sequencing Flash Status Register bit breakdown */
 140 /* Offset 04h HSFSTS */
 141 union ich8_hws_flash_status {
 142         struct ich8_hsfsts {
 143                 u16 flcdone:1; /* bit 0 Flash Cycle Done */
 144                 u16 flcerr:1; /* bit 1 Flash Cycle Error */
 145                 u16 dael:1; /* bit 2 Direct Access error Log */
 146                 u16 berasesz:2; /* bit 4:3 Sector Erase Size */
 147                 u16 flcinprog:1; /* bit 5 flash cycle in Progress */
 148                 u16 reserved1:2; /* bit 13:6 Reserved */
 149                 u16 reserved2:6; /* bit 13:6 Reserved */
 150                 u16 fldesvalid:1; /* bit 14 Flash Descriptor Valid */
 151                 u16 flockdn:1; /* bit 15 Flash Config Lock-Down */
 152         } hsf_status;
 153         u16 regval;
 154 };
 155
 156 /* ICH GbE Flash Hardware Sequencing Flash control Register bit breakdown */
 157 /* Offset 06h FLCTL */
 158 union ich8_hws_flash_ctrl {
 159         struct ich8_hsflctl {
 160                 u16 flcgo:1;   /* 0 Flash Cycle Go */
 161                 u16 flcycle:2;   /* 2:1 Flash Cycle */
 162                 u16 reserved:5;   /* 7:3 Reserved  */
 163                 u16 fldbcount:2;   /* 9:8 Flash Data Byte Count */
 164                 u16 flockdn:6;   /* 15:10 Reserved */
 165         } hsf_ctrl;
 166         u16 regval;
 167 };
 168
 169 /* ICH Flash Region Access Permissions */
 170 union ich8_hws_flash_regacc {
 171         struct ich8_flracc {
 172                 u32 grra:8; /* 0:7 GbE region Read Access */
 173                 u32 grwa:8; /* 8:15 GbE region Write Access */
 174                 u32 gmrag:8; /* 23:16 GbE Master Read Access Grant */
 175                 u32 gmwag:8; /* 31:24 GbE Master Write Access Grant */
 176         } hsf_flregacc;
 177         u16 regval;
 178 };
 179
 180 /**
 181  *  e1000_phy_is_accessible_pchlan - Check if able to access PHY registers
 182  *  @hw: pointer to the HW structure
 183  *
 184  *  Test access to the PHY registers by reading the PHY ID registers.  If
 185  *  the PHY ID is already known (e.g. resume path) compare it with known ID,
 186  *  otherwise assume the read PHY ID is correct if it is valid.
 187  *
 188  *  Assumes the sw/fw/hw semaphore is already acquired.
 189  **/
 190 STATIC bool e1000_phy_is_accessible_pchlan(struct e1000_hw *hw)
 191 {
 192         u16 phy_reg = 0;
 193         u32 phy_id = 0;
 194         s32 ret_val = 0;
 195         u16 retry_count;
 196         u32 mac_reg = 0;
 197
 198         for (retry_count = 0; retry_count < 2; retry_count++) {
 199                 ret_val = hw->phy.ops.read_reg_locked(hw, PHY_ID1, &phy_reg);
 200                 if (ret_val || (phy_reg == 0xFFFF))
 201                         continue;
 202                 phy_id = (u32)(phy_reg << 16);
 203
 204                 ret_val = hw->phy.ops.read_reg_locked(hw, PHY_ID2, &phy_reg);
 205                 if (ret_val || (phy_reg == 0xFFFF)) {
 206                         phy_id = 0;
 207                         continue;
 208                 }
 209                 phy_id |= (u32)(phy_reg & PHY_REVISION_MASK);
 210                 break;
 211         }
 212
 213         if (hw->phy.id) {
 214                 if  (hw->phy.id == phy_id)
 215                         goto out;
 216         } else if (phy_id) {
 217                 hw->phy.id = phy_id;
 218                 hw->phy.revision = (u32)(phy_reg & ~PHY_REVISION_MASK);
 219                 goto out;
 220         }
 221
 222         /* In case the PHY needs to be in mdio slow mode,
 223          * set slow mode and try to get the PHY id again.
 224          */
 225         if (hw->mac.type < e1000_pch_lpt) {
 226                 hw->phy.ops.release(hw);
 227                 ret_val = e1000_set_mdio_slow_mode_hv(hw);
 228                 if (!ret_val)
 229                         ret_val = e1000_get_phy_id(hw);
 230                 hw->phy.ops.acquire(hw);
 231         }
 232
 233         if (ret_val)
 234                 return false;
 235 out:
 236         if (hw->mac.type == e1000_pch_lpt) {
 237                 /* Only unforce SMBus if ME is not active */
 238                 if (!(E1000_READ_REG(hw, E1000_FWSM) &
 239                     E1000_ICH_FWSM_FW_VALID)) {
 240                         /* Unforce SMBus mode in PHY */
 241                         hw->phy.ops.read_reg_locked(hw, CV_SMB_CTRL, &phy_reg);
 242                         phy_reg &= ~CV_SMB_CTRL_FORCE_SMBUS;
 243                         hw->phy.ops.write_reg_locked(hw, CV_SMB_CTRL, phy_reg);
 244
 245                         /* Unforce SMBus mode in MAC */
 246                         mac_reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
 247                         mac_reg &= ~E1000_CTRL_EXT_FORCE_SMBUS;
 248                         E1000_WRITE_REG(hw, E1000_CTRL_EXT, mac_reg);
 249                 }
 250         }
 251
 252         return true;
 253 }
 254
 255 /**
 256  *  e1000_toggle_lanphypc_pch_lpt - toggle the LANPHYPC pin value
 257  *  @hw: pointer to the HW structure
 258  *
 259  *  Toggling the LANPHYPC pin value fully power-cycles the PHY and is
 260  *  used to reset the PHY to a quiescent state when necessary.
 261  **/
 262 STATIC void e1000_toggle_lanphypc_pch_lpt(struct e1000_hw *hw)
 263 {
 264         u32 mac_reg;
 265
 266         DEBUGFUNC("e1000_toggle_lanphypc_pch_lpt");
 267
 268         /* Set Phy Config Counter to 50msec */
 269         mac_reg = E1000_READ_REG(hw, E1000_FEXTNVM3);
 270         mac_reg &= ~E1000_FEXTNVM3_PHY_CFG_COUNTER_MASK;
 271         mac_reg |= E1000_FEXTNVM3_PHY_CFG_COUNTER_50MSEC;
 272         E1000_WRITE_REG(hw, E1000_FEXTNVM3, mac_reg);
 273
 274         /* Toggle LANPHYPC Value bit */
 275         mac_reg = E1000_READ_REG(hw, E1000_CTRL);
 276         mac_reg |= E1000_CTRL_LANPHYPC_OVERRIDE;
 277         mac_reg &= ~E1000_CTRL_LANPHYPC_VALUE;
 278         E1000_WRITE_REG(hw, E1000_CTRL, mac_reg);
 279         E1000_WRITE_FLUSH(hw);
 280         usec_delay(10);
 281         mac_reg &= ~E1000_CTRL_LANPHYPC_OVERRIDE;
 282         E1000_WRITE_REG(hw, E1000_CTRL, mac_reg);
 283         E1000_WRITE_FLUSH(hw);
 284
 285         if (hw->mac.type < e1000_pch_lpt) {
 286                 msec_delay(50);
 287         } else {
 288                 u16 count = 20;
 289
 290                 do {
 291                         msec_delay(5);
 292                 } while (!(E1000_READ_REG(hw, E1000_CTRL_EXT) &
 293                            E1000_CTRL_EXT_LPCD) && count--);
 294
 295                 msec_delay(30);
 296         }
 297 }
 298
 299 /**
 300  *  e1000_init_phy_workarounds_pchlan - PHY initialization workarounds
 301  *  @hw: pointer to the HW structure
 302  *
 303  *  Workarounds/flow necessary for PHY initialization during driver load
 304  *  and resume paths.
 305  **/
 306 STATIC s32 e1000_init_phy_workarounds_pchlan(struct e1000_hw *hw)
 307 {
 308         u32 mac_reg, fwsm = E1000_READ_REG(hw, E1000_FWSM);
 309         s32 ret_val;
 310
 311         DEBUGFUNC("e1000_init_phy_workarounds_pchlan");
 312
 313         /* Gate automatic PHY configuration by hardware on managed and
 314          * non-managed 82579 and newer adapters.
 315          */
 316         e1000_gate_hw_phy_config_ich8lan(hw, true);
 317
 318 #ifdef ULP_SUPPORT
 319         /* It is not possible to be certain of the current state of ULP
 320          * so forcibly disable it.
 321          */
 322         hw->dev_spec.ich8lan.ulp_state = e1000_ulp_state_unknown;
 323
 324 #endif /* ULP_SUPPORT */
 325         ret_val = hw->phy.ops.acquire(hw);
 326         if (ret_val) {
 327                 DEBUGOUT("Failed to initialize PHY flow\n");
 328                 goto out;
 329         }
 330
 331         /* The MAC-PHY interconnect may be in SMBus mode.  If the PHY is
 332          * inaccessible and resetting the PHY is not blocked, toggle the
 333          * LANPHYPC Value bit to force the interconnect to PCIe mode.
 334          */
 335         switch (hw->mac.type) {
 336         case e1000_pch_lpt:
 337                 if (e1000_phy_is_accessible_pchlan(hw))
 338                         break;
 339
 340                 /* Before toggling LANPHYPC, see if PHY is accessible by
 341                  * forcing MAC to SMBus mode first.
 342                  */
 343                 mac_reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
 344                 mac_reg |= E1000_CTRL_EXT_FORCE_SMBUS;
 345                 E1000_WRITE_REG(hw, E1000_CTRL_EXT, mac_reg);
 346
 347                 /* Wait 50 milliseconds for MAC to finish any retries
 348                  * that it might be trying to perform from previous
 349                  * attempts to acknowledge any phy read requests.
 350                  */
 351                  msec_delay(50);
 352
 353                 /* fall-through */
 354         case e1000_pch2lan:
 355                 if (e1000_phy_is_accessible_pchlan(hw))
 356                         break;
 357
 358                 /* fall-through */
 359         case e1000_pchlan:
 360                 if ((hw->mac.type == e1000_pchlan) &&
 361                     (fwsm & E1000_ICH_FWSM_FW_VALID))
 362                         break;
 363
 364                 if (hw->phy.ops.check_reset_block(hw)) {
 365                         DEBUGOUT("Required LANPHYPC toggle blocked by ME\n");
 366                         ret_val = -E1000_ERR_PHY;
 367                         break;
 368                 }
 369
 370                 /* Toggle LANPHYPC Value bit */
 371                 e1000_toggle_lanphypc_pch_lpt(hw);
 372                 if (hw->mac.type >= e1000_pch_lpt) {
 373                         if (e1000_phy_is_accessible_pchlan(hw))
 374                                 break;
 375
 376                         /* Toggling LANPHYPC brings the PHY out of SMBus mode
 377                          * so ensure that the MAC is also out of SMBus mode
 378                          */
 379                         mac_reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
 380                         mac_reg &= ~E1000_CTRL_EXT_FORCE_SMBUS;
 381                         E1000_WRITE_REG(hw, E1000_CTRL_EXT, mac_reg);
 382
 383                         if (e1000_phy_is_accessible_pchlan(hw))
 384                                 break;
 385
 386                         ret_val = -E1000_ERR_PHY;
 387                 }
 388                 break;
 389         default:
 390                 break;
 391         }
 392
 393         hw->phy.ops.release(hw);
 394         if (!ret_val) {
 395
 396                 /* Check to see if able to reset PHY.  Print error if not */
 397                 if (hw->phy.ops.check_reset_block(hw)) {
 398                         ERROR_REPORT("Reset blocked by ME\n");
 399                         goto out;
 400                 }
 401
 402                 /* Reset the PHY before any access to it.  Doing so, ensures
 403                  * that the PHY is in a known good state before we read/write
 404                  * PHY registers.  The generic reset is sufficient here,
 405                  * because we haven't determined the PHY type yet.
 406                  */
 407                 ret_val = e1000_phy_hw_reset_generic(hw);
 408                 if (ret_val)
 409                         goto out;
 410
 411                 /* On a successful reset, possibly need to wait for the PHY
 412                  * to quiesce to an accessible state before returning control
 413                  * to the calling function.  If the PHY does not quiesce, then
 414                  * return E1000E_BLK_PHY_RESET, as this is the condition that
 415                  *  the PHY is in.
 416                  */
 417                 ret_val = hw->phy.ops.check_reset_block(hw);
 418                 if (ret_val)
 419                         ERROR_REPORT("ME blocked access to PHY after reset\n");
 420         }
 421
 422 out:
 423         /* Ungate automatic PHY configuration on non-managed 82579 */
 424         if ((hw->mac.type == e1000_pch2lan) &&
 425             !(fwsm & E1000_ICH_FWSM_FW_VALID)) {
 426                 msec_delay(10);
 427                 e1000_gate_hw_phy_config_ich8lan(hw, false);
 428         }
 429
 430         return ret_val;
 431 }
 432
 433 /**
 434  *  e1000_init_phy_params_pchlan - Initialize PHY function pointers
 435  *  @hw: pointer to the HW structure
 436  *
 437  *  Initialize family-specific PHY parameters and function pointers.
 438  **/
 439 STATIC s32 e1000_init_phy_params_pchlan(struct e1000_hw *hw)
 440 {
 441         struct e1000_phy_info *phy = &hw->phy;
 442         s32 ret_val;
 443
 444         DEBUGFUNC("e1000_init_phy_params_pchlan");
 445
 446         phy->addr               = 1;
 447         phy->reset_delay_us     = 100;
 448
 449         phy->ops.acquire        = e1000_acquire_swflag_ich8lan;
 450         phy->ops.check_reset_block = e1000_check_reset_block_ich8lan;
 451         phy->ops.get_cfg_done   = e1000_get_cfg_done_ich8lan;
 452         phy->ops.set_page       = e1000_set_page_igp;
 453         phy->ops.read_reg       = e1000_read_phy_reg_hv;
 454         phy->ops.read_reg_locked = e1000_read_phy_reg_hv_locked;
 455         phy->ops.read_reg_page  = e1000_read_phy_reg_page_hv;
 456         phy->ops.release        = e1000_release_swflag_ich8lan;
 457         phy->ops.reset          = e1000_phy_hw_reset_ich8lan;
 458         phy->ops.set_d0_lplu_state = e1000_set_lplu_state_pchlan;
 459         phy->ops.set_d3_lplu_state = e1000_set_lplu_state_pchlan;
 460         phy->ops.write_reg      = e1000_write_phy_reg_hv;
 461         phy->ops.write_reg_locked = e1000_write_phy_reg_hv_locked;
 462         phy->ops.write_reg_page = e1000_write_phy_reg_page_hv;
 463         phy->ops.power_up       = e1000_power_up_phy_copper;
 464         phy->ops.power_down     = e1000_power_down_phy_copper_ich8lan;
 465         phy->autoneg_mask       = AUTONEG_ADVERTISE_SPEED_DEFAULT;
 466
 467         phy->id = e1000_phy_unknown;
 468
 469         ret_val = e1000_init_phy_workarounds_pchlan(hw);
 470         if (ret_val)
 471                 return ret_val;
 472
 473         if (phy->id == e1000_phy_unknown)
 474                 switch (hw->mac.type) {
 475                 default:
 476                         ret_val = e1000_get_phy_id(hw);
 477                         if (ret_val)
 478                                 return ret_val;
 479                         if ((phy->id != 0) && (phy->id != PHY_REVISION_MASK))
 480                                 break;
 481                         /* fall-through */
 482                 case e1000_pch2lan:
 483                 case e1000_pch_lpt:
 484                         /* In case the PHY needs to be in mdio slow mode,
 485                          * set slow mode and try to get the PHY id again.
 486                          */
 487                         ret_val = e1000_set_mdio_slow_mode_hv(hw);
 488                         if (ret_val)
 489                                 return ret_val;
 490                         ret_val = e1000_get_phy_id(hw);
 491                         if (ret_val)
 492                                 return ret_val;
 493                         break;
 494                 }
 495         phy->type = e1000_get_phy_type_from_id(phy->id);
 496
 497         switch (phy->type) {
 498         case e1000_phy_82577:
 499         case e1000_phy_82579:
 500         case e1000_phy_i217:
 501                 phy->ops.check_polarity = e1000_check_polarity_82577;
 502                 phy->ops.force_speed_duplex =
 503                         e1000_phy_force_speed_duplex_82577;
 504                 phy->ops.get_cable_length = e1000_get_cable_length_82577;
 505                 phy->ops.get_info = e1000_get_phy_info_82577;
 506                 phy->ops.commit = e1000_phy_sw_reset_generic;
 507                 break;
 508         case e1000_phy_82578:
 509                 phy->ops.check_polarity = e1000_check_polarity_m88;
 510                 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_m88;
 511                 phy->ops.get_cable_length = e1000_get_cable_length_m88;
 512                 phy->ops.get_info = e1000_get_phy_info_m88;
 513                 break;
 514         default:
 515                 ret_val = -E1000_ERR_PHY;
 516                 break;
 517         }
 518
 519         return ret_val;
 520 }
 521
 522 /**
 523  *  e1000_init_phy_params_ich8lan - Initialize PHY function pointers
 524  *  @hw: pointer to the HW structure
 525  *
 526  *  Initialize family-specific PHY parameters and function pointers.
 527  **/
 528 STATIC s32 e1000_init_phy_params_ich8lan(struct e1000_hw *hw)
 529 {
 530         struct e1000_phy_info *phy = &hw->phy;
 531         s32 ret_val;
 532         u16 i = 0;
 533
 534         DEBUGFUNC("e1000_init_phy_params_ich8lan");
 535
 536         phy->addr               = 1;
 537         phy->reset_delay_us     = 100;
 538
 539         phy->ops.acquire        = e1000_acquire_swflag_ich8lan;
 540         phy->ops.check_reset_block = e1000_check_reset_block_ich8lan;
 541         phy->ops.get_cable_length = e1000_get_cable_length_igp_2;
 542         phy->ops.get_cfg_done   = e1000_get_cfg_done_ich8lan;
 543         phy->ops.read_reg       = e1000_read_phy_reg_igp;
 544         phy->ops.release        = e1000_release_swflag_ich8lan;
 545         phy->ops.reset          = e1000_phy_hw_reset_ich8lan;
 546         phy->ops.set_d0_lplu_state = e1000_set_d0_lplu_state_ich8lan;
 547         phy->ops.set_d3_lplu_state = e1000_set_d3_lplu_state_ich8lan;
 548         phy->ops.write_reg      = e1000_write_phy_reg_igp;
 549         phy->ops.power_up       = e1000_power_up_phy_copper;
 550         phy->ops.power_down     = e1000_power_down_phy_copper_ich8lan;
 551
 552         /* We may need to do this twice - once for IGP and if that fails,
 553          * we'll set BM func pointers and try again
 554          */
 555         ret_val = e1000_determine_phy_address(hw);
 556         if (ret_val) {
 557                 phy->ops.write_reg = e1000_write_phy_reg_bm;
 558                 phy->ops.read_reg  = e1000_read_phy_reg_bm;
 559                 ret_val = e1000_determine_phy_address(hw);
 560                 if (ret_val) {
 561                         DEBUGOUT("Cannot determine PHY addr. Erroring out\n");
 562                         return ret_val;
 563                 }
 564         }
 565
 566         phy->id = 0;
 567         while ((e1000_phy_unknown == e1000_get_phy_type_from_id(phy->id)) &&
 568                (i++ < 100)) {
 569                 msec_delay(1);
 570                 ret_val = e1000_get_phy_id(hw);
 571                 if (ret_val)
 572                         return ret_val;
 573         }
 574
 575         /* Verify phy id */
 576         switch (phy->id) {
 577         case IGP03E1000_E_PHY_ID:
 578                 phy->type = e1000_phy_igp_3;
 579                 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
 580                 phy->ops.read_reg_locked = e1000_read_phy_reg_igp_locked;
 581                 phy->ops.write_reg_locked = e1000_write_phy_reg_igp_locked;
 582                 phy->ops.get_info = e1000_get_phy_info_igp;
 583                 phy->ops.check_polarity = e1000_check_polarity_igp;
 584                 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_igp;
 585                 break;
 586         case IFE_E_PHY_ID:
 587         case IFE_PLUS_E_PHY_ID:
 588         case IFE_C_E_PHY_ID:
 589                 phy->type = e1000_phy_ife;
 590                 phy->autoneg_mask = E1000_ALL_NOT_GIG;
 591                 phy->ops.get_info = e1000_get_phy_info_ife;
 592                 phy->ops.check_polarity = e1000_check_polarity_ife;
 593                 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_ife;
 594                 break;
 595         case BME1000_E_PHY_ID:
 596                 phy->type = e1000_phy_bm;
 597                 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
 598                 phy->ops.read_reg = e1000_read_phy_reg_bm;
 599                 phy->ops.write_reg = e1000_write_phy_reg_bm;
 600                 phy->ops.commit = e1000_phy_sw_reset_generic;
 601                 phy->ops.get_info = e1000_get_phy_info_m88;
 602                 phy->ops.check_polarity = e1000_check_polarity_m88;
 603                 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_m88;
 604                 break;
 605         default:
 606                 return -E1000_ERR_PHY;
 607                 break;
 608         }
 609
 610         return E1000_SUCCESS;
 611 }
 612
 613 /**
 614  *  e1000_init_nvm_params_ich8lan - Initialize NVM function pointers
 615  *  @hw: pointer to the HW structure
 616  *
 617  *  Initialize family-specific NVM parameters and function
 618  *  pointers.
 619  **/
 620 STATIC s32 e1000_init_nvm_params_ich8lan(struct e1000_hw *hw)
 621 {
 622         struct e1000_nvm_info *nvm = &hw->nvm;
 623         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
 624         u32 gfpreg, sector_base_addr, sector_end_addr;
 625         u16 i;
 626
 627         DEBUGFUNC("e1000_init_nvm_params_ich8lan");
 628
 629         /* Can't read flash registers if the register set isn't mapped. */
 630         nvm->type = e1000_nvm_flash_sw;
 631         if (!hw->flash_address) {
 632                 DEBUGOUT("ERROR: Flash registers not mapped\n");
 633                 return -E1000_ERR_CONFIG;
 634         }
 635
 636         gfpreg = E1000_READ_FLASH_REG(hw, ICH_FLASH_GFPREG);
 637
 638         /* sector_X_addr is a "sector"-aligned address (4096 bytes)
 639          * Add 1 to sector_end_addr since this sector is included in
 640          * the overall size.
 641          */
 642         sector_base_addr = gfpreg & FLASH_GFPREG_BASE_MASK;
 643         sector_end_addr = ((gfpreg >> 16) & FLASH_GFPREG_BASE_MASK) + 1;
 644
 645         /* flash_base_addr is byte-aligned */
 646         nvm->flash_base_addr = sector_base_addr << FLASH_SECTOR_ADDR_SHIFT;
 647
 648         /* find total size of the NVM, then cut in half since the total
 649          * size represents two separate NVM banks.
 650          */
 651         nvm->flash_bank_size = ((sector_end_addr - sector_base_addr)
 652                                 << FLASH_SECTOR_ADDR_SHIFT);
 653         nvm->flash_bank_size /= 2;
 654         /* Adjust to word count */
 655         nvm->flash_bank_size /= sizeof(u16);
 656
 657         nvm->word_size = E1000_SHADOW_RAM_WORDS;
 658
 659         /* Clear shadow ram */
 660         for (i = 0; i < nvm->word_size; i++) {
 661                 dev_spec->shadow_ram[i].modified = false;
 662                 dev_spec->shadow_ram[i].value    = 0xFFFF;
 663         }
 664
 665         E1000_MUTEX_INIT(&dev_spec->nvm_mutex);
 666         E1000_MUTEX_INIT(&dev_spec->swflag_mutex);
 667
 668         /* Function Pointers */
 669         nvm->ops.acquire        = e1000_acquire_nvm_ich8lan;
 670         nvm->ops.release        = e1000_release_nvm_ich8lan;
 671         nvm->ops.read           = e1000_read_nvm_ich8lan;
 672         nvm->ops.update         = e1000_update_nvm_checksum_ich8lan;
 673         nvm->ops.valid_led_default = e1000_valid_led_default_ich8lan;
 674         nvm->ops.validate       = e1000_validate_nvm_checksum_ich8lan;
 675         nvm->ops.write          = e1000_write_nvm_ich8lan;
 676
 677         return E1000_SUCCESS;
 678 }
 679
 680 /**
 681  *  e1000_init_mac_params_ich8lan - Initialize MAC function pointers
 682  *  @hw: pointer to the HW structure
 683  *
 684  *  Initialize family-specific MAC parameters and function
 685  *  pointers.
 686  **/
 687 STATIC s32 e1000_init_mac_params_ich8lan(struct e1000_hw *hw)
 688 {
 689         struct e1000_mac_info *mac = &hw->mac;
 690 #if defined(QV_RELEASE) || !defined(NO_PCH_LPT_B0_SUPPORT)
 691         u16 pci_cfg;
 692 #endif /* QV_RELEASE || !defined(NO_PCH_LPT_B0_SUPPORT) */
 693
 694         DEBUGFUNC("e1000_init_mac_params_ich8lan");
 695
 696         /* Set media type function pointer */
 697         hw->phy.media_type = e1000_media_type_copper;
 698
 699         /* Set mta register count */
 700         mac->mta_reg_count = 32;
 701         /* Set rar entry count */
 702         mac->rar_entry_count = E1000_ICH_RAR_ENTRIES;
 703         if (mac->type == e1000_ich8lan)
 704                 mac->rar_entry_count--;
 705         /* Set if part includes ASF firmware */
 706         mac->asf_firmware_present = true;
 707         /* FWSM register */
 708         mac->has_fwsm = true;
 709         /* ARC subsystem not supported */
 710         mac->arc_subsystem_valid = false;
 711         /* Adaptive IFS supported */
 712         mac->adaptive_ifs = true;
 713
 714         /* Function pointers */
 715
 716         /* bus type/speed/width */
 717         mac->ops.get_bus_info = e1000_get_bus_info_ich8lan;
 718         /* function id */
 719         mac->ops.set_lan_id = e1000_set_lan_id_single_port;
 720         /* reset */
 721         mac->ops.reset_hw = e1000_reset_hw_ich8lan;
 722         /* hw initialization */
 723         mac->ops.init_hw = e1000_init_hw_ich8lan;
 724         /* link setup */
 725         mac->ops.setup_link = e1000_setup_link_ich8lan;
 726         /* physical interface setup */
 727         mac->ops.setup_physical_interface = e1000_setup_copper_link_ich8lan;
 728         /* check for link */
 729         mac->ops.check_for_link = e1000_check_for_copper_link_ich8lan;
 730         /* link info */
 731         mac->ops.get_link_up_info = e1000_get_link_up_info_ich8lan;
 732         /* multicast address update */
 733         mac->ops.update_mc_addr_list = e1000_update_mc_addr_list_generic;
 734         /* clear hardware counters */
 735         mac->ops.clear_hw_cntrs = e1000_clear_hw_cntrs_ich8lan;
 736
 737         /* LED and other operations */
 738         switch (mac->type) {
 739         case e1000_ich8lan:
 740         case e1000_ich9lan:
 741         case e1000_ich10lan:
 742                 /* check management mode */
 743                 mac->ops.check_mng_mode = e1000_check_mng_mode_ich8lan;
 744                 /* ID LED init */
 745                 mac->ops.id_led_init = e1000_id_led_init_generic;
 746                 /* blink LED */
 747                 mac->ops.blink_led = e1000_blink_led_generic;
 748                 /* setup LED */
 749                 mac->ops.setup_led = e1000_setup_led_generic;
 750                 /* cleanup LED */
 751                 mac->ops.cleanup_led = e1000_cleanup_led_ich8lan;
 752                 /* turn on/off LED */
 753                 mac->ops.led_on = e1000_led_on_ich8lan;
 754                 mac->ops.led_off = e1000_led_off_ich8lan;
 755                 break;
 756         case e1000_pch2lan:
 757                 mac->rar_entry_count = E1000_PCH2_RAR_ENTRIES;
 758                 mac->ops.rar_set = e1000_rar_set_pch2lan;
 759                 /* fall-through */
 760         case e1000_pch_lpt:
 761 #ifndef NO_NON_BLOCKING_PHY_MTA_UPDATE_SUPPORT
 762                 /* multicast address update for pch2 */
 763                 mac->ops.update_mc_addr_list =
 764                         e1000_update_mc_addr_list_pch2lan;
 765                 /* fall-through */
 766 #endif
 767         case e1000_pchlan:
 768 #if defined(QV_RELEASE) || !defined(NO_PCH_LPT_B0_SUPPORT)
 769                 /* save PCH revision_id */
 770                 e1000_read_pci_cfg(hw, E1000_PCI_REVISION_ID_REG, &pci_cfg);
 771                 hw->revision_id = (u8)(pci_cfg &= 0x000F);
 772 #endif /* QV_RELEASE || !defined(NO_PCH_LPT_B0_SUPPORT) */
 773                 /* check management mode */
 774                 mac->ops.check_mng_mode = e1000_check_mng_mode_pchlan;
 775                 /* ID LED init */
 776                 mac->ops.id_led_init = e1000_id_led_init_pchlan;
 777                 /* setup LED */
 778                 mac->ops.setup_led = e1000_setup_led_pchlan;
 779                 /* cleanup LED */
 780                 mac->ops.cleanup_led = e1000_cleanup_led_pchlan;
 781                 /* turn on/off LED */
 782                 mac->ops.led_on = e1000_led_on_pchlan;
 783                 mac->ops.led_off = e1000_led_off_pchlan;
 784                 break;
 785         default:
 786                 break;
 787         }
 788
 789         if (mac->type == e1000_pch_lpt) {
 790                 mac->rar_entry_count = E1000_PCH_LPT_RAR_ENTRIES;
 791                 mac->ops.rar_set = e1000_rar_set_pch_lpt;
 792                 mac->ops.setup_physical_interface = e1000_setup_copper_link_pch_lpt;
 793         }
 794
 795         /* Enable PCS Lock-loss workaround for ICH8 */
 796         if (mac->type == e1000_ich8lan)
 797                 e1000_set_kmrn_lock_loss_workaround_ich8lan(hw, true);
 798
 799         return E1000_SUCCESS;
 800 }
 801
 802 /**
 803  *  __e1000_access_emi_reg_locked - Read/write EMI register
 804  *  @hw: pointer to the HW structure
 805  *  @addr: EMI address to program
 806  *  @data: pointer to value to read/write from/to the EMI address
 807  *  @read: boolean flag to indicate read or write
 808  *
 809  *  This helper function assumes the SW/FW/HW Semaphore is already acquired.
 810  **/
 811 STATIC s32 __e1000_access_emi_reg_locked(struct e1000_hw *hw, u16 address,
 812                                          u16 *data, bool read)
 813 {
 814         s32 ret_val;
 815
 816         DEBUGFUNC("__e1000_access_emi_reg_locked");
 817
 818         ret_val = hw->phy.ops.write_reg_locked(hw, I82579_EMI_ADDR, address);
 819         if (ret_val)
 820                 return ret_val;
 821
 822         if (read)
 823                 ret_val = hw->phy.ops.read_reg_locked(hw, I82579_EMI_DATA,
 824                                                       data);
 825         else
 826                 ret_val = hw->phy.ops.write_reg_locked(hw, I82579_EMI_DATA,
 827                                                        *data);
 828
 829         return ret_val;
 830 }
 831
 832 /**
 833  *  e1000_read_emi_reg_locked - Read Extended Management Interface register
 834  *  @hw: pointer to the HW structure
 835  *  @addr: EMI address to program
 836  *  @data: value to be read from the EMI address
 837  *
 838  *  Assumes the SW/FW/HW Semaphore is already acquired.
 839  **/
 840 s32 e1000_read_emi_reg_locked(struct e1000_hw *hw, u16 addr, u16 *data)
 841 {
 842         DEBUGFUNC("e1000_read_emi_reg_locked");
 843
 844         return __e1000_access_emi_reg_locked(hw, addr, data, true);
 845 }
 846
 847 /**
 848  *  e1000_write_emi_reg_locked - Write Extended Management Interface register
 849  *  @hw: pointer to the HW structure
 850  *  @addr: EMI address to program
 851  *  @data: value to be written to the EMI address
 852  *
 853  *  Assumes the SW/FW/HW Semaphore is already acquired.
 854  **/
 855 s32 e1000_write_emi_reg_locked(struct e1000_hw *hw, u16 addr, u16 data)
 856 {
 857         DEBUGFUNC("e1000_read_emi_reg_locked");
 858
 859         return __e1000_access_emi_reg_locked(hw, addr, &data, false);
 860 }
 861
 862 /**
 863  *  e1000_set_eee_pchlan - Enable/disable EEE support
 864  *  @hw: pointer to the HW structure
 865  *
 866  *  Enable/disable EEE based on setting in dev_spec structure, the duplex of
 867  *  the link and the EEE capabilities of the link partner.  The LPI Control
 868  *  register bits will remain set only if/when link is up.
 869  *
 870  *  EEE LPI must not be asserted earlier than one second after link is up.
 871  *  On 82579, EEE LPI should not be enabled until such time otherwise there
 872  *  can be link issues with some switches.  Other devices can have EEE LPI
 873  *  enabled immediately upon link up since they have a timer in hardware which
 874  *  prevents LPI from being asserted too early.
 875  **/
 876 s32 e1000_set_eee_pchlan(struct e1000_hw *hw)
 877 {
 878         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
 879         s32 ret_val;
 880         u16 lpa, pcs_status, adv, adv_addr, lpi_ctrl, data;
 881
 882         DEBUGFUNC("e1000_set_eee_pchlan");
 883
 884         switch (hw->phy.type) {
 885         case e1000_phy_82579:
 886                 lpa = I82579_EEE_LP_ABILITY;
 887                 pcs_status = I82579_EEE_PCS_STATUS;
 888                 adv_addr = I82579_EEE_ADVERTISEMENT;
 889                 break;
 890         case e1000_phy_i217:
 891                 lpa = I217_EEE_LP_ABILITY;
 892                 pcs_status = I217_EEE_PCS_STATUS;
 893                 adv_addr = I217_EEE_ADVERTISEMENT;
 894                 break;
 895         default:
 896                 return E1000_SUCCESS;
 897         }
 898
 899         ret_val = hw->phy.ops.acquire(hw);
 900         if (ret_val)
 901                 return ret_val;
 902
 903         ret_val = hw->phy.ops.read_reg_locked(hw, I82579_LPI_CTRL, &lpi_ctrl);
 904         if (ret_val)
 905                 goto release;
 906
 907         /* Clear bits that enable EEE in various speeds */
 908         lpi_ctrl &= ~I82579_LPI_CTRL_ENABLE_MASK;
 909
 910         /* Enable EEE if not disabled by user */
 911         if (!dev_spec->eee_disable) {
 912                 /* Save off link partner's EEE ability */
 913                 ret_val = e1000_read_emi_reg_locked(hw, lpa,
 914                                                     &dev_spec->eee_lp_ability);
 915                 if (ret_val)
 916                         goto release;
 917
 918                 /* Read EEE advertisement */
 919                 ret_val = e1000_read_emi_reg_locked(hw, adv_addr, &adv);
 920                 if (ret_val)
 921                         goto release;
 922
 923                 /* Enable EEE only for speeds in which the link partner is
 924                  * EEE capable and for which we advertise EEE.
 925                  */
 926                 if (adv & dev_spec->eee_lp_ability & I82579_EEE_1000_SUPPORTED)
 927                         lpi_ctrl |= I82579_LPI_CTRL_1000_ENABLE;
 928
 929                 if (adv & dev_spec->eee_lp_ability & I82579_EEE_100_SUPPORTED) {
 930                         hw->phy.ops.read_reg_locked(hw, PHY_LP_ABILITY, &data);
 931                         if (data & NWAY_LPAR_100TX_FD_CAPS)
 932                                 lpi_ctrl |= I82579_LPI_CTRL_100_ENABLE;
 933                         else
 934                                 /* EEE is not supported in 100Half, so ignore
 935                                  * partner's EEE in 100 ability if full-duplex
 936                                  * is not advertised.
 937                                  */
 938                                 dev_spec->eee_lp_ability &=
 939                                     ~I82579_EEE_100_SUPPORTED;
 940                 }
 941         }
 942
 943         if (hw->phy.type == e1000_phy_82579) {
 944                 ret_val = e1000_read_emi_reg_locked(hw, I82579_LPI_PLL_SHUT,
 945                                                     &data);
 946                 if (ret_val)
 947                         goto release;
 948
 949                 data &= ~I82579_LPI_100_PLL_SHUT;
 950                 ret_val = e1000_write_emi_reg_locked(hw, I82579_LPI_PLL_SHUT,
 951                                                      data);
 952         }
 953
 954         /* R/Clr IEEE MMD 3.1 bits 11:10 - Tx/Rx LPI Received */
 955         ret_val = e1000_read_emi_reg_locked(hw, pcs_status, &data);
 956         if (ret_val)
 957                 goto release;
 958
 959         ret_val = hw->phy.ops.write_reg_locked(hw, I82579_LPI_CTRL, lpi_ctrl);
 960 release:
 961         hw->phy.ops.release(hw);
 962
 963         return ret_val;
 964 }
 965
 966 /**
 967  *  e1000_k1_workaround_lpt_lp - K1 workaround on Lynxpoint-LP
 968  *  @hw:   pointer to the HW structure
 969  *  @link: link up bool flag
 970  *
 971  *  When K1 is enabled for 1Gbps, the MAC can miss 2 DMA completion indications
 972  *  preventing further DMA write requests.  Workaround the issue by disabling
 973  *  the de-assertion of the clock request when in 1Gpbs mode.
 974  *  Also, set appropriate Tx re-transmission timeouts for 10 and 100Half link
 975  *  speeds in order to avoid Tx hangs.
 976  **/
 977 STATIC s32 e1000_k1_workaround_lpt_lp(struct e1000_hw *hw, bool link)
 978 {
 979         u32 fextnvm6 = E1000_READ_REG(hw, E1000_FEXTNVM6);
 980         u32 status = E1000_READ_REG(hw, E1000_STATUS);
 981         s32 ret_val = E1000_SUCCESS;
 982         u16 reg;
 983
 984         if (link && (status & E1000_STATUS_SPEED_1000)) {
 985                 ret_val = hw->phy.ops.acquire(hw);
 986                 if (ret_val)
 987                         return ret_val;
 988
 989                 ret_val =
 990                     e1000_read_kmrn_reg_locked(hw, E1000_KMRNCTRLSTA_K1_CONFIG,
 991                                                &reg);
 992                 if (ret_val)
 993                         goto release;
 994
 995                 ret_val =
 996                     e1000_write_kmrn_reg_locked(hw,
 997                                                 E1000_KMRNCTRLSTA_K1_CONFIG,
 998                                                 reg &
 999                                                 ~E1000_KMRNCTRLSTA_K1_ENABLE);
1000                 if (ret_val)
1001                         goto release;
1002
1003                 usec_delay(10);
1004
1005                 E1000_WRITE_REG(hw, E1000_FEXTNVM6,
1006                                 fextnvm6 | E1000_FEXTNVM6_REQ_PLL_CLK);
1007
1008                 ret_val =
1009                     e1000_write_kmrn_reg_locked(hw,
1010                                                 E1000_KMRNCTRLSTA_K1_CONFIG,
1011                                                 reg);
1012 release:
1013                 hw->phy.ops.release(hw);
1014         } else {
1015                 /* clear FEXTNVM6 bit 8 on link down or 10/100 */
1016                 fextnvm6 &= ~E1000_FEXTNVM6_REQ_PLL_CLK;
1017
1018                 if (!link || ((status & E1000_STATUS_SPEED_100) &&
1019                               (status & E1000_STATUS_FD)))
1020                         goto update_fextnvm6;
1021
1022                 ret_val = hw->phy.ops.read_reg(hw, I217_INBAND_CTRL, &reg);
1023                 if (ret_val)
1024                         return ret_val;
1025
1026                 /* Clear link status transmit timeout */
1027                 reg &= ~I217_INBAND_CTRL_LINK_STAT_TX_TIMEOUT_MASK;
1028
1029                 if (status & E1000_STATUS_SPEED_100) {
1030                         /* Set inband Tx timeout to 5x10us for 100Half */
1031                         reg |= 5 << I217_INBAND_CTRL_LINK_STAT_TX_TIMEOUT_SHIFT;
1032
1033                         /* Do not extend the K1 entry latency for 100Half */
1034                         fextnvm6 &= ~E1000_FEXTNVM6_ENABLE_K1_ENTRY_CONDITION;
1035                 } else {
1036                         /* Set inband Tx timeout to 50x10us for 10Full/Half */
1037                         reg |= 50 <<
1038                                I217_INBAND_CTRL_LINK_STAT_TX_TIMEOUT_SHIFT;
1039
1040                         /* Extend the K1 entry latency for 10 Mbps */
1041                         fextnvm6 |= E1000_FEXTNVM6_ENABLE_K1_ENTRY_CONDITION;
1042                 }
1043
1044                 ret_val = hw->phy.ops.write_reg(hw, I217_INBAND_CTRL, reg);
1045                 if (ret_val)
1046                         return ret_val;
1047
1048 update_fextnvm6:
1049                 E1000_WRITE_REG(hw, E1000_FEXTNVM6, fextnvm6);
1050         }
1051
1052         return ret_val;
1053 }
1054
1055 #ifdef ULP_SUPPORT
1056 /**
1057  *  e1000_enable_ulp_lpt_lp - configure Ultra Low Power mode for LynxPoint-LP
1058  *  @hw: pointer to the HW structure
1059  *  @to_sx: boolean indicating a system power state transition to Sx
1060  *
1061  *  When link is down, configure ULP mode to significantly reduce the power
1062  *  to the PHY.  If on a Manageability Engine (ME) enabled system, tell the
1063  *  ME firmware to start the ULP configuration.  If not on an ME enabled
1064  *  system, configure the ULP mode by software.
1065  */
1066 s32 e1000_enable_ulp_lpt_lp(struct e1000_hw *hw, bool to_sx)
1067 {
1068         u32 mac_reg;
1069         s32 ret_val = E1000_SUCCESS;
1070         u16 phy_reg;
1071
1072         if ((hw->mac.type < e1000_pch_lpt) ||
1073             (hw->device_id == E1000_DEV_ID_PCH_LPT_I217_LM) ||
1074             (hw->device_id == E1000_DEV_ID_PCH_LPT_I217_V) ||
1075             (hw->device_id == E1000_DEV_ID_PCH_I218_LM2) ||
1076             (hw->device_id == E1000_DEV_ID_PCH_I218_V2) ||
1077             (hw->dev_spec.ich8lan.ulp_state == e1000_ulp_state_on))
1078                 return 0;
1079
1080         if (!to_sx) {
1081                 int i = 0;
1082                 /* Poll up to 5 seconds for Cable Disconnected indication */
1083                 while (!(E1000_READ_REG(hw, E1000_FEXT) &
1084                          E1000_FEXT_PHY_CABLE_DISCONNECTED)) {
1085                         /* Bail if link is re-acquired */
1086                         if (E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU)
1087                                 return -E1000_ERR_PHY;
1088                         if (i++ == 100)
1089                                 break;
1090
1091                         msec_delay(50);
1092                 }
1093                 DEBUGOUT2("CABLE_DISCONNECTED %s set after %dmsec\n",
1094                           (E1000_READ_REG(hw, E1000_FEXT) &
1095                            E1000_FEXT_PHY_CABLE_DISCONNECTED) ? "" : "not",
1096                           i * 50);
1097                 if (!(E1000_READ_REG(hw, E1000_FEXT) &
1098                     E1000_FEXT_PHY_CABLE_DISCONNECTED))
1099                         return 0;
1100         }
1101
1102         if (E1000_READ_REG(hw, E1000_FWSM) & E1000_ICH_FWSM_FW_VALID) {
1103                 /* Request ME configure ULP mode in the PHY */
1104                 mac_reg = E1000_READ_REG(hw, E1000_H2ME);
1105                 mac_reg |= E1000_H2ME_ULP | E1000_H2ME_ENFORCE_SETTINGS;
1106                 E1000_WRITE_REG(hw, E1000_H2ME, mac_reg);
1107
1108                 goto out;
1109         }
1110
1111         ret_val = hw->phy.ops.acquire(hw);
1112         if (ret_val)
1113                 goto out;
1114
1115         /* During S0 Idle keep the phy in PCI-E mode */
1116         if (hw->dev_spec.ich8lan.smbus_disable)
1117                 goto skip_smbus;
1118
1119         /* Force SMBus mode in PHY */
1120         ret_val = e1000_read_phy_reg_hv_locked(hw, CV_SMB_CTRL, &phy_reg);
1121         if (ret_val)
1122                 goto release;
1123         phy_reg |= CV_SMB_CTRL_FORCE_SMBUS;
1124         e1000_write_phy_reg_hv_locked(hw, CV_SMB_CTRL, phy_reg);
1125
1126         /* Force SMBus mode in MAC */
1127         mac_reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
1128         mac_reg |= E1000_CTRL_EXT_FORCE_SMBUS;
1129         E1000_WRITE_REG(hw, E1000_CTRL_EXT, mac_reg);
1130
1131 skip_smbus:
1132         if (!to_sx) {
1133                 /* Change the 'Link Status Change' interrupt to trigger
1134                  * on 'Cable Status Change'
1135                  */
1136                 ret_val = e1000_read_kmrn_reg_locked(hw,
1137                                                      E1000_KMRNCTRLSTA_OP_MODES,
1138                                                      &phy_reg);
1139                 if (ret_val)
1140                         goto release;
1141                 phy_reg |= E1000_KMRNCTRLSTA_OP_MODES_LSC2CSC;
1142                 e1000_write_kmrn_reg_locked(hw, E1000_KMRNCTRLSTA_OP_MODES,
1143                                             phy_reg);
1144         }
1145
1146         /* Set Inband ULP Exit, Reset to SMBus mode and
1147          * Disable SMBus Release on PERST# in PHY
1148          */
1149         ret_val = e1000_read_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, &phy_reg);
1150         if (ret_val)
1151                 goto release;
1152         phy_reg |= (I218_ULP_CONFIG1_RESET_TO_SMBUS |
1153                     I218_ULP_CONFIG1_DISABLE_SMB_PERST);
1154         if (to_sx) {
1155                 if (E1000_READ_REG(hw, E1000_WUFC) & E1000_WUFC_LNKC)
1156                         phy_reg |= I218_ULP_CONFIG1_WOL_HOST;
1157                 else
1158                         phy_reg &= ~I218_ULP_CONFIG1_WOL_HOST;
1159
1160                 phy_reg |= I218_ULP_CONFIG1_STICKY_ULP;
1161                 phy_reg &= ~I218_ULP_CONFIG1_INBAND_EXIT;
1162         } else {
1163                 phy_reg |= I218_ULP_CONFIG1_INBAND_EXIT;
1164                 phy_reg &= ~I218_ULP_CONFIG1_STICKY_ULP;
1165                 phy_reg &= ~I218_ULP_CONFIG1_WOL_HOST;
1166         }
1167         e1000_write_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, phy_reg);
1168
1169         /* Set Disable SMBus Release on PERST# in MAC */
1170         mac_reg = E1000_READ_REG(hw, E1000_FEXTNVM7);
1171         mac_reg |= E1000_FEXTNVM7_DISABLE_SMB_PERST;
1172         E1000_WRITE_REG(hw, E1000_FEXTNVM7, mac_reg);
1173
1174         /* Commit ULP changes in PHY by starting auto ULP configuration */
1175         phy_reg |= I218_ULP_CONFIG1_START;
1176         e1000_write_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, phy_reg);
1177
1178         if (!to_sx) {
1179                 /* Disable Tx so that the MAC doesn't send any (buffered)
1180                  * packets to the PHY.
1181                  */
1182                 mac_reg = E1000_READ_REG(hw, E1000_TCTL);
1183                 mac_reg &= ~E1000_TCTL_EN;
1184                 E1000_WRITE_REG(hw, E1000_TCTL, mac_reg);
1185         }
1186
1187 release:
1188         hw->phy.ops.release(hw);
1189 out:
1190         if (ret_val)
1191                 DEBUGOUT1("Error in ULP enable flow: %d\n", ret_val);
1192         else
1193                 hw->dev_spec.ich8lan.ulp_state = e1000_ulp_state_on;
1194
1195         return ret_val;
1196 }
1197
1198 /**
1199  *  e1000_disable_ulp_lpt_lp - unconfigure Ultra Low Power mode for LynxPoint-LP
1200  *  @hw: pointer to the HW structure
1201  *  @force: boolean indicating whether or not to force disabling ULP
1202  *
1203  *  Un-configure ULP mode when link is up, the system is transitioned from
1204  *  Sx or the driver is unloaded.  If on a Manageability Engine (ME) enabled
1205  *  system, poll for an indication from ME that ULP has been un-configured.
1206  *  If not on an ME enabled system, un-configure the ULP mode by software.
1207  *
1208  *  During nominal operation, this function is called when link is acquired
1209  *  to disable ULP mode (force=false); otherwise, for example when unloading
1210  *  the driver or during Sx->S0 transitions, this is called with force=true
1211  *  to forcibly disable ULP.
1212
1213  *  When the cable is plugged in while the device is in D0, a Cable Status
1214  *  Change interrupt is generated which causes this function to be called
1215  *  to partially disable ULP mode and restart autonegotiation.  This function
1216  *  is then called again due to the resulting Link Status Change interrupt
1217  *  to finish cleaning up after the ULP flow.
1218  */
1219 s32 e1000_disable_ulp_lpt_lp(struct e1000_hw *hw, bool force)
1220 {
1221         s32 ret_val = E1000_SUCCESS;
1222         u32 mac_reg;
1223         u16 phy_reg;
1224         int i = 0;
1225
1226         if ((hw->mac.type < e1000_pch_lpt) ||
1227             (hw->device_id == E1000_DEV_ID_PCH_LPT_I217_LM) ||
1228             (hw->device_id == E1000_DEV_ID_PCH_LPT_I217_V) ||
1229             (hw->device_id == E1000_DEV_ID_PCH_I218_LM2) ||
1230             (hw->device_id == E1000_DEV_ID_PCH_I218_V2) ||
1231             (hw->dev_spec.ich8lan.ulp_state == e1000_ulp_state_off))
1232                 return 0;
1233
1234         if (E1000_READ_REG(hw, E1000_FWSM) & E1000_ICH_FWSM_FW_VALID) {
1235                 if (force) {
1236                         /* Request ME un-configure ULP mode in the PHY */
1237                         mac_reg = E1000_READ_REG(hw, E1000_H2ME);
1238                         mac_reg &= ~E1000_H2ME_ULP;
1239                         mac_reg |= E1000_H2ME_ENFORCE_SETTINGS;
1240                         E1000_WRITE_REG(hw, E1000_H2ME, mac_reg);
1241                 }
1242
1243                 /* Poll up to 100msec for ME to clear ULP_CFG_DONE */
1244                 while (E1000_READ_REG(hw, E1000_FWSM) &
1245                        E1000_FWSM_ULP_CFG_DONE) {
1246                         if (i++ == 10) {
1247                                 ret_val = -E1000_ERR_PHY;
1248                                 goto out;
1249                         }
1250
1251                         msec_delay(10);
1252                 }
1253                 DEBUGOUT1("ULP_CONFIG_DONE cleared after %dmsec\n", i * 10);
1254
1255                 if (force) {
1256                         mac_reg = E1000_READ_REG(hw, E1000_H2ME);
1257                         mac_reg &= ~E1000_H2ME_ENFORCE_SETTINGS;
1258                         E1000_WRITE_REG(hw, E1000_H2ME, mac_reg);
1259                 } else {
1260                         /* Clear H2ME.ULP after ME ULP configuration */
1261                         mac_reg = E1000_READ_REG(hw, E1000_H2ME);
1262                         mac_reg &= ~E1000_H2ME_ULP;
1263                         E1000_WRITE_REG(hw, E1000_H2ME, mac_reg);
1264
1265                         /* Restore link speed advertisements and restart
1266                          * Auto-negotiation
1267                          */
1268                         if (hw->mac.autoneg) {
1269                                 ret_val = e1000_phy_setup_autoneg(hw);
1270                                 if (ret_val)
1271                                         goto out;
1272                         } else {
1273                                 ret_val = e1000_setup_copper_link_generic(hw);
1274                                 if (ret_val)
1275                                         goto out;
1276                         }
1277                         ret_val = e1000_oem_bits_config_ich8lan(hw, true);
1278                 }
1279
1280                 goto out;
1281         }
1282
1283         ret_val = hw->phy.ops.acquire(hw);
1284         if (ret_val)
1285                 goto out;
1286
1287         /* Revert the change to the 'Link Status Change'
1288          * interrupt to trigger on 'Cable Status Change'
1289          */
1290         ret_val = e1000_read_kmrn_reg_locked(hw, E1000_KMRNCTRLSTA_OP_MODES,
1291                                              &phy_reg);
1292         if (ret_val)
1293                 goto release;
1294         phy_reg &= ~E1000_KMRNCTRLSTA_OP_MODES_LSC2CSC;
1295         e1000_write_kmrn_reg_locked(hw, E1000_KMRNCTRLSTA_OP_MODES, phy_reg);
1296
1297         if (force)
1298                 /* Toggle LANPHYPC Value bit */
1299                 e1000_toggle_lanphypc_pch_lpt(hw);
1300
1301         /* Unforce SMBus mode in PHY */
1302         ret_val = e1000_read_phy_reg_hv_locked(hw, CV_SMB_CTRL, &phy_reg);
1303         if (ret_val) {
1304                 /* The MAC might be in PCIe mode, so temporarily force to
1305                  * SMBus mode in order to access the PHY.
1306                  */
1307                 mac_reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
1308                 mac_reg |= E1000_CTRL_EXT_FORCE_SMBUS;
1309                 E1000_WRITE_REG(hw, E1000_CTRL_EXT, mac_reg);
1310
1311                 msec_delay(50);
1312
1313                 ret_val = e1000_read_phy_reg_hv_locked(hw, CV_SMB_CTRL,
1314                                                        &phy_reg);
1315                 if (ret_val)
1316                         goto release;
1317         }
1318         phy_reg &= ~CV_SMB_CTRL_FORCE_SMBUS;
1319         e1000_write_phy_reg_hv_locked(hw, CV_SMB_CTRL, phy_reg);
1320
1321         /* Unforce SMBus mode in MAC */
1322         mac_reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
1323         mac_reg &= ~E1000_CTRL_EXT_FORCE_SMBUS;
1324         E1000_WRITE_REG(hw, E1000_CTRL_EXT, mac_reg);
1325
1326         /* When ULP mode was previously entered, K1 was disabled by the
1327          * hardware.  Re-Enable K1 in the PHY when exiting ULP.
1328          */
1329         ret_val = e1000_read_phy_reg_hv_locked(hw, HV_PM_CTRL, &phy_reg);
1330         if (ret_val)
1331                 goto release;
1332         phy_reg |= HV_PM_CTRL_K1_ENABLE;
1333         e1000_write_phy_reg_hv_locked(hw, HV_PM_CTRL, phy_reg);
1334
1335         /* Clear ULP enabled configuration */
1336         ret_val = e1000_read_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, &phy_reg);
1337         if (ret_val)
1338                 goto release;
1339         /* CSC interrupt received due to ULP Indication */
1340         if ((phy_reg & I218_ULP_CONFIG1_IND) || force) {
1341                 phy_reg &= ~(I218_ULP_CONFIG1_IND |
1342                              I218_ULP_CONFIG1_STICKY_ULP |
1343                              I218_ULP_CONFIG1_RESET_TO_SMBUS |
1344                              I218_ULP_CONFIG1_WOL_HOST |
1345                              I218_ULP_CONFIG1_INBAND_EXIT |
1346                              I218_ULP_CONFIG1_DISABLE_SMB_PERST);
1347                 e1000_write_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, phy_reg);
1348
1349                 /* Commit ULP changes by starting auto ULP configuration */
1350                 phy_reg |= I218_ULP_CONFIG1_START;
1351                 e1000_write_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, phy_reg);
1352
1353                 /* Clear Disable SMBus Release on PERST# in MAC */
1354                 mac_reg = E1000_READ_REG(hw, E1000_FEXTNVM7);
1355                 mac_reg &= ~E1000_FEXTNVM7_DISABLE_SMB_PERST;
1356                 E1000_WRITE_REG(hw, E1000_FEXTNVM7, mac_reg);
1357
1358                 if (!force) {
1359                         hw->phy.ops.release(hw);
1360
1361                         if (hw->mac.autoneg)
1362                                 e1000_phy_setup_autoneg(hw);
1363
1364                         e1000_sw_lcd_config_ich8lan(hw);
1365
1366                         e1000_oem_bits_config_ich8lan(hw, true);
1367
1368                         /* Set ULP state to unknown and return non-zero to
1369                          * indicate no link (yet) and re-enter on the next LSC
1370                          * to finish disabling ULP flow.
1371                          */
1372                         hw->dev_spec.ich8lan.ulp_state =
1373                             e1000_ulp_state_unknown;
1374
1375                         return 1;
1376                 }
1377         }
1378
1379         /* Re-enable Tx */
1380         mac_reg = E1000_READ_REG(hw, E1000_TCTL);
1381         mac_reg |= E1000_TCTL_EN;
1382         E1000_WRITE_REG(hw, E1000_TCTL, mac_reg);
1383
1384 release:
1385         hw->phy.ops.release(hw);
1386         if (force) {
1387                 hw->phy.ops.reset(hw);
1388                 msec_delay(50);
1389         }
1390 out:
1391         if (ret_val)
1392                 DEBUGOUT1("Error in ULP disable flow: %d\n", ret_val);
1393         else
1394                 hw->dev_spec.ich8lan.ulp_state = e1000_ulp_state_off;
1395
1396         return ret_val;
1397 }
1398
1399 #endif /* ULP_SUPPORT */
1400 /**
1401  *  e1000_check_for_copper_link_ich8lan - Check for link (Copper)
1402  *  @hw: pointer to the HW structure
1403  *
1404  *  Checks to see of the link status of the hardware has changed.  If a
1405  *  change in link status has been detected, then we read the PHY registers
1406  *  to get the current speed/duplex if link exists.
1407  **/
1408 STATIC s32 e1000_check_for_copper_link_ich8lan(struct e1000_hw *hw)
1409 {
1410         struct e1000_mac_info *mac = &hw->mac;
1411         s32 ret_val, tipg_reg = 0;
1412         u16 emi_addr, emi_val = 0;
1413         bool link = false;
1414         u16 phy_reg;
1415
1416         DEBUGFUNC("e1000_check_for_copper_link_ich8lan");
1417
1418         /* We only want to go out to the PHY registers to see if Auto-Neg
1419          * has completed and/or if our link status has changed.  The
1420          * get_link_status flag is set upon receiving a Link Status
1421          * Change or Rx Sequence Error interrupt.
1422          */
1423         if (!mac->get_link_status)
1424                 return E1000_SUCCESS;
1425
1426         if ((hw->mac.type < e1000_pch_lpt) ||
1427             (hw->device_id == E1000_DEV_ID_PCH_LPT_I217_LM) ||
1428             (hw->device_id == E1000_DEV_ID_PCH_LPT_I217_V)) {
1429                 /* First we want to see if the MII Status Register reports
1430                  * link.  If so, then we want to get the current speed/duplex
1431                  * of the PHY.
1432                  */
1433                 ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link);
1434                 if (ret_val)
1435                         return ret_val;
1436         } else {
1437                 /* Check the MAC's STATUS register to determine link state
1438                  * since the PHY could be inaccessible while in ULP mode.
1439                  */
1440                 link = !!(E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU);
1441                 if (link)
1442                         ret_val = e1000_disable_ulp_lpt_lp(hw, false);
1443                 else
1444                         ret_val = e1000_enable_ulp_lpt_lp(hw, false);
1445                 if (ret_val)
1446                         return ret_val;
1447         }
1448
1449         if (hw->mac.type == e1000_pchlan) {
1450                 ret_val = e1000_k1_gig_workaround_hv(hw, link);
1451                 if (ret_val)
1452                         return ret_val;
1453         }
1454
1455         /* When connected at 10Mbps half-duplex, some parts are excessively
1456          * aggressive resulting in many collisions. To avoid this, increase
1457          * the IPG and reduce Rx latency in the PHY.
1458          */
1459         if (((hw->mac.type == e1000_pch2lan) ||
1460              (hw->mac.type == e1000_pch_lpt)) && link) {
1461                 u16 speed, duplex;
1462
1463                 e1000_get_speed_and_duplex_copper_generic(hw, &speed, &duplex);
1464                 tipg_reg = E1000_READ_REG(hw, E1000_TIPG);
1465                 tipg_reg &= ~E1000_TIPG_IPGT_MASK;
1466
1467                 if (duplex == HALF_DUPLEX && speed == SPEED_10) {
1468                         tipg_reg |= 0xFF;
1469                         /* Reduce Rx latency in analog PHY */
1470                         emi_val = 0;
1471                 } else {
1472                         /* Roll back the default values */
1473                         tipg_reg |= 0x08;
1474                         emi_val = 1;
1475                 }
1476
1477                 E1000_WRITE_REG(hw, E1000_TIPG, tipg_reg);
1478
1479                 ret_val = hw->phy.ops.acquire(hw);
1480                 if (ret_val)
1481                         return ret_val;
1482
1483                 if (hw->mac.type == e1000_pch2lan)
1484                         emi_addr = I82579_RX_CONFIG;
1485                 else
1486                         emi_addr = I217_RX_CONFIG;
1487                 ret_val = e1000_write_emi_reg_locked(hw, emi_addr, emi_val);
1488
1489                 hw->phy.ops.release(hw);
1490
1491                 if (ret_val)
1492                         return ret_val;
1493         }
1494
1495         /* I217 Packet Loss issue:
1496          * ensure that FEXTNVM4 Beacon Duration is set correctly
1497          * on power up.
1498          * Set the Beacon Duration for I217 to 8 usec
1499          */
1500         if (hw->mac.type == e1000_pch_lpt) {
1501                 u32 mac_reg;
1502
1503                 mac_reg = E1000_READ_REG(hw, E1000_FEXTNVM4);
1504                 mac_reg &= ~E1000_FEXTNVM4_BEACON_DURATION_MASK;
1505                 mac_reg |= E1000_FEXTNVM4_BEACON_DURATION_8USEC;
1506                 E1000_WRITE_REG(hw, E1000_FEXTNVM4, mac_reg);
1507         }
1508
1509         /* Work-around I218 hang issue */
1510         if ((hw->device_id == E1000_DEV_ID_PCH_LPTLP_I218_LM) ||
1511             (hw->device_id == E1000_DEV_ID_PCH_LPTLP_I218_V) ||
1512             (hw->device_id == E1000_DEV_ID_PCH_I218_LM3) ||
1513             (hw->device_id == E1000_DEV_ID_PCH_I218_V3)) {
1514                 ret_val = e1000_k1_workaround_lpt_lp(hw, link);
1515                 if (ret_val)
1516                         return ret_val;
1517         }
1518         /* Clear link partner's EEE ability */
1519         hw->dev_spec.ich8lan.eee_lp_ability = 0;
1520
1521         /* Configure K0s minimum time */
1522         if (hw->mac.type == e1000_pch_lpt) {
1523                 e1000_configure_k0s_lpt(hw, K1_ENTRY_LATENCY, K1_MIN_TIME);
1524         }
1525
1526         if (!link)
1527                 return E1000_SUCCESS; /* No link detected */
1528
1529         mac->get_link_status = false;
1530
1531         switch (hw->mac.type) {
1532         case e1000_pch2lan:
1533                 ret_val = e1000_k1_workaround_lv(hw);
1534                 if (ret_val)
1535                         return ret_val;
1536                 /* fall-thru */
1537         case e1000_pchlan:
1538                 if (hw->phy.type == e1000_phy_82578) {
1539                         ret_val = e1000_link_stall_workaround_hv(hw);
1540                         if (ret_val)
1541                                 return ret_val;
1542                 }
1543
1544                 /* Workaround for PCHx parts in half-duplex:
1545                  * Set the number of preambles removed from the packet
1546                  * when it is passed from the PHY to the MAC to prevent
1547                  * the MAC from misinterpreting the packet type.
1548                  */
1549                 hw->phy.ops.read_reg(hw, HV_KMRN_FIFO_CTRLSTA, &phy_reg);
1550                 phy_reg &= ~HV_KMRN_FIFO_CTRLSTA_PREAMBLE_MASK;
1551
1552                 if ((E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_FD) !=
1553                     E1000_STATUS_FD)
1554                         phy_reg |= (1 << HV_KMRN_FIFO_CTRLSTA_PREAMBLE_SHIFT);
1555
1556                 hw->phy.ops.write_reg(hw, HV_KMRN_FIFO_CTRLSTA, phy_reg);
1557                 break;
1558         default:
1559                 break;
1560         }
1561
1562         /* Check if there was DownShift, must be checked
1563          * immediately after link-up
1564          */
1565         e1000_check_downshift_generic(hw);
1566
1567         /* Enable/Disable EEE after link up */
1568         if (hw->phy.type > e1000_phy_82579) {
1569                 ret_val = e1000_set_eee_pchlan(hw);
1570                 if (ret_val)
1571                         return ret_val;
1572         }
1573
1574         /* If we are forcing speed/duplex, then we simply return since
1575          * we have already determined whether we have link or not.
1576          */
1577         if (!mac->autoneg)
1578                 return -E1000_ERR_CONFIG;
1579
1580         /* Auto-Neg is enabled.  Auto Speed Detection takes care
1581          * of MAC speed/duplex configuration.  So we only need to
1582          * configure Collision Distance in the MAC.
1583          */
1584         mac->ops.config_collision_dist(hw);
1585
1586         /* Configure Flow Control now that Auto-Neg has completed.
1587          * First, we need to restore the desired flow control
1588          * settings because we may have had to re-autoneg with a
1589          * different link partner.
1590          */
1591         ret_val = e1000_config_fc_after_link_up_generic(hw);
1592         if (ret_val)
1593                 DEBUGOUT("Error configuring flow control\n");
1594
1595         return ret_val;
1596 }
1597
1598 /**
1599  *  e1000_init_function_pointers_ich8lan - Initialize ICH8 function pointers
1600  *  @hw: pointer to the HW structure
1601  *
1602  *  Initialize family-specific function pointers for PHY, MAC, and NVM.
1603  **/
1604 void e1000_init_function_pointers_ich8lan(struct e1000_hw *hw)
1605 {
1606         DEBUGFUNC("e1000_init_function_pointers_ich8lan");
1607
1608         hw->mac.ops.init_params = e1000_init_mac_params_ich8lan;
1609         hw->nvm.ops.init_params = e1000_init_nvm_params_ich8lan;
1610         switch (hw->mac.type) {
1611         case e1000_ich8lan:
1612         case e1000_ich9lan:
1613         case e1000_ich10lan:
1614                 hw->phy.ops.init_params = e1000_init_phy_params_ich8lan;
1615                 break;
1616         case e1000_pchlan:
1617         case e1000_pch2lan:
1618         case e1000_pch_lpt:
1619                 hw->phy.ops.init_params = e1000_init_phy_params_pchlan;
1620                 break;
1621         default:
1622                 break;
1623         }
1624 }
1625
1626 /**
1627  *  e1000_acquire_nvm_ich8lan - Acquire NVM mutex
1628  *  @hw: pointer to the HW structure
1629  *
1630  *  Acquires the mutex for performing NVM operations.
1631  **/
1632 STATIC s32 e1000_acquire_nvm_ich8lan(struct e1000_hw *hw)
1633 {
1634         DEBUGFUNC("e1000_acquire_nvm_ich8lan");
1635
1636         E1000_MUTEX_LOCK(&hw->dev_spec.ich8lan.nvm_mutex);
1637
1638         return E1000_SUCCESS;
1639 }
1640
1641 /**
1642  *  e1000_release_nvm_ich8lan - Release NVM mutex
1643  *  @hw: pointer to the HW structure
1644  *
1645  *  Releases the mutex used while performing NVM operations.
1646  **/
1647 STATIC void e1000_release_nvm_ich8lan(struct e1000_hw *hw)
1648 {
1649         DEBUGFUNC("e1000_release_nvm_ich8lan");
1650
1651         E1000_MUTEX_UNLOCK(&hw->dev_spec.ich8lan.nvm_mutex);
1652
1653         return;
1654 }
1655
1656 /**
1657  *  e1000_acquire_swflag_ich8lan - Acquire software control flag
1658  *  @hw: pointer to the HW structure
1659  *
1660  *  Acquires the software control flag for performing PHY and select
1661  *  MAC CSR accesses.
1662  **/
1663 STATIC s32 e1000_acquire_swflag_ich8lan(struct e1000_hw *hw)
1664 {
1665         u32 extcnf_ctrl, timeout = PHY_CFG_TIMEOUT;
1666         s32 ret_val = E1000_SUCCESS;
1667
1668         DEBUGFUNC("e1000_acquire_swflag_ich8lan");
1669
1670         E1000_MUTEX_LOCK(&hw->dev_spec.ich8lan.swflag_mutex);
1671
1672         while (timeout) {
1673                 extcnf_ctrl = E1000_READ_REG(hw, E1000_EXTCNF_CTRL);
1674                 if (!(extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG))
1675                         break;
1676
1677                 msec_delay_irq(1);
1678                 timeout--;
1679         }
1680
1681         if (!timeout) {
1682                 DEBUGOUT("SW has already locked the resource.\n");
1683                 ret_val = -E1000_ERR_CONFIG;
1684                 goto out;
1685         }
1686
1687         timeout = SW_FLAG_TIMEOUT;
1688
1689         extcnf_ctrl |= E1000_EXTCNF_CTRL_SWFLAG;
1690         E1000_WRITE_REG(hw, E1000_EXTCNF_CTRL, extcnf_ctrl);
1691
1692         while (timeout) {
1693                 extcnf_ctrl = E1000_READ_REG(hw, E1000_EXTCNF_CTRL);
1694                 if (extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG)
1695                         break;
1696
1697                 msec_delay_irq(1);
1698                 timeout--;
1699         }
1700
1701         if (!timeout) {
1702                 DEBUGOUT2("Failed to acquire the semaphore, FW or HW has it: FWSM=0x%8.8x EXTCNF_CTRL=0x%8.8x)\n",
1703                           E1000_READ_REG(hw, E1000_FWSM), extcnf_ctrl);
1704                 extcnf_ctrl &= ~E1000_EXTCNF_CTRL_SWFLAG;
1705                 E1000_WRITE_REG(hw, E1000_EXTCNF_CTRL, extcnf_ctrl);
1706                 ret_val = -E1000_ERR_CONFIG;
1707                 goto out;
1708         }
1709
1710 out:
1711         if (ret_val)
1712                 E1000_MUTEX_UNLOCK(&hw->dev_spec.ich8lan.swflag_mutex);
1713
1714         return ret_val;
1715 }
1716
1717 /**
1718  *  e1000_release_swflag_ich8lan - Release software control flag
1719  *  @hw: pointer to the HW structure
1720  *
1721  *  Releases the software control flag for performing PHY and select
1722  *  MAC CSR accesses.
1723  **/
1724 STATIC void e1000_release_swflag_ich8lan(struct e1000_hw *hw)
1725 {
1726         u32 extcnf_ctrl;
1727
1728         DEBUGFUNC("e1000_release_swflag_ich8lan");
1729
1730         extcnf_ctrl = E1000_READ_REG(hw, E1000_EXTCNF_CTRL);
1731
1732         if (extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG) {
1733                 extcnf_ctrl &= ~E1000_EXTCNF_CTRL_SWFLAG;
1734                 E1000_WRITE_REG(hw, E1000_EXTCNF_CTRL, extcnf_ctrl);
1735         } else {
1736                 DEBUGOUT("Semaphore unexpectedly released by sw/fw/hw\n");
1737         }
1738
1739         E1000_MUTEX_UNLOCK(&hw->dev_spec.ich8lan.swflag_mutex);
1740
1741         return;
1742 }
1743
1744 /**
1745  *  e1000_check_mng_mode_ich8lan - Checks management mode
1746  *  @hw: pointer to the HW structure
1747  *
1748  *  This checks if the adapter has any manageability enabled.
1749  *  This is a function pointer entry point only called by read/write
1750  *  routines for the PHY and NVM parts.
1751  **/
1752 STATIC bool e1000_check_mng_mode_ich8lan(struct e1000_hw *hw)
1753 {
1754         u32 fwsm;
1755
1756         DEBUGFUNC("e1000_check_mng_mode_ich8lan");
1757
1758         fwsm = E1000_READ_REG(hw, E1000_FWSM);
1759
1760         return (fwsm & E1000_ICH_FWSM_FW_VALID) &&
1761                ((fwsm & E1000_FWSM_MODE_MASK) ==
1762                 (E1000_ICH_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT));
1763 }
1764
1765 /**
1766  *  e1000_check_mng_mode_pchlan - Checks management mode
1767  *  @hw: pointer to the HW structure
1768  *
1769  *  This checks if the adapter has iAMT enabled.
1770  *  This is a function pointer entry point only called by read/write
1771  *  routines for the PHY and NVM parts.
1772  **/
1773 STATIC bool e1000_check_mng_mode_pchlan(struct e1000_hw *hw)
1774 {
1775         u32 fwsm;
1776
1777         DEBUGFUNC("e1000_check_mng_mode_pchlan");
1778
1779         fwsm = E1000_READ_REG(hw, E1000_FWSM);
1780
1781         return (fwsm & E1000_ICH_FWSM_FW_VALID) &&
1782                (fwsm & (E1000_ICH_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT));
1783 }
1784
1785 /**
1786  *  e1000_rar_set_pch2lan - Set receive address register
1787  *  @hw: pointer to the HW structure
1788  *  @addr: pointer to the receive address
1789  *  @index: receive address array register
1790  *
1791  *  Sets the receive address array register at index to the address passed
1792  *  in by addr.  For 82579, RAR[0] is the base address register that is to
1793  *  contain the MAC address but RAR[1-6] are reserved for manageability (ME).
1794  *  Use SHRA[0-3] in place of those reserved for ME.
1795  **/
1796 STATIC int e1000_rar_set_pch2lan(struct e1000_hw *hw, u8 *addr, u32 index)
1797 {
1798         u32 rar_low, rar_high;
1799
1800         DEBUGFUNC("e1000_rar_set_pch2lan");
1801
1802         /* HW expects these in little endian so we reverse the byte order
1803          * from network order (big endian) to little endian
1804          */
1805         rar_low = ((u32) addr[0] |
1806                    ((u32) addr[1] << 8) |
1807                    ((u32) addr[2] << 16) | ((u32) addr[3] << 24));
1808
1809         rar_high = ((u32) addr[4] | ((u32) addr[5] << 8));
1810
1811         /* If MAC address zero, no need to set the AV bit */
1812         if (rar_low || rar_high)
1813                 rar_high |= E1000_RAH_AV;
1814
1815         if (index == 0) {
1816                 E1000_WRITE_REG(hw, E1000_RAL(index), rar_low);
1817                 E1000_WRITE_FLUSH(hw);
1818                 E1000_WRITE_REG(hw, E1000_RAH(index), rar_high);
1819                 E1000_WRITE_FLUSH(hw);
1820                 return E1000_SUCCESS;
1821         }
1822
1823         /* RAR[1-6] are owned by manageability.  Skip those and program the
1824          * next address into the SHRA register array.
1825          */
1826         if (index < (u32) (hw->mac.rar_entry_count)) {
1827                 s32 ret_val;
1828
1829                 ret_val = e1000_acquire_swflag_ich8lan(hw);
1830                 if (ret_val)
1831                         goto out;
1832
1833                 E1000_WRITE_REG(hw, E1000_SHRAL(index - 1), rar_low);
1834                 E1000_WRITE_FLUSH(hw);
1835                 E1000_WRITE_REG(hw, E1000_SHRAH(index - 1), rar_high);
1836                 E1000_WRITE_FLUSH(hw);
1837
1838                 e1000_release_swflag_ich8lan(hw);
1839
1840                 /* verify the register updates */
1841                 if ((E1000_READ_REG(hw, E1000_SHRAL(index - 1)) == rar_low) &&
1842                     (E1000_READ_REG(hw, E1000_SHRAH(index - 1)) == rar_high))
1843                         return E1000_SUCCESS;
1844
1845                 DEBUGOUT2("SHRA[%d] might be locked by ME - FWSM=0x%8.8x\n",
1846                          (index - 1), E1000_READ_REG(hw, E1000_FWSM));
1847         }
1848
1849 out:
1850         DEBUGOUT1("Failed to write receive address at index %d\n", index);
1851         return -E1000_ERR_CONFIG;
1852 }
1853
1854 /**
1855  *  e1000_rar_set_pch_lpt - Set receive address registers
1856  *  @hw: pointer to the HW structure
1857  *  @addr: pointer to the receive address
1858  *  @index: receive address array register
1859  *
1860  *  Sets the receive address register array at index to the address passed
1861  *  in by addr. For LPT, RAR[0] is the base address register that is to
1862  *  contain the MAC address. SHRA[0-10] are the shared receive address
1863  *  registers that are shared between the Host and manageability engine (ME).
1864  **/
1865 STATIC int e1000_rar_set_pch_lpt(struct e1000_hw *hw, u8 *addr, u32 index)
1866 {
1867         u32 rar_low, rar_high;
1868         u32 wlock_mac;
1869
1870         DEBUGFUNC("e1000_rar_set_pch_lpt");
1871
1872         /* HW expects these in little endian so we reverse the byte order
1873          * from network order (big endian) to little endian
1874          */
1875         rar_low = ((u32) addr[0] | ((u32) addr[1] << 8) |
1876                    ((u32) addr[2] << 16) | ((u32) addr[3] << 24));
1877
1878         rar_high = ((u32) addr[4] | ((u32) addr[5] << 8));
1879
1880         /* If MAC address zero, no need to set the AV bit */
1881         if (rar_low || rar_high)
1882                 rar_high |= E1000_RAH_AV;
1883
1884         if (index == 0) {
1885                 E1000_WRITE_REG(hw, E1000_RAL(index), rar_low);
1886                 E1000_WRITE_FLUSH(hw);
1887                 E1000_WRITE_REG(hw, E1000_RAH(index), rar_high);
1888                 E1000_WRITE_FLUSH(hw);
1889                 return E1000_SUCCESS;
1890         }
1891
1892         /* The manageability engine (ME) can lock certain SHRAR registers that
1893          * it is using - those registers are unavailable for use.
1894          */
1895         if (index < hw->mac.rar_entry_count) {
1896                 wlock_mac = E1000_READ_REG(hw, E1000_FWSM) &
1897                             E1000_FWSM_WLOCK_MAC_MASK;
1898                 wlock_mac >>= E1000_FWSM_WLOCK_MAC_SHIFT;
1899
1900                 /* Check if all SHRAR registers are locked */
1901                 if (wlock_mac == 1)
1902                         goto out;
1903
1904                 if ((wlock_mac == 0) || (index <= wlock_mac)) {
1905                         s32 ret_val;
1906
1907                         ret_val = e1000_acquire_swflag_ich8lan(hw);
1908
1909                         if (ret_val)
1910                                 goto out;
1911
1912                         E1000_WRITE_REG(hw, E1000_SHRAL_PCH_LPT(index - 1),
1913                                         rar_low);
1914                         E1000_WRITE_FLUSH(hw);
1915                         E1000_WRITE_REG(hw, E1000_SHRAH_PCH_LPT(index - 1),
1916                                         rar_high);
1917                         E1000_WRITE_FLUSH(hw);
1918
1919                         e1000_release_swflag_ich8lan(hw);
1920
1921                         /* verify the register updates */
1922                         if ((E1000_READ_REG(hw, E1000_SHRAL_PCH_LPT(index - 1)) == rar_low) &&
1923                             (E1000_READ_REG(hw, E1000_SHRAH_PCH_LPT(index - 1)) == rar_high))
1924                                 return E1000_SUCCESS;
1925                 }
1926         }
1927
1928 out:
1929         DEBUGOUT1("Failed to write receive address at index %d\n", index);
1930         return -E1000_ERR_CONFIG;
1931 }
1932
1933 #ifndef NO_NON_BLOCKING_PHY_MTA_UPDATE_SUPPORT
1934 /**
1935  *  e1000_update_mc_addr_list_pch2lan - Update Multicast addresses
1936  *  @hw: pointer to the HW structure
1937  *  @mc_addr_list: array of multicast addresses to program
1938  *  @mc_addr_count: number of multicast addresses to program
1939  *
1940  *  Updates entire Multicast Table Array of the PCH2 MAC and PHY.
1941  *  The caller must have a packed mc_addr_list of multicast addresses.
1942  **/
1943 STATIC void e1000_update_mc_addr_list_pch2lan(struct e1000_hw *hw,
1944                                               u8 *mc_addr_list,
1945                                               u32 mc_addr_count)
1946 {
1947         u16 phy_reg = 0;
1948         int i;
1949         s32 ret_val;
1950
1951         DEBUGFUNC("e1000_update_mc_addr_list_pch2lan");
1952
1953         e1000_update_mc_addr_list_generic(hw, mc_addr_list, mc_addr_count);
1954
1955         ret_val = hw->phy.ops.acquire(hw);
1956         if (ret_val)
1957                 return;
1958
1959         ret_val = e1000_enable_phy_wakeup_reg_access_bm(hw, &phy_reg);
1960         if (ret_val)
1961                 goto release;
1962
1963         for (i = 0; i < hw->mac.mta_reg_count; i++) {
1964                 hw->phy.ops.write_reg_page(hw, BM_MTA(i),
1965                                            (u16)(hw->mac.mta_shadow[i] &
1966                                                  0xFFFF));
1967                 hw->phy.ops.write_reg_page(hw, (BM_MTA(i) + 1),
1968                                            (u16)((hw->mac.mta_shadow[i] >> 16) &
1969                                                  0xFFFF));
1970         }
1971
1972         e1000_disable_phy_wakeup_reg_access_bm(hw, &phy_reg);
1973
1974 release:
1975         hw->phy.ops.release(hw);
1976 }
1977
1978 #endif /* NO_NON_BLOCKING_PHY_MTA_UPDATE_SUPPORT */
1979 /**
1980  *  e1000_check_reset_block_ich8lan - Check if PHY reset is blocked
1981  *  @hw: pointer to the HW structure
1982  *
1983  *  Checks if firmware is blocking the reset of the PHY.
1984  *  This is a function pointer entry point only called by
1985  *  reset routines.
1986  **/
1987 STATIC s32 e1000_check_reset_block_ich8lan(struct e1000_hw *hw)
1988 {
1989         u32 fwsm;
1990         bool blocked = false;
1991         int i = 0;
1992
1993         DEBUGFUNC("e1000_check_reset_block_ich8lan");
1994
1995         do {
1996                 fwsm = E1000_READ_REG(hw, E1000_FWSM);
1997                 if (!(fwsm & E1000_ICH_FWSM_RSPCIPHY)) {
1998                         blocked = true;
1999                         msec_delay(10);
2000                         continue;
2001                 }
2002                 blocked = false;
2003         } while (blocked && (i++ < 30));
2004         return blocked ? E1000_BLK_PHY_RESET : E1000_SUCCESS;
2005 }
2006
2007 /**
2008  *  e1000_write_smbus_addr - Write SMBus address to PHY needed during Sx states
2009  *  @hw: pointer to the HW structure
2010  *
2011  *  Assumes semaphore already acquired.
2012  *
2013  **/
2014 STATIC s32 e1000_write_smbus_addr(struct e1000_hw *hw)
2015 {
2016         u16 phy_data;
2017         u32 strap = E1000_READ_REG(hw, E1000_STRAP);
2018         u32 freq = (strap & E1000_STRAP_SMT_FREQ_MASK) >>
2019                 E1000_STRAP_SMT_FREQ_SHIFT;
2020         s32 ret_val;
2021
2022         strap &= E1000_STRAP_SMBUS_ADDRESS_MASK;
2023
2024         ret_val = e1000_read_phy_reg_hv_locked(hw, HV_SMB_ADDR, &phy_data);
2025         if (ret_val)
2026                 return ret_val;
2027
2028         phy_data &= ~HV_SMB_ADDR_MASK;
2029         phy_data |= (strap >> E1000_STRAP_SMBUS_ADDRESS_SHIFT);
2030         phy_data |= HV_SMB_ADDR_PEC_EN | HV_SMB_ADDR_VALID;
2031
2032         if (hw->phy.type == e1000_phy_i217) {
2033                 /* Restore SMBus frequency */
2034                 if (freq--) {
2035                         phy_data &= ~HV_SMB_ADDR_FREQ_MASK;
2036                         phy_data |= (freq & (1 << 0)) <<
2037                                 HV_SMB_ADDR_FREQ_LOW_SHIFT;
2038                         phy_data |= (freq & (1 << 1)) <<
2039                                 (HV_SMB_ADDR_FREQ_HIGH_SHIFT - 1);
2040                 } else {
2041                         DEBUGOUT("Unsupported SMB frequency in PHY\n");
2042                 }
2043         }
2044
2045         return e1000_write_phy_reg_hv_locked(hw, HV_SMB_ADDR, phy_data);
2046 }
2047
2048 /**
2049  *  e1000_sw_lcd_config_ich8lan - SW-based LCD Configuration
2050  *  @hw:   pointer to the HW structure
2051  *
2052  *  SW should configure the LCD from the NVM extended configuration region
2053  *  as a workaround for certain parts.
2054  **/
2055 STATIC s32 e1000_sw_lcd_config_ich8lan(struct e1000_hw *hw)
2056 {
2057         struct e1000_phy_info *phy = &hw->phy;
2058         u32 i, data, cnf_size, cnf_base_addr, sw_cfg_mask;
2059         s32 ret_val = E1000_SUCCESS;
2060         u16 word_addr, reg_data, reg_addr, phy_page = 0;
2061
2062         DEBUGFUNC("e1000_sw_lcd_config_ich8lan");
2063
2064         /* Initialize the PHY from the NVM on ICH platforms.  This
2065          * is needed due to an issue where the NVM configuration is
2066          * not properly autoloaded after power transitions.
2067          * Therefore, after each PHY reset, we will load the
2068          * configuration data out of the NVM manually.
2069          */
2070         switch (hw->mac.type) {
2071         case e1000_ich8lan:
2072                 if (phy->type != e1000_phy_igp_3)
2073                         return ret_val;
2074
2075                 if ((hw->device_id == E1000_DEV_ID_ICH8_IGP_AMT) ||
2076                     (hw->device_id == E1000_DEV_ID_ICH8_IGP_C)) {
2077                         sw_cfg_mask = E1000_FEXTNVM_SW_CONFIG;
2078                         break;
2079                 }
2080                 /* Fall-thru */
2081         case e1000_pchlan:
2082         case e1000_pch2lan:
2083         case e1000_pch_lpt:
2084                 sw_cfg_mask = E1000_FEXTNVM_SW_CONFIG_ICH8M;
2085                 break;
2086         default:
2087                 return ret_val;
2088         }
2089
2090         ret_val = hw->phy.ops.acquire(hw);
2091         if (ret_val)
2092                 return ret_val;
2093
2094         data = E1000_READ_REG(hw, E1000_FEXTNVM);
2095         if (!(data & sw_cfg_mask))
2096                 goto release;
2097
2098         /* Make sure HW does not configure LCD from PHY
2099          * extended configuration before SW configuration
2100          */
2101         data = E1000_READ_REG(hw, E1000_EXTCNF_CTRL);
2102         if ((hw->mac.type < e1000_pch2lan) &&
2103             (data & E1000_EXTCNF_CTRL_LCD_WRITE_ENABLE))
2104                         goto release;
2105
2106         cnf_size = E1000_READ_REG(hw, E1000_EXTCNF_SIZE);
2107         cnf_size &= E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_MASK;
2108         cnf_size >>= E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_SHIFT;
2109         if (!cnf_size)
2110                 goto release;
2111
2112         cnf_base_addr = data & E1000_EXTCNF_CTRL_EXT_CNF_POINTER_MASK;
2113         cnf_base_addr >>= E1000_EXTCNF_CTRL_EXT_CNF_POINTER_SHIFT;
2114
2115         if (((hw->mac.type == e1000_pchlan) &&
2116              !(data & E1000_EXTCNF_CTRL_OEM_WRITE_ENABLE)) ||
2117             (hw->mac.type > e1000_pchlan)) {
2118                 /* HW configures the SMBus address and LEDs when the
2119                  * OEM and LCD Write Enable bits are set in the NVM.
2120                  * When both NVM bits are cleared, SW will configure
2121                  * them instead.
2122                  */
2123                 ret_val = e1000_write_smbus_addr(hw);
2124                 if (ret_val)
2125                         goto release;
2126
2127                 data = E1000_READ_REG(hw, E1000_LEDCTL);
2128                 ret_val = e1000_write_phy_reg_hv_locked(hw, HV_LED_CONFIG,
2129                                                         (u16)data);
2130                 if (ret_val)
2131                         goto release;
2132         }
2133
2134         /* Configure LCD from extended configuration region. */
2135
2136         /* cnf_base_addr is in DWORD */
2137         word_addr = (u16)(cnf_base_addr << 1);
2138
2139         for (i = 0; i < cnf_size; i++) {
2140                 ret_val = hw->nvm.ops.read(hw, (word_addr + i * 2), 1,
2141                                            &reg_data);
2142                 if (ret_val)
2143                         goto release;
2144
2145                 ret_val = hw->nvm.ops.read(hw, (word_addr + i * 2 + 1),
2146                                            1, &reg_addr);
2147                 if (ret_val)
2148                         goto release;
2149
2150                 /* Save off the PHY page for future writes. */
2151                 if (reg_addr == IGP01E1000_PHY_PAGE_SELECT) {
2152                         phy_page = reg_data;
2153                         continue;
2154                 }
2155
2156                 reg_addr &= PHY_REG_MASK;
2157                 reg_addr |= phy_page;
2158
2159                 ret_val = phy->ops.write_reg_locked(hw, (u32)reg_addr,
2160                                                     reg_data);
2161                 if (ret_val)
2162                         goto release;
2163         }
2164
2165 release:
2166         hw->phy.ops.release(hw);
2167         return ret_val;
2168 }
2169
2170 /**
2171  *  e1000_k1_gig_workaround_hv - K1 Si workaround
2172  *  @hw:   pointer to the HW structure
2173  *  @link: link up bool flag
2174  *
2175  *  If K1 is enabled for 1Gbps, the MAC might stall when transitioning
2176  *  from a lower speed.  This workaround disables K1 whenever link is at 1Gig
2177  *  If link is down, the function will restore the default K1 setting located
2178  *  in the NVM.
2179  **/
2180 STATIC s32 e1000_k1_gig_workaround_hv(struct e1000_hw *hw, bool link)
2181 {
2182         s32 ret_val = E1000_SUCCESS;
2183         u16 status_reg = 0;
2184         bool k1_enable = hw->dev_spec.ich8lan.nvm_k1_enabled;
2185
2186         DEBUGFUNC("e1000_k1_gig_workaround_hv");
2187
2188         if (hw->mac.type != e1000_pchlan)
2189                 return E1000_SUCCESS;
2190
2191         /* Wrap the whole flow with the sw flag */
2192         ret_val = hw->phy.ops.acquire(hw);
2193         if (ret_val)
2194                 return ret_val;
2195
2196         /* Disable K1 when link is 1Gbps, otherwise use the NVM setting */
2197         if (link) {
2198                 if (hw->phy.type == e1000_phy_82578) {
2199                         ret_val = hw->phy.ops.read_reg_locked(hw, BM_CS_STATUS,
2200                                                               &status_reg);
2201                         if (ret_val)
2202                                 goto release;
2203
2204                         status_reg &= (BM_CS_STATUS_LINK_UP |
2205                                        BM_CS_STATUS_RESOLVED |
2206                                        BM_CS_STATUS_SPEED_MASK);
2207
2208                         if (status_reg == (BM_CS_STATUS_LINK_UP |
2209                                            BM_CS_STATUS_RESOLVED |
2210                                            BM_CS_STATUS_SPEED_1000))
2211                                 k1_enable = false;
2212                 }
2213
2214                 if (hw->phy.type == e1000_phy_82577) {
2215                         ret_val = hw->phy.ops.read_reg_locked(hw, HV_M_STATUS,
2216                                                               &status_reg);
2217                         if (ret_val)
2218                                 goto release;
2219
2220                         status_reg &= (HV_M_STATUS_LINK_UP |
2221                                        HV_M_STATUS_AUTONEG_COMPLETE |
2222                                        HV_M_STATUS_SPEED_MASK);
2223
2224                         if (status_reg == (HV_M_STATUS_LINK_UP |
2225                                            HV_M_STATUS_AUTONEG_COMPLETE |
2226                                            HV_M_STATUS_SPEED_1000))
2227                                 k1_enable = false;
2228                 }
2229
2230                 /* Link stall fix for link up */
2231                 ret_val = hw->phy.ops.write_reg_locked(hw, PHY_REG(770, 19),
2232                                                        0x0100);
2233                 if (ret_val)
2234                         goto release;
2235
2236         } else {
2237                 /* Link stall fix for link down */
2238                 ret_val = hw->phy.ops.write_reg_locked(hw, PHY_REG(770, 19),
2239                                                        0x4100);
2240                 if (ret_val)
2241                         goto release;
2242         }
2243
2244         ret_val = e1000_configure_k1_ich8lan(hw, k1_enable);
2245
2246 release:
2247         hw->phy.ops.release(hw);
2248
2249         return ret_val;
2250 }
2251
2252 /**
2253  *  e1000_configure_k1_ich8lan - Configure K1 power state
2254  *  @hw: pointer to the HW structure
2255  *  @enable: K1 state to configure
2256  *
2257  *  Configure the K1 power state based on the provided parameter.
2258  *  Assumes semaphore already acquired.
2259  *
2260  *  Success returns 0, Failure returns -E1000_ERR_PHY (-2)
2261  **/
2262 s32 e1000_configure_k1_ich8lan(struct e1000_hw *hw, bool k1_enable)
2263 {
2264         s32 ret_val;
2265         u32 ctrl_reg = 0;
2266         u32 ctrl_ext = 0;
2267         u32 reg = 0;
2268         u16 kmrn_reg = 0;
2269
2270         DEBUGFUNC("e1000_configure_k1_ich8lan");
2271
2272         ret_val = e1000_read_kmrn_reg_locked(hw, E1000_KMRNCTRLSTA_K1_CONFIG,
2273                                              &kmrn_reg);
2274         if (ret_val)
2275                 return ret_val;
2276
2277         if (k1_enable)
2278                 kmrn_reg |= E1000_KMRNCTRLSTA_K1_ENABLE;
2279         else
2280                 kmrn_reg &= ~E1000_KMRNCTRLSTA_K1_ENABLE;
2281
2282         ret_val = e1000_write_kmrn_reg_locked(hw, E1000_KMRNCTRLSTA_K1_CONFIG,
2283                                               kmrn_reg);
2284         if (ret_val)
2285                 return ret_val;
2286
2287         usec_delay(20);
2288         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
2289         ctrl_reg = E1000_READ_REG(hw, E1000_CTRL);
2290
2291         reg = ctrl_reg & ~(E1000_CTRL_SPD_1000 | E1000_CTRL_SPD_100);
2292         reg |= E1000_CTRL_FRCSPD;
2293         E1000_WRITE_REG(hw, E1000_CTRL, reg);
2294
2295         E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext | E1000_CTRL_EXT_SPD_BYPS);
2296         E1000_WRITE_FLUSH(hw);
2297         usec_delay(20);
2298         E1000_WRITE_REG(hw, E1000_CTRL, ctrl_reg);
2299         E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
2300         E1000_WRITE_FLUSH(hw);
2301         usec_delay(20);
2302
2303         return E1000_SUCCESS;
2304 }
2305
2306 /**
2307  *  e1000_oem_bits_config_ich8lan - SW-based LCD Configuration
2308  *  @hw:       pointer to the HW structure
2309  *  @d0_state: boolean if entering d0 or d3 device state
2310  *
2311  *  SW will configure Gbe Disable and LPLU based on the NVM. The four bits are
2312  *  collectively called OEM bits.  The OEM Write Enable bit and SW Config bit
2313  *  in NVM determines whether HW should configure LPLU and Gbe Disable.
2314  **/
2315 STATIC s32 e1000_oem_bits_config_ich8lan(struct e1000_hw *hw, bool d0_state)
2316 {
2317         s32 ret_val = 0;
2318         u32 mac_reg;
2319         u16 oem_reg;
2320
2321         DEBUGFUNC("e1000_oem_bits_config_ich8lan");
2322
2323         if (hw->mac.type < e1000_pchlan)
2324                 return ret_val;
2325
2326         ret_val = hw->phy.ops.acquire(hw);
2327         if (ret_val)
2328                 return ret_val;
2329
2330         if (hw->mac.type == e1000_pchlan) {
2331                 mac_reg = E1000_READ_REG(hw, E1000_EXTCNF_CTRL);
2332                 if (mac_reg & E1000_EXTCNF_CTRL_OEM_WRITE_ENABLE)
2333                         goto release;
2334         }
2335
2336         mac_reg = E1000_READ_REG(hw, E1000_FEXTNVM);
2337         if (!(mac_reg & E1000_FEXTNVM_SW_CONFIG_ICH8M))
2338                 goto release;
2339
2340         mac_reg = E1000_READ_REG(hw, E1000_PHY_CTRL);
2341
2342         ret_val = hw->phy.ops.read_reg_locked(hw, HV_OEM_BITS, &oem_reg);
2343         if (ret_val)
2344                 goto release;
2345
2346         oem_reg &= ~(HV_OEM_BITS_GBE_DIS | HV_OEM_BITS_LPLU);
2347
2348         if (d0_state) {
2349                 if (mac_reg & E1000_PHY_CTRL_GBE_DISABLE)
2350                         oem_reg |= HV_OEM_BITS_GBE_DIS;
2351
2352                 if (mac_reg & E1000_PHY_CTRL_D0A_LPLU)
2353                         oem_reg |= HV_OEM_BITS_LPLU;
2354         } else {
2355                 if (mac_reg & (E1000_PHY_CTRL_GBE_DISABLE |
2356                     E1000_PHY_CTRL_NOND0A_GBE_DISABLE))
2357                         oem_reg |= HV_OEM_BITS_GBE_DIS;
2358
2359                 if (mac_reg & (E1000_PHY_CTRL_D0A_LPLU |
2360                     E1000_PHY_CTRL_NOND0A_LPLU))
2361                         oem_reg |= HV_OEM_BITS_LPLU;
2362         }
2363
2364         /* Set Restart auto-neg to activate the bits */
2365         if ((d0_state || (hw->mac.type != e1000_pchlan)) &&
2366             !hw->phy.ops.check_reset_block(hw))
2367                 oem_reg |= HV_OEM_BITS_RESTART_AN;
2368
2369         ret_val = hw->phy.ops.write_reg_locked(hw, HV_OEM_BITS, oem_reg);
2370
2371 release:
2372         hw->phy.ops.release(hw);
2373
2374         return ret_val;
2375 }
2376
2377
2378 /**
2379  *  e1000_set_mdio_slow_mode_hv - Set slow MDIO access mode
2380  *  @hw:   pointer to the HW structure
2381  **/
2382 STATIC s32 e1000_set_mdio_slow_mode_hv(struct e1000_hw *hw)
2383 {
2384         s32 ret_val;
2385         u16 data;
2386
2387         DEBUGFUNC("e1000_set_mdio_slow_mode_hv");
2388
2389         ret_val = hw->phy.ops.read_reg(hw, HV_KMRN_MODE_CTRL, &data);
2390         if (ret_val)
2391                 return ret_val;
2392
2393         data |= HV_KMRN_MDIO_SLOW;
2394
2395         ret_val = hw->phy.ops.write_reg(hw, HV_KMRN_MODE_CTRL, data);
2396
2397         return ret_val;
2398 }
2399
2400 /**
2401  *  e1000_hv_phy_workarounds_ich8lan - A series of Phy workarounds to be
2402  *  done after every PHY reset.
2403  **/
2404 STATIC s32 e1000_hv_phy_workarounds_ich8lan(struct e1000_hw *hw)
2405 {
2406         s32 ret_val = E1000_SUCCESS;
2407         u16 phy_data;
2408
2409         DEBUGFUNC("e1000_hv_phy_workarounds_ich8lan");
2410
2411         if (hw->mac.type != e1000_pchlan)
2412                 return E1000_SUCCESS;
2413
2414         /* Set MDIO slow mode before any other MDIO access */
2415         if (hw->phy.type == e1000_phy_82577) {
2416                 ret_val = e1000_set_mdio_slow_mode_hv(hw);
2417                 if (ret_val)
2418                         return ret_val;
2419         }
2420
2421         if (((hw->phy.type == e1000_phy_82577) &&
2422              ((hw->phy.revision == 1) || (hw->phy.revision == 2))) ||
2423             ((hw->phy.type == e1000_phy_82578) && (hw->phy.revision == 1))) {
2424                 /* Disable generation of early preamble */
2425                 ret_val = hw->phy.ops.write_reg(hw, PHY_REG(769, 25), 0x4431);
2426                 if (ret_val)
2427                         return ret_val;
2428
2429                 /* Preamble tuning for SSC */
2430                 ret_val = hw->phy.ops.write_reg(hw, HV_KMRN_FIFO_CTRLSTA,
2431                                                 0xA204);
2432                 if (ret_val)
2433                         return ret_val;
2434         }
2435
2436         if (hw->phy.type == e1000_phy_82578) {
2437                 /* Return registers to default by doing a soft reset then
2438                  * writing 0x3140 to the control register.
2439                  */
2440                 if (hw->phy.revision < 2) {
2441                         e1000_phy_sw_reset_generic(hw);
2442                         ret_val = hw->phy.ops.write_reg(hw, PHY_CONTROL,
2443                                                         0x3140);
2444                 }
2445         }
2446
2447         /* Select page 0 */
2448         ret_val = hw->phy.ops.acquire(hw);
2449         if (ret_val)
2450                 return ret_val;
2451
2452         hw->phy.addr = 1;
2453         ret_val = e1000_write_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT, 0);
2454         hw->phy.ops.release(hw);
2455         if (ret_val)
2456                 return ret_val;
2457
2458         /* Configure the K1 Si workaround during phy reset assuming there is
2459          * link so that it disables K1 if link is in 1Gbps.
2460          */
2461         ret_val = e1000_k1_gig_workaround_hv(hw, true);
2462         if (ret_val)
2463                 return ret_val;
2464
2465         /* Workaround for link disconnects on a busy hub in half duplex */
2466         ret_val = hw->phy.ops.acquire(hw);
2467         if (ret_val)
2468                 return ret_val;
2469         ret_val = hw->phy.ops.read_reg_locked(hw, BM_PORT_GEN_CFG, &phy_data);
2470         if (ret_val)
2471                 goto release;
2472         ret_val = hw->phy.ops.write_reg_locked(hw, BM_PORT_GEN_CFG,
2473                                                phy_data & 0x00FF);
2474         if (ret_val)
2475                 goto release;
2476
2477         /* set MSE higher to enable link to stay up when noise is high */
2478         ret_val = e1000_write_emi_reg_locked(hw, I82577_MSE_THRESHOLD, 0x0034);
2479 release:
2480         hw->phy.ops.release(hw);
2481
2482         return ret_val;
2483 }
2484
2485 /**
2486  *  e1000_copy_rx_addrs_to_phy_ich8lan - Copy Rx addresses from MAC to PHY
2487  *  @hw:   pointer to the HW structure
2488  **/
2489 void e1000_copy_rx_addrs_to_phy_ich8lan(struct e1000_hw *hw)
2490 {
2491         u32 mac_reg;
2492         u16 i, phy_reg = 0;
2493         s32 ret_val;
2494
2495         DEBUGFUNC("e1000_copy_rx_addrs_to_phy_ich8lan");
2496
2497         ret_val = hw->phy.ops.acquire(hw);
2498         if (ret_val)
2499                 return;
2500         ret_val = e1000_enable_phy_wakeup_reg_access_bm(hw, &phy_reg);
2501         if (ret_val)
2502                 goto release;
2503
2504         /* Copy both RAL/H (rar_entry_count) and SHRAL/H to PHY */
2505         for (i = 0; i < (hw->mac.rar_entry_count); i++) {
2506                 mac_reg = E1000_READ_REG(hw, E1000_RAL(i));
2507                 hw->phy.ops.write_reg_page(hw, BM_RAR_L(i),
2508                                            (u16)(mac_reg & 0xFFFF));
2509                 hw->phy.ops.write_reg_page(hw, BM_RAR_M(i),
2510                                            (u16)((mac_reg >> 16) & 0xFFFF));
2511
2512                 mac_reg = E1000_READ_REG(hw, E1000_RAH(i));
2513                 hw->phy.ops.write_reg_page(hw, BM_RAR_H(i),
2514                                            (u16)(mac_reg & 0xFFFF));
2515                 hw->phy.ops.write_reg_page(hw, BM_RAR_CTRL(i),
2516                                            (u16)((mac_reg & E1000_RAH_AV)
2517                                                  >> 16));
2518         }
2519
2520         e1000_disable_phy_wakeup_reg_access_bm(hw, &phy_reg);
2521
2522 release:
2523         hw->phy.ops.release(hw);
2524 }
2525
2526 #ifndef CRC32_OS_SUPPORT
2527 STATIC u32 e1000_calc_rx_da_crc(u8 mac[])
2528 {
2529         u32 poly = 0xEDB88320;  /* Polynomial for 802.3 CRC calculation */
2530         u32 i, j, mask, crc;
2531
2532         DEBUGFUNC("e1000_calc_rx_da_crc");
2533
2534         crc = 0xffffffff;
2535         for (i = 0; i < 6; i++) {
2536                 crc = crc ^ mac[i];
2537                 for (j = 8; j > 0; j--) {
2538                         mask = (crc & 1) * (-1);
2539                         crc = (crc >> 1) ^ (poly & mask);
2540                 }
2541         }
2542         return ~crc;
2543 }
2544
2545 #endif /* CRC32_OS_SUPPORT */
2546 /**
2547  *  e1000_lv_jumbo_workaround_ich8lan - required for jumbo frame operation
2548  *  with 82579 PHY
2549  *  @hw: pointer to the HW structure
2550  *  @enable: flag to enable/disable workaround when enabling/disabling jumbos
2551  **/
2552 s32 e1000_lv_jumbo_workaround_ich8lan(struct e1000_hw *hw, bool enable)
2553 {
2554         s32 ret_val = E1000_SUCCESS;
2555         u16 phy_reg, data;
2556         u32 mac_reg;
2557         u16 i;
2558
2559         DEBUGFUNC("e1000_lv_jumbo_workaround_ich8lan");
2560
2561         if (hw->mac.type < e1000_pch2lan)
2562                 return E1000_SUCCESS;
2563
2564         /* disable Rx path while enabling/disabling workaround */
2565         hw->phy.ops.read_reg(hw, PHY_REG(769, 20), &phy_reg);
2566         ret_val = hw->phy.ops.write_reg(hw, PHY_REG(769, 20),
2567                                         phy_reg | (1 << 14));
2568         if (ret_val)
2569                 return ret_val;
2570
2571         if (enable) {
2572                 /* Write Rx addresses (rar_entry_count for RAL/H, and
2573                  * SHRAL/H) and initial CRC values to the MAC
2574                  */
2575                 for (i = 0; i < hw->mac.rar_entry_count; i++) {
2576                         u8 mac_addr[ETH_ADDR_LEN] = {0};
2577                         u32 addr_high, addr_low;
2578
2579                         addr_high = E1000_READ_REG(hw, E1000_RAH(i));
2580                         if (!(addr_high & E1000_RAH_AV))
2581                                 continue;
2582                         addr_low = E1000_READ_REG(hw, E1000_RAL(i));
2583                         mac_addr[0] = (addr_low & 0xFF);
2584                         mac_addr[1] = ((addr_low >> 8) & 0xFF);
2585                         mac_addr[2] = ((addr_low >> 16) & 0xFF);
2586                         mac_addr[3] = ((addr_low >> 24) & 0xFF);
2587                         mac_addr[4] = (addr_high & 0xFF);
2588                         mac_addr[5] = ((addr_high >> 8) & 0xFF);
2589
2590 #ifndef CRC32_OS_SUPPORT
2591                         E1000_WRITE_REG(hw, E1000_PCH_RAICC(i),
2592                                         e1000_calc_rx_da_crc(mac_addr));
2593 #else /* CRC32_OS_SUPPORT */
2594                         E1000_WRITE_REG(hw, E1000_PCH_RAICC(i),
2595                                         E1000_CRC32(ETH_ADDR_LEN, mac_addr));
2596 #endif /* CRC32_OS_SUPPORT */
2597                 }
2598
2599                 /* Write Rx addresses to the PHY */
2600                 e1000_copy_rx_addrs_to_phy_ich8lan(hw);
2601
2602                 /* Enable jumbo frame workaround in the MAC */
2603                 mac_reg = E1000_READ_REG(hw, E1000_FFLT_DBG);
2604                 mac_reg &= ~(1 << 14);
2605                 mac_reg |= (7 << 15);
2606                 E1000_WRITE_REG(hw, E1000_FFLT_DBG, mac_reg);
2607
2608                 mac_reg = E1000_READ_REG(hw, E1000_RCTL);
2609                 mac_reg |= E1000_RCTL_SECRC;
2610                 E1000_WRITE_REG(hw, E1000_RCTL, mac_reg);
2611
2612                 ret_val = e1000_read_kmrn_reg_generic(hw,
2613                                                 E1000_KMRNCTRLSTA_CTRL_OFFSET,
2614                                                 &data);
2615                 if (ret_val)
2616                         return ret_val;
2617                 ret_val = e1000_write_kmrn_reg_generic(hw,
2618                                                 E1000_KMRNCTRLSTA_CTRL_OFFSET,
2619                                                 data | (1 << 0));
2620                 if (ret_val)
2621                         return ret_val;
2622                 ret_val = e1000_read_kmrn_reg_generic(hw,
2623                                                 E1000_KMRNCTRLSTA_HD_CTRL,
2624                                                 &data);
2625                 if (ret_val)
2626                         return ret_val;
2627                 data &= ~(0xF << 8);
2628                 data |= (0xB << 8);
2629                 ret_val = e1000_write_kmrn_reg_generic(hw,
2630                                                 E1000_KMRNCTRLSTA_HD_CTRL,
2631                                                 data);
2632                 if (ret_val)
2633                         return ret_val;
2634
2635                 /* Enable jumbo frame workaround in the PHY */
2636                 hw->phy.ops.read_reg(hw, PHY_REG(769, 23), &data);
2637                 data &= ~(0x7F << 5);
2638                 data |= (0x37 << 5);
2639                 ret_val = hw->phy.ops.write_reg(hw, PHY_REG(769, 23), data);
2640                 if (ret_val)
2641                         return ret_val;
2642                 hw->phy.ops.read_reg(hw, PHY_REG(769, 16), &data);
2643                 data &= ~(1 << 13);
2644                 ret_val = hw->phy.ops.write_reg(hw, PHY_REG(769, 16), data);
2645                 if (ret_val)
2646                         return ret_val;
2647                 hw->phy.ops.read_reg(hw, PHY_REG(776, 20), &data);
2648                 data &= ~(0x3FF << 2);
2649                 data |= (E1000_TX_PTR_GAP << 2);
2650                 ret_val = hw->phy.ops.write_reg(hw, PHY_REG(776, 20), data);
2651                 if (ret_val)
2652                         return ret_val;
2653                 ret_val = hw->phy.ops.write_reg(hw, PHY_REG(776, 23), 0xF100);
2654                 if (ret_val)
2655                         return ret_val;
2656                 hw->phy.ops.read_reg(hw, HV_PM_CTRL, &data);
2657                 ret_val = hw->phy.ops.write_reg(hw, HV_PM_CTRL, data |
2658                                                 (1 << 10));
2659                 if (ret_val)
2660                         return ret_val;
2661         } else {
2662                 /* Write MAC register values back to h/w defaults */
2663                 mac_reg = E1000_READ_REG(hw, E1000_FFLT_DBG);
2664                 mac_reg &= ~(0xF << 14);
2665                 E1000_WRITE_REG(hw, E1000_FFLT_DBG, mac_reg);
2666
2667                 mac_reg = E1000_READ_REG(hw, E1000_RCTL);
2668                 mac_reg &= ~E1000_RCTL_SECRC;
2669                 E1000_WRITE_REG(hw, E1000_RCTL, mac_reg);
2670
2671                 ret_val = e1000_read_kmrn_reg_generic(hw,
2672                                                 E1000_KMRNCTRLSTA_CTRL_OFFSET,
2673                                                 &data);
2674                 if (ret_val)
2675                         return ret_val;
2676                 ret_val = e1000_write_kmrn_reg_generic(hw,
2677                                                 E1000_KMRNCTRLSTA_CTRL_OFFSET,
2678                                                 data & ~(1 << 0));
2679                 if (ret_val)
2680                         return ret_val;
2681                 ret_val = e1000_read_kmrn_reg_generic(hw,
2682                                                 E1000_KMRNCTRLSTA_HD_CTRL,
2683                                                 &data);
2684                 if (ret_val)
2685                         return ret_val;
2686                 data &= ~(0xF << 8);
2687                 data |= (0xB << 8);
2688                 ret_val = e1000_write_kmrn_reg_generic(hw,
2689                                                 E1000_KMRNCTRLSTA_HD_CTRL,
2690                                                 data);
2691                 if (ret_val)
2692                         return ret_val;
2693
2694                 /* Write PHY register values back to h/w defaults */
2695                 hw->phy.ops.read_reg(hw, PHY_REG(769, 23), &data);
2696                 data &= ~(0x7F << 5);
2697                 ret_val = hw->phy.ops.write_reg(hw, PHY_REG(769, 23), data);
2698                 if (ret_val)
2699                         return ret_val;
2700                 hw->phy.ops.read_reg(hw, PHY_REG(769, 16), &data);
2701                 data |= (1 << 13);
2702                 ret_val = hw->phy.ops.write_reg(hw, PHY_REG(769, 16), data);
2703                 if (ret_val)
2704                         return ret_val;
2705                 hw->phy.ops.read_reg(hw, PHY_REG(776, 20), &data);
2706                 data &= ~(0x3FF << 2);
2707                 data |= (0x8 << 2);
2708                 ret_val = hw->phy.ops.write_reg(hw, PHY_REG(776, 20), data);
2709                 if (ret_val)
2710                         return ret_val;
2711                 ret_val = hw->phy.ops.write_reg(hw, PHY_REG(776, 23), 0x7E00);
2712                 if (ret_val)
2713                         return ret_val;
2714                 hw->phy.ops.read_reg(hw, HV_PM_CTRL, &data);
2715                 ret_val = hw->phy.ops.write_reg(hw, HV_PM_CTRL, data &
2716                                                 ~(1 << 10));
2717                 if (ret_val)
2718                         return ret_val;
2719         }
2720
2721         /* re-enable Rx path after enabling/disabling workaround */
2722         return hw->phy.ops.write_reg(hw, PHY_REG(769, 20), phy_reg &
2723                                      ~(1 << 14));
2724 }
2725
2726 /**
2727  *  e1000_lv_phy_workarounds_ich8lan - A series of Phy workarounds to be
2728  *  done after every PHY reset.
2729  **/
2730 STATIC s32 e1000_lv_phy_workarounds_ich8lan(struct e1000_hw *hw)
2731 {
2732         s32 ret_val = E1000_SUCCESS;
2733
2734         DEBUGFUNC("e1000_lv_phy_workarounds_ich8lan");
2735
2736         if (hw->mac.type != e1000_pch2lan)
2737                 return E1000_SUCCESS;
2738
2739         /* Set MDIO slow mode before any other MDIO access */
2740         ret_val = e1000_set_mdio_slow_mode_hv(hw);
2741         if (ret_val)
2742                 return ret_val;
2743
2744         ret_val = hw->phy.ops.acquire(hw);
2745         if (ret_val)
2746                 return ret_val;
2747         /* set MSE higher to enable link to stay up when noise is high */
2748         ret_val = e1000_write_emi_reg_locked(hw, I82579_MSE_THRESHOLD, 0x0034);
2749         if (ret_val)
2750                 goto release;
2751         /* drop link after 5 times MSE threshold was reached */
2752         ret_val = e1000_write_emi_reg_locked(hw, I82579_MSE_LINK_DOWN, 0x0005);
2753 release:
2754         hw->phy.ops.release(hw);
2755
2756         return ret_val;
2757 }
2758
2759 /**
2760  *  e1000_k1_gig_workaround_lv - K1 Si workaround
2761  *  @hw:   pointer to the HW structure
2762  *
2763  *  Workaround to set the K1 beacon duration for 82579 parts in 10Mbps
2764  *  Disable K1 for 1000 and 100 speeds
2765  **/
2766 STATIC s32 e1000_k1_workaround_lv(struct e1000_hw *hw)
2767 {
2768         s32 ret_val = E1000_SUCCESS;
2769         u16 status_reg = 0;
2770
2771         DEBUGFUNC("e1000_k1_workaround_lv");
2772
2773         if (hw->mac.type != e1000_pch2lan)
2774                 return E1000_SUCCESS;
2775
2776         /* Set K1 beacon duration based on 10Mbs speed */
2777         ret_val = hw->phy.ops.read_reg(hw, HV_M_STATUS, &status_reg);
2778         if (ret_val)
2779                 return ret_val;
2780
2781         if ((status_reg & (HV_M_STATUS_LINK_UP | HV_M_STATUS_AUTONEG_COMPLETE))
2782             == (HV_M_STATUS_LINK_UP | HV_M_STATUS_AUTONEG_COMPLETE)) {
2783                 if (status_reg &
2784                     (HV_M_STATUS_SPEED_1000 | HV_M_STATUS_SPEED_100)) {
2785                         u16 pm_phy_reg;
2786
2787                         /* LV 1G/100 Packet drop issue wa  */
2788                         ret_val = hw->phy.ops.read_reg(hw, HV_PM_CTRL,
2789                                                        &pm_phy_reg);
2790                         if (ret_val)
2791                                 return ret_val;
2792                         pm_phy_reg &= ~HV_PM_CTRL_K1_ENABLE;
2793                         ret_val = hw->phy.ops.write_reg(hw, HV_PM_CTRL,
2794                                                         pm_phy_reg);
2795                         if (ret_val)
2796                                 return ret_val;
2797                 } else {
2798                         u32 mac_reg;
2799                         mac_reg = E1000_READ_REG(hw, E1000_FEXTNVM4);
2800                         mac_reg &= ~E1000_FEXTNVM4_BEACON_DURATION_MASK;
2801                         mac_reg |= E1000_FEXTNVM4_BEACON_DURATION_16USEC;
2802                         E1000_WRITE_REG(hw, E1000_FEXTNVM4, mac_reg);
2803                 }
2804         }
2805
2806         return ret_val;
2807 }
2808
2809 /**
2810  *  e1000_gate_hw_phy_config_ich8lan - disable PHY config via hardware
2811  *  @hw:   pointer to the HW structure
2812  *  @gate: boolean set to true to gate, false to ungate
2813  *
2814  *  Gate/ungate the automatic PHY configuration via hardware; perform
2815  *  the configuration via software instead.
2816  **/
2817 STATIC void e1000_gate_hw_phy_config_ich8lan(struct e1000_hw *hw, bool gate)
2818 {
2819         u32 extcnf_ctrl;
2820
2821         DEBUGFUNC("e1000_gate_hw_phy_config_ich8lan");
2822
2823         if (hw->mac.type < e1000_pch2lan)
2824                 return;
2825
2826         extcnf_ctrl = E1000_READ_REG(hw, E1000_EXTCNF_CTRL);
2827
2828         if (gate)
2829                 extcnf_ctrl |= E1000_EXTCNF_CTRL_GATE_PHY_CFG;
2830         else
2831                 extcnf_ctrl &= ~E1000_EXTCNF_CTRL_GATE_PHY_CFG;
2832
2833         E1000_WRITE_REG(hw, E1000_EXTCNF_CTRL, extcnf_ctrl);
2834 }
2835
2836 /**
2837  *  e1000_lan_init_done_ich8lan - Check for PHY config completion
2838  *  @hw: pointer to the HW structure
2839  *
2840  *  Check the appropriate indication the MAC has finished configuring the
2841  *  PHY after a software reset.
2842  **/
2843 STATIC void e1000_lan_init_done_ich8lan(struct e1000_hw *hw)
2844 {
2845         u32 data, loop = E1000_ICH8_LAN_INIT_TIMEOUT;
2846
2847         DEBUGFUNC("e1000_lan_init_done_ich8lan");
2848
2849         /* Wait for basic configuration completes before proceeding */
2850         do {
2851                 data = E1000_READ_REG(hw, E1000_STATUS);
2852                 data &= E1000_STATUS_LAN_INIT_DONE;
2853                 usec_delay(100);
2854         } while ((!data) && --loop);
2855
2856         /* If basic configuration is incomplete before the above loop
2857          * count reaches 0, loading the configuration from NVM will
2858          * leave the PHY in a bad state possibly resulting in no link.
2859          */
2860         if (loop == 0)
2861                 DEBUGOUT("LAN_INIT_DONE not set, increase timeout\n");
2862
2863         /* Clear the Init Done bit for the next init event */
2864         data = E1000_READ_REG(hw, E1000_STATUS);
2865         data &= ~E1000_STATUS_LAN_INIT_DONE;
2866         E1000_WRITE_REG(hw, E1000_STATUS, data);
2867 }
2868
2869 /**
2870  *  e1000_post_phy_reset_ich8lan - Perform steps required after a PHY reset
2871  *  @hw: pointer to the HW structure
2872  **/
2873 STATIC s32 e1000_post_phy_reset_ich8lan(struct e1000_hw *hw)
2874 {
2875         s32 ret_val = E1000_SUCCESS;
2876         u16 reg;
2877
2878         DEBUGFUNC("e1000_post_phy_reset_ich8lan");
2879
2880         if (hw->phy.ops.check_reset_block(hw))
2881                 return E1000_SUCCESS;
2882
2883         /* Allow time for h/w to get to quiescent state after reset */
2884         msec_delay(10);
2885
2886         /* Perform any necessary post-reset workarounds */
2887         switch (hw->mac.type) {
2888         case e1000_pchlan:
2889                 ret_val = e1000_hv_phy_workarounds_ich8lan(hw);
2890                 if (ret_val)
2891                         return ret_val;
2892                 break;
2893         case e1000_pch2lan:
2894                 ret_val = e1000_lv_phy_workarounds_ich8lan(hw);
2895                 if (ret_val)
2896                         return ret_val;
2897                 break;
2898         default:
2899                 break;
2900         }
2901
2902         /* Clear the host wakeup bit after lcd reset */
2903         if (hw->mac.type >= e1000_pchlan) {
2904                 hw->phy.ops.read_reg(hw, BM_PORT_GEN_CFG, &reg);
2905                 reg &= ~BM_WUC_HOST_WU_BIT;
2906                 hw->phy.ops.write_reg(hw, BM_PORT_GEN_CFG, reg);
2907         }
2908
2909         /* Configure the LCD with the extended configuration region in NVM */
2910         ret_val = e1000_sw_lcd_config_ich8lan(hw);
2911         if (ret_val)
2912                 return ret_val;
2913
2914         /* Configure the LCD with the OEM bits in NVM */
2915         ret_val = e1000_oem_bits_config_ich8lan(hw, true);
2916
2917         if (hw->mac.type == e1000_pch2lan) {
2918                 /* Ungate automatic PHY configuration on non-managed 82579 */
2919                 if (!(E1000_READ_REG(hw, E1000_FWSM) &
2920                     E1000_ICH_FWSM_FW_VALID)) {
2921                         msec_delay(10);
2922                         e1000_gate_hw_phy_config_ich8lan(hw, false);
2923                 }
2924
2925                 /* Set EEE LPI Update Timer to 200usec */
2926                 ret_val = hw->phy.ops.acquire(hw);
2927                 if (ret_val)
2928                         return ret_val;
2929                 ret_val = e1000_write_emi_reg_locked(hw,
2930                                                      I82579_LPI_UPDATE_TIMER,
2931                                                      0x1387);
2932                 hw->phy.ops.release(hw);
2933         }
2934
2935         return ret_val;
2936 }
2937
2938 /**
2939  *  e1000_phy_hw_reset_ich8lan - Performs a PHY reset
2940  *  @hw: pointer to the HW structure
2941  *
2942  *  Resets the PHY
2943  *  This is a function pointer entry point called by drivers
2944  *  or other shared routines.
2945  **/
2946 STATIC s32 e1000_phy_hw_reset_ich8lan(struct e1000_hw *hw)
2947 {
2948         s32 ret_val = E1000_SUCCESS;
2949
2950         DEBUGFUNC("e1000_phy_hw_reset_ich8lan");
2951
2952         /* Gate automatic PHY configuration by hardware on non-managed 82579 */
2953         if ((hw->mac.type == e1000_pch2lan) &&
2954             !(E1000_READ_REG(hw, E1000_FWSM) & E1000_ICH_FWSM_FW_VALID))
2955                 e1000_gate_hw_phy_config_ich8lan(hw, true);
2956
2957         ret_val = e1000_phy_hw_reset_generic(hw);
2958         if (ret_val)
2959                 return ret_val;
2960
2961         return e1000_post_phy_reset_ich8lan(hw);
2962 }
2963
2964 /**
2965  *  e1000_set_lplu_state_pchlan - Set Low Power Link Up state
2966  *  @hw: pointer to the HW structure
2967  *  @active: true to enable LPLU, false to disable
2968  *
2969  *  Sets the LPLU state according to the active flag.  For PCH, if OEM write
2970  *  bit are disabled in the NVM, writing the LPLU bits in the MAC will not set
2971  *  the phy speed. This function will manually set the LPLU bit and restart
2972  *  auto-neg as hw would do. D3 and D0 LPLU will call the same function
2973  *  since it configures the same bit.
2974  **/
2975 STATIC s32 e1000_set_lplu_state_pchlan(struct e1000_hw *hw, bool active)
2976 {
2977         s32 ret_val;
2978         u16 oem_reg;
2979
2980         DEBUGFUNC("e1000_set_lplu_state_pchlan");
2981         ret_val = hw->phy.ops.read_reg(hw, HV_OEM_BITS, &oem_reg);
2982         if (ret_val)
2983                 return ret_val;
2984
2985         if (active)
2986                 oem_reg |= HV_OEM_BITS_LPLU;
2987         else
2988                 oem_reg &= ~HV_OEM_BITS_LPLU;
2989
2990         if (!hw->phy.ops.check_reset_block(hw))
2991                 oem_reg |= HV_OEM_BITS_RESTART_AN;
2992
2993         return hw->phy.ops.write_reg(hw, HV_OEM_BITS, oem_reg);
2994 }
2995
2996 /**
2997  *  e1000_set_d0_lplu_state_ich8lan - Set Low Power Linkup D0 state
2998  *  @hw: pointer to the HW structure
2999  *  @active: true to enable LPLU, false to disable
3000  *
3001  *  Sets the LPLU D0 state according to the active flag.  When
3002  *  activating LPLU this function also disables smart speed
3003  *  and vice versa.  LPLU will not be activated unless the
3004  *  device autonegotiation advertisement meets standards of
3005  *  either 10 or 10/100 or 10/100/1000 at all duplexes.
3006  *  This is a function pointer entry point only called by
3007  *  PHY setup routines.
3008  **/
3009 STATIC s32 e1000_set_d0_lplu_state_ich8lan(struct e1000_hw *hw, bool active)
3010 {
3011         struct e1000_phy_info *phy = &hw->phy;
3012         u32 phy_ctrl;
3013         s32 ret_val = E1000_SUCCESS;
3014         u16 data;
3015
3016         DEBUGFUNC("e1000_set_d0_lplu_state_ich8lan");
3017
3018         if (phy->type == e1000_phy_ife)
3019                 return E1000_SUCCESS;
3020
3021         phy_ctrl = E1000_READ_REG(hw, E1000_PHY_CTRL);
3022
3023         if (active) {
3024                 phy_ctrl |= E1000_PHY_CTRL_D0A_LPLU;
3025                 E1000_WRITE_REG(hw, E1000_PHY_CTRL, phy_ctrl);
3026
3027                 if (phy->type != e1000_phy_igp_3)
3028                         return E1000_SUCCESS;
3029
3030                 /* Call gig speed drop workaround on LPLU before accessing
3031                  * any PHY registers
3032                  */
3033                 if (hw->mac.type == e1000_ich8lan)
3034                         e1000_gig_downshift_workaround_ich8lan(hw);
3035
3036                 /* When LPLU is enabled, we should disable SmartSpeed */
3037                 ret_val = phy->ops.read_reg(hw,
3038                                             IGP01E1000_PHY_PORT_CONFIG,
3039                                             &data);
3040                 if (ret_val)
3041                         return ret_val;
3042                 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
3043                 ret_val = phy->ops.write_reg(hw,
3044                                              IGP01E1000_PHY_PORT_CONFIG,
3045                                              data);
3046                 if (ret_val)
3047                         return ret_val;
3048         } else {
3049                 phy_ctrl &= ~E1000_PHY_CTRL_D0A_LPLU;
3050                 E1000_WRITE_REG(hw, E1000_PHY_CTRL, phy_ctrl);
3051
3052                 if (phy->type != e1000_phy_igp_3)
3053                         return E1000_SUCCESS;
3054
3055                 /* LPLU and SmartSpeed are mutually exclusive.  LPLU is used
3056                  * during Dx states where the power conservation is most
3057                  * important.  During driver activity we should enable
3058                  * SmartSpeed, so performance is maintained.
3059                  */
3060                 if (phy->smart_speed == e1000_smart_speed_on) {
3061                         ret_val = phy->ops.read_reg(hw,
3062                                                     IGP01E1000_PHY_PORT_CONFIG,
3063                                                     &data);
3064                         if (ret_val)
3065                                 return ret_val;
3066
3067                         data |= IGP01E1000_PSCFR_SMART_SPEED;
3068                         ret_val = phy->ops.write_reg(hw,
3069                                                      IGP01E1000_PHY_PORT_CONFIG,
3070                                                      data);
3071                         if (ret_val)
3072                                 return ret_val;
3073                 } else if (phy->smart_speed == e1000_smart_speed_off) {
3074                         ret_val = phy->ops.read_reg(hw,
3075                                                     IGP01E1000_PHY_PORT_CONFIG,
3076                                                     &data);
3077                         if (ret_val)
3078                                 return ret_val;
3079
3080                         data &= ~IGP01E1000_PSCFR_SMART_SPEED;
3081                         ret_val = phy->ops.write_reg(hw,
3082                                                      IGP01E1000_PHY_PORT_CONFIG,
3083                                                      data);
3084                         if (ret_val)
3085                                 return ret_val;
3086                 }
3087         }
3088
3089         return E1000_SUCCESS;
3090 }
3091
3092 /**
3093  *  e1000_set_d3_lplu_state_ich8lan - Set Low Power Linkup D3 state
3094  *  @hw: pointer to the HW structure
3095  *  @active: true to enable LPLU, false to disable
3096  *
3097  *  Sets the LPLU D3 state according to the active flag.  When
3098  *  activating LPLU this function also disables smart speed
3099  *  and vice versa.  LPLU will not be activated unless the
3100  *  device autonegotiation advertisement meets standards of
3101  *  either 10 or 10/100 or 10/100/1000 at all duplexes.
3102  *  This is a function pointer entry point only called by
3103  *  PHY setup routines.
3104  **/
3105 STATIC s32 e1000_set_d3_lplu_state_ich8lan(struct e1000_hw *hw, bool active)
3106 {
3107         struct e1000_phy_info *phy = &hw->phy;
3108         u32 phy_ctrl;
3109         s32 ret_val = E1000_SUCCESS;
3110         u16 data;
3111
3112         DEBUGFUNC("e1000_set_d3_lplu_state_ich8lan");
3113
3114         phy_ctrl = E1000_READ_REG(hw, E1000_PHY_CTRL);
3115
3116         if (!active) {
3117                 phy_ctrl &= ~E1000_PHY_CTRL_NOND0A_LPLU;
3118                 E1000_WRITE_REG(hw, E1000_PHY_CTRL, phy_ctrl);
3119
3120                 if (phy->type != e1000_phy_igp_3)
3121                         return E1000_SUCCESS;
3122
3123                 /* LPLU and SmartSpeed are mutually exclusive.  LPLU is used
3124                  * during Dx states where the power conservation is most
3125                  * important.  During driver activity we should enable
3126                  * SmartSpeed, so performance is maintained.
3127                  */
3128                 if (phy->smart_speed == e1000_smart_speed_on) {
3129                         ret_val = phy->ops.read_reg(hw,
3130                                                     IGP01E1000_PHY_PORT_CONFIG,
3131                                                     &data);
3132                         if (ret_val)
3133                                 return ret_val;
3134
3135                         data |= IGP01E1000_PSCFR_SMART_SPEED;
3136                         ret_val = phy->ops.write_reg(hw,
3137                                                      IGP01E1000_PHY_PORT_CONFIG,
3138                                                      data);
3139                         if (ret_val)
3140                                 return ret_val;
3141                 } else if (phy->smart_speed == e1000_smart_speed_off) {
3142                         ret_val = phy->ops.read_reg(hw,
3143                                                     IGP01E1000_PHY_PORT_CONFIG,
3144                                                     &data);
3145                         if (ret_val)
3146                                 return ret_val;
3147
3148                         data &= ~IGP01E1000_PSCFR_SMART_SPEED;
3149                         ret_val = phy->ops.write_reg(hw,
3150                                                      IGP01E1000_PHY_PORT_CONFIG,
3151                                                      data);
3152                         if (ret_val)
3153                                 return ret_val;
3154                 }
3155         } else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) ||
3156                    (phy->autoneg_advertised == E1000_ALL_NOT_GIG) ||
3157                    (phy->autoneg_advertised == E1000_ALL_10_SPEED)) {
3158                 phy_ctrl |= E1000_PHY_CTRL_NOND0A_LPLU;
3159                 E1000_WRITE_REG(hw, E1000_PHY_CTRL, phy_ctrl);
3160
3161                 if (phy->type != e1000_phy_igp_3)
3162                         return E1000_SUCCESS;
3163
3164                 /* Call gig speed drop workaround on LPLU before accessing
3165                  * any PHY registers
3166                  */
3167                 if (hw->mac.type == e1000_ich8lan)
3168                         e1000_gig_downshift_workaround_ich8lan(hw);
3169
3170                 /* When LPLU is enabled, we should disable SmartSpeed */
3171                 ret_val = phy->ops.read_reg(hw,
3172                                             IGP01E1000_PHY_PORT_CONFIG,
3173                                             &data);
3174                 if (ret_val)
3175                         return ret_val;
3176
3177                 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
3178                 ret_val = phy->ops.write_reg(hw,
3179                                              IGP01E1000_PHY_PORT_CONFIG,
3180                                              data);
3181         }
3182
3183         return ret_val;
3184 }
3185
3186 /**
3187  *  e1000_valid_nvm_bank_detect_ich8lan - finds out the valid bank 0 or 1
3188  *  @hw: pointer to the HW structure
3189  *  @bank:  pointer to the variable that returns the active bank
3190  *
3191  *  Reads signature byte from the NVM using the flash access registers.
3192  *  Word 0x13 bits 15:14 = 10b indicate a valid signature for that bank.
3193  **/
3194 STATIC s32 e1000_valid_nvm_bank_detect_ich8lan(struct e1000_hw *hw, u32 *bank)
3195 {
3196         u32 eecd;
3197         struct e1000_nvm_info *nvm = &hw->nvm;
3198         u32 bank1_offset = nvm->flash_bank_size * sizeof(u16);
3199         u32 act_offset = E1000_ICH_NVM_SIG_WORD * 2 + 1;
3200         u32 nvm_dword = 0;
3201         u8 sig_byte = 0;
3202         s32 ret_val;
3203
3204         DEBUGFUNC("e1000_valid_nvm_bank_detect_ich8lan");
3205
3206         switch (hw->mac.type) {
3207         case e1000_ich8lan:
3208         case e1000_ich9lan:
3209                 eecd = E1000_READ_REG(hw, E1000_EECD);
3210                 if ((eecd & E1000_EECD_SEC1VAL_VALID_MASK) ==
3211                     E1000_EECD_SEC1VAL_VALID_MASK) {
3212                         if (eecd & E1000_EECD_SEC1VAL)
3213                                 *bank = 1;
3214                         else
3215                                 *bank = 0;
3216
3217                         return E1000_SUCCESS;
3218                 }
3219                 DEBUGOUT("Unable to determine valid NVM bank via EEC - reading flash signature\n");
3220                 /* fall-thru */
3221         default:
3222                 /* set bank to 0 in case flash read fails */
3223                 *bank = 0;
3224
3225                 /* Check bank 0 */
3226                 ret_val = e1000_read_flash_byte_ich8lan(hw, act_offset,
3227                                                         &sig_byte);
3228                 if (ret_val)
3229                         return ret_val;
3230                 if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) ==
3231                     E1000_ICH_NVM_SIG_VALUE) {
3232                         *bank = 0;
3233                         return E1000_SUCCESS;
3234                 }
3235
3236                 /* Check bank 1 */
3237                 ret_val = e1000_read_flash_byte_ich8lan(hw, act_offset +
3238                                                         bank1_offset,
3239                                                         &sig_byte);
3240                 if (ret_val)
3241                         return ret_val;
3242                 if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) ==
3243                     E1000_ICH_NVM_SIG_VALUE) {
3244                         *bank = 1;
3245                         return E1000_SUCCESS;
3246                 }
3247
3248                 DEBUGOUT("ERROR: No valid NVM bank present\n");
3249                 return -E1000_ERR_NVM;
3250         }
3251 }
3252
3253 /**
3254  *  e1000_read_nvm_ich8lan - Read word(s) from the NVM
3255  *  @hw: pointer to the HW structure
3256  *  @offset: The offset (in bytes) of the word(s) to read.
3257  *  @words: Size of data to read in words
3258  *  @data: Pointer to the word(s) to read at offset.
3259  *
3260  *  Reads a word(s) from the NVM using the flash access registers.
3261  **/
3262 STATIC s32 e1000_read_nvm_ich8lan(struct e1000_hw *hw, u16 offset, u16 words,
3263                                   u16 *data)
3264 {
3265         struct e1000_nvm_info *nvm = &hw->nvm;
3266         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
3267         u32 act_offset;
3268         s32 ret_val = E1000_SUCCESS;
3269         u32 bank = 0;
3270         u16 i, word;
3271
3272         DEBUGFUNC("e1000_read_nvm_ich8lan");
3273
3274         if ((offset >= nvm->word_size) || (words > nvm->word_size - offset) ||
3275             (words == 0)) {
3276                 DEBUGOUT("nvm parameter(s) out of bounds\n");
3277                 ret_val = -E1000_ERR_NVM;
3278                 goto out;
3279         }
3280
3281         nvm->ops.acquire(hw);
3282
3283         ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, &bank);
3284         if (ret_val != E1000_SUCCESS) {
3285                 DEBUGOUT("Could not detect valid bank, assuming bank 0\n");
3286                 bank = 0;
3287         }
3288
3289         act_offset = (bank) ? nvm->flash_bank_size : 0;
3290         act_offset += offset;
3291
3292         ret_val = E1000_SUCCESS;
3293         for (i = 0; i < words; i++) {
3294                 if (dev_spec->shadow_ram[offset+i].modified) {
3295                         data[i] = dev_spec->shadow_ram[offset+i].value;
3296                 } else {
3297                         ret_val = e1000_read_flash_word_ich8lan(hw,
3298                                                                 act_offset + i,
3299                                                                 &word);
3300                         if (ret_val)
3301                                 break;
3302                         data[i] = word;
3303                 }
3304         }
3305
3306         nvm->ops.release(hw);
3307
3308 out:
3309         if (ret_val)
3310                 DEBUGOUT1("NVM read error: %d\n", ret_val);
3311
3312         return ret_val;
3313 }
3314
3315 /**
3316  *  e1000_flash_cycle_init_ich8lan - Initialize flash
3317  *  @hw: pointer to the HW structure
3318  *
3319  *  This function does initial flash setup so that a new read/write/erase cycle
3320  *  can be started.
3321  **/
3322 STATIC s32 e1000_flash_cycle_init_ich8lan(struct e1000_hw *hw)
3323 {
3324         union ich8_hws_flash_status hsfsts;
3325         s32 ret_val = -E1000_ERR_NVM;
3326
3327         DEBUGFUNC("e1000_flash_cycle_init_ich8lan");
3328
3329         hsfsts.regval = E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFSTS);
3330
3331         /* Check if the flash descriptor is valid */
3332         if (!hsfsts.hsf_status.fldesvalid) {
3333                 DEBUGOUT("Flash descriptor invalid.  SW Sequencing must be used.\n");
3334                 return -E1000_ERR_NVM;
3335         }
3336
3337         /* Clear FCERR and DAEL in hw status by writing 1 */
3338         hsfsts.hsf_status.flcerr = 1;
3339         hsfsts.hsf_status.dael = 1;
3340         E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFSTS, hsfsts.regval);
3341
3342         /* Either we should have a hardware SPI cycle in progress
3343          * bit to check against, in order to start a new cycle or
3344          * FDONE bit should be changed in the hardware so that it
3345          * is 1 after hardware reset, which can then be used as an
3346          * indication whether a cycle is in progress or has been
3347          * completed.
3348          */
3349
3350         if (!hsfsts.hsf_status.flcinprog) {
3351                 /* There is no cycle running at present,
3352                  * so we can start a cycle.
3353                  * Begin by setting Flash Cycle Done.
3354                  */
3355                 hsfsts.hsf_status.flcdone = 1;
3356                 E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFSTS, hsfsts.regval);
3357                 ret_val = E1000_SUCCESS;
3358         } else {
3359                 s32 i;
3360
3361                 /* Otherwise poll for sometime so the current
3362                  * cycle has a chance to end before giving up.
3363                  */
3364                 for (i = 0; i < ICH_FLASH_READ_COMMAND_TIMEOUT; i++) {
3365                         hsfsts.regval = E1000_READ_FLASH_REG16(hw,
3366                                                               ICH_FLASH_HSFSTS);
3367                         if (!hsfsts.hsf_status.flcinprog) {
3368                                 ret_val = E1000_SUCCESS;
3369                                 break;
3370                         }
3371                         usec_delay(1);
3372                 }
3373                 if (ret_val == E1000_SUCCESS) {
3374                         /* Successful in waiting for previous cycle to timeout,
3375                          * now set the Flash Cycle Done.
3376                          */
3377                         hsfsts.hsf_status.flcdone = 1;
3378                         E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFSTS,
3379                                                 hsfsts.regval);
3380                 } else {
3381                         DEBUGOUT("Flash controller busy, cannot get access\n");
3382                 }
3383         }
3384
3385         return ret_val;
3386 }
3387
3388 /**
3389  *  e1000_flash_cycle_ich8lan - Starts flash cycle (read/write/erase)
3390  *  @hw: pointer to the HW structure
3391  *  @timeout: maximum time to wait for completion
3392  *
3393  *  This function starts a flash cycle and waits for its completion.
3394  **/
3395 STATIC s32 e1000_flash_cycle_ich8lan(struct e1000_hw *hw, u32 timeout)
3396 {
3397         union ich8_hws_flash_ctrl hsflctl;
3398         union ich8_hws_flash_status hsfsts;
3399         u32 i = 0;
3400
3401         DEBUGFUNC("e1000_flash_cycle_ich8lan");
3402
3403         /* Start a cycle by writing 1 in Flash Cycle Go in Hw Flash Control */
3404         hsflctl.regval = E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFCTL);
3405         hsflctl.hsf_ctrl.flcgo = 1;
3406
3407         E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFCTL, hsflctl.regval);
3408
3409         /* wait till FDONE bit is set to 1 */
3410         do {
3411                 hsfsts.regval = E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFSTS);
3412                 if (hsfsts.hsf_status.flcdone)
3413                         break;
3414                 usec_delay(1);
3415         } while (i++ < timeout);
3416
3417         if (hsfsts.hsf_status.flcdone && !hsfsts.hsf_status.flcerr)
3418                 return E1000_SUCCESS;
3419
3420         return -E1000_ERR_NVM;
3421 }
3422
3423 /**
3424  *  e1000_read_flash_word_ich8lan - Read word from flash
3425  *  @hw: pointer to the HW structure
3426  *  @offset: offset to data location
3427  *  @data: pointer to the location for storing the data
3428  *
3429  *  Reads the flash word at offset into data.  Offset is converted
3430  *  to bytes before read.
3431  **/
3432 STATIC s32 e1000_read_flash_word_ich8lan(struct e1000_hw *hw, u32 offset,
3433                                          u16 *data)
3434 {
3435         DEBUGFUNC("e1000_read_flash_word_ich8lan");
3436
3437         if (!data)
3438                 return -E1000_ERR_NVM;
3439
3440         /* Must convert offset into bytes. */
3441         offset <<= 1;
3442
3443         return e1000_read_flash_data_ich8lan(hw, offset, 2, data);
3444 }
3445
3446 /**
3447  *  e1000_read_flash_byte_ich8lan - Read byte from flash
3448  *  @hw: pointer to the HW structure
3449  *  @offset: The offset of the byte to read.
3450  *  @data: Pointer to a byte to store the value read.
3451  *
3452  *  Reads a single byte from the NVM using the flash access registers.
3453  **/
3454 STATIC s32 e1000_read_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset,
3455                                          u8 *data)
3456 {
3457         s32 ret_val;
3458         u16 word = 0;
3459
3460         ret_val = e1000_read_flash_data_ich8lan(hw, offset, 1, &word);
3461
3462         if (ret_val)
3463                 return ret_val;
3464
3465         *data = (u8)word;
3466
3467         return E1000_SUCCESS;
3468 }
3469
3470 /**
3471  *  e1000_read_flash_data_ich8lan - Read byte or word from NVM
3472  *  @hw: pointer to the HW structure
3473  *  @offset: The offset (in bytes) of the byte or word to read.
3474  *  @size: Size of data to read, 1=byte 2=word
3475  *  @data: Pointer to the word to store the value read.
3476  *
3477  *  Reads a byte or word from the NVM using the flash access registers.
3478  **/
3479 STATIC s32 e1000_read_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
3480                                          u8 size, u16 *data)
3481 {
3482         union ich8_hws_flash_status hsfsts;
3483         union ich8_hws_flash_ctrl hsflctl;
3484         u32 flash_linear_addr;
3485         u32 flash_data = 0;
3486         s32 ret_val = -E1000_ERR_NVM;
3487         u8 count = 0;
3488
3489         DEBUGFUNC("e1000_read_flash_data_ich8lan");
3490
3491         if (size < 1 || size > 2 || offset > ICH_FLASH_LINEAR_ADDR_MASK)
3492                 return -E1000_ERR_NVM;
3493         flash_linear_addr = ((ICH_FLASH_LINEAR_ADDR_MASK & offset) +
3494                              hw->nvm.flash_base_addr);
3495
3496         do {
3497                 usec_delay(1);
3498                 /* Steps */
3499                 ret_val = e1000_flash_cycle_init_ich8lan(hw);
3500                 if (ret_val != E1000_SUCCESS)
3501                         break;
3502                 hsflctl.regval = E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFCTL);
3503
3504                 /* 0b/1b corresponds to 1 or 2 byte size, respectively. */
3505                 hsflctl.hsf_ctrl.fldbcount = size - 1;
3506                 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_READ;
3507                 E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFCTL, hsflctl.regval);
3508                 E1000_WRITE_FLASH_REG(hw, ICH_FLASH_FADDR, flash_linear_addr);
3509
3510                 ret_val = e1000_flash_cycle_ich8lan(hw,
3511                                                 ICH_FLASH_READ_COMMAND_TIMEOUT);
3512
3513                 /* Check if FCERR is set to 1, if set to 1, clear it
3514                  * and try the whole sequence a few more times, else
3515                  * read in (shift in) the Flash Data0, the order is
3516                  * least significant byte first msb to lsb
3517                  */
3518                 if (ret_val == E1000_SUCCESS) {
3519                         flash_data = E1000_READ_FLASH_REG(hw, ICH_FLASH_FDATA0);
3520                         if (size == 1)
3521                                 *data = (u8)(flash_data & 0x000000FF);
3522                         else if (size == 2)
3523                                 *data = (u16)(flash_data & 0x0000FFFF);
3524                         break;
3525                 } else {
3526                         /* If we've gotten here, then things are probably
3527                          * completely hosed, but if the error condition is
3528                          * detected, it won't hurt to give it another try...
3529                          * ICH_FLASH_CYCLE_REPEAT_COUNT times.
3530                          */
3531                         hsfsts.regval = E1000_READ_FLASH_REG16(hw,
3532                                                               ICH_FLASH_HSFSTS);
3533                         if (hsfsts.hsf_status.flcerr) {
3534                                 /* Repeat for some time before giving up. */
3535                                 continue;
3536                         } else if (!hsfsts.hsf_status.flcdone) {
3537                                 DEBUGOUT("Timeout error - flash cycle did not complete.\n");
3538                                 break;
3539                         }
3540                 }
3541         } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT);
3542
3543         return ret_val;
3544 }
3545
3546
3547 /**
3548  *  e1000_write_nvm_ich8lan - Write word(s) to the NVM
3549  *  @hw: pointer to the HW structure
3550  *  @offset: The offset (in bytes) of the word(s) to write.
3551  *  @words: Size of data to write in words
3552  *  @data: Pointer to the word(s) to write at offset.
3553  *
3554  *  Writes a byte or word to the NVM using the flash access registers.
3555  **/
3556 STATIC s32 e1000_write_nvm_ich8lan(struct e1000_hw *hw, u16 offset, u16 words,
3557                                    u16 *data)
3558 {
3559         struct e1000_nvm_info *nvm = &hw->nvm;
3560         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
3561         u16 i;
3562
3563         DEBUGFUNC("e1000_write_nvm_ich8lan");
3564
3565         if ((offset >= nvm->word_size) || (words > nvm->word_size - offset) ||
3566             (words == 0)) {
3567                 DEBUGOUT("nvm parameter(s) out of bounds\n");
3568                 return -E1000_ERR_NVM;
3569         }
3570
3571         nvm->ops.acquire(hw);
3572
3573         for (i = 0; i < words; i++) {
3574                 dev_spec->shadow_ram[offset+i].modified = true;
3575                 dev_spec->shadow_ram[offset+i].value = data[i];
3576         }
3577
3578         nvm->ops.release(hw);
3579
3580         return E1000_SUCCESS;
3581 }
3582
3583 /**
3584  *  e1000_update_nvm_checksum_ich8lan - Update the checksum for NVM
3585  *  @hw: pointer to the HW structure
3586  *
3587  *  The NVM checksum is updated by calling the generic update_nvm_checksum,
3588  *  which writes the checksum to the shadow ram.  The changes in the shadow
3589  *  ram are then committed to the EEPROM by processing each bank at a time
3590  *  checking for the modified bit and writing only the pending changes.
3591  *  After a successful commit, the shadow ram is cleared and is ready for
3592  *  future writes.
3593  **/
3594 STATIC s32 e1000_update_nvm_checksum_ich8lan(struct e1000_hw *hw)
3595 {
3596         struct e1000_nvm_info *nvm = &hw->nvm;
3597         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
3598         u32 i, act_offset, new_bank_offset, old_bank_offset, bank;
3599         s32 ret_val;
3600         u16 data = 0;
3601
3602         DEBUGFUNC("e1000_update_nvm_checksum_ich8lan");
3603
3604         ret_val = e1000_update_nvm_checksum_generic(hw);
3605         if (ret_val)
3606                 goto out;
3607
3608         if (nvm->type != e1000_nvm_flash_sw)
3609                 goto out;
3610
3611         nvm->ops.acquire(hw);
3612
3613         /* We're writing to the opposite bank so if we're on bank 1,
3614          * write to bank 0 etc.  We also need to erase the segment that
3615          * is going to be written
3616          */
3617         ret_val =  e1000_valid_nvm_bank_detect_ich8lan(hw, &bank);
3618         if (ret_val != E1000_SUCCESS) {
3619                 DEBUGOUT("Could not detect valid bank, assuming bank 0\n");
3620                 bank = 0;
3621         }
3622
3623         if (bank == 0) {
3624                 new_bank_offset = nvm->flash_bank_size;
3625                 old_bank_offset = 0;
3626                 ret_val = e1000_erase_flash_bank_ich8lan(hw, 1);
3627                 if (ret_val)
3628                         goto release;
3629         } else {
3630                 old_bank_offset = nvm->flash_bank_size;
3631                 new_bank_offset = 0;
3632                 ret_val = e1000_erase_flash_bank_ich8lan(hw, 0);
3633                 if (ret_val)
3634                         goto release;
3635         }
3636         for (i = 0; i < E1000_SHADOW_RAM_WORDS; i++) {
3637                 if (dev_spec->shadow_ram[i].modified) {
3638                         data = dev_spec->shadow_ram[i].value;
3639                 } else {
3640                         ret_val = e1000_read_flash_word_ich8lan(hw, i +
3641                                                                 old_bank_offset,
3642                                                                 &data);
3643                         if (ret_val)
3644                                 break;
3645                 }
3646                 /* If the word is 0x13, then make sure the signature bits
3647                  * (15:14) are 11b until the commit has completed.
3648                  * This will allow us to write 10b which indicates the
3649                  * signature is valid.  We want to do this after the write
3650                  * has completed so that we don't mark the segment valid
3651                  * while the write is still in progress
3652                  */
3653                 if (i == E1000_ICH_NVM_SIG_WORD)
3654                         data |= E1000_ICH_NVM_SIG_MASK;
3655
3656                 /* Convert offset to bytes. */
3657                 act_offset = (i + new_bank_offset) << 1;
3658
3659                 usec_delay(100);
3660
3661                 /* Write the bytes to the new bank. */
3662                 ret_val = e1000_retry_write_flash_byte_ich8lan(hw,
3663                                                                act_offset,
3664                                                                (u8)data);
3665                 if (ret_val)
3666                         break;
3667
3668                 usec_delay(100);
3669                 ret_val = e1000_retry_write_flash_byte_ich8lan(hw,
3670                                                           act_offset + 1,
3671                                                           (u8)(data >> 8));
3672                 if (ret_val)
3673                         break;
3674         }
3675
3676         /* Don't bother writing the segment valid bits if sector
3677          * programming failed.
3678          */
3679         if (ret_val) {
3680                 DEBUGOUT("Flash commit failed.\n");
3681                 goto release;
3682         }
3683
3684         /* Finally validate the new segment by setting bit 15:14
3685          * to 10b in word 0x13 , this can be done without an
3686          * erase as well since these bits are 11 to start with
3687          * and we need to change bit 14 to 0b
3688          */
3689         act_offset = new_bank_offset + E1000_ICH_NVM_SIG_WORD;
3690         ret_val = e1000_read_flash_word_ich8lan(hw, act_offset, &data);
3691         if (ret_val)
3692                 goto release;
3693
3694         data &= 0xBFFF;
3695         ret_val = e1000_retry_write_flash_byte_ich8lan(hw, act_offset * 2 + 1,
3696                                                        (u8)(data >> 8));
3697         if (ret_val)
3698                 goto release;
3699
3700         /* And invalidate the previously valid segment by setting
3701          * its signature word (0x13) high_byte to 0b. This can be
3702          * done without an erase because flash erase sets all bits
3703          * to 1's. We can write 1's to 0's without an erase
3704          */
3705         act_offset = (old_bank_offset + E1000_ICH_NVM_SIG_WORD) * 2 + 1;
3706
3707         ret_val = e1000_retry_write_flash_byte_ich8lan(hw, act_offset, 0);
3708
3709         if (ret_val)
3710                 goto release;
3711
3712         /* Great!  Everything worked, we can now clear the cached entries. */
3713         for (i = 0; i < E1000_SHADOW_RAM_WORDS; i++) {
3714                 dev_spec->shadow_ram[i].modified = false;
3715                 dev_spec->shadow_ram[i].value = 0xFFFF;
3716         }
3717
3718 release:
3719         nvm->ops.release(hw);
3720
3721         /* Reload the EEPROM, or else modifications will not appear
3722          * until after the next adapter reset.
3723          */
3724         if (!ret_val) {
3725                 nvm->ops.reload(hw);
3726                 msec_delay(10);
3727         }
3728
3729 out:
3730         if (ret_val)
3731                 DEBUGOUT1("NVM update error: %d\n", ret_val);
3732
3733         return ret_val;
3734 }
3735
3736 /**
3737  *  e1000_validate_nvm_checksum_ich8lan - Validate EEPROM checksum
3738  *  @hw: pointer to the HW structure
3739  *
3740  *  Check to see if checksum needs to be fixed by reading bit 6 in word 0x19.
3741  *  If the bit is 0, that the EEPROM had been modified, but the checksum was not
3742  *  calculated, in which case we need to calculate the checksum and set bit 6.
3743  **/
3744 STATIC s32 e1000_validate_nvm_checksum_ich8lan(struct e1000_hw *hw)
3745 {
3746         s32 ret_val;
3747         u16 data;
3748         u16 word;
3749         u16 valid_csum_mask;
3750
3751         DEBUGFUNC("e1000_validate_nvm_checksum_ich8lan");
3752
3753         /* Read NVM and check Invalid Image CSUM bit.  If this bit is 0,
3754          * the checksum needs to be fixed.  This bit is an indication that
3755          * the NVM was prepared by OEM software and did not calculate
3756          * the checksum...a likely scenario.
3757          */
3758         switch (hw->mac.type) {
3759         case e1000_pch_lpt:
3760                 word = NVM_COMPAT;
3761                 valid_csum_mask = NVM_COMPAT_VALID_CSUM;
3762                 break;
3763         default:
3764                 word = NVM_FUTURE_INIT_WORD1;
3765                 valid_csum_mask = NVM_FUTURE_INIT_WORD1_VALID_CSUM;
3766                 break;
3767         }
3768
3769         ret_val = hw->nvm.ops.read(hw, word, 1, &data);
3770         if (ret_val)
3771                 return ret_val;
3772
3773         if (!(data & valid_csum_mask)) {
3774                 data |= valid_csum_mask;
3775                 ret_val = hw->nvm.ops.write(hw, word, 1, &data);
3776                 if (ret_val)
3777                         return ret_val;
3778                 ret_val = hw->nvm.ops.update(hw);
3779                 if (ret_val)
3780                         return ret_val;
3781         }
3782
3783         return e1000_validate_nvm_checksum_generic(hw);
3784 }
3785
3786 /**
3787  *  e1000_write_flash_data_ich8lan - Writes bytes to the NVM
3788  *  @hw: pointer to the HW structure
3789  *  @offset: The offset (in bytes) of the byte/word to read.
3790  *  @size: Size of data to read, 1=byte 2=word
3791  *  @data: The byte(s) to write to the NVM.
3792  *
3793  *  Writes one/two bytes to the NVM using the flash access registers.
3794  **/
3795 STATIC s32 e1000_write_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
3796                                           u8 size, u16 data)
3797 {
3798         union ich8_hws_flash_status hsfsts;
3799         union ich8_hws_flash_ctrl hsflctl;
3800         u32 flash_linear_addr;
3801         u32 flash_data = 0;
3802         s32 ret_val;
3803         u8 count = 0;
3804
3805         DEBUGFUNC("e1000_write_ich8_data");
3806
3807         if (size < 1 || size > 2 || offset > ICH_FLASH_LINEAR_ADDR_MASK)
3808                 return -E1000_ERR_NVM;
3809
3810         flash_linear_addr = ((ICH_FLASH_LINEAR_ADDR_MASK & offset) +
3811                              hw->nvm.flash_base_addr);
3812
3813         do {
3814                 usec_delay(1);
3815                 /* Steps */
3816                 ret_val = e1000_flash_cycle_init_ich8lan(hw);
3817                 if (ret_val != E1000_SUCCESS)
3818                         break;
3819                 hsflctl.regval = E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFCTL);
3820
3821                 /* 0b/1b corresponds to 1 or 2 byte size, respectively. */
3822                 hsflctl.hsf_ctrl.fldbcount = size - 1;
3823                 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_WRITE;
3824                 E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFCTL, hsflctl.regval);
3825
3826                 E1000_WRITE_FLASH_REG(hw, ICH_FLASH_FADDR, flash_linear_addr);
3827
3828                 if (size == 1)
3829                         flash_data = (u32)data & 0x00FF;
3830                 else
3831                         flash_data = (u32)data;
3832
3833                 E1000_WRITE_FLASH_REG(hw, ICH_FLASH_FDATA0, flash_data);
3834
3835                 /* check if FCERR is set to 1 , if set to 1, clear it
3836                  * and try the whole sequence a few more times else done
3837                  */
3838                 ret_val =
3839                     e1000_flash_cycle_ich8lan(hw,
3840                                               ICH_FLASH_WRITE_COMMAND_TIMEOUT);
3841                 if (ret_val == E1000_SUCCESS)
3842                         break;
3843
3844                 /* If we're here, then things are most likely
3845                  * completely hosed, but if the error condition
3846                  * is detected, it won't hurt to give it another
3847                  * try...ICH_FLASH_CYCLE_REPEAT_COUNT times.
3848                  */
3849                 hsfsts.regval = E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFSTS);
3850                 if (hsfsts.hsf_status.flcerr)
3851                         /* Repeat for some time before giving up. */
3852                         continue;
3853                 if (!hsfsts.hsf_status.flcdone) {
3854                         DEBUGOUT("Timeout error - flash cycle did not complete.\n");
3855                         break;
3856                 }
3857         } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT);
3858
3859         return ret_val;
3860 }
3861
3862
3863 /**
3864  *  e1000_write_flash_byte_ich8lan - Write a single byte to NVM
3865  *  @hw: pointer to the HW structure
3866  *  @offset: The index of the byte to read.
3867  *  @data: The byte to write to the NVM.
3868  *
3869  *  Writes a single byte to the NVM using the flash access registers.
3870  **/
3871 STATIC s32 e1000_write_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset,
3872                                           u8 data)
3873 {
3874         u16 word = (u16)data;
3875
3876         DEBUGFUNC("e1000_write_flash_byte_ich8lan");
3877
3878         return e1000_write_flash_data_ich8lan(hw, offset, 1, word);
3879 }
3880
3881
3882
3883 /**
3884  *  e1000_retry_write_flash_byte_ich8lan - Writes a single byte to NVM
3885  *  @hw: pointer to the HW structure
3886  *  @offset: The offset of the byte to write.
3887  *  @byte: The byte to write to the NVM.
3888  *
3889  *  Writes a single byte to the NVM using the flash access registers.
3890  *  Goes through a retry algorithm before giving up.
3891  **/
3892 STATIC s32 e1000_retry_write_flash_byte_ich8lan(struct e1000_hw *hw,
3893                                                 u32 offset, u8 byte)
3894 {
3895         s32 ret_val;
3896         u16 program_retries;
3897
3898         DEBUGFUNC("e1000_retry_write_flash_byte_ich8lan");
3899
3900         ret_val = e1000_write_flash_byte_ich8lan(hw, offset, byte);
3901         if (!ret_val)
3902                 return ret_val;
3903
3904         for (program_retries = 0; program_retries < 100; program_retries++) {
3905                 DEBUGOUT2("Retrying Byte %2.2X at offset %u\n", byte, offset);
3906                 usec_delay(100);
3907                 ret_val = e1000_write_flash_byte_ich8lan(hw, offset, byte);
3908                 if (ret_val == E1000_SUCCESS)
3909                         break;
3910         }
3911         if (program_retries == 100)
3912                 return -E1000_ERR_NVM;
3913
3914         return E1000_SUCCESS;
3915 }
3916
3917 /**
3918  *  e1000_erase_flash_bank_ich8lan - Erase a bank (4k) from NVM
3919  *  @hw: pointer to the HW structure
3920  *  @bank: 0 for first bank, 1 for second bank, etc.
3921  *
3922  *  Erases the bank specified. Each bank is a 4k block. Banks are 0 based.
3923  *  bank N is 4096 * N + flash_reg_addr.
3924  **/
3925 STATIC s32 e1000_erase_flash_bank_ich8lan(struct e1000_hw *hw, u32 bank)
3926 {
3927         struct e1000_nvm_info *nvm = &hw->nvm;
3928         union ich8_hws_flash_status hsfsts;
3929         union ich8_hws_flash_ctrl hsflctl;
3930         u32 flash_linear_addr;
3931         /* bank size is in 16bit words - adjust to bytes */
3932         u32 flash_bank_size = nvm->flash_bank_size * 2;
3933         s32 ret_val;
3934         s32 count = 0;
3935         s32 j, iteration, sector_size;
3936
3937         DEBUGFUNC("e1000_erase_flash_bank_ich8lan");
3938
3939         hsfsts.regval = E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFSTS);
3940
3941         /* Determine HW Sector size: Read BERASE bits of hw flash status
3942          * register
3943          * 00: The Hw sector is 256 bytes, hence we need to erase 16
3944          *     consecutive sectors.  The start index for the nth Hw sector
3945          *     can be calculated as = bank * 4096 + n * 256
3946          * 01: The Hw sector is 4K bytes, hence we need to erase 1 sector.
3947          *     The start index for the nth Hw sector can be calculated
3948          *     as = bank * 4096
3949          * 10: The Hw sector is 8K bytes, nth sector = bank * 8192
3950          *     (ich9 only, otherwise error condition)
3951          * 11: The Hw sector is 64K bytes, nth sector = bank * 65536
3952          */
3953         switch (hsfsts.hsf_status.berasesz) {
3954         case 0:
3955                 /* Hw sector size 256 */
3956                 sector_size = ICH_FLASH_SEG_SIZE_256;
3957                 iteration = flash_bank_size / ICH_FLASH_SEG_SIZE_256;
3958                 break;
3959         case 1:
3960                 sector_size = ICH_FLASH_SEG_SIZE_4K;
3961                 iteration = 1;
3962                 break;
3963         case 2:
3964                 sector_size = ICH_FLASH_SEG_SIZE_8K;
3965                 iteration = 1;
3966                 break;
3967         case 3:
3968                 sector_size = ICH_FLASH_SEG_SIZE_64K;
3969                 iteration = 1;
3970                 break;
3971         default:
3972                 return -E1000_ERR_NVM;
3973         }
3974
3975         /* Start with the base address, then add the sector offset. */
3976         flash_linear_addr = hw->nvm.flash_base_addr;
3977         flash_linear_addr += (bank) ? flash_bank_size : 0;
3978
3979         for (j = 0; j < iteration; j++) {
3980                 do {
3981                         u32 timeout = ICH_FLASH_ERASE_COMMAND_TIMEOUT;
3982
3983                         /* Steps */
3984                         ret_val = e1000_flash_cycle_init_ich8lan(hw);
3985                         if (ret_val)
3986                                 return ret_val;
3987
3988                         /* Write a value 11 (block Erase) in Flash
3989                          * Cycle field in hw flash control
3990                          */
3991                         hsflctl.regval =
3992                             E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFCTL);
3993
3994                         hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_ERASE;
3995                         E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFCTL,
3996                                                 hsflctl.regval);
3997
3998                         /* Write the last 24 bits of an index within the
3999                          * block into Flash Linear address field in Flash
4000                          * Address.
4001                          */
4002                         flash_linear_addr += (j * sector_size);
4003                         E1000_WRITE_FLASH_REG(hw, ICH_FLASH_FADDR,
4004                                               flash_linear_addr);
4005
4006                         ret_val = e1000_flash_cycle_ich8lan(hw, timeout);
4007                         if (ret_val == E1000_SUCCESS)
4008                                 break;
4009
4010                         /* Check if FCERR is set to 1.  If 1,
4011                          * clear it and try the whole sequence
4012                          * a few more times else Done
4013                          */
4014                         hsfsts.regval = E1000_READ_FLASH_REG16(hw,
4015                                                       ICH_FLASH_HSFSTS);
4016                         if (hsfsts.hsf_status.flcerr)
4017                                 /* repeat for some time before giving up */
4018                                 continue;
4019                         else if (!hsfsts.hsf_status.flcdone)
4020                                 return ret_val;
4021                 } while (++count < ICH_FLASH_CYCLE_REPEAT_COUNT);
4022         }
4023
4024         return E1000_SUCCESS;
4025 }
4026
4027 /**
4028  *  e1000_valid_led_default_ich8lan - Set the default LED settings
4029  *  @hw: pointer to the HW structure
4030  *  @data: Pointer to the LED settings
4031  *
4032  *  Reads the LED default settings from the NVM to data.  If the NVM LED
4033  *  settings is all 0's or F's, set the LED default to a valid LED default
4034  *  setting.
4035  **/
4036 STATIC s32 e1000_valid_led_default_ich8lan(struct e1000_hw *hw, u16 *data)
4037 {
4038         s32 ret_val;
4039
4040         DEBUGFUNC("e1000_valid_led_default_ich8lan");
4041
4042         ret_val = hw->nvm.ops.read(hw, NVM_ID_LED_SETTINGS, 1, data);
4043         if (ret_val) {
4044                 DEBUGOUT("NVM Read Error\n");
4045                 return ret_val;
4046         }
4047
4048         if (*data == ID_LED_RESERVED_0000 || *data == ID_LED_RESERVED_FFFF)
4049                 *data = ID_LED_DEFAULT_ICH8LAN;
4050
4051         return E1000_SUCCESS;
4052 }
4053
4054 /**
4055  *  e1000_id_led_init_pchlan - store LED configurations
4056  *  @hw: pointer to the HW structure
4057  *
4058  *  PCH does not control LEDs via the LEDCTL register, rather it uses
4059  *  the PHY LED configuration register.
4060  *
4061  *  PCH also does not have an "always on" or "always off" mode which
4062  *  complicates the ID feature.  Instead of using the "on" mode to indicate
4063  *  in ledctl_mode2 the LEDs to use for ID (see e1000_id_led_init_generic()),
4064  *  use "link_up" mode.  The LEDs will still ID on request if there is no
4065  *  link based on logic in e1000_led_[on|off]_pchlan().
4066  **/
4067 STATIC s32 e1000_id_led_init_pchlan(struct e1000_hw *hw)
4068 {
4069         struct e1000_mac_info *mac = &hw->mac;
4070         s32 ret_val;
4071         const u32 ledctl_on = E1000_LEDCTL_MODE_LINK_UP;
4072         const u32 ledctl_off = E1000_LEDCTL_MODE_LINK_UP | E1000_PHY_LED0_IVRT;
4073         u16 data, i, temp, shift;
4074
4075         DEBUGFUNC("e1000_id_led_init_pchlan");
4076
4077         /* Get default ID LED modes */
4078         ret_val = hw->nvm.ops.valid_led_default(hw, &data);
4079         if (ret_val)
4080                 return ret_val;
4081
4082         mac->ledctl_default = E1000_READ_REG(hw, E1000_LEDCTL);
4083         mac->ledctl_mode1 = mac->ledctl_default;
4084         mac->ledctl_mode2 = mac->ledctl_default;
4085
4086         for (i = 0; i < 4; i++) {
4087                 temp = (data >> (i << 2)) & E1000_LEDCTL_LED0_MODE_MASK;
4088                 shift = (i * 5);
4089                 switch (temp) {
4090                 case ID_LED_ON1_DEF2:
4091                 case ID_LED_ON1_ON2:
4092                 case ID_LED_ON1_OFF2:
4093                         mac->ledctl_mode1 &= ~(E1000_PHY_LED0_MASK << shift);
4094                         mac->ledctl_mode1 |= (ledctl_on << shift);
4095                         break;
4096                 case ID_LED_OFF1_DEF2:
4097                 case ID_LED_OFF1_ON2:
4098                 case ID_LED_OFF1_OFF2:
4099                         mac->ledctl_mode1 &= ~(E1000_PHY_LED0_MASK << shift);
4100                         mac->ledctl_mode1 |= (ledctl_off << shift);
4101                         break;
4102                 default:
4103                         /* Do nothing */
4104                         break;
4105                 }
4106                 switch (temp) {
4107                 case ID_LED_DEF1_ON2:
4108                 case ID_LED_ON1_ON2:
4109                 case ID_LED_OFF1_ON2:
4110                         mac->ledctl_mode2 &= ~(E1000_PHY_LED0_MASK << shift);
4111                         mac->ledctl_mode2 |= (ledctl_on << shift);
4112                         break;
4113                 case ID_LED_DEF1_OFF2:
4114                 case ID_LED_ON1_OFF2:
4115                 case ID_LED_OFF1_OFF2:
4116                         mac->ledctl_mode2 &= ~(E1000_PHY_LED0_MASK << shift);
4117                         mac->ledctl_mode2 |= (ledctl_off << shift);
4118                         break;
4119                 default:
4120                         /* Do nothing */
4121                         break;
4122                 }
4123         }
4124
4125         return E1000_SUCCESS;
4126 }
4127
4128 /**
4129  *  e1000_get_bus_info_ich8lan - Get/Set the bus type and width
4130  *  @hw: pointer to the HW structure
4131  *
4132  *  ICH8 use the PCI Express bus, but does not contain a PCI Express Capability
4133  *  register, so the the bus width is hard coded.
4134  **/
4135 STATIC s32 e1000_get_bus_info_ich8lan(struct e1000_hw *hw)
4136 {
4137         struct e1000_bus_info *bus = &hw->bus;
4138         s32 ret_val;
4139
4140         DEBUGFUNC("e1000_get_bus_info_ich8lan");
4141
4142         ret_val = e1000_get_bus_info_pcie_generic(hw);
4143
4144         /* ICH devices are "PCI Express"-ish.  They have
4145          * a configuration space, but do not contain
4146          * PCI Express Capability registers, so bus width
4147          * must be hardcoded.
4148          */
4149         if (bus->width == e1000_bus_width_unknown)
4150                 bus->width = e1000_bus_width_pcie_x1;
4151
4152         return ret_val;
4153 }
4154
4155 /**
4156  *  e1000_reset_hw_ich8lan - Reset the hardware
4157  *  @hw: pointer to the HW structure
4158  *
4159  *  Does a full reset of the hardware which includes a reset of the PHY and
4160  *  MAC.
4161  **/
4162 STATIC s32 e1000_reset_hw_ich8lan(struct e1000_hw *hw)
4163 {
4164         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
4165         u16 kum_cfg;
4166         u32 ctrl, reg;
4167         s32 ret_val;
4168
4169         DEBUGFUNC("e1000_reset_hw_ich8lan");
4170
4171         /* Prevent the PCI-E bus from sticking if there is no TLP connection
4172          * on the last TLP read/write transaction when MAC is reset.
4173          */
4174         ret_val = e1000_disable_pcie_master_generic(hw);
4175         if (ret_val)
4176                 DEBUGOUT("PCI-E Master disable polling has failed.\n");
4177
4178         DEBUGOUT("Masking off all interrupts\n");
4179         E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff);
4180
4181         /* Disable the Transmit and Receive units.  Then delay to allow
4182          * any pending transactions to complete before we hit the MAC
4183          * with the global reset.
4184          */
4185         E1000_WRITE_REG(hw, E1000_RCTL, 0);
4186         E1000_WRITE_REG(hw, E1000_TCTL, E1000_TCTL_PSP);
4187         E1000_WRITE_FLUSH(hw);
4188
4189         msec_delay(10);
4190
4191         /* Workaround for ICH8 bit corruption issue in FIFO memory */
4192         if (hw->mac.type == e1000_ich8lan) {
4193                 /* Set Tx and Rx buffer allocation to 8k apiece. */
4194                 E1000_WRITE_REG(hw, E1000_PBA, E1000_PBA_8K);
4195                 /* Set Packet Buffer Size to 16k. */
4196                 E1000_WRITE_REG(hw, E1000_PBS, E1000_PBS_16K);
4197         }
4198
4199         if (hw->mac.type == e1000_pchlan) {
4200                 /* Save the NVM K1 bit setting*/
4201                 ret_val = e1000_read_nvm(hw, E1000_NVM_K1_CONFIG, 1, &kum_cfg);
4202                 if (ret_val)
4203                         return ret_val;
4204
4205                 if (kum_cfg & E1000_NVM_K1_ENABLE)
4206                         dev_spec->nvm_k1_enabled = true;
4207                 else
4208                         dev_spec->nvm_k1_enabled = false;
4209         }
4210
4211         ctrl = E1000_READ_REG(hw, E1000_CTRL);
4212
4213         if (!hw->phy.ops.check_reset_block(hw)) {
4214                 /* Full-chip reset requires MAC and PHY reset at the same
4215                  * time to make sure the interface between MAC and the
4216                  * external PHY is reset.
4217                  */
4218                 ctrl |= E1000_CTRL_PHY_RST;
4219
4220                 /* Gate automatic PHY configuration by hardware on
4221                  * non-managed 82579
4222                  */
4223                 if ((hw->mac.type == e1000_pch2lan) &&
4224                     !(E1000_READ_REG(hw, E1000_FWSM) & E1000_ICH_FWSM_FW_VALID))
4225                         e1000_gate_hw_phy_config_ich8lan(hw, true);
4226         }
4227         ret_val = e1000_acquire_swflag_ich8lan(hw);
4228         DEBUGOUT("Issuing a global reset to ich8lan\n");
4229         E1000_WRITE_REG(hw, E1000_CTRL, (ctrl | E1000_CTRL_RST));
4230         /* cannot issue a flush here because it hangs the hardware */
4231         msec_delay(20);
4232
4233         /* Set Phy Config Counter to 50msec */
4234         if (hw->mac.type == e1000_pch2lan) {
4235                 reg = E1000_READ_REG(hw, E1000_FEXTNVM3);
4236                 reg &= ~E1000_FEXTNVM3_PHY_CFG_COUNTER_MASK;
4237                 reg |= E1000_FEXTNVM3_PHY_CFG_COUNTER_50MSEC;
4238                 E1000_WRITE_REG(hw, E1000_FEXTNVM3, reg);
4239         }
4240
4241         if (!ret_val)
4242                 E1000_MUTEX_UNLOCK(&hw->dev_spec.ich8lan.swflag_mutex);
4243
4244         if (ctrl & E1000_CTRL_PHY_RST) {
4245                 ret_val = hw->phy.ops.get_cfg_done(hw);
4246                 if (ret_val)
4247                         return ret_val;
4248
4249                 ret_val = e1000_post_phy_reset_ich8lan(hw);
4250                 if (ret_val)
4251                         return ret_val;
4252         }
4253
4254         /* For PCH, this write will make sure that any noise
4255          * will be detected as a CRC error and be dropped rather than show up
4256          * as a bad packet to the DMA engine.
4257          */
4258         if (hw->mac.type == e1000_pchlan)
4259                 E1000_WRITE_REG(hw, E1000_CRC_OFFSET, 0x65656565);
4260
4261         E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff);
4262         E1000_READ_REG(hw, E1000_ICR);
4263
4264         reg = E1000_READ_REG(hw, E1000_KABGTXD);
4265         reg |= E1000_KABGTXD_BGSQLBIAS;
4266         E1000_WRITE_REG(hw, E1000_KABGTXD, reg);
4267
4268         return E1000_SUCCESS;
4269 }
4270
4271 /**
4272  *  e1000_init_hw_ich8lan - Initialize the hardware
4273  *  @hw: pointer to the HW structure
4274  *
4275  *  Prepares the hardware for transmit and receive by doing the following:
4276  *   - initialize hardware bits
4277  *   - initialize LED identification
4278  *   - setup receive address registers
4279  *   - setup flow control
4280  *   - setup transmit descriptors
4281  *   - clear statistics
4282  **/
4283 STATIC s32 e1000_init_hw_ich8lan(struct e1000_hw *hw)
4284 {
4285         struct e1000_mac_info *mac = &hw->mac;
4286         u32 ctrl_ext, txdctl, snoop;
4287         s32 ret_val;
4288         u16 i;
4289
4290         DEBUGFUNC("e1000_init_hw_ich8lan");
4291
4292         e1000_initialize_hw_bits_ich8lan(hw);
4293
4294         /* Initialize identification LED */
4295         ret_val = mac->ops.id_led_init(hw);
4296         /* An error is not fatal and we should not stop init due to this */
4297         if (ret_val)
4298                 DEBUGOUT("Error initializing identification LED\n");
4299
4300         /* Setup the receive address. */
4301         e1000_init_rx_addrs_generic(hw, mac->rar_entry_count);
4302
4303         /* Zero out the Multicast HASH table */
4304         DEBUGOUT("Zeroing the MTA\n");
4305         for (i = 0; i < mac->mta_reg_count; i++)
4306                 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0);
4307
4308         /* The 82578 Rx buffer will stall if wakeup is enabled in host and
4309          * the ME.  Disable wakeup by clearing the host wakeup bit.
4310          * Reset the phy after disabling host wakeup to reset the Rx buffer.
4311          */
4312         if (hw->phy.type == e1000_phy_82578) {
4313                 hw->phy.ops.read_reg(hw, BM_PORT_GEN_CFG, &i);
4314                 i &= ~BM_WUC_HOST_WU_BIT;
4315                 hw->phy.ops.write_reg(hw, BM_PORT_GEN_CFG, i);
4316                 ret_val = e1000_phy_hw_reset_ich8lan(hw);
4317                 if (ret_val)
4318                         return ret_val;
4319         }
4320
4321         /* Setup link and flow control */
4322         ret_val = mac->ops.setup_link(hw);
4323
4324         /* Set the transmit descriptor write-back policy for both queues */
4325         txdctl = E1000_READ_REG(hw, E1000_TXDCTL(0));
4326         txdctl = ((txdctl & ~E1000_TXDCTL_WTHRESH) |
4327                   E1000_TXDCTL_FULL_TX_DESC_WB);
4328         txdctl = ((txdctl & ~E1000_TXDCTL_PTHRESH) |
4329                   E1000_TXDCTL_MAX_TX_DESC_PREFETCH);
4330         E1000_WRITE_REG(hw, E1000_TXDCTL(0), txdctl);
4331         txdctl = E1000_READ_REG(hw, E1000_TXDCTL(1));
4332         txdctl = ((txdctl & ~E1000_TXDCTL_WTHRESH) |
4333                   E1000_TXDCTL_FULL_TX_DESC_WB);
4334         txdctl = ((txdctl & ~E1000_TXDCTL_PTHRESH) |
4335                   E1000_TXDCTL_MAX_TX_DESC_PREFETCH);
4336         E1000_WRITE_REG(hw, E1000_TXDCTL(1), txdctl);
4337
4338         /* ICH8 has opposite polarity of no_snoop bits.
4339          * By default, we should use snoop behavior.
4340          */
4341         if (mac->type == e1000_ich8lan)
4342                 snoop = PCIE_ICH8_SNOOP_ALL;
4343         else
4344                 snoop = (u32) ~(PCIE_NO_SNOOP_ALL);
4345         e1000_set_pcie_no_snoop_generic(hw, snoop);
4346
4347         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
4348         ctrl_ext |= E1000_CTRL_EXT_RO_DIS;
4349         E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
4350
4351         /* Clear all of the statistics registers (clear on read).  It is
4352          * important that we do this after we have tried to establish link
4353          * because the symbol error count will increment wildly if there
4354          * is no link.
4355          */
4356         e1000_clear_hw_cntrs_ich8lan(hw);
4357
4358         return ret_val;
4359 }
4360
4361 /**
4362  *  e1000_initialize_hw_bits_ich8lan - Initialize required hardware bits
4363  *  @hw: pointer to the HW structure
4364  *
4365  *  Sets/Clears required hardware bits necessary for correctly setting up the
4366  *  hardware for transmit and receive.
4367  **/
4368 STATIC void e1000_initialize_hw_bits_ich8lan(struct e1000_hw *hw)
4369 {
4370         u32 reg;
4371
4372         DEBUGFUNC("e1000_initialize_hw_bits_ich8lan");
4373
4374         /* Extended Device Control */
4375         reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
4376         reg |= (1 << 22);
4377         /* Enable PHY low-power state when MAC is at D3 w/o WoL */
4378         if (hw->mac.type >= e1000_pchlan)
4379                 reg |= E1000_CTRL_EXT_PHYPDEN;
4380         E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg);
4381
4382         /* Transmit Descriptor Control 0 */
4383         reg = E1000_READ_REG(hw, E1000_TXDCTL(0));
4384         reg |= (1 << 22);
4385         E1000_WRITE_REG(hw, E1000_TXDCTL(0), reg);
4386
4387         /* Transmit Descriptor Control 1 */
4388         reg = E1000_READ_REG(hw, E1000_TXDCTL(1));
4389         reg |= (1 << 22);
4390         E1000_WRITE_REG(hw, E1000_TXDCTL(1), reg);
4391
4392         /* Transmit Arbitration Control 0 */
4393         reg = E1000_READ_REG(hw, E1000_TARC(0));
4394         if (hw->mac.type == e1000_ich8lan)
4395                 reg |= (1 << 28) | (1 << 29);
4396         reg |= (1 << 23) | (1 << 24) | (1 << 26) | (1 << 27);
4397         E1000_WRITE_REG(hw, E1000_TARC(0), reg);
4398
4399         /* Transmit Arbitration Control 1 */
4400         reg = E1000_READ_REG(hw, E1000_TARC(1));
4401         if (E1000_READ_REG(hw, E1000_TCTL) & E1000_TCTL_MULR)
4402                 reg &= ~(1 << 28);
4403         else
4404                 reg |= (1 << 28);
4405         reg |= (1 << 24) | (1 << 26) | (1 << 30);
4406         E1000_WRITE_REG(hw, E1000_TARC(1), reg);
4407
4408         /* Device Status */
4409         if (hw->mac.type == e1000_ich8lan) {
4410                 reg = E1000_READ_REG(hw, E1000_STATUS);
4411                 reg &= ~(1 << 31);
4412                 E1000_WRITE_REG(hw, E1000_STATUS, reg);
4413         }
4414
4415         /* work-around descriptor data corruption issue during nfs v2 udp
4416          * traffic, just disable the nfs filtering capability
4417          */
4418         reg = E1000_READ_REG(hw, E1000_RFCTL);
4419         reg |= (E1000_RFCTL_NFSW_DIS | E1000_RFCTL_NFSR_DIS);
4420
4421         /* Disable IPv6 extension header parsing because some malformed
4422          * IPv6 headers can hang the Rx.
4423          */
4424         if (hw->mac.type == e1000_ich8lan)
4425                 reg |= (E1000_RFCTL_IPV6_EX_DIS | E1000_RFCTL_NEW_IPV6_EXT_DIS);
4426         E1000_WRITE_REG(hw, E1000_RFCTL, reg);
4427
4428         /* Enable ECC on Lynxpoint */
4429         if (hw->mac.type == e1000_pch_lpt) {
4430                 reg = E1000_READ_REG(hw, E1000_PBECCSTS);
4431                 reg |= E1000_PBECCSTS_ECC_ENABLE;
4432                 E1000_WRITE_REG(hw, E1000_PBECCSTS, reg);
4433
4434                 reg = E1000_READ_REG(hw, E1000_CTRL);
4435                 reg |= E1000_CTRL_MEHE;
4436                 E1000_WRITE_REG(hw, E1000_CTRL, reg);
4437         }
4438
4439         return;
4440 }
4441
4442 /**
4443  *  e1000_setup_link_ich8lan - Setup flow control and link settings
4444  *  @hw: pointer to the HW structure
4445  *
4446  *  Determines which flow control settings to use, then configures flow
4447  *  control.  Calls the appropriate media-specific link configuration
4448  *  function.  Assuming the adapter has a valid link partner, a valid link
4449  *  should be established.  Assumes the hardware has previously been reset
4450  *  and the transmitter and receiver are not enabled.
4451  **/
4452 STATIC s32 e1000_setup_link_ich8lan(struct e1000_hw *hw)
4453 {
4454         s32 ret_val;
4455
4456         DEBUGFUNC("e1000_setup_link_ich8lan");
4457
4458         if (hw->phy.ops.check_reset_block(hw))
4459                 return E1000_SUCCESS;
4460
4461         /* ICH parts do not have a word in the NVM to determine
4462          * the default flow control setting, so we explicitly
4463          * set it to full.
4464          */
4465         if (hw->fc.requested_mode == e1000_fc_default)
4466                 hw->fc.requested_mode = e1000_fc_full;
4467
4468         /* Save off the requested flow control mode for use later.  Depending
4469          * on the link partner's capabilities, we may or may not use this mode.
4470          */
4471         hw->fc.current_mode = hw->fc.requested_mode;
4472
4473         DEBUGOUT1("After fix-ups FlowControl is now = %x\n",
4474                 hw->fc.current_mode);
4475
4476         /* Continue to configure the copper link. */
4477         ret_val = hw->mac.ops.setup_physical_interface(hw);
4478         if (ret_val)
4479                 return ret_val;
4480
4481         E1000_WRITE_REG(hw, E1000_FCTTV, hw->fc.pause_time);
4482         if ((hw->phy.type == e1000_phy_82578) ||
4483             (hw->phy.type == e1000_phy_82579) ||
4484             (hw->phy.type == e1000_phy_i217) ||
4485             (hw->phy.type == e1000_phy_82577)) {
4486                 E1000_WRITE_REG(hw, E1000_FCRTV_PCH, hw->fc.refresh_time);
4487
4488                 ret_val = hw->phy.ops.write_reg(hw,
4489                                              PHY_REG(BM_PORT_CTRL_PAGE, 27),
4490                                              hw->fc.pause_time);
4491                 if (ret_val)
4492                         return ret_val;
4493         }
4494
4495         return e1000_set_fc_watermarks_generic(hw);
4496 }
4497
4498 /**
4499  *  e1000_setup_copper_link_ich8lan - Configure MAC/PHY interface
4500  *  @hw: pointer to the HW structure
4501  *
4502  *  Configures the kumeran interface to the PHY to wait the appropriate time
4503  *  when polling the PHY, then call the generic setup_copper_link to finish
4504  *  configuring the copper link.
4505  **/
4506 STATIC s32 e1000_setup_copper_link_ich8lan(struct e1000_hw *hw)
4507 {
4508         u32 ctrl;
4509         s32 ret_val;
4510         u16 reg_data;
4511
4512         DEBUGFUNC("e1000_setup_copper_link_ich8lan");
4513
4514         ctrl = E1000_READ_REG(hw, E1000_CTRL);
4515         ctrl |= E1000_CTRL_SLU;
4516         ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
4517         E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
4518
4519         /* Set the mac to wait the maximum time between each iteration
4520          * and increase the max iterations when polling the phy;
4521          * this fixes erroneous timeouts at 10Mbps.
4522          */
4523         ret_val = e1000_write_kmrn_reg_generic(hw, E1000_KMRNCTRLSTA_TIMEOUTS,
4524                                                0xFFFF);
4525         if (ret_val)
4526                 return ret_val;
4527         ret_val = e1000_read_kmrn_reg_generic(hw,
4528                                               E1000_KMRNCTRLSTA_INBAND_PARAM,
4529                                               &reg_data);
4530         if (ret_val)
4531                 return ret_val;
4532         reg_data |= 0x3F;
4533         ret_val = e1000_write_kmrn_reg_generic(hw,
4534                                                E1000_KMRNCTRLSTA_INBAND_PARAM,
4535                                                reg_data);
4536         if (ret_val)
4537                 return ret_val;
4538
4539         switch (hw->phy.type) {
4540         case e1000_phy_igp_3:
4541                 ret_val = e1000_copper_link_setup_igp(hw);
4542                 if (ret_val)
4543                         return ret_val;
4544                 break;
4545         case e1000_phy_bm:
4546         case e1000_phy_82578:
4547                 ret_val = e1000_copper_link_setup_m88(hw);
4548                 if (ret_val)
4549                         return ret_val;
4550                 break;
4551         case e1000_phy_82577:
4552         case e1000_phy_82579:
4553                 ret_val = e1000_copper_link_setup_82577(hw);
4554                 if (ret_val)
4555                         return ret_val;
4556                 break;
4557         case e1000_phy_ife:
4558                 ret_val = hw->phy.ops.read_reg(hw, IFE_PHY_MDIX_CONTROL,
4559                                                &reg_data);
4560                 if (ret_val)
4561                         return ret_val;
4562
4563                 reg_data &= ~IFE_PMC_AUTO_MDIX;
4564
4565                 switch (hw->phy.mdix) {
4566                 case 1:
4567                         reg_data &= ~IFE_PMC_FORCE_MDIX;
4568                         break;
4569                 case 2:
4570                         reg_data |= IFE_PMC_FORCE_MDIX;
4571                         break;
4572                 case 0:
4573                 default:
4574                         reg_data |= IFE_PMC_AUTO_MDIX;
4575                         break;
4576                 }
4577                 ret_val = hw->phy.ops.write_reg(hw, IFE_PHY_MDIX_CONTROL,
4578                                                 reg_data);
4579                 if (ret_val)
4580                         return ret_val;
4581                 break;
4582         default:
4583                 break;
4584         }
4585
4586         return e1000_setup_copper_link_generic(hw);
4587 }
4588
4589 /**
4590  *  e1000_setup_copper_link_pch_lpt - Configure MAC/PHY interface
4591  *  @hw: pointer to the HW structure
4592  *
4593  *  Calls the PHY specific link setup function and then calls the
4594  *  generic setup_copper_link to finish configuring the link for
4595  *  Lynxpoint PCH devices
4596  **/
4597 STATIC s32 e1000_setup_copper_link_pch_lpt(struct e1000_hw *hw)
4598 {
4599         u32 ctrl;
4600         s32 ret_val;
4601
4602         DEBUGFUNC("e1000_setup_copper_link_pch_lpt");
4603
4604         ctrl = E1000_READ_REG(hw, E1000_CTRL);
4605         ctrl |= E1000_CTRL_SLU;
4606         ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
4607         E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
4608
4609         ret_val = e1000_copper_link_setup_82577(hw);
4610         if (ret_val)
4611                 return ret_val;
4612
4613         return e1000_setup_copper_link_generic(hw);
4614 }
4615
4616 /**
4617  *  e1000_get_link_up_info_ich8lan - Get current link speed and duplex
4618  *  @hw: pointer to the HW structure
4619  *  @speed: pointer to store current link speed
4620  *  @duplex: pointer to store the current link duplex
4621  *
4622  *  Calls the generic get_speed_and_duplex to retrieve the current link
4623  *  information and then calls the Kumeran lock loss workaround for links at
4624  *  gigabit speeds.
4625  **/
4626 STATIC s32 e1000_get_link_up_info_ich8lan(struct e1000_hw *hw, u16 *speed,
4627                                           u16 *duplex)
4628 {
4629         s32 ret_val;
4630
4631         DEBUGFUNC("e1000_get_link_up_info_ich8lan");
4632
4633         ret_val = e1000_get_speed_and_duplex_copper_generic(hw, speed, duplex);
4634         if (ret_val)
4635                 return ret_val;
4636
4637         if ((hw->mac.type == e1000_ich8lan) &&
4638             (hw->phy.type == e1000_phy_igp_3) &&
4639             (*speed == SPEED_1000)) {
4640                 ret_val = e1000_kmrn_lock_loss_workaround_ich8lan(hw);
4641         }
4642
4643         return ret_val;
4644 }
4645
4646 /**
4647  *  e1000_kmrn_lock_loss_workaround_ich8lan - Kumeran workaround
4648  *  @hw: pointer to the HW structure
4649  *
4650  *  Work-around for 82566 Kumeran PCS lock loss:
4651  *  On link status change (i.e. PCI reset, speed change) and link is up and
4652  *  speed is gigabit-
4653  *    0) if workaround is optionally disabled do nothing
4654  *    1) wait 1ms for Kumeran link to come up
4655  *    2) check Kumeran Diagnostic register PCS lock loss bit
4656  *    3) if not set the link is locked (all is good), otherwise...
4657  *    4) reset the PHY
4658  *    5) repeat up to 10 times
4659  *  Note: this is only called for IGP3 copper when speed is 1gb.
4660  **/
4661 STATIC s32 e1000_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw)
4662 {
4663         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
4664         u32 phy_ctrl;
4665         s32 ret_val;
4666         u16 i, data;
4667         bool link;
4668
4669         DEBUGFUNC("e1000_kmrn_lock_loss_workaround_ich8lan");
4670
4671         if (!dev_spec->kmrn_lock_loss_workaround_enabled)
4672                 return E1000_SUCCESS;
4673
4674         /* Make sure link is up before proceeding.  If not just return.
4675          * Attempting this while link is negotiating fouled up link
4676          * stability
4677          */
4678         ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link);
4679         if (!link)
4680                 return E1000_SUCCESS;
4681
4682         for (i = 0; i < 10; i++) {
4683                 /* read once to clear */
4684                 ret_val = hw->phy.ops.read_reg(hw, IGP3_KMRN_DIAG, &data);
4685                 if (ret_val)
4686                         return ret_val;
4687                 /* and again to get new status */
4688                 ret_val = hw->phy.ops.read_reg(hw, IGP3_KMRN_DIAG, &data);
4689                 if (ret_val)
4690                         return ret_val;
4691
4692                 /* check for PCS lock */
4693                 if (!(data & IGP3_KMRN_DIAG_PCS_LOCK_LOSS))
4694                         return E1000_SUCCESS;
4695
4696                 /* Issue PHY reset */
4697                 hw->phy.ops.reset(hw);
4698                 msec_delay_irq(5);
4699         }
4700         /* Disable GigE link negotiation */
4701         phy_ctrl = E1000_READ_REG(hw, E1000_PHY_CTRL);
4702         phy_ctrl |= (E1000_PHY_CTRL_GBE_DISABLE |
4703                      E1000_PHY_CTRL_NOND0A_GBE_DISABLE);
4704         E1000_WRITE_REG(hw, E1000_PHY_CTRL, phy_ctrl);
4705
4706         /* Call gig speed drop workaround on Gig disable before accessing
4707          * any PHY registers
4708          */
4709         e1000_gig_downshift_workaround_ich8lan(hw);
4710
4711         /* unable to acquire PCS lock */
4712         return -E1000_ERR_PHY;
4713 }
4714
4715 /**
4716  *  e1000_set_kmrn_lock_loss_workaround_ich8lan - Set Kumeran workaround state
4717  *  @hw: pointer to the HW structure
4718  *  @state: boolean value used to set the current Kumeran workaround state
4719  *
4720  *  If ICH8, set the current Kumeran workaround state (enabled - true
4721  *  /disabled - false).
4722  **/
4723 void e1000_set_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw,
4724                                                  bool state)
4725 {
4726         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
4727
4728         DEBUGFUNC("e1000_set_kmrn_lock_loss_workaround_ich8lan");
4729
4730         if (hw->mac.type != e1000_ich8lan) {
4731                 DEBUGOUT("Workaround applies to ICH8 only.\n");
4732                 return;
4733         }
4734
4735         dev_spec->kmrn_lock_loss_workaround_enabled = state;
4736
4737         return;
4738 }
4739
4740 /**
4741  *  e1000_ipg3_phy_powerdown_workaround_ich8lan - Power down workaround on D3
4742  *  @hw: pointer to the HW structure
4743  *
4744  *  Workaround for 82566 power-down on D3 entry:
4745  *    1) disable gigabit link
4746  *    2) write VR power-down enable
4747  *    3) read it back
4748  *  Continue if successful, else issue LCD reset and repeat
4749  **/
4750 void e1000_igp3_phy_powerdown_workaround_ich8lan(struct e1000_hw *hw)
4751 {
4752         u32 reg;
4753         u16 data;
4754         u8  retry = 0;
4755
4756         DEBUGFUNC("e1000_igp3_phy_powerdown_workaround_ich8lan");
4757
4758         if (hw->phy.type != e1000_phy_igp_3)
4759                 return;
4760
4761         /* Try the workaround twice (if needed) */
4762         do {
4763                 /* Disable link */
4764                 reg = E1000_READ_REG(hw, E1000_PHY_CTRL);
4765                 reg |= (E1000_PHY_CTRL_GBE_DISABLE |
4766                         E1000_PHY_CTRL_NOND0A_GBE_DISABLE);
4767                 E1000_WRITE_REG(hw, E1000_PHY_CTRL, reg);
4768
4769                 /* Call gig speed drop workaround on Gig disable before
4770                  * accessing any PHY registers
4771                  */
4772                 if (hw->mac.type == e1000_ich8lan)
4773                         e1000_gig_downshift_workaround_ich8lan(hw);
4774
4775                 /* Write VR power-down enable */
4776                 hw->phy.ops.read_reg(hw, IGP3_VR_CTRL, &data);
4777                 data &= ~IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK;
4778                 hw->phy.ops.write_reg(hw, IGP3_VR_CTRL,
4779                                       data | IGP3_VR_CTRL_MODE_SHUTDOWN);
4780
4781                 /* Read it back and test */
4782                 hw->phy.ops.read_reg(hw, IGP3_VR_CTRL, &data);
4783                 data &= IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK;
4784                 if ((data == IGP3_VR_CTRL_MODE_SHUTDOWN) || retry)
4785                         break;
4786
4787                 /* Issue PHY reset and repeat at most one more time */
4788                 reg = E1000_READ_REG(hw, E1000_CTRL);
4789                 E1000_WRITE_REG(hw, E1000_CTRL, reg | E1000_CTRL_PHY_RST);
4790                 retry++;
4791         } while (retry);
4792 }
4793
4794 /**
4795  *  e1000_gig_downshift_workaround_ich8lan - WoL from S5 stops working
4796  *  @hw: pointer to the HW structure
4797  *
4798  *  Steps to take when dropping from 1Gb/s (eg. link cable removal (LSC),
4799  *  LPLU, Gig disable, MDIC PHY reset):
4800  *    1) Set Kumeran Near-end loopback
4801  *    2) Clear Kumeran Near-end loopback
4802  *  Should only be called for ICH8[m] devices with any 1G Phy.
4803  **/
4804 void e1000_gig_downshift_workaround_ich8lan(struct e1000_hw *hw)
4805 {
4806         s32 ret_val;
4807         u16 reg_data;
4808
4809         DEBUGFUNC("e1000_gig_downshift_workaround_ich8lan");
4810
4811         if ((hw->mac.type != e1000_ich8lan) ||
4812             (hw->phy.type == e1000_phy_ife))
4813                 return;
4814
4815         ret_val = e1000_read_kmrn_reg_generic(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET,
4816                                               &reg_data);
4817         if (ret_val)
4818                 return;
4819         reg_data |= E1000_KMRNCTRLSTA_DIAG_NELPBK;
4820         ret_val = e1000_write_kmrn_reg_generic(hw,
4821                                                E1000_KMRNCTRLSTA_DIAG_OFFSET,
4822                                                reg_data);
4823         if (ret_val)
4824                 return;
4825         reg_data &= ~E1000_KMRNCTRLSTA_DIAG_NELPBK;
4826         e1000_write_kmrn_reg_generic(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET,
4827                                      reg_data);
4828 }
4829
4830 /**
4831  *  e1000_suspend_workarounds_ich8lan - workarounds needed during S0->Sx
4832  *  @hw: pointer to the HW structure
4833  *
4834  *  During S0 to Sx transition, it is possible the link remains at gig
4835  *  instead of negotiating to a lower speed.  Before going to Sx, set
4836  *  'Gig Disable' to force link speed negotiation to a lower speed based on
4837  *  the LPLU setting in the NVM or custom setting.  For PCH and newer parts,
4838  *  the OEM bits PHY register (LED, GbE disable and LPLU configurations) also
4839  *  needs to be written.
4840  *  Parts that support (and are linked to a partner which support) EEE in
4841  *  100Mbps should disable LPLU since 100Mbps w/ EEE requires less power
4842  *  than 10Mbps w/o EEE.
4843  **/
4844 void e1000_suspend_workarounds_ich8lan(struct e1000_hw *hw)
4845 {
4846         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
4847         u32 phy_ctrl;
4848         s32 ret_val;
4849
4850         DEBUGFUNC("e1000_suspend_workarounds_ich8lan");
4851
4852         phy_ctrl = E1000_READ_REG(hw, E1000_PHY_CTRL);
4853         phy_ctrl |= E1000_PHY_CTRL_GBE_DISABLE;
4854
4855         if (hw->phy.type == e1000_phy_i217) {
4856                 u16 phy_reg, device_id = hw->device_id;
4857
4858                 if ((device_id == E1000_DEV_ID_PCH_LPTLP_I218_LM) ||
4859                     (device_id == E1000_DEV_ID_PCH_LPTLP_I218_V) ||
4860                     (device_id == E1000_DEV_ID_PCH_I218_LM3) ||
4861                     (device_id == E1000_DEV_ID_PCH_I218_V3)) {
4862                         u32 fextnvm6 = E1000_READ_REG(hw, E1000_FEXTNVM6);
4863
4864                         E1000_WRITE_REG(hw, E1000_FEXTNVM6,
4865                                         fextnvm6 & ~E1000_FEXTNVM6_REQ_PLL_CLK);
4866                 }
4867
4868                 ret_val = hw->phy.ops.acquire(hw);
4869                 if (ret_val)
4870                         goto out;
4871
4872                 if (!dev_spec->eee_disable) {
4873                         u16 eee_advert;
4874
4875                         ret_val =
4876                             e1000_read_emi_reg_locked(hw,
4877                                                       I217_EEE_ADVERTISEMENT,
4878                                                       &eee_advert);
4879                         if (ret_val)
4880                                 goto release;
4881
4882                         /* Disable LPLU if both link partners support 100BaseT
4883                          * EEE and 100Full is advertised on both ends of the
4884                          * link, and enable Auto Enable LPI since there will
4885                          * be no driver to enable LPI while in Sx.
4886                          */
4887                         if ((eee_advert & I82579_EEE_100_SUPPORTED) &&
4888                             (dev_spec->eee_lp_ability &
4889                              I82579_EEE_100_SUPPORTED) &&
4890                             (hw->phy.autoneg_advertised & ADVERTISE_100_FULL)) {
4891                                 phy_ctrl &= ~(E1000_PHY_CTRL_D0A_LPLU |
4892                                               E1000_PHY_CTRL_NOND0A_LPLU);
4893
4894                                 /* Set Auto Enable LPI after link up */
4895                                 hw->phy.ops.read_reg_locked(hw,
4896                                                             I217_LPI_GPIO_CTRL,
4897                                                             &phy_reg);
4898                                 phy_reg |= I217_LPI_GPIO_CTRL_AUTO_EN_LPI;
4899                                 hw->phy.ops.write_reg_locked(hw,
4900                                                              I217_LPI_GPIO_CTRL,
4901                                                              phy_reg);
4902                         }
4903                 }
4904
4905                 /* For i217 Intel Rapid Start Technology support,
4906                  * when the system is going into Sx and no manageability engine
4907                  * is present, the driver must configure proxy to reset only on
4908                  * power good.  LPI (Low Power Idle) state must also reset only
4909                  * on power good, as well as the MTA (Multicast table array).
4910                  * The SMBus release must also be disabled on LCD reset.
4911                  */
4912                 if (!(E1000_READ_REG(hw, E1000_FWSM) &
4913                       E1000_ICH_FWSM_FW_VALID)) {
4914                         /* Enable proxy to reset only on power good. */
4915                         hw->phy.ops.read_reg_locked(hw, I217_PROXY_CTRL,
4916                                                     &phy_reg);
4917                         phy_reg |= I217_PROXY_CTRL_AUTO_DISABLE;
4918                         hw->phy.ops.write_reg_locked(hw, I217_PROXY_CTRL,
4919                                                      phy_reg);
4920
4921                         /* Set bit enable LPI (EEE) to reset only on
4922                          * power good.
4923                         */
4924                         hw->phy.ops.read_reg_locked(hw, I217_SxCTRL, &phy_reg);
4925                         phy_reg |= I217_SxCTRL_ENABLE_LPI_RESET;
4926                         hw->phy.ops.write_reg_locked(hw, I217_SxCTRL, phy_reg);
4927
4928                         /* Disable the SMB release on LCD reset. */
4929                         hw->phy.ops.read_reg_locked(hw, I217_MEMPWR, &phy_reg);
4930                         phy_reg &= ~I217_MEMPWR_DISABLE_SMB_RELEASE;
4931                         hw->phy.ops.write_reg_locked(hw, I217_MEMPWR, phy_reg);
4932                 }
4933
4934                 /* Enable MTA to reset for Intel Rapid Start Technology
4935                  * Support
4936                  */
4937                 hw->phy.ops.read_reg_locked(hw, I217_CGFREG, &phy_reg);
4938                 phy_reg |= I217_CGFREG_ENABLE_MTA_RESET;
4939                 hw->phy.ops.write_reg_locked(hw, I217_CGFREG, phy_reg);
4940
4941 release:
4942                 hw->phy.ops.release(hw);
4943         }
4944 out:
4945         E1000_WRITE_REG(hw, E1000_PHY_CTRL, phy_ctrl);
4946
4947         if (hw->mac.type == e1000_ich8lan)
4948                 e1000_gig_downshift_workaround_ich8lan(hw);
4949
4950         if (hw->mac.type >= e1000_pchlan) {
4951                 e1000_oem_bits_config_ich8lan(hw, false);
4952
4953                 /* Reset PHY to activate OEM bits on 82577/8 */
4954                 if (hw->mac.type == e1000_pchlan)
4955                         e1000_phy_hw_reset_generic(hw);
4956
4957                 ret_val = hw->phy.ops.acquire(hw);
4958                 if (ret_val)
4959                         return;
4960                 e1000_write_smbus_addr(hw);
4961                 hw->phy.ops.release(hw);
4962         }
4963
4964         return;
4965 }
4966
4967 /**
4968  *  e1000_resume_workarounds_pchlan - workarounds needed during Sx->S0
4969  *  @hw: pointer to the HW structure
4970  *
4971  *  During Sx to S0 transitions on non-managed devices or managed devices
4972  *  on which PHY resets are not blocked, if the PHY registers cannot be
4973  *  accessed properly by the s/w toggle the LANPHYPC value to power cycle
4974  *  the PHY.
4975  *  On i217, setup Intel Rapid Start Technology.
4976  **/
4977 u32 e1000_resume_workarounds_pchlan(struct e1000_hw *hw)
4978 {
4979         s32 ret_val;
4980
4981         DEBUGFUNC("e1000_resume_workarounds_pchlan");
4982         if (hw->mac.type < e1000_pch2lan)
4983                 return E1000_SUCCESS;
4984
4985         ret_val = e1000_init_phy_workarounds_pchlan(hw);
4986         if (ret_val) {
4987                 DEBUGOUT1("Failed to init PHY flow ret_val=%d\n", ret_val);
4988                 return ret_val;
4989         }
4990
4991         /* For i217 Intel Rapid Start Technology support when the system
4992          * is transitioning from Sx and no manageability engine is present
4993          * configure SMBus to restore on reset, disable proxy, and enable
4994          * the reset on MTA (Multicast table array).
4995          */
4996         if (hw->phy.type == e1000_phy_i217) {
4997                 u16 phy_reg;
4998
4999                 ret_val = hw->phy.ops.acquire(hw);
5000                 if (ret_val) {
5001                         DEBUGOUT("Failed to setup iRST\n");
5002                         return ret_val;
5003                 }
5004
5005                 /* Clear Auto Enable LPI after link up */
5006                 hw->phy.ops.read_reg_locked(hw, I217_LPI_GPIO_CTRL, &phy_reg);
5007                 phy_reg &= ~I217_LPI_GPIO_CTRL_AUTO_EN_LPI;
5008                 hw->phy.ops.write_reg_locked(hw, I217_LPI_GPIO_CTRL, phy_reg);
5009
5010                 if (!(E1000_READ_REG(hw, E1000_FWSM) &
5011                     E1000_ICH_FWSM_FW_VALID)) {
5012                         /* Restore clear on SMB if no manageability engine
5013                          * is present
5014                          */
5015                         ret_val = hw->phy.ops.read_reg_locked(hw, I217_MEMPWR,
5016                                                               &phy_reg);
5017                         if (ret_val)
5018                                 goto release;
5019                         phy_reg |= I217_MEMPWR_DISABLE_SMB_RELEASE;
5020                         hw->phy.ops.write_reg_locked(hw, I217_MEMPWR, phy_reg);
5021
5022                         /* Disable Proxy */
5023                         hw->phy.ops.write_reg_locked(hw, I217_PROXY_CTRL, 0);
5024                 }
5025                 /* Enable reset on MTA */
5026                 ret_val = hw->phy.ops.read_reg_locked(hw, I217_CGFREG,
5027                                                       &phy_reg);
5028                 if (ret_val)
5029                         goto release;
5030                 phy_reg &= ~I217_CGFREG_ENABLE_MTA_RESET;
5031                 hw->phy.ops.write_reg_locked(hw, I217_CGFREG, phy_reg);
5032 release:
5033                 if (ret_val)
5034                         DEBUGOUT1("Error %d in resume workarounds\n", ret_val);
5035                 hw->phy.ops.release(hw);
5036                 return ret_val;
5037         }
5038         return E1000_SUCCESS;
5039 }
5040
5041 /**
5042  *  e1000_cleanup_led_ich8lan - Restore the default LED operation
5043  *  @hw: pointer to the HW structure
5044  *
5045  *  Return the LED back to the default configuration.
5046  **/
5047 STATIC s32 e1000_cleanup_led_ich8lan(struct e1000_hw *hw)
5048 {
5049         DEBUGFUNC("e1000_cleanup_led_ich8lan");
5050
5051         if (hw->phy.type == e1000_phy_ife)
5052                 return hw->phy.ops.write_reg(hw, IFE_PHY_SPECIAL_CONTROL_LED,
5053                                              0);
5054
5055         E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_default);
5056         return E1000_SUCCESS;
5057 }
5058
5059 /**
5060  *  e1000_led_on_ich8lan - Turn LEDs on
5061  *  @hw: pointer to the HW structure
5062  *
5063  *  Turn on the LEDs.
5064  **/
5065 STATIC s32 e1000_led_on_ich8lan(struct e1000_hw *hw)
5066 {
5067         DEBUGFUNC("e1000_led_on_ich8lan");
5068
5069         if (hw->phy.type == e1000_phy_ife)
5070                 return hw->phy.ops.write_reg(hw, IFE_PHY_SPECIAL_CONTROL_LED,
5071                                 (IFE_PSCL_PROBE_MODE | IFE_PSCL_PROBE_LEDS_ON));
5072
5073         E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_mode2);
5074         return E1000_SUCCESS;
5075 }
5076
5077 /**
5078  *  e1000_led_off_ich8lan - Turn LEDs off
5079  *  @hw: pointer to the HW structure
5080  *
5081  *  Turn off the LEDs.
5082  **/
5083 STATIC s32 e1000_led_off_ich8lan(struct e1000_hw *hw)
5084 {
5085         DEBUGFUNC("e1000_led_off_ich8lan");
5086
5087         if (hw->phy.type == e1000_phy_ife)
5088                 return hw->phy.ops.write_reg(hw, IFE_PHY_SPECIAL_CONTROL_LED,
5089                                (IFE_PSCL_PROBE_MODE | IFE_PSCL_PROBE_LEDS_OFF));
5090
5091         E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_mode1);
5092         return E1000_SUCCESS;
5093 }
5094
5095 /**
5096  *  e1000_setup_led_pchlan - Configures SW controllable LED
5097  *  @hw: pointer to the HW structure
5098  *
5099  *  This prepares the SW controllable LED for use.
5100  **/
5101 STATIC s32 e1000_setup_led_pchlan(struct e1000_hw *hw)
5102 {
5103         DEBUGFUNC("e1000_setup_led_pchlan");
5104
5105         return hw->phy.ops.write_reg(hw, HV_LED_CONFIG,
5106                                      (u16)hw->mac.ledctl_mode1);
5107 }
5108
5109 /**
5110  *  e1000_cleanup_led_pchlan - Restore the default LED operation
5111  *  @hw: pointer to the HW structure
5112  *
5113  *  Return the LED back to the default configuration.
5114  **/
5115 STATIC s32 e1000_cleanup_led_pchlan(struct e1000_hw *hw)
5116 {
5117         DEBUGFUNC("e1000_cleanup_led_pchlan");
5118
5119         return hw->phy.ops.write_reg(hw, HV_LED_CONFIG,
5120                                      (u16)hw->mac.ledctl_default);
5121 }
5122
5123 /**
5124  *  e1000_led_on_pchlan - Turn LEDs on
5125  *  @hw: pointer to the HW structure
5126  *
5127  *  Turn on the LEDs.
5128  **/
5129 STATIC s32 e1000_led_on_pchlan(struct e1000_hw *hw)
5130 {
5131         u16 data = (u16)hw->mac.ledctl_mode2;
5132         u32 i, led;
5133
5134         DEBUGFUNC("e1000_led_on_pchlan");
5135
5136         /* If no link, then turn LED on by setting the invert bit
5137          * for each LED that's mode is "link_up" in ledctl_mode2.
5138          */
5139         if (!(E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU)) {
5140                 for (i = 0; i < 3; i++) {
5141                         led = (data >> (i * 5)) & E1000_PHY_LED0_MASK;
5142                         if ((led & E1000_PHY_LED0_MODE_MASK) !=
5143                             E1000_LEDCTL_MODE_LINK_UP)
5144                                 continue;
5145                         if (led & E1000_PHY_LED0_IVRT)
5146                                 data &= ~(E1000_PHY_LED0_IVRT << (i * 5));
5147                         else
5148                                 data |= (E1000_PHY_LED0_IVRT << (i * 5));
5149                 }
5150         }
5151
5152         return hw->phy.ops.write_reg(hw, HV_LED_CONFIG, data);
5153 }
5154
5155 /**
5156  *  e1000_led_off_pchlan - Turn LEDs off
5157  *  @hw: pointer to the HW structure
5158  *
5159  *  Turn off the LEDs.
5160  **/
5161 STATIC s32 e1000_led_off_pchlan(struct e1000_hw *hw)
5162 {
5163         u16 data = (u16)hw->mac.ledctl_mode1;
5164         u32 i, led;
5165
5166         DEBUGFUNC("e1000_led_off_pchlan");
5167
5168         /* If no link, then turn LED off by clearing the invert bit
5169          * for each LED that's mode is "link_up" in ledctl_mode1.
5170          */
5171         if (!(E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU)) {
5172                 for (i = 0; i < 3; i++) {
5173                         led = (data >> (i * 5)) & E1000_PHY_LED0_MASK;
5174                         if ((led & E1000_PHY_LED0_MODE_MASK) !=
5175                             E1000_LEDCTL_MODE_LINK_UP)
5176                                 continue;
5177                         if (led & E1000_PHY_LED0_IVRT)
5178                                 data &= ~(E1000_PHY_LED0_IVRT << (i * 5));
5179                         else
5180                                 data |= (E1000_PHY_LED0_IVRT << (i * 5));
5181                 }
5182         }
5183
5184         return hw->phy.ops.write_reg(hw, HV_LED_CONFIG, data);
5185 }
5186
5187 /**
5188  *  e1000_get_cfg_done_ich8lan - Read config done bit after Full or PHY reset
5189  *  @hw: pointer to the HW structure
5190  *
5191  *  Read appropriate register for the config done bit for completion status
5192  *  and configure the PHY through s/w for EEPROM-less parts.
5193  *
5194  *  NOTE: some silicon which is EEPROM-less will fail trying to read the
5195  *  config done bit, so only an error is logged and continues.  If we were
5196  *  to return with error, EEPROM-less silicon would not be able to be reset
5197  *  or change link.
5198  **/
5199 STATIC s32 e1000_get_cfg_done_ich8lan(struct e1000_hw *hw)
5200 {
5201         s32 ret_val = E1000_SUCCESS;
5202         u32 bank = 0;
5203         u32 status;
5204
5205         DEBUGFUNC("e1000_get_cfg_done_ich8lan");
5206
5207         e1000_get_cfg_done_generic(hw);
5208
5209         /* Wait for indication from h/w that it has completed basic config */
5210         if (hw->mac.type >= e1000_ich10lan) {
5211                 e1000_lan_init_done_ich8lan(hw);
5212         } else {
5213                 ret_val = e1000_get_auto_rd_done_generic(hw);
5214                 if (ret_val) {
5215                         /* When auto config read does not complete, do not
5216                          * return with an error. This can happen in situations
5217                          * where there is no eeprom and prevents getting link.
5218                          */
5219                         DEBUGOUT("Auto Read Done did not complete\n");
5220                         ret_val = E1000_SUCCESS;
5221                 }
5222         }
5223
5224         /* Clear PHY Reset Asserted bit */
5225         status = E1000_READ_REG(hw, E1000_STATUS);
5226         if (status & E1000_STATUS_PHYRA)
5227                 E1000_WRITE_REG(hw, E1000_STATUS, status & ~E1000_STATUS_PHYRA);
5228         else
5229                 DEBUGOUT("PHY Reset Asserted not set - needs delay\n");
5230
5231         /* If EEPROM is not marked present, init the IGP 3 PHY manually */
5232         if (hw->mac.type <= e1000_ich9lan) {
5233                 if (!(E1000_READ_REG(hw, E1000_EECD) & E1000_EECD_PRES) &&
5234                     (hw->phy.type == e1000_phy_igp_3)) {
5235                         e1000_phy_init_script_igp3(hw);
5236                 }
5237         } else {
5238                 if (e1000_valid_nvm_bank_detect_ich8lan(hw, &bank)) {
5239                         /* Maybe we should do a basic PHY config */
5240                         DEBUGOUT("EEPROM not present\n");
5241                         ret_val = -E1000_ERR_CONFIG;
5242                 }
5243         }
5244
5245         return ret_val;
5246 }
5247
5248 /**
5249  * e1000_power_down_phy_copper_ich8lan - Remove link during PHY power down
5250  * @hw: pointer to the HW structure
5251  *
5252  * In the case of a PHY power down to save power, or to turn off link during a
5253  * driver unload, or wake on lan is not enabled, remove the link.
5254  **/
5255 STATIC void e1000_power_down_phy_copper_ich8lan(struct e1000_hw *hw)
5256 {
5257         /* If the management interface is not enabled, then power down */
5258         if (!(hw->mac.ops.check_mng_mode(hw) ||
5259               hw->phy.ops.check_reset_block(hw)))
5260                 e1000_power_down_phy_copper(hw);
5261
5262         return;
5263 }
5264
5265 /**
5266  *  e1000_clear_hw_cntrs_ich8lan - Clear statistical counters
5267  *  @hw: pointer to the HW structure
5268  *
5269  *  Clears hardware counters specific to the silicon family and calls
5270  *  clear_hw_cntrs_generic to clear all general purpose counters.
5271  **/
5272 STATIC void e1000_clear_hw_cntrs_ich8lan(struct e1000_hw *hw)
5273 {
5274         u16 phy_data;
5275         s32 ret_val;
5276
5277         DEBUGFUNC("e1000_clear_hw_cntrs_ich8lan");
5278
5279         e1000_clear_hw_cntrs_base_generic(hw);
5280
5281         E1000_READ_REG(hw, E1000_ALGNERRC);
5282         E1000_READ_REG(hw, E1000_RXERRC);
5283         E1000_READ_REG(hw, E1000_TNCRS);
5284         E1000_READ_REG(hw, E1000_CEXTERR);
5285         E1000_READ_REG(hw, E1000_TSCTC);
5286         E1000_READ_REG(hw, E1000_TSCTFC);
5287
5288         E1000_READ_REG(hw, E1000_MGTPRC);
5289         E1000_READ_REG(hw, E1000_MGTPDC);
5290         E1000_READ_REG(hw, E1000_MGTPTC);
5291
5292         E1000_READ_REG(hw, E1000_IAC);
5293         E1000_READ_REG(hw, E1000_ICRXOC);
5294
5295         /* Clear PHY statistics registers */
5296         if ((hw->phy.type == e1000_phy_82578) ||
5297             (hw->phy.type == e1000_phy_82579) ||
5298             (hw->phy.type == e1000_phy_i217) ||
5299             (hw->phy.type == e1000_phy_82577)) {
5300                 ret_val = hw->phy.ops.acquire(hw);
5301                 if (ret_val)
5302                         return;
5303                 ret_val = hw->phy.ops.set_page(hw,
5304                                                HV_STATS_PAGE << IGP_PAGE_SHIFT);
5305                 if (ret_val)
5306                         goto release;
5307                 hw->phy.ops.read_reg_page(hw, HV_SCC_UPPER, &phy_data);
5308                 hw->phy.ops.read_reg_page(hw, HV_SCC_LOWER, &phy_data);
5309                 hw->phy.ops.read_reg_page(hw, HV_ECOL_UPPER, &phy_data);
5310                 hw->phy.ops.read_reg_page(hw, HV_ECOL_LOWER, &phy_data);
5311                 hw->phy.ops.read_reg_page(hw, HV_MCC_UPPER, &phy_data);
5312                 hw->phy.ops.read_reg_page(hw, HV_MCC_LOWER, &phy_data);
5313                 hw->phy.ops.read_reg_page(hw, HV_LATECOL_UPPER, &phy_data);
5314                 hw->phy.ops.read_reg_page(hw, HV_LATECOL_LOWER, &phy_data);
5315                 hw->phy.ops.read_reg_page(hw, HV_COLC_UPPER, &phy_data);
5316                 hw->phy.ops.read_reg_page(hw, HV_COLC_LOWER, &phy_data);
5317                 hw->phy.ops.read_reg_page(hw, HV_DC_UPPER, &phy_data);
5318                 hw->phy.ops.read_reg_page(hw, HV_DC_LOWER, &phy_data);
5319                 hw->phy.ops.read_reg_page(hw, HV_TNCRS_UPPER, &phy_data);
5320                 hw->phy.ops.read_reg_page(hw, HV_TNCRS_LOWER, &phy_data);
5321 release:
5322                 hw->phy.ops.release(hw);
5323         }
5324 }
5325
5326 /**
5327  *  e1000_configure_k0s_lpt - Configure K0s power state
5328  *  @hw: pointer to the HW structure
5329  *  @entry_latency: Tx idle period for entering K0s - valid values are 0 to 3.
5330  *      0 corresponds to 128ns, each value over 0 doubles the duration.
5331  *  @min_time: Minimum Tx idle period allowed  - valid values are 0 to 4.
5332  *      0 corresponds to 128ns, each value over 0 doubles the duration.
5333  *
5334  *  Configure the K1 power state based on the provided parameter.
5335  *  Assumes semaphore already acquired.
5336  *
5337  *  Success returns 0, Failure returns:
5338  *      -E1000_ERR_PHY (-2) in case of access error
5339  *      -E1000_ERR_PARAM (-4) in case of parameters error
5340  **/
5341 s32 e1000_configure_k0s_lpt(struct e1000_hw *hw, u8 entry_latency, u8 min_time)
5342 {
5343         s32 ret_val;
5344         u16 kmrn_reg = 0;
5345
5346         DEBUGFUNC("e1000_configure_k0s_lpt");
5347
5348         if (entry_latency > 3 || min_time > 4)
5349                 return -E1000_ERR_PARAM;
5350
5351         ret_val = e1000_read_kmrn_reg_locked(hw, E1000_KMRNCTRLSTA_K0S_CTRL,
5352                                              &kmrn_reg);
5353         if (ret_val)
5354                 return ret_val;
5355
5356         /* for now don't touch the latency */
5357         kmrn_reg &= ~(E1000_KMRNCTRLSTA_K0S_CTRL_MIN_TIME_MASK);
5358         kmrn_reg |= ((min_time << E1000_KMRNCTRLSTA_K0S_CTRL_MIN_TIME_SHIFT));
5359
5360         ret_val = e1000_write_kmrn_reg_locked(hw, E1000_KMRNCTRLSTA_K0S_CTRL,
5361                                               kmrn_reg);
5362         if (ret_val)
5363                 return ret_val;
5364
5365         return E1000_SUCCESS;
5366 }