drivers/net/e1000/base/e1000_nvm.c

   1 /*******************************************************************************
   2
   3 Copyright (c) 2001-2015, Intel Corporation
   4 All rights reserved.
   5
   6 Redistribution and use in source and binary forms, with or without
   7 modification, are permitted provided that the following conditions are met:
   8
   9  1. Redistributions of source code must retain the above copyright notice,
  10     this list of conditions and the following disclaimer.
  11
  12  2. Redistributions in binary form must reproduce the above copyright
  13     notice, this list of conditions and the following disclaimer in the
  14     documentation and/or other materials provided with the distribution.
  15
  16  3. Neither the name of the Intel Corporation nor the names of its
  17     contributors may be used to endorse or promote products derived from
  18     this software without specific prior written permission.
  19
  20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
  24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  30 POSSIBILITY OF SUCH DAMAGE.
  31
  32 ***************************************************************************/
  33
  34 #include "e1000_api.h"
  35
  36 STATIC void e1000_reload_nvm_generic(struct e1000_hw *hw);
  37
  38 /**
  39  *  e1000_init_nvm_ops_generic - Initialize NVM function pointers
  40  *  @hw: pointer to the HW structure
  41  *
  42  *  Setups up the function pointers to no-op functions
  43  **/
  44 void e1000_init_nvm_ops_generic(struct e1000_hw *hw)
  45 {
  46         struct e1000_nvm_info *nvm = &hw->nvm;
  47         DEBUGFUNC("e1000_init_nvm_ops_generic");
  48
  49         /* Initialize function pointers */
  50         nvm->ops.init_params = e1000_null_ops_generic;
  51         nvm->ops.acquire = e1000_null_ops_generic;
  52         nvm->ops.read = e1000_null_read_nvm;
  53         nvm->ops.release = e1000_null_nvm_generic;
  54         nvm->ops.reload = e1000_reload_nvm_generic;
  55         nvm->ops.update = e1000_null_ops_generic;
  56         nvm->ops.valid_led_default = e1000_null_led_default;
  57         nvm->ops.validate = e1000_null_ops_generic;
  58         nvm->ops.write = e1000_null_write_nvm;
  59 }
  60
  61 /**
  62  *  e1000_null_nvm_read - No-op function, return 0
  63  *  @hw: pointer to the HW structure
  64  **/
  65 s32 e1000_null_read_nvm(struct e1000_hw E1000_UNUSEDARG *hw,
  66                         u16 E1000_UNUSEDARG a, u16 E1000_UNUSEDARG b,
  67                         u16 E1000_UNUSEDARG *c)
  68 {
  69         DEBUGFUNC("e1000_null_read_nvm");
  70         UNREFERENCED_4PARAMETER(hw, a, b, c);
  71         return E1000_SUCCESS;
  72 }
  73
  74 /**
  75  *  e1000_null_nvm_generic - No-op function, return void
  76  *  @hw: pointer to the HW structure
  77  **/
  78 void e1000_null_nvm_generic(struct e1000_hw E1000_UNUSEDARG *hw)
  79 {
  80         DEBUGFUNC("e1000_null_nvm_generic");
  81         UNREFERENCED_1PARAMETER(hw);
  82         return;
  83 }
  84
  85 /**
  86  *  e1000_null_led_default - No-op function, return 0
  87  *  @hw: pointer to the HW structure
  88  **/
  89 s32 e1000_null_led_default(struct e1000_hw E1000_UNUSEDARG *hw,
  90                            u16 E1000_UNUSEDARG *data)
  91 {
  92         DEBUGFUNC("e1000_null_led_default");
  93         UNREFERENCED_2PARAMETER(hw, data);
  94         return E1000_SUCCESS;
  95 }
  96
  97 /**
  98  *  e1000_null_write_nvm - No-op function, return 0
  99  *  @hw: pointer to the HW structure
 100  **/
 101 s32 e1000_null_write_nvm(struct e1000_hw E1000_UNUSEDARG *hw,
 102                          u16 E1000_UNUSEDARG a, u16 E1000_UNUSEDARG b,
 103                          u16 E1000_UNUSEDARG *c)
 104 {
 105         DEBUGFUNC("e1000_null_write_nvm");
 106         UNREFERENCED_4PARAMETER(hw, a, b, c);
 107         return E1000_SUCCESS;
 108 }
 109
 110 /**
 111  *  e1000_raise_eec_clk - Raise EEPROM clock
 112  *  @hw: pointer to the HW structure
 113  *  @eecd: pointer to the EEPROM
 114  *
 115  *  Enable/Raise the EEPROM clock bit.
 116  **/
 117 STATIC void e1000_raise_eec_clk(struct e1000_hw *hw, u32 *eecd)
 118 {
 119         *eecd = *eecd | E1000_EECD_SK;
 120         E1000_WRITE_REG(hw, E1000_EECD, *eecd);
 121         E1000_WRITE_FLUSH(hw);
 122         usec_delay(hw->nvm.delay_usec);
 123 }
 124
 125 /**
 126  *  e1000_lower_eec_clk - Lower EEPROM clock
 127  *  @hw: pointer to the HW structure
 128  *  @eecd: pointer to the EEPROM
 129  *
 130  *  Clear/Lower the EEPROM clock bit.
 131  **/
 132 STATIC void e1000_lower_eec_clk(struct e1000_hw *hw, u32 *eecd)
 133 {
 134         *eecd = *eecd & ~E1000_EECD_SK;
 135         E1000_WRITE_REG(hw, E1000_EECD, *eecd);
 136         E1000_WRITE_FLUSH(hw);
 137         usec_delay(hw->nvm.delay_usec);
 138 }
 139
 140 /**
 141  *  e1000_shift_out_eec_bits - Shift data bits our to the EEPROM
 142  *  @hw: pointer to the HW structure
 143  *  @data: data to send to the EEPROM
 144  *  @count: number of bits to shift out
 145  *
 146  *  We need to shift 'count' bits out to the EEPROM.  So, the value in the
 147  *  "data" parameter will be shifted out to the EEPROM one bit at a time.
 148  *  In order to do this, "data" must be broken down into bits.
 149  **/
 150 STATIC void e1000_shift_out_eec_bits(struct e1000_hw *hw, u16 data, u16 count)
 151 {
 152         struct e1000_nvm_info *nvm = &hw->nvm;
 153         u32 eecd = E1000_READ_REG(hw, E1000_EECD);
 154         u32 mask;
 155
 156         DEBUGFUNC("e1000_shift_out_eec_bits");
 157
 158         mask = 0x01 << (count - 1);
 159         if (nvm->type == e1000_nvm_eeprom_microwire)
 160                 eecd &= ~E1000_EECD_DO;
 161         else
 162         if (nvm->type == e1000_nvm_eeprom_spi)
 163                 eecd |= E1000_EECD_DO;
 164
 165         do {
 166                 eecd &= ~E1000_EECD_DI;
 167
 168                 if (data & mask)
 169                         eecd |= E1000_EECD_DI;
 170
 171                 E1000_WRITE_REG(hw, E1000_EECD, eecd);
 172                 E1000_WRITE_FLUSH(hw);
 173
 174                 usec_delay(nvm->delay_usec);
 175
 176                 e1000_raise_eec_clk(hw, &eecd);
 177                 e1000_lower_eec_clk(hw, &eecd);
 178
 179                 mask >>= 1;
 180         } while (mask);
 181
 182         eecd &= ~E1000_EECD_DI;
 183         E1000_WRITE_REG(hw, E1000_EECD, eecd);
 184 }
 185
 186 /**
 187  *  e1000_shift_in_eec_bits - Shift data bits in from the EEPROM
 188  *  @hw: pointer to the HW structure
 189  *  @count: number of bits to shift in
 190  *
 191  *  In order to read a register from the EEPROM, we need to shift 'count' bits
 192  *  in from the EEPROM.  Bits are "shifted in" by raising the clock input to
 193  *  the EEPROM (setting the SK bit), and then reading the value of the data out
 194  *  "DO" bit.  During this "shifting in" process the data in "DI" bit should
 195  *  always be clear.
 196  **/
 197 STATIC u16 e1000_shift_in_eec_bits(struct e1000_hw *hw, u16 count)
 198 {
 199         u32 eecd;
 200         u32 i;
 201         u16 data;
 202
 203         DEBUGFUNC("e1000_shift_in_eec_bits");
 204
 205         eecd = E1000_READ_REG(hw, E1000_EECD);
 206
 207         eecd &= ~(E1000_EECD_DO | E1000_EECD_DI);
 208         data = 0;
 209
 210         for (i = 0; i < count; i++) {
 211                 data <<= 1;
 212                 e1000_raise_eec_clk(hw, &eecd);
 213
 214                 eecd = E1000_READ_REG(hw, E1000_EECD);
 215
 216                 eecd &= ~E1000_EECD_DI;
 217                 if (eecd & E1000_EECD_DO)
 218                         data |= 1;
 219
 220                 e1000_lower_eec_clk(hw, &eecd);
 221         }
 222
 223         return data;
 224 }
 225
 226 /**
 227  *  e1000_poll_eerd_eewr_done - Poll for EEPROM read/write completion
 228  *  @hw: pointer to the HW structure
 229  *  @ee_reg: EEPROM flag for polling
 230  *
 231  *  Polls the EEPROM status bit for either read or write completion based
 232  *  upon the value of 'ee_reg'.
 233  **/
 234 s32 e1000_poll_eerd_eewr_done(struct e1000_hw *hw, int ee_reg)
 235 {
 236         u32 attempts = 100000;
 237         u32 i, reg = 0;
 238
 239         DEBUGFUNC("e1000_poll_eerd_eewr_done");
 240
 241         for (i = 0; i < attempts; i++) {
 242                 if (ee_reg == E1000_NVM_POLL_READ)
 243                         reg = E1000_READ_REG(hw, E1000_EERD);
 244                 else
 245                         reg = E1000_READ_REG(hw, E1000_EEWR);
 246
 247                 if (reg & E1000_NVM_RW_REG_DONE)
 248                         return E1000_SUCCESS;
 249
 250                 usec_delay(5);
 251         }
 252
 253         return -E1000_ERR_NVM;
 254 }
 255
 256 /**
 257  *  e1000_acquire_nvm_generic - Generic request for access to EEPROM
 258  *  @hw: pointer to the HW structure
 259  *
 260  *  Set the EEPROM access request bit and wait for EEPROM access grant bit.
 261  *  Return successful if access grant bit set, else clear the request for
 262  *  EEPROM access and return -E1000_ERR_NVM (-1).
 263  **/
 264 s32 e1000_acquire_nvm_generic(struct e1000_hw *hw)
 265 {
 266         u32 eecd = E1000_READ_REG(hw, E1000_EECD);
 267         s32 timeout = E1000_NVM_GRANT_ATTEMPTS;
 268
 269         DEBUGFUNC("e1000_acquire_nvm_generic");
 270
 271         E1000_WRITE_REG(hw, E1000_EECD, eecd | E1000_EECD_REQ);
 272         eecd = E1000_READ_REG(hw, E1000_EECD);
 273
 274         while (timeout) {
 275                 if (eecd & E1000_EECD_GNT)
 276                         break;
 277                 usec_delay(5);
 278                 eecd = E1000_READ_REG(hw, E1000_EECD);
 279                 timeout--;
 280         }
 281
 282         if (!timeout) {
 283                 eecd &= ~E1000_EECD_REQ;
 284                 E1000_WRITE_REG(hw, E1000_EECD, eecd);
 285                 DEBUGOUT("Could not acquire NVM grant\n");
 286                 return -E1000_ERR_NVM;
 287         }
 288
 289         return E1000_SUCCESS;
 290 }
 291
 292 /**
 293  *  e1000_standby_nvm - Return EEPROM to standby state
 294  *  @hw: pointer to the HW structure
 295  *
 296  *  Return the EEPROM to a standby state.
 297  **/
 298 STATIC void e1000_standby_nvm(struct e1000_hw *hw)
 299 {
 300         struct e1000_nvm_info *nvm = &hw->nvm;
 301         u32 eecd = E1000_READ_REG(hw, E1000_EECD);
 302
 303         DEBUGFUNC("e1000_standby_nvm");
 304
 305         if (nvm->type == e1000_nvm_eeprom_microwire) {
 306                 eecd &= ~(E1000_EECD_CS | E1000_EECD_SK);
 307                 E1000_WRITE_REG(hw, E1000_EECD, eecd);
 308                 E1000_WRITE_FLUSH(hw);
 309                 usec_delay(nvm->delay_usec);
 310
 311                 e1000_raise_eec_clk(hw, &eecd);
 312
 313                 /* Select EEPROM */
 314                 eecd |= E1000_EECD_CS;
 315                 E1000_WRITE_REG(hw, E1000_EECD, eecd);
 316                 E1000_WRITE_FLUSH(hw);
 317                 usec_delay(nvm->delay_usec);
 318
 319                 e1000_lower_eec_clk(hw, &eecd);
 320         } else if (nvm->type == e1000_nvm_eeprom_spi) {
 321                 /* Toggle CS to flush commands */
 322                 eecd |= E1000_EECD_CS;
 323                 E1000_WRITE_REG(hw, E1000_EECD, eecd);
 324                 E1000_WRITE_FLUSH(hw);
 325                 usec_delay(nvm->delay_usec);
 326                 eecd &= ~E1000_EECD_CS;
 327                 E1000_WRITE_REG(hw, E1000_EECD, eecd);
 328                 E1000_WRITE_FLUSH(hw);
 329                 usec_delay(nvm->delay_usec);
 330         }
 331 }
 332
 333 /**
 334  *  e1000_stop_nvm - Terminate EEPROM command
 335  *  @hw: pointer to the HW structure
 336  *
 337  *  Terminates the current command by inverting the EEPROM's chip select pin.
 338  **/
 339 void e1000_stop_nvm(struct e1000_hw *hw)
 340 {
 341         u32 eecd;
 342
 343         DEBUGFUNC("e1000_stop_nvm");
 344
 345         eecd = E1000_READ_REG(hw, E1000_EECD);
 346         if (hw->nvm.type == e1000_nvm_eeprom_spi) {
 347                 /* Pull CS high */
 348                 eecd |= E1000_EECD_CS;
 349                 e1000_lower_eec_clk(hw, &eecd);
 350         } else if (hw->nvm.type == e1000_nvm_eeprom_microwire) {
 351                 /* CS on Microwire is active-high */
 352                 eecd &= ~(E1000_EECD_CS | E1000_EECD_DI);
 353                 E1000_WRITE_REG(hw, E1000_EECD, eecd);
 354                 e1000_raise_eec_clk(hw, &eecd);
 355                 e1000_lower_eec_clk(hw, &eecd);
 356         }
 357 }
 358
 359 /**
 360  *  e1000_release_nvm_generic - Release exclusive access to EEPROM
 361  *  @hw: pointer to the HW structure
 362  *
 363  *  Stop any current commands to the EEPROM and clear the EEPROM request bit.
 364  **/
 365 void e1000_release_nvm_generic(struct e1000_hw *hw)
 366 {
 367         u32 eecd;
 368
 369         DEBUGFUNC("e1000_release_nvm_generic");
 370
 371         e1000_stop_nvm(hw);
 372
 373         eecd = E1000_READ_REG(hw, E1000_EECD);
 374         eecd &= ~E1000_EECD_REQ;
 375         E1000_WRITE_REG(hw, E1000_EECD, eecd);
 376 }
 377
 378 /**
 379  *  e1000_ready_nvm_eeprom - Prepares EEPROM for read/write
 380  *  @hw: pointer to the HW structure
 381  *
 382  *  Setups the EEPROM for reading and writing.
 383  **/
 384 STATIC s32 e1000_ready_nvm_eeprom(struct e1000_hw *hw)
 385 {
 386         struct e1000_nvm_info *nvm = &hw->nvm;
 387         u32 eecd = E1000_READ_REG(hw, E1000_EECD);
 388         u8 spi_stat_reg;
 389
 390         DEBUGFUNC("e1000_ready_nvm_eeprom");
 391
 392         if (nvm->type == e1000_nvm_eeprom_microwire) {
 393                 /* Clear SK and DI */
 394                 eecd &= ~(E1000_EECD_DI | E1000_EECD_SK);
 395                 E1000_WRITE_REG(hw, E1000_EECD, eecd);
 396                 /* Set CS */
 397                 eecd |= E1000_EECD_CS;
 398                 E1000_WRITE_REG(hw, E1000_EECD, eecd);
 399         } else if (nvm->type == e1000_nvm_eeprom_spi) {
 400                 u16 timeout = NVM_MAX_RETRY_SPI;
 401
 402                 /* Clear SK and CS */
 403                 eecd &= ~(E1000_EECD_CS | E1000_EECD_SK);
 404                 E1000_WRITE_REG(hw, E1000_EECD, eecd);
 405                 E1000_WRITE_FLUSH(hw);
 406                 usec_delay(1);
 407
 408                 /* Read "Status Register" repeatedly until the LSB is cleared.
 409                  * The EEPROM will signal that the command has been completed
 410                  * by clearing bit 0 of the internal status register.  If it's
 411                  * not cleared within 'timeout', then error out.
 412                  */
 413                 while (timeout) {
 414                         e1000_shift_out_eec_bits(hw, NVM_RDSR_OPCODE_SPI,
 415                                                  hw->nvm.opcode_bits);
 416                         spi_stat_reg = (u8)e1000_shift_in_eec_bits(hw, 8);
 417                         if (!(spi_stat_reg & NVM_STATUS_RDY_SPI))
 418                                 break;
 419
 420                         usec_delay(5);
 421                         e1000_standby_nvm(hw);
 422                         timeout--;
 423                 }
 424
 425                 if (!timeout) {
 426                         DEBUGOUT("SPI NVM Status error\n");
 427                         return -E1000_ERR_NVM;
 428                 }
 429         }
 430
 431         return E1000_SUCCESS;
 432 }
 433
 434 /**
 435  *  e1000_read_nvm_spi - Read EEPROM's using SPI
 436  *  @hw: pointer to the HW structure
 437  *  @offset: offset of word in the EEPROM to read
 438  *  @words: number of words to read
 439  *  @data: word read from the EEPROM
 440  *
 441  *  Reads a 16 bit word from the EEPROM.
 442  **/
 443 s32 e1000_read_nvm_spi(struct e1000_hw *hw, u16 offset, u16 words, u16 *data)
 444 {
 445         struct e1000_nvm_info *nvm = &hw->nvm;
 446         u32 i = 0;
 447         s32 ret_val;
 448         u16 word_in;
 449         u8 read_opcode = NVM_READ_OPCODE_SPI;
 450
 451         DEBUGFUNC("e1000_read_nvm_spi");
 452
 453         /* A check for invalid values:  offset too large, too many words,
 454          * and not enough words.
 455          */
 456         if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) ||
 457             (words == 0)) {
 458                 DEBUGOUT("nvm parameter(s) out of bounds\n");
 459                 return -E1000_ERR_NVM;
 460         }
 461
 462         ret_val = nvm->ops.acquire(hw);
 463         if (ret_val)
 464                 return ret_val;
 465
 466         ret_val = e1000_ready_nvm_eeprom(hw);
 467         if (ret_val)
 468                 goto release;
 469
 470         e1000_standby_nvm(hw);
 471
 472         if ((nvm->address_bits == 8) && (offset >= 128))
 473                 read_opcode |= NVM_A8_OPCODE_SPI;
 474
 475         /* Send the READ command (opcode + addr) */
 476         e1000_shift_out_eec_bits(hw, read_opcode, nvm->opcode_bits);
 477         e1000_shift_out_eec_bits(hw, (u16)(offset*2), nvm->address_bits);
 478
 479         /* Read the data.  SPI NVMs increment the address with each byte
 480          * read and will roll over if reading beyond the end.  This allows
 481          * us to read the whole NVM from any offset
 482          */
 483         for (i = 0; i < words; i++) {
 484                 word_in = e1000_shift_in_eec_bits(hw, 16);
 485                 data[i] = (word_in >> 8) | (word_in << 8);
 486         }
 487
 488 release:
 489         nvm->ops.release(hw);
 490
 491         return ret_val;
 492 }
 493
 494 /**
 495  *  e1000_read_nvm_microwire - Reads EEPROM's using microwire
 496  *  @hw: pointer to the HW structure
 497  *  @offset: offset of word in the EEPROM to read
 498  *  @words: number of words to read
 499  *  @data: word read from the EEPROM
 500  *
 501  *  Reads a 16 bit word from the EEPROM.
 502  **/
 503 s32 e1000_read_nvm_microwire(struct e1000_hw *hw, u16 offset, u16 words,
 504                              u16 *data)
 505 {
 506         struct e1000_nvm_info *nvm = &hw->nvm;
 507         u32 i = 0;
 508         s32 ret_val;
 509         u8 read_opcode = NVM_READ_OPCODE_MICROWIRE;
 510
 511         DEBUGFUNC("e1000_read_nvm_microwire");
 512
 513         /* A check for invalid values:  offset too large, too many words,
 514          * and not enough words.
 515          */
 516         if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) ||
 517             (words == 0)) {
 518                 DEBUGOUT("nvm parameter(s) out of bounds\n");
 519                 return -E1000_ERR_NVM;
 520         }
 521
 522         ret_val = nvm->ops.acquire(hw);
 523         if (ret_val)
 524                 return ret_val;
 525
 526         ret_val = e1000_ready_nvm_eeprom(hw);
 527         if (ret_val)
 528                 goto release;
 529
 530         for (i = 0; i < words; i++) {
 531                 /* Send the READ command (opcode + addr) */
 532                 e1000_shift_out_eec_bits(hw, read_opcode, nvm->opcode_bits);
 533                 e1000_shift_out_eec_bits(hw, (u16)(offset + i),
 534                                         nvm->address_bits);
 535
 536                 /* Read the data.  For microwire, each word requires the
 537                  * overhead of setup and tear-down.
 538                  */
 539                 data[i] = e1000_shift_in_eec_bits(hw, 16);
 540                 e1000_standby_nvm(hw);
 541         }
 542
 543 release:
 544         nvm->ops.release(hw);
 545
 546         return ret_val;
 547 }
 548
 549 /**
 550  *  e1000_read_nvm_eerd - Reads EEPROM using EERD register
 551  *  @hw: pointer to the HW structure
 552  *  @offset: offset of word in the EEPROM to read
 553  *  @words: number of words to read
 554  *  @data: word read from the EEPROM
 555  *
 556  *  Reads a 16 bit word from the EEPROM using the EERD register.
 557  **/
 558 s32 e1000_read_nvm_eerd(struct e1000_hw *hw, u16 offset, u16 words, u16 *data)
 559 {
 560         struct e1000_nvm_info *nvm = &hw->nvm;
 561         u32 i, eerd = 0;
 562         s32 ret_val = E1000_SUCCESS;
 563
 564         DEBUGFUNC("e1000_read_nvm_eerd");
 565
 566         /* A check for invalid values:  offset too large, too many words,
 567          * too many words for the offset, and not enough words.
 568          */
 569         if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) ||
 570             (words == 0)) {
 571                 DEBUGOUT("nvm parameter(s) out of bounds\n");
 572                 return -E1000_ERR_NVM;
 573         }
 574
 575         for (i = 0; i < words; i++) {
 576                 eerd = ((offset+i) << E1000_NVM_RW_ADDR_SHIFT) +
 577                        E1000_NVM_RW_REG_START;
 578
 579                 E1000_WRITE_REG(hw, E1000_EERD, eerd);
 580                 ret_val = e1000_poll_eerd_eewr_done(hw, E1000_NVM_POLL_READ);
 581                 if (ret_val)
 582                         break;
 583
 584                 data[i] = (E1000_READ_REG(hw, E1000_EERD) >>
 585                            E1000_NVM_RW_REG_DATA);
 586         }
 587
 588         if (ret_val)
 589                 DEBUGOUT1("NVM read error: %d\n", ret_val);
 590
 591         return ret_val;
 592 }
 593
 594 /**
 595  *  e1000_write_nvm_spi - Write to EEPROM using SPI
 596  *  @hw: pointer to the HW structure
 597  *  @offset: offset within the EEPROM to be written to
 598  *  @words: number of words to write
 599  *  @data: 16 bit word(s) to be written to the EEPROM
 600  *
 601  *  Writes data to EEPROM at offset using SPI interface.
 602  *
 603  *  If e1000_update_nvm_checksum is not called after this function , the
 604  *  EEPROM will most likely contain an invalid checksum.
 605  **/
 606 s32 e1000_write_nvm_spi(struct e1000_hw *hw, u16 offset, u16 words, u16 *data)
 607 {
 608         struct e1000_nvm_info *nvm = &hw->nvm;
 609         s32 ret_val = -E1000_ERR_NVM;
 610         u16 widx = 0;
 611
 612         DEBUGFUNC("e1000_write_nvm_spi");
 613
 614         /* A check for invalid values:  offset too large, too many words,
 615          * and not enough words.
 616          */
 617         if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) ||
 618             (words == 0)) {
 619                 DEBUGOUT("nvm parameter(s) out of bounds\n");
 620                 return -E1000_ERR_NVM;
 621         }
 622
 623         while (widx < words) {
 624                 u8 write_opcode = NVM_WRITE_OPCODE_SPI;
 625
 626                 ret_val = nvm->ops.acquire(hw);
 627                 if (ret_val)
 628                         return ret_val;
 629
 630                 ret_val = e1000_ready_nvm_eeprom(hw);
 631                 if (ret_val) {
 632                         nvm->ops.release(hw);
 633                         return ret_val;
 634                 }
 635
 636                 e1000_standby_nvm(hw);
 637
 638                 /* Send the WRITE ENABLE command (8 bit opcode) */
 639                 e1000_shift_out_eec_bits(hw, NVM_WREN_OPCODE_SPI,
 640                                          nvm->opcode_bits);
 641
 642                 e1000_standby_nvm(hw);
 643
 644                 /* Some SPI eeproms use the 8th address bit embedded in the
 645                  * opcode
 646                  */
 647                 if ((nvm->address_bits == 8) && (offset >= 128))
 648                         write_opcode |= NVM_A8_OPCODE_SPI;
 649
 650                 /* Send the Write command (8-bit opcode + addr) */
 651                 e1000_shift_out_eec_bits(hw, write_opcode, nvm->opcode_bits);
 652                 e1000_shift_out_eec_bits(hw, (u16)((offset + widx) * 2),
 653                                          nvm->address_bits);
 654
 655                 /* Loop to allow for up to whole page write of eeprom */
 656                 while (widx < words) {
 657                         u16 word_out = data[widx];
 658                         word_out = (word_out >> 8) | (word_out << 8);
 659                         e1000_shift_out_eec_bits(hw, word_out, 16);
 660                         widx++;
 661
 662                         if ((((offset + widx) * 2) % nvm->page_size) == 0) {
 663                                 e1000_standby_nvm(hw);
 664                                 break;
 665                         }
 666                 }
 667                 msec_delay(10);
 668                 nvm->ops.release(hw);
 669         }
 670
 671         return ret_val;
 672 }
 673
 674 /**
 675  *  e1000_write_nvm_microwire - Writes EEPROM using microwire
 676  *  @hw: pointer to the HW structure
 677  *  @offset: offset within the EEPROM to be written to
 678  *  @words: number of words to write
 679  *  @data: 16 bit word(s) to be written to the EEPROM
 680  *
 681  *  Writes data to EEPROM at offset using microwire interface.
 682  *
 683  *  If e1000_update_nvm_checksum is not called after this function , the
 684  *  EEPROM will most likely contain an invalid checksum.
 685  **/
 686 s32 e1000_write_nvm_microwire(struct e1000_hw *hw, u16 offset, u16 words,
 687                               u16 *data)
 688 {
 689         struct e1000_nvm_info *nvm = &hw->nvm;
 690         s32  ret_val;
 691         u32 eecd;
 692         u16 words_written = 0;
 693         u16 widx = 0;
 694
 695         DEBUGFUNC("e1000_write_nvm_microwire");
 696
 697         /* A check for invalid values:  offset too large, too many words,
 698          * and not enough words.
 699          */
 700         if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) ||
 701             (words == 0)) {
 702                 DEBUGOUT("nvm parameter(s) out of bounds\n");
 703                 return -E1000_ERR_NVM;
 704         }
 705
 706         ret_val = nvm->ops.acquire(hw);
 707         if (ret_val)
 708                 return ret_val;
 709
 710         ret_val = e1000_ready_nvm_eeprom(hw);
 711         if (ret_val)
 712                 goto release;
 713
 714         e1000_shift_out_eec_bits(hw, NVM_EWEN_OPCODE_MICROWIRE,
 715                                  (u16)(nvm->opcode_bits + 2));
 716
 717         e1000_shift_out_eec_bits(hw, 0, (u16)(nvm->address_bits - 2));
 718
 719         e1000_standby_nvm(hw);
 720
 721         while (words_written < words) {
 722                 e1000_shift_out_eec_bits(hw, NVM_WRITE_OPCODE_MICROWIRE,
 723                                          nvm->opcode_bits);
 724
 725                 e1000_shift_out_eec_bits(hw, (u16)(offset + words_written),
 726                                          nvm->address_bits);
 727
 728                 e1000_shift_out_eec_bits(hw, data[words_written], 16);
 729
 730                 e1000_standby_nvm(hw);
 731
 732                 for (widx = 0; widx < 200; widx++) {
 733                         eecd = E1000_READ_REG(hw, E1000_EECD);
 734                         if (eecd & E1000_EECD_DO)
 735                                 break;
 736                         usec_delay(50);
 737                 }
 738
 739                 if (widx == 200) {
 740                         DEBUGOUT("NVM Write did not complete\n");
 741                         ret_val = -E1000_ERR_NVM;
 742                         goto release;
 743                 }
 744
 745                 e1000_standby_nvm(hw);
 746
 747                 words_written++;
 748         }
 749
 750         e1000_shift_out_eec_bits(hw, NVM_EWDS_OPCODE_MICROWIRE,
 751                                  (u16)(nvm->opcode_bits + 2));
 752
 753         e1000_shift_out_eec_bits(hw, 0, (u16)(nvm->address_bits - 2));
 754
 755 release:
 756         nvm->ops.release(hw);
 757
 758         return ret_val;
 759 }
 760
 761 /**
 762  *  e1000_read_pba_string_generic - Read device part number
 763  *  @hw: pointer to the HW structure
 764  *  @pba_num: pointer to device part number
 765  *  @pba_num_size: size of part number buffer
 766  *
 767  *  Reads the product board assembly (PBA) number from the EEPROM and stores
 768  *  the value in pba_num.
 769  **/
 770 s32 e1000_read_pba_string_generic(struct e1000_hw *hw, u8 *pba_num,
 771                                   u32 pba_num_size)
 772 {
 773         s32 ret_val;
 774         u16 nvm_data;
 775         u16 pba_ptr;
 776         u16 offset;
 777         u16 length;
 778
 779         DEBUGFUNC("e1000_read_pba_string_generic");
 780
 781         if ((hw->mac.type >= e1000_i210) &&
 782             !e1000_get_flash_presence_i210(hw)) {
 783                 DEBUGOUT("Flashless no PBA string\n");
 784                 return -E1000_ERR_NVM_PBA_SECTION;
 785         }
 786
 787         if (pba_num == NULL) {
 788                 DEBUGOUT("PBA string buffer was null\n");
 789                 return -E1000_ERR_INVALID_ARGUMENT;
 790         }
 791
 792         ret_val = hw->nvm.ops.read(hw, NVM_PBA_OFFSET_0, 1, &nvm_data);
 793         if (ret_val) {
 794                 DEBUGOUT("NVM Read Error\n");
 795                 return ret_val;
 796         }
 797
 798         ret_val = hw->nvm.ops.read(hw, NVM_PBA_OFFSET_1, 1, &pba_ptr);
 799         if (ret_val) {
 800                 DEBUGOUT("NVM Read Error\n");
 801                 return ret_val;
 802         }
 803
 804         /* if nvm_data is not ptr guard the PBA must be in legacy format which
 805          * means pba_ptr is actually our second data word for the PBA number
 806          * and we can decode it into an ascii string
 807          */
 808         if (nvm_data != NVM_PBA_PTR_GUARD) {
 809                 DEBUGOUT("NVM PBA number is not stored as string\n");
 810
 811                 /* make sure callers buffer is big enough to store the PBA */
 812                 if (pba_num_size < E1000_PBANUM_LENGTH) {
 813                         DEBUGOUT("PBA string buffer too small\n");
 814                         return E1000_ERR_NO_SPACE;
 815                 }
 816
 817                 /* extract hex string from data and pba_ptr */
 818                 pba_num[0] = (nvm_data >> 12) & 0xF;
 819                 pba_num[1] = (nvm_data >> 8) & 0xF;
 820                 pba_num[2] = (nvm_data >> 4) & 0xF;
 821                 pba_num[3] = nvm_data & 0xF;
 822                 pba_num[4] = (pba_ptr >> 12) & 0xF;
 823                 pba_num[5] = (pba_ptr >> 8) & 0xF;
 824                 pba_num[6] = '-';
 825                 pba_num[7] = 0;
 826                 pba_num[8] = (pba_ptr >> 4) & 0xF;
 827                 pba_num[9] = pba_ptr & 0xF;
 828
 829                 /* put a null character on the end of our string */
 830                 pba_num[10] = '\0';
 831
 832                 /* switch all the data but the '-' to hex char */
 833                 for (offset = 0; offset < 10; offset++) {
 834                         if (pba_num[offset] < 0xA)
 835                                 pba_num[offset] += '0';
 836                         else if (pba_num[offset] < 0x10)
 837                                 pba_num[offset] += 'A' - 0xA;
 838                 }
 839
 840                 return E1000_SUCCESS;
 841         }
 842
 843         ret_val = hw->nvm.ops.read(hw, pba_ptr, 1, &length);
 844         if (ret_val) {
 845                 DEBUGOUT("NVM Read Error\n");
 846                 return ret_val;
 847         }
 848
 849         if (length == 0xFFFF || length == 0) {
 850                 DEBUGOUT("NVM PBA number section invalid length\n");
 851                 return -E1000_ERR_NVM_PBA_SECTION;
 852         }
 853         /* check if pba_num buffer is big enough */
 854         if (pba_num_size < (((u32)length * 2) - 1)) {
 855                 DEBUGOUT("PBA string buffer too small\n");
 856                 return -E1000_ERR_NO_SPACE;
 857         }
 858
 859         /* trim pba length from start of string */
 860         pba_ptr++;
 861         length--;
 862
 863         for (offset = 0; offset < length; offset++) {
 864                 ret_val = hw->nvm.ops.read(hw, pba_ptr + offset, 1, &nvm_data);
 865                 if (ret_val) {
 866                         DEBUGOUT("NVM Read Error\n");
 867                         return ret_val;
 868                 }
 869                 pba_num[offset * 2] = (u8)(nvm_data >> 8);
 870                 pba_num[(offset * 2) + 1] = (u8)(nvm_data & 0xFF);
 871         }
 872         pba_num[offset * 2] = '\0';
 873
 874         return E1000_SUCCESS;
 875 }
 876
 877 /**
 878  *  e1000_read_pba_length_generic - Read device part number length
 879  *  @hw: pointer to the HW structure
 880  *  @pba_num_size: size of part number buffer
 881  *
 882  *  Reads the product board assembly (PBA) number length from the EEPROM and
 883  *  stores the value in pba_num_size.
 884  **/
 885 s32 e1000_read_pba_length_generic(struct e1000_hw *hw, u32 *pba_num_size)
 886 {
 887         s32 ret_val;
 888         u16 nvm_data;
 889         u16 pba_ptr;
 890         u16 length;
 891
 892         DEBUGFUNC("e1000_read_pba_length_generic");
 893
 894         if (pba_num_size == NULL) {
 895                 DEBUGOUT("PBA buffer size was null\n");
 896                 return -E1000_ERR_INVALID_ARGUMENT;
 897         }
 898
 899         ret_val = hw->nvm.ops.read(hw, NVM_PBA_OFFSET_0, 1, &nvm_data);
 900         if (ret_val) {
 901                 DEBUGOUT("NVM Read Error\n");
 902                 return ret_val;
 903         }
 904
 905         ret_val = hw->nvm.ops.read(hw, NVM_PBA_OFFSET_1, 1, &pba_ptr);
 906         if (ret_val) {
 907                 DEBUGOUT("NVM Read Error\n");
 908                 return ret_val;
 909         }
 910
 911          /* if data is not ptr guard the PBA must be in legacy format */
 912         if (nvm_data != NVM_PBA_PTR_GUARD) {
 913                 *pba_num_size = E1000_PBANUM_LENGTH;
 914                 return E1000_SUCCESS;
 915         }
 916
 917         ret_val = hw->nvm.ops.read(hw, pba_ptr, 1, &length);
 918         if (ret_val) {
 919                 DEBUGOUT("NVM Read Error\n");
 920                 return ret_val;
 921         }
 922
 923         if (length == 0xFFFF || length == 0) {
 924                 DEBUGOUT("NVM PBA number section invalid length\n");
 925                 return -E1000_ERR_NVM_PBA_SECTION;
 926         }
 927
 928         /* Convert from length in u16 values to u8 chars, add 1 for NULL,
 929          * and subtract 2 because length field is included in length.
 930          */
 931         *pba_num_size = ((u32)length * 2) - 1;
 932
 933         return E1000_SUCCESS;
 934 }
 935
 936 /**
 937  *  e1000_read_pba_num_generic - Read device part number
 938  *  @hw: pointer to the HW structure
 939  *  @pba_num: pointer to device part number
 940  *
 941  *  Reads the product board assembly (PBA) number from the EEPROM and stores
 942  *  the value in pba_num.
 943  **/
 944 s32 e1000_read_pba_num_generic(struct e1000_hw *hw, u32 *pba_num)
 945 {
 946         s32 ret_val;
 947         u16 nvm_data;
 948
 949         DEBUGFUNC("e1000_read_pba_num_generic");
 950
 951         ret_val = hw->nvm.ops.read(hw, NVM_PBA_OFFSET_0, 1, &nvm_data);
 952         if (ret_val) {
 953                 DEBUGOUT("NVM Read Error\n");
 954                 return ret_val;
 955         } else if (nvm_data == NVM_PBA_PTR_GUARD) {
 956                 DEBUGOUT("NVM Not Supported\n");
 957                 return -E1000_NOT_IMPLEMENTED;
 958         }
 959         *pba_num = (u32)(nvm_data << 16);
 960
 961         ret_val = hw->nvm.ops.read(hw, NVM_PBA_OFFSET_1, 1, &nvm_data);
 962         if (ret_val) {
 963                 DEBUGOUT("NVM Read Error\n");
 964                 return ret_val;
 965         }
 966         *pba_num |= nvm_data;
 967
 968         return E1000_SUCCESS;
 969 }
 970
 971
 972 /**
 973  *  e1000_read_pba_raw
 974  *  @hw: pointer to the HW structure
 975  *  @eeprom_buf: optional pointer to EEPROM image
 976  *  @eeprom_buf_size: size of EEPROM image in words
 977  *  @max_pba_block_size: PBA block size limit
 978  *  @pba: pointer to output PBA structure
 979  *
 980  *  Reads PBA from EEPROM image when eeprom_buf is not NULL.
 981  *  Reads PBA from physical EEPROM device when eeprom_buf is NULL.
 982  *
 983  **/
 984 s32 e1000_read_pba_raw(struct e1000_hw *hw, u16 *eeprom_buf,
 985                        u32 eeprom_buf_size, u16 max_pba_block_size,
 986                        struct e1000_pba *pba)
 987 {
 988         s32 ret_val;
 989         u16 pba_block_size;
 990
 991         if (pba == NULL)
 992                 return -E1000_ERR_PARAM;
 993
 994         if (eeprom_buf == NULL) {
 995                 ret_val = e1000_read_nvm(hw, NVM_PBA_OFFSET_0, 2,
 996                                          &pba->word[0]);
 997                 if (ret_val)
 998                         return ret_val;
 999         } else {
1000                 if (eeprom_buf_size > NVM_PBA_OFFSET_1) {
1001                         pba->word[0] = eeprom_buf[NVM_PBA_OFFSET_0];
1002                         pba->word[1] = eeprom_buf[NVM_PBA_OFFSET_1];
1003                 } else {
1004                         return -E1000_ERR_PARAM;
1005                 }
1006         }
1007
1008         if (pba->word[0] == NVM_PBA_PTR_GUARD) {
1009                 if (pba->pba_block == NULL)
1010                         return -E1000_ERR_PARAM;
1011
1012                 ret_val = e1000_get_pba_block_size(hw, eeprom_buf,
1013                                                    eeprom_buf_size,
1014                                                    &pba_block_size);
1015                 if (ret_val)
1016                         return ret_val;
1017
1018                 if (pba_block_size > max_pba_block_size)
1019                         return -E1000_ERR_PARAM;
1020
1021                 if (eeprom_buf == NULL) {
1022                         ret_val = e1000_read_nvm(hw, pba->word[1],
1023                                                  pba_block_size,
1024                                                  pba->pba_block);
1025                         if (ret_val)
1026                                 return ret_val;
1027                 } else {
1028                         if (eeprom_buf_size > (u32)(pba->word[1] +
1029                                               pba_block_size)) {
1030                                 memcpy(pba->pba_block,
1031                                        &eeprom_buf[pba->word[1]],
1032                                        pba_block_size * sizeof(u16));
1033                         } else {
1034                                 return -E1000_ERR_PARAM;
1035                         }
1036                 }
1037         }
1038
1039         return E1000_SUCCESS;
1040 }
1041
1042 /**
1043  *  e1000_write_pba_raw
1044  *  @hw: pointer to the HW structure
1045  *  @eeprom_buf: optional pointer to EEPROM image
1046  *  @eeprom_buf_size: size of EEPROM image in words
1047  *  @pba: pointer to PBA structure
1048  *
1049  *  Writes PBA to EEPROM image when eeprom_buf is not NULL.
1050  *  Writes PBA to physical EEPROM device when eeprom_buf is NULL.
1051  *
1052  **/
1053 s32 e1000_write_pba_raw(struct e1000_hw *hw, u16 *eeprom_buf,
1054                         u32 eeprom_buf_size, struct e1000_pba *pba)
1055 {
1056         s32 ret_val;
1057
1058         if (pba == NULL)
1059                 return -E1000_ERR_PARAM;
1060
1061         if (eeprom_buf == NULL) {
1062                 ret_val = e1000_write_nvm(hw, NVM_PBA_OFFSET_0, 2,
1063                                           &pba->word[0]);
1064                 if (ret_val)
1065                         return ret_val;
1066         } else {
1067                 if (eeprom_buf_size > NVM_PBA_OFFSET_1) {
1068                         eeprom_buf[NVM_PBA_OFFSET_0] = pba->word[0];
1069                         eeprom_buf[NVM_PBA_OFFSET_1] = pba->word[1];
1070                 } else {
1071                         return -E1000_ERR_PARAM;
1072                 }
1073         }
1074
1075         if (pba->word[0] == NVM_PBA_PTR_GUARD) {
1076                 if (pba->pba_block == NULL)
1077                         return -E1000_ERR_PARAM;
1078
1079                 if (eeprom_buf == NULL) {
1080                         ret_val = e1000_write_nvm(hw, pba->word[1],
1081                                                   pba->pba_block[0],
1082                                                   pba->pba_block);
1083                         if (ret_val)
1084                                 return ret_val;
1085                 } else {
1086                         if (eeprom_buf_size > (u32)(pba->word[1] +
1087                                               pba->pba_block[0])) {
1088                                 memcpy(&eeprom_buf[pba->word[1]],
1089                                        pba->pba_block,
1090                                        pba->pba_block[0] * sizeof(u16));
1091                         } else {
1092                                 return -E1000_ERR_PARAM;
1093                         }
1094                 }
1095         }
1096
1097         return E1000_SUCCESS;
1098 }
1099
1100 /**
1101  *  e1000_get_pba_block_size
1102  *  @hw: pointer to the HW structure
1103  *  @eeprom_buf: optional pointer to EEPROM image
1104  *  @eeprom_buf_size: size of EEPROM image in words
1105  *  @pba_data_size: pointer to output variable
1106  *
1107  *  Returns the size of the PBA block in words. Function operates on EEPROM
1108  *  image if the eeprom_buf pointer is not NULL otherwise it accesses physical
1109  *  EEPROM device.
1110  *
1111  **/
1112 s32 e1000_get_pba_block_size(struct e1000_hw *hw, u16 *eeprom_buf,
1113                              u32 eeprom_buf_size, u16 *pba_block_size)
1114 {
1115         s32 ret_val;
1116         u16 pba_word[2];
1117         u16 length;
1118
1119         DEBUGFUNC("e1000_get_pba_block_size");
1120
1121         if (eeprom_buf == NULL) {
1122                 ret_val = e1000_read_nvm(hw, NVM_PBA_OFFSET_0, 2, &pba_word[0]);
1123                 if (ret_val)
1124                         return ret_val;
1125         } else {
1126                 if (eeprom_buf_size > NVM_PBA_OFFSET_1) {
1127                         pba_word[0] = eeprom_buf[NVM_PBA_OFFSET_0];
1128                         pba_word[1] = eeprom_buf[NVM_PBA_OFFSET_1];
1129                 } else {
1130                         return -E1000_ERR_PARAM;
1131                 }
1132         }
1133
1134         if (pba_word[0] == NVM_PBA_PTR_GUARD) {
1135                 if (eeprom_buf == NULL) {
1136                         ret_val = e1000_read_nvm(hw, pba_word[1] + 0, 1,
1137                                                  &length);
1138                         if (ret_val)
1139                                 return ret_val;
1140                 } else {
1141                         if (eeprom_buf_size > pba_word[1])
1142                                 length = eeprom_buf[pba_word[1] + 0];
1143                         else
1144                                 return -E1000_ERR_PARAM;
1145                 }
1146
1147                 if (length == 0xFFFF || length == 0)
1148                         return -E1000_ERR_NVM_PBA_SECTION;
1149         } else {
1150                 /* PBA number in legacy format, there is no PBA Block. */
1151                 length = 0;
1152         }
1153
1154         if (pba_block_size != NULL)
1155                 *pba_block_size = length;
1156
1157         return E1000_SUCCESS;
1158 }
1159
1160 /**
1161  *  e1000_read_mac_addr_generic - Read device MAC address
1162  *  @hw: pointer to the HW structure
1163  *
1164  *  Reads the device MAC address from the EEPROM and stores the value.
1165  *  Since devices with two ports use the same EEPROM, we increment the
1166  *  last bit in the MAC address for the second port.
1167  **/
1168 s32 e1000_read_mac_addr_generic(struct e1000_hw *hw)
1169 {
1170         u32 rar_high;
1171         u32 rar_low;
1172         u16 i;
1173
1174         rar_high = E1000_READ_REG(hw, E1000_RAH(0));
1175         rar_low = E1000_READ_REG(hw, E1000_RAL(0));
1176
1177         for (i = 0; i < E1000_RAL_MAC_ADDR_LEN; i++)
1178                 hw->mac.perm_addr[i] = (u8)(rar_low >> (i*8));
1179
1180         for (i = 0; i < E1000_RAH_MAC_ADDR_LEN; i++)
1181                 hw->mac.perm_addr[i+4] = (u8)(rar_high >> (i*8));
1182
1183         for (i = 0; i < ETH_ADDR_LEN; i++)
1184                 hw->mac.addr[i] = hw->mac.perm_addr[i];
1185
1186         return E1000_SUCCESS;
1187 }
1188
1189 /**
1190  *  e1000_validate_nvm_checksum_generic - Validate EEPROM checksum
1191  *  @hw: pointer to the HW structure
1192  *
1193  *  Calculates the EEPROM checksum by reading/adding each word of the EEPROM
1194  *  and then verifies that the sum of the EEPROM is equal to 0xBABA.
1195  **/
1196 s32 e1000_validate_nvm_checksum_generic(struct e1000_hw *hw)
1197 {
1198         s32 ret_val;
1199         u16 checksum = 0;
1200         u16 i, nvm_data;
1201
1202         DEBUGFUNC("e1000_validate_nvm_checksum_generic");
1203
1204         for (i = 0; i < (NVM_CHECKSUM_REG + 1); i++) {
1205                 ret_val = hw->nvm.ops.read(hw, i, 1, &nvm_data);
1206                 if (ret_val) {
1207                         DEBUGOUT("NVM Read Error\n");
1208                         return ret_val;
1209                 }
1210                 checksum += nvm_data;
1211         }
1212
1213         if (checksum != (u16) NVM_SUM) {
1214                 DEBUGOUT("NVM Checksum Invalid\n");
1215                 return -E1000_ERR_NVM;
1216         }
1217
1218         return E1000_SUCCESS;
1219 }
1220
1221 /**
1222  *  e1000_update_nvm_checksum_generic - Update EEPROM checksum
1223  *  @hw: pointer to the HW structure
1224  *
1225  *  Updates the EEPROM checksum by reading/adding each word of the EEPROM
1226  *  up to the checksum.  Then calculates the EEPROM checksum and writes the
1227  *  value to the EEPROM.
1228  **/
1229 s32 e1000_update_nvm_checksum_generic(struct e1000_hw *hw)
1230 {
1231         s32 ret_val;
1232         u16 checksum = 0;
1233         u16 i, nvm_data;
1234
1235         DEBUGFUNC("e1000_update_nvm_checksum");
1236
1237         for (i = 0; i < NVM_CHECKSUM_REG; i++) {
1238                 ret_val = hw->nvm.ops.read(hw, i, 1, &nvm_data);
1239                 if (ret_val) {
1240                         DEBUGOUT("NVM Read Error while updating checksum.\n");
1241                         return ret_val;
1242                 }
1243                 checksum += nvm_data;
1244         }
1245         checksum = (u16) NVM_SUM - checksum;
1246         ret_val = hw->nvm.ops.write(hw, NVM_CHECKSUM_REG, 1, &checksum);
1247         if (ret_val)
1248                 DEBUGOUT("NVM Write Error while updating checksum.\n");
1249
1250         return ret_val;
1251 }
1252
1253 /**
1254  *  e1000_reload_nvm_generic - Reloads EEPROM
1255  *  @hw: pointer to the HW structure
1256  *
1257  *  Reloads the EEPROM by setting the "Reinitialize from EEPROM" bit in the
1258  *  extended control register.
1259  **/
1260 STATIC void e1000_reload_nvm_generic(struct e1000_hw *hw)
1261 {
1262         u32 ctrl_ext;
1263
1264         DEBUGFUNC("e1000_reload_nvm_generic");
1265
1266         usec_delay(10);
1267         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
1268         ctrl_ext |= E1000_CTRL_EXT_EE_RST;
1269         E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
1270         E1000_WRITE_FLUSH(hw);
1271 }
1272
1273 /**
1274  *  e1000_get_fw_version - Get firmware version information
1275  *  @hw: pointer to the HW structure
1276  *  @fw_vers: pointer to output version structure
1277  *
1278  *  unsupported/not present features return 0 in version structure
1279  **/
1280 void e1000_get_fw_version(struct e1000_hw *hw, struct e1000_fw_version *fw_vers)
1281 {
1282         u16 eeprom_verh, eeprom_verl, etrack_test, fw_version;
1283         u8 q, hval, rem, result;
1284         u16 comb_verh, comb_verl, comb_offset;
1285
1286         memset(fw_vers, 0, sizeof(struct e1000_fw_version));
1287
1288         /* basic eeprom version numbers, bits used vary by part and by tool
1289          * used to create the nvm images */
1290         /* Check which data format we have */
1291         switch (hw->mac.type) {
1292         case e1000_i211:
1293                 e1000_read_invm_version(hw, fw_vers);
1294                 return;
1295         case e1000_82575:
1296         case e1000_82576:
1297         case e1000_82580:
1298                 hw->nvm.ops.read(hw, NVM_ETRACK_HIWORD, 1, &etrack_test);
1299                 /* Use this format, unless EETRACK ID exists,
1300                  * then use alternate format
1301                  */
1302                 if ((etrack_test &  NVM_MAJOR_MASK) != NVM_ETRACK_VALID) {
1303                         hw->nvm.ops.read(hw, NVM_VERSION, 1, &fw_version);
1304                         fw_vers->eep_major = (fw_version & NVM_MAJOR_MASK)
1305                                               >> NVM_MAJOR_SHIFT;
1306                         fw_vers->eep_minor = (fw_version & NVM_MINOR_MASK)
1307                                               >> NVM_MINOR_SHIFT;
1308                         fw_vers->eep_build = (fw_version & NVM_IMAGE_ID_MASK);
1309                         goto etrack_id;
1310                 }
1311                 break;
1312         case e1000_i210:
1313                 if (!(e1000_get_flash_presence_i210(hw))) {
1314                         e1000_read_invm_version(hw, fw_vers);
1315                         return;
1316                 }
1317                 /* fall through */
1318         case e1000_i350:
1319                 hw->nvm.ops.read(hw, NVM_ETRACK_HIWORD, 1, &etrack_test);
1320                 /* find combo image version */
1321                 hw->nvm.ops.read(hw, NVM_COMB_VER_PTR, 1, &comb_offset);
1322                 if ((comb_offset != 0x0) &&
1323                     (comb_offset != NVM_VER_INVALID)) {
1324
1325                         hw->nvm.ops.read(hw, (NVM_COMB_VER_OFF + comb_offset
1326                                          + 1), 1, &comb_verh);
1327                         hw->nvm.ops.read(hw, (NVM_COMB_VER_OFF + comb_offset),
1328                                          1, &comb_verl);
1329
1330                         /* get Option Rom version if it exists and is valid */
1331                         if ((comb_verh && comb_verl) &&
1332                             ((comb_verh != NVM_VER_INVALID) &&
1333                              (comb_verl != NVM_VER_INVALID))) {
1334
1335                                 fw_vers->or_valid = true;
1336                                 fw_vers->or_major =
1337                                         comb_verl >> NVM_COMB_VER_SHFT;
1338                                 fw_vers->or_build =
1339                                         (comb_verl << NVM_COMB_VER_SHFT)
1340                                         | (comb_verh >> NVM_COMB_VER_SHFT);
1341                                 fw_vers->or_patch =
1342                                         comb_verh & NVM_COMB_VER_MASK;
1343                         }
1344                 }
1345                 break;
1346         default:
1347                 hw->nvm.ops.read(hw, NVM_ETRACK_HIWORD, 1, &etrack_test);
1348                 return;
1349         }
1350         hw->nvm.ops.read(hw, NVM_VERSION, 1, &fw_version);
1351         fw_vers->eep_major = (fw_version & NVM_MAJOR_MASK)
1352                               >> NVM_MAJOR_SHIFT;
1353
1354         /* check for old style version format in newer images*/
1355         if ((fw_version & NVM_NEW_DEC_MASK) == 0x0) {
1356                 eeprom_verl = (fw_version & NVM_COMB_VER_MASK);
1357         } else {
1358                 eeprom_verl = (fw_version & NVM_MINOR_MASK)
1359                                 >> NVM_MINOR_SHIFT;
1360         }
1361         /* Convert minor value to hex before assigning to output struct
1362          * Val to be converted will not be higher than 99, per tool output
1363          */
1364         q = eeprom_verl / NVM_HEX_CONV;
1365         hval = q * NVM_HEX_TENS;
1366         rem = eeprom_verl % NVM_HEX_CONV;
1367         result = hval + rem;
1368         fw_vers->eep_minor = result;
1369
1370 etrack_id:
1371         if ((etrack_test &  NVM_MAJOR_MASK) == NVM_ETRACK_VALID) {
1372                 hw->nvm.ops.read(hw, NVM_ETRACK_WORD, 1, &eeprom_verl);
1373                 hw->nvm.ops.read(hw, (NVM_ETRACK_WORD + 1), 1, &eeprom_verh);
1374                 fw_vers->etrack_id = (eeprom_verh << NVM_ETRACK_SHIFT)
1375                         | eeprom_verl;
1376         } else if ((etrack_test & NVM_ETRACK_VALID) == 0) {
1377                 hw->nvm.ops.read(hw, NVM_ETRACK_WORD, 1, &eeprom_verh);
1378                 hw->nvm.ops.read(hw, (NVM_ETRACK_WORD + 1), 1, &eeprom_verl);
1379                 fw_vers->etrack_id = (eeprom_verh << NVM_ETRACK_SHIFT) |
1380                                      eeprom_verl;
1381         }
1382 }
1383
1384