drivers/net/e1000/em_ethdev.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2010-2016 Intel Corporation
   3  */
   4
   5 #include <sys/queue.h>
   6 #include <stdio.h>
   7 #include <errno.h>
   8 #include <stdint.h>
   9 #include <stdarg.h>
  10
  11 #include <rte_common.h>
  12 #include <rte_interrupts.h>
  13 #include <rte_byteorder.h>
  14 #include <rte_debug.h>
  15 #include <rte_pci.h>
  16 #include <rte_bus_pci.h>
  17 #include <rte_ether.h>
  18 #include <rte_ethdev_driver.h>
  19 #include <rte_ethdev_pci.h>
  20 #include <rte_memory.h>
  21 #include <rte_eal.h>
  22 #include <rte_malloc.h>
  23 #include <rte_dev.h>
  24
  25 #include "e1000_logs.h"
  26 #include "base/e1000_api.h"
  27 #include "e1000_ethdev.h"
  28
  29 #define EM_EIAC                 0x000DC
  30
  31 #define PMD_ROUNDUP(x,y)        (((x) + (y) - 1)/(y) * (y))
  32
  33
  34 static int eth_em_configure(struct rte_eth_dev *dev);
  35 static int eth_em_start(struct rte_eth_dev *dev);
  36 static void eth_em_stop(struct rte_eth_dev *dev);
  37 static void eth_em_close(struct rte_eth_dev *dev);
  38 static void eth_em_promiscuous_enable(struct rte_eth_dev *dev);
  39 static void eth_em_promiscuous_disable(struct rte_eth_dev *dev);
  40 static void eth_em_allmulticast_enable(struct rte_eth_dev *dev);
  41 static void eth_em_allmulticast_disable(struct rte_eth_dev *dev);
  42 static int eth_em_link_update(struct rte_eth_dev *dev,
  43                                 int wait_to_complete);
  44 static int eth_em_stats_get(struct rte_eth_dev *dev,
  45                                 struct rte_eth_stats *rte_stats);
  46 static void eth_em_stats_reset(struct rte_eth_dev *dev);
  47 static void eth_em_infos_get(struct rte_eth_dev *dev,
  48                                 struct rte_eth_dev_info *dev_info);
  49 static int eth_em_flow_ctrl_get(struct rte_eth_dev *dev,
  50                                 struct rte_eth_fc_conf *fc_conf);
  51 static int eth_em_flow_ctrl_set(struct rte_eth_dev *dev,
  52                                 struct rte_eth_fc_conf *fc_conf);
  53 static int eth_em_interrupt_setup(struct rte_eth_dev *dev);
  54 static int eth_em_rxq_interrupt_setup(struct rte_eth_dev *dev);
  55 static int eth_em_interrupt_get_status(struct rte_eth_dev *dev);
  56 static int eth_em_interrupt_action(struct rte_eth_dev *dev,
  57                                    struct rte_intr_handle *handle);
  58 static void eth_em_interrupt_handler(void *param);
  59
  60 static int em_hw_init(struct e1000_hw *hw);
  61 static int em_hardware_init(struct e1000_hw *hw);
  62 static void em_hw_control_acquire(struct e1000_hw *hw);
  63 static void em_hw_control_release(struct e1000_hw *hw);
  64 static void em_init_manageability(struct e1000_hw *hw);
  65 static void em_release_manageability(struct e1000_hw *hw);
  66
  67 static int eth_em_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
  68
  69 static int eth_em_vlan_filter_set(struct rte_eth_dev *dev,
  70                 uint16_t vlan_id, int on);
  71 static int eth_em_vlan_offload_set(struct rte_eth_dev *dev, int mask);
  72 static void em_vlan_hw_filter_enable(struct rte_eth_dev *dev);
  73 static void em_vlan_hw_filter_disable(struct rte_eth_dev *dev);
  74 static void em_vlan_hw_strip_enable(struct rte_eth_dev *dev);
  75 static void em_vlan_hw_strip_disable(struct rte_eth_dev *dev);
  76
  77 /*
  78 static void eth_em_vlan_filter_set(struct rte_eth_dev *dev,
  79                                         uint16_t vlan_id, int on);
  80 */
  81
  82 static int eth_em_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id);
  83 static int eth_em_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id);
  84 static void em_lsc_intr_disable(struct e1000_hw *hw);
  85 static void em_rxq_intr_enable(struct e1000_hw *hw);
  86 static void em_rxq_intr_disable(struct e1000_hw *hw);
  87
  88 static int eth_em_led_on(struct rte_eth_dev *dev);
  89 static int eth_em_led_off(struct rte_eth_dev *dev);
  90
  91 static int em_get_rx_buffer_size(struct e1000_hw *hw);
  92 static int eth_em_rar_set(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
  93                           uint32_t index, uint32_t pool);
  94 static void eth_em_rar_clear(struct rte_eth_dev *dev, uint32_t index);
  95 static int eth_em_default_mac_addr_set(struct rte_eth_dev *dev,
  96                                          struct ether_addr *addr);
  97
  98 static int eth_em_set_mc_addr_list(struct rte_eth_dev *dev,
  99                                    struct ether_addr *mc_addr_set,
 100                                    uint32_t nb_mc_addr);
 101
 102 #define EM_FC_PAUSE_TIME 0x0680
 103 #define EM_LINK_UPDATE_CHECK_TIMEOUT  90  /* 9s */
 104 #define EM_LINK_UPDATE_CHECK_INTERVAL 100 /* ms */
 105
 106 static enum e1000_fc_mode em_fc_setting = e1000_fc_full;
 107
 108 /*
 109  * The set of PCI devices this driver supports
 110  */
 111 static const struct rte_pci_id pci_id_em_map[] = {
 112         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82540EM) },
 113         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82545EM_COPPER) },
 114         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82545EM_FIBER) },
 115         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82546EB_COPPER) },
 116         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82546EB_FIBER) },
 117         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82546EB_QUAD_COPPER) },
 118         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82571EB_COPPER) },
 119         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82571EB_FIBER) },
 120         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82571EB_SERDES) },
 121         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82571EB_SERDES_DUAL) },
 122         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82571EB_SERDES_QUAD) },
 123         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82571EB_QUAD_COPPER) },
 124         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82571PT_QUAD_COPPER) },
 125         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82571EB_QUAD_FIBER) },
 126         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82571EB_QUAD_COPPER_LP) },
 127         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82572EI_COPPER) },
 128         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82572EI_FIBER) },
 129         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82572EI_SERDES) },
 130         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82572EI) },
 131         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82573L) },
 132         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82574L) },
 133         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82574LA) },
 134         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82583V) },
 135         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH2_LV_LM) },
 136         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_LPT_I217_LM) },
 137         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_LPT_I217_V) },
 138         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_LPTLP_I218_LM) },
 139         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_LPTLP_I218_V) },
 140         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_I218_LM2) },
 141         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_I218_V2) },
 142         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_I218_LM3) },
 143         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_I218_V3) },
 144         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_SPT_I219_LM) },
 145         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_SPT_I219_V) },
 146         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_SPT_I219_LM2) },
 147         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_SPT_I219_V2) },
 148         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_LBG_I219_LM3) },
 149         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_SPT_I219_LM4) },
 150         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_SPT_I219_V4) },
 151         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_SPT_I219_LM5) },
 152         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_SPT_I219_V5) },
 153         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_CNP_I219_LM6) },
 154         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_CNP_I219_V6) },
 155         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_CNP_I219_LM7) },
 156         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_CNP_I219_V7) },
 157         { .vendor_id = 0, /* sentinel */ },
 158 };
 159
 160 static const struct eth_dev_ops eth_em_ops = {
 161         .dev_configure        = eth_em_configure,
 162         .dev_start            = eth_em_start,
 163         .dev_stop             = eth_em_stop,
 164         .dev_close            = eth_em_close,
 165         .promiscuous_enable   = eth_em_promiscuous_enable,
 166         .promiscuous_disable  = eth_em_promiscuous_disable,
 167         .allmulticast_enable  = eth_em_allmulticast_enable,
 168         .allmulticast_disable = eth_em_allmulticast_disable,
 169         .link_update          = eth_em_link_update,
 170         .stats_get            = eth_em_stats_get,
 171         .stats_reset          = eth_em_stats_reset,
 172         .dev_infos_get        = eth_em_infos_get,
 173         .mtu_set              = eth_em_mtu_set,
 174         .vlan_filter_set      = eth_em_vlan_filter_set,
 175         .vlan_offload_set     = eth_em_vlan_offload_set,
 176         .rx_queue_setup       = eth_em_rx_queue_setup,
 177         .rx_queue_release     = eth_em_rx_queue_release,
 178         .rx_queue_count       = eth_em_rx_queue_count,
 179         .rx_descriptor_done   = eth_em_rx_descriptor_done,
 180         .rx_descriptor_status = eth_em_rx_descriptor_status,
 181         .tx_descriptor_status = eth_em_tx_descriptor_status,
 182         .tx_queue_setup       = eth_em_tx_queue_setup,
 183         .tx_queue_release     = eth_em_tx_queue_release,
 184         .rx_queue_intr_enable = eth_em_rx_queue_intr_enable,
 185         .rx_queue_intr_disable = eth_em_rx_queue_intr_disable,
 186         .dev_led_on           = eth_em_led_on,
 187         .dev_led_off          = eth_em_led_off,
 188         .flow_ctrl_get        = eth_em_flow_ctrl_get,
 189         .flow_ctrl_set        = eth_em_flow_ctrl_set,
 190         .mac_addr_set         = eth_em_default_mac_addr_set,
 191         .mac_addr_add         = eth_em_rar_set,
 192         .mac_addr_remove      = eth_em_rar_clear,
 193         .set_mc_addr_list     = eth_em_set_mc_addr_list,
 194         .rxq_info_get         = em_rxq_info_get,
 195         .txq_info_get         = em_txq_info_get,
 196 };
 197
 198
 199 /**
 200  *  eth_em_dev_is_ich8 - Check for ICH8 device
 201  *  @hw: pointer to the HW structure
 202  *
 203  *  return TRUE for ICH8, otherwise FALSE
 204  **/
 205 static bool
 206 eth_em_dev_is_ich8(struct e1000_hw *hw)
 207 {
 208         DEBUGFUNC("eth_em_dev_is_ich8");
 209
 210         switch (hw->device_id) {
 211         case E1000_DEV_ID_PCH2_LV_LM:
 212         case E1000_DEV_ID_PCH_LPT_I217_LM:
 213         case E1000_DEV_ID_PCH_LPT_I217_V:
 214         case E1000_DEV_ID_PCH_LPTLP_I218_LM:
 215         case E1000_DEV_ID_PCH_LPTLP_I218_V:
 216         case E1000_DEV_ID_PCH_I218_V2:
 217         case E1000_DEV_ID_PCH_I218_LM2:
 218         case E1000_DEV_ID_PCH_I218_V3:
 219         case E1000_DEV_ID_PCH_I218_LM3:
 220         case E1000_DEV_ID_PCH_SPT_I219_LM:
 221         case E1000_DEV_ID_PCH_SPT_I219_V:
 222         case E1000_DEV_ID_PCH_SPT_I219_LM2:
 223         case E1000_DEV_ID_PCH_SPT_I219_V2:
 224         case E1000_DEV_ID_PCH_LBG_I219_LM3:
 225         case E1000_DEV_ID_PCH_SPT_I219_LM4:
 226         case E1000_DEV_ID_PCH_SPT_I219_V4:
 227         case E1000_DEV_ID_PCH_SPT_I219_LM5:
 228         case E1000_DEV_ID_PCH_SPT_I219_V5:
 229         case E1000_DEV_ID_PCH_CNP_I219_LM6:
 230         case E1000_DEV_ID_PCH_CNP_I219_V6:
 231         case E1000_DEV_ID_PCH_CNP_I219_LM7:
 232         case E1000_DEV_ID_PCH_CNP_I219_V7:
 233                 return 1;
 234         default:
 235                 return 0;
 236         }
 237 }
 238
 239 static int
 240 eth_em_dev_init(struct rte_eth_dev *eth_dev)
 241 {
 242         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
 243         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
 244         struct e1000_adapter *adapter =
 245                 E1000_DEV_PRIVATE(eth_dev->data->dev_private);
 246         struct e1000_hw *hw =
 247                 E1000_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 248         struct e1000_vfta * shadow_vfta =
 249                 E1000_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
 250
 251         eth_dev->dev_ops = &eth_em_ops;
 252         eth_dev->rx_pkt_burst = (eth_rx_burst_t)&eth_em_recv_pkts;
 253         eth_dev->tx_pkt_burst = (eth_tx_burst_t)&eth_em_xmit_pkts;
 254         eth_dev->tx_pkt_prepare = (eth_tx_prep_t)&eth_em_prep_pkts;
 255
 256         /* for secondary processes, we don't initialise any further as primary
 257          * has already done this work. Only check we don't need a different
 258          * RX function */
 259         if (rte_eal_process_type() != RTE_PROC_PRIMARY){
 260                 if (eth_dev->data->scattered_rx)
 261                         eth_dev->rx_pkt_burst =
 262                                 (eth_rx_burst_t)&eth_em_recv_scattered_pkts;
 263                 return 0;
 264         }
 265
 266         rte_eth_copy_pci_info(eth_dev, pci_dev);
 267
 268         hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
 269         hw->device_id = pci_dev->id.device_id;
 270         adapter->stopped = 0;
 271
 272         /* For ICH8 support we'll need to map the flash memory BAR */
 273         if (eth_em_dev_is_ich8(hw))
 274                 hw->flash_address = (void *)pci_dev->mem_resource[1].addr;
 275
 276         if (e1000_setup_init_funcs(hw, TRUE) != E1000_SUCCESS ||
 277                         em_hw_init(hw) != 0) {
 278                 PMD_INIT_LOG(ERR, "port_id %d vendorID=0x%x deviceID=0x%x: "
 279                         "failed to init HW",
 280                         eth_dev->data->port_id, pci_dev->id.vendor_id,
 281                         pci_dev->id.device_id);
 282                 return -ENODEV;
 283         }
 284
 285         /* Allocate memory for storing MAC addresses */
 286         eth_dev->data->mac_addrs = rte_zmalloc("e1000", ETHER_ADDR_LEN *
 287                         hw->mac.rar_entry_count, 0);
 288         if (eth_dev->data->mac_addrs == NULL) {
 289                 PMD_INIT_LOG(ERR, "Failed to allocate %d bytes needed to "
 290                         "store MAC addresses",
 291                         ETHER_ADDR_LEN * hw->mac.rar_entry_count);
 292                 return -ENOMEM;
 293         }
 294
 295         /* Copy the permanent MAC address */
 296         ether_addr_copy((struct ether_addr *) hw->mac.addr,
 297                 eth_dev->data->mac_addrs);
 298
 299         /* initialize the vfta */
 300         memset(shadow_vfta, 0, sizeof(*shadow_vfta));
 301
 302         PMD_INIT_LOG(DEBUG, "port_id %d vendorID=0x%x deviceID=0x%x",
 303                      eth_dev->data->port_id, pci_dev->id.vendor_id,
 304                      pci_dev->id.device_id);
 305
 306         rte_intr_callback_register(intr_handle,
 307                                    eth_em_interrupt_handler, eth_dev);
 308
 309         return 0;
 310 }
 311
 312 static int
 313 eth_em_dev_uninit(struct rte_eth_dev *eth_dev)
 314 {
 315         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
 316         struct e1000_adapter *adapter =
 317                 E1000_DEV_PRIVATE(eth_dev->data->dev_private);
 318         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
 319
 320         PMD_INIT_FUNC_TRACE();
 321
 322         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
 323                 return -EPERM;
 324
 325         if (adapter->stopped == 0)
 326                 eth_em_close(eth_dev);
 327
 328         eth_dev->dev_ops = NULL;
 329         eth_dev->rx_pkt_burst = NULL;
 330         eth_dev->tx_pkt_burst = NULL;
 331
 332         rte_free(eth_dev->data->mac_addrs);
 333         eth_dev->data->mac_addrs = NULL;
 334
 335         /* disable uio intr before callback unregister */
 336         rte_intr_disable(intr_handle);
 337         rte_intr_callback_unregister(intr_handle,
 338                                      eth_em_interrupt_handler, eth_dev);
 339
 340         return 0;
 341 }
 342
 343 static int eth_em_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
 344         struct rte_pci_device *pci_dev)
 345 {
 346         return rte_eth_dev_pci_generic_probe(pci_dev,
 347                 sizeof(struct e1000_adapter), eth_em_dev_init);
 348 }
 349
 350 static int eth_em_pci_remove(struct rte_pci_device *pci_dev)
 351 {
 352         return rte_eth_dev_pci_generic_remove(pci_dev, eth_em_dev_uninit);
 353 }
 354
 355 static struct rte_pci_driver rte_em_pmd = {
 356         .id_table = pci_id_em_map,
 357         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC |
 358                      RTE_PCI_DRV_IOVA_AS_VA,
 359         .probe = eth_em_pci_probe,
 360         .remove = eth_em_pci_remove,
 361 };
 362
 363 static int
 364 em_hw_init(struct e1000_hw *hw)
 365 {
 366         int diag;
 367
 368         diag = hw->mac.ops.init_params(hw);
 369         if (diag != 0) {
 370                 PMD_INIT_LOG(ERR, "MAC Initialization Error");
 371                 return diag;
 372         }
 373         diag = hw->nvm.ops.init_params(hw);
 374         if (diag != 0) {
 375                 PMD_INIT_LOG(ERR, "NVM Initialization Error");
 376                 return diag;
 377         }
 378         diag = hw->phy.ops.init_params(hw);
 379         if (diag != 0) {
 380                 PMD_INIT_LOG(ERR, "PHY Initialization Error");
 381                 return diag;
 382         }
 383         (void) e1000_get_bus_info(hw);
 384
 385         hw->mac.autoneg = 1;
 386         hw->phy.autoneg_wait_to_complete = 0;
 387         hw->phy.autoneg_advertised = E1000_ALL_SPEED_DUPLEX;
 388
 389         e1000_init_script_state_82541(hw, TRUE);
 390         e1000_set_tbi_compatibility_82543(hw, TRUE);
 391
 392         /* Copper options */
 393         if (hw->phy.media_type == e1000_media_type_copper) {
 394                 hw->phy.mdix = 0; /* AUTO_ALL_MODES */
 395                 hw->phy.disable_polarity_correction = 0;
 396                 hw->phy.ms_type = e1000_ms_hw_default;
 397         }
 398
 399         /*
 400          * Start from a known state, this is important in reading the nvm
 401          * and mac from that.
 402          */
 403         e1000_reset_hw(hw);
 404
 405         /* Make sure we have a good EEPROM before we read from it */
 406         if (e1000_validate_nvm_checksum(hw) < 0) {
 407                 /*
 408                  * Some PCI-E parts fail the first check due to
 409                  * the link being in sleep state, call it again,
 410                  * if it fails a second time its a real issue.
 411                  */
 412                 diag = e1000_validate_nvm_checksum(hw);
 413                 if (diag < 0) {
 414                         PMD_INIT_LOG(ERR, "EEPROM checksum invalid");
 415                         goto error;
 416                 }
 417         }
 418
 419         /* Read the permanent MAC address out of the EEPROM */
 420         diag = e1000_read_mac_addr(hw);
 421         if (diag != 0) {
 422                 PMD_INIT_LOG(ERR, "EEPROM error while reading MAC address");
 423                 goto error;
 424         }
 425
 426         /* Now initialize the hardware */
 427         diag = em_hardware_init(hw);
 428         if (diag != 0) {
 429                 PMD_INIT_LOG(ERR, "Hardware initialization failed");
 430                 goto error;
 431         }
 432
 433         hw->mac.get_link_status = 1;
 434
 435         /* Indicate SOL/IDER usage */
 436         diag = e1000_check_reset_block(hw);
 437         if (diag < 0) {
 438                 PMD_INIT_LOG(ERR, "PHY reset is blocked due to "
 439                         "SOL/IDER session");
 440         }
 441         return 0;
 442
 443 error:
 444         em_hw_control_release(hw);
 445         return diag;
 446 }
 447
 448 static int
 449 eth_em_configure(struct rte_eth_dev *dev)
 450 {
 451         struct e1000_interrupt *intr =
 452                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
 453
 454         PMD_INIT_FUNC_TRACE();
 455         intr->flags |= E1000_FLAG_NEED_LINK_UPDATE;
 456
 457         PMD_INIT_FUNC_TRACE();
 458
 459         return 0;
 460 }
 461
 462 static void
 463 em_set_pba(struct e1000_hw *hw)
 464 {
 465         uint32_t pba;
 466
 467         /*
 468          * Packet Buffer Allocation (PBA)
 469          * Writing PBA sets the receive portion of the buffer
 470          * the remainder is used for the transmit buffer.
 471          * Devices before the 82547 had a Packet Buffer of 64K.
 472          * After the 82547 the buffer was reduced to 40K.
 473          */
 474         switch (hw->mac.type) {
 475                 case e1000_82547:
 476                 case e1000_82547_rev_2:
 477                 /* 82547: Total Packet Buffer is 40K */
 478                         pba = E1000_PBA_22K; /* 22K for Rx, 18K for Tx */
 479                         break;
 480                 case e1000_82571:
 481                 case e1000_82572:
 482                 case e1000_80003es2lan:
 483                         pba = E1000_PBA_32K; /* 32K for Rx, 16K for Tx */
 484                         break;
 485                 case e1000_82573: /* 82573: Total Packet Buffer is 32K */
 486                         pba = E1000_PBA_12K; /* 12K for Rx, 20K for Tx */
 487                         break;
 488                 case e1000_82574:
 489                 case e1000_82583:
 490                         pba = E1000_PBA_20K; /* 20K for Rx, 20K for Tx */
 491                         break;
 492                 case e1000_ich8lan:
 493                         pba = E1000_PBA_8K;
 494                         break;
 495                 case e1000_ich9lan:
 496                 case e1000_ich10lan:
 497                         pba = E1000_PBA_10K;
 498                         break;
 499                 case e1000_pchlan:
 500                 case e1000_pch2lan:
 501                 case e1000_pch_lpt:
 502                 case e1000_pch_spt:
 503                 case e1000_pch_cnp:
 504                         pba = E1000_PBA_26K;
 505                         break;
 506                 default:
 507                         pba = E1000_PBA_40K; /* 40K for Rx, 24K for Tx */
 508         }
 509
 510         E1000_WRITE_REG(hw, E1000_PBA, pba);
 511 }
 512
 513 static void
 514 eth_em_rxtx_control(struct rte_eth_dev *dev,
 515                     bool enable)
 516 {
 517         struct e1000_hw *hw =
 518                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 519         uint32_t tctl, rctl;
 520
 521         tctl = E1000_READ_REG(hw, E1000_TCTL);
 522         rctl = E1000_READ_REG(hw, E1000_RCTL);
 523         if (enable) {
 524                 /* enable Tx/Rx */
 525                 tctl |= E1000_TCTL_EN;
 526                 rctl |= E1000_RCTL_EN;
 527         } else {
 528                 /* disable Tx/Rx */
 529                 tctl &= ~E1000_TCTL_EN;
 530                 rctl &= ~E1000_RCTL_EN;
 531         }
 532         E1000_WRITE_REG(hw, E1000_TCTL, tctl);
 533         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
 534         E1000_WRITE_FLUSH(hw);
 535 }
 536
 537 static int
 538 eth_em_start(struct rte_eth_dev *dev)
 539 {
 540         struct e1000_adapter *adapter =
 541                 E1000_DEV_PRIVATE(dev->data->dev_private);
 542         struct e1000_hw *hw =
 543                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 544         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
 545         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
 546         int ret, mask;
 547         uint32_t intr_vector = 0;
 548         uint32_t *speeds;
 549         int num_speeds;
 550         bool autoneg;
 551
 552         PMD_INIT_FUNC_TRACE();
 553
 554         eth_em_stop(dev);
 555
 556         e1000_power_up_phy(hw);
 557
 558         /* Set default PBA value */
 559         em_set_pba(hw);
 560
 561         /* Put the address into the Receive Address Array */
 562         e1000_rar_set(hw, hw->mac.addr, 0);
 563
 564         /*
 565          * With the 82571 adapter, RAR[0] may be overwritten
 566          * when the other port is reset, we make a duplicate
 567          * in RAR[14] for that eventuality, this assures
 568          * the interface continues to function.
 569          */
 570         if (hw->mac.type == e1000_82571) {
 571                 e1000_set_laa_state_82571(hw, TRUE);
 572                 e1000_rar_set(hw, hw->mac.addr, E1000_RAR_ENTRIES - 1);
 573         }
 574
 575         /* Initialize the hardware */
 576         if (em_hardware_init(hw)) {
 577                 PMD_INIT_LOG(ERR, "Unable to initialize the hardware");
 578                 return -EIO;
 579         }
 580
 581         E1000_WRITE_REG(hw, E1000_VET, ETHER_TYPE_VLAN);
 582
 583         /* Configure for OS presence */
 584         em_init_manageability(hw);
 585
 586         if (dev->data->dev_conf.intr_conf.rxq != 0) {
 587                 intr_vector = dev->data->nb_rx_queues;
 588                 if (rte_intr_efd_enable(intr_handle, intr_vector))
 589                         return -1;
 590         }
 591
 592         if (rte_intr_dp_is_en(intr_handle)) {
 593                 intr_handle->intr_vec =
 594                         rte_zmalloc("intr_vec",
 595                                         dev->data->nb_rx_queues * sizeof(int), 0);
 596                 if (intr_handle->intr_vec == NULL) {
 597                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
 598                                                 " intr_vec", dev->data->nb_rx_queues);
 599                         return -ENOMEM;
 600                 }
 601
 602                 /* enable rx interrupt */
 603                 em_rxq_intr_enable(hw);
 604         }
 605
 606         eth_em_tx_init(dev);
 607
 608         ret = eth_em_rx_init(dev);
 609         if (ret) {
 610                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
 611                 em_dev_clear_queues(dev);
 612                 return ret;
 613         }
 614
 615         e1000_clear_hw_cntrs_base_generic(hw);
 616
 617         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK | \
 618                         ETH_VLAN_EXTEND_MASK;
 619         ret = eth_em_vlan_offload_set(dev, mask);
 620         if (ret) {
 621                 PMD_INIT_LOG(ERR, "Unable to update vlan offload");
 622                 em_dev_clear_queues(dev);
 623                 return ret;
 624         }
 625
 626         /* Set Interrupt Throttling Rate to maximum allowed value. */
 627         E1000_WRITE_REG(hw, E1000_ITR, UINT16_MAX);
 628
 629         /* Setup link speed and duplex */
 630         speeds = &dev->data->dev_conf.link_speeds;
 631         if (*speeds == ETH_LINK_SPEED_AUTONEG) {
 632                 hw->phy.autoneg_advertised = E1000_ALL_SPEED_DUPLEX;
 633                 hw->mac.autoneg = 1;
 634         } else {
 635                 num_speeds = 0;
 636                 autoneg = (*speeds & ETH_LINK_SPEED_FIXED) == 0;
 637
 638                 /* Reset */
 639                 hw->phy.autoneg_advertised = 0;
 640
 641                 if (*speeds & ~(ETH_LINK_SPEED_10M_HD | ETH_LINK_SPEED_10M |
 642                                 ETH_LINK_SPEED_100M_HD | ETH_LINK_SPEED_100M |
 643                                 ETH_LINK_SPEED_1G | ETH_LINK_SPEED_FIXED)) {
 644                         num_speeds = -1;
 645                         goto error_invalid_config;
 646                 }
 647                 if (*speeds & ETH_LINK_SPEED_10M_HD) {
 648                         hw->phy.autoneg_advertised |= ADVERTISE_10_HALF;
 649                         num_speeds++;
 650                 }
 651                 if (*speeds & ETH_LINK_SPEED_10M) {
 652                         hw->phy.autoneg_advertised |= ADVERTISE_10_FULL;
 653                         num_speeds++;
 654                 }
 655                 if (*speeds & ETH_LINK_SPEED_100M_HD) {
 656                         hw->phy.autoneg_advertised |= ADVERTISE_100_HALF;
 657                         num_speeds++;
 658                 }
 659                 if (*speeds & ETH_LINK_SPEED_100M) {
 660                         hw->phy.autoneg_advertised |= ADVERTISE_100_FULL;
 661                         num_speeds++;
 662                 }
 663                 if (*speeds & ETH_LINK_SPEED_1G) {
 664                         hw->phy.autoneg_advertised |= ADVERTISE_1000_FULL;
 665                         num_speeds++;
 666                 }
 667                 if (num_speeds == 0 || (!autoneg && (num_speeds > 1)))
 668                         goto error_invalid_config;
 669
 670                 /* Set/reset the mac.autoneg based on the link speed,
 671                  * fixed or not
 672                  */
 673                 if (!autoneg) {
 674                         hw->mac.autoneg = 0;
 675                         hw->mac.forced_speed_duplex =
 676                                         hw->phy.autoneg_advertised;
 677                 } else {
 678                         hw->mac.autoneg = 1;
 679                 }
 680         }
 681
 682         e1000_setup_link(hw);
 683
 684         if (rte_intr_allow_others(intr_handle)) {
 685                 /* check if lsc interrupt is enabled */
 686                 if (dev->data->dev_conf.intr_conf.lsc != 0) {
 687                         ret = eth_em_interrupt_setup(dev);
 688                         if (ret) {
 689                                 PMD_INIT_LOG(ERR, "Unable to setup interrupts");
 690                                 em_dev_clear_queues(dev);
 691                                 return ret;
 692                         }
 693                 }
 694         } else {
 695                 rte_intr_callback_unregister(intr_handle,
 696                                                 eth_em_interrupt_handler,
 697                                                 (void *)dev);
 698                 if (dev->data->dev_conf.intr_conf.lsc != 0)
 699                         PMD_INIT_LOG(INFO, "lsc won't enable because of"
 700                                      " no intr multiplexn");
 701         }
 702         /* check if rxq interrupt is enabled */
 703         if (dev->data->dev_conf.intr_conf.rxq != 0)
 704                 eth_em_rxq_interrupt_setup(dev);
 705
 706         rte_intr_enable(intr_handle);
 707
 708         adapter->stopped = 0;
 709
 710         eth_em_rxtx_control(dev, true);
 711         eth_em_link_update(dev, 0);
 712
 713         PMD_INIT_LOG(DEBUG, "<<");
 714
 715         return 0;
 716
 717 error_invalid_config:
 718         PMD_INIT_LOG(ERR, "Invalid advertised speeds (%u) for port %u",
 719                      dev->data->dev_conf.link_speeds, dev->data->port_id);
 720         em_dev_clear_queues(dev);
 721         return -EINVAL;
 722 }
 723
 724 /*********************************************************************
 725  *
 726  *  This routine disables all traffic on the adapter by issuing a
 727  *  global reset on the MAC.
 728  *
 729  **********************************************************************/
 730 static void
 731 eth_em_stop(struct rte_eth_dev *dev)
 732 {
 733         struct rte_eth_link link;
 734         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 735         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
 736         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
 737
 738         eth_em_rxtx_control(dev, false);
 739         em_rxq_intr_disable(hw);
 740         em_lsc_intr_disable(hw);
 741
 742         e1000_reset_hw(hw);
 743         if (hw->mac.type >= e1000_82544)
 744                 E1000_WRITE_REG(hw, E1000_WUC, 0);
 745
 746         /* Power down the phy. Needed to make the link go down */
 747         e1000_power_down_phy(hw);
 748
 749         em_dev_clear_queues(dev);
 750
 751         /* clear the recorded link status */
 752         memset(&link, 0, sizeof(link));
 753         rte_eth_linkstatus_set(dev, &link);
 754
 755         if (!rte_intr_allow_others(intr_handle))
 756                 /* resume to the default handler */
 757                 rte_intr_callback_register(intr_handle,
 758                                            eth_em_interrupt_handler,
 759                                            (void *)dev);
 760
 761         /* Clean datapath event and queue/vec mapping */
 762         rte_intr_efd_disable(intr_handle);
 763         if (intr_handle->intr_vec != NULL) {
 764                 rte_free(intr_handle->intr_vec);
 765                 intr_handle->intr_vec = NULL;
 766         }
 767 }
 768
 769 static void
 770 eth_em_close(struct rte_eth_dev *dev)
 771 {
 772         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 773         struct e1000_adapter *adapter =
 774                 E1000_DEV_PRIVATE(dev->data->dev_private);
 775
 776         eth_em_stop(dev);
 777         adapter->stopped = 1;
 778         em_dev_free_queues(dev);
 779         e1000_phy_hw_reset(hw);
 780         em_release_manageability(hw);
 781         em_hw_control_release(hw);
 782 }
 783
 784 static int
 785 em_get_rx_buffer_size(struct e1000_hw *hw)
 786 {
 787         uint32_t rx_buf_size;
 788
 789         rx_buf_size = ((E1000_READ_REG(hw, E1000_PBA) & UINT16_MAX) << 10);
 790         return rx_buf_size;
 791 }
 792
 793 /*********************************************************************
 794  *
 795  *  Initialize the hardware
 796  *
 797  **********************************************************************/
 798 static int
 799 em_hardware_init(struct e1000_hw *hw)
 800 {
 801         uint32_t rx_buf_size;
 802         int diag;
 803
 804         /* Issue a global reset */
 805         e1000_reset_hw(hw);
 806
 807         /* Let the firmware know the OS is in control */
 808         em_hw_control_acquire(hw);
 809
 810         /*
 811          * These parameters control the automatic generation (Tx) and
 812          * response (Rx) to Ethernet PAUSE frames.
 813          * - High water mark should allow for at least two standard size (1518)
 814          *   frames to be received after sending an XOFF.
 815          * - Low water mark works best when it is very near the high water mark.
 816          *   This allows the receiver to restart by sending XON when it has
 817          *   drained a bit. Here we use an arbitrary value of 1500 which will
 818          *   restart after one full frame is pulled from the buffer. There
 819          *   could be several smaller frames in the buffer and if so they will
 820          *   not trigger the XON until their total number reduces the buffer
 821          *   by 1500.
 822          * - The pause time is fairly large at 1000 x 512ns = 512 usec.
 823          */
 824         rx_buf_size = em_get_rx_buffer_size(hw);
 825
 826         hw->fc.high_water = rx_buf_size - PMD_ROUNDUP(ETHER_MAX_LEN * 2, 1024);
 827         hw->fc.low_water = hw->fc.high_water - 1500;
 828
 829         if (hw->mac.type == e1000_80003es2lan)
 830                 hw->fc.pause_time = UINT16_MAX;
 831         else
 832                 hw->fc.pause_time = EM_FC_PAUSE_TIME;
 833
 834         hw->fc.send_xon = 1;
 835
 836         /* Set Flow control, use the tunable location if sane */
 837         if (em_fc_setting <= e1000_fc_full)
 838                 hw->fc.requested_mode = em_fc_setting;
 839         else
 840                 hw->fc.requested_mode = e1000_fc_none;
 841
 842         /* Workaround: no TX flow ctrl for PCH */
 843         if (hw->mac.type == e1000_pchlan)
 844                 hw->fc.requested_mode = e1000_fc_rx_pause;
 845
 846         /* Override - settings for PCH2LAN, ya its magic :) */
 847         if (hw->mac.type == e1000_pch2lan) {
 848                 hw->fc.high_water = 0x5C20;
 849                 hw->fc.low_water = 0x5048;
 850                 hw->fc.pause_time = 0x0650;
 851                 hw->fc.refresh_time = 0x0400;
 852         } else if (hw->mac.type == e1000_pch_lpt ||
 853                    hw->mac.type == e1000_pch_spt ||
 854                    hw->mac.type == e1000_pch_cnp) {
 855                 hw->fc.requested_mode = e1000_fc_full;
 856         }
 857
 858         diag = e1000_init_hw(hw);
 859         if (diag < 0)
 860                 return diag;
 861         e1000_check_for_link(hw);
 862         return 0;
 863 }
 864
 865 /* This function is based on em_update_stats_counters() in e1000/if_em.c */
 866 static int
 867 eth_em_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *rte_stats)
 868 {
 869         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 870         struct e1000_hw_stats *stats =
 871                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
 872         int pause_frames;
 873
 874         if(hw->phy.media_type == e1000_media_type_copper ||
 875                         (E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU)) {
 876                 stats->symerrs += E1000_READ_REG(hw,E1000_SYMERRS);
 877                 stats->sec += E1000_READ_REG(hw, E1000_SEC);
 878         }
 879
 880         stats->crcerrs += E1000_READ_REG(hw, E1000_CRCERRS);
 881         stats->mpc += E1000_READ_REG(hw, E1000_MPC);
 882         stats->scc += E1000_READ_REG(hw, E1000_SCC);
 883         stats->ecol += E1000_READ_REG(hw, E1000_ECOL);
 884
 885         stats->mcc += E1000_READ_REG(hw, E1000_MCC);
 886         stats->latecol += E1000_READ_REG(hw, E1000_LATECOL);
 887         stats->colc += E1000_READ_REG(hw, E1000_COLC);
 888         stats->dc += E1000_READ_REG(hw, E1000_DC);
 889         stats->rlec += E1000_READ_REG(hw, E1000_RLEC);
 890         stats->xonrxc += E1000_READ_REG(hw, E1000_XONRXC);
 891         stats->xontxc += E1000_READ_REG(hw, E1000_XONTXC);
 892
 893         /*
 894          * For watchdog management we need to know if we have been
 895          * paused during the last interval, so capture that here.
 896          */
 897         pause_frames = E1000_READ_REG(hw, E1000_XOFFRXC);
 898         stats->xoffrxc += pause_frames;
 899         stats->xofftxc += E1000_READ_REG(hw, E1000_XOFFTXC);
 900         stats->fcruc += E1000_READ_REG(hw, E1000_FCRUC);
 901         stats->prc64 += E1000_READ_REG(hw, E1000_PRC64);
 902         stats->prc127 += E1000_READ_REG(hw, E1000_PRC127);
 903         stats->prc255 += E1000_READ_REG(hw, E1000_PRC255);
 904         stats->prc511 += E1000_READ_REG(hw, E1000_PRC511);
 905         stats->prc1023 += E1000_READ_REG(hw, E1000_PRC1023);
 906         stats->prc1522 += E1000_READ_REG(hw, E1000_PRC1522);
 907         stats->gprc += E1000_READ_REG(hw, E1000_GPRC);
 908         stats->bprc += E1000_READ_REG(hw, E1000_BPRC);
 909         stats->mprc += E1000_READ_REG(hw, E1000_MPRC);
 910         stats->gptc += E1000_READ_REG(hw, E1000_GPTC);
 911
 912         /*
 913          * For the 64-bit byte counters the low dword must be read first.
 914          * Both registers clear on the read of the high dword.
 915          */
 916
 917         stats->gorc += E1000_READ_REG(hw, E1000_GORCL);
 918         stats->gorc += ((uint64_t)E1000_READ_REG(hw, E1000_GORCH) << 32);
 919         stats->gotc += E1000_READ_REG(hw, E1000_GOTCL);
 920         stats->gotc += ((uint64_t)E1000_READ_REG(hw, E1000_GOTCH) << 32);
 921
 922         stats->rnbc += E1000_READ_REG(hw, E1000_RNBC);
 923         stats->ruc += E1000_READ_REG(hw, E1000_RUC);
 924         stats->rfc += E1000_READ_REG(hw, E1000_RFC);
 925         stats->roc += E1000_READ_REG(hw, E1000_ROC);
 926         stats->rjc += E1000_READ_REG(hw, E1000_RJC);
 927
 928         stats->tor += E1000_READ_REG(hw, E1000_TORH);
 929         stats->tot += E1000_READ_REG(hw, E1000_TOTH);
 930
 931         stats->tpr += E1000_READ_REG(hw, E1000_TPR);
 932         stats->tpt += E1000_READ_REG(hw, E1000_TPT);
 933         stats->ptc64 += E1000_READ_REG(hw, E1000_PTC64);
 934         stats->ptc127 += E1000_READ_REG(hw, E1000_PTC127);
 935         stats->ptc255 += E1000_READ_REG(hw, E1000_PTC255);
 936         stats->ptc511 += E1000_READ_REG(hw, E1000_PTC511);
 937         stats->ptc1023 += E1000_READ_REG(hw, E1000_PTC1023);
 938         stats->ptc1522 += E1000_READ_REG(hw, E1000_PTC1522);
 939         stats->mptc += E1000_READ_REG(hw, E1000_MPTC);
 940         stats->bptc += E1000_READ_REG(hw, E1000_BPTC);
 941
 942         /* Interrupt Counts */
 943
 944         if (hw->mac.type >= e1000_82571) {
 945                 stats->iac += E1000_READ_REG(hw, E1000_IAC);
 946                 stats->icrxptc += E1000_READ_REG(hw, E1000_ICRXPTC);
 947                 stats->icrxatc += E1000_READ_REG(hw, E1000_ICRXATC);
 948                 stats->ictxptc += E1000_READ_REG(hw, E1000_ICTXPTC);
 949                 stats->ictxatc += E1000_READ_REG(hw, E1000_ICTXATC);
 950                 stats->ictxqec += E1000_READ_REG(hw, E1000_ICTXQEC);
 951                 stats->ictxqmtc += E1000_READ_REG(hw, E1000_ICTXQMTC);
 952                 stats->icrxdmtc += E1000_READ_REG(hw, E1000_ICRXDMTC);
 953                 stats->icrxoc += E1000_READ_REG(hw, E1000_ICRXOC);
 954         }
 955
 956         if (hw->mac.type >= e1000_82543) {
 957                 stats->algnerrc += E1000_READ_REG(hw, E1000_ALGNERRC);
 958                 stats->rxerrc += E1000_READ_REG(hw, E1000_RXERRC);
 959                 stats->tncrs += E1000_READ_REG(hw, E1000_TNCRS);
 960                 stats->cexterr += E1000_READ_REG(hw, E1000_CEXTERR);
 961                 stats->tsctc += E1000_READ_REG(hw, E1000_TSCTC);
 962                 stats->tsctfc += E1000_READ_REG(hw, E1000_TSCTFC);
 963         }
 964
 965         if (rte_stats == NULL)
 966                 return -EINVAL;
 967
 968         /* Rx Errors */
 969         rte_stats->imissed = stats->mpc;
 970         rte_stats->ierrors = stats->crcerrs +
 971                              stats->rlec + stats->ruc + stats->roc +
 972                              stats->rxerrc + stats->algnerrc + stats->cexterr;
 973
 974         /* Tx Errors */
 975         rte_stats->oerrors = stats->ecol + stats->latecol;
 976
 977         rte_stats->ipackets = stats->gprc;
 978         rte_stats->opackets = stats->gptc;
 979         rte_stats->ibytes   = stats->gorc;
 980         rte_stats->obytes   = stats->gotc;
 981         return 0;
 982 }
 983
 984 static void
 985 eth_em_stats_reset(struct rte_eth_dev *dev)
 986 {
 987         struct e1000_hw_stats *hw_stats =
 988                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
 989
 990         /* HW registers are cleared on read */
 991         eth_em_stats_get(dev, NULL);
 992
 993         /* Reset software totals */
 994         memset(hw_stats, 0, sizeof(*hw_stats));
 995 }
 996
 997 static int
 998 eth_em_rx_queue_intr_enable(struct rte_eth_dev *dev, __rte_unused uint16_t queue_id)
 999 {
1000         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1001         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1002         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1003
1004         em_rxq_intr_enable(hw);
1005         rte_intr_enable(intr_handle);
1006
1007         return 0;
1008 }
1009
1010 static int
1011 eth_em_rx_queue_intr_disable(struct rte_eth_dev *dev, __rte_unused uint16_t queue_id)
1012 {
1013         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1014
1015         em_rxq_intr_disable(hw);
1016
1017         return 0;
1018 }
1019
1020 uint32_t
1021 em_get_max_pktlen(struct rte_eth_dev *dev)
1022 {
1023         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1024
1025         switch (hw->mac.type) {
1026         case e1000_82571:
1027         case e1000_82572:
1028         case e1000_ich9lan:
1029         case e1000_ich10lan:
1030         case e1000_pch2lan:
1031         case e1000_pch_lpt:
1032         case e1000_pch_spt:
1033         case e1000_pch_cnp:
1034         case e1000_82574:
1035         case e1000_80003es2lan: /* 9K Jumbo Frame size */
1036         case e1000_82583:
1037                 return 0x2412;
1038         case e1000_pchlan:
1039                 return 0x1000;
1040         /* Adapters that do not support jumbo frames */
1041         case e1000_ich8lan:
1042                 return ETHER_MAX_LEN;
1043         default:
1044                 return MAX_JUMBO_FRAME_SIZE;
1045         }
1046 }
1047
1048 static void
1049 eth_em_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
1050 {
1051         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1052
1053         dev_info->min_rx_bufsize = 256; /* See BSIZE field of RCTL register. */
1054         dev_info->max_rx_pktlen = em_get_max_pktlen(dev);
1055         dev_info->max_mac_addrs = hw->mac.rar_entry_count;
1056
1057         /*
1058          * Starting with 631xESB hw supports 2 TX/RX queues per port.
1059          * Unfortunatelly, all these nics have just one TX context.
1060          * So we have few choises for TX:
1061          * - Use just one TX queue.
1062          * - Allow cksum offload only for one TX queue.
1063          * - Don't allow TX cksum offload at all.
1064          * For now, option #1 was chosen.
1065          * To use second RX queue we have to use extended RX descriptor
1066          * (Multiple Receive Queues are mutually exclusive with UDP
1067          * fragmentation and are not supported when a legacy receive
1068          * descriptor format is used).
1069          * Which means separate RX routinies - as legacy nics (82540, 82545)
1070          * don't support extended RXD.
1071          * To avoid it we support just one RX queue for now (no RSS).
1072          */
1073
1074         dev_info->max_rx_queues = 1;
1075         dev_info->max_tx_queues = 1;
1076
1077         dev_info->rx_queue_offload_capa = em_get_rx_queue_offloads_capa(dev);
1078         dev_info->rx_offload_capa = em_get_rx_port_offloads_capa(dev) |
1079                                     dev_info->rx_queue_offload_capa;
1080         dev_info->tx_queue_offload_capa = em_get_tx_queue_offloads_capa(dev);
1081         dev_info->tx_offload_capa = em_get_tx_port_offloads_capa(dev) |
1082                                     dev_info->tx_queue_offload_capa;
1083
1084         dev_info->rx_desc_lim = (struct rte_eth_desc_lim) {
1085                 .nb_max = E1000_MAX_RING_DESC,
1086                 .nb_min = E1000_MIN_RING_DESC,
1087                 .nb_align = EM_RXD_ALIGN,
1088         };
1089
1090         dev_info->tx_desc_lim = (struct rte_eth_desc_lim) {
1091                 .nb_max = E1000_MAX_RING_DESC,
1092                 .nb_min = E1000_MIN_RING_DESC,
1093                 .nb_align = EM_TXD_ALIGN,
1094                 .nb_seg_max = EM_TX_MAX_SEG,
1095                 .nb_mtu_seg_max = EM_TX_MAX_MTU_SEG,
1096         };
1097
1098         dev_info->speed_capa = ETH_LINK_SPEED_10M_HD | ETH_LINK_SPEED_10M |
1099                         ETH_LINK_SPEED_100M_HD | ETH_LINK_SPEED_100M |
1100                         ETH_LINK_SPEED_1G;
1101
1102         /* Preferred queue parameters */
1103         dev_info->default_rxportconf.nb_queues = 1;
1104         dev_info->default_txportconf.nb_queues = 1;
1105         dev_info->default_txportconf.ring_size = 256;
1106         dev_info->default_rxportconf.ring_size = 256;
1107 }
1108
1109 /* return 0 means link status changed, -1 means not changed */
1110 static int
1111 eth_em_link_update(struct rte_eth_dev *dev, int wait_to_complete)
1112 {
1113         struct e1000_hw *hw =
1114                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1115         struct rte_eth_link link;
1116         int link_check, count;
1117
1118         link_check = 0;
1119         hw->mac.get_link_status = 1;
1120
1121         /* possible wait-to-complete in up to 9 seconds */
1122         for (count = 0; count < EM_LINK_UPDATE_CHECK_TIMEOUT; count ++) {
1123                 /* Read the real link status */
1124                 switch (hw->phy.media_type) {
1125                 case e1000_media_type_copper:
1126                         /* Do the work to read phy */
1127                         e1000_check_for_link(hw);
1128                         link_check = !hw->mac.get_link_status;
1129                         break;
1130
1131                 case e1000_media_type_fiber:
1132                         e1000_check_for_link(hw);
1133                         link_check = (E1000_READ_REG(hw, E1000_STATUS) &
1134                                         E1000_STATUS_LU);
1135                         break;
1136
1137                 case e1000_media_type_internal_serdes:
1138                         e1000_check_for_link(hw);
1139                         link_check = hw->mac.serdes_has_link;
1140                         break;
1141
1142                 default:
1143                         break;
1144                 }
1145                 if (link_check || wait_to_complete == 0)
1146                         break;
1147                 rte_delay_ms(EM_LINK_UPDATE_CHECK_INTERVAL);
1148         }
1149         memset(&link, 0, sizeof(link));
1150
1151         /* Now we check if a transition has happened */
1152         if (link_check && (link.link_status == ETH_LINK_DOWN)) {
1153                 uint16_t duplex, speed;
1154                 hw->mac.ops.get_link_up_info(hw, &speed, &duplex);
1155                 link.link_duplex = (duplex == FULL_DUPLEX) ?
1156                                 ETH_LINK_FULL_DUPLEX :
1157                                 ETH_LINK_HALF_DUPLEX;
1158                 link.link_speed = speed;
1159                 link.link_status = ETH_LINK_UP;
1160                 link.link_autoneg = !(dev->data->dev_conf.link_speeds &
1161                                 ETH_LINK_SPEED_FIXED);
1162         } else if (!link_check && (link.link_status == ETH_LINK_UP)) {
1163                 link.link_speed = ETH_SPEED_NUM_NONE;
1164                 link.link_duplex = ETH_LINK_HALF_DUPLEX;
1165                 link.link_status = ETH_LINK_DOWN;
1166                 link.link_autoneg = ETH_LINK_FIXED;
1167         }
1168
1169         return rte_eth_linkstatus_set(dev, &link);
1170 }
1171
1172 /*
1173  * em_hw_control_acquire sets {CTRL_EXT|FWSM}:DRV_LOAD bit.
1174  * For ASF and Pass Through versions of f/w this means
1175  * that the driver is loaded. For AMT version type f/w
1176  * this means that the network i/f is open.
1177  */
1178 static void
1179 em_hw_control_acquire(struct e1000_hw *hw)
1180 {
1181         uint32_t ctrl_ext, swsm;
1182
1183         /* Let firmware know the driver has taken over */
1184         if (hw->mac.type == e1000_82573) {
1185                 swsm = E1000_READ_REG(hw, E1000_SWSM);
1186                 E1000_WRITE_REG(hw, E1000_SWSM, swsm | E1000_SWSM_DRV_LOAD);
1187
1188         } else {
1189                 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
1190                 E1000_WRITE_REG(hw, E1000_CTRL_EXT,
1191                         ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
1192         }
1193 }
1194
1195 /*
1196  * em_hw_control_release resets {CTRL_EXTT|FWSM}:DRV_LOAD bit.
1197  * For ASF and Pass Through versions of f/w this means that the
1198  * driver is no longer loaded. For AMT versions of the
1199  * f/w this means that the network i/f is closed.
1200  */
1201 static void
1202 em_hw_control_release(struct e1000_hw *hw)
1203 {
1204         uint32_t ctrl_ext, swsm;
1205
1206         /* Let firmware taken over control of h/w */
1207         if (hw->mac.type == e1000_82573) {
1208                 swsm = E1000_READ_REG(hw, E1000_SWSM);
1209                 E1000_WRITE_REG(hw, E1000_SWSM, swsm & ~E1000_SWSM_DRV_LOAD);
1210         } else {
1211                 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
1212                 E1000_WRITE_REG(hw, E1000_CTRL_EXT,
1213                         ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
1214         }
1215 }
1216
1217 /*
1218  * Bit of a misnomer, what this really means is
1219  * to enable OS management of the system... aka
1220  * to disable special hardware management features.
1221  */
1222 static void
1223 em_init_manageability(struct e1000_hw *hw)
1224 {
1225         if (e1000_enable_mng_pass_thru(hw)) {
1226                 uint32_t manc2h = E1000_READ_REG(hw, E1000_MANC2H);
1227                 uint32_t manc = E1000_READ_REG(hw, E1000_MANC);
1228
1229                 /* disable hardware interception of ARP */
1230                 manc &= ~(E1000_MANC_ARP_EN);
1231
1232                 /* enable receiving management packets to the host */
1233                 manc |= E1000_MANC_EN_MNG2HOST;
1234                 manc2h |= 1 << 5;  /* Mng Port 623 */
1235                 manc2h |= 1 << 6;  /* Mng Port 664 */
1236                 E1000_WRITE_REG(hw, E1000_MANC2H, manc2h);
1237                 E1000_WRITE_REG(hw, E1000_MANC, manc);
1238         }
1239 }
1240
1241 /*
1242  * Give control back to hardware management
1243  * controller if there is one.
1244  */
1245 static void
1246 em_release_manageability(struct e1000_hw *hw)
1247 {
1248         uint32_t manc;
1249
1250         if (e1000_enable_mng_pass_thru(hw)) {
1251                 manc = E1000_READ_REG(hw, E1000_MANC);
1252
1253                 /* re-enable hardware interception of ARP */
1254                 manc |= E1000_MANC_ARP_EN;
1255                 manc &= ~E1000_MANC_EN_MNG2HOST;
1256
1257                 E1000_WRITE_REG(hw, E1000_MANC, manc);
1258         }
1259 }
1260
1261 static void
1262 eth_em_promiscuous_enable(struct rte_eth_dev *dev)
1263 {
1264         struct e1000_hw *hw =
1265                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1266         uint32_t rctl;
1267
1268         rctl = E1000_READ_REG(hw, E1000_RCTL);
1269         rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
1270         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1271 }
1272
1273 static void
1274 eth_em_promiscuous_disable(struct rte_eth_dev *dev)
1275 {
1276         struct e1000_hw *hw =
1277                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1278         uint32_t rctl;
1279
1280         rctl = E1000_READ_REG(hw, E1000_RCTL);
1281         rctl &= ~(E1000_RCTL_UPE | E1000_RCTL_SBP);
1282         if (dev->data->all_multicast == 1)
1283                 rctl |= E1000_RCTL_MPE;
1284         else
1285                 rctl &= (~E1000_RCTL_MPE);
1286         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1287 }
1288
1289 static void
1290 eth_em_allmulticast_enable(struct rte_eth_dev *dev)
1291 {
1292         struct e1000_hw *hw =
1293                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1294         uint32_t rctl;
1295
1296         rctl = E1000_READ_REG(hw, E1000_RCTL);
1297         rctl |= E1000_RCTL_MPE;
1298         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1299 }
1300
1301 static void
1302 eth_em_allmulticast_disable(struct rte_eth_dev *dev)
1303 {
1304         struct e1000_hw *hw =
1305                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1306         uint32_t rctl;
1307
1308         if (dev->data->promiscuous == 1)
1309                 return; /* must remain in all_multicast mode */
1310         rctl = E1000_READ_REG(hw, E1000_RCTL);
1311         rctl &= (~E1000_RCTL_MPE);
1312         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1313 }
1314
1315 static int
1316 eth_em_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1317 {
1318         struct e1000_hw *hw =
1319                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1320         struct e1000_vfta * shadow_vfta =
1321                 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1322         uint32_t vfta;
1323         uint32_t vid_idx;
1324         uint32_t vid_bit;
1325
1326         vid_idx = (uint32_t) ((vlan_id >> E1000_VFTA_ENTRY_SHIFT) &
1327                               E1000_VFTA_ENTRY_MASK);
1328         vid_bit = (uint32_t) (1 << (vlan_id & E1000_VFTA_ENTRY_BIT_SHIFT_MASK));
1329         vfta = E1000_READ_REG_ARRAY(hw, E1000_VFTA, vid_idx);
1330         if (on)
1331                 vfta |= vid_bit;
1332         else
1333                 vfta &= ~vid_bit;
1334         E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, vid_idx, vfta);
1335
1336         /* update local VFTA copy */
1337         shadow_vfta->vfta[vid_idx] = vfta;
1338
1339         return 0;
1340 }
1341
1342 static void
1343 em_vlan_hw_filter_disable(struct rte_eth_dev *dev)
1344 {
1345         struct e1000_hw *hw =
1346                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1347         uint32_t reg;
1348
1349         /* Filter Table Disable */
1350         reg = E1000_READ_REG(hw, E1000_RCTL);
1351         reg &= ~E1000_RCTL_CFIEN;
1352         reg &= ~E1000_RCTL_VFE;
1353         E1000_WRITE_REG(hw, E1000_RCTL, reg);
1354 }
1355
1356 static void
1357 em_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1358 {
1359         struct e1000_hw *hw =
1360                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1361         struct e1000_vfta * shadow_vfta =
1362                 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1363         uint32_t reg;
1364         int i;
1365
1366         /* Filter Table Enable, CFI not used for packet acceptance */
1367         reg = E1000_READ_REG(hw, E1000_RCTL);
1368         reg &= ~E1000_RCTL_CFIEN;
1369         reg |= E1000_RCTL_VFE;
1370         E1000_WRITE_REG(hw, E1000_RCTL, reg);
1371
1372         /* restore vfta from local copy */
1373         for (i = 0; i < IGB_VFTA_SIZE; i++)
1374                 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, i, shadow_vfta->vfta[i]);
1375 }
1376
1377 static void
1378 em_vlan_hw_strip_disable(struct rte_eth_dev *dev)
1379 {
1380         struct e1000_hw *hw =
1381                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1382         uint32_t reg;
1383
1384         /* VLAN Mode Disable */
1385         reg = E1000_READ_REG(hw, E1000_CTRL);
1386         reg &= ~E1000_CTRL_VME;
1387         E1000_WRITE_REG(hw, E1000_CTRL, reg);
1388
1389 }
1390
1391 static void
1392 em_vlan_hw_strip_enable(struct rte_eth_dev *dev)
1393 {
1394         struct e1000_hw *hw =
1395                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1396         uint32_t reg;
1397
1398         /* VLAN Mode Enable */
1399         reg = E1000_READ_REG(hw, E1000_CTRL);
1400         reg |= E1000_CTRL_VME;
1401         E1000_WRITE_REG(hw, E1000_CTRL, reg);
1402 }
1403
1404 static int
1405 eth_em_vlan_offload_set(struct rte_eth_dev *dev, int mask)
1406 {
1407         struct rte_eth_rxmode *rxmode;
1408
1409         rxmode = &dev->data->dev_conf.rxmode;
1410         if(mask & ETH_VLAN_STRIP_MASK){
1411                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
1412                         em_vlan_hw_strip_enable(dev);
1413                 else
1414                         em_vlan_hw_strip_disable(dev);
1415         }
1416
1417         if(mask & ETH_VLAN_FILTER_MASK){
1418                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
1419                         em_vlan_hw_filter_enable(dev);
1420                 else
1421                         em_vlan_hw_filter_disable(dev);
1422         }
1423
1424         return 0;
1425 }
1426
1427 /*
1428  * It enables the interrupt mask and then enable the interrupt.
1429  *
1430  * @param dev
1431  *  Pointer to struct rte_eth_dev.
1432  *
1433  * @return
1434  *  - On success, zero.
1435  *  - On failure, a negative value.
1436  */
1437 static int
1438 eth_em_interrupt_setup(struct rte_eth_dev *dev)
1439 {
1440         uint32_t regval;
1441         struct e1000_hw *hw =
1442                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1443
1444         /* clear interrupt */
1445         E1000_READ_REG(hw, E1000_ICR);
1446         regval = E1000_READ_REG(hw, E1000_IMS);
1447         E1000_WRITE_REG(hw, E1000_IMS, regval | E1000_ICR_LSC);
1448         return 0;
1449 }
1450
1451 /*
1452  * It clears the interrupt causes and enables the interrupt.
1453  * It will be called once only during nic initialized.
1454  *
1455  * @param dev
1456  *  Pointer to struct rte_eth_dev.
1457  *
1458  * @return
1459  *  - On success, zero.
1460  *  - On failure, a negative value.
1461  */
1462 static int
1463 eth_em_rxq_interrupt_setup(struct rte_eth_dev *dev)
1464 {
1465         struct e1000_hw *hw =
1466         E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1467
1468         E1000_READ_REG(hw, E1000_ICR);
1469         em_rxq_intr_enable(hw);
1470         return 0;
1471 }
1472
1473 /*
1474  * It enable receive packet interrupt.
1475  * @param hw
1476  * Pointer to struct e1000_hw
1477  *
1478  * @return
1479  */
1480 static void
1481 em_rxq_intr_enable(struct e1000_hw *hw)
1482 {
1483         E1000_WRITE_REG(hw, E1000_IMS, E1000_IMS_RXT0);
1484         E1000_WRITE_FLUSH(hw);
1485 }
1486
1487 /*
1488  * It disabled lsc interrupt.
1489  * @param hw
1490  * Pointer to struct e1000_hw
1491  *
1492  * @return
1493  */
1494 static void
1495 em_lsc_intr_disable(struct e1000_hw *hw)
1496 {
1497         E1000_WRITE_REG(hw, E1000_IMC, E1000_IMS_LSC);
1498         E1000_WRITE_FLUSH(hw);
1499 }
1500
1501 /*
1502  * It disabled receive packet interrupt.
1503  * @param hw
1504  * Pointer to struct e1000_hw
1505  *
1506  * @return
1507  */
1508 static void
1509 em_rxq_intr_disable(struct e1000_hw *hw)
1510 {
1511         E1000_READ_REG(hw, E1000_ICR);
1512         E1000_WRITE_REG(hw, E1000_IMC, E1000_IMS_RXT0);
1513         E1000_WRITE_FLUSH(hw);
1514 }
1515
1516 /*
1517  * It reads ICR and gets interrupt causes, check it and set a bit flag
1518  * to update link status.
1519  *
1520  * @param dev
1521  *  Pointer to struct rte_eth_dev.
1522  *
1523  * @return
1524  *  - On success, zero.
1525  *  - On failure, a negative value.
1526  */
1527 static int
1528 eth_em_interrupt_get_status(struct rte_eth_dev *dev)
1529 {
1530         uint32_t icr;
1531         struct e1000_hw *hw =
1532                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1533         struct e1000_interrupt *intr =
1534                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
1535
1536         /* read-on-clear nic registers here */
1537         icr = E1000_READ_REG(hw, E1000_ICR);
1538         if (icr & E1000_ICR_LSC) {
1539                 intr->flags |= E1000_FLAG_NEED_LINK_UPDATE;
1540         }
1541
1542         return 0;
1543 }
1544
1545 /*
1546  * It executes link_update after knowing an interrupt is prsent.
1547  *
1548  * @param dev
1549  *  Pointer to struct rte_eth_dev.
1550  *
1551  * @return
1552  *  - On success, zero.
1553  *  - On failure, a negative value.
1554  */
1555 static int
1556 eth_em_interrupt_action(struct rte_eth_dev *dev,
1557                         struct rte_intr_handle *intr_handle)
1558 {
1559         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1560         struct e1000_hw *hw =
1561                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1562         struct e1000_interrupt *intr =
1563                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
1564         struct rte_eth_link link;
1565         int ret;
1566
1567         if (!(intr->flags & E1000_FLAG_NEED_LINK_UPDATE))
1568                 return -1;
1569
1570         intr->flags &= ~E1000_FLAG_NEED_LINK_UPDATE;
1571         rte_intr_enable(intr_handle);
1572
1573         /* set get_link_status to check register later */
1574         hw->mac.get_link_status = 1;
1575         ret = eth_em_link_update(dev, 0);
1576
1577         /* check if link has changed */
1578         if (ret < 0)
1579                 return 0;
1580
1581         rte_eth_linkstatus_get(dev, &link);
1582
1583         if (link.link_status) {
1584                 PMD_INIT_LOG(INFO, " Port %d: Link Up - speed %u Mbps - %s",
1585                              dev->data->port_id, link.link_speed,
1586                              link.link_duplex == ETH_LINK_FULL_DUPLEX ?
1587                              "full-duplex" : "half-duplex");
1588         } else {
1589                 PMD_INIT_LOG(INFO, " Port %d: Link Down", dev->data->port_id);
1590         }
1591         PMD_INIT_LOG(DEBUG, "PCI Address: %04d:%02d:%02d:%d",
1592                      pci_dev->addr.domain, pci_dev->addr.bus,
1593                      pci_dev->addr.devid, pci_dev->addr.function);
1594
1595         return 0;
1596 }
1597
1598 /**
1599  * Interrupt handler which shall be registered at first.
1600  *
1601  * @param handle
1602  *  Pointer to interrupt handle.
1603  * @param param
1604  *  The address of parameter (struct rte_eth_dev *) regsitered before.
1605  *
1606  * @return
1607  *  void
1608  */
1609 static void
1610 eth_em_interrupt_handler(void *param)
1611 {
1612         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
1613
1614         eth_em_interrupt_get_status(dev);
1615         eth_em_interrupt_action(dev, dev->intr_handle);
1616         _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC, NULL);
1617 }
1618
1619 static int
1620 eth_em_led_on(struct rte_eth_dev *dev)
1621 {
1622         struct e1000_hw *hw;
1623
1624         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1625         return e1000_led_on(hw) == E1000_SUCCESS ? 0 : -ENOTSUP;
1626 }
1627
1628 static int
1629 eth_em_led_off(struct rte_eth_dev *dev)
1630 {
1631         struct e1000_hw *hw;
1632
1633         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1634         return e1000_led_off(hw) == E1000_SUCCESS ? 0 : -ENOTSUP;
1635 }
1636
1637 static int
1638 eth_em_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
1639 {
1640         struct e1000_hw *hw;
1641         uint32_t ctrl;
1642         int tx_pause;
1643         int rx_pause;
1644
1645         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1646         fc_conf->pause_time = hw->fc.pause_time;
1647         fc_conf->high_water = hw->fc.high_water;
1648         fc_conf->low_water = hw->fc.low_water;
1649         fc_conf->send_xon = hw->fc.send_xon;
1650         fc_conf->autoneg = hw->mac.autoneg;
1651
1652         /*
1653          * Return rx_pause and tx_pause status according to actual setting of
1654          * the TFCE and RFCE bits in the CTRL register.
1655          */
1656         ctrl = E1000_READ_REG(hw, E1000_CTRL);
1657         if (ctrl & E1000_CTRL_TFCE)
1658                 tx_pause = 1;
1659         else
1660                 tx_pause = 0;
1661
1662         if (ctrl & E1000_CTRL_RFCE)
1663                 rx_pause = 1;
1664         else
1665                 rx_pause = 0;
1666
1667         if (rx_pause && tx_pause)
1668                 fc_conf->mode = RTE_FC_FULL;
1669         else if (rx_pause)
1670                 fc_conf->mode = RTE_FC_RX_PAUSE;
1671         else if (tx_pause)
1672                 fc_conf->mode = RTE_FC_TX_PAUSE;
1673         else
1674                 fc_conf->mode = RTE_FC_NONE;
1675
1676         return 0;
1677 }
1678
1679 static int
1680 eth_em_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
1681 {
1682         struct e1000_hw *hw;
1683         int err;
1684         enum e1000_fc_mode rte_fcmode_2_e1000_fcmode[] = {
1685                 e1000_fc_none,
1686                 e1000_fc_rx_pause,
1687                 e1000_fc_tx_pause,
1688                 e1000_fc_full
1689         };
1690         uint32_t rx_buf_size;
1691         uint32_t max_high_water;
1692         uint32_t rctl;
1693
1694         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1695         if (fc_conf->autoneg != hw->mac.autoneg)
1696                 return -ENOTSUP;
1697         rx_buf_size = em_get_rx_buffer_size(hw);
1698         PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
1699
1700         /* At least reserve one Ethernet frame for watermark */
1701         max_high_water = rx_buf_size - ETHER_MAX_LEN;
1702         if ((fc_conf->high_water > max_high_water) ||
1703             (fc_conf->high_water < fc_conf->low_water)) {
1704                 PMD_INIT_LOG(ERR, "e1000 incorrect high/low water value");
1705                 PMD_INIT_LOG(ERR, "high water must <= 0x%x", max_high_water);
1706                 return -EINVAL;
1707         }
1708
1709         hw->fc.requested_mode = rte_fcmode_2_e1000_fcmode[fc_conf->mode];
1710         hw->fc.pause_time     = fc_conf->pause_time;
1711         hw->fc.high_water     = fc_conf->high_water;
1712         hw->fc.low_water      = fc_conf->low_water;
1713         hw->fc.send_xon       = fc_conf->send_xon;
1714
1715         err = e1000_setup_link_generic(hw);
1716         if (err == E1000_SUCCESS) {
1717
1718                 /* check if we want to forward MAC frames - driver doesn't have native
1719                  * capability to do that, so we'll write the registers ourselves */
1720
1721                 rctl = E1000_READ_REG(hw, E1000_RCTL);
1722
1723                 /* set or clear MFLCN.PMCF bit depending on configuration */
1724                 if (fc_conf->mac_ctrl_frame_fwd != 0)
1725                         rctl |= E1000_RCTL_PMCF;
1726                 else
1727                         rctl &= ~E1000_RCTL_PMCF;
1728
1729                 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1730                 E1000_WRITE_FLUSH(hw);
1731
1732                 return 0;
1733         }
1734
1735         PMD_INIT_LOG(ERR, "e1000_setup_link_generic = 0x%x", err);
1736         return -EIO;
1737 }
1738
1739 static int
1740 eth_em_rar_set(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
1741                 uint32_t index, __rte_unused uint32_t pool)
1742 {
1743         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1744
1745         return e1000_rar_set(hw, mac_addr->addr_bytes, index);
1746 }
1747
1748 static void
1749 eth_em_rar_clear(struct rte_eth_dev *dev, uint32_t index)
1750 {
1751         uint8_t addr[ETHER_ADDR_LEN];
1752         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1753
1754         memset(addr, 0, sizeof(addr));
1755
1756         e1000_rar_set(hw, addr, index);
1757 }
1758
1759 static int
1760 eth_em_default_mac_addr_set(struct rte_eth_dev *dev,
1761                             struct ether_addr *addr)
1762 {
1763         eth_em_rar_clear(dev, 0);
1764
1765         return eth_em_rar_set(dev, (void *)addr, 0, 0);
1766 }
1767
1768 static int
1769 eth_em_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
1770 {
1771         struct rte_eth_dev_info dev_info;
1772         struct e1000_hw *hw;
1773         uint32_t frame_size;
1774         uint32_t rctl;
1775
1776         eth_em_infos_get(dev, &dev_info);
1777         frame_size = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN + VLAN_TAG_SIZE;
1778
1779         /* check that mtu is within the allowed range */
1780         if ((mtu < ETHER_MIN_MTU) || (frame_size > dev_info.max_rx_pktlen))
1781                 return -EINVAL;
1782
1783         /* refuse mtu that requires the support of scattered packets when this
1784          * feature has not been enabled before. */
1785         if (!dev->data->scattered_rx &&
1786             frame_size > dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)
1787                 return -EINVAL;
1788
1789         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1790         rctl = E1000_READ_REG(hw, E1000_RCTL);
1791
1792         /* switch to jumbo mode if needed */
1793         if (frame_size > ETHER_MAX_LEN) {
1794                 dev->data->dev_conf.rxmode.offloads |=
1795                         DEV_RX_OFFLOAD_JUMBO_FRAME;
1796                 rctl |= E1000_RCTL_LPE;
1797         } else {
1798                 dev->data->dev_conf.rxmode.offloads &=
1799                         ~DEV_RX_OFFLOAD_JUMBO_FRAME;
1800                 rctl &= ~E1000_RCTL_LPE;
1801         }
1802         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1803
1804         /* update max frame size */
1805         dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
1806         return 0;
1807 }
1808
1809 static int
1810 eth_em_set_mc_addr_list(struct rte_eth_dev *dev,
1811                         struct ether_addr *mc_addr_set,
1812                         uint32_t nb_mc_addr)
1813 {
1814         struct e1000_hw *hw;
1815
1816         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1817         e1000_update_mc_addr_list(hw, (u8 *)mc_addr_set, nb_mc_addr);
1818         return 0;
1819 }
1820
1821 RTE_PMD_REGISTER_PCI(net_e1000_em, rte_em_pmd);
1822 RTE_PMD_REGISTER_PCI_TABLE(net_e1000_em, pci_id_em_map);
1823 RTE_PMD_REGISTER_KMOD_DEP(net_e1000_em, "* igb_uio | uio_pci_generic | vfio-pci");
1824
1825 /* see e1000_logs.c */
1826 RTE_INIT(igb_init_log)
1827 {
1828         e1000_igb_init_log();
1829 }