drivers/net/e1000/em_ethdev.c

   1 /*-
   2  *   BSD LICENSE
   3  *
   4  *   Copyright(c) 2010-2016 Intel Corporation. All rights reserved.
   5  *   All rights reserved.
   6  *
   7  *   Redistribution and use in source and binary forms, with or without
   8  *   modification, are permitted provided that the following conditions
   9  *   are met:
  10  *
  11  *     * Redistributions of source code must retain the above copyright
  12  *       notice, this list of conditions and the following disclaimer.
  13  *     * Redistributions in binary form must reproduce the above copyright
  14  *       notice, this list of conditions and the following disclaimer in
  15  *       the documentation and/or other materials provided with the
  16  *       distribution.
  17  *     * Neither the name of Intel Corporation nor the names of its
  18  *       contributors may be used to endorse or promote products derived
  19  *       from this software without specific prior written permission.
  20  *
  21  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 #include <sys/queue.h>
  35 #include <stdio.h>
  36 #include <errno.h>
  37 #include <stdint.h>
  38 #include <stdarg.h>
  39
  40 #include <rte_common.h>
  41 #include <rte_interrupts.h>
  42 #include <rte_byteorder.h>
  43 #include <rte_log.h>
  44 #include <rte_debug.h>
  45 #include <rte_pci.h>
  46 #include <rte_ether.h>
  47 #include <rte_ethdev.h>
  48 #include <rte_ethdev_pci.h>
  49 #include <rte_memory.h>
  50 #include <rte_memzone.h>
  51 #include <rte_eal.h>
  52 #include <rte_atomic.h>
  53 #include <rte_malloc.h>
  54 #include <rte_dev.h>
  55
  56 #include "e1000_logs.h"
  57 #include "base/e1000_api.h"
  58 #include "e1000_ethdev.h"
  59
  60 #define EM_EIAC                 0x000DC
  61
  62 #define PMD_ROUNDUP(x,y)        (((x) + (y) - 1)/(y) * (y))
  63
  64
  65 static int eth_em_configure(struct rte_eth_dev *dev);
  66 static int eth_em_start(struct rte_eth_dev *dev);
  67 static void eth_em_stop(struct rte_eth_dev *dev);
  68 static void eth_em_close(struct rte_eth_dev *dev);
  69 static void eth_em_promiscuous_enable(struct rte_eth_dev *dev);
  70 static void eth_em_promiscuous_disable(struct rte_eth_dev *dev);
  71 static void eth_em_allmulticast_enable(struct rte_eth_dev *dev);
  72 static void eth_em_allmulticast_disable(struct rte_eth_dev *dev);
  73 static int eth_em_link_update(struct rte_eth_dev *dev,
  74                                 int wait_to_complete);
  75 static void eth_em_stats_get(struct rte_eth_dev *dev,
  76                                 struct rte_eth_stats *rte_stats);
  77 static void eth_em_stats_reset(struct rte_eth_dev *dev);
  78 static void eth_em_infos_get(struct rte_eth_dev *dev,
  79                                 struct rte_eth_dev_info *dev_info);
  80 static int eth_em_flow_ctrl_get(struct rte_eth_dev *dev,
  81                                 struct rte_eth_fc_conf *fc_conf);
  82 static int eth_em_flow_ctrl_set(struct rte_eth_dev *dev,
  83                                 struct rte_eth_fc_conf *fc_conf);
  84 static int eth_em_interrupt_setup(struct rte_eth_dev *dev);
  85 static int eth_em_rxq_interrupt_setup(struct rte_eth_dev *dev);
  86 static int eth_em_interrupt_get_status(struct rte_eth_dev *dev);
  87 static int eth_em_interrupt_action(struct rte_eth_dev *dev,
  88                                    struct rte_intr_handle *handle);
  89 static void eth_em_interrupt_handler(void *param);
  90
  91 static int em_hw_init(struct e1000_hw *hw);
  92 static int em_hardware_init(struct e1000_hw *hw);
  93 static void em_hw_control_acquire(struct e1000_hw *hw);
  94 static void em_hw_control_release(struct e1000_hw *hw);
  95 static void em_init_manageability(struct e1000_hw *hw);
  96 static void em_release_manageability(struct e1000_hw *hw);
  97
  98 static int eth_em_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
  99
 100 static int eth_em_vlan_filter_set(struct rte_eth_dev *dev,
 101                 uint16_t vlan_id, int on);
 102 static void eth_em_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 103 static void em_vlan_hw_filter_enable(struct rte_eth_dev *dev);
 104 static void em_vlan_hw_filter_disable(struct rte_eth_dev *dev);
 105 static void em_vlan_hw_strip_enable(struct rte_eth_dev *dev);
 106 static void em_vlan_hw_strip_disable(struct rte_eth_dev *dev);
 107
 108 /*
 109 static void eth_em_vlan_filter_set(struct rte_eth_dev *dev,
 110                                         uint16_t vlan_id, int on);
 111 */
 112
 113 static int eth_em_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id);
 114 static int eth_em_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id);
 115 static void em_lsc_intr_disable(struct e1000_hw *hw);
 116 static void em_rxq_intr_enable(struct e1000_hw *hw);
 117 static void em_rxq_intr_disable(struct e1000_hw *hw);
 118
 119 static int eth_em_led_on(struct rte_eth_dev *dev);
 120 static int eth_em_led_off(struct rte_eth_dev *dev);
 121
 122 static int em_get_rx_buffer_size(struct e1000_hw *hw);
 123 static int eth_em_rar_set(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
 124                           uint32_t index, uint32_t pool);
 125 static void eth_em_rar_clear(struct rte_eth_dev *dev, uint32_t index);
 126
 127 static int eth_em_set_mc_addr_list(struct rte_eth_dev *dev,
 128                                    struct ether_addr *mc_addr_set,
 129                                    uint32_t nb_mc_addr);
 130
 131 #define EM_FC_PAUSE_TIME 0x0680
 132 #define EM_LINK_UPDATE_CHECK_TIMEOUT  90  /* 9s */
 133 #define EM_LINK_UPDATE_CHECK_INTERVAL 100 /* ms */
 134
 135 static enum e1000_fc_mode em_fc_setting = e1000_fc_full;
 136
 137 /*
 138  * The set of PCI devices this driver supports
 139  */
 140 static const struct rte_pci_id pci_id_em_map[] = {
 141         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82540EM) },
 142         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82545EM_COPPER) },
 143         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82545EM_FIBER) },
 144         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82546EB_COPPER) },
 145         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82546EB_FIBER) },
 146         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82546EB_QUAD_COPPER) },
 147         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82571EB_COPPER) },
 148         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82571EB_FIBER) },
 149         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82571EB_SERDES) },
 150         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82571EB_SERDES_DUAL) },
 151         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82571EB_SERDES_QUAD) },
 152         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82571EB_QUAD_COPPER) },
 153         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82571PT_QUAD_COPPER) },
 154         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82571EB_QUAD_FIBER) },
 155         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82571EB_QUAD_COPPER_LP) },
 156         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82572EI_COPPER) },
 157         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82572EI_FIBER) },
 158         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82572EI_SERDES) },
 159         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82572EI) },
 160         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82573L) },
 161         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82574L) },
 162         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82574LA) },
 163         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82583V) },
 164         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_LPT_I217_LM) },
 165         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_LPT_I217_V) },
 166         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_LPTLP_I218_LM) },
 167         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_LPTLP_I218_V) },
 168         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_I218_LM2) },
 169         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_I218_V2) },
 170         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_I218_LM3) },
 171         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_I218_V3) },
 172         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_SPT_I219_LM) },
 173         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_SPT_I219_V) },
 174         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_SPT_I219_LM2) },
 175         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_SPT_I219_V2) },
 176         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_LBG_I219_LM3) },
 177         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_SPT_I219_LM4) },
 178         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_SPT_I219_V4) },
 179         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_SPT_I219_LM5) },
 180         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_SPT_I219_V5) },
 181         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_CNP_I219_LM6) },
 182         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_CNP_I219_V6) },
 183         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_CNP_I219_LM7) },
 184         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_CNP_I219_V7) },
 185         { .vendor_id = 0, /* sentinel */ },
 186 };
 187
 188 static const struct eth_dev_ops eth_em_ops = {
 189         .dev_configure        = eth_em_configure,
 190         .dev_start            = eth_em_start,
 191         .dev_stop             = eth_em_stop,
 192         .dev_close            = eth_em_close,
 193         .promiscuous_enable   = eth_em_promiscuous_enable,
 194         .promiscuous_disable  = eth_em_promiscuous_disable,
 195         .allmulticast_enable  = eth_em_allmulticast_enable,
 196         .allmulticast_disable = eth_em_allmulticast_disable,
 197         .link_update          = eth_em_link_update,
 198         .stats_get            = eth_em_stats_get,
 199         .stats_reset          = eth_em_stats_reset,
 200         .dev_infos_get        = eth_em_infos_get,
 201         .mtu_set              = eth_em_mtu_set,
 202         .vlan_filter_set      = eth_em_vlan_filter_set,
 203         .vlan_offload_set     = eth_em_vlan_offload_set,
 204         .rx_queue_setup       = eth_em_rx_queue_setup,
 205         .rx_queue_release     = eth_em_rx_queue_release,
 206         .rx_queue_count       = eth_em_rx_queue_count,
 207         .rx_descriptor_done   = eth_em_rx_descriptor_done,
 208         .rx_descriptor_status = eth_em_rx_descriptor_status,
 209         .tx_descriptor_status = eth_em_tx_descriptor_status,
 210         .tx_queue_setup       = eth_em_tx_queue_setup,
 211         .tx_queue_release     = eth_em_tx_queue_release,
 212         .rx_queue_intr_enable = eth_em_rx_queue_intr_enable,
 213         .rx_queue_intr_disable = eth_em_rx_queue_intr_disable,
 214         .dev_led_on           = eth_em_led_on,
 215         .dev_led_off          = eth_em_led_off,
 216         .flow_ctrl_get        = eth_em_flow_ctrl_get,
 217         .flow_ctrl_set        = eth_em_flow_ctrl_set,
 218         .mac_addr_add         = eth_em_rar_set,
 219         .mac_addr_remove      = eth_em_rar_clear,
 220         .set_mc_addr_list     = eth_em_set_mc_addr_list,
 221         .rxq_info_get         = em_rxq_info_get,
 222         .txq_info_get         = em_txq_info_get,
 223 };
 224
 225 /**
 226  * Atomically reads the link status information from global
 227  * structure rte_eth_dev.
 228  *
 229  * @param dev
 230  *   - Pointer to the structure rte_eth_dev to read from.
 231  *   - Pointer to the buffer to be saved with the link status.
 232  *
 233  * @return
 234  *   - On success, zero.
 235  *   - On failure, negative value.
 236  */
 237 static inline int
 238 rte_em_dev_atomic_read_link_status(struct rte_eth_dev *dev,
 239                                 struct rte_eth_link *link)
 240 {
 241         struct rte_eth_link *dst = link;
 242         struct rte_eth_link *src = &(dev->data->dev_link);
 243
 244         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 245                                         *(uint64_t *)src) == 0)
 246                 return -1;
 247
 248         return 0;
 249 }
 250
 251 /**
 252  * Atomically writes the link status information into global
 253  * structure rte_eth_dev.
 254  *
 255  * @param dev
 256  *   - Pointer to the structure rte_eth_dev to read from.
 257  *   - Pointer to the buffer to be saved with the link status.
 258  *
 259  * @return
 260  *   - On success, zero.
 261  *   - On failure, negative value.
 262  */
 263 static inline int
 264 rte_em_dev_atomic_write_link_status(struct rte_eth_dev *dev,
 265                                 struct rte_eth_link *link)
 266 {
 267         struct rte_eth_link *dst = &(dev->data->dev_link);
 268         struct rte_eth_link *src = link;
 269
 270         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 271                                         *(uint64_t *)src) == 0)
 272                 return -1;
 273
 274         return 0;
 275 }
 276
 277 /**
 278  *  eth_em_dev_is_ich8 - Check for ICH8 device
 279  *  @hw: pointer to the HW structure
 280  *
 281  *  return TRUE for ICH8, otherwise FALSE
 282  **/
 283 static bool
 284 eth_em_dev_is_ich8(struct e1000_hw *hw)
 285 {
 286         DEBUGFUNC("eth_em_dev_is_ich8");
 287
 288         switch (hw->device_id) {
 289         case E1000_DEV_ID_PCH_LPT_I217_LM:
 290         case E1000_DEV_ID_PCH_LPT_I217_V:
 291         case E1000_DEV_ID_PCH_LPTLP_I218_LM:
 292         case E1000_DEV_ID_PCH_LPTLP_I218_V:
 293         case E1000_DEV_ID_PCH_I218_V2:
 294         case E1000_DEV_ID_PCH_I218_LM2:
 295         case E1000_DEV_ID_PCH_I218_V3:
 296         case E1000_DEV_ID_PCH_I218_LM3:
 297         case E1000_DEV_ID_PCH_SPT_I219_LM:
 298         case E1000_DEV_ID_PCH_SPT_I219_V:
 299         case E1000_DEV_ID_PCH_SPT_I219_LM2:
 300         case E1000_DEV_ID_PCH_SPT_I219_V2:
 301         case E1000_DEV_ID_PCH_LBG_I219_LM3:
 302         case E1000_DEV_ID_PCH_SPT_I219_LM4:
 303         case E1000_DEV_ID_PCH_SPT_I219_V4:
 304         case E1000_DEV_ID_PCH_SPT_I219_LM5:
 305         case E1000_DEV_ID_PCH_SPT_I219_V5:
 306         case E1000_DEV_ID_PCH_CNP_I219_LM6:
 307         case E1000_DEV_ID_PCH_CNP_I219_V6:
 308         case E1000_DEV_ID_PCH_CNP_I219_LM7:
 309         case E1000_DEV_ID_PCH_CNP_I219_V7:
 310                 return 1;
 311         default:
 312                 return 0;
 313         }
 314 }
 315
 316 static int
 317 eth_em_dev_init(struct rte_eth_dev *eth_dev)
 318 {
 319         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
 320         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
 321         struct e1000_adapter *adapter =
 322                 E1000_DEV_PRIVATE(eth_dev->data->dev_private);
 323         struct e1000_hw *hw =
 324                 E1000_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 325         struct e1000_vfta * shadow_vfta =
 326                 E1000_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
 327
 328         eth_dev->dev_ops = &eth_em_ops;
 329         eth_dev->rx_pkt_burst = (eth_rx_burst_t)&eth_em_recv_pkts;
 330         eth_dev->tx_pkt_burst = (eth_tx_burst_t)&eth_em_xmit_pkts;
 331         eth_dev->tx_pkt_prepare = (eth_tx_prep_t)&eth_em_prep_pkts;
 332
 333         /* for secondary processes, we don't initialise any further as primary
 334          * has already done this work. Only check we don't need a different
 335          * RX function */
 336         if (rte_eal_process_type() != RTE_PROC_PRIMARY){
 337                 if (eth_dev->data->scattered_rx)
 338                         eth_dev->rx_pkt_burst =
 339                                 (eth_rx_burst_t)&eth_em_recv_scattered_pkts;
 340                 return 0;
 341         }
 342
 343         rte_eth_copy_pci_info(eth_dev, pci_dev);
 344         eth_dev->data->dev_flags |= RTE_ETH_DEV_DETACHABLE;
 345
 346         hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
 347         hw->device_id = pci_dev->id.device_id;
 348         adapter->stopped = 0;
 349
 350         /* For ICH8 support we'll need to map the flash memory BAR */
 351         if (eth_em_dev_is_ich8(hw))
 352                 hw->flash_address = (void *)pci_dev->mem_resource[1].addr;
 353
 354         if (e1000_setup_init_funcs(hw, TRUE) != E1000_SUCCESS ||
 355                         em_hw_init(hw) != 0) {
 356                 PMD_INIT_LOG(ERR, "port_id %d vendorID=0x%x deviceID=0x%x: "
 357                         "failed to init HW",
 358                         eth_dev->data->port_id, pci_dev->id.vendor_id,
 359                         pci_dev->id.device_id);
 360                 return -ENODEV;
 361         }
 362
 363         /* Allocate memory for storing MAC addresses */
 364         eth_dev->data->mac_addrs = rte_zmalloc("e1000", ETHER_ADDR_LEN *
 365                         hw->mac.rar_entry_count, 0);
 366         if (eth_dev->data->mac_addrs == NULL) {
 367                 PMD_INIT_LOG(ERR, "Failed to allocate %d bytes needed to "
 368                         "store MAC addresses",
 369                         ETHER_ADDR_LEN * hw->mac.rar_entry_count);
 370                 return -ENOMEM;
 371         }
 372
 373         /* Copy the permanent MAC address */
 374         ether_addr_copy((struct ether_addr *) hw->mac.addr,
 375                 eth_dev->data->mac_addrs);
 376
 377         /* initialize the vfta */
 378         memset(shadow_vfta, 0, sizeof(*shadow_vfta));
 379
 380         PMD_INIT_LOG(DEBUG, "port_id %d vendorID=0x%x deviceID=0x%x",
 381                      eth_dev->data->port_id, pci_dev->id.vendor_id,
 382                      pci_dev->id.device_id);
 383
 384         rte_intr_callback_register(intr_handle,
 385                                    eth_em_interrupt_handler, eth_dev);
 386
 387         return 0;
 388 }
 389
 390 static int
 391 eth_em_dev_uninit(struct rte_eth_dev *eth_dev)
 392 {
 393         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
 394         struct e1000_adapter *adapter =
 395                 E1000_DEV_PRIVATE(eth_dev->data->dev_private);
 396         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
 397
 398         PMD_INIT_FUNC_TRACE();
 399
 400         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
 401                 return -EPERM;
 402
 403         if (adapter->stopped == 0)
 404                 eth_em_close(eth_dev);
 405
 406         eth_dev->dev_ops = NULL;
 407         eth_dev->rx_pkt_burst = NULL;
 408         eth_dev->tx_pkt_burst = NULL;
 409
 410         rte_free(eth_dev->data->mac_addrs);
 411         eth_dev->data->mac_addrs = NULL;
 412
 413         /* disable uio intr before callback unregister */
 414         rte_intr_disable(intr_handle);
 415         rte_intr_callback_unregister(intr_handle,
 416                                      eth_em_interrupt_handler, eth_dev);
 417
 418         return 0;
 419 }
 420
 421 static int eth_em_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
 422         struct rte_pci_device *pci_dev)
 423 {
 424         return rte_eth_dev_pci_generic_probe(pci_dev,
 425                 sizeof(struct e1000_adapter), eth_em_dev_init);
 426 }
 427
 428 static int eth_em_pci_remove(struct rte_pci_device *pci_dev)
 429 {
 430         return rte_eth_dev_pci_generic_remove(pci_dev, eth_em_dev_uninit);
 431 }
 432
 433 static struct rte_pci_driver rte_em_pmd = {
 434         .id_table = pci_id_em_map,
 435         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
 436         .probe = eth_em_pci_probe,
 437         .remove = eth_em_pci_remove,
 438 };
 439
 440 static int
 441 em_hw_init(struct e1000_hw *hw)
 442 {
 443         int diag;
 444
 445         diag = hw->mac.ops.init_params(hw);
 446         if (diag != 0) {
 447                 PMD_INIT_LOG(ERR, "MAC Initialization Error");
 448                 return diag;
 449         }
 450         diag = hw->nvm.ops.init_params(hw);
 451         if (diag != 0) {
 452                 PMD_INIT_LOG(ERR, "NVM Initialization Error");
 453                 return diag;
 454         }
 455         diag = hw->phy.ops.init_params(hw);
 456         if (diag != 0) {
 457                 PMD_INIT_LOG(ERR, "PHY Initialization Error");
 458                 return diag;
 459         }
 460         (void) e1000_get_bus_info(hw);
 461
 462         hw->mac.autoneg = 1;
 463         hw->phy.autoneg_wait_to_complete = 0;
 464         hw->phy.autoneg_advertised = E1000_ALL_SPEED_DUPLEX;
 465
 466         e1000_init_script_state_82541(hw, TRUE);
 467         e1000_set_tbi_compatibility_82543(hw, TRUE);
 468
 469         /* Copper options */
 470         if (hw->phy.media_type == e1000_media_type_copper) {
 471                 hw->phy.mdix = 0; /* AUTO_ALL_MODES */
 472                 hw->phy.disable_polarity_correction = 0;
 473                 hw->phy.ms_type = e1000_ms_hw_default;
 474         }
 475
 476         /*
 477          * Start from a known state, this is important in reading the nvm
 478          * and mac from that.
 479          */
 480         e1000_reset_hw(hw);
 481
 482         /* Make sure we have a good EEPROM before we read from it */
 483         if (e1000_validate_nvm_checksum(hw) < 0) {
 484                 /*
 485                  * Some PCI-E parts fail the first check due to
 486                  * the link being in sleep state, call it again,
 487                  * if it fails a second time its a real issue.
 488                  */
 489                 diag = e1000_validate_nvm_checksum(hw);
 490                 if (diag < 0) {
 491                         PMD_INIT_LOG(ERR, "EEPROM checksum invalid");
 492                         goto error;
 493                 }
 494         }
 495
 496         /* Read the permanent MAC address out of the EEPROM */
 497         diag = e1000_read_mac_addr(hw);
 498         if (diag != 0) {
 499                 PMD_INIT_LOG(ERR, "EEPROM error while reading MAC address");
 500                 goto error;
 501         }
 502
 503         /* Now initialize the hardware */
 504         diag = em_hardware_init(hw);
 505         if (diag != 0) {
 506                 PMD_INIT_LOG(ERR, "Hardware initialization failed");
 507                 goto error;
 508         }
 509
 510         hw->mac.get_link_status = 1;
 511
 512         /* Indicate SOL/IDER usage */
 513         diag = e1000_check_reset_block(hw);
 514         if (diag < 0) {
 515                 PMD_INIT_LOG(ERR, "PHY reset is blocked due to "
 516                         "SOL/IDER session");
 517         }
 518         return 0;
 519
 520 error:
 521         em_hw_control_release(hw);
 522         return diag;
 523 }
 524
 525 static int
 526 eth_em_configure(struct rte_eth_dev *dev)
 527 {
 528         struct e1000_interrupt *intr =
 529                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
 530
 531         PMD_INIT_FUNC_TRACE();
 532         intr->flags |= E1000_FLAG_NEED_LINK_UPDATE;
 533         PMD_INIT_FUNC_TRACE();
 534
 535         return 0;
 536 }
 537
 538 static void
 539 em_set_pba(struct e1000_hw *hw)
 540 {
 541         uint32_t pba;
 542
 543         /*
 544          * Packet Buffer Allocation (PBA)
 545          * Writing PBA sets the receive portion of the buffer
 546          * the remainder is used for the transmit buffer.
 547          * Devices before the 82547 had a Packet Buffer of 64K.
 548          * After the 82547 the buffer was reduced to 40K.
 549          */
 550         switch (hw->mac.type) {
 551                 case e1000_82547:
 552                 case e1000_82547_rev_2:
 553                 /* 82547: Total Packet Buffer is 40K */
 554                         pba = E1000_PBA_22K; /* 22K for Rx, 18K for Tx */
 555                         break;
 556                 case e1000_82571:
 557                 case e1000_82572:
 558                 case e1000_80003es2lan:
 559                         pba = E1000_PBA_32K; /* 32K for Rx, 16K for Tx */
 560                         break;
 561                 case e1000_82573: /* 82573: Total Packet Buffer is 32K */
 562                         pba = E1000_PBA_12K; /* 12K for Rx, 20K for Tx */
 563                         break;
 564                 case e1000_82574:
 565                 case e1000_82583:
 566                         pba = E1000_PBA_20K; /* 20K for Rx, 20K for Tx */
 567                         break;
 568                 case e1000_ich8lan:
 569                         pba = E1000_PBA_8K;
 570                         break;
 571                 case e1000_ich9lan:
 572                 case e1000_ich10lan:
 573                         pba = E1000_PBA_10K;
 574                         break;
 575                 case e1000_pchlan:
 576                 case e1000_pch2lan:
 577                 case e1000_pch_lpt:
 578                 case e1000_pch_spt:
 579                 case e1000_pch_cnp:
 580                         pba = E1000_PBA_26K;
 581                         break;
 582                 default:
 583                         pba = E1000_PBA_40K; /* 40K for Rx, 24K for Tx */
 584         }
 585
 586         E1000_WRITE_REG(hw, E1000_PBA, pba);
 587 }
 588
 589 static int
 590 eth_em_start(struct rte_eth_dev *dev)
 591 {
 592         struct e1000_adapter *adapter =
 593                 E1000_DEV_PRIVATE(dev->data->dev_private);
 594         struct e1000_hw *hw =
 595                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 596         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
 597         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
 598         int ret, mask;
 599         uint32_t intr_vector = 0;
 600         uint32_t *speeds;
 601         int num_speeds;
 602         bool autoneg;
 603
 604         PMD_INIT_FUNC_TRACE();
 605
 606         eth_em_stop(dev);
 607
 608         e1000_power_up_phy(hw);
 609
 610         /* Set default PBA value */
 611         em_set_pba(hw);
 612
 613         /* Put the address into the Receive Address Array */
 614         e1000_rar_set(hw, hw->mac.addr, 0);
 615
 616         /*
 617          * With the 82571 adapter, RAR[0] may be overwritten
 618          * when the other port is reset, we make a duplicate
 619          * in RAR[14] for that eventuality, this assures
 620          * the interface continues to function.
 621          */
 622         if (hw->mac.type == e1000_82571) {
 623                 e1000_set_laa_state_82571(hw, TRUE);
 624                 e1000_rar_set(hw, hw->mac.addr, E1000_RAR_ENTRIES - 1);
 625         }
 626
 627         /* Initialize the hardware */
 628         if (em_hardware_init(hw)) {
 629                 PMD_INIT_LOG(ERR, "Unable to initialize the hardware");
 630                 return -EIO;
 631         }
 632
 633         E1000_WRITE_REG(hw, E1000_VET, ETHER_TYPE_VLAN);
 634
 635         /* Configure for OS presence */
 636         em_init_manageability(hw);
 637
 638         if (dev->data->dev_conf.intr_conf.rxq != 0) {
 639                 intr_vector = dev->data->nb_rx_queues;
 640                 if (rte_intr_efd_enable(intr_handle, intr_vector))
 641                         return -1;
 642         }
 643
 644         if (rte_intr_dp_is_en(intr_handle)) {
 645                 intr_handle->intr_vec =
 646                         rte_zmalloc("intr_vec",
 647                                         dev->data->nb_rx_queues * sizeof(int), 0);
 648                 if (intr_handle->intr_vec == NULL) {
 649                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
 650                                                 " intr_vec", dev->data->nb_rx_queues);
 651                         return -ENOMEM;
 652                 }
 653
 654                 /* enable rx interrupt */
 655                 em_rxq_intr_enable(hw);
 656         }
 657
 658         eth_em_tx_init(dev);
 659
 660         ret = eth_em_rx_init(dev);
 661         if (ret) {
 662                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
 663                 em_dev_clear_queues(dev);
 664                 return ret;
 665         }
 666
 667         e1000_clear_hw_cntrs_base_generic(hw);
 668
 669         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK | \
 670                         ETH_VLAN_EXTEND_MASK;
 671         eth_em_vlan_offload_set(dev, mask);
 672
 673         /* Set Interrupt Throttling Rate to maximum allowed value. */
 674         E1000_WRITE_REG(hw, E1000_ITR, UINT16_MAX);
 675
 676         /* Setup link speed and duplex */
 677         speeds = &dev->data->dev_conf.link_speeds;
 678         if (*speeds == ETH_LINK_SPEED_AUTONEG) {
 679                 hw->phy.autoneg_advertised = E1000_ALL_SPEED_DUPLEX;
 680                 hw->mac.autoneg = 1;
 681         } else {
 682                 num_speeds = 0;
 683                 autoneg = (*speeds & ETH_LINK_SPEED_FIXED) == 0;
 684
 685                 /* Reset */
 686                 hw->phy.autoneg_advertised = 0;
 687
 688                 if (*speeds & ~(ETH_LINK_SPEED_10M_HD | ETH_LINK_SPEED_10M |
 689                                 ETH_LINK_SPEED_100M_HD | ETH_LINK_SPEED_100M |
 690                                 ETH_LINK_SPEED_1G | ETH_LINK_SPEED_FIXED)) {
 691                         num_speeds = -1;
 692                         goto error_invalid_config;
 693                 }
 694                 if (*speeds & ETH_LINK_SPEED_10M_HD) {
 695                         hw->phy.autoneg_advertised |= ADVERTISE_10_HALF;
 696                         num_speeds++;
 697                 }
 698                 if (*speeds & ETH_LINK_SPEED_10M) {
 699                         hw->phy.autoneg_advertised |= ADVERTISE_10_FULL;
 700                         num_speeds++;
 701                 }
 702                 if (*speeds & ETH_LINK_SPEED_100M_HD) {
 703                         hw->phy.autoneg_advertised |= ADVERTISE_100_HALF;
 704                         num_speeds++;
 705                 }
 706                 if (*speeds & ETH_LINK_SPEED_100M) {
 707                         hw->phy.autoneg_advertised |= ADVERTISE_100_FULL;
 708                         num_speeds++;
 709                 }
 710                 if (*speeds & ETH_LINK_SPEED_1G) {
 711                         hw->phy.autoneg_advertised |= ADVERTISE_1000_FULL;
 712                         num_speeds++;
 713                 }
 714                 if (num_speeds == 0 || (!autoneg && (num_speeds > 1)))
 715                         goto error_invalid_config;
 716
 717                 /* Set/reset the mac.autoneg based on the link speed,
 718                  * fixed or not
 719                  */
 720                 if (!autoneg) {
 721                         hw->mac.autoneg = 0;
 722                         hw->mac.forced_speed_duplex =
 723                                         hw->phy.autoneg_advertised;
 724                 } else {
 725                         hw->mac.autoneg = 1;
 726                 }
 727         }
 728
 729         e1000_setup_link(hw);
 730
 731         if (rte_intr_allow_others(intr_handle)) {
 732                 /* check if lsc interrupt is enabled */
 733                 if (dev->data->dev_conf.intr_conf.lsc != 0) {
 734                         ret = eth_em_interrupt_setup(dev);
 735                         if (ret) {
 736                                 PMD_INIT_LOG(ERR, "Unable to setup interrupts");
 737                                 em_dev_clear_queues(dev);
 738                                 return ret;
 739                         }
 740                 }
 741         } else {
 742                 rte_intr_callback_unregister(intr_handle,
 743                                                 eth_em_interrupt_handler,
 744                                                 (void *)dev);
 745                 if (dev->data->dev_conf.intr_conf.lsc != 0)
 746                         PMD_INIT_LOG(INFO, "lsc won't enable because of"
 747                                      " no intr multiplexn");
 748         }
 749         /* check if rxq interrupt is enabled */
 750         if (dev->data->dev_conf.intr_conf.rxq != 0)
 751                 eth_em_rxq_interrupt_setup(dev);
 752
 753         rte_intr_enable(intr_handle);
 754
 755         adapter->stopped = 0;
 756
 757         PMD_INIT_LOG(DEBUG, "<<");
 758
 759         return 0;
 760
 761 error_invalid_config:
 762         PMD_INIT_LOG(ERR, "Invalid advertised speeds (%u) for port %u",
 763                      dev->data->dev_conf.link_speeds, dev->data->port_id);
 764         em_dev_clear_queues(dev);
 765         return -EINVAL;
 766 }
 767
 768 /*********************************************************************
 769  *
 770  *  This routine disables all traffic on the adapter by issuing a
 771  *  global reset on the MAC.
 772  *
 773  **********************************************************************/
 774 static void
 775 eth_em_stop(struct rte_eth_dev *dev)
 776 {
 777         struct rte_eth_link link;
 778         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 779         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
 780         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
 781
 782         em_rxq_intr_disable(hw);
 783         em_lsc_intr_disable(hw);
 784
 785         e1000_reset_hw(hw);
 786         if (hw->mac.type >= e1000_82544)
 787                 E1000_WRITE_REG(hw, E1000_WUC, 0);
 788
 789         /* Power down the phy. Needed to make the link go down */
 790         e1000_power_down_phy(hw);
 791
 792         em_dev_clear_queues(dev);
 793
 794         /* clear the recorded link status */
 795         memset(&link, 0, sizeof(link));
 796         rte_em_dev_atomic_write_link_status(dev, &link);
 797
 798         if (!rte_intr_allow_others(intr_handle))
 799                 /* resume to the default handler */
 800                 rte_intr_callback_register(intr_handle,
 801                                            eth_em_interrupt_handler,
 802                                            (void *)dev);
 803
 804         /* Clean datapath event and queue/vec mapping */
 805         rte_intr_efd_disable(intr_handle);
 806         if (intr_handle->intr_vec != NULL) {
 807                 rte_free(intr_handle->intr_vec);
 808                 intr_handle->intr_vec = NULL;
 809         }
 810 }
 811
 812 static void
 813 eth_em_close(struct rte_eth_dev *dev)
 814 {
 815         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 816         struct e1000_adapter *adapter =
 817                 E1000_DEV_PRIVATE(dev->data->dev_private);
 818
 819         eth_em_stop(dev);
 820         adapter->stopped = 1;
 821         em_dev_free_queues(dev);
 822         e1000_phy_hw_reset(hw);
 823         em_release_manageability(hw);
 824         em_hw_control_release(hw);
 825 }
 826
 827 static int
 828 em_get_rx_buffer_size(struct e1000_hw *hw)
 829 {
 830         uint32_t rx_buf_size;
 831
 832         rx_buf_size = ((E1000_READ_REG(hw, E1000_PBA) & UINT16_MAX) << 10);
 833         return rx_buf_size;
 834 }
 835
 836 /*********************************************************************
 837  *
 838  *  Initialize the hardware
 839  *
 840  **********************************************************************/
 841 static int
 842 em_hardware_init(struct e1000_hw *hw)
 843 {
 844         uint32_t rx_buf_size;
 845         int diag;
 846
 847         /* Issue a global reset */
 848         e1000_reset_hw(hw);
 849
 850         /* Let the firmware know the OS is in control */
 851         em_hw_control_acquire(hw);
 852
 853         /*
 854          * These parameters control the automatic generation (Tx) and
 855          * response (Rx) to Ethernet PAUSE frames.
 856          * - High water mark should allow for at least two standard size (1518)
 857          *   frames to be received after sending an XOFF.
 858          * - Low water mark works best when it is very near the high water mark.
 859          *   This allows the receiver to restart by sending XON when it has
 860          *   drained a bit. Here we use an arbitrary value of 1500 which will
 861          *   restart after one full frame is pulled from the buffer. There
 862          *   could be several smaller frames in the buffer and if so they will
 863          *   not trigger the XON until their total number reduces the buffer
 864          *   by 1500.
 865          * - The pause time is fairly large at 1000 x 512ns = 512 usec.
 866          */
 867         rx_buf_size = em_get_rx_buffer_size(hw);
 868
 869         hw->fc.high_water = rx_buf_size - PMD_ROUNDUP(ETHER_MAX_LEN * 2, 1024);
 870         hw->fc.low_water = hw->fc.high_water - 1500;
 871
 872         if (hw->mac.type == e1000_80003es2lan)
 873                 hw->fc.pause_time = UINT16_MAX;
 874         else
 875                 hw->fc.pause_time = EM_FC_PAUSE_TIME;
 876
 877         hw->fc.send_xon = 1;
 878
 879         /* Set Flow control, use the tunable location if sane */
 880         if (em_fc_setting <= e1000_fc_full)
 881                 hw->fc.requested_mode = em_fc_setting;
 882         else
 883                 hw->fc.requested_mode = e1000_fc_none;
 884
 885         /* Workaround: no TX flow ctrl for PCH */
 886         if (hw->mac.type == e1000_pchlan)
 887                 hw->fc.requested_mode = e1000_fc_rx_pause;
 888
 889         /* Override - settings for PCH2LAN, ya its magic :) */
 890         if (hw->mac.type == e1000_pch2lan) {
 891                 hw->fc.high_water = 0x5C20;
 892                 hw->fc.low_water = 0x5048;
 893                 hw->fc.pause_time = 0x0650;
 894                 hw->fc.refresh_time = 0x0400;
 895         } else if (hw->mac.type == e1000_pch_lpt ||
 896                    hw->mac.type == e1000_pch_spt ||
 897                    hw->mac.type == e1000_pch_cnp) {
 898                 hw->fc.requested_mode = e1000_fc_full;
 899         }
 900
 901         diag = e1000_init_hw(hw);
 902         if (diag < 0)
 903                 return diag;
 904         e1000_check_for_link(hw);
 905         return 0;
 906 }
 907
 908 /* This function is based on em_update_stats_counters() in e1000/if_em.c */
 909 static void
 910 eth_em_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *rte_stats)
 911 {
 912         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 913         struct e1000_hw_stats *stats =
 914                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
 915         int pause_frames;
 916
 917         if(hw->phy.media_type == e1000_media_type_copper ||
 918                         (E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU)) {
 919                 stats->symerrs += E1000_READ_REG(hw,E1000_SYMERRS);
 920                 stats->sec += E1000_READ_REG(hw, E1000_SEC);
 921         }
 922
 923         stats->crcerrs += E1000_READ_REG(hw, E1000_CRCERRS);
 924         stats->mpc += E1000_READ_REG(hw, E1000_MPC);
 925         stats->scc += E1000_READ_REG(hw, E1000_SCC);
 926         stats->ecol += E1000_READ_REG(hw, E1000_ECOL);
 927
 928         stats->mcc += E1000_READ_REG(hw, E1000_MCC);
 929         stats->latecol += E1000_READ_REG(hw, E1000_LATECOL);
 930         stats->colc += E1000_READ_REG(hw, E1000_COLC);
 931         stats->dc += E1000_READ_REG(hw, E1000_DC);
 932         stats->rlec += E1000_READ_REG(hw, E1000_RLEC);
 933         stats->xonrxc += E1000_READ_REG(hw, E1000_XONRXC);
 934         stats->xontxc += E1000_READ_REG(hw, E1000_XONTXC);
 935
 936         /*
 937          * For watchdog management we need to know if we have been
 938          * paused during the last interval, so capture that here.
 939          */
 940         pause_frames = E1000_READ_REG(hw, E1000_XOFFRXC);
 941         stats->xoffrxc += pause_frames;
 942         stats->xofftxc += E1000_READ_REG(hw, E1000_XOFFTXC);
 943         stats->fcruc += E1000_READ_REG(hw, E1000_FCRUC);
 944         stats->prc64 += E1000_READ_REG(hw, E1000_PRC64);
 945         stats->prc127 += E1000_READ_REG(hw, E1000_PRC127);
 946         stats->prc255 += E1000_READ_REG(hw, E1000_PRC255);
 947         stats->prc511 += E1000_READ_REG(hw, E1000_PRC511);
 948         stats->prc1023 += E1000_READ_REG(hw, E1000_PRC1023);
 949         stats->prc1522 += E1000_READ_REG(hw, E1000_PRC1522);
 950         stats->gprc += E1000_READ_REG(hw, E1000_GPRC);
 951         stats->bprc += E1000_READ_REG(hw, E1000_BPRC);
 952         stats->mprc += E1000_READ_REG(hw, E1000_MPRC);
 953         stats->gptc += E1000_READ_REG(hw, E1000_GPTC);
 954
 955         /*
 956          * For the 64-bit byte counters the low dword must be read first.
 957          * Both registers clear on the read of the high dword.
 958          */
 959
 960         stats->gorc += E1000_READ_REG(hw, E1000_GORCL);
 961         stats->gorc += ((uint64_t)E1000_READ_REG(hw, E1000_GORCH) << 32);
 962         stats->gotc += E1000_READ_REG(hw, E1000_GOTCL);
 963         stats->gotc += ((uint64_t)E1000_READ_REG(hw, E1000_GOTCH) << 32);
 964
 965         stats->rnbc += E1000_READ_REG(hw, E1000_RNBC);
 966         stats->ruc += E1000_READ_REG(hw, E1000_RUC);
 967         stats->rfc += E1000_READ_REG(hw, E1000_RFC);
 968         stats->roc += E1000_READ_REG(hw, E1000_ROC);
 969         stats->rjc += E1000_READ_REG(hw, E1000_RJC);
 970
 971         stats->tor += E1000_READ_REG(hw, E1000_TORH);
 972         stats->tot += E1000_READ_REG(hw, E1000_TOTH);
 973
 974         stats->tpr += E1000_READ_REG(hw, E1000_TPR);
 975         stats->tpt += E1000_READ_REG(hw, E1000_TPT);
 976         stats->ptc64 += E1000_READ_REG(hw, E1000_PTC64);
 977         stats->ptc127 += E1000_READ_REG(hw, E1000_PTC127);
 978         stats->ptc255 += E1000_READ_REG(hw, E1000_PTC255);
 979         stats->ptc511 += E1000_READ_REG(hw, E1000_PTC511);
 980         stats->ptc1023 += E1000_READ_REG(hw, E1000_PTC1023);
 981         stats->ptc1522 += E1000_READ_REG(hw, E1000_PTC1522);
 982         stats->mptc += E1000_READ_REG(hw, E1000_MPTC);
 983         stats->bptc += E1000_READ_REG(hw, E1000_BPTC);
 984
 985         /* Interrupt Counts */
 986
 987         if (hw->mac.type >= e1000_82571) {
 988                 stats->iac += E1000_READ_REG(hw, E1000_IAC);
 989                 stats->icrxptc += E1000_READ_REG(hw, E1000_ICRXPTC);
 990                 stats->icrxatc += E1000_READ_REG(hw, E1000_ICRXATC);
 991                 stats->ictxptc += E1000_READ_REG(hw, E1000_ICTXPTC);
 992                 stats->ictxatc += E1000_READ_REG(hw, E1000_ICTXATC);
 993                 stats->ictxqec += E1000_READ_REG(hw, E1000_ICTXQEC);
 994                 stats->ictxqmtc += E1000_READ_REG(hw, E1000_ICTXQMTC);
 995                 stats->icrxdmtc += E1000_READ_REG(hw, E1000_ICRXDMTC);
 996                 stats->icrxoc += E1000_READ_REG(hw, E1000_ICRXOC);
 997         }
 998
 999         if (hw->mac.type >= e1000_82543) {
1000                 stats->algnerrc += E1000_READ_REG(hw, E1000_ALGNERRC);
1001                 stats->rxerrc += E1000_READ_REG(hw, E1000_RXERRC);
1002                 stats->tncrs += E1000_READ_REG(hw, E1000_TNCRS);
1003                 stats->cexterr += E1000_READ_REG(hw, E1000_CEXTERR);
1004                 stats->tsctc += E1000_READ_REG(hw, E1000_TSCTC);
1005                 stats->tsctfc += E1000_READ_REG(hw, E1000_TSCTFC);
1006         }
1007
1008         if (rte_stats == NULL)
1009                 return;
1010
1011         /* Rx Errors */
1012         rte_stats->imissed = stats->mpc;
1013         rte_stats->ierrors = stats->crcerrs +
1014                              stats->rlec + stats->ruc + stats->roc +
1015                              stats->rxerrc + stats->algnerrc + stats->cexterr;
1016
1017         /* Tx Errors */
1018         rte_stats->oerrors = stats->ecol + stats->latecol;
1019
1020         rte_stats->ipackets = stats->gprc;
1021         rte_stats->opackets = stats->gptc;
1022         rte_stats->ibytes   = stats->gorc;
1023         rte_stats->obytes   = stats->gotc;
1024 }
1025
1026 static void
1027 eth_em_stats_reset(struct rte_eth_dev *dev)
1028 {
1029         struct e1000_hw_stats *hw_stats =
1030                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1031
1032         /* HW registers are cleared on read */
1033         eth_em_stats_get(dev, NULL);
1034
1035         /* Reset software totals */
1036         memset(hw_stats, 0, sizeof(*hw_stats));
1037 }
1038
1039 static int
1040 eth_em_rx_queue_intr_enable(struct rte_eth_dev *dev, __rte_unused uint16_t queue_id)
1041 {
1042         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1043         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1044         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1045
1046         em_rxq_intr_enable(hw);
1047         rte_intr_enable(intr_handle);
1048
1049         return 0;
1050 }
1051
1052 static int
1053 eth_em_rx_queue_intr_disable(struct rte_eth_dev *dev, __rte_unused uint16_t queue_id)
1054 {
1055         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1056
1057         em_rxq_intr_disable(hw);
1058
1059         return 0;
1060 }
1061
1062 static uint32_t
1063 em_get_max_pktlen(const struct e1000_hw *hw)
1064 {
1065         switch (hw->mac.type) {
1066         case e1000_82571:
1067         case e1000_82572:
1068         case e1000_ich9lan:
1069         case e1000_ich10lan:
1070         case e1000_pch2lan:
1071         case e1000_pch_lpt:
1072         case e1000_pch_spt:
1073         case e1000_pch_cnp:
1074         case e1000_82574:
1075         case e1000_80003es2lan: /* 9K Jumbo Frame size */
1076         case e1000_82583:
1077                 return 0x2412;
1078         case e1000_pchlan:
1079                 return 0x1000;
1080         /* Adapters that do not support jumbo frames */
1081         case e1000_ich8lan:
1082                 return ETHER_MAX_LEN;
1083         default:
1084                 return MAX_JUMBO_FRAME_SIZE;
1085         }
1086 }
1087
1088 static void
1089 eth_em_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
1090 {
1091         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1092
1093         dev_info->pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1094         dev_info->min_rx_bufsize = 256; /* See BSIZE field of RCTL register. */
1095         dev_info->max_rx_pktlen = em_get_max_pktlen(hw);
1096         dev_info->max_mac_addrs = hw->mac.rar_entry_count;
1097         dev_info->rx_offload_capa =
1098                 DEV_RX_OFFLOAD_VLAN_STRIP |
1099                 DEV_RX_OFFLOAD_IPV4_CKSUM |
1100                 DEV_RX_OFFLOAD_UDP_CKSUM  |
1101                 DEV_RX_OFFLOAD_TCP_CKSUM;
1102         dev_info->tx_offload_capa =
1103                 DEV_TX_OFFLOAD_VLAN_INSERT |
1104                 DEV_TX_OFFLOAD_IPV4_CKSUM  |
1105                 DEV_TX_OFFLOAD_UDP_CKSUM   |
1106                 DEV_TX_OFFLOAD_TCP_CKSUM;
1107
1108         /*
1109          * Starting with 631xESB hw supports 2 TX/RX queues per port.
1110          * Unfortunatelly, all these nics have just one TX context.
1111          * So we have few choises for TX:
1112          * - Use just one TX queue.
1113          * - Allow cksum offload only for one TX queue.
1114          * - Don't allow TX cksum offload at all.
1115          * For now, option #1 was chosen.
1116          * To use second RX queue we have to use extended RX descriptor
1117          * (Multiple Receive Queues are mutually exclusive with UDP
1118          * fragmentation and are not supported when a legacy receive
1119          * descriptor format is used).
1120          * Which means separate RX routinies - as legacy nics (82540, 82545)
1121          * don't support extended RXD.
1122          * To avoid it we support just one RX queue for now (no RSS).
1123          */
1124
1125         dev_info->max_rx_queues = 1;
1126         dev_info->max_tx_queues = 1;
1127
1128         dev_info->rx_desc_lim = (struct rte_eth_desc_lim) {
1129                 .nb_max = E1000_MAX_RING_DESC,
1130                 .nb_min = E1000_MIN_RING_DESC,
1131                 .nb_align = EM_RXD_ALIGN,
1132         };
1133
1134         dev_info->tx_desc_lim = (struct rte_eth_desc_lim) {
1135                 .nb_max = E1000_MAX_RING_DESC,
1136                 .nb_min = E1000_MIN_RING_DESC,
1137                 .nb_align = EM_TXD_ALIGN,
1138                 .nb_seg_max = EM_TX_MAX_SEG,
1139                 .nb_mtu_seg_max = EM_TX_MAX_MTU_SEG,
1140         };
1141
1142         dev_info->speed_capa = ETH_LINK_SPEED_10M_HD | ETH_LINK_SPEED_10M |
1143                         ETH_LINK_SPEED_100M_HD | ETH_LINK_SPEED_100M |
1144                         ETH_LINK_SPEED_1G;
1145 }
1146
1147 /* return 0 means link status changed, -1 means not changed */
1148 static int
1149 eth_em_link_update(struct rte_eth_dev *dev, int wait_to_complete)
1150 {
1151         struct e1000_hw *hw =
1152                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1153         struct rte_eth_link link, old;
1154         int link_check, count;
1155
1156         link_check = 0;
1157         hw->mac.get_link_status = 1;
1158
1159         /* possible wait-to-complete in up to 9 seconds */
1160         for (count = 0; count < EM_LINK_UPDATE_CHECK_TIMEOUT; count ++) {
1161                 /* Read the real link status */
1162                 switch (hw->phy.media_type) {
1163                 case e1000_media_type_copper:
1164                         /* Do the work to read phy */
1165                         e1000_check_for_link(hw);
1166                         link_check = !hw->mac.get_link_status;
1167                         break;
1168
1169                 case e1000_media_type_fiber:
1170                         e1000_check_for_link(hw);
1171                         link_check = (E1000_READ_REG(hw, E1000_STATUS) &
1172                                         E1000_STATUS_LU);
1173                         break;
1174
1175                 case e1000_media_type_internal_serdes:
1176                         e1000_check_for_link(hw);
1177                         link_check = hw->mac.serdes_has_link;
1178                         break;
1179
1180                 default:
1181                         break;
1182                 }
1183                 if (link_check || wait_to_complete == 0)
1184                         break;
1185                 rte_delay_ms(EM_LINK_UPDATE_CHECK_INTERVAL);
1186         }
1187         memset(&link, 0, sizeof(link));
1188         rte_em_dev_atomic_read_link_status(dev, &link);
1189         old = link;
1190
1191         /* Now we check if a transition has happened */
1192         if (link_check && (link.link_status == ETH_LINK_DOWN)) {
1193                 uint16_t duplex, speed;
1194                 hw->mac.ops.get_link_up_info(hw, &speed, &duplex);
1195                 link.link_duplex = (duplex == FULL_DUPLEX) ?
1196                                 ETH_LINK_FULL_DUPLEX :
1197                                 ETH_LINK_HALF_DUPLEX;
1198                 link.link_speed = speed;
1199                 link.link_status = ETH_LINK_UP;
1200                 link.link_autoneg = !(dev->data->dev_conf.link_speeds &
1201                                 ETH_LINK_SPEED_FIXED);
1202         } else if (!link_check && (link.link_status == ETH_LINK_UP)) {
1203                 link.link_speed = 0;
1204                 link.link_duplex = ETH_LINK_HALF_DUPLEX;
1205                 link.link_status = ETH_LINK_DOWN;
1206                 link.link_autoneg = ETH_LINK_SPEED_FIXED;
1207         }
1208         rte_em_dev_atomic_write_link_status(dev, &link);
1209
1210         /* not changed */
1211         if (old.link_status == link.link_status)
1212                 return -1;
1213
1214         /* changed */
1215         return 0;
1216 }
1217
1218 /*
1219  * em_hw_control_acquire sets {CTRL_EXT|FWSM}:DRV_LOAD bit.
1220  * For ASF and Pass Through versions of f/w this means
1221  * that the driver is loaded. For AMT version type f/w
1222  * this means that the network i/f is open.
1223  */
1224 static void
1225 em_hw_control_acquire(struct e1000_hw *hw)
1226 {
1227         uint32_t ctrl_ext, swsm;
1228
1229         /* Let firmware know the driver has taken over */
1230         if (hw->mac.type == e1000_82573) {
1231                 swsm = E1000_READ_REG(hw, E1000_SWSM);
1232                 E1000_WRITE_REG(hw, E1000_SWSM, swsm | E1000_SWSM_DRV_LOAD);
1233
1234         } else {
1235                 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
1236                 E1000_WRITE_REG(hw, E1000_CTRL_EXT,
1237                         ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
1238         }
1239 }
1240
1241 /*
1242  * em_hw_control_release resets {CTRL_EXTT|FWSM}:DRV_LOAD bit.
1243  * For ASF and Pass Through versions of f/w this means that the
1244  * driver is no longer loaded. For AMT versions of the
1245  * f/w this means that the network i/f is closed.
1246  */
1247 static void
1248 em_hw_control_release(struct e1000_hw *hw)
1249 {
1250         uint32_t ctrl_ext, swsm;
1251
1252         /* Let firmware taken over control of h/w */
1253         if (hw->mac.type == e1000_82573) {
1254                 swsm = E1000_READ_REG(hw, E1000_SWSM);
1255                 E1000_WRITE_REG(hw, E1000_SWSM, swsm & ~E1000_SWSM_DRV_LOAD);
1256         } else {
1257                 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
1258                 E1000_WRITE_REG(hw, E1000_CTRL_EXT,
1259                         ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
1260         }
1261 }
1262
1263 /*
1264  * Bit of a misnomer, what this really means is
1265  * to enable OS management of the system... aka
1266  * to disable special hardware management features.
1267  */
1268 static void
1269 em_init_manageability(struct e1000_hw *hw)
1270 {
1271         if (e1000_enable_mng_pass_thru(hw)) {
1272                 uint32_t manc2h = E1000_READ_REG(hw, E1000_MANC2H);
1273                 uint32_t manc = E1000_READ_REG(hw, E1000_MANC);
1274
1275                 /* disable hardware interception of ARP */
1276                 manc &= ~(E1000_MANC_ARP_EN);
1277
1278                 /* enable receiving management packets to the host */
1279                 manc |= E1000_MANC_EN_MNG2HOST;
1280                 manc2h |= 1 << 5;  /* Mng Port 623 */
1281                 manc2h |= 1 << 6;  /* Mng Port 664 */
1282                 E1000_WRITE_REG(hw, E1000_MANC2H, manc2h);
1283                 E1000_WRITE_REG(hw, E1000_MANC, manc);
1284         }
1285 }
1286
1287 /*
1288  * Give control back to hardware management
1289  * controller if there is one.
1290  */
1291 static void
1292 em_release_manageability(struct e1000_hw *hw)
1293 {
1294         uint32_t manc;
1295
1296         if (e1000_enable_mng_pass_thru(hw)) {
1297                 manc = E1000_READ_REG(hw, E1000_MANC);
1298
1299                 /* re-enable hardware interception of ARP */
1300                 manc |= E1000_MANC_ARP_EN;
1301                 manc &= ~E1000_MANC_EN_MNG2HOST;
1302
1303                 E1000_WRITE_REG(hw, E1000_MANC, manc);
1304         }
1305 }
1306
1307 static void
1308 eth_em_promiscuous_enable(struct rte_eth_dev *dev)
1309 {
1310         struct e1000_hw *hw =
1311                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1312         uint32_t rctl;
1313
1314         rctl = E1000_READ_REG(hw, E1000_RCTL);
1315         rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
1316         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1317 }
1318
1319 static void
1320 eth_em_promiscuous_disable(struct rte_eth_dev *dev)
1321 {
1322         struct e1000_hw *hw =
1323                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1324         uint32_t rctl;
1325
1326         rctl = E1000_READ_REG(hw, E1000_RCTL);
1327         rctl &= ~(E1000_RCTL_UPE | E1000_RCTL_SBP);
1328         if (dev->data->all_multicast == 1)
1329                 rctl |= E1000_RCTL_MPE;
1330         else
1331                 rctl &= (~E1000_RCTL_MPE);
1332         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1333 }
1334
1335 static void
1336 eth_em_allmulticast_enable(struct rte_eth_dev *dev)
1337 {
1338         struct e1000_hw *hw =
1339                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1340         uint32_t rctl;
1341
1342         rctl = E1000_READ_REG(hw, E1000_RCTL);
1343         rctl |= E1000_RCTL_MPE;
1344         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1345 }
1346
1347 static void
1348 eth_em_allmulticast_disable(struct rte_eth_dev *dev)
1349 {
1350         struct e1000_hw *hw =
1351                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1352         uint32_t rctl;
1353
1354         if (dev->data->promiscuous == 1)
1355                 return; /* must remain in all_multicast mode */
1356         rctl = E1000_READ_REG(hw, E1000_RCTL);
1357         rctl &= (~E1000_RCTL_MPE);
1358         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1359 }
1360
1361 static int
1362 eth_em_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1363 {
1364         struct e1000_hw *hw =
1365                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1366         struct e1000_vfta * shadow_vfta =
1367                 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1368         uint32_t vfta;
1369         uint32_t vid_idx;
1370         uint32_t vid_bit;
1371
1372         vid_idx = (uint32_t) ((vlan_id >> E1000_VFTA_ENTRY_SHIFT) &
1373                               E1000_VFTA_ENTRY_MASK);
1374         vid_bit = (uint32_t) (1 << (vlan_id & E1000_VFTA_ENTRY_BIT_SHIFT_MASK));
1375         vfta = E1000_READ_REG_ARRAY(hw, E1000_VFTA, vid_idx);
1376         if (on)
1377                 vfta |= vid_bit;
1378         else
1379                 vfta &= ~vid_bit;
1380         E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, vid_idx, vfta);
1381
1382         /* update local VFTA copy */
1383         shadow_vfta->vfta[vid_idx] = vfta;
1384
1385         return 0;
1386 }
1387
1388 static void
1389 em_vlan_hw_filter_disable(struct rte_eth_dev *dev)
1390 {
1391         struct e1000_hw *hw =
1392                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1393         uint32_t reg;
1394
1395         /* Filter Table Disable */
1396         reg = E1000_READ_REG(hw, E1000_RCTL);
1397         reg &= ~E1000_RCTL_CFIEN;
1398         reg &= ~E1000_RCTL_VFE;
1399         E1000_WRITE_REG(hw, E1000_RCTL, reg);
1400 }
1401
1402 static void
1403 em_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1404 {
1405         struct e1000_hw *hw =
1406                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1407         struct e1000_vfta * shadow_vfta =
1408                 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1409         uint32_t reg;
1410         int i;
1411
1412         /* Filter Table Enable, CFI not used for packet acceptance */
1413         reg = E1000_READ_REG(hw, E1000_RCTL);
1414         reg &= ~E1000_RCTL_CFIEN;
1415         reg |= E1000_RCTL_VFE;
1416         E1000_WRITE_REG(hw, E1000_RCTL, reg);
1417
1418         /* restore vfta from local copy */
1419         for (i = 0; i < IGB_VFTA_SIZE; i++)
1420                 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, i, shadow_vfta->vfta[i]);
1421 }
1422
1423 static void
1424 em_vlan_hw_strip_disable(struct rte_eth_dev *dev)
1425 {
1426         struct e1000_hw *hw =
1427                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1428         uint32_t reg;
1429
1430         /* VLAN Mode Disable */
1431         reg = E1000_READ_REG(hw, E1000_CTRL);
1432         reg &= ~E1000_CTRL_VME;
1433         E1000_WRITE_REG(hw, E1000_CTRL, reg);
1434
1435 }
1436
1437 static void
1438 em_vlan_hw_strip_enable(struct rte_eth_dev *dev)
1439 {
1440         struct e1000_hw *hw =
1441                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1442         uint32_t reg;
1443
1444         /* VLAN Mode Enable */
1445         reg = E1000_READ_REG(hw, E1000_CTRL);
1446         reg |= E1000_CTRL_VME;
1447         E1000_WRITE_REG(hw, E1000_CTRL, reg);
1448 }
1449
1450 static void
1451 eth_em_vlan_offload_set(struct rte_eth_dev *dev, int mask)
1452 {
1453         if(mask & ETH_VLAN_STRIP_MASK){
1454                 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
1455                         em_vlan_hw_strip_enable(dev);
1456                 else
1457                         em_vlan_hw_strip_disable(dev);
1458         }
1459
1460         if(mask & ETH_VLAN_FILTER_MASK){
1461                 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
1462                         em_vlan_hw_filter_enable(dev);
1463                 else
1464                         em_vlan_hw_filter_disable(dev);
1465         }
1466 }
1467
1468 /*
1469  * It enables the interrupt mask and then enable the interrupt.
1470  *
1471  * @param dev
1472  *  Pointer to struct rte_eth_dev.
1473  *
1474  * @return
1475  *  - On success, zero.
1476  *  - On failure, a negative value.
1477  */
1478 static int
1479 eth_em_interrupt_setup(struct rte_eth_dev *dev)
1480 {
1481         uint32_t regval;
1482         struct e1000_hw *hw =
1483                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1484
1485         /* clear interrupt */
1486         E1000_READ_REG(hw, E1000_ICR);
1487         regval = E1000_READ_REG(hw, E1000_IMS);
1488         E1000_WRITE_REG(hw, E1000_IMS, regval | E1000_ICR_LSC);
1489         return 0;
1490 }
1491
1492 /*
1493  * It clears the interrupt causes and enables the interrupt.
1494  * It will be called once only during nic initialized.
1495  *
1496  * @param dev
1497  *  Pointer to struct rte_eth_dev.
1498  *
1499  * @return
1500  *  - On success, zero.
1501  *  - On failure, a negative value.
1502  */
1503 static int
1504 eth_em_rxq_interrupt_setup(struct rte_eth_dev *dev)
1505 {
1506         struct e1000_hw *hw =
1507         E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1508
1509         E1000_READ_REG(hw, E1000_ICR);
1510         em_rxq_intr_enable(hw);
1511         return 0;
1512 }
1513
1514 /*
1515  * It enable receive packet interrupt.
1516  * @param hw
1517  * Pointer to struct e1000_hw
1518  *
1519  * @return
1520  */
1521 static void
1522 em_rxq_intr_enable(struct e1000_hw *hw)
1523 {
1524         E1000_WRITE_REG(hw, E1000_IMS, E1000_IMS_RXT0);
1525         E1000_WRITE_FLUSH(hw);
1526 }
1527
1528 /*
1529  * It disabled lsc interrupt.
1530  * @param hw
1531  * Pointer to struct e1000_hw
1532  *
1533  * @return
1534  */
1535 static void
1536 em_lsc_intr_disable(struct e1000_hw *hw)
1537 {
1538         E1000_WRITE_REG(hw, E1000_IMC, E1000_IMS_LSC);
1539         E1000_WRITE_FLUSH(hw);
1540 }
1541
1542 /*
1543  * It disabled receive packet interrupt.
1544  * @param hw
1545  * Pointer to struct e1000_hw
1546  *
1547  * @return
1548  */
1549 static void
1550 em_rxq_intr_disable(struct e1000_hw *hw)
1551 {
1552         E1000_READ_REG(hw, E1000_ICR);
1553         E1000_WRITE_REG(hw, E1000_IMC, E1000_IMS_RXT0);
1554         E1000_WRITE_FLUSH(hw);
1555 }
1556
1557 /*
1558  * It reads ICR and gets interrupt causes, check it and set a bit flag
1559  * to update link status.
1560  *
1561  * @param dev
1562  *  Pointer to struct rte_eth_dev.
1563  *
1564  * @return
1565  *  - On success, zero.
1566  *  - On failure, a negative value.
1567  */
1568 static int
1569 eth_em_interrupt_get_status(struct rte_eth_dev *dev)
1570 {
1571         uint32_t icr;
1572         struct e1000_hw *hw =
1573                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1574         struct e1000_interrupt *intr =
1575                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
1576
1577         /* read-on-clear nic registers here */
1578         icr = E1000_READ_REG(hw, E1000_ICR);
1579         if (icr & E1000_ICR_LSC) {
1580                 intr->flags |= E1000_FLAG_NEED_LINK_UPDATE;
1581         }
1582
1583         return 0;
1584 }
1585
1586 /*
1587  * It executes link_update after knowing an interrupt is prsent.
1588  *
1589  * @param dev
1590  *  Pointer to struct rte_eth_dev.
1591  *
1592  * @return
1593  *  - On success, zero.
1594  *  - On failure, a negative value.
1595  */
1596 static int
1597 eth_em_interrupt_action(struct rte_eth_dev *dev,
1598                         struct rte_intr_handle *intr_handle)
1599 {
1600         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1601         struct e1000_hw *hw =
1602                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1603         struct e1000_interrupt *intr =
1604                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
1605         uint32_t tctl, rctl;
1606         struct rte_eth_link link;
1607         int ret;
1608
1609         if (!(intr->flags & E1000_FLAG_NEED_LINK_UPDATE))
1610                 return -1;
1611
1612         intr->flags &= ~E1000_FLAG_NEED_LINK_UPDATE;
1613         rte_intr_enable(intr_handle);
1614
1615         /* set get_link_status to check register later */
1616         hw->mac.get_link_status = 1;
1617         ret = eth_em_link_update(dev, 0);
1618
1619         /* check if link has changed */
1620         if (ret < 0)
1621                 return 0;
1622
1623         memset(&link, 0, sizeof(link));
1624         rte_em_dev_atomic_read_link_status(dev, &link);
1625         if (link.link_status) {
1626                 PMD_INIT_LOG(INFO, " Port %d: Link Up - speed %u Mbps - %s",
1627                              dev->data->port_id, (unsigned)link.link_speed,
1628                              link.link_duplex == ETH_LINK_FULL_DUPLEX ?
1629                              "full-duplex" : "half-duplex");
1630         } else {
1631                 PMD_INIT_LOG(INFO, " Port %d: Link Down", dev->data->port_id);
1632         }
1633         PMD_INIT_LOG(DEBUG, "PCI Address: %04d:%02d:%02d:%d",
1634                      pci_dev->addr.domain, pci_dev->addr.bus,
1635                      pci_dev->addr.devid, pci_dev->addr.function);
1636
1637         tctl = E1000_READ_REG(hw, E1000_TCTL);
1638         rctl = E1000_READ_REG(hw, E1000_RCTL);
1639         if (link.link_status) {
1640                 /* enable Tx/Rx */
1641                 tctl |= E1000_TCTL_EN;
1642                 rctl |= E1000_RCTL_EN;
1643         } else {
1644                 /* disable Tx/Rx */
1645                 tctl &= ~E1000_TCTL_EN;
1646                 rctl &= ~E1000_RCTL_EN;
1647         }
1648         E1000_WRITE_REG(hw, E1000_TCTL, tctl);
1649         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1650         E1000_WRITE_FLUSH(hw);
1651
1652         return 0;
1653 }
1654
1655 /**
1656  * Interrupt handler which shall be registered at first.
1657  *
1658  * @param handle
1659  *  Pointer to interrupt handle.
1660  * @param param
1661  *  The address of parameter (struct rte_eth_dev *) regsitered before.
1662  *
1663  * @return
1664  *  void
1665  */
1666 static void
1667 eth_em_interrupt_handler(void *param)
1668 {
1669         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
1670
1671         eth_em_interrupt_get_status(dev);
1672         eth_em_interrupt_action(dev, dev->intr_handle);
1673         _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC, NULL, NULL);
1674 }
1675
1676 static int
1677 eth_em_led_on(struct rte_eth_dev *dev)
1678 {
1679         struct e1000_hw *hw;
1680
1681         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1682         return e1000_led_on(hw) == E1000_SUCCESS ? 0 : -ENOTSUP;
1683 }
1684
1685 static int
1686 eth_em_led_off(struct rte_eth_dev *dev)
1687 {
1688         struct e1000_hw *hw;
1689
1690         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1691         return e1000_led_off(hw) == E1000_SUCCESS ? 0 : -ENOTSUP;
1692 }
1693
1694 static int
1695 eth_em_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
1696 {
1697         struct e1000_hw *hw;
1698         uint32_t ctrl;
1699         int tx_pause;
1700         int rx_pause;
1701
1702         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1703         fc_conf->pause_time = hw->fc.pause_time;
1704         fc_conf->high_water = hw->fc.high_water;
1705         fc_conf->low_water = hw->fc.low_water;
1706         fc_conf->send_xon = hw->fc.send_xon;
1707         fc_conf->autoneg = hw->mac.autoneg;
1708
1709         /*
1710          * Return rx_pause and tx_pause status according to actual setting of
1711          * the TFCE and RFCE bits in the CTRL register.
1712          */
1713         ctrl = E1000_READ_REG(hw, E1000_CTRL);
1714         if (ctrl & E1000_CTRL_TFCE)
1715                 tx_pause = 1;
1716         else
1717                 tx_pause = 0;
1718
1719         if (ctrl & E1000_CTRL_RFCE)
1720                 rx_pause = 1;
1721         else
1722                 rx_pause = 0;
1723
1724         if (rx_pause && tx_pause)
1725                 fc_conf->mode = RTE_FC_FULL;
1726         else if (rx_pause)
1727                 fc_conf->mode = RTE_FC_RX_PAUSE;
1728         else if (tx_pause)
1729                 fc_conf->mode = RTE_FC_TX_PAUSE;
1730         else
1731                 fc_conf->mode = RTE_FC_NONE;
1732
1733         return 0;
1734 }
1735
1736 static int
1737 eth_em_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
1738 {
1739         struct e1000_hw *hw;
1740         int err;
1741         enum e1000_fc_mode rte_fcmode_2_e1000_fcmode[] = {
1742                 e1000_fc_none,
1743                 e1000_fc_rx_pause,
1744                 e1000_fc_tx_pause,
1745                 e1000_fc_full
1746         };
1747         uint32_t rx_buf_size;
1748         uint32_t max_high_water;
1749         uint32_t rctl;
1750
1751         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1752         if (fc_conf->autoneg != hw->mac.autoneg)
1753                 return -ENOTSUP;
1754         rx_buf_size = em_get_rx_buffer_size(hw);
1755         PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
1756
1757         /* At least reserve one Ethernet frame for watermark */
1758         max_high_water = rx_buf_size - ETHER_MAX_LEN;
1759         if ((fc_conf->high_water > max_high_water) ||
1760             (fc_conf->high_water < fc_conf->low_water)) {
1761                 PMD_INIT_LOG(ERR, "e1000 incorrect high/low water value");
1762                 PMD_INIT_LOG(ERR, "high water must <= 0x%x", max_high_water);
1763                 return -EINVAL;
1764         }
1765
1766         hw->fc.requested_mode = rte_fcmode_2_e1000_fcmode[fc_conf->mode];
1767         hw->fc.pause_time     = fc_conf->pause_time;
1768         hw->fc.high_water     = fc_conf->high_water;
1769         hw->fc.low_water      = fc_conf->low_water;
1770         hw->fc.send_xon       = fc_conf->send_xon;
1771
1772         err = e1000_setup_link_generic(hw);
1773         if (err == E1000_SUCCESS) {
1774
1775                 /* check if we want to forward MAC frames - driver doesn't have native
1776                  * capability to do that, so we'll write the registers ourselves */
1777
1778                 rctl = E1000_READ_REG(hw, E1000_RCTL);
1779
1780                 /* set or clear MFLCN.PMCF bit depending on configuration */
1781                 if (fc_conf->mac_ctrl_frame_fwd != 0)
1782                         rctl |= E1000_RCTL_PMCF;
1783                 else
1784                         rctl &= ~E1000_RCTL_PMCF;
1785
1786                 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1787                 E1000_WRITE_FLUSH(hw);
1788
1789                 return 0;
1790         }
1791
1792         PMD_INIT_LOG(ERR, "e1000_setup_link_generic = 0x%x", err);
1793         return -EIO;
1794 }
1795
1796 static int
1797 eth_em_rar_set(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
1798                 uint32_t index, __rte_unused uint32_t pool)
1799 {
1800         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1801
1802         return e1000_rar_set(hw, mac_addr->addr_bytes, index);
1803 }
1804
1805 static void
1806 eth_em_rar_clear(struct rte_eth_dev *dev, uint32_t index)
1807 {
1808         uint8_t addr[ETHER_ADDR_LEN];
1809         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1810
1811         memset(addr, 0, sizeof(addr));
1812
1813         e1000_rar_set(hw, addr, index);
1814 }
1815
1816 static int
1817 eth_em_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
1818 {
1819         struct rte_eth_dev_info dev_info;
1820         struct e1000_hw *hw;
1821         uint32_t frame_size;
1822         uint32_t rctl;
1823
1824         eth_em_infos_get(dev, &dev_info);
1825         frame_size = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN + VLAN_TAG_SIZE;
1826
1827         /* check that mtu is within the allowed range */
1828         if ((mtu < ETHER_MIN_MTU) || (frame_size > dev_info.max_rx_pktlen))
1829                 return -EINVAL;
1830
1831         /* refuse mtu that requires the support of scattered packets when this
1832          * feature has not been enabled before. */
1833         if (!dev->data->scattered_rx &&
1834             frame_size > dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)
1835                 return -EINVAL;
1836
1837         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1838         rctl = E1000_READ_REG(hw, E1000_RCTL);
1839
1840         /* switch to jumbo mode if needed */
1841         if (frame_size > ETHER_MAX_LEN) {
1842                 dev->data->dev_conf.rxmode.jumbo_frame = 1;
1843                 rctl |= E1000_RCTL_LPE;
1844         } else {
1845                 dev->data->dev_conf.rxmode.jumbo_frame = 0;
1846                 rctl &= ~E1000_RCTL_LPE;
1847         }
1848         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1849
1850         /* update max frame size */
1851         dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
1852         return 0;
1853 }
1854
1855 static int
1856 eth_em_set_mc_addr_list(struct rte_eth_dev *dev,
1857                         struct ether_addr *mc_addr_set,
1858                         uint32_t nb_mc_addr)
1859 {
1860         struct e1000_hw *hw;
1861
1862         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1863         e1000_update_mc_addr_list(hw, (u8 *)mc_addr_set, nb_mc_addr);
1864         return 0;
1865 }
1866
1867 RTE_PMD_REGISTER_PCI(net_e1000_em, rte_em_pmd);
1868 RTE_PMD_REGISTER_PCI_TABLE(net_e1000_em, pci_id_em_map);
1869 RTE_PMD_REGISTER_KMOD_DEP(net_e1000_em, "* igb_uio | uio_pci_generic | vfio-pci");