drivers/net/e1000/em_ethdev.c

   1 /*-
   2  *   BSD LICENSE
   3  *
   4  *   Copyright(c) 2010-2015 Intel Corporation. All rights reserved.
   5  *   All rights reserved.
   6  *
   7  *   Redistribution and use in source and binary forms, with or without
   8  *   modification, are permitted provided that the following conditions
   9  *   are met:
  10  *
  11  *     * Redistributions of source code must retain the above copyright
  12  *       notice, this list of conditions and the following disclaimer.
  13  *     * Redistributions in binary form must reproduce the above copyright
  14  *       notice, this list of conditions and the following disclaimer in
  15  *       the documentation and/or other materials provided with the
  16  *       distribution.
  17  *     * Neither the name of Intel Corporation nor the names of its
  18  *       contributors may be used to endorse or promote products derived
  19  *       from this software without specific prior written permission.
  20  *
  21  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 #include <sys/queue.h>
  35 #include <stdio.h>
  36 #include <errno.h>
  37 #include <stdint.h>
  38 #include <stdarg.h>
  39
  40 #include <rte_common.h>
  41 #include <rte_interrupts.h>
  42 #include <rte_byteorder.h>
  43 #include <rte_log.h>
  44 #include <rte_debug.h>
  45 #include <rte_pci.h>
  46 #include <rte_ether.h>
  47 #include <rte_ethdev.h>
  48 #include <rte_memory.h>
  49 #include <rte_memzone.h>
  50 #include <rte_eal.h>
  51 #include <rte_atomic.h>
  52 #include <rte_malloc.h>
  53 #include <rte_dev.h>
  54
  55 #include "e1000_logs.h"
  56 #include "base/e1000_api.h"
  57 #include "e1000_ethdev.h"
  58
  59 #define EM_EIAC                 0x000DC
  60
  61 #define PMD_ROUNDUP(x,y)        (((x) + (y) - 1)/(y) * (y))
  62
  63
  64 static int eth_em_configure(struct rte_eth_dev *dev);
  65 static int eth_em_start(struct rte_eth_dev *dev);
  66 static void eth_em_stop(struct rte_eth_dev *dev);
  67 static void eth_em_close(struct rte_eth_dev *dev);
  68 static void eth_em_promiscuous_enable(struct rte_eth_dev *dev);
  69 static void eth_em_promiscuous_disable(struct rte_eth_dev *dev);
  70 static void eth_em_allmulticast_enable(struct rte_eth_dev *dev);
  71 static void eth_em_allmulticast_disable(struct rte_eth_dev *dev);
  72 static int eth_em_link_update(struct rte_eth_dev *dev,
  73                                 int wait_to_complete);
  74 static void eth_em_stats_get(struct rte_eth_dev *dev,
  75                                 struct rte_eth_stats *rte_stats);
  76 static void eth_em_stats_reset(struct rte_eth_dev *dev);
  77 static void eth_em_infos_get(struct rte_eth_dev *dev,
  78                                 struct rte_eth_dev_info *dev_info);
  79 static int eth_em_flow_ctrl_get(struct rte_eth_dev *dev,
  80                                 struct rte_eth_fc_conf *fc_conf);
  81 static int eth_em_flow_ctrl_set(struct rte_eth_dev *dev,
  82                                 struct rte_eth_fc_conf *fc_conf);
  83 static int eth_em_interrupt_setup(struct rte_eth_dev *dev);
  84 static int eth_em_rxq_interrupt_setup(struct rte_eth_dev *dev);
  85 static int eth_em_interrupt_get_status(struct rte_eth_dev *dev);
  86 static int eth_em_interrupt_action(struct rte_eth_dev *dev);
  87 static void eth_em_interrupt_handler(struct rte_intr_handle *handle,
  88                                                         void *param);
  89
  90 static int em_hw_init(struct e1000_hw *hw);
  91 static int em_hardware_init(struct e1000_hw *hw);
  92 static void em_hw_control_acquire(struct e1000_hw *hw);
  93 static void em_hw_control_release(struct e1000_hw *hw);
  94 static void em_init_manageability(struct e1000_hw *hw);
  95 static void em_release_manageability(struct e1000_hw *hw);
  96
  97 static int eth_em_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
  98
  99 static int eth_em_vlan_filter_set(struct rte_eth_dev *dev,
 100                 uint16_t vlan_id, int on);
 101 static void eth_em_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 102 static void em_vlan_hw_filter_enable(struct rte_eth_dev *dev);
 103 static void em_vlan_hw_filter_disable(struct rte_eth_dev *dev);
 104 static void em_vlan_hw_strip_enable(struct rte_eth_dev *dev);
 105 static void em_vlan_hw_strip_disable(struct rte_eth_dev *dev);
 106
 107 /*
 108 static void eth_em_vlan_filter_set(struct rte_eth_dev *dev,
 109                                         uint16_t vlan_id, int on);
 110 */
 111
 112 static int eth_em_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id);
 113 static int eth_em_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id);
 114 static void em_lsc_intr_disable(struct e1000_hw *hw);
 115 static void em_rxq_intr_enable(struct e1000_hw *hw);
 116 static void em_rxq_intr_disable(struct e1000_hw *hw);
 117
 118 static int eth_em_led_on(struct rte_eth_dev *dev);
 119 static int eth_em_led_off(struct rte_eth_dev *dev);
 120
 121 static int em_get_rx_buffer_size(struct e1000_hw *hw);
 122 static void eth_em_rar_set(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
 123                 uint32_t index, uint32_t pool);
 124 static void eth_em_rar_clear(struct rte_eth_dev *dev, uint32_t index);
 125
 126 static int eth_em_set_mc_addr_list(struct rte_eth_dev *dev,
 127                                    struct ether_addr *mc_addr_set,
 128                                    uint32_t nb_mc_addr);
 129
 130 #define EM_FC_PAUSE_TIME 0x0680
 131 #define EM_LINK_UPDATE_CHECK_TIMEOUT  90  /* 9s */
 132 #define EM_LINK_UPDATE_CHECK_INTERVAL 100 /* ms */
 133
 134 static enum e1000_fc_mode em_fc_setting = e1000_fc_full;
 135
 136 /*
 137  * The set of PCI devices this driver supports
 138  */
 139 static const struct rte_pci_id pci_id_em_map[] = {
 140
 141 #define RTE_PCI_DEV_ID_DECL_EM(vend, dev) {RTE_PCI_DEVICE(vend, dev)},
 142 #include "rte_pci_dev_ids.h"
 143
 144 {0},
 145 };
 146
 147 static const struct eth_dev_ops eth_em_ops = {
 148         .dev_configure        = eth_em_configure,
 149         .dev_start            = eth_em_start,
 150         .dev_stop             = eth_em_stop,
 151         .dev_close            = eth_em_close,
 152         .promiscuous_enable   = eth_em_promiscuous_enable,
 153         .promiscuous_disable  = eth_em_promiscuous_disable,
 154         .allmulticast_enable  = eth_em_allmulticast_enable,
 155         .allmulticast_disable = eth_em_allmulticast_disable,
 156         .link_update          = eth_em_link_update,
 157         .stats_get            = eth_em_stats_get,
 158         .stats_reset          = eth_em_stats_reset,
 159         .dev_infos_get        = eth_em_infos_get,
 160         .mtu_set              = eth_em_mtu_set,
 161         .vlan_filter_set      = eth_em_vlan_filter_set,
 162         .vlan_offload_set     = eth_em_vlan_offload_set,
 163         .rx_queue_setup       = eth_em_rx_queue_setup,
 164         .rx_queue_release     = eth_em_rx_queue_release,
 165         .rx_queue_count       = eth_em_rx_queue_count,
 166         .rx_descriptor_done   = eth_em_rx_descriptor_done,
 167         .tx_queue_setup       = eth_em_tx_queue_setup,
 168         .tx_queue_release     = eth_em_tx_queue_release,
 169         .rx_queue_intr_enable = eth_em_rx_queue_intr_enable,
 170         .rx_queue_intr_disable = eth_em_rx_queue_intr_disable,
 171         .dev_led_on           = eth_em_led_on,
 172         .dev_led_off          = eth_em_led_off,
 173         .flow_ctrl_get        = eth_em_flow_ctrl_get,
 174         .flow_ctrl_set        = eth_em_flow_ctrl_set,
 175         .mac_addr_add         = eth_em_rar_set,
 176         .mac_addr_remove      = eth_em_rar_clear,
 177         .set_mc_addr_list     = eth_em_set_mc_addr_list,
 178         .rxq_info_get         = em_rxq_info_get,
 179         .txq_info_get         = em_txq_info_get,
 180 };
 181
 182 /**
 183  * Atomically reads the link status information from global
 184  * structure rte_eth_dev.
 185  *
 186  * @param dev
 187  *   - Pointer to the structure rte_eth_dev to read from.
 188  *   - Pointer to the buffer to be saved with the link status.
 189  *
 190  * @return
 191  *   - On success, zero.
 192  *   - On failure, negative value.
 193  */
 194 static inline int
 195 rte_em_dev_atomic_read_link_status(struct rte_eth_dev *dev,
 196                                 struct rte_eth_link *link)
 197 {
 198         struct rte_eth_link *dst = link;
 199         struct rte_eth_link *src = &(dev->data->dev_link);
 200
 201         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 202                                         *(uint64_t *)src) == 0)
 203                 return -1;
 204
 205         return 0;
 206 }
 207
 208 /**
 209  * Atomically writes the link status information into global
 210  * structure rte_eth_dev.
 211  *
 212  * @param dev
 213  *   - Pointer to the structure rte_eth_dev to read from.
 214  *   - Pointer to the buffer to be saved with the link status.
 215  *
 216  * @return
 217  *   - On success, zero.
 218  *   - On failure, negative value.
 219  */
 220 static inline int
 221 rte_em_dev_atomic_write_link_status(struct rte_eth_dev *dev,
 222                                 struct rte_eth_link *link)
 223 {
 224         struct rte_eth_link *dst = &(dev->data->dev_link);
 225         struct rte_eth_link *src = link;
 226
 227         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 228                                         *(uint64_t *)src) == 0)
 229                 return -1;
 230
 231         return 0;
 232 }
 233
 234 /**
 235  *  eth_em_dev_is_ich8 - Check for ICH8 device
 236  *  @hw: pointer to the HW structure
 237  *
 238  *  return TRUE for ICH8, otherwise FALSE
 239  **/
 240 static bool
 241 eth_em_dev_is_ich8(struct e1000_hw *hw)
 242 {
 243         DEBUGFUNC("eth_em_dev_is_ich8");
 244
 245         switch (hw->device_id) {
 246         case E1000_DEV_ID_PCH_LPT_I217_LM:
 247         case E1000_DEV_ID_PCH_LPT_I217_V:
 248         case E1000_DEV_ID_PCH_LPTLP_I218_LM:
 249         case E1000_DEV_ID_PCH_LPTLP_I218_V:
 250         case E1000_DEV_ID_PCH_I218_V2:
 251         case E1000_DEV_ID_PCH_I218_LM2:
 252         case E1000_DEV_ID_PCH_I218_V3:
 253         case E1000_DEV_ID_PCH_I218_LM3:
 254                 return 1;
 255         default:
 256                 return 0;
 257         }
 258 }
 259
 260 static int
 261 eth_em_dev_init(struct rte_eth_dev *eth_dev)
 262 {
 263         struct rte_pci_device *pci_dev;
 264         struct e1000_adapter *adapter =
 265                 E1000_DEV_PRIVATE(eth_dev->data->dev_private);
 266         struct e1000_hw *hw =
 267                 E1000_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 268         struct e1000_vfta * shadow_vfta =
 269                 E1000_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
 270
 271         pci_dev = eth_dev->pci_dev;
 272
 273         eth_dev->dev_ops = &eth_em_ops;
 274         eth_dev->rx_pkt_burst = (eth_rx_burst_t)&eth_em_recv_pkts;
 275         eth_dev->tx_pkt_burst = (eth_tx_burst_t)&eth_em_xmit_pkts;
 276
 277         /* for secondary processes, we don't initialise any further as primary
 278          * has already done this work. Only check we don't need a different
 279          * RX function */
 280         if (rte_eal_process_type() != RTE_PROC_PRIMARY){
 281                 if (eth_dev->data->scattered_rx)
 282                         eth_dev->rx_pkt_burst =
 283                                 (eth_rx_burst_t)&eth_em_recv_scattered_pkts;
 284                 return 0;
 285         }
 286
 287         rte_eth_copy_pci_info(eth_dev, pci_dev);
 288
 289         hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
 290         hw->device_id = pci_dev->id.device_id;
 291         adapter->stopped = 0;
 292
 293         /* For ICH8 support we'll need to map the flash memory BAR */
 294         if (eth_em_dev_is_ich8(hw))
 295                 hw->flash_address = (void *)pci_dev->mem_resource[1].addr;
 296
 297         if (e1000_setup_init_funcs(hw, TRUE) != E1000_SUCCESS ||
 298                         em_hw_init(hw) != 0) {
 299                 PMD_INIT_LOG(ERR, "port_id %d vendorID=0x%x deviceID=0x%x: "
 300                         "failed to init HW",
 301                         eth_dev->data->port_id, pci_dev->id.vendor_id,
 302                         pci_dev->id.device_id);
 303                 return -ENODEV;
 304         }
 305
 306         /* Allocate memory for storing MAC addresses */
 307         eth_dev->data->mac_addrs = rte_zmalloc("e1000", ETHER_ADDR_LEN *
 308                         hw->mac.rar_entry_count, 0);
 309         if (eth_dev->data->mac_addrs == NULL) {
 310                 PMD_INIT_LOG(ERR, "Failed to allocate %d bytes needed to "
 311                         "store MAC addresses",
 312                         ETHER_ADDR_LEN * hw->mac.rar_entry_count);
 313                 return -ENOMEM;
 314         }
 315
 316         /* Copy the permanent MAC address */
 317         ether_addr_copy((struct ether_addr *) hw->mac.addr,
 318                 eth_dev->data->mac_addrs);
 319
 320         /* initialize the vfta */
 321         memset(shadow_vfta, 0, sizeof(*shadow_vfta));
 322
 323         PMD_INIT_LOG(DEBUG, "port_id %d vendorID=0x%x deviceID=0x%x",
 324                      eth_dev->data->port_id, pci_dev->id.vendor_id,
 325                      pci_dev->id.device_id);
 326
 327         rte_intr_callback_register(&(pci_dev->intr_handle),
 328                 eth_em_interrupt_handler, (void *)eth_dev);
 329
 330         return 0;
 331 }
 332
 333 static int
 334 eth_em_dev_uninit(struct rte_eth_dev *eth_dev)
 335 {
 336         struct rte_pci_device *pci_dev;
 337         struct e1000_adapter *adapter =
 338                 E1000_DEV_PRIVATE(eth_dev->data->dev_private);
 339
 340         PMD_INIT_FUNC_TRACE();
 341
 342         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
 343                 return -EPERM;
 344
 345         pci_dev = eth_dev->pci_dev;
 346
 347         if (adapter->stopped == 0)
 348                 eth_em_close(eth_dev);
 349
 350         eth_dev->dev_ops = NULL;
 351         eth_dev->rx_pkt_burst = NULL;
 352         eth_dev->tx_pkt_burst = NULL;
 353
 354         rte_free(eth_dev->data->mac_addrs);
 355         eth_dev->data->mac_addrs = NULL;
 356
 357         /* disable uio intr before callback unregister */
 358         rte_intr_disable(&(pci_dev->intr_handle));
 359         rte_intr_callback_unregister(&(pci_dev->intr_handle),
 360                 eth_em_interrupt_handler, (void *)eth_dev);
 361
 362         return 0;
 363 }
 364
 365 static struct eth_driver rte_em_pmd = {
 366         .pci_drv = {
 367                 .name = "rte_em_pmd",
 368                 .id_table = pci_id_em_map,
 369                 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC |
 370                         RTE_PCI_DRV_DETACHABLE,
 371         },
 372         .eth_dev_init = eth_em_dev_init,
 373         .eth_dev_uninit = eth_em_dev_uninit,
 374         .dev_private_size = sizeof(struct e1000_adapter),
 375 };
 376
 377 static int
 378 rte_em_pmd_init(const char *name __rte_unused, const char *params __rte_unused)
 379 {
 380         rte_eth_driver_register(&rte_em_pmd);
 381         return 0;
 382 }
 383
 384 static int
 385 em_hw_init(struct e1000_hw *hw)
 386 {
 387         int diag;
 388
 389         diag = hw->mac.ops.init_params(hw);
 390         if (diag != 0) {
 391                 PMD_INIT_LOG(ERR, "MAC Initialization Error");
 392                 return diag;
 393         }
 394         diag = hw->nvm.ops.init_params(hw);
 395         if (diag != 0) {
 396                 PMD_INIT_LOG(ERR, "NVM Initialization Error");
 397                 return diag;
 398         }
 399         diag = hw->phy.ops.init_params(hw);
 400         if (diag != 0) {
 401                 PMD_INIT_LOG(ERR, "PHY Initialization Error");
 402                 return diag;
 403         }
 404         (void) e1000_get_bus_info(hw);
 405
 406         hw->mac.autoneg = 1;
 407         hw->phy.autoneg_wait_to_complete = 0;
 408         hw->phy.autoneg_advertised = E1000_ALL_SPEED_DUPLEX;
 409
 410         e1000_init_script_state_82541(hw, TRUE);
 411         e1000_set_tbi_compatibility_82543(hw, TRUE);
 412
 413         /* Copper options */
 414         if (hw->phy.media_type == e1000_media_type_copper) {
 415                 hw->phy.mdix = 0; /* AUTO_ALL_MODES */
 416                 hw->phy.disable_polarity_correction = 0;
 417                 hw->phy.ms_type = e1000_ms_hw_default;
 418         }
 419
 420         /*
 421          * Start from a known state, this is important in reading the nvm
 422          * and mac from that.
 423          */
 424         e1000_reset_hw(hw);
 425
 426         /* Make sure we have a good EEPROM before we read from it */
 427         if (e1000_validate_nvm_checksum(hw) < 0) {
 428                 /*
 429                  * Some PCI-E parts fail the first check due to
 430                  * the link being in sleep state, call it again,
 431                  * if it fails a second time its a real issue.
 432                  */
 433                 diag = e1000_validate_nvm_checksum(hw);
 434                 if (diag < 0) {
 435                         PMD_INIT_LOG(ERR, "EEPROM checksum invalid");
 436                         goto error;
 437                 }
 438         }
 439
 440         /* Read the permanent MAC address out of the EEPROM */
 441         diag = e1000_read_mac_addr(hw);
 442         if (diag != 0) {
 443                 PMD_INIT_LOG(ERR, "EEPROM error while reading MAC address");
 444                 goto error;
 445         }
 446
 447         /* Now initialize the hardware */
 448         diag = em_hardware_init(hw);
 449         if (diag != 0) {
 450                 PMD_INIT_LOG(ERR, "Hardware initialization failed");
 451                 goto error;
 452         }
 453
 454         hw->mac.get_link_status = 1;
 455
 456         /* Indicate SOL/IDER usage */
 457         diag = e1000_check_reset_block(hw);
 458         if (diag < 0) {
 459                 PMD_INIT_LOG(ERR, "PHY reset is blocked due to "
 460                         "SOL/IDER session");
 461         }
 462         return 0;
 463
 464 error:
 465         em_hw_control_release(hw);
 466         return diag;
 467 }
 468
 469 static int
 470 eth_em_configure(struct rte_eth_dev *dev)
 471 {
 472         struct e1000_interrupt *intr =
 473                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
 474
 475         PMD_INIT_FUNC_TRACE();
 476         intr->flags |= E1000_FLAG_NEED_LINK_UPDATE;
 477         PMD_INIT_FUNC_TRACE();
 478
 479         return 0;
 480 }
 481
 482 static void
 483 em_set_pba(struct e1000_hw *hw)
 484 {
 485         uint32_t pba;
 486
 487         /*
 488          * Packet Buffer Allocation (PBA)
 489          * Writing PBA sets the receive portion of the buffer
 490          * the remainder is used for the transmit buffer.
 491          * Devices before the 82547 had a Packet Buffer of 64K.
 492          * After the 82547 the buffer was reduced to 40K.
 493          */
 494         switch (hw->mac.type) {
 495                 case e1000_82547:
 496                 case e1000_82547_rev_2:
 497                 /* 82547: Total Packet Buffer is 40K */
 498                         pba = E1000_PBA_22K; /* 22K for Rx, 18K for Tx */
 499                         break;
 500                 case e1000_82571:
 501                 case e1000_82572:
 502                 case e1000_80003es2lan:
 503                         pba = E1000_PBA_32K; /* 32K for Rx, 16K for Tx */
 504                         break;
 505                 case e1000_82573: /* 82573: Total Packet Buffer is 32K */
 506                         pba = E1000_PBA_12K; /* 12K for Rx, 20K for Tx */
 507                         break;
 508                 case e1000_82574:
 509                 case e1000_82583:
 510                         pba = E1000_PBA_20K; /* 20K for Rx, 20K for Tx */
 511                         break;
 512                 case e1000_ich8lan:
 513                         pba = E1000_PBA_8K;
 514                         break;
 515                 case e1000_ich9lan:
 516                 case e1000_ich10lan:
 517                         pba = E1000_PBA_10K;
 518                         break;
 519                 case e1000_pchlan:
 520                 case e1000_pch2lan:
 521                 case e1000_pch_lpt:
 522                         pba = E1000_PBA_26K;
 523                         break;
 524                 default:
 525                         pba = E1000_PBA_40K; /* 40K for Rx, 24K for Tx */
 526         }
 527
 528         E1000_WRITE_REG(hw, E1000_PBA, pba);
 529 }
 530
 531 static int
 532 eth_em_start(struct rte_eth_dev *dev)
 533 {
 534         struct e1000_adapter *adapter =
 535                 E1000_DEV_PRIVATE(dev->data->dev_private);
 536         struct e1000_hw *hw =
 537                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 538         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
 539         int ret, mask;
 540         uint32_t intr_vector = 0;
 541         uint32_t *speeds;
 542         int num_speeds;
 543         bool autoneg;
 544
 545         PMD_INIT_FUNC_TRACE();
 546
 547         eth_em_stop(dev);
 548
 549         e1000_power_up_phy(hw);
 550
 551         /* Set default PBA value */
 552         em_set_pba(hw);
 553
 554         /* Put the address into the Receive Address Array */
 555         e1000_rar_set(hw, hw->mac.addr, 0);
 556
 557         /*
 558          * With the 82571 adapter, RAR[0] may be overwritten
 559          * when the other port is reset, we make a duplicate
 560          * in RAR[14] for that eventuality, this assures
 561          * the interface continues to function.
 562          */
 563         if (hw->mac.type == e1000_82571) {
 564                 e1000_set_laa_state_82571(hw, TRUE);
 565                 e1000_rar_set(hw, hw->mac.addr, E1000_RAR_ENTRIES - 1);
 566         }
 567
 568         /* Initialize the hardware */
 569         if (em_hardware_init(hw)) {
 570                 PMD_INIT_LOG(ERR, "Unable to initialize the hardware");
 571                 return -EIO;
 572         }
 573
 574         E1000_WRITE_REG(hw, E1000_VET, ETHER_TYPE_VLAN);
 575
 576         /* Configure for OS presence */
 577         em_init_manageability(hw);
 578
 579         if (dev->data->dev_conf.intr_conf.rxq != 0) {
 580                 intr_vector = dev->data->nb_rx_queues;
 581                 if (rte_intr_efd_enable(intr_handle, intr_vector))
 582                         return -1;
 583         }
 584
 585         if (rte_intr_dp_is_en(intr_handle)) {
 586                 intr_handle->intr_vec =
 587                         rte_zmalloc("intr_vec",
 588                                         dev->data->nb_rx_queues * sizeof(int), 0);
 589                 if (intr_handle->intr_vec == NULL) {
 590                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
 591                                                 " intr_vec\n", dev->data->nb_rx_queues);
 592                         return -ENOMEM;
 593                 }
 594
 595                 /* enable rx interrupt */
 596                 em_rxq_intr_enable(hw);
 597         }
 598
 599         eth_em_tx_init(dev);
 600
 601         ret = eth_em_rx_init(dev);
 602         if (ret) {
 603                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
 604                 em_dev_clear_queues(dev);
 605                 return ret;
 606         }
 607
 608         e1000_clear_hw_cntrs_base_generic(hw);
 609
 610         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK | \
 611                         ETH_VLAN_EXTEND_MASK;
 612         eth_em_vlan_offload_set(dev, mask);
 613
 614         /* Set Interrupt Throttling Rate to maximum allowed value. */
 615         E1000_WRITE_REG(hw, E1000_ITR, UINT16_MAX);
 616
 617         /* Setup link speed and duplex */
 618         speeds = &dev->data->dev_conf.link_speeds;
 619         if (*speeds == ETH_LINK_SPEED_AUTONEG) {
 620                 hw->phy.autoneg_advertised = E1000_ALL_SPEED_DUPLEX;
 621         } else {
 622                 num_speeds = 0;
 623                 autoneg = (*speeds & ETH_LINK_SPEED_FIXED) == 0;
 624
 625                 /* Reset */
 626                 hw->phy.autoneg_advertised = 0;
 627
 628                 if (*speeds & ~(ETH_LINK_SPEED_10M_HD | ETH_LINK_SPEED_10M |
 629                                 ETH_LINK_SPEED_100M_HD | ETH_LINK_SPEED_100M |
 630                                 ETH_LINK_SPEED_1G | ETH_LINK_SPEED_FIXED)) {
 631                         num_speeds = -1;
 632                         goto error_invalid_config;
 633                 }
 634                 if (*speeds & ETH_LINK_SPEED_10M_HD) {
 635                         hw->phy.autoneg_advertised |= ADVERTISE_10_HALF;
 636                         num_speeds++;
 637                 }
 638                 if (*speeds & ETH_LINK_SPEED_10M) {
 639                         hw->phy.autoneg_advertised |= ADVERTISE_10_FULL;
 640                         num_speeds++;
 641                 }
 642                 if (*speeds & ETH_LINK_SPEED_100M_HD) {
 643                         hw->phy.autoneg_advertised |= ADVERTISE_100_HALF;
 644                         num_speeds++;
 645                 }
 646                 if (*speeds & ETH_LINK_SPEED_100M) {
 647                         hw->phy.autoneg_advertised |= ADVERTISE_100_FULL;
 648                         num_speeds++;
 649                 }
 650                 if (*speeds & ETH_LINK_SPEED_1G) {
 651                         hw->phy.autoneg_advertised |= ADVERTISE_1000_FULL;
 652                         num_speeds++;
 653                 }
 654                 if (num_speeds == 0 || (!autoneg && (num_speeds > 1)))
 655                         goto error_invalid_config;
 656         }
 657
 658         e1000_setup_link(hw);
 659
 660         if (rte_intr_allow_others(intr_handle)) {
 661                 /* check if lsc interrupt is enabled */
 662                 if (dev->data->dev_conf.intr_conf.lsc != 0) {
 663                         ret = eth_em_interrupt_setup(dev);
 664                         if (ret) {
 665                                 PMD_INIT_LOG(ERR, "Unable to setup interrupts");
 666                                 em_dev_clear_queues(dev);
 667                                 return ret;
 668                         }
 669                 }
 670         } else {
 671                 rte_intr_callback_unregister(intr_handle,
 672                                                 eth_em_interrupt_handler,
 673                                                 (void *)dev);
 674                 if (dev->data->dev_conf.intr_conf.lsc != 0)
 675                         PMD_INIT_LOG(INFO, "lsc won't enable because of"
 676                                      " no intr multiplex\n");
 677         }
 678         /* check if rxq interrupt is enabled */
 679         if (dev->data->dev_conf.intr_conf.rxq != 0)
 680                 eth_em_rxq_interrupt_setup(dev);
 681
 682         rte_intr_enable(intr_handle);
 683
 684         adapter->stopped = 0;
 685
 686         PMD_INIT_LOG(DEBUG, "<<");
 687
 688         return 0;
 689
 690 error_invalid_config:
 691         PMD_INIT_LOG(ERR, "Invalid advertised speeds (%u) for port %u",
 692                      dev->data->dev_conf.link_speeds, dev->data->port_id);
 693         em_dev_clear_queues(dev);
 694         return -EINVAL;
 695 }
 696
 697 /*********************************************************************
 698  *
 699  *  This routine disables all traffic on the adapter by issuing a
 700  *  global reset on the MAC.
 701  *
 702  **********************************************************************/
 703 static void
 704 eth_em_stop(struct rte_eth_dev *dev)
 705 {
 706         struct rte_eth_link link;
 707         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 708         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
 709
 710         em_rxq_intr_disable(hw);
 711         em_lsc_intr_disable(hw);
 712
 713         e1000_reset_hw(hw);
 714         if (hw->mac.type >= e1000_82544)
 715                 E1000_WRITE_REG(hw, E1000_WUC, 0);
 716
 717         /* Power down the phy. Needed to make the link go down */
 718         e1000_power_down_phy(hw);
 719
 720         em_dev_clear_queues(dev);
 721
 722         /* clear the recorded link status */
 723         memset(&link, 0, sizeof(link));
 724         rte_em_dev_atomic_write_link_status(dev, &link);
 725
 726         if (!rte_intr_allow_others(intr_handle))
 727                 /* resume to the default handler */
 728                 rte_intr_callback_register(intr_handle,
 729                                            eth_em_interrupt_handler,
 730                                            (void *)dev);
 731
 732         /* Clean datapath event and queue/vec mapping */
 733         rte_intr_efd_disable(intr_handle);
 734         if (intr_handle->intr_vec != NULL) {
 735                 rte_free(intr_handle->intr_vec);
 736                 intr_handle->intr_vec = NULL;
 737         }
 738 }
 739
 740 static void
 741 eth_em_close(struct rte_eth_dev *dev)
 742 {
 743         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 744         struct e1000_adapter *adapter =
 745                 E1000_DEV_PRIVATE(dev->data->dev_private);
 746
 747         eth_em_stop(dev);
 748         adapter->stopped = 1;
 749         em_dev_free_queues(dev);
 750         e1000_phy_hw_reset(hw);
 751         em_release_manageability(hw);
 752         em_hw_control_release(hw);
 753 }
 754
 755 static int
 756 em_get_rx_buffer_size(struct e1000_hw *hw)
 757 {
 758         uint32_t rx_buf_size;
 759
 760         rx_buf_size = ((E1000_READ_REG(hw, E1000_PBA) & UINT16_MAX) << 10);
 761         return rx_buf_size;
 762 }
 763
 764 /*********************************************************************
 765  *
 766  *  Initialize the hardware
 767  *
 768  **********************************************************************/
 769 static int
 770 em_hardware_init(struct e1000_hw *hw)
 771 {
 772         uint32_t rx_buf_size;
 773         int diag;
 774
 775         /* Issue a global reset */
 776         e1000_reset_hw(hw);
 777
 778         /* Let the firmware know the OS is in control */
 779         em_hw_control_acquire(hw);
 780
 781         /*
 782          * These parameters control the automatic generation (Tx) and
 783          * response (Rx) to Ethernet PAUSE frames.
 784          * - High water mark should allow for at least two standard size (1518)
 785          *   frames to be received after sending an XOFF.
 786          * - Low water mark works best when it is very near the high water mark.
 787          *   This allows the receiver to restart by sending XON when it has
 788          *   drained a bit. Here we use an arbitrary value of 1500 which will
 789          *   restart after one full frame is pulled from the buffer. There
 790          *   could be several smaller frames in the buffer and if so they will
 791          *   not trigger the XON until their total number reduces the buffer
 792          *   by 1500.
 793          * - The pause time is fairly large at 1000 x 512ns = 512 usec.
 794          */
 795         rx_buf_size = em_get_rx_buffer_size(hw);
 796
 797         hw->fc.high_water = rx_buf_size - PMD_ROUNDUP(ETHER_MAX_LEN * 2, 1024);
 798         hw->fc.low_water = hw->fc.high_water - 1500;
 799
 800         if (hw->mac.type == e1000_80003es2lan)
 801                 hw->fc.pause_time = UINT16_MAX;
 802         else
 803                 hw->fc.pause_time = EM_FC_PAUSE_TIME;
 804
 805         hw->fc.send_xon = 1;
 806
 807         /* Set Flow control, use the tunable location if sane */
 808         if (em_fc_setting <= e1000_fc_full)
 809                 hw->fc.requested_mode = em_fc_setting;
 810         else
 811                 hw->fc.requested_mode = e1000_fc_none;
 812
 813         /* Workaround: no TX flow ctrl for PCH */
 814         if (hw->mac.type == e1000_pchlan)
 815                 hw->fc.requested_mode = e1000_fc_rx_pause;
 816
 817         /* Override - settings for PCH2LAN, ya its magic :) */
 818         if (hw->mac.type == e1000_pch2lan) {
 819                 hw->fc.high_water = 0x5C20;
 820                 hw->fc.low_water = 0x5048;
 821                 hw->fc.pause_time = 0x0650;
 822                 hw->fc.refresh_time = 0x0400;
 823         } else if (hw->mac.type == e1000_pch_lpt) {
 824                 hw->fc.requested_mode = e1000_fc_full;
 825         }
 826
 827         diag = e1000_init_hw(hw);
 828         if (diag < 0)
 829                 return diag;
 830         e1000_check_for_link(hw);
 831         return 0;
 832 }
 833
 834 /* This function is based on em_update_stats_counters() in e1000/if_em.c */
 835 static void
 836 eth_em_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *rte_stats)
 837 {
 838         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 839         struct e1000_hw_stats *stats =
 840                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
 841         int pause_frames;
 842
 843         if(hw->phy.media_type == e1000_media_type_copper ||
 844                         (E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU)) {
 845                 stats->symerrs += E1000_READ_REG(hw,E1000_SYMERRS);
 846                 stats->sec += E1000_READ_REG(hw, E1000_SEC);
 847         }
 848
 849         stats->crcerrs += E1000_READ_REG(hw, E1000_CRCERRS);
 850         stats->mpc += E1000_READ_REG(hw, E1000_MPC);
 851         stats->scc += E1000_READ_REG(hw, E1000_SCC);
 852         stats->ecol += E1000_READ_REG(hw, E1000_ECOL);
 853
 854         stats->mcc += E1000_READ_REG(hw, E1000_MCC);
 855         stats->latecol += E1000_READ_REG(hw, E1000_LATECOL);
 856         stats->colc += E1000_READ_REG(hw, E1000_COLC);
 857         stats->dc += E1000_READ_REG(hw, E1000_DC);
 858         stats->rlec += E1000_READ_REG(hw, E1000_RLEC);
 859         stats->xonrxc += E1000_READ_REG(hw, E1000_XONRXC);
 860         stats->xontxc += E1000_READ_REG(hw, E1000_XONTXC);
 861
 862         /*
 863          * For watchdog management we need to know if we have been
 864          * paused during the last interval, so capture that here.
 865          */
 866         pause_frames = E1000_READ_REG(hw, E1000_XOFFRXC);
 867         stats->xoffrxc += pause_frames;
 868         stats->xofftxc += E1000_READ_REG(hw, E1000_XOFFTXC);
 869         stats->fcruc += E1000_READ_REG(hw, E1000_FCRUC);
 870         stats->prc64 += E1000_READ_REG(hw, E1000_PRC64);
 871         stats->prc127 += E1000_READ_REG(hw, E1000_PRC127);
 872         stats->prc255 += E1000_READ_REG(hw, E1000_PRC255);
 873         stats->prc511 += E1000_READ_REG(hw, E1000_PRC511);
 874         stats->prc1023 += E1000_READ_REG(hw, E1000_PRC1023);
 875         stats->prc1522 += E1000_READ_REG(hw, E1000_PRC1522);
 876         stats->gprc += E1000_READ_REG(hw, E1000_GPRC);
 877         stats->bprc += E1000_READ_REG(hw, E1000_BPRC);
 878         stats->mprc += E1000_READ_REG(hw, E1000_MPRC);
 879         stats->gptc += E1000_READ_REG(hw, E1000_GPTC);
 880
 881         /*
 882          * For the 64-bit byte counters the low dword must be read first.
 883          * Both registers clear on the read of the high dword.
 884          */
 885
 886         stats->gorc += E1000_READ_REG(hw, E1000_GORCL);
 887         stats->gorc += ((uint64_t)E1000_READ_REG(hw, E1000_GORCH) << 32);
 888         stats->gotc += E1000_READ_REG(hw, E1000_GOTCL);
 889         stats->gotc += ((uint64_t)E1000_READ_REG(hw, E1000_GOTCH) << 32);
 890
 891         stats->rnbc += E1000_READ_REG(hw, E1000_RNBC);
 892         stats->ruc += E1000_READ_REG(hw, E1000_RUC);
 893         stats->rfc += E1000_READ_REG(hw, E1000_RFC);
 894         stats->roc += E1000_READ_REG(hw, E1000_ROC);
 895         stats->rjc += E1000_READ_REG(hw, E1000_RJC);
 896
 897         stats->tor += E1000_READ_REG(hw, E1000_TORH);
 898         stats->tot += E1000_READ_REG(hw, E1000_TOTH);
 899
 900         stats->tpr += E1000_READ_REG(hw, E1000_TPR);
 901         stats->tpt += E1000_READ_REG(hw, E1000_TPT);
 902         stats->ptc64 += E1000_READ_REG(hw, E1000_PTC64);
 903         stats->ptc127 += E1000_READ_REG(hw, E1000_PTC127);
 904         stats->ptc255 += E1000_READ_REG(hw, E1000_PTC255);
 905         stats->ptc511 += E1000_READ_REG(hw, E1000_PTC511);
 906         stats->ptc1023 += E1000_READ_REG(hw, E1000_PTC1023);
 907         stats->ptc1522 += E1000_READ_REG(hw, E1000_PTC1522);
 908         stats->mptc += E1000_READ_REG(hw, E1000_MPTC);
 909         stats->bptc += E1000_READ_REG(hw, E1000_BPTC);
 910
 911         /* Interrupt Counts */
 912
 913         if (hw->mac.type >= e1000_82571) {
 914                 stats->iac += E1000_READ_REG(hw, E1000_IAC);
 915                 stats->icrxptc += E1000_READ_REG(hw, E1000_ICRXPTC);
 916                 stats->icrxatc += E1000_READ_REG(hw, E1000_ICRXATC);
 917                 stats->ictxptc += E1000_READ_REG(hw, E1000_ICTXPTC);
 918                 stats->ictxatc += E1000_READ_REG(hw, E1000_ICTXATC);
 919                 stats->ictxqec += E1000_READ_REG(hw, E1000_ICTXQEC);
 920                 stats->ictxqmtc += E1000_READ_REG(hw, E1000_ICTXQMTC);
 921                 stats->icrxdmtc += E1000_READ_REG(hw, E1000_ICRXDMTC);
 922                 stats->icrxoc += E1000_READ_REG(hw, E1000_ICRXOC);
 923         }
 924
 925         if (hw->mac.type >= e1000_82543) {
 926                 stats->algnerrc += E1000_READ_REG(hw, E1000_ALGNERRC);
 927                 stats->rxerrc += E1000_READ_REG(hw, E1000_RXERRC);
 928                 stats->tncrs += E1000_READ_REG(hw, E1000_TNCRS);
 929                 stats->cexterr += E1000_READ_REG(hw, E1000_CEXTERR);
 930                 stats->tsctc += E1000_READ_REG(hw, E1000_TSCTC);
 931                 stats->tsctfc += E1000_READ_REG(hw, E1000_TSCTFC);
 932         }
 933
 934         if (rte_stats == NULL)
 935                 return;
 936
 937         /* Rx Errors */
 938         rte_stats->imissed = stats->mpc;
 939         rte_stats->ierrors = stats->crcerrs +
 940                              stats->rlec + stats->ruc + stats->roc +
 941                              stats->rxerrc + stats->algnerrc + stats->cexterr;
 942
 943         /* Tx Errors */
 944         rte_stats->oerrors = stats->ecol + stats->latecol;
 945
 946         rte_stats->ipackets = stats->gprc;
 947         rte_stats->opackets = stats->gptc;
 948         rte_stats->ibytes   = stats->gorc;
 949         rte_stats->obytes   = stats->gotc;
 950 }
 951
 952 static void
 953 eth_em_stats_reset(struct rte_eth_dev *dev)
 954 {
 955         struct e1000_hw_stats *hw_stats =
 956                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
 957
 958         /* HW registers are cleared on read */
 959         eth_em_stats_get(dev, NULL);
 960
 961         /* Reset software totals */
 962         memset(hw_stats, 0, sizeof(*hw_stats));
 963 }
 964
 965 static int
 966 eth_em_rx_queue_intr_enable(struct rte_eth_dev *dev, __rte_unused uint16_t queue_id)
 967 {
 968         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 969
 970         em_rxq_intr_enable(hw);
 971         rte_intr_enable(&dev->pci_dev->intr_handle);
 972
 973         return 0;
 974 }
 975
 976 static int
 977 eth_em_rx_queue_intr_disable(struct rte_eth_dev *dev, __rte_unused uint16_t queue_id)
 978 {
 979         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 980
 981         em_rxq_intr_disable(hw);
 982
 983         return 0;
 984 }
 985
 986 static uint32_t
 987 em_get_max_pktlen(const struct e1000_hw *hw)
 988 {
 989         switch (hw->mac.type) {
 990         case e1000_82571:
 991         case e1000_82572:
 992         case e1000_ich9lan:
 993         case e1000_ich10lan:
 994         case e1000_pch2lan:
 995         case e1000_pch_lpt:
 996         case e1000_82574:
 997         case e1000_80003es2lan: /* 9K Jumbo Frame size */
 998         case e1000_82583:
 999                 return 0x2412;
1000         case e1000_pchlan:
1001                 return 0x1000;
1002         /* Adapters that do not support jumbo frames */
1003         case e1000_ich8lan:
1004                 return ETHER_MAX_LEN;
1005         default:
1006                 return MAX_JUMBO_FRAME_SIZE;
1007         }
1008 }
1009
1010 static void
1011 eth_em_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
1012 {
1013         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1014
1015         dev_info->min_rx_bufsize = 256; /* See BSIZE field of RCTL register. */
1016         dev_info->max_rx_pktlen = em_get_max_pktlen(hw);
1017         dev_info->max_mac_addrs = hw->mac.rar_entry_count;
1018
1019         /*
1020          * Starting with 631xESB hw supports 2 TX/RX queues per port.
1021          * Unfortunatelly, all these nics have just one TX context.
1022          * So we have few choises for TX:
1023          * - Use just one TX queue.
1024          * - Allow cksum offload only for one TX queue.
1025          * - Don't allow TX cksum offload at all.
1026          * For now, option #1 was chosen.
1027          * To use second RX queue we have to use extended RX descriptor
1028          * (Multiple Receive Queues are mutually exclusive with UDP
1029          * fragmentation and are not supported when a legacy receive
1030          * descriptor format is used).
1031          * Which means separate RX routinies - as legacy nics (82540, 82545)
1032          * don't support extended RXD.
1033          * To avoid it we support just one RX queue for now (no RSS).
1034          */
1035
1036         dev_info->max_rx_queues = 1;
1037         dev_info->max_tx_queues = 1;
1038
1039         dev_info->rx_desc_lim = (struct rte_eth_desc_lim) {
1040                 .nb_max = E1000_MAX_RING_DESC,
1041                 .nb_min = E1000_MIN_RING_DESC,
1042                 .nb_align = EM_RXD_ALIGN,
1043         };
1044
1045         dev_info->tx_desc_lim = (struct rte_eth_desc_lim) {
1046                 .nb_max = E1000_MAX_RING_DESC,
1047                 .nb_min = E1000_MIN_RING_DESC,
1048                 .nb_align = EM_TXD_ALIGN,
1049         };
1050
1051         dev_info->speed_capa = ETH_LINK_SPEED_10M_HD | ETH_LINK_SPEED_10M |
1052                         ETH_LINK_SPEED_100M_HD | ETH_LINK_SPEED_100M |
1053                         ETH_LINK_SPEED_1G;
1054 }
1055
1056 /* return 0 means link status changed, -1 means not changed */
1057 static int
1058 eth_em_link_update(struct rte_eth_dev *dev, int wait_to_complete)
1059 {
1060         struct e1000_hw *hw =
1061                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1062         struct rte_eth_link link, old;
1063         int link_check, count;
1064
1065         link_check = 0;
1066         hw->mac.get_link_status = 1;
1067
1068         /* possible wait-to-complete in up to 9 seconds */
1069         for (count = 0; count < EM_LINK_UPDATE_CHECK_TIMEOUT; count ++) {
1070                 /* Read the real link status */
1071                 switch (hw->phy.media_type) {
1072                 case e1000_media_type_copper:
1073                         /* Do the work to read phy */
1074                         e1000_check_for_link(hw);
1075                         link_check = !hw->mac.get_link_status;
1076                         break;
1077
1078                 case e1000_media_type_fiber:
1079                         e1000_check_for_link(hw);
1080                         link_check = (E1000_READ_REG(hw, E1000_STATUS) &
1081                                         E1000_STATUS_LU);
1082                         break;
1083
1084                 case e1000_media_type_internal_serdes:
1085                         e1000_check_for_link(hw);
1086                         link_check = hw->mac.serdes_has_link;
1087                         break;
1088
1089                 default:
1090                         break;
1091                 }
1092                 if (link_check || wait_to_complete == 0)
1093                         break;
1094                 rte_delay_ms(EM_LINK_UPDATE_CHECK_INTERVAL);
1095         }
1096         memset(&link, 0, sizeof(link));
1097         rte_em_dev_atomic_read_link_status(dev, &link);
1098         old = link;
1099
1100         /* Now we check if a transition has happened */
1101         if (link_check && (link.link_status == ETH_LINK_DOWN)) {
1102                 uint16_t duplex, speed;
1103                 hw->mac.ops.get_link_up_info(hw, &speed, &duplex);
1104                 link.link_duplex = (duplex == FULL_DUPLEX) ?
1105                                 ETH_LINK_FULL_DUPLEX :
1106                                 ETH_LINK_HALF_DUPLEX;
1107                 link.link_speed = speed;
1108                 link.link_status = ETH_LINK_UP;
1109                 link.link_autoneg = !(dev->data->dev_conf.link_speeds &
1110                                 ETH_LINK_SPEED_FIXED);
1111         } else if (!link_check && (link.link_status == ETH_LINK_UP)) {
1112                 link.link_speed = 0;
1113                 link.link_duplex = ETH_LINK_HALF_DUPLEX;
1114                 link.link_status = ETH_LINK_DOWN;
1115                 link.link_autoneg = ETH_LINK_SPEED_FIXED;
1116         }
1117         rte_em_dev_atomic_write_link_status(dev, &link);
1118
1119         /* not changed */
1120         if (old.link_status == link.link_status)
1121                 return -1;
1122
1123         /* changed */
1124         return 0;
1125 }
1126
1127 /*
1128  * em_hw_control_acquire sets {CTRL_EXT|FWSM}:DRV_LOAD bit.
1129  * For ASF and Pass Through versions of f/w this means
1130  * that the driver is loaded. For AMT version type f/w
1131  * this means that the network i/f is open.
1132  */
1133 static void
1134 em_hw_control_acquire(struct e1000_hw *hw)
1135 {
1136         uint32_t ctrl_ext, swsm;
1137
1138         /* Let firmware know the driver has taken over */
1139         if (hw->mac.type == e1000_82573) {
1140                 swsm = E1000_READ_REG(hw, E1000_SWSM);
1141                 E1000_WRITE_REG(hw, E1000_SWSM, swsm | E1000_SWSM_DRV_LOAD);
1142
1143         } else {
1144                 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
1145                 E1000_WRITE_REG(hw, E1000_CTRL_EXT,
1146                         ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
1147         }
1148 }
1149
1150 /*
1151  * em_hw_control_release resets {CTRL_EXTT|FWSM}:DRV_LOAD bit.
1152  * For ASF and Pass Through versions of f/w this means that the
1153  * driver is no longer loaded. For AMT versions of the
1154  * f/w this means that the network i/f is closed.
1155  */
1156 static void
1157 em_hw_control_release(struct e1000_hw *hw)
1158 {
1159         uint32_t ctrl_ext, swsm;
1160
1161         /* Let firmware taken over control of h/w */
1162         if (hw->mac.type == e1000_82573) {
1163                 swsm = E1000_READ_REG(hw, E1000_SWSM);
1164                 E1000_WRITE_REG(hw, E1000_SWSM, swsm & ~E1000_SWSM_DRV_LOAD);
1165         } else {
1166                 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
1167                 E1000_WRITE_REG(hw, E1000_CTRL_EXT,
1168                         ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
1169         }
1170 }
1171
1172 /*
1173  * Bit of a misnomer, what this really means is
1174  * to enable OS management of the system... aka
1175  * to disable special hardware management features.
1176  */
1177 static void
1178 em_init_manageability(struct e1000_hw *hw)
1179 {
1180         if (e1000_enable_mng_pass_thru(hw)) {
1181                 uint32_t manc2h = E1000_READ_REG(hw, E1000_MANC2H);
1182                 uint32_t manc = E1000_READ_REG(hw, E1000_MANC);
1183
1184                 /* disable hardware interception of ARP */
1185                 manc &= ~(E1000_MANC_ARP_EN);
1186
1187                 /* enable receiving management packets to the host */
1188                 manc |= E1000_MANC_EN_MNG2HOST;
1189                 manc2h |= 1 << 5;  /* Mng Port 623 */
1190                 manc2h |= 1 << 6;  /* Mng Port 664 */
1191                 E1000_WRITE_REG(hw, E1000_MANC2H, manc2h);
1192                 E1000_WRITE_REG(hw, E1000_MANC, manc);
1193         }
1194 }
1195
1196 /*
1197  * Give control back to hardware management
1198  * controller if there is one.
1199  */
1200 static void
1201 em_release_manageability(struct e1000_hw *hw)
1202 {
1203         uint32_t manc;
1204
1205         if (e1000_enable_mng_pass_thru(hw)) {
1206                 manc = E1000_READ_REG(hw, E1000_MANC);
1207
1208                 /* re-enable hardware interception of ARP */
1209                 manc |= E1000_MANC_ARP_EN;
1210                 manc &= ~E1000_MANC_EN_MNG2HOST;
1211
1212                 E1000_WRITE_REG(hw, E1000_MANC, manc);
1213         }
1214 }
1215
1216 static void
1217 eth_em_promiscuous_enable(struct rte_eth_dev *dev)
1218 {
1219         struct e1000_hw *hw =
1220                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1221         uint32_t rctl;
1222
1223         rctl = E1000_READ_REG(hw, E1000_RCTL);
1224         rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
1225         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1226 }
1227
1228 static void
1229 eth_em_promiscuous_disable(struct rte_eth_dev *dev)
1230 {
1231         struct e1000_hw *hw =
1232                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1233         uint32_t rctl;
1234
1235         rctl = E1000_READ_REG(hw, E1000_RCTL);
1236         rctl &= ~(E1000_RCTL_UPE | E1000_RCTL_SBP);
1237         if (dev->data->all_multicast == 1)
1238                 rctl |= E1000_RCTL_MPE;
1239         else
1240                 rctl &= (~E1000_RCTL_MPE);
1241         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1242 }
1243
1244 static void
1245 eth_em_allmulticast_enable(struct rte_eth_dev *dev)
1246 {
1247         struct e1000_hw *hw =
1248                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1249         uint32_t rctl;
1250
1251         rctl = E1000_READ_REG(hw, E1000_RCTL);
1252         rctl |= E1000_RCTL_MPE;
1253         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1254 }
1255
1256 static void
1257 eth_em_allmulticast_disable(struct rte_eth_dev *dev)
1258 {
1259         struct e1000_hw *hw =
1260                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1261         uint32_t rctl;
1262
1263         if (dev->data->promiscuous == 1)
1264                 return; /* must remain in all_multicast mode */
1265         rctl = E1000_READ_REG(hw, E1000_RCTL);
1266         rctl &= (~E1000_RCTL_MPE);
1267         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1268 }
1269
1270 static int
1271 eth_em_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1272 {
1273         struct e1000_hw *hw =
1274                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1275         struct e1000_vfta * shadow_vfta =
1276                 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1277         uint32_t vfta;
1278         uint32_t vid_idx;
1279         uint32_t vid_bit;
1280
1281         vid_idx = (uint32_t) ((vlan_id >> E1000_VFTA_ENTRY_SHIFT) &
1282                               E1000_VFTA_ENTRY_MASK);
1283         vid_bit = (uint32_t) (1 << (vlan_id & E1000_VFTA_ENTRY_BIT_SHIFT_MASK));
1284         vfta = E1000_READ_REG_ARRAY(hw, E1000_VFTA, vid_idx);
1285         if (on)
1286                 vfta |= vid_bit;
1287         else
1288                 vfta &= ~vid_bit;
1289         E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, vid_idx, vfta);
1290
1291         /* update local VFTA copy */
1292         shadow_vfta->vfta[vid_idx] = vfta;
1293
1294         return 0;
1295 }
1296
1297 static void
1298 em_vlan_hw_filter_disable(struct rte_eth_dev *dev)
1299 {
1300         struct e1000_hw *hw =
1301                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1302         uint32_t reg;
1303
1304         /* Filter Table Disable */
1305         reg = E1000_READ_REG(hw, E1000_RCTL);
1306         reg &= ~E1000_RCTL_CFIEN;
1307         reg &= ~E1000_RCTL_VFE;
1308         E1000_WRITE_REG(hw, E1000_RCTL, reg);
1309 }
1310
1311 static void
1312 em_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1313 {
1314         struct e1000_hw *hw =
1315                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1316         struct e1000_vfta * shadow_vfta =
1317                 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1318         uint32_t reg;
1319         int i;
1320
1321         /* Filter Table Enable, CFI not used for packet acceptance */
1322         reg = E1000_READ_REG(hw, E1000_RCTL);
1323         reg &= ~E1000_RCTL_CFIEN;
1324         reg |= E1000_RCTL_VFE;
1325         E1000_WRITE_REG(hw, E1000_RCTL, reg);
1326
1327         /* restore vfta from local copy */
1328         for (i = 0; i < IGB_VFTA_SIZE; i++)
1329                 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, i, shadow_vfta->vfta[i]);
1330 }
1331
1332 static void
1333 em_vlan_hw_strip_disable(struct rte_eth_dev *dev)
1334 {
1335         struct e1000_hw *hw =
1336                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1337         uint32_t reg;
1338
1339         /* VLAN Mode Disable */
1340         reg = E1000_READ_REG(hw, E1000_CTRL);
1341         reg &= ~E1000_CTRL_VME;
1342         E1000_WRITE_REG(hw, E1000_CTRL, reg);
1343
1344 }
1345
1346 static void
1347 em_vlan_hw_strip_enable(struct rte_eth_dev *dev)
1348 {
1349         struct e1000_hw *hw =
1350                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1351         uint32_t reg;
1352
1353         /* VLAN Mode Enable */
1354         reg = E1000_READ_REG(hw, E1000_CTRL);
1355         reg |= E1000_CTRL_VME;
1356         E1000_WRITE_REG(hw, E1000_CTRL, reg);
1357 }
1358
1359 static void
1360 eth_em_vlan_offload_set(struct rte_eth_dev *dev, int mask)
1361 {
1362         if(mask & ETH_VLAN_STRIP_MASK){
1363                 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
1364                         em_vlan_hw_strip_enable(dev);
1365                 else
1366                         em_vlan_hw_strip_disable(dev);
1367         }
1368
1369         if(mask & ETH_VLAN_FILTER_MASK){
1370                 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
1371                         em_vlan_hw_filter_enable(dev);
1372                 else
1373                         em_vlan_hw_filter_disable(dev);
1374         }
1375 }
1376
1377 /*
1378  * It enables the interrupt mask and then enable the interrupt.
1379  *
1380  * @param dev
1381  *  Pointer to struct rte_eth_dev.
1382  *
1383  * @return
1384  *  - On success, zero.
1385  *  - On failure, a negative value.
1386  */
1387 static int
1388 eth_em_interrupt_setup(struct rte_eth_dev *dev)
1389 {
1390         uint32_t regval;
1391         struct e1000_hw *hw =
1392                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1393
1394         /* clear interrupt */
1395         E1000_READ_REG(hw, E1000_ICR);
1396         regval = E1000_READ_REG(hw, E1000_IMS);
1397         E1000_WRITE_REG(hw, E1000_IMS, regval | E1000_ICR_LSC);
1398         return 0;
1399 }
1400
1401 /*
1402  * It clears the interrupt causes and enables the interrupt.
1403  * It will be called once only during nic initialized.
1404  *
1405  * @param dev
1406  *  Pointer to struct rte_eth_dev.
1407  *
1408  * @return
1409  *  - On success, zero.
1410  *  - On failure, a negative value.
1411  */
1412 static int
1413 eth_em_rxq_interrupt_setup(struct rte_eth_dev *dev)
1414 {
1415         struct e1000_hw *hw =
1416         E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1417
1418         E1000_READ_REG(hw, E1000_ICR);
1419         em_rxq_intr_enable(hw);
1420         return 0;
1421 }
1422
1423 /*
1424  * It enable receive packet interrupt.
1425  * @param hw
1426  * Pointer to struct e1000_hw
1427  *
1428  * @return
1429  */
1430 static void
1431 em_rxq_intr_enable(struct e1000_hw *hw)
1432 {
1433         E1000_WRITE_REG(hw, E1000_IMS, E1000_IMS_RXT0);
1434         E1000_WRITE_FLUSH(hw);
1435 }
1436
1437 /*
1438  * It disabled lsc interrupt.
1439  * @param hw
1440  * Pointer to struct e1000_hw
1441  *
1442  * @return
1443  */
1444 static void
1445 em_lsc_intr_disable(struct e1000_hw *hw)
1446 {
1447         E1000_WRITE_REG(hw, E1000_IMC, E1000_IMS_LSC);
1448         E1000_WRITE_FLUSH(hw);
1449 }
1450
1451 /*
1452  * It disabled receive packet interrupt.
1453  * @param hw
1454  * Pointer to struct e1000_hw
1455  *
1456  * @return
1457  */
1458 static void
1459 em_rxq_intr_disable(struct e1000_hw *hw)
1460 {
1461         E1000_READ_REG(hw, E1000_ICR);
1462         E1000_WRITE_REG(hw, E1000_IMC, E1000_IMS_RXT0);
1463         E1000_WRITE_FLUSH(hw);
1464 }
1465
1466 /*
1467  * It reads ICR and gets interrupt causes, check it and set a bit flag
1468  * to update link status.
1469  *
1470  * @param dev
1471  *  Pointer to struct rte_eth_dev.
1472  *
1473  * @return
1474  *  - On success, zero.
1475  *  - On failure, a negative value.
1476  */
1477 static int
1478 eth_em_interrupt_get_status(struct rte_eth_dev *dev)
1479 {
1480         uint32_t icr;
1481         struct e1000_hw *hw =
1482                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1483         struct e1000_interrupt *intr =
1484                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
1485
1486         /* read-on-clear nic registers here */
1487         icr = E1000_READ_REG(hw, E1000_ICR);
1488         if (icr & E1000_ICR_LSC) {
1489                 intr->flags |= E1000_FLAG_NEED_LINK_UPDATE;
1490         }
1491
1492         return 0;
1493 }
1494
1495 /*
1496  * It executes link_update after knowing an interrupt is prsent.
1497  *
1498  * @param dev
1499  *  Pointer to struct rte_eth_dev.
1500  *
1501  * @return
1502  *  - On success, zero.
1503  *  - On failure, a negative value.
1504  */
1505 static int
1506 eth_em_interrupt_action(struct rte_eth_dev *dev)
1507 {
1508         struct e1000_hw *hw =
1509                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1510         struct e1000_interrupt *intr =
1511                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
1512         uint32_t tctl, rctl;
1513         struct rte_eth_link link;
1514         int ret;
1515
1516         if (!(intr->flags & E1000_FLAG_NEED_LINK_UPDATE))
1517                 return -1;
1518
1519         intr->flags &= ~E1000_FLAG_NEED_LINK_UPDATE;
1520         rte_intr_enable(&(dev->pci_dev->intr_handle));
1521
1522         /* set get_link_status to check register later */
1523         hw->mac.get_link_status = 1;
1524         ret = eth_em_link_update(dev, 0);
1525
1526         /* check if link has changed */
1527         if (ret < 0)
1528                 return 0;
1529
1530         memset(&link, 0, sizeof(link));
1531         rte_em_dev_atomic_read_link_status(dev, &link);
1532         if (link.link_status) {
1533                 PMD_INIT_LOG(INFO, " Port %d: Link Up - speed %u Mbps - %s",
1534                              dev->data->port_id, (unsigned)link.link_speed,
1535                              link.link_duplex == ETH_LINK_FULL_DUPLEX ?
1536                              "full-duplex" : "half-duplex");
1537         } else {
1538                 PMD_INIT_LOG(INFO, " Port %d: Link Down", dev->data->port_id);
1539         }
1540         PMD_INIT_LOG(DEBUG, "PCI Address: %04d:%02d:%02d:%d",
1541                      dev->pci_dev->addr.domain, dev->pci_dev->addr.bus,
1542                      dev->pci_dev->addr.devid, dev->pci_dev->addr.function);
1543
1544         tctl = E1000_READ_REG(hw, E1000_TCTL);
1545         rctl = E1000_READ_REG(hw, E1000_RCTL);
1546         if (link.link_status) {
1547                 /* enable Tx/Rx */
1548                 tctl |= E1000_TCTL_EN;
1549                 rctl |= E1000_RCTL_EN;
1550         } else {
1551                 /* disable Tx/Rx */
1552                 tctl &= ~E1000_TCTL_EN;
1553                 rctl &= ~E1000_RCTL_EN;
1554         }
1555         E1000_WRITE_REG(hw, E1000_TCTL, tctl);
1556         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1557         E1000_WRITE_FLUSH(hw);
1558
1559         return 0;
1560 }
1561
1562 /**
1563  * Interrupt handler which shall be registered at first.
1564  *
1565  * @param handle
1566  *  Pointer to interrupt handle.
1567  * @param param
1568  *  The address of parameter (struct rte_eth_dev *) regsitered before.
1569  *
1570  * @return
1571  *  void
1572  */
1573 static void
1574 eth_em_interrupt_handler(__rte_unused struct rte_intr_handle *handle,
1575                                                         void *param)
1576 {
1577         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
1578
1579         eth_em_interrupt_get_status(dev);
1580         eth_em_interrupt_action(dev);
1581         _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC);
1582 }
1583
1584 static int
1585 eth_em_led_on(struct rte_eth_dev *dev)
1586 {
1587         struct e1000_hw *hw;
1588
1589         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1590         return e1000_led_on(hw) == E1000_SUCCESS ? 0 : -ENOTSUP;
1591 }
1592
1593 static int
1594 eth_em_led_off(struct rte_eth_dev *dev)
1595 {
1596         struct e1000_hw *hw;
1597
1598         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1599         return e1000_led_off(hw) == E1000_SUCCESS ? 0 : -ENOTSUP;
1600 }
1601
1602 static int
1603 eth_em_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
1604 {
1605         struct e1000_hw *hw;
1606         uint32_t ctrl;
1607         int tx_pause;
1608         int rx_pause;
1609
1610         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1611         fc_conf->pause_time = hw->fc.pause_time;
1612         fc_conf->high_water = hw->fc.high_water;
1613         fc_conf->low_water = hw->fc.low_water;
1614         fc_conf->send_xon = hw->fc.send_xon;
1615         fc_conf->autoneg = hw->mac.autoneg;
1616
1617         /*
1618          * Return rx_pause and tx_pause status according to actual setting of
1619          * the TFCE and RFCE bits in the CTRL register.
1620          */
1621         ctrl = E1000_READ_REG(hw, E1000_CTRL);
1622         if (ctrl & E1000_CTRL_TFCE)
1623                 tx_pause = 1;
1624         else
1625                 tx_pause = 0;
1626
1627         if (ctrl & E1000_CTRL_RFCE)
1628                 rx_pause = 1;
1629         else
1630                 rx_pause = 0;
1631
1632         if (rx_pause && tx_pause)
1633                 fc_conf->mode = RTE_FC_FULL;
1634         else if (rx_pause)
1635                 fc_conf->mode = RTE_FC_RX_PAUSE;
1636         else if (tx_pause)
1637                 fc_conf->mode = RTE_FC_TX_PAUSE;
1638         else
1639                 fc_conf->mode = RTE_FC_NONE;
1640
1641         return 0;
1642 }
1643
1644 static int
1645 eth_em_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
1646 {
1647         struct e1000_hw *hw;
1648         int err;
1649         enum e1000_fc_mode rte_fcmode_2_e1000_fcmode[] = {
1650                 e1000_fc_none,
1651                 e1000_fc_rx_pause,
1652                 e1000_fc_tx_pause,
1653                 e1000_fc_full
1654         };
1655         uint32_t rx_buf_size;
1656         uint32_t max_high_water;
1657         uint32_t rctl;
1658
1659         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1660         if (fc_conf->autoneg != hw->mac.autoneg)
1661                 return -ENOTSUP;
1662         rx_buf_size = em_get_rx_buffer_size(hw);
1663         PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
1664
1665         /* At least reserve one Ethernet frame for watermark */
1666         max_high_water = rx_buf_size - ETHER_MAX_LEN;
1667         if ((fc_conf->high_water > max_high_water) ||
1668             (fc_conf->high_water < fc_conf->low_water)) {
1669                 PMD_INIT_LOG(ERR, "e1000 incorrect high/low water value");
1670                 PMD_INIT_LOG(ERR, "high water must <= 0x%x", max_high_water);
1671                 return -EINVAL;
1672         }
1673
1674         hw->fc.requested_mode = rte_fcmode_2_e1000_fcmode[fc_conf->mode];
1675         hw->fc.pause_time     = fc_conf->pause_time;
1676         hw->fc.high_water     = fc_conf->high_water;
1677         hw->fc.low_water      = fc_conf->low_water;
1678         hw->fc.send_xon       = fc_conf->send_xon;
1679
1680         err = e1000_setup_link_generic(hw);
1681         if (err == E1000_SUCCESS) {
1682
1683                 /* check if we want to forward MAC frames - driver doesn't have native
1684                  * capability to do that, so we'll write the registers ourselves */
1685
1686                 rctl = E1000_READ_REG(hw, E1000_RCTL);
1687
1688                 /* set or clear MFLCN.PMCF bit depending on configuration */
1689                 if (fc_conf->mac_ctrl_frame_fwd != 0)
1690                         rctl |= E1000_RCTL_PMCF;
1691                 else
1692                         rctl &= ~E1000_RCTL_PMCF;
1693
1694                 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1695                 E1000_WRITE_FLUSH(hw);
1696
1697                 return 0;
1698         }
1699
1700         PMD_INIT_LOG(ERR, "e1000_setup_link_generic = 0x%x", err);
1701         return -EIO;
1702 }
1703
1704 static void
1705 eth_em_rar_set(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
1706                 uint32_t index, __rte_unused uint32_t pool)
1707 {
1708         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1709
1710         e1000_rar_set(hw, mac_addr->addr_bytes, index);
1711 }
1712
1713 static void
1714 eth_em_rar_clear(struct rte_eth_dev *dev, uint32_t index)
1715 {
1716         uint8_t addr[ETHER_ADDR_LEN];
1717         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1718
1719         memset(addr, 0, sizeof(addr));
1720
1721         e1000_rar_set(hw, addr, index);
1722 }
1723
1724 static int
1725 eth_em_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
1726 {
1727         struct rte_eth_dev_info dev_info;
1728         struct e1000_hw *hw;
1729         uint32_t frame_size;
1730         uint32_t rctl;
1731
1732         eth_em_infos_get(dev, &dev_info);
1733         frame_size = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN + VLAN_TAG_SIZE;
1734
1735         /* check that mtu is within the allowed range */
1736         if ((mtu < ETHER_MIN_MTU) || (frame_size > dev_info.max_rx_pktlen))
1737                 return -EINVAL;
1738
1739         /* refuse mtu that requires the support of scattered packets when this
1740          * feature has not been enabled before. */
1741         if (!dev->data->scattered_rx &&
1742             frame_size > dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)
1743                 return -EINVAL;
1744
1745         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1746         rctl = E1000_READ_REG(hw, E1000_RCTL);
1747
1748         /* switch to jumbo mode if needed */
1749         if (frame_size > ETHER_MAX_LEN) {
1750                 dev->data->dev_conf.rxmode.jumbo_frame = 1;
1751                 rctl |= E1000_RCTL_LPE;
1752         } else {
1753                 dev->data->dev_conf.rxmode.jumbo_frame = 0;
1754                 rctl &= ~E1000_RCTL_LPE;
1755         }
1756         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1757
1758         /* update max frame size */
1759         dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
1760         return 0;
1761 }
1762
1763 static int
1764 eth_em_set_mc_addr_list(struct rte_eth_dev *dev,
1765                         struct ether_addr *mc_addr_set,
1766                         uint32_t nb_mc_addr)
1767 {
1768         struct e1000_hw *hw;
1769
1770         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1771         e1000_update_mc_addr_list(hw, (u8 *)mc_addr_set, nb_mc_addr);
1772         return 0;
1773 }
1774
1775 struct rte_driver em_pmd_drv = {
1776         .type = PMD_PDEV,
1777         .init = rte_em_pmd_init,
1778 };
1779
1780 PMD_REGISTER_DRIVER(em_pmd_drv);