drivers/net/e1000/em_ethdev.c

   1 /*-
   2  *   BSD LICENSE
   3  *
   4  *   Copyright(c) 2010-2015 Intel Corporation. All rights reserved.
   5  *   All rights reserved.
   6  *
   7  *   Redistribution and use in source and binary forms, with or without
   8  *   modification, are permitted provided that the following conditions
   9  *   are met:
  10  *
  11  *     * Redistributions of source code must retain the above copyright
  12  *       notice, this list of conditions and the following disclaimer.
  13  *     * Redistributions in binary form must reproduce the above copyright
  14  *       notice, this list of conditions and the following disclaimer in
  15  *       the documentation and/or other materials provided with the
  16  *       distribution.
  17  *     * Neither the name of Intel Corporation nor the names of its
  18  *       contributors may be used to endorse or promote products derived
  19  *       from this software without specific prior written permission.
  20  *
  21  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 #include <sys/queue.h>
  35 #include <stdio.h>
  36 #include <errno.h>
  37 #include <stdint.h>
  38 #include <stdarg.h>
  39
  40 #include <rte_common.h>
  41 #include <rte_interrupts.h>
  42 #include <rte_byteorder.h>
  43 #include <rte_log.h>
  44 #include <rte_debug.h>
  45 #include <rte_pci.h>
  46 #include <rte_ether.h>
  47 #include <rte_ethdev.h>
  48 #include <rte_memory.h>
  49 #include <rte_memzone.h>
  50 #include <rte_eal.h>
  51 #include <rte_atomic.h>
  52 #include <rte_malloc.h>
  53 #include <rte_dev.h>
  54
  55 #include "e1000_logs.h"
  56 #include "base/e1000_api.h"
  57 #include "e1000_ethdev.h"
  58
  59 #define EM_EIAC                 0x000DC
  60
  61 #define PMD_ROUNDUP(x,y)        (((x) + (y) - 1)/(y) * (y))
  62
  63
  64 static int eth_em_configure(struct rte_eth_dev *dev);
  65 static int eth_em_start(struct rte_eth_dev *dev);
  66 static void eth_em_stop(struct rte_eth_dev *dev);
  67 static void eth_em_close(struct rte_eth_dev *dev);
  68 static void eth_em_promiscuous_enable(struct rte_eth_dev *dev);
  69 static void eth_em_promiscuous_disable(struct rte_eth_dev *dev);
  70 static void eth_em_allmulticast_enable(struct rte_eth_dev *dev);
  71 static void eth_em_allmulticast_disable(struct rte_eth_dev *dev);
  72 static int eth_em_link_update(struct rte_eth_dev *dev,
  73                                 int wait_to_complete);
  74 static void eth_em_stats_get(struct rte_eth_dev *dev,
  75                                 struct rte_eth_stats *rte_stats);
  76 static void eth_em_stats_reset(struct rte_eth_dev *dev);
  77 static void eth_em_infos_get(struct rte_eth_dev *dev,
  78                                 struct rte_eth_dev_info *dev_info);
  79 static int eth_em_flow_ctrl_get(struct rte_eth_dev *dev,
  80                                 struct rte_eth_fc_conf *fc_conf);
  81 static int eth_em_flow_ctrl_set(struct rte_eth_dev *dev,
  82                                 struct rte_eth_fc_conf *fc_conf);
  83 static int eth_em_interrupt_setup(struct rte_eth_dev *dev);
  84 static int eth_em_rxq_interrupt_setup(struct rte_eth_dev *dev);
  85 static int eth_em_interrupt_get_status(struct rte_eth_dev *dev);
  86 static int eth_em_interrupt_action(struct rte_eth_dev *dev);
  87 static void eth_em_interrupt_handler(struct rte_intr_handle *handle,
  88                                                         void *param);
  89
  90 static int em_hw_init(struct e1000_hw *hw);
  91 static int em_hardware_init(struct e1000_hw *hw);
  92 static void em_hw_control_acquire(struct e1000_hw *hw);
  93 static void em_hw_control_release(struct e1000_hw *hw);
  94 static void em_init_manageability(struct e1000_hw *hw);
  95 static void em_release_manageability(struct e1000_hw *hw);
  96
  97 static int eth_em_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
  98
  99 static int eth_em_vlan_filter_set(struct rte_eth_dev *dev,
 100                 uint16_t vlan_id, int on);
 101 static void eth_em_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 102 static void em_vlan_hw_filter_enable(struct rte_eth_dev *dev);
 103 static void em_vlan_hw_filter_disable(struct rte_eth_dev *dev);
 104 static void em_vlan_hw_strip_enable(struct rte_eth_dev *dev);
 105 static void em_vlan_hw_strip_disable(struct rte_eth_dev *dev);
 106
 107 /*
 108 static void eth_em_vlan_filter_set(struct rte_eth_dev *dev,
 109                                         uint16_t vlan_id, int on);
 110 */
 111
 112 static int eth_em_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id);
 113 static int eth_em_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id);
 114 static void em_lsc_intr_disable(struct e1000_hw *hw);
 115 static void em_rxq_intr_enable(struct e1000_hw *hw);
 116 static void em_rxq_intr_disable(struct e1000_hw *hw);
 117
 118 static int eth_em_led_on(struct rte_eth_dev *dev);
 119 static int eth_em_led_off(struct rte_eth_dev *dev);
 120
 121 static int em_get_rx_buffer_size(struct e1000_hw *hw);
 122 static void eth_em_rar_set(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
 123                 uint32_t index, uint32_t pool);
 124 static void eth_em_rar_clear(struct rte_eth_dev *dev, uint32_t index);
 125
 126 static int eth_em_set_mc_addr_list(struct rte_eth_dev *dev,
 127                                    struct ether_addr *mc_addr_set,
 128                                    uint32_t nb_mc_addr);
 129
 130 #define EM_FC_PAUSE_TIME 0x0680
 131 #define EM_LINK_UPDATE_CHECK_TIMEOUT  90  /* 9s */
 132 #define EM_LINK_UPDATE_CHECK_INTERVAL 100 /* ms */
 133
 134 static enum e1000_fc_mode em_fc_setting = e1000_fc_full;
 135
 136 /*
 137  * The set of PCI devices this driver supports
 138  */
 139 static const struct rte_pci_id pci_id_em_map[] = {
 140         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82540EM) },
 141         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82545EM_COPPER) },
 142         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82545EM_FIBER) },
 143         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82546EB_COPPER) },
 144         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82546EB_FIBER) },
 145         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82546EB_QUAD_COPPER) },
 146         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82571EB_COPPER) },
 147         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82571EB_FIBER) },
 148         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82571EB_SERDES) },
 149         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82571EB_SERDES_DUAL) },
 150         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82571EB_SERDES_QUAD) },
 151         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82571EB_QUAD_COPPER) },
 152         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82571PT_QUAD_COPPER) },
 153         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82571EB_QUAD_FIBER) },
 154         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82571EB_QUAD_COPPER_LP) },
 155         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82572EI_COPPER) },
 156         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82572EI_FIBER) },
 157         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82572EI_SERDES) },
 158         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82572EI) },
 159         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82573L) },
 160         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82574L) },
 161         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82574LA) },
 162         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82583V) },
 163         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_LPT_I217_LM) },
 164         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_LPT_I217_V) },
 165         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_LPTLP_I218_LM) },
 166         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_LPTLP_I218_V) },
 167         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_I218_LM2) },
 168         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_I218_V2) },
 169         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_I218_LM3) },
 170         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_I218_V3) },
 171         { .vendor_id = 0, /* sentinel */ },
 172 };
 173
 174 static const struct eth_dev_ops eth_em_ops = {
 175         .dev_configure        = eth_em_configure,
 176         .dev_start            = eth_em_start,
 177         .dev_stop             = eth_em_stop,
 178         .dev_close            = eth_em_close,
 179         .promiscuous_enable   = eth_em_promiscuous_enable,
 180         .promiscuous_disable  = eth_em_promiscuous_disable,
 181         .allmulticast_enable  = eth_em_allmulticast_enable,
 182         .allmulticast_disable = eth_em_allmulticast_disable,
 183         .link_update          = eth_em_link_update,
 184         .stats_get            = eth_em_stats_get,
 185         .stats_reset          = eth_em_stats_reset,
 186         .dev_infos_get        = eth_em_infos_get,
 187         .mtu_set              = eth_em_mtu_set,
 188         .vlan_filter_set      = eth_em_vlan_filter_set,
 189         .vlan_offload_set     = eth_em_vlan_offload_set,
 190         .rx_queue_setup       = eth_em_rx_queue_setup,
 191         .rx_queue_release     = eth_em_rx_queue_release,
 192         .rx_queue_count       = eth_em_rx_queue_count,
 193         .rx_descriptor_done   = eth_em_rx_descriptor_done,
 194         .tx_queue_setup       = eth_em_tx_queue_setup,
 195         .tx_queue_release     = eth_em_tx_queue_release,
 196         .rx_queue_intr_enable = eth_em_rx_queue_intr_enable,
 197         .rx_queue_intr_disable = eth_em_rx_queue_intr_disable,
 198         .dev_led_on           = eth_em_led_on,
 199         .dev_led_off          = eth_em_led_off,
 200         .flow_ctrl_get        = eth_em_flow_ctrl_get,
 201         .flow_ctrl_set        = eth_em_flow_ctrl_set,
 202         .mac_addr_add         = eth_em_rar_set,
 203         .mac_addr_remove      = eth_em_rar_clear,
 204         .set_mc_addr_list     = eth_em_set_mc_addr_list,
 205         .rxq_info_get         = em_rxq_info_get,
 206         .txq_info_get         = em_txq_info_get,
 207 };
 208
 209 /**
 210  * Atomically reads the link status information from global
 211  * structure rte_eth_dev.
 212  *
 213  * @param dev
 214  *   - Pointer to the structure rte_eth_dev to read from.
 215  *   - Pointer to the buffer to be saved with the link status.
 216  *
 217  * @return
 218  *   - On success, zero.
 219  *   - On failure, negative value.
 220  */
 221 static inline int
 222 rte_em_dev_atomic_read_link_status(struct rte_eth_dev *dev,
 223                                 struct rte_eth_link *link)
 224 {
 225         struct rte_eth_link *dst = link;
 226         struct rte_eth_link *src = &(dev->data->dev_link);
 227
 228         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 229                                         *(uint64_t *)src) == 0)
 230                 return -1;
 231
 232         return 0;
 233 }
 234
 235 /**
 236  * Atomically writes the link status information into global
 237  * structure rte_eth_dev.
 238  *
 239  * @param dev
 240  *   - Pointer to the structure rte_eth_dev to read from.
 241  *   - Pointer to the buffer to be saved with the link status.
 242  *
 243  * @return
 244  *   - On success, zero.
 245  *   - On failure, negative value.
 246  */
 247 static inline int
 248 rte_em_dev_atomic_write_link_status(struct rte_eth_dev *dev,
 249                                 struct rte_eth_link *link)
 250 {
 251         struct rte_eth_link *dst = &(dev->data->dev_link);
 252         struct rte_eth_link *src = link;
 253
 254         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 255                                         *(uint64_t *)src) == 0)
 256                 return -1;
 257
 258         return 0;
 259 }
 260
 261 /**
 262  *  eth_em_dev_is_ich8 - Check for ICH8 device
 263  *  @hw: pointer to the HW structure
 264  *
 265  *  return TRUE for ICH8, otherwise FALSE
 266  **/
 267 static bool
 268 eth_em_dev_is_ich8(struct e1000_hw *hw)
 269 {
 270         DEBUGFUNC("eth_em_dev_is_ich8");
 271
 272         switch (hw->device_id) {
 273         case E1000_DEV_ID_PCH_LPT_I217_LM:
 274         case E1000_DEV_ID_PCH_LPT_I217_V:
 275         case E1000_DEV_ID_PCH_LPTLP_I218_LM:
 276         case E1000_DEV_ID_PCH_LPTLP_I218_V:
 277         case E1000_DEV_ID_PCH_I218_V2:
 278         case E1000_DEV_ID_PCH_I218_LM2:
 279         case E1000_DEV_ID_PCH_I218_V3:
 280         case E1000_DEV_ID_PCH_I218_LM3:
 281                 return 1;
 282         default:
 283                 return 0;
 284         }
 285 }
 286
 287 static int
 288 eth_em_dev_init(struct rte_eth_dev *eth_dev)
 289 {
 290         struct rte_pci_device *pci_dev;
 291         struct e1000_adapter *adapter =
 292                 E1000_DEV_PRIVATE(eth_dev->data->dev_private);
 293         struct e1000_hw *hw =
 294                 E1000_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 295         struct e1000_vfta * shadow_vfta =
 296                 E1000_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
 297
 298         pci_dev = eth_dev->pci_dev;
 299
 300         eth_dev->dev_ops = &eth_em_ops;
 301         eth_dev->rx_pkt_burst = (eth_rx_burst_t)&eth_em_recv_pkts;
 302         eth_dev->tx_pkt_burst = (eth_tx_burst_t)&eth_em_xmit_pkts;
 303
 304         /* for secondary processes, we don't initialise any further as primary
 305          * has already done this work. Only check we don't need a different
 306          * RX function */
 307         if (rte_eal_process_type() != RTE_PROC_PRIMARY){
 308                 if (eth_dev->data->scattered_rx)
 309                         eth_dev->rx_pkt_burst =
 310                                 (eth_rx_burst_t)&eth_em_recv_scattered_pkts;
 311                 return 0;
 312         }
 313
 314         rte_eth_copy_pci_info(eth_dev, pci_dev);
 315
 316         hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
 317         hw->device_id = pci_dev->id.device_id;
 318         adapter->stopped = 0;
 319
 320         /* For ICH8 support we'll need to map the flash memory BAR */
 321         if (eth_em_dev_is_ich8(hw))
 322                 hw->flash_address = (void *)pci_dev->mem_resource[1].addr;
 323
 324         if (e1000_setup_init_funcs(hw, TRUE) != E1000_SUCCESS ||
 325                         em_hw_init(hw) != 0) {
 326                 PMD_INIT_LOG(ERR, "port_id %d vendorID=0x%x deviceID=0x%x: "
 327                         "failed to init HW",
 328                         eth_dev->data->port_id, pci_dev->id.vendor_id,
 329                         pci_dev->id.device_id);
 330                 return -ENODEV;
 331         }
 332
 333         /* Allocate memory for storing MAC addresses */
 334         eth_dev->data->mac_addrs = rte_zmalloc("e1000", ETHER_ADDR_LEN *
 335                         hw->mac.rar_entry_count, 0);
 336         if (eth_dev->data->mac_addrs == NULL) {
 337                 PMD_INIT_LOG(ERR, "Failed to allocate %d bytes needed to "
 338                         "store MAC addresses",
 339                         ETHER_ADDR_LEN * hw->mac.rar_entry_count);
 340                 return -ENOMEM;
 341         }
 342
 343         /* Copy the permanent MAC address */
 344         ether_addr_copy((struct ether_addr *) hw->mac.addr,
 345                 eth_dev->data->mac_addrs);
 346
 347         /* initialize the vfta */
 348         memset(shadow_vfta, 0, sizeof(*shadow_vfta));
 349
 350         PMD_INIT_LOG(DEBUG, "port_id %d vendorID=0x%x deviceID=0x%x",
 351                      eth_dev->data->port_id, pci_dev->id.vendor_id,
 352                      pci_dev->id.device_id);
 353
 354         rte_intr_callback_register(&(pci_dev->intr_handle),
 355                 eth_em_interrupt_handler, (void *)eth_dev);
 356
 357         return 0;
 358 }
 359
 360 static int
 361 eth_em_dev_uninit(struct rte_eth_dev *eth_dev)
 362 {
 363         struct rte_pci_device *pci_dev;
 364         struct e1000_adapter *adapter =
 365                 E1000_DEV_PRIVATE(eth_dev->data->dev_private);
 366
 367         PMD_INIT_FUNC_TRACE();
 368
 369         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
 370                 return -EPERM;
 371
 372         pci_dev = eth_dev->pci_dev;
 373
 374         if (adapter->stopped == 0)
 375                 eth_em_close(eth_dev);
 376
 377         eth_dev->dev_ops = NULL;
 378         eth_dev->rx_pkt_burst = NULL;
 379         eth_dev->tx_pkt_burst = NULL;
 380
 381         rte_free(eth_dev->data->mac_addrs);
 382         eth_dev->data->mac_addrs = NULL;
 383
 384         /* disable uio intr before callback unregister */
 385         rte_intr_disable(&(pci_dev->intr_handle));
 386         rte_intr_callback_unregister(&(pci_dev->intr_handle),
 387                 eth_em_interrupt_handler, (void *)eth_dev);
 388
 389         return 0;
 390 }
 391
 392 static struct eth_driver rte_em_pmd = {
 393         .pci_drv = {
 394                 .name = "rte_em_pmd",
 395                 .id_table = pci_id_em_map,
 396                 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC |
 397                         RTE_PCI_DRV_DETACHABLE,
 398         },
 399         .eth_dev_init = eth_em_dev_init,
 400         .eth_dev_uninit = eth_em_dev_uninit,
 401         .dev_private_size = sizeof(struct e1000_adapter),
 402 };
 403
 404 static int
 405 rte_em_pmd_init(const char *name __rte_unused, const char *params __rte_unused)
 406 {
 407         rte_eth_driver_register(&rte_em_pmd);
 408         return 0;
 409 }
 410
 411 static int
 412 em_hw_init(struct e1000_hw *hw)
 413 {
 414         int diag;
 415
 416         diag = hw->mac.ops.init_params(hw);
 417         if (diag != 0) {
 418                 PMD_INIT_LOG(ERR, "MAC Initialization Error");
 419                 return diag;
 420         }
 421         diag = hw->nvm.ops.init_params(hw);
 422         if (diag != 0) {
 423                 PMD_INIT_LOG(ERR, "NVM Initialization Error");
 424                 return diag;
 425         }
 426         diag = hw->phy.ops.init_params(hw);
 427         if (diag != 0) {
 428                 PMD_INIT_LOG(ERR, "PHY Initialization Error");
 429                 return diag;
 430         }
 431         (void) e1000_get_bus_info(hw);
 432
 433         hw->mac.autoneg = 1;
 434         hw->phy.autoneg_wait_to_complete = 0;
 435         hw->phy.autoneg_advertised = E1000_ALL_SPEED_DUPLEX;
 436
 437         e1000_init_script_state_82541(hw, TRUE);
 438         e1000_set_tbi_compatibility_82543(hw, TRUE);
 439
 440         /* Copper options */
 441         if (hw->phy.media_type == e1000_media_type_copper) {
 442                 hw->phy.mdix = 0; /* AUTO_ALL_MODES */
 443                 hw->phy.disable_polarity_correction = 0;
 444                 hw->phy.ms_type = e1000_ms_hw_default;
 445         }
 446
 447         /*
 448          * Start from a known state, this is important in reading the nvm
 449          * and mac from that.
 450          */
 451         e1000_reset_hw(hw);
 452
 453         /* Make sure we have a good EEPROM before we read from it */
 454         if (e1000_validate_nvm_checksum(hw) < 0) {
 455                 /*
 456                  * Some PCI-E parts fail the first check due to
 457                  * the link being in sleep state, call it again,
 458                  * if it fails a second time its a real issue.
 459                  */
 460                 diag = e1000_validate_nvm_checksum(hw);
 461                 if (diag < 0) {
 462                         PMD_INIT_LOG(ERR, "EEPROM checksum invalid");
 463                         goto error;
 464                 }
 465         }
 466
 467         /* Read the permanent MAC address out of the EEPROM */
 468         diag = e1000_read_mac_addr(hw);
 469         if (diag != 0) {
 470                 PMD_INIT_LOG(ERR, "EEPROM error while reading MAC address");
 471                 goto error;
 472         }
 473
 474         /* Now initialize the hardware */
 475         diag = em_hardware_init(hw);
 476         if (diag != 0) {
 477                 PMD_INIT_LOG(ERR, "Hardware initialization failed");
 478                 goto error;
 479         }
 480
 481         hw->mac.get_link_status = 1;
 482
 483         /* Indicate SOL/IDER usage */
 484         diag = e1000_check_reset_block(hw);
 485         if (diag < 0) {
 486                 PMD_INIT_LOG(ERR, "PHY reset is blocked due to "
 487                         "SOL/IDER session");
 488         }
 489         return 0;
 490
 491 error:
 492         em_hw_control_release(hw);
 493         return diag;
 494 }
 495
 496 static int
 497 eth_em_configure(struct rte_eth_dev *dev)
 498 {
 499         struct e1000_interrupt *intr =
 500                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
 501
 502         PMD_INIT_FUNC_TRACE();
 503         intr->flags |= E1000_FLAG_NEED_LINK_UPDATE;
 504         PMD_INIT_FUNC_TRACE();
 505
 506         return 0;
 507 }
 508
 509 static void
 510 em_set_pba(struct e1000_hw *hw)
 511 {
 512         uint32_t pba;
 513
 514         /*
 515          * Packet Buffer Allocation (PBA)
 516          * Writing PBA sets the receive portion of the buffer
 517          * the remainder is used for the transmit buffer.
 518          * Devices before the 82547 had a Packet Buffer of 64K.
 519          * After the 82547 the buffer was reduced to 40K.
 520          */
 521         switch (hw->mac.type) {
 522                 case e1000_82547:
 523                 case e1000_82547_rev_2:
 524                 /* 82547: Total Packet Buffer is 40K */
 525                         pba = E1000_PBA_22K; /* 22K for Rx, 18K for Tx */
 526                         break;
 527                 case e1000_82571:
 528                 case e1000_82572:
 529                 case e1000_80003es2lan:
 530                         pba = E1000_PBA_32K; /* 32K for Rx, 16K for Tx */
 531                         break;
 532                 case e1000_82573: /* 82573: Total Packet Buffer is 32K */
 533                         pba = E1000_PBA_12K; /* 12K for Rx, 20K for Tx */
 534                         break;
 535                 case e1000_82574:
 536                 case e1000_82583:
 537                         pba = E1000_PBA_20K; /* 20K for Rx, 20K for Tx */
 538                         break;
 539                 case e1000_ich8lan:
 540                         pba = E1000_PBA_8K;
 541                         break;
 542                 case e1000_ich9lan:
 543                 case e1000_ich10lan:
 544                         pba = E1000_PBA_10K;
 545                         break;
 546                 case e1000_pchlan:
 547                 case e1000_pch2lan:
 548                 case e1000_pch_lpt:
 549                         pba = E1000_PBA_26K;
 550                         break;
 551                 default:
 552                         pba = E1000_PBA_40K; /* 40K for Rx, 24K for Tx */
 553         }
 554
 555         E1000_WRITE_REG(hw, E1000_PBA, pba);
 556 }
 557
 558 static int
 559 eth_em_start(struct rte_eth_dev *dev)
 560 {
 561         struct e1000_adapter *adapter =
 562                 E1000_DEV_PRIVATE(dev->data->dev_private);
 563         struct e1000_hw *hw =
 564                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 565         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
 566         int ret, mask;
 567         uint32_t intr_vector = 0;
 568         uint32_t *speeds;
 569         int num_speeds;
 570         bool autoneg;
 571
 572         PMD_INIT_FUNC_TRACE();
 573
 574         eth_em_stop(dev);
 575
 576         e1000_power_up_phy(hw);
 577
 578         /* Set default PBA value */
 579         em_set_pba(hw);
 580
 581         /* Put the address into the Receive Address Array */
 582         e1000_rar_set(hw, hw->mac.addr, 0);
 583
 584         /*
 585          * With the 82571 adapter, RAR[0] may be overwritten
 586          * when the other port is reset, we make a duplicate
 587          * in RAR[14] for that eventuality, this assures
 588          * the interface continues to function.
 589          */
 590         if (hw->mac.type == e1000_82571) {
 591                 e1000_set_laa_state_82571(hw, TRUE);
 592                 e1000_rar_set(hw, hw->mac.addr, E1000_RAR_ENTRIES - 1);
 593         }
 594
 595         /* Initialize the hardware */
 596         if (em_hardware_init(hw)) {
 597                 PMD_INIT_LOG(ERR, "Unable to initialize the hardware");
 598                 return -EIO;
 599         }
 600
 601         E1000_WRITE_REG(hw, E1000_VET, ETHER_TYPE_VLAN);
 602
 603         /* Configure for OS presence */
 604         em_init_manageability(hw);
 605
 606         if (dev->data->dev_conf.intr_conf.rxq != 0) {
 607                 intr_vector = dev->data->nb_rx_queues;
 608                 if (rte_intr_efd_enable(intr_handle, intr_vector))
 609                         return -1;
 610         }
 611
 612         if (rte_intr_dp_is_en(intr_handle)) {
 613                 intr_handle->intr_vec =
 614                         rte_zmalloc("intr_vec",
 615                                         dev->data->nb_rx_queues * sizeof(int), 0);
 616                 if (intr_handle->intr_vec == NULL) {
 617                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
 618                                                 " intr_vec\n", dev->data->nb_rx_queues);
 619                         return -ENOMEM;
 620                 }
 621
 622                 /* enable rx interrupt */
 623                 em_rxq_intr_enable(hw);
 624         }
 625
 626         eth_em_tx_init(dev);
 627
 628         ret = eth_em_rx_init(dev);
 629         if (ret) {
 630                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
 631                 em_dev_clear_queues(dev);
 632                 return ret;
 633         }
 634
 635         e1000_clear_hw_cntrs_base_generic(hw);
 636
 637         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK | \
 638                         ETH_VLAN_EXTEND_MASK;
 639         eth_em_vlan_offload_set(dev, mask);
 640
 641         /* Set Interrupt Throttling Rate to maximum allowed value. */
 642         E1000_WRITE_REG(hw, E1000_ITR, UINT16_MAX);
 643
 644         /* Setup link speed and duplex */
 645         speeds = &dev->data->dev_conf.link_speeds;
 646         if (*speeds == ETH_LINK_SPEED_AUTONEG) {
 647                 hw->phy.autoneg_advertised = E1000_ALL_SPEED_DUPLEX;
 648         } else {
 649                 num_speeds = 0;
 650                 autoneg = (*speeds & ETH_LINK_SPEED_FIXED) == 0;
 651
 652                 /* Reset */
 653                 hw->phy.autoneg_advertised = 0;
 654
 655                 if (*speeds & ~(ETH_LINK_SPEED_10M_HD | ETH_LINK_SPEED_10M |
 656                                 ETH_LINK_SPEED_100M_HD | ETH_LINK_SPEED_100M |
 657                                 ETH_LINK_SPEED_1G | ETH_LINK_SPEED_FIXED)) {
 658                         num_speeds = -1;
 659                         goto error_invalid_config;
 660                 }
 661                 if (*speeds & ETH_LINK_SPEED_10M_HD) {
 662                         hw->phy.autoneg_advertised |= ADVERTISE_10_HALF;
 663                         num_speeds++;
 664                 }
 665                 if (*speeds & ETH_LINK_SPEED_10M) {
 666                         hw->phy.autoneg_advertised |= ADVERTISE_10_FULL;
 667                         num_speeds++;
 668                 }
 669                 if (*speeds & ETH_LINK_SPEED_100M_HD) {
 670                         hw->phy.autoneg_advertised |= ADVERTISE_100_HALF;
 671                         num_speeds++;
 672                 }
 673                 if (*speeds & ETH_LINK_SPEED_100M) {
 674                         hw->phy.autoneg_advertised |= ADVERTISE_100_FULL;
 675                         num_speeds++;
 676                 }
 677                 if (*speeds & ETH_LINK_SPEED_1G) {
 678                         hw->phy.autoneg_advertised |= ADVERTISE_1000_FULL;
 679                         num_speeds++;
 680                 }
 681                 if (num_speeds == 0 || (!autoneg && (num_speeds > 1)))
 682                         goto error_invalid_config;
 683         }
 684
 685         e1000_setup_link(hw);
 686
 687         if (rte_intr_allow_others(intr_handle)) {
 688                 /* check if lsc interrupt is enabled */
 689                 if (dev->data->dev_conf.intr_conf.lsc != 0) {
 690                         ret = eth_em_interrupt_setup(dev);
 691                         if (ret) {
 692                                 PMD_INIT_LOG(ERR, "Unable to setup interrupts");
 693                                 em_dev_clear_queues(dev);
 694                                 return ret;
 695                         }
 696                 }
 697         } else {
 698                 rte_intr_callback_unregister(intr_handle,
 699                                                 eth_em_interrupt_handler,
 700                                                 (void *)dev);
 701                 if (dev->data->dev_conf.intr_conf.lsc != 0)
 702                         PMD_INIT_LOG(INFO, "lsc won't enable because of"
 703                                      " no intr multiplex\n");
 704         }
 705         /* check if rxq interrupt is enabled */
 706         if (dev->data->dev_conf.intr_conf.rxq != 0)
 707                 eth_em_rxq_interrupt_setup(dev);
 708
 709         rte_intr_enable(intr_handle);
 710
 711         adapter->stopped = 0;
 712
 713         PMD_INIT_LOG(DEBUG, "<<");
 714
 715         return 0;
 716
 717 error_invalid_config:
 718         PMD_INIT_LOG(ERR, "Invalid advertised speeds (%u) for port %u",
 719                      dev->data->dev_conf.link_speeds, dev->data->port_id);
 720         em_dev_clear_queues(dev);
 721         return -EINVAL;
 722 }
 723
 724 /*********************************************************************
 725  *
 726  *  This routine disables all traffic on the adapter by issuing a
 727  *  global reset on the MAC.
 728  *
 729  **********************************************************************/
 730 static void
 731 eth_em_stop(struct rte_eth_dev *dev)
 732 {
 733         struct rte_eth_link link;
 734         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 735         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
 736
 737         em_rxq_intr_disable(hw);
 738         em_lsc_intr_disable(hw);
 739
 740         e1000_reset_hw(hw);
 741         if (hw->mac.type >= e1000_82544)
 742                 E1000_WRITE_REG(hw, E1000_WUC, 0);
 743
 744         /* Power down the phy. Needed to make the link go down */
 745         e1000_power_down_phy(hw);
 746
 747         em_dev_clear_queues(dev);
 748
 749         /* clear the recorded link status */
 750         memset(&link, 0, sizeof(link));
 751         rte_em_dev_atomic_write_link_status(dev, &link);
 752
 753         if (!rte_intr_allow_others(intr_handle))
 754                 /* resume to the default handler */
 755                 rte_intr_callback_register(intr_handle,
 756                                            eth_em_interrupt_handler,
 757                                            (void *)dev);
 758
 759         /* Clean datapath event and queue/vec mapping */
 760         rte_intr_efd_disable(intr_handle);
 761         if (intr_handle->intr_vec != NULL) {
 762                 rte_free(intr_handle->intr_vec);
 763                 intr_handle->intr_vec = NULL;
 764         }
 765 }
 766
 767 static void
 768 eth_em_close(struct rte_eth_dev *dev)
 769 {
 770         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 771         struct e1000_adapter *adapter =
 772                 E1000_DEV_PRIVATE(dev->data->dev_private);
 773
 774         eth_em_stop(dev);
 775         adapter->stopped = 1;
 776         em_dev_free_queues(dev);
 777         e1000_phy_hw_reset(hw);
 778         em_release_manageability(hw);
 779         em_hw_control_release(hw);
 780 }
 781
 782 static int
 783 em_get_rx_buffer_size(struct e1000_hw *hw)
 784 {
 785         uint32_t rx_buf_size;
 786
 787         rx_buf_size = ((E1000_READ_REG(hw, E1000_PBA) & UINT16_MAX) << 10);
 788         return rx_buf_size;
 789 }
 790
 791 /*********************************************************************
 792  *
 793  *  Initialize the hardware
 794  *
 795  **********************************************************************/
 796 static int
 797 em_hardware_init(struct e1000_hw *hw)
 798 {
 799         uint32_t rx_buf_size;
 800         int diag;
 801
 802         /* Issue a global reset */
 803         e1000_reset_hw(hw);
 804
 805         /* Let the firmware know the OS is in control */
 806         em_hw_control_acquire(hw);
 807
 808         /*
 809          * These parameters control the automatic generation (Tx) and
 810          * response (Rx) to Ethernet PAUSE frames.
 811          * - High water mark should allow for at least two standard size (1518)
 812          *   frames to be received after sending an XOFF.
 813          * - Low water mark works best when it is very near the high water mark.
 814          *   This allows the receiver to restart by sending XON when it has
 815          *   drained a bit. Here we use an arbitrary value of 1500 which will
 816          *   restart after one full frame is pulled from the buffer. There
 817          *   could be several smaller frames in the buffer and if so they will
 818          *   not trigger the XON until their total number reduces the buffer
 819          *   by 1500.
 820          * - The pause time is fairly large at 1000 x 512ns = 512 usec.
 821          */
 822         rx_buf_size = em_get_rx_buffer_size(hw);
 823
 824         hw->fc.high_water = rx_buf_size - PMD_ROUNDUP(ETHER_MAX_LEN * 2, 1024);
 825         hw->fc.low_water = hw->fc.high_water - 1500;
 826
 827         if (hw->mac.type == e1000_80003es2lan)
 828                 hw->fc.pause_time = UINT16_MAX;
 829         else
 830                 hw->fc.pause_time = EM_FC_PAUSE_TIME;
 831
 832         hw->fc.send_xon = 1;
 833
 834         /* Set Flow control, use the tunable location if sane */
 835         if (em_fc_setting <= e1000_fc_full)
 836                 hw->fc.requested_mode = em_fc_setting;
 837         else
 838                 hw->fc.requested_mode = e1000_fc_none;
 839
 840         /* Workaround: no TX flow ctrl for PCH */
 841         if (hw->mac.type == e1000_pchlan)
 842                 hw->fc.requested_mode = e1000_fc_rx_pause;
 843
 844         /* Override - settings for PCH2LAN, ya its magic :) */
 845         if (hw->mac.type == e1000_pch2lan) {
 846                 hw->fc.high_water = 0x5C20;
 847                 hw->fc.low_water = 0x5048;
 848                 hw->fc.pause_time = 0x0650;
 849                 hw->fc.refresh_time = 0x0400;
 850         } else if (hw->mac.type == e1000_pch_lpt) {
 851                 hw->fc.requested_mode = e1000_fc_full;
 852         }
 853
 854         diag = e1000_init_hw(hw);
 855         if (diag < 0)
 856                 return diag;
 857         e1000_check_for_link(hw);
 858         return 0;
 859 }
 860
 861 /* This function is based on em_update_stats_counters() in e1000/if_em.c */
 862 static void
 863 eth_em_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *rte_stats)
 864 {
 865         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 866         struct e1000_hw_stats *stats =
 867                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
 868         int pause_frames;
 869
 870         if(hw->phy.media_type == e1000_media_type_copper ||
 871                         (E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU)) {
 872                 stats->symerrs += E1000_READ_REG(hw,E1000_SYMERRS);
 873                 stats->sec += E1000_READ_REG(hw, E1000_SEC);
 874         }
 875
 876         stats->crcerrs += E1000_READ_REG(hw, E1000_CRCERRS);
 877         stats->mpc += E1000_READ_REG(hw, E1000_MPC);
 878         stats->scc += E1000_READ_REG(hw, E1000_SCC);
 879         stats->ecol += E1000_READ_REG(hw, E1000_ECOL);
 880
 881         stats->mcc += E1000_READ_REG(hw, E1000_MCC);
 882         stats->latecol += E1000_READ_REG(hw, E1000_LATECOL);
 883         stats->colc += E1000_READ_REG(hw, E1000_COLC);
 884         stats->dc += E1000_READ_REG(hw, E1000_DC);
 885         stats->rlec += E1000_READ_REG(hw, E1000_RLEC);
 886         stats->xonrxc += E1000_READ_REG(hw, E1000_XONRXC);
 887         stats->xontxc += E1000_READ_REG(hw, E1000_XONTXC);
 888
 889         /*
 890          * For watchdog management we need to know if we have been
 891          * paused during the last interval, so capture that here.
 892          */
 893         pause_frames = E1000_READ_REG(hw, E1000_XOFFRXC);
 894         stats->xoffrxc += pause_frames;
 895         stats->xofftxc += E1000_READ_REG(hw, E1000_XOFFTXC);
 896         stats->fcruc += E1000_READ_REG(hw, E1000_FCRUC);
 897         stats->prc64 += E1000_READ_REG(hw, E1000_PRC64);
 898         stats->prc127 += E1000_READ_REG(hw, E1000_PRC127);
 899         stats->prc255 += E1000_READ_REG(hw, E1000_PRC255);
 900         stats->prc511 += E1000_READ_REG(hw, E1000_PRC511);
 901         stats->prc1023 += E1000_READ_REG(hw, E1000_PRC1023);
 902         stats->prc1522 += E1000_READ_REG(hw, E1000_PRC1522);
 903         stats->gprc += E1000_READ_REG(hw, E1000_GPRC);
 904         stats->bprc += E1000_READ_REG(hw, E1000_BPRC);
 905         stats->mprc += E1000_READ_REG(hw, E1000_MPRC);
 906         stats->gptc += E1000_READ_REG(hw, E1000_GPTC);
 907
 908         /*
 909          * For the 64-bit byte counters the low dword must be read first.
 910          * Both registers clear on the read of the high dword.
 911          */
 912
 913         stats->gorc += E1000_READ_REG(hw, E1000_GORCL);
 914         stats->gorc += ((uint64_t)E1000_READ_REG(hw, E1000_GORCH) << 32);
 915         stats->gotc += E1000_READ_REG(hw, E1000_GOTCL);
 916         stats->gotc += ((uint64_t)E1000_READ_REG(hw, E1000_GOTCH) << 32);
 917
 918         stats->rnbc += E1000_READ_REG(hw, E1000_RNBC);
 919         stats->ruc += E1000_READ_REG(hw, E1000_RUC);
 920         stats->rfc += E1000_READ_REG(hw, E1000_RFC);
 921         stats->roc += E1000_READ_REG(hw, E1000_ROC);
 922         stats->rjc += E1000_READ_REG(hw, E1000_RJC);
 923
 924         stats->tor += E1000_READ_REG(hw, E1000_TORH);
 925         stats->tot += E1000_READ_REG(hw, E1000_TOTH);
 926
 927         stats->tpr += E1000_READ_REG(hw, E1000_TPR);
 928         stats->tpt += E1000_READ_REG(hw, E1000_TPT);
 929         stats->ptc64 += E1000_READ_REG(hw, E1000_PTC64);
 930         stats->ptc127 += E1000_READ_REG(hw, E1000_PTC127);
 931         stats->ptc255 += E1000_READ_REG(hw, E1000_PTC255);
 932         stats->ptc511 += E1000_READ_REG(hw, E1000_PTC511);
 933         stats->ptc1023 += E1000_READ_REG(hw, E1000_PTC1023);
 934         stats->ptc1522 += E1000_READ_REG(hw, E1000_PTC1522);
 935         stats->mptc += E1000_READ_REG(hw, E1000_MPTC);
 936         stats->bptc += E1000_READ_REG(hw, E1000_BPTC);
 937
 938         /* Interrupt Counts */
 939
 940         if (hw->mac.type >= e1000_82571) {
 941                 stats->iac += E1000_READ_REG(hw, E1000_IAC);
 942                 stats->icrxptc += E1000_READ_REG(hw, E1000_ICRXPTC);
 943                 stats->icrxatc += E1000_READ_REG(hw, E1000_ICRXATC);
 944                 stats->ictxptc += E1000_READ_REG(hw, E1000_ICTXPTC);
 945                 stats->ictxatc += E1000_READ_REG(hw, E1000_ICTXATC);
 946                 stats->ictxqec += E1000_READ_REG(hw, E1000_ICTXQEC);
 947                 stats->ictxqmtc += E1000_READ_REG(hw, E1000_ICTXQMTC);
 948                 stats->icrxdmtc += E1000_READ_REG(hw, E1000_ICRXDMTC);
 949                 stats->icrxoc += E1000_READ_REG(hw, E1000_ICRXOC);
 950         }
 951
 952         if (hw->mac.type >= e1000_82543) {
 953                 stats->algnerrc += E1000_READ_REG(hw, E1000_ALGNERRC);
 954                 stats->rxerrc += E1000_READ_REG(hw, E1000_RXERRC);
 955                 stats->tncrs += E1000_READ_REG(hw, E1000_TNCRS);
 956                 stats->cexterr += E1000_READ_REG(hw, E1000_CEXTERR);
 957                 stats->tsctc += E1000_READ_REG(hw, E1000_TSCTC);
 958                 stats->tsctfc += E1000_READ_REG(hw, E1000_TSCTFC);
 959         }
 960
 961         if (rte_stats == NULL)
 962                 return;
 963
 964         /* Rx Errors */
 965         rte_stats->imissed = stats->mpc;
 966         rte_stats->ierrors = stats->crcerrs +
 967                              stats->rlec + stats->ruc + stats->roc +
 968                              stats->rxerrc + stats->algnerrc + stats->cexterr;
 969
 970         /* Tx Errors */
 971         rte_stats->oerrors = stats->ecol + stats->latecol;
 972
 973         rte_stats->ipackets = stats->gprc;
 974         rte_stats->opackets = stats->gptc;
 975         rte_stats->ibytes   = stats->gorc;
 976         rte_stats->obytes   = stats->gotc;
 977 }
 978
 979 static void
 980 eth_em_stats_reset(struct rte_eth_dev *dev)
 981 {
 982         struct e1000_hw_stats *hw_stats =
 983                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
 984
 985         /* HW registers are cleared on read */
 986         eth_em_stats_get(dev, NULL);
 987
 988         /* Reset software totals */
 989         memset(hw_stats, 0, sizeof(*hw_stats));
 990 }
 991
 992 static int
 993 eth_em_rx_queue_intr_enable(struct rte_eth_dev *dev, __rte_unused uint16_t queue_id)
 994 {
 995         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 996
 997         em_rxq_intr_enable(hw);
 998         rte_intr_enable(&dev->pci_dev->intr_handle);
 999
1000         return 0;
1001 }
1002
1003 static int
1004 eth_em_rx_queue_intr_disable(struct rte_eth_dev *dev, __rte_unused uint16_t queue_id)
1005 {
1006         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1007
1008         em_rxq_intr_disable(hw);
1009
1010         return 0;
1011 }
1012
1013 static uint32_t
1014 em_get_max_pktlen(const struct e1000_hw *hw)
1015 {
1016         switch (hw->mac.type) {
1017         case e1000_82571:
1018         case e1000_82572:
1019         case e1000_ich9lan:
1020         case e1000_ich10lan:
1021         case e1000_pch2lan:
1022         case e1000_pch_lpt:
1023         case e1000_82574:
1024         case e1000_80003es2lan: /* 9K Jumbo Frame size */
1025         case e1000_82583:
1026                 return 0x2412;
1027         case e1000_pchlan:
1028                 return 0x1000;
1029         /* Adapters that do not support jumbo frames */
1030         case e1000_ich8lan:
1031                 return ETHER_MAX_LEN;
1032         default:
1033                 return MAX_JUMBO_FRAME_SIZE;
1034         }
1035 }
1036
1037 static void
1038 eth_em_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
1039 {
1040         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1041
1042         dev_info->min_rx_bufsize = 256; /* See BSIZE field of RCTL register. */
1043         dev_info->max_rx_pktlen = em_get_max_pktlen(hw);
1044         dev_info->max_mac_addrs = hw->mac.rar_entry_count;
1045
1046         /*
1047          * Starting with 631xESB hw supports 2 TX/RX queues per port.
1048          * Unfortunatelly, all these nics have just one TX context.
1049          * So we have few choises for TX:
1050          * - Use just one TX queue.
1051          * - Allow cksum offload only for one TX queue.
1052          * - Don't allow TX cksum offload at all.
1053          * For now, option #1 was chosen.
1054          * To use second RX queue we have to use extended RX descriptor
1055          * (Multiple Receive Queues are mutually exclusive with UDP
1056          * fragmentation and are not supported when a legacy receive
1057          * descriptor format is used).
1058          * Which means separate RX routinies - as legacy nics (82540, 82545)
1059          * don't support extended RXD.
1060          * To avoid it we support just one RX queue for now (no RSS).
1061          */
1062
1063         dev_info->max_rx_queues = 1;
1064         dev_info->max_tx_queues = 1;
1065
1066         dev_info->rx_desc_lim = (struct rte_eth_desc_lim) {
1067                 .nb_max = E1000_MAX_RING_DESC,
1068                 .nb_min = E1000_MIN_RING_DESC,
1069                 .nb_align = EM_RXD_ALIGN,
1070         };
1071
1072         dev_info->tx_desc_lim = (struct rte_eth_desc_lim) {
1073                 .nb_max = E1000_MAX_RING_DESC,
1074                 .nb_min = E1000_MIN_RING_DESC,
1075                 .nb_align = EM_TXD_ALIGN,
1076         };
1077
1078         dev_info->speed_capa = ETH_LINK_SPEED_10M_HD | ETH_LINK_SPEED_10M |
1079                         ETH_LINK_SPEED_100M_HD | ETH_LINK_SPEED_100M |
1080                         ETH_LINK_SPEED_1G;
1081 }
1082
1083 /* return 0 means link status changed, -1 means not changed */
1084 static int
1085 eth_em_link_update(struct rte_eth_dev *dev, int wait_to_complete)
1086 {
1087         struct e1000_hw *hw =
1088                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1089         struct rte_eth_link link, old;
1090         int link_check, count;
1091
1092         link_check = 0;
1093         hw->mac.get_link_status = 1;
1094
1095         /* possible wait-to-complete in up to 9 seconds */
1096         for (count = 0; count < EM_LINK_UPDATE_CHECK_TIMEOUT; count ++) {
1097                 /* Read the real link status */
1098                 switch (hw->phy.media_type) {
1099                 case e1000_media_type_copper:
1100                         /* Do the work to read phy */
1101                         e1000_check_for_link(hw);
1102                         link_check = !hw->mac.get_link_status;
1103                         break;
1104
1105                 case e1000_media_type_fiber:
1106                         e1000_check_for_link(hw);
1107                         link_check = (E1000_READ_REG(hw, E1000_STATUS) &
1108                                         E1000_STATUS_LU);
1109                         break;
1110
1111                 case e1000_media_type_internal_serdes:
1112                         e1000_check_for_link(hw);
1113                         link_check = hw->mac.serdes_has_link;
1114                         break;
1115
1116                 default:
1117                         break;
1118                 }
1119                 if (link_check || wait_to_complete == 0)
1120                         break;
1121                 rte_delay_ms(EM_LINK_UPDATE_CHECK_INTERVAL);
1122         }
1123         memset(&link, 0, sizeof(link));
1124         rte_em_dev_atomic_read_link_status(dev, &link);
1125         old = link;
1126
1127         /* Now we check if a transition has happened */
1128         if (link_check && (link.link_status == ETH_LINK_DOWN)) {
1129                 uint16_t duplex, speed;
1130                 hw->mac.ops.get_link_up_info(hw, &speed, &duplex);
1131                 link.link_duplex = (duplex == FULL_DUPLEX) ?
1132                                 ETH_LINK_FULL_DUPLEX :
1133                                 ETH_LINK_HALF_DUPLEX;
1134                 link.link_speed = speed;
1135                 link.link_status = ETH_LINK_UP;
1136                 link.link_autoneg = !(dev->data->dev_conf.link_speeds &
1137                                 ETH_LINK_SPEED_FIXED);
1138         } else if (!link_check && (link.link_status == ETH_LINK_UP)) {
1139                 link.link_speed = 0;
1140                 link.link_duplex = ETH_LINK_HALF_DUPLEX;
1141                 link.link_status = ETH_LINK_DOWN;
1142                 link.link_autoneg = ETH_LINK_SPEED_FIXED;
1143         }
1144         rte_em_dev_atomic_write_link_status(dev, &link);
1145
1146         /* not changed */
1147         if (old.link_status == link.link_status)
1148                 return -1;
1149
1150         /* changed */
1151         return 0;
1152 }
1153
1154 /*
1155  * em_hw_control_acquire sets {CTRL_EXT|FWSM}:DRV_LOAD bit.
1156  * For ASF and Pass Through versions of f/w this means
1157  * that the driver is loaded. For AMT version type f/w
1158  * this means that the network i/f is open.
1159  */
1160 static void
1161 em_hw_control_acquire(struct e1000_hw *hw)
1162 {
1163         uint32_t ctrl_ext, swsm;
1164
1165         /* Let firmware know the driver has taken over */
1166         if (hw->mac.type == e1000_82573) {
1167                 swsm = E1000_READ_REG(hw, E1000_SWSM);
1168                 E1000_WRITE_REG(hw, E1000_SWSM, swsm | E1000_SWSM_DRV_LOAD);
1169
1170         } else {
1171                 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
1172                 E1000_WRITE_REG(hw, E1000_CTRL_EXT,
1173                         ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
1174         }
1175 }
1176
1177 /*
1178  * em_hw_control_release resets {CTRL_EXTT|FWSM}:DRV_LOAD bit.
1179  * For ASF and Pass Through versions of f/w this means that the
1180  * driver is no longer loaded. For AMT versions of the
1181  * f/w this means that the network i/f is closed.
1182  */
1183 static void
1184 em_hw_control_release(struct e1000_hw *hw)
1185 {
1186         uint32_t ctrl_ext, swsm;
1187
1188         /* Let firmware taken over control of h/w */
1189         if (hw->mac.type == e1000_82573) {
1190                 swsm = E1000_READ_REG(hw, E1000_SWSM);
1191                 E1000_WRITE_REG(hw, E1000_SWSM, swsm & ~E1000_SWSM_DRV_LOAD);
1192         } else {
1193                 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
1194                 E1000_WRITE_REG(hw, E1000_CTRL_EXT,
1195                         ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
1196         }
1197 }
1198
1199 /*
1200  * Bit of a misnomer, what this really means is
1201  * to enable OS management of the system... aka
1202  * to disable special hardware management features.
1203  */
1204 static void
1205 em_init_manageability(struct e1000_hw *hw)
1206 {
1207         if (e1000_enable_mng_pass_thru(hw)) {
1208                 uint32_t manc2h = E1000_READ_REG(hw, E1000_MANC2H);
1209                 uint32_t manc = E1000_READ_REG(hw, E1000_MANC);
1210
1211                 /* disable hardware interception of ARP */
1212                 manc &= ~(E1000_MANC_ARP_EN);
1213
1214                 /* enable receiving management packets to the host */
1215                 manc |= E1000_MANC_EN_MNG2HOST;
1216                 manc2h |= 1 << 5;  /* Mng Port 623 */
1217                 manc2h |= 1 << 6;  /* Mng Port 664 */
1218                 E1000_WRITE_REG(hw, E1000_MANC2H, manc2h);
1219                 E1000_WRITE_REG(hw, E1000_MANC, manc);
1220         }
1221 }
1222
1223 /*
1224  * Give control back to hardware management
1225  * controller if there is one.
1226  */
1227 static void
1228 em_release_manageability(struct e1000_hw *hw)
1229 {
1230         uint32_t manc;
1231
1232         if (e1000_enable_mng_pass_thru(hw)) {
1233                 manc = E1000_READ_REG(hw, E1000_MANC);
1234
1235                 /* re-enable hardware interception of ARP */
1236                 manc |= E1000_MANC_ARP_EN;
1237                 manc &= ~E1000_MANC_EN_MNG2HOST;
1238
1239                 E1000_WRITE_REG(hw, E1000_MANC, manc);
1240         }
1241 }
1242
1243 static void
1244 eth_em_promiscuous_enable(struct rte_eth_dev *dev)
1245 {
1246         struct e1000_hw *hw =
1247                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1248         uint32_t rctl;
1249
1250         rctl = E1000_READ_REG(hw, E1000_RCTL);
1251         rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
1252         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1253 }
1254
1255 static void
1256 eth_em_promiscuous_disable(struct rte_eth_dev *dev)
1257 {
1258         struct e1000_hw *hw =
1259                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1260         uint32_t rctl;
1261
1262         rctl = E1000_READ_REG(hw, E1000_RCTL);
1263         rctl &= ~(E1000_RCTL_UPE | E1000_RCTL_SBP);
1264         if (dev->data->all_multicast == 1)
1265                 rctl |= E1000_RCTL_MPE;
1266         else
1267                 rctl &= (~E1000_RCTL_MPE);
1268         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1269 }
1270
1271 static void
1272 eth_em_allmulticast_enable(struct rte_eth_dev *dev)
1273 {
1274         struct e1000_hw *hw =
1275                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1276         uint32_t rctl;
1277
1278         rctl = E1000_READ_REG(hw, E1000_RCTL);
1279         rctl |= E1000_RCTL_MPE;
1280         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1281 }
1282
1283 static void
1284 eth_em_allmulticast_disable(struct rte_eth_dev *dev)
1285 {
1286         struct e1000_hw *hw =
1287                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1288         uint32_t rctl;
1289
1290         if (dev->data->promiscuous == 1)
1291                 return; /* must remain in all_multicast mode */
1292         rctl = E1000_READ_REG(hw, E1000_RCTL);
1293         rctl &= (~E1000_RCTL_MPE);
1294         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1295 }
1296
1297 static int
1298 eth_em_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1299 {
1300         struct e1000_hw *hw =
1301                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1302         struct e1000_vfta * shadow_vfta =
1303                 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1304         uint32_t vfta;
1305         uint32_t vid_idx;
1306         uint32_t vid_bit;
1307
1308         vid_idx = (uint32_t) ((vlan_id >> E1000_VFTA_ENTRY_SHIFT) &
1309                               E1000_VFTA_ENTRY_MASK);
1310         vid_bit = (uint32_t) (1 << (vlan_id & E1000_VFTA_ENTRY_BIT_SHIFT_MASK));
1311         vfta = E1000_READ_REG_ARRAY(hw, E1000_VFTA, vid_idx);
1312         if (on)
1313                 vfta |= vid_bit;
1314         else
1315                 vfta &= ~vid_bit;
1316         E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, vid_idx, vfta);
1317
1318         /* update local VFTA copy */
1319         shadow_vfta->vfta[vid_idx] = vfta;
1320
1321         return 0;
1322 }
1323
1324 static void
1325 em_vlan_hw_filter_disable(struct rte_eth_dev *dev)
1326 {
1327         struct e1000_hw *hw =
1328                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1329         uint32_t reg;
1330
1331         /* Filter Table Disable */
1332         reg = E1000_READ_REG(hw, E1000_RCTL);
1333         reg &= ~E1000_RCTL_CFIEN;
1334         reg &= ~E1000_RCTL_VFE;
1335         E1000_WRITE_REG(hw, E1000_RCTL, reg);
1336 }
1337
1338 static void
1339 em_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1340 {
1341         struct e1000_hw *hw =
1342                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1343         struct e1000_vfta * shadow_vfta =
1344                 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1345         uint32_t reg;
1346         int i;
1347
1348         /* Filter Table Enable, CFI not used for packet acceptance */
1349         reg = E1000_READ_REG(hw, E1000_RCTL);
1350         reg &= ~E1000_RCTL_CFIEN;
1351         reg |= E1000_RCTL_VFE;
1352         E1000_WRITE_REG(hw, E1000_RCTL, reg);
1353
1354         /* restore vfta from local copy */
1355         for (i = 0; i < IGB_VFTA_SIZE; i++)
1356                 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, i, shadow_vfta->vfta[i]);
1357 }
1358
1359 static void
1360 em_vlan_hw_strip_disable(struct rte_eth_dev *dev)
1361 {
1362         struct e1000_hw *hw =
1363                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1364         uint32_t reg;
1365
1366         /* VLAN Mode Disable */
1367         reg = E1000_READ_REG(hw, E1000_CTRL);
1368         reg &= ~E1000_CTRL_VME;
1369         E1000_WRITE_REG(hw, E1000_CTRL, reg);
1370
1371 }
1372
1373 static void
1374 em_vlan_hw_strip_enable(struct rte_eth_dev *dev)
1375 {
1376         struct e1000_hw *hw =
1377                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1378         uint32_t reg;
1379
1380         /* VLAN Mode Enable */
1381         reg = E1000_READ_REG(hw, E1000_CTRL);
1382         reg |= E1000_CTRL_VME;
1383         E1000_WRITE_REG(hw, E1000_CTRL, reg);
1384 }
1385
1386 static void
1387 eth_em_vlan_offload_set(struct rte_eth_dev *dev, int mask)
1388 {
1389         if(mask & ETH_VLAN_STRIP_MASK){
1390                 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
1391                         em_vlan_hw_strip_enable(dev);
1392                 else
1393                         em_vlan_hw_strip_disable(dev);
1394         }
1395
1396         if(mask & ETH_VLAN_FILTER_MASK){
1397                 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
1398                         em_vlan_hw_filter_enable(dev);
1399                 else
1400                         em_vlan_hw_filter_disable(dev);
1401         }
1402 }
1403
1404 /*
1405  * It enables the interrupt mask and then enable the interrupt.
1406  *
1407  * @param dev
1408  *  Pointer to struct rte_eth_dev.
1409  *
1410  * @return
1411  *  - On success, zero.
1412  *  - On failure, a negative value.
1413  */
1414 static int
1415 eth_em_interrupt_setup(struct rte_eth_dev *dev)
1416 {
1417         uint32_t regval;
1418         struct e1000_hw *hw =
1419                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1420
1421         /* clear interrupt */
1422         E1000_READ_REG(hw, E1000_ICR);
1423         regval = E1000_READ_REG(hw, E1000_IMS);
1424         E1000_WRITE_REG(hw, E1000_IMS, regval | E1000_ICR_LSC);
1425         return 0;
1426 }
1427
1428 /*
1429  * It clears the interrupt causes and enables the interrupt.
1430  * It will be called once only during nic initialized.
1431  *
1432  * @param dev
1433  *  Pointer to struct rte_eth_dev.
1434  *
1435  * @return
1436  *  - On success, zero.
1437  *  - On failure, a negative value.
1438  */
1439 static int
1440 eth_em_rxq_interrupt_setup(struct rte_eth_dev *dev)
1441 {
1442         struct e1000_hw *hw =
1443         E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1444
1445         E1000_READ_REG(hw, E1000_ICR);
1446         em_rxq_intr_enable(hw);
1447         return 0;
1448 }
1449
1450 /*
1451  * It enable receive packet interrupt.
1452  * @param hw
1453  * Pointer to struct e1000_hw
1454  *
1455  * @return
1456  */
1457 static void
1458 em_rxq_intr_enable(struct e1000_hw *hw)
1459 {
1460         E1000_WRITE_REG(hw, E1000_IMS, E1000_IMS_RXT0);
1461         E1000_WRITE_FLUSH(hw);
1462 }
1463
1464 /*
1465  * It disabled lsc interrupt.
1466  * @param hw
1467  * Pointer to struct e1000_hw
1468  *
1469  * @return
1470  */
1471 static void
1472 em_lsc_intr_disable(struct e1000_hw *hw)
1473 {
1474         E1000_WRITE_REG(hw, E1000_IMC, E1000_IMS_LSC);
1475         E1000_WRITE_FLUSH(hw);
1476 }
1477
1478 /*
1479  * It disabled receive packet interrupt.
1480  * @param hw
1481  * Pointer to struct e1000_hw
1482  *
1483  * @return
1484  */
1485 static void
1486 em_rxq_intr_disable(struct e1000_hw *hw)
1487 {
1488         E1000_READ_REG(hw, E1000_ICR);
1489         E1000_WRITE_REG(hw, E1000_IMC, E1000_IMS_RXT0);
1490         E1000_WRITE_FLUSH(hw);
1491 }
1492
1493 /*
1494  * It reads ICR and gets interrupt causes, check it and set a bit flag
1495  * to update link status.
1496  *
1497  * @param dev
1498  *  Pointer to struct rte_eth_dev.
1499  *
1500  * @return
1501  *  - On success, zero.
1502  *  - On failure, a negative value.
1503  */
1504 static int
1505 eth_em_interrupt_get_status(struct rte_eth_dev *dev)
1506 {
1507         uint32_t icr;
1508         struct e1000_hw *hw =
1509                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1510         struct e1000_interrupt *intr =
1511                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
1512
1513         /* read-on-clear nic registers here */
1514         icr = E1000_READ_REG(hw, E1000_ICR);
1515         if (icr & E1000_ICR_LSC) {
1516                 intr->flags |= E1000_FLAG_NEED_LINK_UPDATE;
1517         }
1518
1519         return 0;
1520 }
1521
1522 /*
1523  * It executes link_update after knowing an interrupt is prsent.
1524  *
1525  * @param dev
1526  *  Pointer to struct rte_eth_dev.
1527  *
1528  * @return
1529  *  - On success, zero.
1530  *  - On failure, a negative value.
1531  */
1532 static int
1533 eth_em_interrupt_action(struct rte_eth_dev *dev)
1534 {
1535         struct e1000_hw *hw =
1536                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1537         struct e1000_interrupt *intr =
1538                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
1539         uint32_t tctl, rctl;
1540         struct rte_eth_link link;
1541         int ret;
1542
1543         if (!(intr->flags & E1000_FLAG_NEED_LINK_UPDATE))
1544                 return -1;
1545
1546         intr->flags &= ~E1000_FLAG_NEED_LINK_UPDATE;
1547         rte_intr_enable(&(dev->pci_dev->intr_handle));
1548
1549         /* set get_link_status to check register later */
1550         hw->mac.get_link_status = 1;
1551         ret = eth_em_link_update(dev, 0);
1552
1553         /* check if link has changed */
1554         if (ret < 0)
1555                 return 0;
1556
1557         memset(&link, 0, sizeof(link));
1558         rte_em_dev_atomic_read_link_status(dev, &link);
1559         if (link.link_status) {
1560                 PMD_INIT_LOG(INFO, " Port %d: Link Up - speed %u Mbps - %s",
1561                              dev->data->port_id, (unsigned)link.link_speed,
1562                              link.link_duplex == ETH_LINK_FULL_DUPLEX ?
1563                              "full-duplex" : "half-duplex");
1564         } else {
1565                 PMD_INIT_LOG(INFO, " Port %d: Link Down", dev->data->port_id);
1566         }
1567         PMD_INIT_LOG(DEBUG, "PCI Address: %04d:%02d:%02d:%d",
1568                      dev->pci_dev->addr.domain, dev->pci_dev->addr.bus,
1569                      dev->pci_dev->addr.devid, dev->pci_dev->addr.function);
1570
1571         tctl = E1000_READ_REG(hw, E1000_TCTL);
1572         rctl = E1000_READ_REG(hw, E1000_RCTL);
1573         if (link.link_status) {
1574                 /* enable Tx/Rx */
1575                 tctl |= E1000_TCTL_EN;
1576                 rctl |= E1000_RCTL_EN;
1577         } else {
1578                 /* disable Tx/Rx */
1579                 tctl &= ~E1000_TCTL_EN;
1580                 rctl &= ~E1000_RCTL_EN;
1581         }
1582         E1000_WRITE_REG(hw, E1000_TCTL, tctl);
1583         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1584         E1000_WRITE_FLUSH(hw);
1585
1586         return 0;
1587 }
1588
1589 /**
1590  * Interrupt handler which shall be registered at first.
1591  *
1592  * @param handle
1593  *  Pointer to interrupt handle.
1594  * @param param
1595  *  The address of parameter (struct rte_eth_dev *) regsitered before.
1596  *
1597  * @return
1598  *  void
1599  */
1600 static void
1601 eth_em_interrupt_handler(__rte_unused struct rte_intr_handle *handle,
1602                                                         void *param)
1603 {
1604         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
1605
1606         eth_em_interrupt_get_status(dev);
1607         eth_em_interrupt_action(dev);
1608         _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC);
1609 }
1610
1611 static int
1612 eth_em_led_on(struct rte_eth_dev *dev)
1613 {
1614         struct e1000_hw *hw;
1615
1616         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1617         return e1000_led_on(hw) == E1000_SUCCESS ? 0 : -ENOTSUP;
1618 }
1619
1620 static int
1621 eth_em_led_off(struct rte_eth_dev *dev)
1622 {
1623         struct e1000_hw *hw;
1624
1625         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1626         return e1000_led_off(hw) == E1000_SUCCESS ? 0 : -ENOTSUP;
1627 }
1628
1629 static int
1630 eth_em_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
1631 {
1632         struct e1000_hw *hw;
1633         uint32_t ctrl;
1634         int tx_pause;
1635         int rx_pause;
1636
1637         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1638         fc_conf->pause_time = hw->fc.pause_time;
1639         fc_conf->high_water = hw->fc.high_water;
1640         fc_conf->low_water = hw->fc.low_water;
1641         fc_conf->send_xon = hw->fc.send_xon;
1642         fc_conf->autoneg = hw->mac.autoneg;
1643
1644         /*
1645          * Return rx_pause and tx_pause status according to actual setting of
1646          * the TFCE and RFCE bits in the CTRL register.
1647          */
1648         ctrl = E1000_READ_REG(hw, E1000_CTRL);
1649         if (ctrl & E1000_CTRL_TFCE)
1650                 tx_pause = 1;
1651         else
1652                 tx_pause = 0;
1653
1654         if (ctrl & E1000_CTRL_RFCE)
1655                 rx_pause = 1;
1656         else
1657                 rx_pause = 0;
1658
1659         if (rx_pause && tx_pause)
1660                 fc_conf->mode = RTE_FC_FULL;
1661         else if (rx_pause)
1662                 fc_conf->mode = RTE_FC_RX_PAUSE;
1663         else if (tx_pause)
1664                 fc_conf->mode = RTE_FC_TX_PAUSE;
1665         else
1666                 fc_conf->mode = RTE_FC_NONE;
1667
1668         return 0;
1669 }
1670
1671 static int
1672 eth_em_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
1673 {
1674         struct e1000_hw *hw;
1675         int err;
1676         enum e1000_fc_mode rte_fcmode_2_e1000_fcmode[] = {
1677                 e1000_fc_none,
1678                 e1000_fc_rx_pause,
1679                 e1000_fc_tx_pause,
1680                 e1000_fc_full
1681         };
1682         uint32_t rx_buf_size;
1683         uint32_t max_high_water;
1684         uint32_t rctl;
1685
1686         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1687         if (fc_conf->autoneg != hw->mac.autoneg)
1688                 return -ENOTSUP;
1689         rx_buf_size = em_get_rx_buffer_size(hw);
1690         PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
1691
1692         /* At least reserve one Ethernet frame for watermark */
1693         max_high_water = rx_buf_size - ETHER_MAX_LEN;
1694         if ((fc_conf->high_water > max_high_water) ||
1695             (fc_conf->high_water < fc_conf->low_water)) {
1696                 PMD_INIT_LOG(ERR, "e1000 incorrect high/low water value");
1697                 PMD_INIT_LOG(ERR, "high water must <= 0x%x", max_high_water);
1698                 return -EINVAL;
1699         }
1700
1701         hw->fc.requested_mode = rte_fcmode_2_e1000_fcmode[fc_conf->mode];
1702         hw->fc.pause_time     = fc_conf->pause_time;
1703         hw->fc.high_water     = fc_conf->high_water;
1704         hw->fc.low_water      = fc_conf->low_water;
1705         hw->fc.send_xon       = fc_conf->send_xon;
1706
1707         err = e1000_setup_link_generic(hw);
1708         if (err == E1000_SUCCESS) {
1709
1710                 /* check if we want to forward MAC frames - driver doesn't have native
1711                  * capability to do that, so we'll write the registers ourselves */
1712
1713                 rctl = E1000_READ_REG(hw, E1000_RCTL);
1714
1715                 /* set or clear MFLCN.PMCF bit depending on configuration */
1716                 if (fc_conf->mac_ctrl_frame_fwd != 0)
1717                         rctl |= E1000_RCTL_PMCF;
1718                 else
1719                         rctl &= ~E1000_RCTL_PMCF;
1720
1721                 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1722                 E1000_WRITE_FLUSH(hw);
1723
1724                 return 0;
1725         }
1726
1727         PMD_INIT_LOG(ERR, "e1000_setup_link_generic = 0x%x", err);
1728         return -EIO;
1729 }
1730
1731 static void
1732 eth_em_rar_set(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
1733                 uint32_t index, __rte_unused uint32_t pool)
1734 {
1735         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1736
1737         e1000_rar_set(hw, mac_addr->addr_bytes, index);
1738 }
1739
1740 static void
1741 eth_em_rar_clear(struct rte_eth_dev *dev, uint32_t index)
1742 {
1743         uint8_t addr[ETHER_ADDR_LEN];
1744         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1745
1746         memset(addr, 0, sizeof(addr));
1747
1748         e1000_rar_set(hw, addr, index);
1749 }
1750
1751 static int
1752 eth_em_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
1753 {
1754         struct rte_eth_dev_info dev_info;
1755         struct e1000_hw *hw;
1756         uint32_t frame_size;
1757         uint32_t rctl;
1758
1759         eth_em_infos_get(dev, &dev_info);
1760         frame_size = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN + VLAN_TAG_SIZE;
1761
1762         /* check that mtu is within the allowed range */
1763         if ((mtu < ETHER_MIN_MTU) || (frame_size > dev_info.max_rx_pktlen))
1764                 return -EINVAL;
1765
1766         /* refuse mtu that requires the support of scattered packets when this
1767          * feature has not been enabled before. */
1768         if (!dev->data->scattered_rx &&
1769             frame_size > dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)
1770                 return -EINVAL;
1771
1772         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1773         rctl = E1000_READ_REG(hw, E1000_RCTL);
1774
1775         /* switch to jumbo mode if needed */
1776         if (frame_size > ETHER_MAX_LEN) {
1777                 dev->data->dev_conf.rxmode.jumbo_frame = 1;
1778                 rctl |= E1000_RCTL_LPE;
1779         } else {
1780                 dev->data->dev_conf.rxmode.jumbo_frame = 0;
1781                 rctl &= ~E1000_RCTL_LPE;
1782         }
1783         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1784
1785         /* update max frame size */
1786         dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
1787         return 0;
1788 }
1789
1790 static int
1791 eth_em_set_mc_addr_list(struct rte_eth_dev *dev,
1792                         struct ether_addr *mc_addr_set,
1793                         uint32_t nb_mc_addr)
1794 {
1795         struct e1000_hw *hw;
1796
1797         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1798         e1000_update_mc_addr_list(hw, (u8 *)mc_addr_set, nb_mc_addr);
1799         return 0;
1800 }
1801
1802 struct rte_driver em_pmd_drv = {
1803         .type = PMD_PDEV,
1804         .init = rte_em_pmd_init,
1805 };
1806
1807 PMD_REGISTER_DRIVER(em_pmd_drv, em);
1808 DRIVER_REGISTER_PCI_TABLE(em, pci_id_em_map);