drivers/net/e1000/igb_ethdev.c

   1 /*-
   2  *   BSD LICENSE
   3  *
   4  *   Copyright(c) 2010-2016 Intel Corporation. All rights reserved.
   5  *   All rights reserved.
   6  *
   7  *   Redistribution and use in source and binary forms, with or without
   8  *   modification, are permitted provided that the following conditions
   9  *   are met:
  10  *
  11  *     * Redistributions of source code must retain the above copyright
  12  *       notice, this list of conditions and the following disclaimer.
  13  *     * Redistributions in binary form must reproduce the above copyright
  14  *       notice, this list of conditions and the following disclaimer in
  15  *       the documentation and/or other materials provided with the
  16  *       distribution.
  17  *     * Neither the name of Intel Corporation nor the names of its
  18  *       contributors may be used to endorse or promote products derived
  19  *       from this software without specific prior written permission.
  20  *
  21  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 #include <sys/queue.h>
  35 #include <stdio.h>
  36 #include <errno.h>
  37 #include <stdint.h>
  38 #include <stdarg.h>
  39
  40 #include <rte_common.h>
  41 #include <rte_interrupts.h>
  42 #include <rte_byteorder.h>
  43 #include <rte_log.h>
  44 #include <rte_debug.h>
  45 #include <rte_pci.h>
  46 #include <rte_ether.h>
  47 #include <rte_ethdev.h>
  48 #include <rte_ethdev_pci.h>
  49 #include <rte_memory.h>
  50 #include <rte_memzone.h>
  51 #include <rte_eal.h>
  52 #include <rte_atomic.h>
  53 #include <rte_malloc.h>
  54 #include <rte_dev.h>
  55
  56 #include "e1000_logs.h"
  57 #include "base/e1000_api.h"
  58 #include "e1000_ethdev.h"
  59 #include "igb_regs.h"
  60
  61 /*
  62  * Default values for port configuration
  63  */
  64 #define IGB_DEFAULT_RX_FREE_THRESH  32
  65
  66 #define IGB_DEFAULT_RX_PTHRESH      ((hw->mac.type == e1000_i354) ? 12 : 8)
  67 #define IGB_DEFAULT_RX_HTHRESH      8
  68 #define IGB_DEFAULT_RX_WTHRESH      ((hw->mac.type == e1000_82576) ? 1 : 4)
  69
  70 #define IGB_DEFAULT_TX_PTHRESH      ((hw->mac.type == e1000_i354) ? 20 : 8)
  71 #define IGB_DEFAULT_TX_HTHRESH      1
  72 #define IGB_DEFAULT_TX_WTHRESH      ((hw->mac.type == e1000_82576) ? 1 : 16)
  73
  74 #define IGB_HKEY_MAX_INDEX 10
  75
  76 /* Bit shift and mask */
  77 #define IGB_4_BIT_WIDTH  (CHAR_BIT / 2)
  78 #define IGB_4_BIT_MASK   RTE_LEN2MASK(IGB_4_BIT_WIDTH, uint8_t)
  79 #define IGB_8_BIT_WIDTH  CHAR_BIT
  80 #define IGB_8_BIT_MASK   UINT8_MAX
  81
  82 /* Additional timesync values. */
  83 #define E1000_CYCLECOUNTER_MASK      0xffffffffffffffffULL
  84 #define E1000_ETQF_FILTER_1588       3
  85 #define IGB_82576_TSYNC_SHIFT        16
  86 #define E1000_INCPERIOD_82576        (1 << E1000_TIMINCA_16NS_SHIFT)
  87 #define E1000_INCVALUE_82576         (16 << IGB_82576_TSYNC_SHIFT)
  88 #define E1000_TSAUXC_DISABLE_SYSTIME 0x80000000
  89
  90 #define E1000_VTIVAR_MISC                0x01740
  91 #define E1000_VTIVAR_MISC_MASK           0xFF
  92 #define E1000_VTIVAR_VALID               0x80
  93 #define E1000_VTIVAR_MISC_MAILBOX        0
  94 #define E1000_VTIVAR_MISC_INTR_MASK      0x3
  95
  96 /* External VLAN Enable bit mask */
  97 #define E1000_CTRL_EXT_EXT_VLAN      (1 << 26)
  98
  99 /* External VLAN Ether Type bit mask and shift */
 100 #define E1000_VET_VET_EXT            0xFFFF0000
 101 #define E1000_VET_VET_EXT_SHIFT      16
 102
 103 static int  eth_igb_configure(struct rte_eth_dev *dev);
 104 static int  eth_igb_start(struct rte_eth_dev *dev);
 105 static void eth_igb_stop(struct rte_eth_dev *dev);
 106 static int  eth_igb_dev_set_link_up(struct rte_eth_dev *dev);
 107 static int  eth_igb_dev_set_link_down(struct rte_eth_dev *dev);
 108 static void eth_igb_close(struct rte_eth_dev *dev);
 109 static void eth_igb_promiscuous_enable(struct rte_eth_dev *dev);
 110 static void eth_igb_promiscuous_disable(struct rte_eth_dev *dev);
 111 static void eth_igb_allmulticast_enable(struct rte_eth_dev *dev);
 112 static void eth_igb_allmulticast_disable(struct rte_eth_dev *dev);
 113 static int  eth_igb_link_update(struct rte_eth_dev *dev,
 114                                 int wait_to_complete);
 115 static void eth_igb_stats_get(struct rte_eth_dev *dev,
 116                                 struct rte_eth_stats *rte_stats);
 117 static int eth_igb_xstats_get(struct rte_eth_dev *dev,
 118                               struct rte_eth_xstat *xstats, unsigned n);
 119 static int eth_igb_xstats_get_by_id(struct rte_eth_dev *dev,
 120                 const uint64_t *ids,
 121                 uint64_t *values, unsigned int n);
 122 static int eth_igb_xstats_get_names(struct rte_eth_dev *dev,
 123                                     struct rte_eth_xstat_name *xstats_names,
 124                                     unsigned int size);
 125 static int eth_igb_xstats_get_names_by_id(struct rte_eth_dev *dev,
 126                 struct rte_eth_xstat_name *xstats_names, const uint64_t *ids,
 127                 unsigned int limit);
 128 static void eth_igb_stats_reset(struct rte_eth_dev *dev);
 129 static void eth_igb_xstats_reset(struct rte_eth_dev *dev);
 130 static int eth_igb_fw_version_get(struct rte_eth_dev *dev,
 131                                    char *fw_version, size_t fw_size);
 132 static void eth_igb_infos_get(struct rte_eth_dev *dev,
 133                               struct rte_eth_dev_info *dev_info);
 134 static const uint32_t *eth_igb_supported_ptypes_get(struct rte_eth_dev *dev);
 135 static void eth_igbvf_infos_get(struct rte_eth_dev *dev,
 136                                 struct rte_eth_dev_info *dev_info);
 137 static int  eth_igb_flow_ctrl_get(struct rte_eth_dev *dev,
 138                                 struct rte_eth_fc_conf *fc_conf);
 139 static int  eth_igb_flow_ctrl_set(struct rte_eth_dev *dev,
 140                                 struct rte_eth_fc_conf *fc_conf);
 141 static int eth_igb_lsc_interrupt_setup(struct rte_eth_dev *dev, uint8_t on);
 142 static int eth_igb_rxq_interrupt_setup(struct rte_eth_dev *dev);
 143 static int eth_igb_interrupt_get_status(struct rte_eth_dev *dev);
 144 static int eth_igb_interrupt_action(struct rte_eth_dev *dev,
 145                                     struct rte_intr_handle *handle);
 146 static void eth_igb_interrupt_handler(void *param);
 147 static int  igb_hardware_init(struct e1000_hw *hw);
 148 static void igb_hw_control_acquire(struct e1000_hw *hw);
 149 static void igb_hw_control_release(struct e1000_hw *hw);
 150 static void igb_init_manageability(struct e1000_hw *hw);
 151 static void igb_release_manageability(struct e1000_hw *hw);
 152
 153 static int  eth_igb_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
 154
 155 static int eth_igb_vlan_filter_set(struct rte_eth_dev *dev,
 156                 uint16_t vlan_id, int on);
 157 static int eth_igb_vlan_tpid_set(struct rte_eth_dev *dev,
 158                                  enum rte_vlan_type vlan_type,
 159                                  uint16_t tpid_id);
 160 static void eth_igb_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 161
 162 static void igb_vlan_hw_filter_enable(struct rte_eth_dev *dev);
 163 static void igb_vlan_hw_filter_disable(struct rte_eth_dev *dev);
 164 static void igb_vlan_hw_strip_enable(struct rte_eth_dev *dev);
 165 static void igb_vlan_hw_strip_disable(struct rte_eth_dev *dev);
 166 static void igb_vlan_hw_extend_enable(struct rte_eth_dev *dev);
 167 static void igb_vlan_hw_extend_disable(struct rte_eth_dev *dev);
 168
 169 static int eth_igb_led_on(struct rte_eth_dev *dev);
 170 static int eth_igb_led_off(struct rte_eth_dev *dev);
 171
 172 static void igb_intr_disable(struct e1000_hw *hw);
 173 static int  igb_get_rx_buffer_size(struct e1000_hw *hw);
 174 static int eth_igb_rar_set(struct rte_eth_dev *dev,
 175                            struct ether_addr *mac_addr,
 176                            uint32_t index, uint32_t pool);
 177 static void eth_igb_rar_clear(struct rte_eth_dev *dev, uint32_t index);
 178 static void eth_igb_default_mac_addr_set(struct rte_eth_dev *dev,
 179                 struct ether_addr *addr);
 180
 181 static void igbvf_intr_disable(struct e1000_hw *hw);
 182 static int igbvf_dev_configure(struct rte_eth_dev *dev);
 183 static int igbvf_dev_start(struct rte_eth_dev *dev);
 184 static void igbvf_dev_stop(struct rte_eth_dev *dev);
 185 static void igbvf_dev_close(struct rte_eth_dev *dev);
 186 static void igbvf_promiscuous_enable(struct rte_eth_dev *dev);
 187 static void igbvf_promiscuous_disable(struct rte_eth_dev *dev);
 188 static void igbvf_allmulticast_enable(struct rte_eth_dev *dev);
 189 static void igbvf_allmulticast_disable(struct rte_eth_dev *dev);
 190 static int eth_igbvf_link_update(struct e1000_hw *hw);
 191 static void eth_igbvf_stats_get(struct rte_eth_dev *dev,
 192                                 struct rte_eth_stats *rte_stats);
 193 static int eth_igbvf_xstats_get(struct rte_eth_dev *dev,
 194                                 struct rte_eth_xstat *xstats, unsigned n);
 195 static int eth_igbvf_xstats_get_names(struct rte_eth_dev *dev,
 196                                       struct rte_eth_xstat_name *xstats_names,
 197                                       unsigned limit);
 198 static void eth_igbvf_stats_reset(struct rte_eth_dev *dev);
 199 static int igbvf_vlan_filter_set(struct rte_eth_dev *dev,
 200                 uint16_t vlan_id, int on);
 201 static int igbvf_set_vfta(struct e1000_hw *hw, uint16_t vid, bool on);
 202 static void igbvf_set_vfta_all(struct rte_eth_dev *dev, bool on);
 203 static void igbvf_default_mac_addr_set(struct rte_eth_dev *dev,
 204                 struct ether_addr *addr);
 205 static int igbvf_get_reg_length(struct rte_eth_dev *dev);
 206 static int igbvf_get_regs(struct rte_eth_dev *dev,
 207                 struct rte_dev_reg_info *regs);
 208
 209 static int eth_igb_rss_reta_update(struct rte_eth_dev *dev,
 210                                    struct rte_eth_rss_reta_entry64 *reta_conf,
 211                                    uint16_t reta_size);
 212 static int eth_igb_rss_reta_query(struct rte_eth_dev *dev,
 213                                   struct rte_eth_rss_reta_entry64 *reta_conf,
 214                                   uint16_t reta_size);
 215
 216 static int eth_igb_syn_filter_set(struct rte_eth_dev *dev,
 217                         struct rte_eth_syn_filter *filter,
 218                         bool add);
 219 static int eth_igb_syn_filter_get(struct rte_eth_dev *dev,
 220                         struct rte_eth_syn_filter *filter);
 221 static int eth_igb_syn_filter_handle(struct rte_eth_dev *dev,
 222                         enum rte_filter_op filter_op,
 223                         void *arg);
 224 static int igb_add_2tuple_filter(struct rte_eth_dev *dev,
 225                         struct rte_eth_ntuple_filter *ntuple_filter);
 226 static int igb_remove_2tuple_filter(struct rte_eth_dev *dev,
 227                         struct rte_eth_ntuple_filter *ntuple_filter);
 228 static int eth_igb_add_del_flex_filter(struct rte_eth_dev *dev,
 229                         struct rte_eth_flex_filter *filter,
 230                         bool add);
 231 static int eth_igb_get_flex_filter(struct rte_eth_dev *dev,
 232                         struct rte_eth_flex_filter *filter);
 233 static int eth_igb_flex_filter_handle(struct rte_eth_dev *dev,
 234                         enum rte_filter_op filter_op,
 235                         void *arg);
 236 static int igb_add_5tuple_filter_82576(struct rte_eth_dev *dev,
 237                         struct rte_eth_ntuple_filter *ntuple_filter);
 238 static int igb_remove_5tuple_filter_82576(struct rte_eth_dev *dev,
 239                         struct rte_eth_ntuple_filter *ntuple_filter);
 240 static int igb_add_del_ntuple_filter(struct rte_eth_dev *dev,
 241                         struct rte_eth_ntuple_filter *filter,
 242                         bool add);
 243 static int igb_get_ntuple_filter(struct rte_eth_dev *dev,
 244                         struct rte_eth_ntuple_filter *filter);
 245 static int igb_ntuple_filter_handle(struct rte_eth_dev *dev,
 246                                 enum rte_filter_op filter_op,
 247                                 void *arg);
 248 static int igb_add_del_ethertype_filter(struct rte_eth_dev *dev,
 249                         struct rte_eth_ethertype_filter *filter,
 250                         bool add);
 251 static int igb_ethertype_filter_handle(struct rte_eth_dev *dev,
 252                                 enum rte_filter_op filter_op,
 253                                 void *arg);
 254 static int igb_get_ethertype_filter(struct rte_eth_dev *dev,
 255                         struct rte_eth_ethertype_filter *filter);
 256 static int eth_igb_filter_ctrl(struct rte_eth_dev *dev,
 257                      enum rte_filter_type filter_type,
 258                      enum rte_filter_op filter_op,
 259                      void *arg);
 260 static int eth_igb_get_reg_length(struct rte_eth_dev *dev);
 261 static int eth_igb_get_regs(struct rte_eth_dev *dev,
 262                 struct rte_dev_reg_info *regs);
 263 static int eth_igb_get_eeprom_length(struct rte_eth_dev *dev);
 264 static int eth_igb_get_eeprom(struct rte_eth_dev *dev,
 265                 struct rte_dev_eeprom_info *eeprom);
 266 static int eth_igb_set_eeprom(struct rte_eth_dev *dev,
 267                 struct rte_dev_eeprom_info *eeprom);
 268 static int eth_igb_set_mc_addr_list(struct rte_eth_dev *dev,
 269                                     struct ether_addr *mc_addr_set,
 270                                     uint32_t nb_mc_addr);
 271 static int igb_timesync_enable(struct rte_eth_dev *dev);
 272 static int igb_timesync_disable(struct rte_eth_dev *dev);
 273 static int igb_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
 274                                           struct timespec *timestamp,
 275                                           uint32_t flags);
 276 static int igb_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
 277                                           struct timespec *timestamp);
 278 static int igb_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);
 279 static int igb_timesync_read_time(struct rte_eth_dev *dev,
 280                                   struct timespec *timestamp);
 281 static int igb_timesync_write_time(struct rte_eth_dev *dev,
 282                                    const struct timespec *timestamp);
 283 static int eth_igb_rx_queue_intr_enable(struct rte_eth_dev *dev,
 284                                         uint16_t queue_id);
 285 static int eth_igb_rx_queue_intr_disable(struct rte_eth_dev *dev,
 286                                          uint16_t queue_id);
 287 static void eth_igb_assign_msix_vector(struct e1000_hw *hw, int8_t direction,
 288                                        uint8_t queue, uint8_t msix_vector);
 289 static void eth_igb_write_ivar(struct e1000_hw *hw, uint8_t msix_vector,
 290                                uint8_t index, uint8_t offset);
 291 static void eth_igb_configure_msix_intr(struct rte_eth_dev *dev);
 292 static void eth_igbvf_interrupt_handler(void *param);
 293 static void igbvf_mbx_process(struct rte_eth_dev *dev);
 294
 295 /*
 296  * Define VF Stats MACRO for Non "cleared on read" register
 297  */
 298 #define UPDATE_VF_STAT(reg, last, cur)            \
 299 {                                                 \
 300         u32 latest = E1000_READ_REG(hw, reg);     \
 301         cur += (latest - last) & UINT_MAX;        \
 302         last = latest;                            \
 303 }
 304
 305 #define IGB_FC_PAUSE_TIME 0x0680
 306 #define IGB_LINK_UPDATE_CHECK_TIMEOUT  90  /* 9s */
 307 #define IGB_LINK_UPDATE_CHECK_INTERVAL 100 /* ms */
 308
 309 #define IGBVF_PMD_NAME "rte_igbvf_pmd"     /* PMD name */
 310
 311 static enum e1000_fc_mode igb_fc_setting = e1000_fc_full;
 312
 313 /*
 314  * The set of PCI devices this driver supports
 315  */
 316 static const struct rte_pci_id pci_id_igb_map[] = {
 317         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576) },
 318         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_FIBER) },
 319         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_SERDES) },
 320         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_QUAD_COPPER) },
 321         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_QUAD_COPPER_ET2) },
 322         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_NS) },
 323         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_NS_SERDES) },
 324         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_SERDES_QUAD) },
 325
 326         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82575EB_COPPER) },
 327         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82575EB_FIBER_SERDES) },
 328         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82575GB_QUAD_COPPER) },
 329
 330         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82580_COPPER) },
 331         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82580_FIBER) },
 332         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82580_SERDES) },
 333         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82580_SGMII) },
 334         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82580_COPPER_DUAL) },
 335         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82580_QUAD_FIBER) },
 336
 337         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_COPPER) },
 338         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_FIBER) },
 339         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_SERDES) },
 340         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_SGMII) },
 341         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_DA4) },
 342         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_COPPER) },
 343         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_COPPER_OEM1) },
 344         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_COPPER_IT) },
 345         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_FIBER) },
 346         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_SERDES) },
 347         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_SGMII) },
 348         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I211_COPPER) },
 349         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I354_BACKPLANE_1GBPS) },
 350         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I354_SGMII) },
 351         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I354_BACKPLANE_2_5GBPS) },
 352         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_DH89XXCC_SGMII) },
 353         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_DH89XXCC_SERDES) },
 354         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_DH89XXCC_BACKPLANE) },
 355         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_DH89XXCC_SFP) },
 356         { .vendor_id = 0, /* sentinel */ },
 357 };
 358
 359 /*
 360  * The set of PCI devices this driver supports (for 82576&I350 VF)
 361  */
 362 static const struct rte_pci_id pci_id_igbvf_map[] = {
 363         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_VF) },
 364         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_VF_HV) },
 365         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_VF) },
 366         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_VF_HV) },
 367         { .vendor_id = 0, /* sentinel */ },
 368 };
 369
 370 static const struct rte_eth_desc_lim rx_desc_lim = {
 371         .nb_max = E1000_MAX_RING_DESC,
 372         .nb_min = E1000_MIN_RING_DESC,
 373         .nb_align = IGB_RXD_ALIGN,
 374 };
 375
 376 static const struct rte_eth_desc_lim tx_desc_lim = {
 377         .nb_max = E1000_MAX_RING_DESC,
 378         .nb_min = E1000_MIN_RING_DESC,
 379         .nb_align = IGB_RXD_ALIGN,
 380         .nb_seg_max = IGB_TX_MAX_SEG,
 381         .nb_mtu_seg_max = IGB_TX_MAX_MTU_SEG,
 382 };
 383
 384 static const struct eth_dev_ops eth_igb_ops = {
 385         .dev_configure        = eth_igb_configure,
 386         .dev_start            = eth_igb_start,
 387         .dev_stop             = eth_igb_stop,
 388         .dev_set_link_up      = eth_igb_dev_set_link_up,
 389         .dev_set_link_down    = eth_igb_dev_set_link_down,
 390         .dev_close            = eth_igb_close,
 391         .promiscuous_enable   = eth_igb_promiscuous_enable,
 392         .promiscuous_disable  = eth_igb_promiscuous_disable,
 393         .allmulticast_enable  = eth_igb_allmulticast_enable,
 394         .allmulticast_disable = eth_igb_allmulticast_disable,
 395         .link_update          = eth_igb_link_update,
 396         .stats_get            = eth_igb_stats_get,
 397         .xstats_get           = eth_igb_xstats_get,
 398         .xstats_get_by_id     = eth_igb_xstats_get_by_id,
 399         .xstats_get_names_by_id = eth_igb_xstats_get_names_by_id,
 400         .xstats_get_names     = eth_igb_xstats_get_names,
 401         .stats_reset          = eth_igb_stats_reset,
 402         .xstats_reset         = eth_igb_xstats_reset,
 403         .fw_version_get       = eth_igb_fw_version_get,
 404         .dev_infos_get        = eth_igb_infos_get,
 405         .dev_supported_ptypes_get = eth_igb_supported_ptypes_get,
 406         .mtu_set              = eth_igb_mtu_set,
 407         .vlan_filter_set      = eth_igb_vlan_filter_set,
 408         .vlan_tpid_set        = eth_igb_vlan_tpid_set,
 409         .vlan_offload_set     = eth_igb_vlan_offload_set,
 410         .rx_queue_setup       = eth_igb_rx_queue_setup,
 411         .rx_queue_intr_enable = eth_igb_rx_queue_intr_enable,
 412         .rx_queue_intr_disable = eth_igb_rx_queue_intr_disable,
 413         .rx_queue_release     = eth_igb_rx_queue_release,
 414         .rx_queue_count       = eth_igb_rx_queue_count,
 415         .rx_descriptor_done   = eth_igb_rx_descriptor_done,
 416         .rx_descriptor_status = eth_igb_rx_descriptor_status,
 417         .tx_descriptor_status = eth_igb_tx_descriptor_status,
 418         .tx_queue_setup       = eth_igb_tx_queue_setup,
 419         .tx_queue_release     = eth_igb_tx_queue_release,
 420         .tx_done_cleanup      = eth_igb_tx_done_cleanup,
 421         .dev_led_on           = eth_igb_led_on,
 422         .dev_led_off          = eth_igb_led_off,
 423         .flow_ctrl_get        = eth_igb_flow_ctrl_get,
 424         .flow_ctrl_set        = eth_igb_flow_ctrl_set,
 425         .mac_addr_add         = eth_igb_rar_set,
 426         .mac_addr_remove      = eth_igb_rar_clear,
 427         .mac_addr_set         = eth_igb_default_mac_addr_set,
 428         .reta_update          = eth_igb_rss_reta_update,
 429         .reta_query           = eth_igb_rss_reta_query,
 430         .rss_hash_update      = eth_igb_rss_hash_update,
 431         .rss_hash_conf_get    = eth_igb_rss_hash_conf_get,
 432         .filter_ctrl          = eth_igb_filter_ctrl,
 433         .set_mc_addr_list     = eth_igb_set_mc_addr_list,
 434         .rxq_info_get         = igb_rxq_info_get,
 435         .txq_info_get         = igb_txq_info_get,
 436         .timesync_enable      = igb_timesync_enable,
 437         .timesync_disable     = igb_timesync_disable,
 438         .timesync_read_rx_timestamp = igb_timesync_read_rx_timestamp,
 439         .timesync_read_tx_timestamp = igb_timesync_read_tx_timestamp,
 440         .get_reg              = eth_igb_get_regs,
 441         .get_eeprom_length    = eth_igb_get_eeprom_length,
 442         .get_eeprom           = eth_igb_get_eeprom,
 443         .set_eeprom           = eth_igb_set_eeprom,
 444         .timesync_adjust_time = igb_timesync_adjust_time,
 445         .timesync_read_time   = igb_timesync_read_time,
 446         .timesync_write_time  = igb_timesync_write_time,
 447 };
 448
 449 /*
 450  * dev_ops for virtual function, bare necessities for basic vf
 451  * operation have been implemented
 452  */
 453 static const struct eth_dev_ops igbvf_eth_dev_ops = {
 454         .dev_configure        = igbvf_dev_configure,
 455         .dev_start            = igbvf_dev_start,
 456         .dev_stop             = igbvf_dev_stop,
 457         .dev_close            = igbvf_dev_close,
 458         .promiscuous_enable   = igbvf_promiscuous_enable,
 459         .promiscuous_disable  = igbvf_promiscuous_disable,
 460         .allmulticast_enable  = igbvf_allmulticast_enable,
 461         .allmulticast_disable = igbvf_allmulticast_disable,
 462         .link_update          = eth_igb_link_update,
 463         .stats_get            = eth_igbvf_stats_get,
 464         .xstats_get           = eth_igbvf_xstats_get,
 465         .xstats_get_names     = eth_igbvf_xstats_get_names,
 466         .stats_reset          = eth_igbvf_stats_reset,
 467         .xstats_reset         = eth_igbvf_stats_reset,
 468         .vlan_filter_set      = igbvf_vlan_filter_set,
 469         .dev_infos_get        = eth_igbvf_infos_get,
 470         .dev_supported_ptypes_get = eth_igb_supported_ptypes_get,
 471         .rx_queue_setup       = eth_igb_rx_queue_setup,
 472         .rx_queue_release     = eth_igb_rx_queue_release,
 473         .tx_queue_setup       = eth_igb_tx_queue_setup,
 474         .tx_queue_release     = eth_igb_tx_queue_release,
 475         .set_mc_addr_list     = eth_igb_set_mc_addr_list,
 476         .rxq_info_get         = igb_rxq_info_get,
 477         .txq_info_get         = igb_txq_info_get,
 478         .mac_addr_set         = igbvf_default_mac_addr_set,
 479         .get_reg              = igbvf_get_regs,
 480 };
 481
 482 /* store statistics names and its offset in stats structure */
 483 struct rte_igb_xstats_name_off {
 484         char name[RTE_ETH_XSTATS_NAME_SIZE];
 485         unsigned offset;
 486 };
 487
 488 static const struct rte_igb_xstats_name_off rte_igb_stats_strings[] = {
 489         {"rx_crc_errors", offsetof(struct e1000_hw_stats, crcerrs)},
 490         {"rx_align_errors", offsetof(struct e1000_hw_stats, algnerrc)},
 491         {"rx_symbol_errors", offsetof(struct e1000_hw_stats, symerrs)},
 492         {"rx_missed_packets", offsetof(struct e1000_hw_stats, mpc)},
 493         {"tx_single_collision_packets", offsetof(struct e1000_hw_stats, scc)},
 494         {"tx_multiple_collision_packets", offsetof(struct e1000_hw_stats, mcc)},
 495         {"tx_excessive_collision_packets", offsetof(struct e1000_hw_stats,
 496                 ecol)},
 497         {"tx_late_collisions", offsetof(struct e1000_hw_stats, latecol)},
 498         {"tx_total_collisions", offsetof(struct e1000_hw_stats, colc)},
 499         {"tx_deferred_packets", offsetof(struct e1000_hw_stats, dc)},
 500         {"tx_no_carrier_sense_packets", offsetof(struct e1000_hw_stats, tncrs)},
 501         {"rx_carrier_ext_errors", offsetof(struct e1000_hw_stats, cexterr)},
 502         {"rx_length_errors", offsetof(struct e1000_hw_stats, rlec)},
 503         {"rx_xon_packets", offsetof(struct e1000_hw_stats, xonrxc)},
 504         {"tx_xon_packets", offsetof(struct e1000_hw_stats, xontxc)},
 505         {"rx_xoff_packets", offsetof(struct e1000_hw_stats, xoffrxc)},
 506         {"tx_xoff_packets", offsetof(struct e1000_hw_stats, xofftxc)},
 507         {"rx_flow_control_unsupported_packets", offsetof(struct e1000_hw_stats,
 508                 fcruc)},
 509         {"rx_size_64_packets", offsetof(struct e1000_hw_stats, prc64)},
 510         {"rx_size_65_to_127_packets", offsetof(struct e1000_hw_stats, prc127)},
 511         {"rx_size_128_to_255_packets", offsetof(struct e1000_hw_stats, prc255)},
 512         {"rx_size_256_to_511_packets", offsetof(struct e1000_hw_stats, prc511)},
 513         {"rx_size_512_to_1023_packets", offsetof(struct e1000_hw_stats,
 514                 prc1023)},
 515         {"rx_size_1024_to_max_packets", offsetof(struct e1000_hw_stats,
 516                 prc1522)},
 517         {"rx_broadcast_packets", offsetof(struct e1000_hw_stats, bprc)},
 518         {"rx_multicast_packets", offsetof(struct e1000_hw_stats, mprc)},
 519         {"rx_undersize_errors", offsetof(struct e1000_hw_stats, ruc)},
 520         {"rx_fragment_errors", offsetof(struct e1000_hw_stats, rfc)},
 521         {"rx_oversize_errors", offsetof(struct e1000_hw_stats, roc)},
 522         {"rx_jabber_errors", offsetof(struct e1000_hw_stats, rjc)},
 523         {"rx_management_packets", offsetof(struct e1000_hw_stats, mgprc)},
 524         {"rx_management_dropped", offsetof(struct e1000_hw_stats, mgpdc)},
 525         {"tx_management_packets", offsetof(struct e1000_hw_stats, mgptc)},
 526         {"rx_total_packets", offsetof(struct e1000_hw_stats, tpr)},
 527         {"tx_total_packets", offsetof(struct e1000_hw_stats, tpt)},
 528         {"rx_total_bytes", offsetof(struct e1000_hw_stats, tor)},
 529         {"tx_total_bytes", offsetof(struct e1000_hw_stats, tot)},
 530         {"tx_size_64_packets", offsetof(struct e1000_hw_stats, ptc64)},
 531         {"tx_size_65_to_127_packets", offsetof(struct e1000_hw_stats, ptc127)},
 532         {"tx_size_128_to_255_packets", offsetof(struct e1000_hw_stats, ptc255)},
 533         {"tx_size_256_to_511_packets", offsetof(struct e1000_hw_stats, ptc511)},
 534         {"tx_size_512_to_1023_packets", offsetof(struct e1000_hw_stats,
 535                 ptc1023)},
 536         {"tx_size_1023_to_max_packets", offsetof(struct e1000_hw_stats,
 537                 ptc1522)},
 538         {"tx_multicast_packets", offsetof(struct e1000_hw_stats, mptc)},
 539         {"tx_broadcast_packets", offsetof(struct e1000_hw_stats, bptc)},
 540         {"tx_tso_packets", offsetof(struct e1000_hw_stats, tsctc)},
 541         {"tx_tso_errors", offsetof(struct e1000_hw_stats, tsctfc)},
 542         {"rx_sent_to_host_packets", offsetof(struct e1000_hw_stats, rpthc)},
 543         {"tx_sent_by_host_packets", offsetof(struct e1000_hw_stats, hgptc)},
 544         {"rx_code_violation_packets", offsetof(struct e1000_hw_stats, scvpc)},
 545
 546         {"interrupt_assert_count", offsetof(struct e1000_hw_stats, iac)},
 547 };
 548
 549 #define IGB_NB_XSTATS (sizeof(rte_igb_stats_strings) / \
 550                 sizeof(rte_igb_stats_strings[0]))
 551
 552 static const struct rte_igb_xstats_name_off rte_igbvf_stats_strings[] = {
 553         {"rx_multicast_packets", offsetof(struct e1000_vf_stats, mprc)},
 554         {"rx_good_loopback_packets", offsetof(struct e1000_vf_stats, gprlbc)},
 555         {"tx_good_loopback_packets", offsetof(struct e1000_vf_stats, gptlbc)},
 556         {"rx_good_loopback_bytes", offsetof(struct e1000_vf_stats, gorlbc)},
 557         {"tx_good_loopback_bytes", offsetof(struct e1000_vf_stats, gotlbc)},
 558 };
 559
 560 #define IGBVF_NB_XSTATS (sizeof(rte_igbvf_stats_strings) / \
 561                 sizeof(rte_igbvf_stats_strings[0]))
 562
 563 /**
 564  * Atomically reads the link status information from global
 565  * structure rte_eth_dev.
 566  *
 567  * @param dev
 568  *   - Pointer to the structure rte_eth_dev to read from.
 569  *   - Pointer to the buffer to be saved with the link status.
 570  *
 571  * @return
 572  *   - On success, zero.
 573  *   - On failure, negative value.
 574  */
 575 static inline int
 576 rte_igb_dev_atomic_read_link_status(struct rte_eth_dev *dev,
 577                                 struct rte_eth_link *link)
 578 {
 579         struct rte_eth_link *dst = link;
 580         struct rte_eth_link *src = &(dev->data->dev_link);
 581
 582         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 583                                         *(uint64_t *)src) == 0)
 584                 return -1;
 585
 586         return 0;
 587 }
 588
 589 /**
 590  * Atomically writes the link status information into global
 591  * structure rte_eth_dev.
 592  *
 593  * @param dev
 594  *   - Pointer to the structure rte_eth_dev to read from.
 595  *   - Pointer to the buffer to be saved with the link status.
 596  *
 597  * @return
 598  *   - On success, zero.
 599  *   - On failure, negative value.
 600  */
 601 static inline int
 602 rte_igb_dev_atomic_write_link_status(struct rte_eth_dev *dev,
 603                                 struct rte_eth_link *link)
 604 {
 605         struct rte_eth_link *dst = &(dev->data->dev_link);
 606         struct rte_eth_link *src = link;
 607
 608         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 609                                         *(uint64_t *)src) == 0)
 610                 return -1;
 611
 612         return 0;
 613 }
 614
 615 static inline void
 616 igb_intr_enable(struct rte_eth_dev *dev)
 617 {
 618         struct e1000_interrupt *intr =
 619                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
 620         struct e1000_hw *hw =
 621                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 622
 623         E1000_WRITE_REG(hw, E1000_IMS, intr->mask);
 624         E1000_WRITE_FLUSH(hw);
 625 }
 626
 627 static void
 628 igb_intr_disable(struct e1000_hw *hw)
 629 {
 630         E1000_WRITE_REG(hw, E1000_IMC, ~0);
 631         E1000_WRITE_FLUSH(hw);
 632 }
 633
 634 static inline void
 635 igbvf_intr_enable(struct rte_eth_dev *dev)
 636 {
 637         struct e1000_hw *hw =
 638                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 639
 640         /* only for mailbox */
 641         E1000_WRITE_REG(hw, E1000_EIAM, 1 << E1000_VTIVAR_MISC_MAILBOX);
 642         E1000_WRITE_REG(hw, E1000_EIAC, 1 << E1000_VTIVAR_MISC_MAILBOX);
 643         E1000_WRITE_REG(hw, E1000_EIMS, 1 << E1000_VTIVAR_MISC_MAILBOX);
 644         E1000_WRITE_FLUSH(hw);
 645 }
 646
 647 /* only for mailbox now. If RX/TX needed, should extend this function.  */
 648 static void
 649 igbvf_set_ivar_map(struct e1000_hw *hw, uint8_t msix_vector)
 650 {
 651         uint32_t tmp = 0;
 652
 653         /* mailbox */
 654         tmp |= (msix_vector & E1000_VTIVAR_MISC_INTR_MASK);
 655         tmp |= E1000_VTIVAR_VALID;
 656         E1000_WRITE_REG(hw, E1000_VTIVAR_MISC, tmp);
 657 }
 658
 659 static void
 660 eth_igbvf_configure_msix_intr(struct rte_eth_dev *dev)
 661 {
 662         struct e1000_hw *hw =
 663                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 664
 665         /* Configure VF other cause ivar */
 666         igbvf_set_ivar_map(hw, E1000_VTIVAR_MISC_MAILBOX);
 667 }
 668
 669 static inline int32_t
 670 igb_pf_reset_hw(struct e1000_hw *hw)
 671 {
 672         uint32_t ctrl_ext;
 673         int32_t status;
 674
 675         status = e1000_reset_hw(hw);
 676
 677         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
 678         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
 679         ctrl_ext |= E1000_CTRL_EXT_PFRSTD;
 680         E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
 681         E1000_WRITE_FLUSH(hw);
 682
 683         return status;
 684 }
 685
 686 static void
 687 igb_identify_hardware(struct rte_eth_dev *dev, struct rte_pci_device *pci_dev)
 688 {
 689         struct e1000_hw *hw =
 690                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 691
 692
 693         hw->vendor_id = pci_dev->id.vendor_id;
 694         hw->device_id = pci_dev->id.device_id;
 695         hw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
 696         hw->subsystem_device_id = pci_dev->id.subsystem_device_id;
 697
 698         e1000_set_mac_type(hw);
 699
 700         /* need to check if it is a vf device below */
 701 }
 702
 703 static int
 704 igb_reset_swfw_lock(struct e1000_hw *hw)
 705 {
 706         int ret_val;
 707
 708         /*
 709          * Do mac ops initialization manually here, since we will need
 710          * some function pointers set by this call.
 711          */
 712         ret_val = e1000_init_mac_params(hw);
 713         if (ret_val)
 714                 return ret_val;
 715
 716         /*
 717          * SMBI lock should not fail in this early stage. If this is the case,
 718          * it is due to an improper exit of the application.
 719          * So force the release of the faulty lock.
 720          */
 721         if (e1000_get_hw_semaphore_generic(hw) < 0) {
 722                 PMD_DRV_LOG(DEBUG, "SMBI lock released");
 723         }
 724         e1000_put_hw_semaphore_generic(hw);
 725
 726         if (hw->mac.ops.acquire_swfw_sync != NULL) {
 727                 uint16_t mask;
 728
 729                 /*
 730                  * Phy lock should not fail in this early stage. If this is the case,
 731                  * it is due to an improper exit of the application.
 732                  * So force the release of the faulty lock.
 733                  */
 734                 mask = E1000_SWFW_PHY0_SM << hw->bus.func;
 735                 if (hw->bus.func > E1000_FUNC_1)
 736                         mask <<= 2;
 737                 if (hw->mac.ops.acquire_swfw_sync(hw, mask) < 0) {
 738                         PMD_DRV_LOG(DEBUG, "SWFW phy%d lock released",
 739                                     hw->bus.func);
 740                 }
 741                 hw->mac.ops.release_swfw_sync(hw, mask);
 742
 743                 /*
 744                  * This one is more tricky since it is common to all ports; but
 745                  * swfw_sync retries last long enough (1s) to be almost sure that if
 746                  * lock can not be taken it is due to an improper lock of the
 747                  * semaphore.
 748                  */
 749                 mask = E1000_SWFW_EEP_SM;
 750                 if (hw->mac.ops.acquire_swfw_sync(hw, mask) < 0) {
 751                         PMD_DRV_LOG(DEBUG, "SWFW common locks released");
 752                 }
 753                 hw->mac.ops.release_swfw_sync(hw, mask);
 754         }
 755
 756         return E1000_SUCCESS;
 757 }
 758
 759 static int
 760 eth_igb_dev_init(struct rte_eth_dev *eth_dev)
 761 {
 762         int error = 0;
 763         struct rte_pci_device *pci_dev = E1000_DEV_TO_PCI(eth_dev);
 764         struct e1000_hw *hw =
 765                 E1000_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 766         struct e1000_vfta * shadow_vfta =
 767                 E1000_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
 768         struct e1000_filter_info *filter_info =
 769                 E1000_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
 770         struct e1000_adapter *adapter =
 771                 E1000_DEV_PRIVATE(eth_dev->data->dev_private);
 772
 773         uint32_t ctrl_ext;
 774
 775         eth_dev->dev_ops = &eth_igb_ops;
 776         eth_dev->rx_pkt_burst = &eth_igb_recv_pkts;
 777         eth_dev->tx_pkt_burst = &eth_igb_xmit_pkts;
 778         eth_dev->tx_pkt_prepare = &eth_igb_prep_pkts;
 779
 780         /* for secondary processes, we don't initialise any further as primary
 781          * has already done this work. Only check we don't need a different
 782          * RX function */
 783         if (rte_eal_process_type() != RTE_PROC_PRIMARY){
 784                 if (eth_dev->data->scattered_rx)
 785                         eth_dev->rx_pkt_burst = &eth_igb_recv_scattered_pkts;
 786                 return 0;
 787         }
 788
 789         rte_eth_copy_pci_info(eth_dev, pci_dev);
 790         eth_dev->data->dev_flags |= RTE_ETH_DEV_DETACHABLE;
 791
 792         hw->hw_addr= (void *)pci_dev->mem_resource[0].addr;
 793
 794         igb_identify_hardware(eth_dev, pci_dev);
 795         if (e1000_setup_init_funcs(hw, FALSE) != E1000_SUCCESS) {
 796                 error = -EIO;
 797                 goto err_late;
 798         }
 799
 800         e1000_get_bus_info(hw);
 801
 802         /* Reset any pending lock */
 803         if (igb_reset_swfw_lock(hw) != E1000_SUCCESS) {
 804                 error = -EIO;
 805                 goto err_late;
 806         }
 807
 808         /* Finish initialization */
 809         if (e1000_setup_init_funcs(hw, TRUE) != E1000_SUCCESS) {
 810                 error = -EIO;
 811                 goto err_late;
 812         }
 813
 814         hw->mac.autoneg = 1;
 815         hw->phy.autoneg_wait_to_complete = 0;
 816         hw->phy.autoneg_advertised = E1000_ALL_SPEED_DUPLEX;
 817
 818         /* Copper options */
 819         if (hw->phy.media_type == e1000_media_type_copper) {
 820                 hw->phy.mdix = 0; /* AUTO_ALL_MODES */
 821                 hw->phy.disable_polarity_correction = 0;
 822                 hw->phy.ms_type = e1000_ms_hw_default;
 823         }
 824
 825         /*
 826          * Start from a known state, this is important in reading the nvm
 827          * and mac from that.
 828          */
 829         igb_pf_reset_hw(hw);
 830
 831         /* Make sure we have a good EEPROM before we read from it */
 832         if (e1000_validate_nvm_checksum(hw) < 0) {
 833                 /*
 834                  * Some PCI-E parts fail the first check due to
 835                  * the link being in sleep state, call it again,
 836                  * if it fails a second time its a real issue.
 837                  */
 838                 if (e1000_validate_nvm_checksum(hw) < 0) {
 839                         PMD_INIT_LOG(ERR, "EEPROM checksum invalid");
 840                         error = -EIO;
 841                         goto err_late;
 842                 }
 843         }
 844
 845         /* Read the permanent MAC address out of the EEPROM */
 846         if (e1000_read_mac_addr(hw) != 0) {
 847                 PMD_INIT_LOG(ERR, "EEPROM error while reading MAC address");
 848                 error = -EIO;
 849                 goto err_late;
 850         }
 851
 852         /* Allocate memory for storing MAC addresses */
 853         eth_dev->data->mac_addrs = rte_zmalloc("e1000",
 854                 ETHER_ADDR_LEN * hw->mac.rar_entry_count, 0);
 855         if (eth_dev->data->mac_addrs == NULL) {
 856                 PMD_INIT_LOG(ERR, "Failed to allocate %d bytes needed to "
 857                                                 "store MAC addresses",
 858                                 ETHER_ADDR_LEN * hw->mac.rar_entry_count);
 859                 error = -ENOMEM;
 860                 goto err_late;
 861         }
 862
 863         /* Copy the permanent MAC address */
 864         ether_addr_copy((struct ether_addr *)hw->mac.addr, &eth_dev->data->mac_addrs[0]);
 865
 866         /* initialize the vfta */
 867         memset(shadow_vfta, 0, sizeof(*shadow_vfta));
 868
 869         /* Now initialize the hardware */
 870         if (igb_hardware_init(hw) != 0) {
 871                 PMD_INIT_LOG(ERR, "Hardware initialization failed");
 872                 rte_free(eth_dev->data->mac_addrs);
 873                 eth_dev->data->mac_addrs = NULL;
 874                 error = -ENODEV;
 875                 goto err_late;
 876         }
 877         hw->mac.get_link_status = 1;
 878         adapter->stopped = 0;
 879
 880         /* Indicate SOL/IDER usage */
 881         if (e1000_check_reset_block(hw) < 0) {
 882                 PMD_INIT_LOG(ERR, "PHY reset is blocked due to"
 883                                         "SOL/IDER session");
 884         }
 885
 886         /* initialize PF if max_vfs not zero */
 887         igb_pf_host_init(eth_dev);
 888
 889         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
 890         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
 891         ctrl_ext |= E1000_CTRL_EXT_PFRSTD;
 892         E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
 893         E1000_WRITE_FLUSH(hw);
 894
 895         PMD_INIT_LOG(DEBUG, "port_id %d vendorID=0x%x deviceID=0x%x",
 896                      eth_dev->data->port_id, pci_dev->id.vendor_id,
 897                      pci_dev->id.device_id);
 898
 899         rte_intr_callback_register(&pci_dev->intr_handle,
 900                                    eth_igb_interrupt_handler,
 901                                    (void *)eth_dev);
 902
 903         /* enable uio/vfio intr/eventfd mapping */
 904         rte_intr_enable(&pci_dev->intr_handle);
 905
 906         /* enable support intr */
 907         igb_intr_enable(eth_dev);
 908
 909         TAILQ_INIT(&filter_info->flex_list);
 910         filter_info->flex_mask = 0;
 911         TAILQ_INIT(&filter_info->twotuple_list);
 912         filter_info->twotuple_mask = 0;
 913         TAILQ_INIT(&filter_info->fivetuple_list);
 914         filter_info->fivetuple_mask = 0;
 915
 916         return 0;
 917
 918 err_late:
 919         igb_hw_control_release(hw);
 920
 921         return error;
 922 }
 923
 924 static int
 925 eth_igb_dev_uninit(struct rte_eth_dev *eth_dev)
 926 {
 927         struct rte_pci_device *pci_dev;
 928         struct rte_intr_handle *intr_handle;
 929         struct e1000_hw *hw;
 930         struct e1000_adapter *adapter =
 931                 E1000_DEV_PRIVATE(eth_dev->data->dev_private);
 932
 933         PMD_INIT_FUNC_TRACE();
 934
 935         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
 936                 return -EPERM;
 937
 938         hw = E1000_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 939         pci_dev = E1000_DEV_TO_PCI(eth_dev);
 940         intr_handle = &pci_dev->intr_handle;
 941
 942         if (adapter->stopped == 0)
 943                 eth_igb_close(eth_dev);
 944
 945         eth_dev->dev_ops = NULL;
 946         eth_dev->rx_pkt_burst = NULL;
 947         eth_dev->tx_pkt_burst = NULL;
 948
 949         /* Reset any pending lock */
 950         igb_reset_swfw_lock(hw);
 951
 952         rte_free(eth_dev->data->mac_addrs);
 953         eth_dev->data->mac_addrs = NULL;
 954
 955         /* uninitialize PF if max_vfs not zero */
 956         igb_pf_host_uninit(eth_dev);
 957
 958         /* disable uio intr before callback unregister */
 959         rte_intr_disable(intr_handle);
 960         rte_intr_callback_unregister(intr_handle,
 961                                      eth_igb_interrupt_handler, eth_dev);
 962
 963         return 0;
 964 }
 965
 966 /*
 967  * Virtual Function device init
 968  */
 969 static int
 970 eth_igbvf_dev_init(struct rte_eth_dev *eth_dev)
 971 {
 972         struct rte_pci_device *pci_dev;
 973         struct rte_intr_handle *intr_handle;
 974         struct e1000_adapter *adapter =
 975                 E1000_DEV_PRIVATE(eth_dev->data->dev_private);
 976         struct e1000_hw *hw =
 977                 E1000_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 978         int diag;
 979         struct ether_addr *perm_addr = (struct ether_addr *)hw->mac.perm_addr;
 980
 981         PMD_INIT_FUNC_TRACE();
 982
 983         eth_dev->dev_ops = &igbvf_eth_dev_ops;
 984         eth_dev->rx_pkt_burst = &eth_igb_recv_pkts;
 985         eth_dev->tx_pkt_burst = &eth_igb_xmit_pkts;
 986         eth_dev->tx_pkt_prepare = &eth_igb_prep_pkts;
 987
 988         /* for secondary processes, we don't initialise any further as primary
 989          * has already done this work. Only check we don't need a different
 990          * RX function */
 991         if (rte_eal_process_type() != RTE_PROC_PRIMARY){
 992                 if (eth_dev->data->scattered_rx)
 993                         eth_dev->rx_pkt_burst = &eth_igb_recv_scattered_pkts;
 994                 return 0;
 995         }
 996
 997         pci_dev = E1000_DEV_TO_PCI(eth_dev);
 998         rte_eth_copy_pci_info(eth_dev, pci_dev);
 999         eth_dev->data->dev_flags |= RTE_ETH_DEV_DETACHABLE;
1000
1001         hw->device_id = pci_dev->id.device_id;
1002         hw->vendor_id = pci_dev->id.vendor_id;
1003         hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
1004         adapter->stopped = 0;
1005
1006         /* Initialize the shared code (base driver) */
1007         diag = e1000_setup_init_funcs(hw, TRUE);
1008         if (diag != 0) {
1009                 PMD_INIT_LOG(ERR, "Shared code init failed for igbvf: %d",
1010                         diag);
1011                 return -EIO;
1012         }
1013
1014         /* init_mailbox_params */
1015         hw->mbx.ops.init_params(hw);
1016
1017         /* Disable the interrupts for VF */
1018         igbvf_intr_disable(hw);
1019
1020         diag = hw->mac.ops.reset_hw(hw);
1021
1022         /* Allocate memory for storing MAC addresses */
1023         eth_dev->data->mac_addrs = rte_zmalloc("igbvf", ETHER_ADDR_LEN *
1024                 hw->mac.rar_entry_count, 0);
1025         if (eth_dev->data->mac_addrs == NULL) {
1026                 PMD_INIT_LOG(ERR,
1027                         "Failed to allocate %d bytes needed to store MAC "
1028                         "addresses",
1029                         ETHER_ADDR_LEN * hw->mac.rar_entry_count);
1030                 return -ENOMEM;
1031         }
1032
1033         /* Generate a random MAC address, if none was assigned by PF. */
1034         if (is_zero_ether_addr(perm_addr)) {
1035                 eth_random_addr(perm_addr->addr_bytes);
1036                 PMD_INIT_LOG(INFO, "\tVF MAC address not assigned by Host PF");
1037                 PMD_INIT_LOG(INFO, "\tAssign randomly generated MAC address "
1038                              "%02x:%02x:%02x:%02x:%02x:%02x",
1039                              perm_addr->addr_bytes[0],
1040                              perm_addr->addr_bytes[1],
1041                              perm_addr->addr_bytes[2],
1042                              perm_addr->addr_bytes[3],
1043                              perm_addr->addr_bytes[4],
1044                              perm_addr->addr_bytes[5]);
1045         }
1046
1047         diag = e1000_rar_set(hw, perm_addr->addr_bytes, 0);
1048         if (diag) {
1049                 rte_free(eth_dev->data->mac_addrs);
1050                 eth_dev->data->mac_addrs = NULL;
1051                 return diag;
1052         }
1053         /* Copy the permanent MAC address */
1054         ether_addr_copy((struct ether_addr *) hw->mac.perm_addr,
1055                         &eth_dev->data->mac_addrs[0]);
1056
1057         PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x "
1058                      "mac.type=%s",
1059                      eth_dev->data->port_id, pci_dev->id.vendor_id,
1060                      pci_dev->id.device_id, "igb_mac_82576_vf");
1061
1062         intr_handle = &pci_dev->intr_handle;
1063         rte_intr_callback_register(intr_handle,
1064                                    eth_igbvf_interrupt_handler, eth_dev);
1065
1066         return 0;
1067 }
1068
1069 static int
1070 eth_igbvf_dev_uninit(struct rte_eth_dev *eth_dev)
1071 {
1072         struct e1000_adapter *adapter =
1073                 E1000_DEV_PRIVATE(eth_dev->data->dev_private);
1074         struct rte_pci_device *pci_dev = E1000_DEV_TO_PCI(eth_dev);
1075
1076         PMD_INIT_FUNC_TRACE();
1077
1078         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1079                 return -EPERM;
1080
1081         if (adapter->stopped == 0)
1082                 igbvf_dev_close(eth_dev);
1083
1084         eth_dev->dev_ops = NULL;
1085         eth_dev->rx_pkt_burst = NULL;
1086         eth_dev->tx_pkt_burst = NULL;
1087
1088         rte_free(eth_dev->data->mac_addrs);
1089         eth_dev->data->mac_addrs = NULL;
1090
1091         /* disable uio intr before callback unregister */
1092         rte_intr_disable(&pci_dev->intr_handle);
1093         rte_intr_callback_unregister(&pci_dev->intr_handle,
1094                                      eth_igbvf_interrupt_handler,
1095                                      (void *)eth_dev);
1096
1097         return 0;
1098 }
1099
1100 static int eth_igb_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
1101         struct rte_pci_device *pci_dev)
1102 {
1103         return rte_eth_dev_pci_generic_probe(pci_dev,
1104                 sizeof(struct e1000_adapter), eth_igb_dev_init);
1105 }
1106
1107 static int eth_igb_pci_remove(struct rte_pci_device *pci_dev)
1108 {
1109         return rte_eth_dev_pci_generic_remove(pci_dev, eth_igb_dev_uninit);
1110 }
1111
1112 static struct rte_pci_driver rte_igb_pmd = {
1113         .id_table = pci_id_igb_map,
1114         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
1115         .probe = eth_igb_pci_probe,
1116         .remove = eth_igb_pci_remove,
1117 };
1118
1119
1120 static int eth_igbvf_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
1121         struct rte_pci_device *pci_dev)
1122 {
1123         return rte_eth_dev_pci_generic_probe(pci_dev,
1124                 sizeof(struct e1000_adapter), eth_igbvf_dev_init);
1125 }
1126
1127 static int eth_igbvf_pci_remove(struct rte_pci_device *pci_dev)
1128 {
1129         return rte_eth_dev_pci_generic_remove(pci_dev, eth_igbvf_dev_uninit);
1130 }
1131
1132 /*
1133  * virtual function driver struct
1134  */
1135 static struct rte_pci_driver rte_igbvf_pmd = {
1136         .id_table = pci_id_igbvf_map,
1137         .drv_flags = RTE_PCI_DRV_NEED_MAPPING,
1138         .probe = eth_igbvf_pci_probe,
1139         .remove = eth_igbvf_pci_remove,
1140 };
1141
1142 static void
1143 igb_vmdq_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1144 {
1145         struct e1000_hw *hw =
1146                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1147         /* RCTL: enable VLAN filter since VMDq always use VLAN filter */
1148         uint32_t rctl = E1000_READ_REG(hw, E1000_RCTL);
1149         rctl |= E1000_RCTL_VFE;
1150         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1151 }
1152
1153 static int
1154 igb_check_mq_mode(struct rte_eth_dev *dev)
1155 {
1156         enum rte_eth_rx_mq_mode rx_mq_mode = dev->data->dev_conf.rxmode.mq_mode;
1157         enum rte_eth_tx_mq_mode tx_mq_mode = dev->data->dev_conf.txmode.mq_mode;
1158         uint16_t nb_rx_q = dev->data->nb_rx_queues;
1159         uint16_t nb_tx_q = dev->data->nb_rx_queues;
1160
1161         if ((rx_mq_mode & ETH_MQ_RX_DCB_FLAG) ||
1162             tx_mq_mode == ETH_MQ_TX_DCB ||
1163             tx_mq_mode == ETH_MQ_TX_VMDQ_DCB) {
1164                 PMD_INIT_LOG(ERR, "DCB mode is not supported.");
1165                 return -EINVAL;
1166         }
1167         if (RTE_ETH_DEV_SRIOV(dev).active != 0) {
1168                 /* Check multi-queue mode.
1169                  * To no break software we accept ETH_MQ_RX_NONE as this might
1170                  * be used to turn off VLAN filter.
1171                  */
1172
1173                 if (rx_mq_mode == ETH_MQ_RX_NONE ||
1174                     rx_mq_mode == ETH_MQ_RX_VMDQ_ONLY) {
1175                         dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_ONLY;
1176                         RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool = 1;
1177                 } else {
1178                         /* Only support one queue on VFs.
1179                          * RSS together with SRIOV is not supported.
1180                          */
1181                         PMD_INIT_LOG(ERR, "SRIOV is active,"
1182                                         " wrong mq_mode rx %d.",
1183                                         rx_mq_mode);
1184                         return -EINVAL;
1185                 }
1186                 /* TX mode is not used here, so mode might be ignored.*/
1187                 if (tx_mq_mode != ETH_MQ_TX_VMDQ_ONLY) {
1188                         /* SRIOV only works in VMDq enable mode */
1189                         PMD_INIT_LOG(WARNING, "SRIOV is active,"
1190                                         " TX mode %d is not supported. "
1191                                         " Driver will behave as %d mode.",
1192                                         tx_mq_mode, ETH_MQ_TX_VMDQ_ONLY);
1193                 }
1194
1195                 /* check valid queue number */
1196                 if ((nb_rx_q > 1) || (nb_tx_q > 1)) {
1197                         PMD_INIT_LOG(ERR, "SRIOV is active,"
1198                                         " only support one queue on VFs.");
1199                         return -EINVAL;
1200                 }
1201         } else {
1202                 /* To no break software that set invalid mode, only display
1203                  * warning if invalid mode is used.
1204                  */
1205                 if (rx_mq_mode != ETH_MQ_RX_NONE &&
1206                     rx_mq_mode != ETH_MQ_RX_VMDQ_ONLY &&
1207                     rx_mq_mode != ETH_MQ_RX_RSS) {
1208                         /* RSS together with VMDq not supported*/
1209                         PMD_INIT_LOG(ERR, "RX mode %d is not supported.",
1210                                      rx_mq_mode);
1211                         return -EINVAL;
1212                 }
1213
1214                 if (tx_mq_mode != ETH_MQ_TX_NONE &&
1215                     tx_mq_mode != ETH_MQ_TX_VMDQ_ONLY) {
1216                         PMD_INIT_LOG(WARNING, "TX mode %d is not supported."
1217                                         " Due to txmode is meaningless in this"
1218                                         " driver, just ignore.",
1219                                         tx_mq_mode);
1220                 }
1221         }
1222         return 0;
1223 }
1224
1225 static int
1226 eth_igb_configure(struct rte_eth_dev *dev)
1227 {
1228         struct e1000_interrupt *intr =
1229                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
1230         int ret;
1231
1232         PMD_INIT_FUNC_TRACE();
1233
1234         /* multipe queue mode checking */
1235         ret  = igb_check_mq_mode(dev);
1236         if (ret != 0) {
1237                 PMD_DRV_LOG(ERR, "igb_check_mq_mode fails with %d.",
1238                             ret);
1239                 return ret;
1240         }
1241
1242         intr->flags |= E1000_FLAG_NEED_LINK_UPDATE;
1243         PMD_INIT_FUNC_TRACE();
1244
1245         return 0;
1246 }
1247
1248 static int
1249 eth_igb_start(struct rte_eth_dev *dev)
1250 {
1251         struct e1000_hw *hw =
1252                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1253         struct e1000_adapter *adapter =
1254                 E1000_DEV_PRIVATE(dev->data->dev_private);
1255         struct rte_pci_device *pci_dev = E1000_DEV_TO_PCI(dev);
1256         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1257         int ret, mask;
1258         uint32_t intr_vector = 0;
1259         uint32_t ctrl_ext;
1260         uint32_t *speeds;
1261         int num_speeds;
1262         bool autoneg;
1263
1264         PMD_INIT_FUNC_TRACE();
1265
1266         /* disable uio/vfio intr/eventfd mapping */
1267         rte_intr_disable(intr_handle);
1268
1269         /* Power up the phy. Needed to make the link go Up */
1270         eth_igb_dev_set_link_up(dev);
1271
1272         /*
1273          * Packet Buffer Allocation (PBA)
1274          * Writing PBA sets the receive portion of the buffer
1275          * the remainder is used for the transmit buffer.
1276          */
1277         if (hw->mac.type == e1000_82575) {
1278                 uint32_t pba;
1279
1280                 pba = E1000_PBA_32K; /* 32K for Rx, 16K for Tx */
1281                 E1000_WRITE_REG(hw, E1000_PBA, pba);
1282         }
1283
1284         /* Put the address into the Receive Address Array */
1285         e1000_rar_set(hw, hw->mac.addr, 0);
1286
1287         /* Initialize the hardware */
1288         if (igb_hardware_init(hw)) {
1289                 PMD_INIT_LOG(ERR, "Unable to initialize the hardware");
1290                 return -EIO;
1291         }
1292         adapter->stopped = 0;
1293
1294         E1000_WRITE_REG(hw, E1000_VET, ETHER_TYPE_VLAN << 16 | ETHER_TYPE_VLAN);
1295
1296         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
1297         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
1298         ctrl_ext |= E1000_CTRL_EXT_PFRSTD;
1299         E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
1300         E1000_WRITE_FLUSH(hw);
1301
1302         /* configure PF module if SRIOV enabled */
1303         igb_pf_host_configure(dev);
1304
1305         /* check and configure queue intr-vector mapping */
1306         if ((rte_intr_cap_multiple(intr_handle) ||
1307              !RTE_ETH_DEV_SRIOV(dev).active) &&
1308             dev->data->dev_conf.intr_conf.rxq != 0) {
1309                 intr_vector = dev->data->nb_rx_queues;
1310                 if (rte_intr_efd_enable(intr_handle, intr_vector))
1311                         return -1;
1312         }
1313
1314         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
1315                 intr_handle->intr_vec =
1316                         rte_zmalloc("intr_vec",
1317                                     dev->data->nb_rx_queues * sizeof(int), 0);
1318                 if (intr_handle->intr_vec == NULL) {
1319                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
1320                                      " intr_vec", dev->data->nb_rx_queues);
1321                         return -ENOMEM;
1322                 }
1323         }
1324
1325         /* confiugre msix for rx interrupt */
1326         eth_igb_configure_msix_intr(dev);
1327
1328         /* Configure for OS presence */
1329         igb_init_manageability(hw);
1330
1331         eth_igb_tx_init(dev);
1332
1333         /* This can fail when allocating mbufs for descriptor rings */
1334         ret = eth_igb_rx_init(dev);
1335         if (ret) {
1336                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
1337                 igb_dev_clear_queues(dev);
1338                 return ret;
1339         }
1340
1341         e1000_clear_hw_cntrs_base_generic(hw);
1342
1343         /*
1344          * VLAN Offload Settings
1345          */
1346         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK | \
1347                         ETH_VLAN_EXTEND_MASK;
1348         eth_igb_vlan_offload_set(dev, mask);
1349
1350         if (dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_VMDQ_ONLY) {
1351                 /* Enable VLAN filter since VMDq always use VLAN filter */
1352                 igb_vmdq_vlan_hw_filter_enable(dev);
1353         }
1354
1355         if ((hw->mac.type == e1000_82576) || (hw->mac.type == e1000_82580) ||
1356                 (hw->mac.type == e1000_i350) || (hw->mac.type == e1000_i210) ||
1357                 (hw->mac.type == e1000_i211)) {
1358                 /* Configure EITR with the maximum possible value (0xFFFF) */
1359                 E1000_WRITE_REG(hw, E1000_EITR(0), 0xFFFF);
1360         }
1361
1362         /* Setup link speed and duplex */
1363         speeds = &dev->data->dev_conf.link_speeds;
1364         if (*speeds == ETH_LINK_SPEED_AUTONEG) {
1365                 hw->phy.autoneg_advertised = E1000_ALL_SPEED_DUPLEX;
1366                 hw->mac.autoneg = 1;
1367         } else {
1368                 num_speeds = 0;
1369                 autoneg = (*speeds & ETH_LINK_SPEED_FIXED) == 0;
1370
1371                 /* Reset */
1372                 hw->phy.autoneg_advertised = 0;
1373
1374                 if (*speeds & ~(ETH_LINK_SPEED_10M_HD | ETH_LINK_SPEED_10M |
1375                                 ETH_LINK_SPEED_100M_HD | ETH_LINK_SPEED_100M |
1376                                 ETH_LINK_SPEED_1G | ETH_LINK_SPEED_FIXED)) {
1377                         num_speeds = -1;
1378                         goto error_invalid_config;
1379                 }
1380                 if (*speeds & ETH_LINK_SPEED_10M_HD) {
1381                         hw->phy.autoneg_advertised |= ADVERTISE_10_HALF;
1382                         num_speeds++;
1383                 }
1384                 if (*speeds & ETH_LINK_SPEED_10M) {
1385                         hw->phy.autoneg_advertised |= ADVERTISE_10_FULL;
1386                         num_speeds++;
1387                 }
1388                 if (*speeds & ETH_LINK_SPEED_100M_HD) {
1389                         hw->phy.autoneg_advertised |= ADVERTISE_100_HALF;
1390                         num_speeds++;
1391                 }
1392                 if (*speeds & ETH_LINK_SPEED_100M) {
1393                         hw->phy.autoneg_advertised |= ADVERTISE_100_FULL;
1394                         num_speeds++;
1395                 }
1396                 if (*speeds & ETH_LINK_SPEED_1G) {
1397                         hw->phy.autoneg_advertised |= ADVERTISE_1000_FULL;
1398                         num_speeds++;
1399                 }
1400                 if (num_speeds == 0 || (!autoneg && (num_speeds > 1)))
1401                         goto error_invalid_config;
1402
1403                 /* Set/reset the mac.autoneg based on the link speed,
1404                  * fixed or not
1405                  */
1406                 if (!autoneg) {
1407                         hw->mac.autoneg = 0;
1408                         hw->mac.forced_speed_duplex =
1409                                         hw->phy.autoneg_advertised;
1410                 } else {
1411                         hw->mac.autoneg = 1;
1412                 }
1413         }
1414
1415         e1000_setup_link(hw);
1416
1417         if (rte_intr_allow_others(intr_handle)) {
1418                 /* check if lsc interrupt is enabled */
1419                 if (dev->data->dev_conf.intr_conf.lsc != 0)
1420                         eth_igb_lsc_interrupt_setup(dev, TRUE);
1421                 else
1422                         eth_igb_lsc_interrupt_setup(dev, FALSE);
1423         } else {
1424                 rte_intr_callback_unregister(intr_handle,
1425                                              eth_igb_interrupt_handler,
1426                                              (void *)dev);
1427                 if (dev->data->dev_conf.intr_conf.lsc != 0)
1428                         PMD_INIT_LOG(INFO, "lsc won't enable because of"
1429                                      " no intr multiplex");
1430         }
1431
1432         /* check if rxq interrupt is enabled */
1433         if (dev->data->dev_conf.intr_conf.rxq != 0 &&
1434             rte_intr_dp_is_en(intr_handle))
1435                 eth_igb_rxq_interrupt_setup(dev);
1436
1437         /* enable uio/vfio intr/eventfd mapping */
1438         rte_intr_enable(intr_handle);
1439
1440         /* resume enabled intr since hw reset */
1441         igb_intr_enable(dev);
1442
1443         PMD_INIT_LOG(DEBUG, "<<");
1444
1445         return 0;
1446
1447 error_invalid_config:
1448         PMD_INIT_LOG(ERR, "Invalid advertised speeds (%u) for port %u",
1449                      dev->data->dev_conf.link_speeds, dev->data->port_id);
1450         igb_dev_clear_queues(dev);
1451         return -EINVAL;
1452 }
1453
1454 /*********************************************************************
1455  *
1456  *  This routine disables all traffic on the adapter by issuing a
1457  *  global reset on the MAC.
1458  *
1459  **********************************************************************/
1460 static void
1461 eth_igb_stop(struct rte_eth_dev *dev)
1462 {
1463         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1464         struct e1000_filter_info *filter_info =
1465                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
1466         struct rte_pci_device *pci_dev = E1000_DEV_TO_PCI(dev);
1467         struct rte_eth_link link;
1468         struct e1000_flex_filter *p_flex;
1469         struct e1000_5tuple_filter *p_5tuple, *p_5tuple_next;
1470         struct e1000_2tuple_filter *p_2tuple, *p_2tuple_next;
1471         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1472
1473         igb_intr_disable(hw);
1474
1475         /* disable intr eventfd mapping */
1476         rte_intr_disable(intr_handle);
1477
1478         igb_pf_reset_hw(hw);
1479         E1000_WRITE_REG(hw, E1000_WUC, 0);
1480
1481         /* Set bit for Go Link disconnect */
1482         if (hw->mac.type >= e1000_82580) {
1483                 uint32_t phpm_reg;
1484
1485                 phpm_reg = E1000_READ_REG(hw, E1000_82580_PHY_POWER_MGMT);
1486                 phpm_reg |= E1000_82580_PM_GO_LINKD;
1487                 E1000_WRITE_REG(hw, E1000_82580_PHY_POWER_MGMT, phpm_reg);
1488         }
1489
1490         /* Power down the phy. Needed to make the link go Down */
1491         eth_igb_dev_set_link_down(dev);
1492
1493         igb_dev_clear_queues(dev);
1494
1495         /* clear the recorded link status */
1496         memset(&link, 0, sizeof(link));
1497         rte_igb_dev_atomic_write_link_status(dev, &link);
1498
1499         /* Remove all flex filters of the device */
1500         while ((p_flex = TAILQ_FIRST(&filter_info->flex_list))) {
1501                 TAILQ_REMOVE(&filter_info->flex_list, p_flex, entries);
1502                 rte_free(p_flex);
1503         }
1504         filter_info->flex_mask = 0;
1505
1506         /* Remove all ntuple filters of the device */
1507         for (p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list);
1508              p_5tuple != NULL; p_5tuple = p_5tuple_next) {
1509                 p_5tuple_next = TAILQ_NEXT(p_5tuple, entries);
1510                 TAILQ_REMOVE(&filter_info->fivetuple_list,
1511                              p_5tuple, entries);
1512                 rte_free(p_5tuple);
1513         }
1514         filter_info->fivetuple_mask = 0;
1515         for (p_2tuple = TAILQ_FIRST(&filter_info->twotuple_list);
1516              p_2tuple != NULL; p_2tuple = p_2tuple_next) {
1517                 p_2tuple_next = TAILQ_NEXT(p_2tuple, entries);
1518                 TAILQ_REMOVE(&filter_info->twotuple_list,
1519                              p_2tuple, entries);
1520                 rte_free(p_2tuple);
1521         }
1522         filter_info->twotuple_mask = 0;
1523
1524         if (!rte_intr_allow_others(intr_handle))
1525                 /* resume to the default handler */
1526                 rte_intr_callback_register(intr_handle,
1527                                            eth_igb_interrupt_handler,
1528                                            (void *)dev);
1529
1530         /* Clean datapath event and queue/vec mapping */
1531         rte_intr_efd_disable(intr_handle);
1532         if (intr_handle->intr_vec != NULL) {
1533                 rte_free(intr_handle->intr_vec);
1534                 intr_handle->intr_vec = NULL;
1535         }
1536 }
1537
1538 static int
1539 eth_igb_dev_set_link_up(struct rte_eth_dev *dev)
1540 {
1541         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1542
1543         if (hw->phy.media_type == e1000_media_type_copper)
1544                 e1000_power_up_phy(hw);
1545         else
1546                 e1000_power_up_fiber_serdes_link(hw);
1547
1548         return 0;
1549 }
1550
1551 static int
1552 eth_igb_dev_set_link_down(struct rte_eth_dev *dev)
1553 {
1554         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1555
1556         if (hw->phy.media_type == e1000_media_type_copper)
1557                 e1000_power_down_phy(hw);
1558         else
1559                 e1000_shutdown_fiber_serdes_link(hw);
1560
1561         return 0;
1562 }
1563
1564 static void
1565 eth_igb_close(struct rte_eth_dev *dev)
1566 {
1567         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1568         struct e1000_adapter *adapter =
1569                 E1000_DEV_PRIVATE(dev->data->dev_private);
1570         struct rte_eth_link link;
1571         struct rte_pci_device *pci_dev = E1000_DEV_TO_PCI(dev);
1572         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1573
1574         eth_igb_stop(dev);
1575         adapter->stopped = 1;
1576
1577         e1000_phy_hw_reset(hw);
1578         igb_release_manageability(hw);
1579         igb_hw_control_release(hw);
1580
1581         /* Clear bit for Go Link disconnect */
1582         if (hw->mac.type >= e1000_82580) {
1583                 uint32_t phpm_reg;
1584
1585                 phpm_reg = E1000_READ_REG(hw, E1000_82580_PHY_POWER_MGMT);
1586                 phpm_reg &= ~E1000_82580_PM_GO_LINKD;
1587                 E1000_WRITE_REG(hw, E1000_82580_PHY_POWER_MGMT, phpm_reg);
1588         }
1589
1590         igb_dev_free_queues(dev);
1591
1592         if (intr_handle->intr_vec) {
1593                 rte_free(intr_handle->intr_vec);
1594                 intr_handle->intr_vec = NULL;
1595         }
1596
1597         memset(&link, 0, sizeof(link));
1598         rte_igb_dev_atomic_write_link_status(dev, &link);
1599 }
1600
1601 static int
1602 igb_get_rx_buffer_size(struct e1000_hw *hw)
1603 {
1604         uint32_t rx_buf_size;
1605         if (hw->mac.type == e1000_82576) {
1606                 rx_buf_size = (E1000_READ_REG(hw, E1000_RXPBS) & 0xffff) << 10;
1607         } else if (hw->mac.type == e1000_82580 || hw->mac.type == e1000_i350) {
1608                 /* PBS needs to be translated according to a lookup table */
1609                 rx_buf_size = (E1000_READ_REG(hw, E1000_RXPBS) & 0xf);
1610                 rx_buf_size = (uint32_t) e1000_rxpbs_adjust_82580(rx_buf_size);
1611                 rx_buf_size = (rx_buf_size << 10);
1612         } else if (hw->mac.type == e1000_i210 || hw->mac.type == e1000_i211) {
1613                 rx_buf_size = (E1000_READ_REG(hw, E1000_RXPBS) & 0x3f) << 10;
1614         } else {
1615                 rx_buf_size = (E1000_READ_REG(hw, E1000_PBA) & 0xffff) << 10;
1616         }
1617
1618         return rx_buf_size;
1619 }
1620
1621 /*********************************************************************
1622  *
1623  *  Initialize the hardware
1624  *
1625  **********************************************************************/
1626 static int
1627 igb_hardware_init(struct e1000_hw *hw)
1628 {
1629         uint32_t rx_buf_size;
1630         int diag;
1631
1632         /* Let the firmware know the OS is in control */
1633         igb_hw_control_acquire(hw);
1634
1635         /*
1636          * These parameters control the automatic generation (Tx) and
1637          * response (Rx) to Ethernet PAUSE frames.
1638          * - High water mark should allow for at least two standard size (1518)
1639          *   frames to be received after sending an XOFF.
1640          * - Low water mark works best when it is very near the high water mark.
1641          *   This allows the receiver to restart by sending XON when it has
1642          *   drained a bit. Here we use an arbitrary value of 1500 which will
1643          *   restart after one full frame is pulled from the buffer. There
1644          *   could be several smaller frames in the buffer and if so they will
1645          *   not trigger the XON until their total number reduces the buffer
1646          *   by 1500.
1647          * - The pause time is fairly large at 1000 x 512ns = 512 usec.
1648          */
1649         rx_buf_size = igb_get_rx_buffer_size(hw);
1650
1651         hw->fc.high_water = rx_buf_size - (ETHER_MAX_LEN * 2);
1652         hw->fc.low_water = hw->fc.high_water - 1500;
1653         hw->fc.pause_time = IGB_FC_PAUSE_TIME;
1654         hw->fc.send_xon = 1;
1655
1656         /* Set Flow control, use the tunable location if sane */
1657         if ((igb_fc_setting != e1000_fc_none) && (igb_fc_setting < 4))
1658                 hw->fc.requested_mode = igb_fc_setting;
1659         else
1660                 hw->fc.requested_mode = e1000_fc_none;
1661
1662         /* Issue a global reset */
1663         igb_pf_reset_hw(hw);
1664         E1000_WRITE_REG(hw, E1000_WUC, 0);
1665
1666         diag = e1000_init_hw(hw);
1667         if (diag < 0)
1668                 return diag;
1669
1670         E1000_WRITE_REG(hw, E1000_VET, ETHER_TYPE_VLAN << 16 | ETHER_TYPE_VLAN);
1671         e1000_get_phy_info(hw);
1672         e1000_check_for_link(hw);
1673
1674         return 0;
1675 }
1676
1677 /* This function is based on igb_update_stats_counters() in igb/if_igb.c */
1678 static void
1679 igb_read_stats_registers(struct e1000_hw *hw, struct e1000_hw_stats *stats)
1680 {
1681         int pause_frames;
1682
1683         uint64_t old_gprc  = stats->gprc;
1684         uint64_t old_gptc  = stats->gptc;
1685         uint64_t old_tpr   = stats->tpr;
1686         uint64_t old_tpt   = stats->tpt;
1687         uint64_t old_rpthc = stats->rpthc;
1688         uint64_t old_hgptc = stats->hgptc;
1689
1690         if(hw->phy.media_type == e1000_media_type_copper ||
1691             (E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU)) {
1692                 stats->symerrs +=
1693                     E1000_READ_REG(hw,E1000_SYMERRS);
1694                 stats->sec += E1000_READ_REG(hw, E1000_SEC);
1695         }
1696
1697         stats->crcerrs += E1000_READ_REG(hw, E1000_CRCERRS);
1698         stats->mpc += E1000_READ_REG(hw, E1000_MPC);
1699         stats->scc += E1000_READ_REG(hw, E1000_SCC);
1700         stats->ecol += E1000_READ_REG(hw, E1000_ECOL);
1701
1702         stats->mcc += E1000_READ_REG(hw, E1000_MCC);
1703         stats->latecol += E1000_READ_REG(hw, E1000_LATECOL);
1704         stats->colc += E1000_READ_REG(hw, E1000_COLC);
1705         stats->dc += E1000_READ_REG(hw, E1000_DC);
1706         stats->rlec += E1000_READ_REG(hw, E1000_RLEC);
1707         stats->xonrxc += E1000_READ_REG(hw, E1000_XONRXC);
1708         stats->xontxc += E1000_READ_REG(hw, E1000_XONTXC);
1709         /*
1710         ** For watchdog management we need to know if we have been
1711         ** paused during the last interval, so capture that here.
1712         */
1713         pause_frames = E1000_READ_REG(hw, E1000_XOFFRXC);
1714         stats->xoffrxc += pause_frames;
1715         stats->xofftxc += E1000_READ_REG(hw, E1000_XOFFTXC);
1716         stats->fcruc += E1000_READ_REG(hw, E1000_FCRUC);
1717         stats->prc64 += E1000_READ_REG(hw, E1000_PRC64);
1718         stats->prc127 += E1000_READ_REG(hw, E1000_PRC127);
1719         stats->prc255 += E1000_READ_REG(hw, E1000_PRC255);
1720         stats->prc511 += E1000_READ_REG(hw, E1000_PRC511);
1721         stats->prc1023 += E1000_READ_REG(hw, E1000_PRC1023);
1722         stats->prc1522 += E1000_READ_REG(hw, E1000_PRC1522);
1723         stats->gprc += E1000_READ_REG(hw, E1000_GPRC);
1724         stats->bprc += E1000_READ_REG(hw, E1000_BPRC);
1725         stats->mprc += E1000_READ_REG(hw, E1000_MPRC);
1726         stats->gptc += E1000_READ_REG(hw, E1000_GPTC);
1727
1728         /* For the 64-bit byte counters the low dword must be read first. */
1729         /* Both registers clear on the read of the high dword */
1730
1731         /* Workaround CRC bytes included in size, take away 4 bytes/packet */
1732         stats->gorc += E1000_READ_REG(hw, E1000_GORCL);
1733         stats->gorc += ((uint64_t)E1000_READ_REG(hw, E1000_GORCH) << 32);
1734         stats->gorc -= (stats->gprc - old_gprc) * ETHER_CRC_LEN;
1735         stats->gotc += E1000_READ_REG(hw, E1000_GOTCL);
1736         stats->gotc += ((uint64_t)E1000_READ_REG(hw, E1000_GOTCH) << 32);
1737         stats->gotc -= (stats->gptc - old_gptc) * ETHER_CRC_LEN;
1738
1739         stats->rnbc += E1000_READ_REG(hw, E1000_RNBC);
1740         stats->ruc += E1000_READ_REG(hw, E1000_RUC);
1741         stats->rfc += E1000_READ_REG(hw, E1000_RFC);
1742         stats->roc += E1000_READ_REG(hw, E1000_ROC);
1743         stats->rjc += E1000_READ_REG(hw, E1000_RJC);
1744
1745         stats->tpr += E1000_READ_REG(hw, E1000_TPR);
1746         stats->tpt += E1000_READ_REG(hw, E1000_TPT);
1747
1748         stats->tor += E1000_READ_REG(hw, E1000_TORL);
1749         stats->tor += ((uint64_t)E1000_READ_REG(hw, E1000_TORH) << 32);
1750         stats->tor -= (stats->tpr - old_tpr) * ETHER_CRC_LEN;
1751         stats->tot += E1000_READ_REG(hw, E1000_TOTL);
1752         stats->tot += ((uint64_t)E1000_READ_REG(hw, E1000_TOTH) << 32);
1753         stats->tot -= (stats->tpt - old_tpt) * ETHER_CRC_LEN;
1754
1755         stats->ptc64 += E1000_READ_REG(hw, E1000_PTC64);
1756         stats->ptc127 += E1000_READ_REG(hw, E1000_PTC127);
1757         stats->ptc255 += E1000_READ_REG(hw, E1000_PTC255);
1758         stats->ptc511 += E1000_READ_REG(hw, E1000_PTC511);
1759         stats->ptc1023 += E1000_READ_REG(hw, E1000_PTC1023);
1760         stats->ptc1522 += E1000_READ_REG(hw, E1000_PTC1522);
1761         stats->mptc += E1000_READ_REG(hw, E1000_MPTC);
1762         stats->bptc += E1000_READ_REG(hw, E1000_BPTC);
1763
1764         /* Interrupt Counts */
1765
1766         stats->iac += E1000_READ_REG(hw, E1000_IAC);
1767         stats->icrxptc += E1000_READ_REG(hw, E1000_ICRXPTC);
1768         stats->icrxatc += E1000_READ_REG(hw, E1000_ICRXATC);
1769         stats->ictxptc += E1000_READ_REG(hw, E1000_ICTXPTC);
1770         stats->ictxatc += E1000_READ_REG(hw, E1000_ICTXATC);
1771         stats->ictxqec += E1000_READ_REG(hw, E1000_ICTXQEC);
1772         stats->ictxqmtc += E1000_READ_REG(hw, E1000_ICTXQMTC);
1773         stats->icrxdmtc += E1000_READ_REG(hw, E1000_ICRXDMTC);
1774         stats->icrxoc += E1000_READ_REG(hw, E1000_ICRXOC);
1775
1776         /* Host to Card Statistics */
1777
1778         stats->cbtmpc += E1000_READ_REG(hw, E1000_CBTMPC);
1779         stats->htdpmc += E1000_READ_REG(hw, E1000_HTDPMC);
1780         stats->cbrdpc += E1000_READ_REG(hw, E1000_CBRDPC);
1781         stats->cbrmpc += E1000_READ_REG(hw, E1000_CBRMPC);
1782         stats->rpthc += E1000_READ_REG(hw, E1000_RPTHC);
1783         stats->hgptc += E1000_READ_REG(hw, E1000_HGPTC);
1784         stats->htcbdpc += E1000_READ_REG(hw, E1000_HTCBDPC);
1785         stats->hgorc += E1000_READ_REG(hw, E1000_HGORCL);
1786         stats->hgorc += ((uint64_t)E1000_READ_REG(hw, E1000_HGORCH) << 32);
1787         stats->hgorc -= (stats->rpthc - old_rpthc) * ETHER_CRC_LEN;
1788         stats->hgotc += E1000_READ_REG(hw, E1000_HGOTCL);
1789         stats->hgotc += ((uint64_t)E1000_READ_REG(hw, E1000_HGOTCH) << 32);
1790         stats->hgotc -= (stats->hgptc - old_hgptc) * ETHER_CRC_LEN;
1791         stats->lenerrs += E1000_READ_REG(hw, E1000_LENERRS);
1792         stats->scvpc += E1000_READ_REG(hw, E1000_SCVPC);
1793         stats->hrmpc += E1000_READ_REG(hw, E1000_HRMPC);
1794
1795         stats->algnerrc += E1000_READ_REG(hw, E1000_ALGNERRC);
1796         stats->rxerrc += E1000_READ_REG(hw, E1000_RXERRC);
1797         stats->tncrs += E1000_READ_REG(hw, E1000_TNCRS);
1798         stats->cexterr += E1000_READ_REG(hw, E1000_CEXTERR);
1799         stats->tsctc += E1000_READ_REG(hw, E1000_TSCTC);
1800         stats->tsctfc += E1000_READ_REG(hw, E1000_TSCTFC);
1801 }
1802
1803 static void
1804 eth_igb_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *rte_stats)
1805 {
1806         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1807         struct e1000_hw_stats *stats =
1808                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1809
1810         igb_read_stats_registers(hw, stats);
1811
1812         if (rte_stats == NULL)
1813                 return;
1814
1815         /* Rx Errors */
1816         rte_stats->imissed = stats->mpc;
1817         rte_stats->ierrors = stats->crcerrs +
1818                              stats->rlec + stats->ruc + stats->roc +
1819                              stats->rxerrc + stats->algnerrc + stats->cexterr;
1820
1821         /* Tx Errors */
1822         rte_stats->oerrors = stats->ecol + stats->latecol;
1823
1824         rte_stats->ipackets = stats->gprc;
1825         rte_stats->opackets = stats->gptc;
1826         rte_stats->ibytes   = stats->gorc;
1827         rte_stats->obytes   = stats->gotc;
1828 }
1829
1830 static void
1831 eth_igb_stats_reset(struct rte_eth_dev *dev)
1832 {
1833         struct e1000_hw_stats *hw_stats =
1834                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1835
1836         /* HW registers are cleared on read */
1837         eth_igb_stats_get(dev, NULL);
1838
1839         /* Reset software totals */
1840         memset(hw_stats, 0, sizeof(*hw_stats));
1841 }
1842
1843 static void
1844 eth_igb_xstats_reset(struct rte_eth_dev *dev)
1845 {
1846         struct e1000_hw_stats *stats =
1847                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1848
1849         /* HW registers are cleared on read */
1850         eth_igb_xstats_get(dev, NULL, IGB_NB_XSTATS);
1851
1852         /* Reset software totals */
1853         memset(stats, 0, sizeof(*stats));
1854 }
1855
1856 static int eth_igb_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
1857         struct rte_eth_xstat_name *xstats_names,
1858         __rte_unused unsigned int size)
1859 {
1860         unsigned i;
1861
1862         if (xstats_names == NULL)
1863                 return IGB_NB_XSTATS;
1864
1865         /* Note: limit checked in rte_eth_xstats_names() */
1866
1867         for (i = 0; i < IGB_NB_XSTATS; i++) {
1868                 snprintf(xstats_names[i].name, sizeof(xstats_names[i].name),
1869                          "%s", rte_igb_stats_strings[i].name);
1870         }
1871
1872         return IGB_NB_XSTATS;
1873 }
1874
1875 static int eth_igb_xstats_get_names_by_id(struct rte_eth_dev *dev,
1876                 struct rte_eth_xstat_name *xstats_names, const uint64_t *ids,
1877                 unsigned int limit)
1878 {
1879         unsigned int i;
1880
1881         if (!ids) {
1882                 if (xstats_names == NULL)
1883                         return IGB_NB_XSTATS;
1884
1885                 for (i = 0; i < IGB_NB_XSTATS; i++)
1886                         snprintf(xstats_names[i].name,
1887                                         sizeof(xstats_names[i].name),
1888                                         "%s", rte_igb_stats_strings[i].name);
1889
1890                 return IGB_NB_XSTATS;
1891
1892         } else {
1893                 struct rte_eth_xstat_name xstats_names_copy[IGB_NB_XSTATS];
1894
1895                 eth_igb_xstats_get_names_by_id(dev, xstats_names_copy, NULL,
1896                                 IGB_NB_XSTATS);
1897
1898                 for (i = 0; i < limit; i++) {
1899                         if (ids[i] >= IGB_NB_XSTATS) {
1900                                 PMD_INIT_LOG(ERR, "id value isn't valid");
1901                                 return -1;
1902                         }
1903                         strcpy(xstats_names[i].name,
1904                                         xstats_names_copy[ids[i]].name);
1905                 }
1906                 return limit;
1907         }
1908 }
1909
1910 static int
1911 eth_igb_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
1912                    unsigned n)
1913 {
1914         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1915         struct e1000_hw_stats *hw_stats =
1916                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1917         unsigned i;
1918
1919         if (n < IGB_NB_XSTATS)
1920                 return IGB_NB_XSTATS;
1921
1922         igb_read_stats_registers(hw, hw_stats);
1923
1924         /* If this is a reset xstats is NULL, and we have cleared the
1925          * registers by reading them.
1926          */
1927         if (!xstats)
1928                 return 0;
1929
1930         /* Extended stats */
1931         for (i = 0; i < IGB_NB_XSTATS; i++) {
1932                 xstats[i].id = i;
1933                 xstats[i].value = *(uint64_t *)(((char *)hw_stats) +
1934                         rte_igb_stats_strings[i].offset);
1935         }
1936
1937         return IGB_NB_XSTATS;
1938 }
1939
1940 static int
1941 eth_igb_xstats_get_by_id(struct rte_eth_dev *dev, const uint64_t *ids,
1942                 uint64_t *values, unsigned int n)
1943 {
1944         unsigned int i;
1945
1946         if (!ids) {
1947                 struct e1000_hw *hw =
1948                         E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1949                 struct e1000_hw_stats *hw_stats =
1950                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1951
1952                 if (n < IGB_NB_XSTATS)
1953                         return IGB_NB_XSTATS;
1954
1955                 igb_read_stats_registers(hw, hw_stats);
1956
1957                 /* If this is a reset xstats is NULL, and we have cleared the
1958                  * registers by reading them.
1959                  */
1960                 if (!values)
1961                         return 0;
1962
1963                 /* Extended stats */
1964                 for (i = 0; i < IGB_NB_XSTATS; i++)
1965                         values[i] = *(uint64_t *)(((char *)hw_stats) +
1966                                         rte_igb_stats_strings[i].offset);
1967
1968                 return IGB_NB_XSTATS;
1969
1970         } else {
1971                 uint64_t values_copy[IGB_NB_XSTATS];
1972
1973                 eth_igb_xstats_get_by_id(dev, NULL, values_copy,
1974                                 IGB_NB_XSTATS);
1975
1976                 for (i = 0; i < n; i++) {
1977                         if (ids[i] >= IGB_NB_XSTATS) {
1978                                 PMD_INIT_LOG(ERR, "id value isn't valid");
1979                                 return -1;
1980                         }
1981                         values[i] = values_copy[ids[i]];
1982                 }
1983                 return n;
1984         }
1985 }
1986
1987 static void
1988 igbvf_read_stats_registers(struct e1000_hw *hw, struct e1000_vf_stats *hw_stats)
1989 {
1990         /* Good Rx packets, include VF loopback */
1991         UPDATE_VF_STAT(E1000_VFGPRC,
1992             hw_stats->last_gprc, hw_stats->gprc);
1993
1994         /* Good Rx octets, include VF loopback */
1995         UPDATE_VF_STAT(E1000_VFGORC,
1996             hw_stats->last_gorc, hw_stats->gorc);
1997
1998         /* Good Tx packets, include VF loopback */
1999         UPDATE_VF_STAT(E1000_VFGPTC,
2000             hw_stats->last_gptc, hw_stats->gptc);
2001
2002         /* Good Tx octets, include VF loopback */
2003         UPDATE_VF_STAT(E1000_VFGOTC,
2004             hw_stats->last_gotc, hw_stats->gotc);
2005
2006         /* Rx Multicst packets */
2007         UPDATE_VF_STAT(E1000_VFMPRC,
2008             hw_stats->last_mprc, hw_stats->mprc);
2009
2010         /* Good Rx loopback packets */
2011         UPDATE_VF_STAT(E1000_VFGPRLBC,
2012             hw_stats->last_gprlbc, hw_stats->gprlbc);
2013
2014         /* Good Rx loopback octets */
2015         UPDATE_VF_STAT(E1000_VFGORLBC,
2016             hw_stats->last_gorlbc, hw_stats->gorlbc);
2017
2018         /* Good Tx loopback packets */
2019         UPDATE_VF_STAT(E1000_VFGPTLBC,
2020             hw_stats->last_gptlbc, hw_stats->gptlbc);
2021
2022         /* Good Tx loopback octets */
2023         UPDATE_VF_STAT(E1000_VFGOTLBC,
2024             hw_stats->last_gotlbc, hw_stats->gotlbc);
2025 }
2026
2027 static int eth_igbvf_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
2028                                      struct rte_eth_xstat_name *xstats_names,
2029                                      __rte_unused unsigned limit)
2030 {
2031         unsigned i;
2032
2033         if (xstats_names != NULL)
2034                 for (i = 0; i < IGBVF_NB_XSTATS; i++) {
2035                         snprintf(xstats_names[i].name,
2036                                 sizeof(xstats_names[i].name), "%s",
2037                                 rte_igbvf_stats_strings[i].name);
2038                 }
2039         return IGBVF_NB_XSTATS;
2040 }
2041
2042 static int
2043 eth_igbvf_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
2044                      unsigned n)
2045 {
2046         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2047         struct e1000_vf_stats *hw_stats = (struct e1000_vf_stats *)
2048                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2049         unsigned i;
2050
2051         if (n < IGBVF_NB_XSTATS)
2052                 return IGBVF_NB_XSTATS;
2053
2054         igbvf_read_stats_registers(hw, hw_stats);
2055
2056         if (!xstats)
2057                 return 0;
2058
2059         for (i = 0; i < IGBVF_NB_XSTATS; i++) {
2060                 xstats[i].id = i;
2061                 xstats[i].value = *(uint64_t *)(((char *)hw_stats) +
2062                         rte_igbvf_stats_strings[i].offset);
2063         }
2064
2065         return IGBVF_NB_XSTATS;
2066 }
2067
2068 static void
2069 eth_igbvf_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *rte_stats)
2070 {
2071         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2072         struct e1000_vf_stats *hw_stats = (struct e1000_vf_stats *)
2073                           E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2074
2075         igbvf_read_stats_registers(hw, hw_stats);
2076
2077         if (rte_stats == NULL)
2078                 return;
2079
2080         rte_stats->ipackets = hw_stats->gprc;
2081         rte_stats->ibytes = hw_stats->gorc;
2082         rte_stats->opackets = hw_stats->gptc;
2083         rte_stats->obytes = hw_stats->gotc;
2084 }
2085
2086 static void
2087 eth_igbvf_stats_reset(struct rte_eth_dev *dev)
2088 {
2089         struct e1000_vf_stats *hw_stats = (struct e1000_vf_stats*)
2090                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2091
2092         /* Sync HW register to the last stats */
2093         eth_igbvf_stats_get(dev, NULL);
2094
2095         /* reset HW current stats*/
2096         memset(&hw_stats->gprc, 0, sizeof(*hw_stats) -
2097                offsetof(struct e1000_vf_stats, gprc));
2098 }
2099
2100 static int
2101 eth_igb_fw_version_get(struct rte_eth_dev *dev, char *fw_version,
2102                        size_t fw_size)
2103 {
2104         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2105         struct e1000_fw_version fw;
2106         int ret;
2107
2108         e1000_get_fw_version(hw, &fw);
2109
2110         switch (hw->mac.type) {
2111         case e1000_i210:
2112         case e1000_i211:
2113                 if (!(e1000_get_flash_presence_i210(hw))) {
2114                         ret = snprintf(fw_version, fw_size,
2115                                  "%2d.%2d-%d",
2116                                  fw.invm_major, fw.invm_minor,
2117                                  fw.invm_img_type);
2118                         break;
2119                 }
2120                 /* fall through */
2121         default:
2122                 /* if option rom is valid, display its version too */
2123                 if (fw.or_valid) {
2124                         ret = snprintf(fw_version, fw_size,
2125                                  "%d.%d, 0x%08x, %d.%d.%d",
2126                                  fw.eep_major, fw.eep_minor, fw.etrack_id,
2127                                  fw.or_major, fw.or_build, fw.or_patch);
2128                 /* no option rom */
2129                 } else {
2130                         if (fw.etrack_id != 0X0000) {
2131                                 ret = snprintf(fw_version, fw_size,
2132                                          "%d.%d, 0x%08x",
2133                                          fw.eep_major, fw.eep_minor,
2134                                          fw.etrack_id);
2135                         } else {
2136                                 ret = snprintf(fw_version, fw_size,
2137                                          "%d.%d.%d",
2138                                          fw.eep_major, fw.eep_minor,
2139                                          fw.eep_build);
2140                         }
2141                 }
2142                 break;
2143         }
2144
2145         ret += 1; /* add the size of '\0' */
2146         if (fw_size < (u32)ret)
2147                 return ret;
2148         else
2149                 return 0;
2150 }
2151
2152 static void
2153 eth_igb_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
2154 {
2155         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2156
2157         dev_info->pci_dev = RTE_DEV_TO_PCI(dev->device);
2158         dev_info->min_rx_bufsize = 256; /* See BSIZE field of RCTL register. */
2159         dev_info->max_rx_pktlen  = 0x3FFF; /* See RLPML register. */
2160         dev_info->max_mac_addrs = hw->mac.rar_entry_count;
2161         dev_info->rx_offload_capa =
2162                 DEV_RX_OFFLOAD_VLAN_STRIP |
2163                 DEV_RX_OFFLOAD_IPV4_CKSUM |
2164                 DEV_RX_OFFLOAD_UDP_CKSUM  |
2165                 DEV_RX_OFFLOAD_TCP_CKSUM;
2166         dev_info->tx_offload_capa =
2167                 DEV_TX_OFFLOAD_VLAN_INSERT |
2168                 DEV_TX_OFFLOAD_IPV4_CKSUM  |
2169                 DEV_TX_OFFLOAD_UDP_CKSUM   |
2170                 DEV_TX_OFFLOAD_TCP_CKSUM   |
2171                 DEV_TX_OFFLOAD_SCTP_CKSUM  |
2172                 DEV_TX_OFFLOAD_TCP_TSO;
2173
2174         switch (hw->mac.type) {
2175         case e1000_82575:
2176                 dev_info->max_rx_queues = 4;
2177                 dev_info->max_tx_queues = 4;
2178                 dev_info->max_vmdq_pools = 0;
2179                 break;
2180
2181         case e1000_82576:
2182                 dev_info->max_rx_queues = 16;
2183                 dev_info->max_tx_queues = 16;
2184                 dev_info->max_vmdq_pools = ETH_8_POOLS;
2185                 dev_info->vmdq_queue_num = 16;
2186                 break;
2187
2188         case e1000_82580:
2189                 dev_info->max_rx_queues = 8;
2190                 dev_info->max_tx_queues = 8;
2191                 dev_info->max_vmdq_pools = ETH_8_POOLS;
2192                 dev_info->vmdq_queue_num = 8;
2193                 break;
2194
2195         case e1000_i350:
2196                 dev_info->max_rx_queues = 8;
2197                 dev_info->max_tx_queues = 8;
2198                 dev_info->max_vmdq_pools = ETH_8_POOLS;
2199                 dev_info->vmdq_queue_num = 8;
2200                 break;
2201
2202         case e1000_i354:
2203                 dev_info->max_rx_queues = 8;
2204                 dev_info->max_tx_queues = 8;
2205                 break;
2206
2207         case e1000_i210:
2208                 dev_info->max_rx_queues = 4;
2209                 dev_info->max_tx_queues = 4;
2210                 dev_info->max_vmdq_pools = 0;
2211                 break;
2212
2213         case e1000_i211:
2214                 dev_info->max_rx_queues = 2;
2215                 dev_info->max_tx_queues = 2;
2216                 dev_info->max_vmdq_pools = 0;
2217                 break;
2218
2219         default:
2220                 /* Should not happen */
2221                 break;
2222         }
2223         dev_info->hash_key_size = IGB_HKEY_MAX_INDEX * sizeof(uint32_t);
2224         dev_info->reta_size = ETH_RSS_RETA_SIZE_128;
2225         dev_info->flow_type_rss_offloads = IGB_RSS_OFFLOAD_ALL;
2226
2227         dev_info->default_rxconf = (struct rte_eth_rxconf) {
2228                 .rx_thresh = {
2229                         .pthresh = IGB_DEFAULT_RX_PTHRESH,
2230                         .hthresh = IGB_DEFAULT_RX_HTHRESH,
2231                         .wthresh = IGB_DEFAULT_RX_WTHRESH,
2232                 },
2233                 .rx_free_thresh = IGB_DEFAULT_RX_FREE_THRESH,
2234                 .rx_drop_en = 0,
2235         };
2236
2237         dev_info->default_txconf = (struct rte_eth_txconf) {
2238                 .tx_thresh = {
2239                         .pthresh = IGB_DEFAULT_TX_PTHRESH,
2240                         .hthresh = IGB_DEFAULT_TX_HTHRESH,
2241                         .wthresh = IGB_DEFAULT_TX_WTHRESH,
2242                 },
2243                 .txq_flags = 0,
2244         };
2245
2246         dev_info->rx_desc_lim = rx_desc_lim;
2247         dev_info->tx_desc_lim = tx_desc_lim;
2248
2249         dev_info->speed_capa = ETH_LINK_SPEED_10M_HD | ETH_LINK_SPEED_10M |
2250                         ETH_LINK_SPEED_100M_HD | ETH_LINK_SPEED_100M |
2251                         ETH_LINK_SPEED_1G;
2252 }
2253
2254 static const uint32_t *
2255 eth_igb_supported_ptypes_get(struct rte_eth_dev *dev)
2256 {
2257         static const uint32_t ptypes[] = {
2258                 /* refers to igb_rxd_pkt_info_to_pkt_type() */
2259                 RTE_PTYPE_L2_ETHER,
2260                 RTE_PTYPE_L3_IPV4,
2261                 RTE_PTYPE_L3_IPV4_EXT,
2262                 RTE_PTYPE_L3_IPV6,
2263                 RTE_PTYPE_L3_IPV6_EXT,
2264                 RTE_PTYPE_L4_TCP,
2265                 RTE_PTYPE_L4_UDP,
2266                 RTE_PTYPE_L4_SCTP,
2267                 RTE_PTYPE_TUNNEL_IP,
2268                 RTE_PTYPE_INNER_L3_IPV6,
2269                 RTE_PTYPE_INNER_L3_IPV6_EXT,
2270                 RTE_PTYPE_INNER_L4_TCP,
2271                 RTE_PTYPE_INNER_L4_UDP,
2272                 RTE_PTYPE_UNKNOWN
2273         };
2274
2275         if (dev->rx_pkt_burst == eth_igb_recv_pkts ||
2276             dev->rx_pkt_burst == eth_igb_recv_scattered_pkts)
2277                 return ptypes;
2278         return NULL;
2279 }
2280
2281 static void
2282 eth_igbvf_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
2283 {
2284         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2285
2286         dev_info->pci_dev = RTE_DEV_TO_PCI(dev->device);
2287         dev_info->min_rx_bufsize = 256; /* See BSIZE field of RCTL register. */
2288         dev_info->max_rx_pktlen  = 0x3FFF; /* See RLPML register. */
2289         dev_info->max_mac_addrs = hw->mac.rar_entry_count;
2290         dev_info->rx_offload_capa = DEV_RX_OFFLOAD_VLAN_STRIP |
2291                                 DEV_RX_OFFLOAD_IPV4_CKSUM |
2292                                 DEV_RX_OFFLOAD_UDP_CKSUM  |
2293                                 DEV_RX_OFFLOAD_TCP_CKSUM;
2294         dev_info->tx_offload_capa = DEV_TX_OFFLOAD_VLAN_INSERT |
2295                                 DEV_TX_OFFLOAD_IPV4_CKSUM  |
2296                                 DEV_TX_OFFLOAD_UDP_CKSUM   |
2297                                 DEV_TX_OFFLOAD_TCP_CKSUM   |
2298                                 DEV_TX_OFFLOAD_SCTP_CKSUM  |
2299                                 DEV_TX_OFFLOAD_TCP_TSO;
2300         switch (hw->mac.type) {
2301         case e1000_vfadapt:
2302                 dev_info->max_rx_queues = 2;
2303                 dev_info->max_tx_queues = 2;
2304                 break;
2305         case e1000_vfadapt_i350:
2306                 dev_info->max_rx_queues = 1;
2307                 dev_info->max_tx_queues = 1;
2308                 break;
2309         default:
2310                 /* Should not happen */
2311                 break;
2312         }
2313
2314         dev_info->default_rxconf = (struct rte_eth_rxconf) {
2315                 .rx_thresh = {
2316                         .pthresh = IGB_DEFAULT_RX_PTHRESH,
2317                         .hthresh = IGB_DEFAULT_RX_HTHRESH,
2318                         .wthresh = IGB_DEFAULT_RX_WTHRESH,
2319                 },
2320                 .rx_free_thresh = IGB_DEFAULT_RX_FREE_THRESH,
2321                 .rx_drop_en = 0,
2322         };
2323
2324         dev_info->default_txconf = (struct rte_eth_txconf) {
2325                 .tx_thresh = {
2326                         .pthresh = IGB_DEFAULT_TX_PTHRESH,
2327                         .hthresh = IGB_DEFAULT_TX_HTHRESH,
2328                         .wthresh = IGB_DEFAULT_TX_WTHRESH,
2329                 },
2330                 .txq_flags = 0,
2331         };
2332
2333         dev_info->rx_desc_lim = rx_desc_lim;
2334         dev_info->tx_desc_lim = tx_desc_lim;
2335 }
2336
2337 /* return 0 means link status changed, -1 means not changed */
2338 static int
2339 eth_igb_link_update(struct rte_eth_dev *dev, int wait_to_complete)
2340 {
2341         struct e1000_hw *hw =
2342                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2343         struct rte_eth_link link, old;
2344         int link_check, count;
2345
2346         link_check = 0;
2347         hw->mac.get_link_status = 1;
2348
2349         /* possible wait-to-complete in up to 9 seconds */
2350         for (count = 0; count < IGB_LINK_UPDATE_CHECK_TIMEOUT; count ++) {
2351                 /* Read the real link status */
2352                 switch (hw->phy.media_type) {
2353                 case e1000_media_type_copper:
2354                         /* Do the work to read phy */
2355                         e1000_check_for_link(hw);
2356                         link_check = !hw->mac.get_link_status;
2357                         break;
2358
2359                 case e1000_media_type_fiber:
2360                         e1000_check_for_link(hw);
2361                         link_check = (E1000_READ_REG(hw, E1000_STATUS) &
2362                                       E1000_STATUS_LU);
2363                         break;
2364
2365                 case e1000_media_type_internal_serdes:
2366                         e1000_check_for_link(hw);
2367                         link_check = hw->mac.serdes_has_link;
2368                         break;
2369
2370                 /* VF device is type_unknown */
2371                 case e1000_media_type_unknown:
2372                         eth_igbvf_link_update(hw);
2373                         link_check = !hw->mac.get_link_status;
2374                         break;
2375
2376                 default:
2377                         break;
2378                 }
2379                 if (link_check || wait_to_complete == 0)
2380                         break;
2381                 rte_delay_ms(IGB_LINK_UPDATE_CHECK_INTERVAL);
2382         }
2383         memset(&link, 0, sizeof(link));
2384         rte_igb_dev_atomic_read_link_status(dev, &link);
2385         old = link;
2386
2387         /* Now we check if a transition has happened */
2388         if (link_check) {
2389                 uint16_t duplex, speed;
2390                 hw->mac.ops.get_link_up_info(hw, &speed, &duplex);
2391                 link.link_duplex = (duplex == FULL_DUPLEX) ?
2392                                 ETH_LINK_FULL_DUPLEX :
2393                                 ETH_LINK_HALF_DUPLEX;
2394                 link.link_speed = speed;
2395                 link.link_status = ETH_LINK_UP;
2396                 link.link_autoneg = !(dev->data->dev_conf.link_speeds &
2397                                 ETH_LINK_SPEED_FIXED);
2398         } else if (!link_check) {
2399                 link.link_speed = 0;
2400                 link.link_duplex = ETH_LINK_HALF_DUPLEX;
2401                 link.link_status = ETH_LINK_DOWN;
2402                 link.link_autoneg = ETH_LINK_SPEED_FIXED;
2403         }
2404         rte_igb_dev_atomic_write_link_status(dev, &link);
2405
2406         /* not changed */
2407         if (old.link_status == link.link_status)
2408                 return -1;
2409
2410         /* changed */
2411         return 0;
2412 }
2413
2414 /*
2415  * igb_hw_control_acquire sets CTRL_EXT:DRV_LOAD bit.
2416  * For ASF and Pass Through versions of f/w this means
2417  * that the driver is loaded.
2418  */
2419 static void
2420 igb_hw_control_acquire(struct e1000_hw *hw)
2421 {
2422         uint32_t ctrl_ext;
2423
2424         /* Let firmware know the driver has taken over */
2425         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
2426         E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
2427 }
2428
2429 /*
2430  * igb_hw_control_release resets CTRL_EXT:DRV_LOAD bit.
2431  * For ASF and Pass Through versions of f/w this means that the
2432  * driver is no longer loaded.
2433  */
2434 static void
2435 igb_hw_control_release(struct e1000_hw *hw)
2436 {
2437         uint32_t ctrl_ext;
2438
2439         /* Let firmware taken over control of h/w */
2440         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
2441         E1000_WRITE_REG(hw, E1000_CTRL_EXT,
2442                         ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
2443 }
2444
2445 /*
2446  * Bit of a misnomer, what this really means is
2447  * to enable OS management of the system... aka
2448  * to disable special hardware management features.
2449  */
2450 static void
2451 igb_init_manageability(struct e1000_hw *hw)
2452 {
2453         if (e1000_enable_mng_pass_thru(hw)) {
2454                 uint32_t manc2h = E1000_READ_REG(hw, E1000_MANC2H);
2455                 uint32_t manc = E1000_READ_REG(hw, E1000_MANC);
2456
2457                 /* disable hardware interception of ARP */
2458                 manc &= ~(E1000_MANC_ARP_EN);
2459
2460                 /* enable receiving management packets to the host */
2461                 manc |= E1000_MANC_EN_MNG2HOST;
2462                 manc2h |= 1 << 5;  /* Mng Port 623 */
2463                 manc2h |= 1 << 6;  /* Mng Port 664 */
2464                 E1000_WRITE_REG(hw, E1000_MANC2H, manc2h);
2465                 E1000_WRITE_REG(hw, E1000_MANC, manc);
2466         }
2467 }
2468
2469 static void
2470 igb_release_manageability(struct e1000_hw *hw)
2471 {
2472         if (e1000_enable_mng_pass_thru(hw)) {
2473                 uint32_t manc = E1000_READ_REG(hw, E1000_MANC);
2474
2475                 manc |= E1000_MANC_ARP_EN;
2476                 manc &= ~E1000_MANC_EN_MNG2HOST;
2477
2478                 E1000_WRITE_REG(hw, E1000_MANC, manc);
2479         }
2480 }
2481
2482 static void
2483 eth_igb_promiscuous_enable(struct rte_eth_dev *dev)
2484 {
2485         struct e1000_hw *hw =
2486                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2487         uint32_t rctl;
2488
2489         rctl = E1000_READ_REG(hw, E1000_RCTL);
2490         rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
2491         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2492 }
2493
2494 static void
2495 eth_igb_promiscuous_disable(struct rte_eth_dev *dev)
2496 {
2497         struct e1000_hw *hw =
2498                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2499         uint32_t rctl;
2500
2501         rctl = E1000_READ_REG(hw, E1000_RCTL);
2502         rctl &= (~E1000_RCTL_UPE);
2503         if (dev->data->all_multicast == 1)
2504                 rctl |= E1000_RCTL_MPE;
2505         else
2506                 rctl &= (~E1000_RCTL_MPE);
2507         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2508 }
2509
2510 static void
2511 eth_igb_allmulticast_enable(struct rte_eth_dev *dev)
2512 {
2513         struct e1000_hw *hw =
2514                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2515         uint32_t rctl;
2516
2517         rctl = E1000_READ_REG(hw, E1000_RCTL);
2518         rctl |= E1000_RCTL_MPE;
2519         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2520 }
2521
2522 static void
2523 eth_igb_allmulticast_disable(struct rte_eth_dev *dev)
2524 {
2525         struct e1000_hw *hw =
2526                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2527         uint32_t rctl;
2528
2529         if (dev->data->promiscuous == 1)
2530                 return; /* must remain in all_multicast mode */
2531         rctl = E1000_READ_REG(hw, E1000_RCTL);
2532         rctl &= (~E1000_RCTL_MPE);
2533         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2534 }
2535
2536 static int
2537 eth_igb_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
2538 {
2539         struct e1000_hw *hw =
2540                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2541         struct e1000_vfta * shadow_vfta =
2542                 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
2543         uint32_t vfta;
2544         uint32_t vid_idx;
2545         uint32_t vid_bit;
2546
2547         vid_idx = (uint32_t) ((vlan_id >> E1000_VFTA_ENTRY_SHIFT) &
2548                               E1000_VFTA_ENTRY_MASK);
2549         vid_bit = (uint32_t) (1 << (vlan_id & E1000_VFTA_ENTRY_BIT_SHIFT_MASK));
2550         vfta = E1000_READ_REG_ARRAY(hw, E1000_VFTA, vid_idx);
2551         if (on)
2552                 vfta |= vid_bit;
2553         else
2554                 vfta &= ~vid_bit;
2555         E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, vid_idx, vfta);
2556
2557         /* update local VFTA copy */
2558         shadow_vfta->vfta[vid_idx] = vfta;
2559
2560         return 0;
2561 }
2562
2563 static int
2564 eth_igb_vlan_tpid_set(struct rte_eth_dev *dev,
2565                       enum rte_vlan_type vlan_type,
2566                       uint16_t tpid)
2567 {
2568         struct e1000_hw *hw =
2569                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2570         uint32_t reg, qinq;
2571
2572         qinq = E1000_READ_REG(hw, E1000_CTRL_EXT);
2573         qinq &= E1000_CTRL_EXT_EXT_VLAN;
2574
2575         /* only outer TPID of double VLAN can be configured*/
2576         if (qinq && vlan_type == ETH_VLAN_TYPE_OUTER) {
2577                 reg = E1000_READ_REG(hw, E1000_VET);
2578                 reg = (reg & (~E1000_VET_VET_EXT)) |
2579                         ((uint32_t)tpid << E1000_VET_VET_EXT_SHIFT);
2580                 E1000_WRITE_REG(hw, E1000_VET, reg);
2581
2582                 return 0;
2583         }
2584
2585         /* all other TPID values are read-only*/
2586         PMD_DRV_LOG(ERR, "Not supported");
2587
2588         return -ENOTSUP;
2589 }
2590
2591 static void
2592 igb_vlan_hw_filter_disable(struct rte_eth_dev *dev)
2593 {
2594         struct e1000_hw *hw =
2595                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2596         uint32_t reg;
2597
2598         /* Filter Table Disable */
2599         reg = E1000_READ_REG(hw, E1000_RCTL);
2600         reg &= ~E1000_RCTL_CFIEN;
2601         reg &= ~E1000_RCTL_VFE;
2602         E1000_WRITE_REG(hw, E1000_RCTL, reg);
2603 }
2604
2605 static void
2606 igb_vlan_hw_filter_enable(struct rte_eth_dev *dev)
2607 {
2608         struct e1000_hw *hw =
2609                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2610         struct e1000_vfta * shadow_vfta =
2611                 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
2612         uint32_t reg;
2613         int i;
2614
2615         /* Filter Table Enable, CFI not used for packet acceptance */
2616         reg = E1000_READ_REG(hw, E1000_RCTL);
2617         reg &= ~E1000_RCTL_CFIEN;
2618         reg |= E1000_RCTL_VFE;
2619         E1000_WRITE_REG(hw, E1000_RCTL, reg);
2620
2621         /* restore VFTA table */
2622         for (i = 0; i < IGB_VFTA_SIZE; i++)
2623                 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, i, shadow_vfta->vfta[i]);
2624 }
2625
2626 static void
2627 igb_vlan_hw_strip_disable(struct rte_eth_dev *dev)
2628 {
2629         struct e1000_hw *hw =
2630                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2631         uint32_t reg;
2632
2633         /* VLAN Mode Disable */
2634         reg = E1000_READ_REG(hw, E1000_CTRL);
2635         reg &= ~E1000_CTRL_VME;
2636         E1000_WRITE_REG(hw, E1000_CTRL, reg);
2637 }
2638
2639 static void
2640 igb_vlan_hw_strip_enable(struct rte_eth_dev *dev)
2641 {
2642         struct e1000_hw *hw =
2643                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2644         uint32_t reg;
2645
2646         /* VLAN Mode Enable */
2647         reg = E1000_READ_REG(hw, E1000_CTRL);
2648         reg |= E1000_CTRL_VME;
2649         E1000_WRITE_REG(hw, E1000_CTRL, reg);
2650 }
2651
2652 static void
2653 igb_vlan_hw_extend_disable(struct rte_eth_dev *dev)
2654 {
2655         struct e1000_hw *hw =
2656                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2657         uint32_t reg;
2658
2659         /* CTRL_EXT: Extended VLAN */
2660         reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
2661         reg &= ~E1000_CTRL_EXT_EXTEND_VLAN;
2662         E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg);
2663
2664         /* Update maximum packet length */
2665         if (dev->data->dev_conf.rxmode.jumbo_frame == 1)
2666                 E1000_WRITE_REG(hw, E1000_RLPML,
2667                         dev->data->dev_conf.rxmode.max_rx_pkt_len +
2668                                                 VLAN_TAG_SIZE);
2669 }
2670
2671 static void
2672 igb_vlan_hw_extend_enable(struct rte_eth_dev *dev)
2673 {
2674         struct e1000_hw *hw =
2675                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2676         uint32_t reg;
2677
2678         /* CTRL_EXT: Extended VLAN */
2679         reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
2680         reg |= E1000_CTRL_EXT_EXTEND_VLAN;
2681         E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg);
2682
2683         /* Update maximum packet length */
2684         if (dev->data->dev_conf.rxmode.jumbo_frame == 1)
2685                 E1000_WRITE_REG(hw, E1000_RLPML,
2686                         dev->data->dev_conf.rxmode.max_rx_pkt_len +
2687                                                 2 * VLAN_TAG_SIZE);
2688 }
2689
2690 static void
2691 eth_igb_vlan_offload_set(struct rte_eth_dev *dev, int mask)
2692 {
2693         if(mask & ETH_VLAN_STRIP_MASK){
2694                 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
2695                         igb_vlan_hw_strip_enable(dev);
2696                 else
2697                         igb_vlan_hw_strip_disable(dev);
2698         }
2699
2700         if(mask & ETH_VLAN_FILTER_MASK){
2701                 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
2702                         igb_vlan_hw_filter_enable(dev);
2703                 else
2704                         igb_vlan_hw_filter_disable(dev);
2705         }
2706
2707         if(mask & ETH_VLAN_EXTEND_MASK){
2708                 if (dev->data->dev_conf.rxmode.hw_vlan_extend)
2709                         igb_vlan_hw_extend_enable(dev);
2710                 else
2711                         igb_vlan_hw_extend_disable(dev);
2712         }
2713 }
2714
2715
2716 /**
2717  * It enables the interrupt mask and then enable the interrupt.
2718  *
2719  * @param dev
2720  *  Pointer to struct rte_eth_dev.
2721  * @param on
2722  *  Enable or Disable
2723  *
2724  * @return
2725  *  - On success, zero.
2726  *  - On failure, a negative value.
2727  */
2728 static int
2729 eth_igb_lsc_interrupt_setup(struct rte_eth_dev *dev, uint8_t on)
2730 {
2731         struct e1000_interrupt *intr =
2732                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2733
2734         if (on)
2735                 intr->mask |= E1000_ICR_LSC;
2736         else
2737                 intr->mask &= ~E1000_ICR_LSC;
2738
2739         return 0;
2740 }
2741
2742 /* It clears the interrupt causes and enables the interrupt.
2743  * It will be called once only during nic initialized.
2744  *
2745  * @param dev
2746  *  Pointer to struct rte_eth_dev.
2747  *
2748  * @return
2749  *  - On success, zero.
2750  *  - On failure, a negative value.
2751  */
2752 static int eth_igb_rxq_interrupt_setup(struct rte_eth_dev *dev)
2753 {
2754         uint32_t mask, regval;
2755         struct e1000_hw *hw =
2756                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2757         struct rte_eth_dev_info dev_info;
2758
2759         memset(&dev_info, 0, sizeof(dev_info));
2760         eth_igb_infos_get(dev, &dev_info);
2761
2762         mask = 0xFFFFFFFF >> (32 - dev_info.max_rx_queues);
2763         regval = E1000_READ_REG(hw, E1000_EIMS);
2764         E1000_WRITE_REG(hw, E1000_EIMS, regval | mask);
2765
2766         return 0;
2767 }
2768
2769 /*
2770  * It reads ICR and gets interrupt causes, check it and set a bit flag
2771  * to update link status.
2772  *
2773  * @param dev
2774  *  Pointer to struct rte_eth_dev.
2775  *
2776  * @return
2777  *  - On success, zero.
2778  *  - On failure, a negative value.
2779  */
2780 static int
2781 eth_igb_interrupt_get_status(struct rte_eth_dev *dev)
2782 {
2783         uint32_t icr;
2784         struct e1000_hw *hw =
2785                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2786         struct e1000_interrupt *intr =
2787                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2788
2789         igb_intr_disable(hw);
2790
2791         /* read-on-clear nic registers here */
2792         icr = E1000_READ_REG(hw, E1000_ICR);
2793
2794         intr->flags = 0;
2795         if (icr & E1000_ICR_LSC) {
2796                 intr->flags |= E1000_FLAG_NEED_LINK_UPDATE;
2797         }
2798
2799         if (icr & E1000_ICR_VMMB)
2800                 intr->flags |= E1000_FLAG_MAILBOX;
2801
2802         return 0;
2803 }
2804
2805 /*
2806  * It executes link_update after knowing an interrupt is prsent.
2807  *
2808  * @param dev
2809  *  Pointer to struct rte_eth_dev.
2810  *
2811  * @return
2812  *  - On success, zero.
2813  *  - On failure, a negative value.
2814  */
2815 static int
2816 eth_igb_interrupt_action(struct rte_eth_dev *dev,
2817                          struct rte_intr_handle *intr_handle)
2818 {
2819         struct e1000_hw *hw =
2820                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2821         struct e1000_interrupt *intr =
2822                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2823         struct rte_pci_device *pci_dev = E1000_DEV_TO_PCI(dev);
2824         uint32_t tctl, rctl;
2825         struct rte_eth_link link;
2826         int ret;
2827
2828         if (intr->flags & E1000_FLAG_MAILBOX) {
2829                 igb_pf_mbx_process(dev);
2830                 intr->flags &= ~E1000_FLAG_MAILBOX;
2831         }
2832
2833         igb_intr_enable(dev);
2834         rte_intr_enable(intr_handle);
2835
2836         if (intr->flags & E1000_FLAG_NEED_LINK_UPDATE) {
2837                 intr->flags &= ~E1000_FLAG_NEED_LINK_UPDATE;
2838
2839                 /* set get_link_status to check register later */
2840                 hw->mac.get_link_status = 1;
2841                 ret = eth_igb_link_update(dev, 0);
2842
2843                 /* check if link has changed */
2844                 if (ret < 0)
2845                         return 0;
2846
2847                 memset(&link, 0, sizeof(link));
2848                 rte_igb_dev_atomic_read_link_status(dev, &link);
2849                 if (link.link_status) {
2850                         PMD_INIT_LOG(INFO,
2851                                      " Port %d: Link Up - speed %u Mbps - %s",
2852                                      dev->data->port_id,
2853                                      (unsigned)link.link_speed,
2854                                      link.link_duplex == ETH_LINK_FULL_DUPLEX ?
2855                                      "full-duplex" : "half-duplex");
2856                 } else {
2857                         PMD_INIT_LOG(INFO, " Port %d: Link Down",
2858                                      dev->data->port_id);
2859                 }
2860
2861                 PMD_INIT_LOG(DEBUG, "PCI Address: %04d:%02d:%02d:%d",
2862                              pci_dev->addr.domain,
2863                              pci_dev->addr.bus,
2864                              pci_dev->addr.devid,
2865                              pci_dev->addr.function);
2866                 tctl = E1000_READ_REG(hw, E1000_TCTL);
2867                 rctl = E1000_READ_REG(hw, E1000_RCTL);
2868                 if (link.link_status) {
2869                         /* enable Tx/Rx */
2870                         tctl |= E1000_TCTL_EN;
2871                         rctl |= E1000_RCTL_EN;
2872                 } else {
2873                         /* disable Tx/Rx */
2874                         tctl &= ~E1000_TCTL_EN;
2875                         rctl &= ~E1000_RCTL_EN;
2876                 }
2877                 E1000_WRITE_REG(hw, E1000_TCTL, tctl);
2878                 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2879                 E1000_WRITE_FLUSH(hw);
2880                 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC, NULL);
2881         }
2882
2883         return 0;
2884 }
2885
2886 /**
2887  * Interrupt handler which shall be registered at first.
2888  *
2889  * @param handle
2890  *  Pointer to interrupt handle.
2891  * @param param
2892  *  The address of parameter (struct rte_eth_dev *) regsitered before.
2893  *
2894  * @return
2895  *  void
2896  */
2897 static void
2898 eth_igb_interrupt_handler(void *param)
2899 {
2900         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
2901
2902         eth_igb_interrupt_get_status(dev);
2903         eth_igb_interrupt_action(dev, dev->intr_handle);
2904 }
2905
2906 static int
2907 eth_igbvf_interrupt_get_status(struct rte_eth_dev *dev)
2908 {
2909         uint32_t eicr;
2910         struct e1000_hw *hw =
2911                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2912         struct e1000_interrupt *intr =
2913                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2914
2915         igbvf_intr_disable(hw);
2916
2917         /* read-on-clear nic registers here */
2918         eicr = E1000_READ_REG(hw, E1000_EICR);
2919         intr->flags = 0;
2920
2921         if (eicr == E1000_VTIVAR_MISC_MAILBOX)
2922                 intr->flags |= E1000_FLAG_MAILBOX;
2923
2924         return 0;
2925 }
2926
2927 void igbvf_mbx_process(struct rte_eth_dev *dev)
2928 {
2929         struct e1000_hw *hw =
2930                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2931         struct e1000_mbx_info *mbx = &hw->mbx;
2932         u32 in_msg = 0;
2933
2934         if (mbx->ops.read(hw, &in_msg, 1, 0))
2935                 return;
2936
2937         /* PF reset VF event */
2938         if (in_msg == E1000_PF_CONTROL_MSG)
2939                 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_RESET, NULL);
2940 }
2941
2942 static int
2943 eth_igbvf_interrupt_action(struct rte_eth_dev *dev, struct rte_intr_handle *intr_handle)
2944 {
2945         struct e1000_interrupt *intr =
2946                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2947
2948         if (intr->flags & E1000_FLAG_MAILBOX) {
2949                 igbvf_mbx_process(dev);
2950                 intr->flags &= ~E1000_FLAG_MAILBOX;
2951         }
2952
2953         igbvf_intr_enable(dev);
2954         rte_intr_enable(intr_handle);
2955
2956         return 0;
2957 }
2958
2959 static void
2960 eth_igbvf_interrupt_handler(void *param)
2961 {
2962         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
2963
2964         eth_igbvf_interrupt_get_status(dev);
2965         eth_igbvf_interrupt_action(dev, dev->intr_handle);
2966 }
2967
2968 static int
2969 eth_igb_led_on(struct rte_eth_dev *dev)
2970 {
2971         struct e1000_hw *hw;
2972
2973         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2974         return e1000_led_on(hw) == E1000_SUCCESS ? 0 : -ENOTSUP;
2975 }
2976
2977 static int
2978 eth_igb_led_off(struct rte_eth_dev *dev)
2979 {
2980         struct e1000_hw *hw;
2981
2982         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2983         return e1000_led_off(hw) == E1000_SUCCESS ? 0 : -ENOTSUP;
2984 }
2985
2986 static int
2987 eth_igb_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
2988 {
2989         struct e1000_hw *hw;
2990         uint32_t ctrl;
2991         int tx_pause;
2992         int rx_pause;
2993
2994         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2995         fc_conf->pause_time = hw->fc.pause_time;
2996         fc_conf->high_water = hw->fc.high_water;
2997         fc_conf->low_water = hw->fc.low_water;
2998         fc_conf->send_xon = hw->fc.send_xon;
2999         fc_conf->autoneg = hw->mac.autoneg;
3000
3001         /*
3002          * Return rx_pause and tx_pause status according to actual setting of
3003          * the TFCE and RFCE bits in the CTRL register.
3004          */
3005         ctrl = E1000_READ_REG(hw, E1000_CTRL);
3006         if (ctrl & E1000_CTRL_TFCE)
3007                 tx_pause = 1;
3008         else
3009                 tx_pause = 0;
3010
3011         if (ctrl & E1000_CTRL_RFCE)
3012                 rx_pause = 1;
3013         else
3014                 rx_pause = 0;
3015
3016         if (rx_pause && tx_pause)
3017                 fc_conf->mode = RTE_FC_FULL;
3018         else if (rx_pause)
3019                 fc_conf->mode = RTE_FC_RX_PAUSE;
3020         else if (tx_pause)
3021                 fc_conf->mode = RTE_FC_TX_PAUSE;
3022         else
3023                 fc_conf->mode = RTE_FC_NONE;
3024
3025         return 0;
3026 }
3027
3028 static int
3029 eth_igb_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3030 {
3031         struct e1000_hw *hw;
3032         int err;
3033         enum e1000_fc_mode rte_fcmode_2_e1000_fcmode[] = {
3034                 e1000_fc_none,
3035                 e1000_fc_rx_pause,
3036                 e1000_fc_tx_pause,
3037                 e1000_fc_full
3038         };
3039         uint32_t rx_buf_size;
3040         uint32_t max_high_water;
3041         uint32_t rctl;
3042
3043         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3044         if (fc_conf->autoneg != hw->mac.autoneg)
3045                 return -ENOTSUP;
3046         rx_buf_size = igb_get_rx_buffer_size(hw);
3047         PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
3048
3049         /* At least reserve one Ethernet frame for watermark */
3050         max_high_water = rx_buf_size - ETHER_MAX_LEN;
3051         if ((fc_conf->high_water > max_high_water) ||
3052             (fc_conf->high_water < fc_conf->low_water)) {
3053                 PMD_INIT_LOG(ERR, "e1000 incorrect high/low water value");
3054                 PMD_INIT_LOG(ERR, "high water must <=  0x%x", max_high_water);
3055                 return -EINVAL;
3056         }
3057
3058         hw->fc.requested_mode = rte_fcmode_2_e1000_fcmode[fc_conf->mode];
3059         hw->fc.pause_time     = fc_conf->pause_time;
3060         hw->fc.high_water     = fc_conf->high_water;
3061         hw->fc.low_water      = fc_conf->low_water;
3062         hw->fc.send_xon       = fc_conf->send_xon;
3063
3064         err = e1000_setup_link_generic(hw);
3065         if (err == E1000_SUCCESS) {
3066
3067                 /* check if we want to forward MAC frames - driver doesn't have native
3068                  * capability to do that, so we'll write the registers ourselves */
3069
3070                 rctl = E1000_READ_REG(hw, E1000_RCTL);
3071
3072                 /* set or clear MFLCN.PMCF bit depending on configuration */
3073                 if (fc_conf->mac_ctrl_frame_fwd != 0)
3074                         rctl |= E1000_RCTL_PMCF;
3075                 else
3076                         rctl &= ~E1000_RCTL_PMCF;
3077
3078                 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
3079                 E1000_WRITE_FLUSH(hw);
3080
3081                 return 0;
3082         }
3083
3084         PMD_INIT_LOG(ERR, "e1000_setup_link_generic = 0x%x", err);
3085         return -EIO;
3086 }
3087
3088 #define E1000_RAH_POOLSEL_SHIFT      (18)
3089 static int
3090 eth_igb_rar_set(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
3091                 uint32_t index, __rte_unused uint32_t pool)
3092 {
3093         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3094         uint32_t rah;
3095
3096         e1000_rar_set(hw, mac_addr->addr_bytes, index);
3097         rah = E1000_READ_REG(hw, E1000_RAH(index));
3098         rah |= (0x1 << (E1000_RAH_POOLSEL_SHIFT + pool));
3099         E1000_WRITE_REG(hw, E1000_RAH(index), rah);
3100         return 0;
3101 }
3102
3103 static void
3104 eth_igb_rar_clear(struct rte_eth_dev *dev, uint32_t index)
3105 {
3106         uint8_t addr[ETHER_ADDR_LEN];
3107         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3108
3109         memset(addr, 0, sizeof(addr));
3110
3111         e1000_rar_set(hw, addr, index);
3112 }
3113
3114 static void
3115 eth_igb_default_mac_addr_set(struct rte_eth_dev *dev,
3116                                 struct ether_addr *addr)
3117 {
3118         eth_igb_rar_clear(dev, 0);
3119
3120         eth_igb_rar_set(dev, (void *)addr, 0, 0);
3121 }
3122 /*
3123  * Virtual Function operations
3124  */
3125 static void
3126 igbvf_intr_disable(struct e1000_hw *hw)
3127 {
3128         PMD_INIT_FUNC_TRACE();
3129
3130         /* Clear interrupt mask to stop from interrupts being generated */
3131         E1000_WRITE_REG(hw, E1000_EIMC, 0xFFFF);
3132
3133         E1000_WRITE_FLUSH(hw);
3134 }
3135
3136 static void
3137 igbvf_stop_adapter(struct rte_eth_dev *dev)
3138 {
3139         u32 reg_val;
3140         u16 i;
3141         struct rte_eth_dev_info dev_info;
3142         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3143
3144         memset(&dev_info, 0, sizeof(dev_info));
3145         eth_igbvf_infos_get(dev, &dev_info);
3146
3147         /* Clear interrupt mask to stop from interrupts being generated */
3148         igbvf_intr_disable(hw);
3149
3150         /* Clear any pending interrupts, flush previous writes */
3151         E1000_READ_REG(hw, E1000_EICR);
3152
3153         /* Disable the transmit unit.  Each queue must be disabled. */
3154         for (i = 0; i < dev_info.max_tx_queues; i++)
3155                 E1000_WRITE_REG(hw, E1000_TXDCTL(i), E1000_TXDCTL_SWFLSH);
3156
3157         /* Disable the receive unit by stopping each queue */
3158         for (i = 0; i < dev_info.max_rx_queues; i++) {
3159                 reg_val = E1000_READ_REG(hw, E1000_RXDCTL(i));
3160                 reg_val &= ~E1000_RXDCTL_QUEUE_ENABLE;
3161                 E1000_WRITE_REG(hw, E1000_RXDCTL(i), reg_val);
3162                 while (E1000_READ_REG(hw, E1000_RXDCTL(i)) & E1000_RXDCTL_QUEUE_ENABLE)
3163                         ;
3164         }
3165
3166         /* flush all queues disables */
3167         E1000_WRITE_FLUSH(hw);
3168         msec_delay(2);
3169 }
3170
3171 static int eth_igbvf_link_update(struct e1000_hw *hw)
3172 {
3173         struct e1000_mbx_info *mbx = &hw->mbx;
3174         struct e1000_mac_info *mac = &hw->mac;
3175         int ret_val = E1000_SUCCESS;
3176
3177         PMD_INIT_LOG(DEBUG, "e1000_check_for_link_vf");
3178
3179         /*
3180          * We only want to run this if there has been a rst asserted.
3181          * in this case that could mean a link change, device reset,
3182          * or a virtual function reset
3183          */
3184
3185         /* If we were hit with a reset or timeout drop the link */
3186         if (!e1000_check_for_rst(hw, 0) || !mbx->timeout)
3187                 mac->get_link_status = TRUE;
3188
3189         if (!mac->get_link_status)
3190                 goto out;
3191
3192         /* if link status is down no point in checking to see if pf is up */
3193         if (!(E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU))
3194                 goto out;
3195
3196         /* if we passed all the tests above then the link is up and we no
3197          * longer need to check for link */
3198         mac->get_link_status = FALSE;
3199
3200 out:
3201         return ret_val;
3202 }
3203
3204
3205 static int
3206 igbvf_dev_configure(struct rte_eth_dev *dev)
3207 {
3208         struct rte_eth_conf* conf = &dev->data->dev_conf;
3209
3210         PMD_INIT_LOG(DEBUG, "Configured Virtual Function port id: %d",
3211                      dev->data->port_id);
3212
3213         /*
3214          * VF has no ability to enable/disable HW CRC
3215          * Keep the persistent behavior the same as Host PF
3216          */
3217 #ifndef RTE_LIBRTE_E1000_PF_DISABLE_STRIP_CRC
3218         if (!conf->rxmode.hw_strip_crc) {
3219                 PMD_INIT_LOG(NOTICE, "VF can't disable HW CRC Strip");
3220                 conf->rxmode.hw_strip_crc = 1;
3221         }
3222 #else
3223         if (conf->rxmode.hw_strip_crc) {
3224                 PMD_INIT_LOG(NOTICE, "VF can't enable HW CRC Strip");
3225                 conf->rxmode.hw_strip_crc = 0;
3226         }
3227 #endif
3228
3229         return 0;
3230 }
3231
3232 static int
3233 igbvf_dev_start(struct rte_eth_dev *dev)
3234 {
3235         struct e1000_hw *hw =
3236                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3237         struct e1000_adapter *adapter =
3238                 E1000_DEV_PRIVATE(dev->data->dev_private);
3239         struct rte_pci_device *pci_dev = E1000_DEV_TO_PCI(dev);
3240         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
3241         int ret;
3242         uint32_t intr_vector = 0;
3243
3244         PMD_INIT_FUNC_TRACE();
3245
3246         hw->mac.ops.reset_hw(hw);
3247         adapter->stopped = 0;
3248
3249         /* Set all vfta */
3250         igbvf_set_vfta_all(dev,1);
3251
3252         eth_igbvf_tx_init(dev);
3253
3254         /* This can fail when allocating mbufs for descriptor rings */
3255         ret = eth_igbvf_rx_init(dev);
3256         if (ret) {
3257                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
3258                 igb_dev_clear_queues(dev);
3259                 return ret;
3260         }
3261
3262         /* check and configure queue intr-vector mapping */
3263         if (dev->data->dev_conf.intr_conf.rxq != 0) {
3264                 intr_vector = dev->data->nb_rx_queues;
3265                 ret = rte_intr_efd_enable(intr_handle, intr_vector);
3266                 if (ret)
3267                         return ret;
3268         }
3269
3270         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
3271                 intr_handle->intr_vec =
3272                         rte_zmalloc("intr_vec",
3273                                     dev->data->nb_rx_queues * sizeof(int), 0);
3274                 if (!intr_handle->intr_vec) {
3275                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
3276                                      " intr_vec", dev->data->nb_rx_queues);
3277                         return -ENOMEM;
3278                 }
3279         }
3280
3281         eth_igbvf_configure_msix_intr(dev);
3282
3283         /* enable uio/vfio intr/eventfd mapping */
3284         rte_intr_enable(intr_handle);
3285
3286         /* resume enabled intr since hw reset */
3287         igbvf_intr_enable(dev);
3288
3289         return 0;
3290 }
3291
3292 static void
3293 igbvf_dev_stop(struct rte_eth_dev *dev)
3294 {
3295         struct rte_pci_device *pci_dev = E1000_DEV_TO_PCI(dev);
3296         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
3297
3298         PMD_INIT_FUNC_TRACE();
3299
3300         igbvf_stop_adapter(dev);
3301
3302         /*
3303           * Clear what we set, but we still keep shadow_vfta to
3304           * restore after device starts
3305           */
3306         igbvf_set_vfta_all(dev,0);
3307
3308         igb_dev_clear_queues(dev);
3309
3310         /* disable intr eventfd mapping */
3311         rte_intr_disable(intr_handle);
3312
3313         /* Clean datapath event and queue/vec mapping */
3314         rte_intr_efd_disable(intr_handle);
3315         if (intr_handle->intr_vec) {
3316                 rte_free(intr_handle->intr_vec);
3317                 intr_handle->intr_vec = NULL;
3318         }
3319 }
3320
3321 static void
3322 igbvf_dev_close(struct rte_eth_dev *dev)
3323 {
3324         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3325         struct e1000_adapter *adapter =
3326                 E1000_DEV_PRIVATE(dev->data->dev_private);
3327         struct ether_addr addr;
3328
3329         PMD_INIT_FUNC_TRACE();
3330
3331         e1000_reset_hw(hw);
3332
3333         igbvf_dev_stop(dev);
3334         adapter->stopped = 1;
3335         igb_dev_free_queues(dev);
3336
3337         /**
3338          * reprogram the RAR with a zero mac address,
3339          * to ensure that the VF traffic goes to the PF
3340          * after stop, close and detach of the VF.
3341          **/
3342
3343         memset(&addr, 0, sizeof(addr));
3344         igbvf_default_mac_addr_set(dev, &addr);
3345 }
3346
3347 static void
3348 igbvf_promiscuous_enable(struct rte_eth_dev *dev)
3349 {
3350         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3351
3352         /* Set both unicast and multicast promisc */
3353         e1000_promisc_set_vf(hw, e1000_promisc_enabled);
3354 }
3355
3356 static void
3357 igbvf_promiscuous_disable(struct rte_eth_dev *dev)
3358 {
3359         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3360
3361         /* If in allmulticast mode leave multicast promisc */
3362         if (dev->data->all_multicast == 1)
3363                 e1000_promisc_set_vf(hw, e1000_promisc_multicast);
3364         else
3365                 e1000_promisc_set_vf(hw, e1000_promisc_disabled);
3366 }
3367
3368 static void
3369 igbvf_allmulticast_enable(struct rte_eth_dev *dev)
3370 {
3371         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3372
3373         /* In promiscuous mode multicast promisc already set */
3374         if (dev->data->promiscuous == 0)
3375                 e1000_promisc_set_vf(hw, e1000_promisc_multicast);
3376 }
3377
3378 static void
3379 igbvf_allmulticast_disable(struct rte_eth_dev *dev)
3380 {
3381         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3382
3383         /* In promiscuous mode leave multicast promisc enabled */
3384         if (dev->data->promiscuous == 0)
3385                 e1000_promisc_set_vf(hw, e1000_promisc_disabled);
3386 }
3387
3388 static int igbvf_set_vfta(struct e1000_hw *hw, uint16_t vid, bool on)
3389 {
3390         struct e1000_mbx_info *mbx = &hw->mbx;
3391         uint32_t msgbuf[2];
3392         s32 err;
3393
3394         /* After set vlan, vlan strip will also be enabled in igb driver*/
3395         msgbuf[0] = E1000_VF_SET_VLAN;
3396         msgbuf[1] = vid;
3397         /* Setting the 8 bit field MSG INFO to TRUE indicates "add" */
3398         if (on)
3399                 msgbuf[0] |= E1000_VF_SET_VLAN_ADD;
3400
3401         err = mbx->ops.write_posted(hw, msgbuf, 2, 0);
3402         if (err)
3403                 goto mbx_err;
3404
3405         err = mbx->ops.read_posted(hw, msgbuf, 2, 0);
3406         if (err)
3407                 goto mbx_err;
3408
3409         msgbuf[0] &= ~E1000_VT_MSGTYPE_CTS;
3410         if (msgbuf[0] == (E1000_VF_SET_VLAN | E1000_VT_MSGTYPE_NACK))
3411                 err = -EINVAL;
3412
3413 mbx_err:
3414         return err;
3415 }
3416
3417 static void igbvf_set_vfta_all(struct rte_eth_dev *dev, bool on)
3418 {
3419         struct e1000_hw *hw =
3420                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3421         struct e1000_vfta * shadow_vfta =
3422                 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
3423         int i = 0, j = 0, vfta = 0, mask = 1;
3424
3425         for (i = 0; i < IGB_VFTA_SIZE; i++){
3426                 vfta = shadow_vfta->vfta[i];
3427                 if(vfta){
3428                         mask = 1;
3429                         for (j = 0; j < 32; j++){
3430                                 if(vfta & mask)
3431                                         igbvf_set_vfta(hw,
3432                                                 (uint16_t)((i<<5)+j), on);
3433                                 mask<<=1;
3434                         }
3435                 }
3436         }
3437
3438 }
3439
3440 static int
3441 igbvf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
3442 {
3443         struct e1000_hw *hw =
3444                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3445         struct e1000_vfta * shadow_vfta =
3446                 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
3447         uint32_t vid_idx = 0;
3448         uint32_t vid_bit = 0;
3449         int ret = 0;
3450
3451         PMD_INIT_FUNC_TRACE();
3452
3453         /*vind is not used in VF driver, set to 0, check ixgbe_set_vfta_vf*/
3454         ret = igbvf_set_vfta(hw, vlan_id, !!on);
3455         if(ret){
3456                 PMD_INIT_LOG(ERR, "Unable to set VF vlan");
3457                 return ret;
3458         }
3459         vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
3460         vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
3461
3462         /*Save what we set and retore it after device reset*/
3463         if (on)
3464                 shadow_vfta->vfta[vid_idx] |= vid_bit;
3465         else
3466                 shadow_vfta->vfta[vid_idx] &= ~vid_bit;
3467
3468         return 0;
3469 }
3470
3471 static void
3472 igbvf_default_mac_addr_set(struct rte_eth_dev *dev, struct ether_addr *addr)
3473 {
3474         struct e1000_hw *hw =
3475                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3476
3477         /* index is not used by rar_set() */
3478         hw->mac.ops.rar_set(hw, (void *)addr, 0);
3479 }
3480
3481
3482 static int
3483 eth_igb_rss_reta_update(struct rte_eth_dev *dev,
3484                         struct rte_eth_rss_reta_entry64 *reta_conf,
3485                         uint16_t reta_size)
3486 {
3487         uint8_t i, j, mask;
3488         uint32_t reta, r;
3489         uint16_t idx, shift;
3490         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3491
3492         if (reta_size != ETH_RSS_RETA_SIZE_128) {
3493                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
3494                         "(%d) doesn't match the number hardware can supported "
3495                         "(%d)", reta_size, ETH_RSS_RETA_SIZE_128);
3496                 return -EINVAL;
3497         }
3498
3499         for (i = 0; i < reta_size; i += IGB_4_BIT_WIDTH) {
3500                 idx = i / RTE_RETA_GROUP_SIZE;
3501                 shift = i % RTE_RETA_GROUP_SIZE;
3502                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
3503                                                 IGB_4_BIT_MASK);
3504                 if (!mask)
3505                         continue;
3506                 if (mask == IGB_4_BIT_MASK)
3507                         r = 0;
3508                 else
3509                         r = E1000_READ_REG(hw, E1000_RETA(i >> 2));
3510                 for (j = 0, reta = 0; j < IGB_4_BIT_WIDTH; j++) {
3511                         if (mask & (0x1 << j))
3512                                 reta |= reta_conf[idx].reta[shift + j] <<
3513                                                         (CHAR_BIT * j);
3514                         else
3515                                 reta |= r & (IGB_8_BIT_MASK << (CHAR_BIT * j));
3516                 }
3517                 E1000_WRITE_REG(hw, E1000_RETA(i >> 2), reta);
3518         }
3519
3520         return 0;
3521 }
3522
3523 static int
3524 eth_igb_rss_reta_query(struct rte_eth_dev *dev,
3525                        struct rte_eth_rss_reta_entry64 *reta_conf,
3526                        uint16_t reta_size)
3527 {
3528         uint8_t i, j, mask;
3529         uint32_t reta;
3530         uint16_t idx, shift;
3531         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3532
3533         if (reta_size != ETH_RSS_RETA_SIZE_128) {
3534                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
3535                         "(%d) doesn't match the number hardware can supported "
3536                         "(%d)", reta_size, ETH_RSS_RETA_SIZE_128);
3537                 return -EINVAL;
3538         }
3539
3540         for (i = 0; i < reta_size; i += IGB_4_BIT_WIDTH) {
3541                 idx = i / RTE_RETA_GROUP_SIZE;
3542                 shift = i % RTE_RETA_GROUP_SIZE;
3543                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
3544                                                 IGB_4_BIT_MASK);
3545                 if (!mask)
3546                         continue;
3547                 reta = E1000_READ_REG(hw, E1000_RETA(i >> 2));
3548                 for (j = 0; j < IGB_4_BIT_WIDTH; j++) {
3549                         if (mask & (0x1 << j))
3550                                 reta_conf[idx].reta[shift + j] =
3551                                         ((reta >> (CHAR_BIT * j)) &
3552                                                 IGB_8_BIT_MASK);
3553                 }
3554         }
3555
3556         return 0;
3557 }
3558
3559 #define MAC_TYPE_FILTER_SUP(type)    do {\
3560         if ((type) != e1000_82580 && (type) != e1000_i350 &&\
3561                 (type) != e1000_82576)\
3562                 return -ENOTSUP;\
3563 } while (0)
3564
3565 static int
3566 eth_igb_syn_filter_set(struct rte_eth_dev *dev,
3567                         struct rte_eth_syn_filter *filter,
3568                         bool add)
3569 {
3570         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3571         uint32_t synqf, rfctl;
3572
3573         if (filter->queue >= IGB_MAX_RX_QUEUE_NUM)
3574                 return -EINVAL;
3575
3576         synqf = E1000_READ_REG(hw, E1000_SYNQF(0));
3577
3578         if (add) {
3579                 if (synqf & E1000_SYN_FILTER_ENABLE)
3580                         return -EINVAL;
3581
3582                 synqf = (uint32_t)(((filter->queue << E1000_SYN_FILTER_QUEUE_SHIFT) &
3583                         E1000_SYN_FILTER_QUEUE) | E1000_SYN_FILTER_ENABLE);
3584
3585                 rfctl = E1000_READ_REG(hw, E1000_RFCTL);
3586                 if (filter->hig_pri)
3587                         rfctl |= E1000_RFCTL_SYNQFP;
3588                 else
3589                         rfctl &= ~E1000_RFCTL_SYNQFP;
3590
3591                 E1000_WRITE_REG(hw, E1000_RFCTL, rfctl);
3592         } else {
3593                 if (!(synqf & E1000_SYN_FILTER_ENABLE))
3594                         return -ENOENT;
3595                 synqf = 0;
3596         }
3597
3598         E1000_WRITE_REG(hw, E1000_SYNQF(0), synqf);
3599         E1000_WRITE_FLUSH(hw);
3600         return 0;
3601 }
3602
3603 static int
3604 eth_igb_syn_filter_get(struct rte_eth_dev *dev,
3605                         struct rte_eth_syn_filter *filter)
3606 {
3607         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3608         uint32_t synqf, rfctl;
3609
3610         synqf = E1000_READ_REG(hw, E1000_SYNQF(0));
3611         if (synqf & E1000_SYN_FILTER_ENABLE) {
3612                 rfctl = E1000_READ_REG(hw, E1000_RFCTL);
3613                 filter->hig_pri = (rfctl & E1000_RFCTL_SYNQFP) ? 1 : 0;
3614                 filter->queue = (uint8_t)((synqf & E1000_SYN_FILTER_QUEUE) >>
3615                                 E1000_SYN_FILTER_QUEUE_SHIFT);
3616                 return 0;
3617         }
3618
3619         return -ENOENT;
3620 }
3621
3622 static int
3623 eth_igb_syn_filter_handle(struct rte_eth_dev *dev,
3624                         enum rte_filter_op filter_op,
3625                         void *arg)
3626 {
3627         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3628         int ret;
3629
3630         MAC_TYPE_FILTER_SUP(hw->mac.type);
3631
3632         if (filter_op == RTE_ETH_FILTER_NOP)
3633                 return 0;
3634
3635         if (arg == NULL) {
3636                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
3637                             filter_op);
3638                 return -EINVAL;
3639         }
3640
3641         switch (filter_op) {
3642         case RTE_ETH_FILTER_ADD:
3643                 ret = eth_igb_syn_filter_set(dev,
3644                                 (struct rte_eth_syn_filter *)arg,
3645                                 TRUE);
3646                 break;
3647         case RTE_ETH_FILTER_DELETE:
3648                 ret = eth_igb_syn_filter_set(dev,
3649                                 (struct rte_eth_syn_filter *)arg,
3650                                 FALSE);
3651                 break;
3652         case RTE_ETH_FILTER_GET:
3653                 ret = eth_igb_syn_filter_get(dev,
3654                                 (struct rte_eth_syn_filter *)arg);
3655                 break;
3656         default:
3657                 PMD_DRV_LOG(ERR, "unsupported operation %u", filter_op);
3658                 ret = -EINVAL;
3659                 break;
3660         }
3661
3662         return ret;
3663 }
3664
3665 #define MAC_TYPE_FILTER_SUP_EXT(type)    do {\
3666         if ((type) != e1000_82580 && (type) != e1000_i350)\
3667                 return -ENOSYS; \
3668 } while (0)
3669
3670 /* translate elements in struct rte_eth_ntuple_filter to struct e1000_2tuple_filter_info*/
3671 static inline int
3672 ntuple_filter_to_2tuple(struct rte_eth_ntuple_filter *filter,
3673                         struct e1000_2tuple_filter_info *filter_info)
3674 {
3675         if (filter->queue >= IGB_MAX_RX_QUEUE_NUM)
3676                 return -EINVAL;
3677         if (filter->priority > E1000_2TUPLE_MAX_PRI)
3678                 return -EINVAL;  /* filter index is out of range. */
3679         if (filter->tcp_flags > TCP_FLAG_ALL)
3680                 return -EINVAL;  /* flags is invalid. */
3681
3682         switch (filter->dst_port_mask) {
3683         case UINT16_MAX:
3684                 filter_info->dst_port_mask = 0;
3685                 filter_info->dst_port = filter->dst_port;
3686                 break;
3687         case 0:
3688                 filter_info->dst_port_mask = 1;
3689                 break;
3690         default:
3691                 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
3692                 return -EINVAL;
3693         }
3694
3695         switch (filter->proto_mask) {
3696         case UINT8_MAX:
3697                 filter_info->proto_mask = 0;
3698                 filter_info->proto = filter->proto;
3699                 break;
3700         case 0:
3701                 filter_info->proto_mask = 1;
3702                 break;
3703         default:
3704                 PMD_DRV_LOG(ERR, "invalid protocol mask.");
3705                 return -EINVAL;
3706         }
3707
3708         filter_info->priority = (uint8_t)filter->priority;
3709         if (filter->flags & RTE_NTUPLE_FLAGS_TCP_FLAG)
3710                 filter_info->tcp_flags = filter->tcp_flags;
3711         else
3712                 filter_info->tcp_flags = 0;
3713
3714         return 0;
3715 }
3716
3717 static inline struct e1000_2tuple_filter *
3718 igb_2tuple_filter_lookup(struct e1000_2tuple_filter_list *filter_list,
3719                         struct e1000_2tuple_filter_info *key)
3720 {
3721         struct e1000_2tuple_filter *it;
3722
3723         TAILQ_FOREACH(it, filter_list, entries) {
3724                 if (memcmp(key, &it->filter_info,
3725                         sizeof(struct e1000_2tuple_filter_info)) == 0) {
3726                         return it;
3727                 }
3728         }
3729         return NULL;
3730 }
3731
3732 /*
3733  * igb_add_2tuple_filter - add a 2tuple filter
3734  *
3735  * @param
3736  * dev: Pointer to struct rte_eth_dev.
3737  * ntuple_filter: ponter to the filter that will be added.
3738  *
3739  * @return
3740  *    - On success, zero.
3741  *    - On failure, a negative value.
3742  */
3743 static int
3744 igb_add_2tuple_filter(struct rte_eth_dev *dev,
3745                         struct rte_eth_ntuple_filter *ntuple_filter)
3746 {
3747         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3748         struct e1000_filter_info *filter_info =
3749                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3750         struct e1000_2tuple_filter *filter;
3751         uint32_t ttqf = E1000_TTQF_DISABLE_MASK;
3752         uint32_t imir, imir_ext = E1000_IMIREXT_SIZE_BP;
3753         int i, ret;
3754
3755         filter = rte_zmalloc("e1000_2tuple_filter",
3756                         sizeof(struct e1000_2tuple_filter), 0);
3757         if (filter == NULL)
3758                 return -ENOMEM;
3759
3760         ret = ntuple_filter_to_2tuple(ntuple_filter,
3761                                       &filter->filter_info);
3762         if (ret < 0) {
3763                 rte_free(filter);
3764                 return ret;
3765         }
3766         if (igb_2tuple_filter_lookup(&filter_info->twotuple_list,
3767                                          &filter->filter_info) != NULL) {
3768                 PMD_DRV_LOG(ERR, "filter exists.");
3769                 rte_free(filter);
3770                 return -EEXIST;
3771         }
3772         filter->queue = ntuple_filter->queue;
3773
3774         /*
3775          * look for an unused 2tuple filter index,
3776          * and insert the filter to list.
3777          */
3778         for (i = 0; i < E1000_MAX_TTQF_FILTERS; i++) {
3779                 if (!(filter_info->twotuple_mask & (1 << i))) {
3780                         filter_info->twotuple_mask |= 1 << i;
3781                         filter->index = i;
3782                         TAILQ_INSERT_TAIL(&filter_info->twotuple_list,
3783                                           filter,
3784                                           entries);
3785                         break;
3786                 }
3787         }
3788         if (i >= E1000_MAX_TTQF_FILTERS) {
3789                 PMD_DRV_LOG(ERR, "2tuple filters are full.");
3790                 rte_free(filter);
3791                 return -ENOSYS;
3792         }
3793
3794         imir = (uint32_t)(filter->filter_info.dst_port & E1000_IMIR_DSTPORT);
3795         if (filter->filter_info.dst_port_mask == 1) /* 1b means not compare. */
3796                 imir |= E1000_IMIR_PORT_BP;
3797         else
3798                 imir &= ~E1000_IMIR_PORT_BP;
3799
3800         imir |= filter->filter_info.priority << E1000_IMIR_PRIORITY_SHIFT;
3801
3802         ttqf |= E1000_TTQF_QUEUE_ENABLE;
3803         ttqf |= (uint32_t)(filter->queue << E1000_TTQF_QUEUE_SHIFT);
3804         ttqf |= (uint32_t)(filter->filter_info.proto & E1000_TTQF_PROTOCOL_MASK);
3805         if (filter->filter_info.proto_mask == 0)
3806                 ttqf &= ~E1000_TTQF_MASK_ENABLE;
3807
3808         /* tcp flags bits setting. */
3809         if (filter->filter_info.tcp_flags & TCP_FLAG_ALL) {
3810                 if (filter->filter_info.tcp_flags & TCP_URG_FLAG)
3811                         imir_ext |= E1000_IMIREXT_CTRL_URG;
3812                 if (filter->filter_info.tcp_flags & TCP_ACK_FLAG)
3813                         imir_ext |= E1000_IMIREXT_CTRL_ACK;
3814                 if (filter->filter_info.tcp_flags & TCP_PSH_FLAG)
3815                         imir_ext |= E1000_IMIREXT_CTRL_PSH;
3816                 if (filter->filter_info.tcp_flags & TCP_RST_FLAG)
3817                         imir_ext |= E1000_IMIREXT_CTRL_RST;
3818                 if (filter->filter_info.tcp_flags & TCP_SYN_FLAG)
3819                         imir_ext |= E1000_IMIREXT_CTRL_SYN;
3820                 if (filter->filter_info.tcp_flags & TCP_FIN_FLAG)
3821                         imir_ext |= E1000_IMIREXT_CTRL_FIN;
3822         } else
3823                 imir_ext |= E1000_IMIREXT_CTRL_BP;
3824         E1000_WRITE_REG(hw, E1000_IMIR(i), imir);
3825         E1000_WRITE_REG(hw, E1000_TTQF(i), ttqf);
3826         E1000_WRITE_REG(hw, E1000_IMIREXT(i), imir_ext);
3827         return 0;
3828 }
3829
3830 /*
3831  * igb_remove_2tuple_filter - remove a 2tuple filter
3832  *
3833  * @param
3834  * dev: Pointer to struct rte_eth_dev.
3835  * ntuple_filter: ponter to the filter that will be removed.
3836  *
3837  * @return
3838  *    - On success, zero.
3839  *    - On failure, a negative value.
3840  */
3841 static int
3842 igb_remove_2tuple_filter(struct rte_eth_dev *dev,
3843                         struct rte_eth_ntuple_filter *ntuple_filter)
3844 {
3845         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3846         struct e1000_filter_info *filter_info =
3847                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3848         struct e1000_2tuple_filter_info filter_2tuple;
3849         struct e1000_2tuple_filter *filter;
3850         int ret;
3851
3852         memset(&filter_2tuple, 0, sizeof(struct e1000_2tuple_filter_info));
3853         ret = ntuple_filter_to_2tuple(ntuple_filter,
3854                                       &filter_2tuple);
3855         if (ret < 0)
3856                 return ret;
3857
3858         filter = igb_2tuple_filter_lookup(&filter_info->twotuple_list,
3859                                          &filter_2tuple);
3860         if (filter == NULL) {
3861                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
3862                 return -ENOENT;
3863         }
3864
3865         filter_info->twotuple_mask &= ~(1 << filter->index);
3866         TAILQ_REMOVE(&filter_info->twotuple_list, filter, entries);
3867         rte_free(filter);
3868
3869         E1000_WRITE_REG(hw, E1000_TTQF(filter->index), E1000_TTQF_DISABLE_MASK);
3870         E1000_WRITE_REG(hw, E1000_IMIR(filter->index), 0);
3871         E1000_WRITE_REG(hw, E1000_IMIREXT(filter->index), 0);
3872         return 0;
3873 }
3874
3875 static inline struct e1000_flex_filter *
3876 eth_igb_flex_filter_lookup(struct e1000_flex_filter_list *filter_list,
3877                         struct e1000_flex_filter_info *key)
3878 {
3879         struct e1000_flex_filter *it;
3880
3881         TAILQ_FOREACH(it, filter_list, entries) {
3882                 if (memcmp(key, &it->filter_info,
3883                         sizeof(struct e1000_flex_filter_info)) == 0)
3884                         return it;
3885         }
3886
3887         return NULL;
3888 }
3889
3890 static int
3891 eth_igb_add_del_flex_filter(struct rte_eth_dev *dev,
3892                         struct rte_eth_flex_filter *filter,
3893                         bool add)
3894 {
3895         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3896         struct e1000_filter_info *filter_info =
3897                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3898         struct e1000_flex_filter *flex_filter, *it;
3899         uint32_t wufc, queueing, mask;
3900         uint32_t reg_off;
3901         uint8_t shift, i, j = 0;
3902
3903         flex_filter = rte_zmalloc("e1000_flex_filter",
3904                         sizeof(struct e1000_flex_filter), 0);
3905         if (flex_filter == NULL)
3906                 return -ENOMEM;
3907
3908         flex_filter->filter_info.len = filter->len;
3909         flex_filter->filter_info.priority = filter->priority;
3910         memcpy(flex_filter->filter_info.dwords, filter->bytes, filter->len);
3911         for (i = 0; i < RTE_ALIGN(filter->len, CHAR_BIT) / CHAR_BIT; i++) {
3912                 mask = 0;
3913                 /* reverse bits in flex filter's mask*/
3914                 for (shift = 0; shift < CHAR_BIT; shift++) {
3915                         if (filter->mask[i] & (0x01 << shift))
3916                                 mask |= (0x80 >> shift);
3917                 }
3918                 flex_filter->filter_info.mask[i] = mask;
3919         }
3920
3921         wufc = E1000_READ_REG(hw, E1000_WUFC);
3922
3923         if (add) {
3924                 if (eth_igb_flex_filter_lookup(&filter_info->flex_list,
3925                                 &flex_filter->filter_info) != NULL) {
3926                         PMD_DRV_LOG(ERR, "filter exists.");
3927                         rte_free(flex_filter);
3928                         return -EEXIST;
3929                 }
3930                 flex_filter->queue = filter->queue;
3931                 /*
3932                  * look for an unused flex filter index
3933                  * and insert the filter into the list.
3934                  */
3935                 for (i = 0; i < E1000_MAX_FLEX_FILTERS; i++) {
3936                         if (!(filter_info->flex_mask & (1 << i))) {
3937                                 filter_info->flex_mask |= 1 << i;
3938                                 flex_filter->index = i;
3939                                 TAILQ_INSERT_TAIL(&filter_info->flex_list,
3940                                         flex_filter,
3941                                         entries);
3942                                 break;
3943                         }
3944                 }
3945                 if (i >= E1000_MAX_FLEX_FILTERS) {
3946                         PMD_DRV_LOG(ERR, "flex filters are full.");
3947                         rte_free(flex_filter);
3948                         return -ENOSYS;
3949                 }
3950
3951                 if (flex_filter->index < E1000_MAX_FHFT)
3952                         reg_off = E1000_FHFT(flex_filter->index);
3953                 else
3954                         reg_off = E1000_FHFT_EXT(flex_filter->index - E1000_MAX_FHFT);
3955
3956                 E1000_WRITE_REG(hw, E1000_WUFC, wufc | E1000_WUFC_FLEX_HQ |
3957                                 (E1000_WUFC_FLX0 << flex_filter->index));
3958                 queueing = filter->len |
3959                         (filter->queue << E1000_FHFT_QUEUEING_QUEUE_SHIFT) |
3960                         (filter->priority << E1000_FHFT_QUEUEING_PRIO_SHIFT);
3961                 E1000_WRITE_REG(hw, reg_off + E1000_FHFT_QUEUEING_OFFSET,
3962                                 queueing);
3963                 for (i = 0; i < E1000_FLEX_FILTERS_MASK_SIZE; i++) {
3964                         E1000_WRITE_REG(hw, reg_off,
3965                                         flex_filter->filter_info.dwords[j]);
3966                         reg_off += sizeof(uint32_t);
3967                         E1000_WRITE_REG(hw, reg_off,
3968                                         flex_filter->filter_info.dwords[++j]);
3969                         reg_off += sizeof(uint32_t);
3970                         E1000_WRITE_REG(hw, reg_off,
3971                                 (uint32_t)flex_filter->filter_info.mask[i]);
3972                         reg_off += sizeof(uint32_t) * 2;
3973                         ++j;
3974                 }
3975         } else {
3976                 it = eth_igb_flex_filter_lookup(&filter_info->flex_list,
3977                                 &flex_filter->filter_info);
3978                 if (it == NULL) {
3979                         PMD_DRV_LOG(ERR, "filter doesn't exist.");
3980                         rte_free(flex_filter);
3981                         return -ENOENT;
3982                 }
3983
3984                 if (it->index < E1000_MAX_FHFT)
3985                         reg_off = E1000_FHFT(it->index);
3986                 else
3987                         reg_off = E1000_FHFT_EXT(it->index - E1000_MAX_FHFT);
3988
3989                 for (i = 0; i < E1000_FHFT_SIZE_IN_DWD; i++)
3990                         E1000_WRITE_REG(hw, reg_off + i * sizeof(uint32_t), 0);
3991                 E1000_WRITE_REG(hw, E1000_WUFC, wufc &
3992                         (~(E1000_WUFC_FLX0 << it->index)));
3993
3994                 filter_info->flex_mask &= ~(1 << it->index);
3995                 TAILQ_REMOVE(&filter_info->flex_list, it, entries);
3996                 rte_free(it);
3997                 rte_free(flex_filter);
3998         }
3999
4000         return 0;
4001 }
4002
4003 static int
4004 eth_igb_get_flex_filter(struct rte_eth_dev *dev,
4005                         struct rte_eth_flex_filter *filter)
4006 {
4007         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4008         struct e1000_filter_info *filter_info =
4009                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4010         struct e1000_flex_filter flex_filter, *it;
4011         uint32_t wufc, queueing, wufc_en = 0;
4012
4013         memset(&flex_filter, 0, sizeof(struct e1000_flex_filter));
4014         flex_filter.filter_info.len = filter->len;
4015         flex_filter.filter_info.priority = filter->priority;
4016         memcpy(flex_filter.filter_info.dwords, filter->bytes, filter->len);
4017         memcpy(flex_filter.filter_info.mask, filter->mask,
4018                         RTE_ALIGN(filter->len, sizeof(char)) / sizeof(char));
4019
4020         it = eth_igb_flex_filter_lookup(&filter_info->flex_list,
4021                                 &flex_filter.filter_info);
4022         if (it == NULL) {
4023                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
4024                 return -ENOENT;
4025         }
4026
4027         wufc = E1000_READ_REG(hw, E1000_WUFC);
4028         wufc_en = E1000_WUFC_FLEX_HQ | (E1000_WUFC_FLX0 << it->index);
4029
4030         if ((wufc & wufc_en) == wufc_en) {
4031                 uint32_t reg_off = 0;
4032                 if (it->index < E1000_MAX_FHFT)
4033                         reg_off = E1000_FHFT(it->index);
4034                 else
4035                         reg_off = E1000_FHFT_EXT(it->index - E1000_MAX_FHFT);
4036
4037                 queueing = E1000_READ_REG(hw,
4038                                 reg_off + E1000_FHFT_QUEUEING_OFFSET);
4039                 filter->len = queueing & E1000_FHFT_QUEUEING_LEN;
4040                 filter->priority = (queueing & E1000_FHFT_QUEUEING_PRIO) >>
4041                         E1000_FHFT_QUEUEING_PRIO_SHIFT;
4042                 filter->queue = (queueing & E1000_FHFT_QUEUEING_QUEUE) >>
4043                         E1000_FHFT_QUEUEING_QUEUE_SHIFT;
4044                 return 0;
4045         }
4046         return -ENOENT;
4047 }
4048
4049 static int
4050 eth_igb_flex_filter_handle(struct rte_eth_dev *dev,
4051                         enum rte_filter_op filter_op,
4052                         void *arg)
4053 {
4054         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4055         struct rte_eth_flex_filter *filter;
4056         int ret = 0;
4057
4058         MAC_TYPE_FILTER_SUP_EXT(hw->mac.type);
4059
4060         if (filter_op == RTE_ETH_FILTER_NOP)
4061                 return ret;
4062
4063         if (arg == NULL) {
4064                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
4065                             filter_op);
4066                 return -EINVAL;
4067         }
4068
4069         filter = (struct rte_eth_flex_filter *)arg;
4070         if (filter->len == 0 || filter->len > E1000_MAX_FLEX_FILTER_LEN
4071             || filter->len % sizeof(uint64_t) != 0) {
4072                 PMD_DRV_LOG(ERR, "filter's length is out of range");
4073                 return -EINVAL;
4074         }
4075         if (filter->priority > E1000_MAX_FLEX_FILTER_PRI) {
4076                 PMD_DRV_LOG(ERR, "filter's priority is out of range");
4077                 return -EINVAL;
4078         }
4079
4080         switch (filter_op) {
4081         case RTE_ETH_FILTER_ADD:
4082                 ret = eth_igb_add_del_flex_filter(dev, filter, TRUE);
4083                 break;
4084         case RTE_ETH_FILTER_DELETE:
4085                 ret = eth_igb_add_del_flex_filter(dev, filter, FALSE);
4086                 break;
4087         case RTE_ETH_FILTER_GET:
4088                 ret = eth_igb_get_flex_filter(dev, filter);
4089                 break;
4090         default:
4091                 PMD_DRV_LOG(ERR, "unsupported operation %u", filter_op);
4092                 ret = -EINVAL;
4093                 break;
4094         }
4095
4096         return ret;
4097 }
4098
4099 /* translate elements in struct rte_eth_ntuple_filter to struct e1000_5tuple_filter_info*/
4100 static inline int
4101 ntuple_filter_to_5tuple_82576(struct rte_eth_ntuple_filter *filter,
4102                         struct e1000_5tuple_filter_info *filter_info)
4103 {
4104         if (filter->queue >= IGB_MAX_RX_QUEUE_NUM_82576)
4105                 return -EINVAL;
4106         if (filter->priority > E1000_2TUPLE_MAX_PRI)
4107                 return -EINVAL;  /* filter index is out of range. */
4108         if (filter->tcp_flags > TCP_FLAG_ALL)
4109                 return -EINVAL;  /* flags is invalid. */
4110
4111         switch (filter->dst_ip_mask) {
4112         case UINT32_MAX:
4113                 filter_info->dst_ip_mask = 0;
4114                 filter_info->dst_ip = filter->dst_ip;
4115                 break;
4116         case 0:
4117                 filter_info->dst_ip_mask = 1;
4118                 break;
4119         default:
4120                 PMD_DRV_LOG(ERR, "invalid dst_ip mask.");
4121                 return -EINVAL;
4122         }
4123
4124         switch (filter->src_ip_mask) {
4125         case UINT32_MAX:
4126                 filter_info->src_ip_mask = 0;
4127                 filter_info->src_ip = filter->src_ip;
4128                 break;
4129         case 0:
4130                 filter_info->src_ip_mask = 1;
4131                 break;
4132         default:
4133                 PMD_DRV_LOG(ERR, "invalid src_ip mask.");
4134                 return -EINVAL;
4135         }
4136
4137         switch (filter->dst_port_mask) {
4138         case UINT16_MAX:
4139                 filter_info->dst_port_mask = 0;
4140                 filter_info->dst_port = filter->dst_port;
4141                 break;
4142         case 0:
4143                 filter_info->dst_port_mask = 1;
4144                 break;
4145         default:
4146                 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
4147                 return -EINVAL;
4148         }
4149
4150         switch (filter->src_port_mask) {
4151         case UINT16_MAX:
4152                 filter_info->src_port_mask = 0;
4153                 filter_info->src_port = filter->src_port;
4154                 break;
4155         case 0:
4156                 filter_info->src_port_mask = 1;
4157                 break;
4158         default:
4159                 PMD_DRV_LOG(ERR, "invalid src_port mask.");
4160                 return -EINVAL;
4161         }
4162
4163         switch (filter->proto_mask) {
4164         case UINT8_MAX:
4165                 filter_info->proto_mask = 0;
4166                 filter_info->proto = filter->proto;
4167                 break;
4168         case 0:
4169                 filter_info->proto_mask = 1;
4170                 break;
4171         default:
4172                 PMD_DRV_LOG(ERR, "invalid protocol mask.");
4173                 return -EINVAL;
4174         }
4175
4176         filter_info->priority = (uint8_t)filter->priority;
4177         if (filter->flags & RTE_NTUPLE_FLAGS_TCP_FLAG)
4178                 filter_info->tcp_flags = filter->tcp_flags;
4179         else
4180                 filter_info->tcp_flags = 0;
4181
4182         return 0;
4183 }
4184
4185 static inline struct e1000_5tuple_filter *
4186 igb_5tuple_filter_lookup_82576(struct e1000_5tuple_filter_list *filter_list,
4187                         struct e1000_5tuple_filter_info *key)
4188 {
4189         struct e1000_5tuple_filter *it;
4190
4191         TAILQ_FOREACH(it, filter_list, entries) {
4192                 if (memcmp(key, &it->filter_info,
4193                         sizeof(struct e1000_5tuple_filter_info)) == 0) {
4194                         return it;
4195                 }
4196         }
4197         return NULL;
4198 }
4199
4200 /*
4201  * igb_add_5tuple_filter_82576 - add a 5tuple filter
4202  *
4203  * @param
4204  * dev: Pointer to struct rte_eth_dev.
4205  * ntuple_filter: ponter to the filter that will be added.
4206  *
4207  * @return
4208  *    - On success, zero.
4209  *    - On failure, a negative value.
4210  */
4211 static int
4212 igb_add_5tuple_filter_82576(struct rte_eth_dev *dev,
4213                         struct rte_eth_ntuple_filter *ntuple_filter)
4214 {
4215         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4216         struct e1000_filter_info *filter_info =
4217                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4218         struct e1000_5tuple_filter *filter;
4219         uint32_t ftqf = E1000_FTQF_VF_BP | E1000_FTQF_MASK;
4220         uint32_t spqf, imir, imir_ext = E1000_IMIREXT_SIZE_BP;
4221         uint8_t i;
4222         int ret;
4223
4224         filter = rte_zmalloc("e1000_5tuple_filter",
4225                         sizeof(struct e1000_5tuple_filter), 0);
4226         if (filter == NULL)
4227                 return -ENOMEM;
4228
4229         ret = ntuple_filter_to_5tuple_82576(ntuple_filter,
4230                                             &filter->filter_info);
4231         if (ret < 0) {
4232                 rte_free(filter);
4233                 return ret;
4234         }
4235
4236         if (igb_5tuple_filter_lookup_82576(&filter_info->fivetuple_list,
4237                                          &filter->filter_info) != NULL) {
4238                 PMD_DRV_LOG(ERR, "filter exists.");
4239                 rte_free(filter);
4240                 return -EEXIST;
4241         }
4242         filter->queue = ntuple_filter->queue;
4243
4244         /*
4245          * look for an unused 5tuple filter index,
4246          * and insert the filter to list.
4247          */
4248         for (i = 0; i < E1000_MAX_FTQF_FILTERS; i++) {
4249                 if (!(filter_info->fivetuple_mask & (1 << i))) {
4250                         filter_info->fivetuple_mask |= 1 << i;
4251                         filter->index = i;
4252                         TAILQ_INSERT_TAIL(&filter_info->fivetuple_list,
4253                                           filter,
4254                                           entries);
4255                         break;
4256                 }
4257         }
4258         if (i >= E1000_MAX_FTQF_FILTERS) {
4259                 PMD_DRV_LOG(ERR, "5tuple filters are full.");
4260                 rte_free(filter);
4261                 return -ENOSYS;
4262         }
4263
4264         ftqf |= filter->filter_info.proto & E1000_FTQF_PROTOCOL_MASK;
4265         if (filter->filter_info.src_ip_mask == 0) /* 0b means compare. */
4266                 ftqf &= ~E1000_FTQF_MASK_SOURCE_ADDR_BP;
4267         if (filter->filter_info.dst_ip_mask == 0)
4268                 ftqf &= ~E1000_FTQF_MASK_DEST_ADDR_BP;
4269         if (filter->filter_info.src_port_mask == 0)
4270                 ftqf &= ~E1000_FTQF_MASK_SOURCE_PORT_BP;
4271         if (filter->filter_info.proto_mask == 0)
4272                 ftqf &= ~E1000_FTQF_MASK_PROTO_BP;
4273         ftqf |= (filter->queue << E1000_FTQF_QUEUE_SHIFT) &
4274                 E1000_FTQF_QUEUE_MASK;
4275         ftqf |= E1000_FTQF_QUEUE_ENABLE;
4276         E1000_WRITE_REG(hw, E1000_FTQF(i), ftqf);
4277         E1000_WRITE_REG(hw, E1000_DAQF(i), filter->filter_info.dst_ip);
4278         E1000_WRITE_REG(hw, E1000_SAQF(i), filter->filter_info.src_ip);
4279
4280         spqf = filter->filter_info.src_port & E1000_SPQF_SRCPORT;
4281         E1000_WRITE_REG(hw, E1000_SPQF(i), spqf);
4282
4283         imir = (uint32_t)(filter->filter_info.dst_port & E1000_IMIR_DSTPORT);
4284         if (filter->filter_info.dst_port_mask == 1) /* 1b means not compare. */
4285                 imir |= E1000_IMIR_PORT_BP;
4286         else
4287                 imir &= ~E1000_IMIR_PORT_BP;
4288         imir |= filter->filter_info.priority << E1000_IMIR_PRIORITY_SHIFT;
4289
4290         /* tcp flags bits setting. */
4291         if (filter->filter_info.tcp_flags & TCP_FLAG_ALL) {
4292                 if (filter->filter_info.tcp_flags & TCP_URG_FLAG)
4293                         imir_ext |= E1000_IMIREXT_CTRL_URG;
4294                 if (filter->filter_info.tcp_flags & TCP_ACK_FLAG)
4295                         imir_ext |= E1000_IMIREXT_CTRL_ACK;
4296                 if (filter->filter_info.tcp_flags & TCP_PSH_FLAG)
4297                         imir_ext |= E1000_IMIREXT_CTRL_PSH;
4298                 if (filter->filter_info.tcp_flags & TCP_RST_FLAG)
4299                         imir_ext |= E1000_IMIREXT_CTRL_RST;
4300                 if (filter->filter_info.tcp_flags & TCP_SYN_FLAG)
4301                         imir_ext |= E1000_IMIREXT_CTRL_SYN;
4302                 if (filter->filter_info.tcp_flags & TCP_FIN_FLAG)
4303                         imir_ext |= E1000_IMIREXT_CTRL_FIN;
4304         } else
4305                 imir_ext |= E1000_IMIREXT_CTRL_BP;
4306         E1000_WRITE_REG(hw, E1000_IMIR(i), imir);
4307         E1000_WRITE_REG(hw, E1000_IMIREXT(i), imir_ext);
4308         return 0;
4309 }
4310
4311 /*
4312  * igb_remove_5tuple_filter_82576 - remove a 5tuple filter
4313  *
4314  * @param
4315  * dev: Pointer to struct rte_eth_dev.
4316  * ntuple_filter: ponter to the filter that will be removed.
4317  *
4318  * @return
4319  *    - On success, zero.
4320  *    - On failure, a negative value.
4321  */
4322 static int
4323 igb_remove_5tuple_filter_82576(struct rte_eth_dev *dev,
4324                                 struct rte_eth_ntuple_filter *ntuple_filter)
4325 {
4326         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4327         struct e1000_filter_info *filter_info =
4328                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4329         struct e1000_5tuple_filter_info filter_5tuple;
4330         struct e1000_5tuple_filter *filter;
4331         int ret;
4332
4333         memset(&filter_5tuple, 0, sizeof(struct e1000_5tuple_filter_info));
4334         ret = ntuple_filter_to_5tuple_82576(ntuple_filter,
4335                                             &filter_5tuple);
4336         if (ret < 0)
4337                 return ret;
4338
4339         filter = igb_5tuple_filter_lookup_82576(&filter_info->fivetuple_list,
4340                                          &filter_5tuple);
4341         if (filter == NULL) {
4342                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
4343                 return -ENOENT;
4344         }
4345
4346         filter_info->fivetuple_mask &= ~(1 << filter->index);
4347         TAILQ_REMOVE(&filter_info->fivetuple_list, filter, entries);
4348         rte_free(filter);
4349
4350         E1000_WRITE_REG(hw, E1000_FTQF(filter->index),
4351                         E1000_FTQF_VF_BP | E1000_FTQF_MASK);
4352         E1000_WRITE_REG(hw, E1000_DAQF(filter->index), 0);
4353         E1000_WRITE_REG(hw, E1000_SAQF(filter->index), 0);
4354         E1000_WRITE_REG(hw, E1000_SPQF(filter->index), 0);
4355         E1000_WRITE_REG(hw, E1000_IMIR(filter->index), 0);
4356         E1000_WRITE_REG(hw, E1000_IMIREXT(filter->index), 0);
4357         return 0;
4358 }
4359
4360 static int
4361 eth_igb_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
4362 {
4363         uint32_t rctl;
4364         struct e1000_hw *hw;
4365         struct rte_eth_dev_info dev_info;
4366         uint32_t frame_size = mtu + (ETHER_HDR_LEN + ETHER_CRC_LEN +
4367                                      VLAN_TAG_SIZE);
4368
4369         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4370
4371 #ifdef RTE_LIBRTE_82571_SUPPORT
4372         /* XXX: not bigger than max_rx_pktlen */
4373         if (hw->mac.type == e1000_82571)
4374                 return -ENOTSUP;
4375 #endif
4376         eth_igb_infos_get(dev, &dev_info);
4377
4378         /* check that mtu is within the allowed range */
4379         if ((mtu < ETHER_MIN_MTU) ||
4380             (frame_size > dev_info.max_rx_pktlen))
4381                 return -EINVAL;
4382
4383         /* refuse mtu that requires the support of scattered packets when this
4384          * feature has not been enabled before. */
4385         if (!dev->data->scattered_rx &&
4386             frame_size > dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)
4387                 return -EINVAL;
4388
4389         rctl = E1000_READ_REG(hw, E1000_RCTL);
4390
4391         /* switch to jumbo mode if needed */
4392         if (frame_size > ETHER_MAX_LEN) {
4393                 dev->data->dev_conf.rxmode.jumbo_frame = 1;
4394                 rctl |= E1000_RCTL_LPE;
4395         } else {
4396                 dev->data->dev_conf.rxmode.jumbo_frame = 0;
4397                 rctl &= ~E1000_RCTL_LPE;
4398         }
4399         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
4400
4401         /* update max frame size */
4402         dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
4403
4404         E1000_WRITE_REG(hw, E1000_RLPML,
4405                         dev->data->dev_conf.rxmode.max_rx_pkt_len);
4406
4407         return 0;
4408 }
4409
4410 /*
4411  * igb_add_del_ntuple_filter - add or delete a ntuple filter
4412  *
4413  * @param
4414  * dev: Pointer to struct rte_eth_dev.
4415  * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
4416  * add: if true, add filter, if false, remove filter
4417  *
4418  * @return
4419  *    - On success, zero.
4420  *    - On failure, a negative value.
4421  */
4422 static int
4423 igb_add_del_ntuple_filter(struct rte_eth_dev *dev,
4424                         struct rte_eth_ntuple_filter *ntuple_filter,
4425                         bool add)
4426 {
4427         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4428         int ret;
4429
4430         switch (ntuple_filter->flags) {
4431         case RTE_5TUPLE_FLAGS:
4432         case (RTE_5TUPLE_FLAGS | RTE_NTUPLE_FLAGS_TCP_FLAG):
4433                 if (hw->mac.type != e1000_82576)
4434                         return -ENOTSUP;
4435                 if (add)
4436                         ret = igb_add_5tuple_filter_82576(dev,
4437                                                           ntuple_filter);
4438                 else
4439                         ret = igb_remove_5tuple_filter_82576(dev,
4440                                                              ntuple_filter);
4441                 break;
4442         case RTE_2TUPLE_FLAGS:
4443         case (RTE_2TUPLE_FLAGS | RTE_NTUPLE_FLAGS_TCP_FLAG):
4444                 if (hw->mac.type != e1000_82580 && hw->mac.type != e1000_i350)
4445                         return -ENOTSUP;
4446                 if (add)
4447                         ret = igb_add_2tuple_filter(dev, ntuple_filter);
4448                 else
4449                         ret = igb_remove_2tuple_filter(dev, ntuple_filter);
4450                 break;
4451         default:
4452                 ret = -EINVAL;
4453                 break;
4454         }
4455
4456         return ret;
4457 }
4458
4459 /*
4460  * igb_get_ntuple_filter - get a ntuple filter
4461  *
4462  * @param
4463  * dev: Pointer to struct rte_eth_dev.
4464  * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
4465  *
4466  * @return
4467  *    - On success, zero.
4468  *    - On failure, a negative value.
4469  */
4470 static int
4471 igb_get_ntuple_filter(struct rte_eth_dev *dev,
4472                         struct rte_eth_ntuple_filter *ntuple_filter)
4473 {
4474         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4475         struct e1000_filter_info *filter_info =
4476                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4477         struct e1000_5tuple_filter_info filter_5tuple;
4478         struct e1000_2tuple_filter_info filter_2tuple;
4479         struct e1000_5tuple_filter *p_5tuple_filter;
4480         struct e1000_2tuple_filter *p_2tuple_filter;
4481         int ret;
4482
4483         switch (ntuple_filter->flags) {
4484         case RTE_5TUPLE_FLAGS:
4485         case (RTE_5TUPLE_FLAGS | RTE_NTUPLE_FLAGS_TCP_FLAG):
4486                 if (hw->mac.type != e1000_82576)
4487                         return -ENOTSUP;
4488                 memset(&filter_5tuple,
4489                         0,
4490                         sizeof(struct e1000_5tuple_filter_info));
4491                 ret = ntuple_filter_to_5tuple_82576(ntuple_filter,
4492                                                     &filter_5tuple);
4493                 if (ret < 0)
4494                         return ret;
4495                 p_5tuple_filter = igb_5tuple_filter_lookup_82576(
4496                                         &filter_info->fivetuple_list,
4497                                         &filter_5tuple);
4498                 if (p_5tuple_filter == NULL) {
4499                         PMD_DRV_LOG(ERR, "filter doesn't exist.");
4500                         return -ENOENT;
4501                 }
4502                 ntuple_filter->queue = p_5tuple_filter->queue;
4503                 break;
4504         case RTE_2TUPLE_FLAGS:
4505         case (RTE_2TUPLE_FLAGS | RTE_NTUPLE_FLAGS_TCP_FLAG):
4506                 if (hw->mac.type != e1000_82580 && hw->mac.type != e1000_i350)
4507                         return -ENOTSUP;
4508                 memset(&filter_2tuple,
4509                         0,
4510                         sizeof(struct e1000_2tuple_filter_info));
4511                 ret = ntuple_filter_to_2tuple(ntuple_filter, &filter_2tuple);
4512                 if (ret < 0)
4513                         return ret;
4514                 p_2tuple_filter = igb_2tuple_filter_lookup(
4515                                         &filter_info->twotuple_list,
4516                                         &filter_2tuple);
4517                 if (p_2tuple_filter == NULL) {
4518                         PMD_DRV_LOG(ERR, "filter doesn't exist.");
4519                         return -ENOENT;
4520                 }
4521                 ntuple_filter->queue = p_2tuple_filter->queue;
4522                 break;
4523         default:
4524                 ret = -EINVAL;
4525                 break;
4526         }
4527
4528         return 0;
4529 }
4530
4531 /*
4532  * igb_ntuple_filter_handle - Handle operations for ntuple filter.
4533  * @dev: pointer to rte_eth_dev structure
4534  * @filter_op:operation will be taken.
4535  * @arg: a pointer to specific structure corresponding to the filter_op
4536  */
4537 static int
4538 igb_ntuple_filter_handle(struct rte_eth_dev *dev,
4539                                 enum rte_filter_op filter_op,
4540                                 void *arg)
4541 {
4542         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4543         int ret;
4544
4545         MAC_TYPE_FILTER_SUP(hw->mac.type);
4546
4547         if (filter_op == RTE_ETH_FILTER_NOP)
4548                 return 0;
4549
4550         if (arg == NULL) {
4551                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
4552                             filter_op);
4553                 return -EINVAL;
4554         }
4555
4556         switch (filter_op) {
4557         case RTE_ETH_FILTER_ADD:
4558                 ret = igb_add_del_ntuple_filter(dev,
4559                         (struct rte_eth_ntuple_filter *)arg,
4560                         TRUE);
4561                 break;
4562         case RTE_ETH_FILTER_DELETE:
4563                 ret = igb_add_del_ntuple_filter(dev,
4564                         (struct rte_eth_ntuple_filter *)arg,
4565                         FALSE);
4566                 break;
4567         case RTE_ETH_FILTER_GET:
4568                 ret = igb_get_ntuple_filter(dev,
4569                         (struct rte_eth_ntuple_filter *)arg);
4570                 break;
4571         default:
4572                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
4573                 ret = -EINVAL;
4574                 break;
4575         }
4576         return ret;
4577 }
4578
4579 static inline int
4580 igb_ethertype_filter_lookup(struct e1000_filter_info *filter_info,
4581                         uint16_t ethertype)
4582 {
4583         int i;
4584
4585         for (i = 0; i < E1000_MAX_ETQF_FILTERS; i++) {
4586                 if (filter_info->ethertype_filters[i] == ethertype &&
4587                     (filter_info->ethertype_mask & (1 << i)))
4588                         return i;
4589         }
4590         return -1;
4591 }
4592
4593 static inline int
4594 igb_ethertype_filter_insert(struct e1000_filter_info *filter_info,
4595                         uint16_t ethertype)
4596 {
4597         int i;
4598
4599         for (i = 0; i < E1000_MAX_ETQF_FILTERS; i++) {
4600                 if (!(filter_info->ethertype_mask & (1 << i))) {
4601                         filter_info->ethertype_mask |= 1 << i;
4602                         filter_info->ethertype_filters[i] = ethertype;
4603                         return i;
4604                 }
4605         }
4606         return -1;
4607 }
4608
4609 static inline int
4610 igb_ethertype_filter_remove(struct e1000_filter_info *filter_info,
4611                         uint8_t idx)
4612 {
4613         if (idx >= E1000_MAX_ETQF_FILTERS)
4614                 return -1;
4615         filter_info->ethertype_mask &= ~(1 << idx);
4616         filter_info->ethertype_filters[idx] = 0;
4617         return idx;
4618 }
4619
4620
4621 static int
4622 igb_add_del_ethertype_filter(struct rte_eth_dev *dev,
4623                         struct rte_eth_ethertype_filter *filter,
4624                         bool add)
4625 {
4626         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4627         struct e1000_filter_info *filter_info =
4628                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4629         uint32_t etqf = 0;
4630         int ret;
4631
4632         if (filter->ether_type == ETHER_TYPE_IPv4 ||
4633                 filter->ether_type == ETHER_TYPE_IPv6) {
4634                 PMD_DRV_LOG(ERR, "unsupported ether_type(0x%04x) in"
4635                         " ethertype filter.", filter->ether_type);
4636                 return -EINVAL;
4637         }
4638
4639         if (filter->flags & RTE_ETHTYPE_FLAGS_MAC) {
4640                 PMD_DRV_LOG(ERR, "mac compare is unsupported.");
4641                 return -EINVAL;
4642         }
4643         if (filter->flags & RTE_ETHTYPE_FLAGS_DROP) {
4644                 PMD_DRV_LOG(ERR, "drop option is unsupported.");
4645                 return -EINVAL;
4646         }
4647
4648         ret = igb_ethertype_filter_lookup(filter_info, filter->ether_type);
4649         if (ret >= 0 && add) {
4650                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter exists.",
4651                             filter->ether_type);
4652                 return -EEXIST;
4653         }
4654         if (ret < 0 && !add) {
4655                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
4656                             filter->ether_type);
4657                 return -ENOENT;
4658         }
4659
4660         if (add) {
4661                 ret = igb_ethertype_filter_insert(filter_info,
4662                         filter->ether_type);
4663                 if (ret < 0) {
4664                         PMD_DRV_LOG(ERR, "ethertype filters are full.");
4665                         return -ENOSYS;
4666                 }
4667
4668                 etqf |= E1000_ETQF_FILTER_ENABLE | E1000_ETQF_QUEUE_ENABLE;
4669                 etqf |= (uint32_t)(filter->ether_type & E1000_ETQF_ETHERTYPE);
4670                 etqf |= filter->queue << E1000_ETQF_QUEUE_SHIFT;
4671         } else {
4672                 ret = igb_ethertype_filter_remove(filter_info, (uint8_t)ret);
4673                 if (ret < 0)
4674                         return -ENOSYS;
4675         }
4676         E1000_WRITE_REG(hw, E1000_ETQF(ret), etqf);
4677         E1000_WRITE_FLUSH(hw);
4678
4679         return 0;
4680 }
4681
4682 static int
4683 igb_get_ethertype_filter(struct rte_eth_dev *dev,
4684                         struct rte_eth_ethertype_filter *filter)
4685 {
4686         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4687         struct e1000_filter_info *filter_info =
4688                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4689         uint32_t etqf;
4690         int ret;
4691
4692         ret = igb_ethertype_filter_lookup(filter_info, filter->ether_type);
4693         if (ret < 0) {
4694                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
4695                             filter->ether_type);
4696                 return -ENOENT;
4697         }
4698
4699         etqf = E1000_READ_REG(hw, E1000_ETQF(ret));
4700         if (etqf & E1000_ETQF_FILTER_ENABLE) {
4701                 filter->ether_type = etqf & E1000_ETQF_ETHERTYPE;
4702                 filter->flags = 0;
4703                 filter->queue = (etqf & E1000_ETQF_QUEUE) >>
4704                                 E1000_ETQF_QUEUE_SHIFT;
4705                 return 0;
4706         }
4707
4708         return -ENOENT;
4709 }
4710
4711 /*
4712  * igb_ethertype_filter_handle - Handle operations for ethertype filter.
4713  * @dev: pointer to rte_eth_dev structure
4714  * @filter_op:operation will be taken.
4715  * @arg: a pointer to specific structure corresponding to the filter_op
4716  */
4717 static int
4718 igb_ethertype_filter_handle(struct rte_eth_dev *dev,
4719                                 enum rte_filter_op filter_op,
4720                                 void *arg)
4721 {
4722         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4723         int ret;
4724
4725         MAC_TYPE_FILTER_SUP(hw->mac.type);
4726
4727         if (filter_op == RTE_ETH_FILTER_NOP)
4728                 return 0;
4729
4730         if (arg == NULL) {
4731                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
4732                             filter_op);
4733                 return -EINVAL;
4734         }
4735
4736         switch (filter_op) {
4737         case RTE_ETH_FILTER_ADD:
4738                 ret = igb_add_del_ethertype_filter(dev,
4739                         (struct rte_eth_ethertype_filter *)arg,
4740                         TRUE);
4741                 break;
4742         case RTE_ETH_FILTER_DELETE:
4743                 ret = igb_add_del_ethertype_filter(dev,
4744                         (struct rte_eth_ethertype_filter *)arg,
4745                         FALSE);
4746                 break;
4747         case RTE_ETH_FILTER_GET:
4748                 ret = igb_get_ethertype_filter(dev,
4749                         (struct rte_eth_ethertype_filter *)arg);
4750                 break;
4751         default:
4752                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
4753                 ret = -EINVAL;
4754                 break;
4755         }
4756         return ret;
4757 }
4758
4759 static int
4760 eth_igb_filter_ctrl(struct rte_eth_dev *dev,
4761                      enum rte_filter_type filter_type,
4762                      enum rte_filter_op filter_op,
4763                      void *arg)
4764 {
4765         int ret = -EINVAL;
4766
4767         switch (filter_type) {
4768         case RTE_ETH_FILTER_NTUPLE:
4769                 ret = igb_ntuple_filter_handle(dev, filter_op, arg);
4770                 break;
4771         case RTE_ETH_FILTER_ETHERTYPE:
4772                 ret = igb_ethertype_filter_handle(dev, filter_op, arg);
4773                 break;
4774         case RTE_ETH_FILTER_SYN:
4775                 ret = eth_igb_syn_filter_handle(dev, filter_op, arg);
4776                 break;
4777         case RTE_ETH_FILTER_FLEXIBLE:
4778                 ret = eth_igb_flex_filter_handle(dev, filter_op, arg);
4779                 break;
4780         default:
4781                 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
4782                                                         filter_type);
4783                 break;
4784         }
4785
4786         return ret;
4787 }
4788
4789 static int
4790 eth_igb_set_mc_addr_list(struct rte_eth_dev *dev,
4791                          struct ether_addr *mc_addr_set,
4792                          uint32_t nb_mc_addr)
4793 {
4794         struct e1000_hw *hw;
4795
4796         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4797         e1000_update_mc_addr_list(hw, (u8 *)mc_addr_set, nb_mc_addr);
4798         return 0;
4799 }
4800
4801 static uint64_t
4802 igb_read_systime_cyclecounter(struct rte_eth_dev *dev)
4803 {
4804         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4805         uint64_t systime_cycles;
4806
4807         switch (hw->mac.type) {
4808         case e1000_i210:
4809         case e1000_i211:
4810                 /*
4811                  * Need to read System Time Residue Register to be able
4812                  * to read the other two registers.
4813                  */
4814                 E1000_READ_REG(hw, E1000_SYSTIMR);
4815                 /* SYSTIMEL stores ns and SYSTIMEH stores seconds. */
4816                 systime_cycles = (uint64_t)E1000_READ_REG(hw, E1000_SYSTIML);
4817                 systime_cycles += (uint64_t)E1000_READ_REG(hw, E1000_SYSTIMH)
4818                                 * NSEC_PER_SEC;
4819                 break;
4820         case e1000_82580:
4821         case e1000_i350:
4822         case e1000_i354:
4823                 /*
4824                  * Need to read System Time Residue Register to be able
4825                  * to read the other two registers.
4826                  */
4827                 E1000_READ_REG(hw, E1000_SYSTIMR);
4828                 systime_cycles = (uint64_t)E1000_READ_REG(hw, E1000_SYSTIML);
4829                 /* Only the 8 LSB are valid. */
4830                 systime_cycles |= (uint64_t)(E1000_READ_REG(hw, E1000_SYSTIMH)
4831                                 & 0xff) << 32;
4832                 break;
4833         default:
4834                 systime_cycles = (uint64_t)E1000_READ_REG(hw, E1000_SYSTIML);
4835                 systime_cycles |= (uint64_t)E1000_READ_REG(hw, E1000_SYSTIMH)
4836                                 << 32;
4837                 break;
4838         }
4839
4840         return systime_cycles;
4841 }
4842
4843 static uint64_t
4844 igb_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev)
4845 {
4846         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4847         uint64_t rx_tstamp_cycles;
4848
4849         switch (hw->mac.type) {
4850         case e1000_i210:
4851         case e1000_i211:
4852                 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
4853                 rx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_RXSTMPL);
4854                 rx_tstamp_cycles += (uint64_t)E1000_READ_REG(hw, E1000_RXSTMPH)
4855                                 * NSEC_PER_SEC;
4856                 break;
4857         case e1000_82580:
4858         case e1000_i350:
4859         case e1000_i354:
4860                 rx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_RXSTMPL);
4861                 /* Only the 8 LSB are valid. */
4862                 rx_tstamp_cycles |= (uint64_t)(E1000_READ_REG(hw, E1000_RXSTMPH)
4863                                 & 0xff) << 32;
4864                 break;
4865         default:
4866                 rx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_RXSTMPL);
4867                 rx_tstamp_cycles |= (uint64_t)E1000_READ_REG(hw, E1000_RXSTMPH)
4868                                 << 32;
4869                 break;
4870         }
4871
4872         return rx_tstamp_cycles;
4873 }
4874
4875 static uint64_t
4876 igb_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev)
4877 {
4878         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4879         uint64_t tx_tstamp_cycles;
4880
4881         switch (hw->mac.type) {
4882         case e1000_i210:
4883         case e1000_i211:
4884                 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
4885                 tx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_TXSTMPL);
4886                 tx_tstamp_cycles += (uint64_t)E1000_READ_REG(hw, E1000_TXSTMPH)
4887                                 * NSEC_PER_SEC;
4888                 break;
4889         case e1000_82580:
4890         case e1000_i350:
4891         case e1000_i354:
4892                 tx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_TXSTMPL);
4893                 /* Only the 8 LSB are valid. */
4894                 tx_tstamp_cycles |= (uint64_t)(E1000_READ_REG(hw, E1000_TXSTMPH)
4895                                 & 0xff) << 32;
4896                 break;
4897         default:
4898                 tx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_TXSTMPL);
4899                 tx_tstamp_cycles |= (uint64_t)E1000_READ_REG(hw, E1000_TXSTMPH)
4900                                 << 32;
4901                 break;
4902         }
4903
4904         return tx_tstamp_cycles;
4905 }
4906
4907 static void
4908 igb_start_timecounters(struct rte_eth_dev *dev)
4909 {
4910         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4911         struct e1000_adapter *adapter =
4912                 (struct e1000_adapter *)dev->data->dev_private;
4913         uint32_t incval = 1;
4914         uint32_t shift = 0;
4915         uint64_t mask = E1000_CYCLECOUNTER_MASK;
4916
4917         switch (hw->mac.type) {
4918         case e1000_82580:
4919         case e1000_i350:
4920         case e1000_i354:
4921                 /* 32 LSB bits + 8 MSB bits = 40 bits */
4922                 mask = (1ULL << 40) - 1;
4923                 /* fall-through */
4924         case e1000_i210:
4925         case e1000_i211:
4926                 /*
4927                  * Start incrementing the register
4928                  * used to timestamp PTP packets.
4929                  */
4930                 E1000_WRITE_REG(hw, E1000_TIMINCA, incval);
4931                 break;
4932         case e1000_82576:
4933                 incval = E1000_INCVALUE_82576;
4934                 shift = IGB_82576_TSYNC_SHIFT;
4935                 E1000_WRITE_REG(hw, E1000_TIMINCA,
4936                                 E1000_INCPERIOD_82576 | incval);
4937                 break;
4938         default:
4939                 /* Not supported */
4940                 return;
4941         }
4942
4943         memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter));
4944         memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
4945         memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
4946
4947         adapter->systime_tc.cc_mask = mask;
4948         adapter->systime_tc.cc_shift = shift;
4949         adapter->systime_tc.nsec_mask = (1ULL << shift) - 1;
4950
4951         adapter->rx_tstamp_tc.cc_mask = mask;
4952         adapter->rx_tstamp_tc.cc_shift = shift;
4953         adapter->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
4954
4955         adapter->tx_tstamp_tc.cc_mask = mask;
4956         adapter->tx_tstamp_tc.cc_shift = shift;
4957         adapter->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
4958 }
4959
4960 static int
4961 igb_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
4962 {
4963         struct e1000_adapter *adapter =
4964                         (struct e1000_adapter *)dev->data->dev_private;
4965
4966         adapter->systime_tc.nsec += delta;
4967         adapter->rx_tstamp_tc.nsec += delta;
4968         adapter->tx_tstamp_tc.nsec += delta;
4969
4970         return 0;
4971 }
4972
4973 static int
4974 igb_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
4975 {
4976         uint64_t ns;
4977         struct e1000_adapter *adapter =
4978                         (struct e1000_adapter *)dev->data->dev_private;
4979
4980         ns = rte_timespec_to_ns(ts);
4981
4982         /* Set the timecounters to a new value. */
4983         adapter->systime_tc.nsec = ns;
4984         adapter->rx_tstamp_tc.nsec = ns;
4985         adapter->tx_tstamp_tc.nsec = ns;
4986
4987         return 0;
4988 }
4989
4990 static int
4991 igb_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
4992 {
4993         uint64_t ns, systime_cycles;
4994         struct e1000_adapter *adapter =
4995                         (struct e1000_adapter *)dev->data->dev_private;
4996
4997         systime_cycles = igb_read_systime_cyclecounter(dev);
4998         ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles);
4999         *ts = rte_ns_to_timespec(ns);
5000
5001         return 0;
5002 }
5003
5004 static int
5005 igb_timesync_enable(struct rte_eth_dev *dev)
5006 {
5007         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5008         uint32_t tsync_ctl;
5009         uint32_t tsauxc;
5010
5011         /* Stop the timesync system time. */
5012         E1000_WRITE_REG(hw, E1000_TIMINCA, 0x0);
5013         /* Reset the timesync system time value. */
5014         switch (hw->mac.type) {
5015         case e1000_82580:
5016         case e1000_i350:
5017         case e1000_i354:
5018         case e1000_i210:
5019         case e1000_i211:
5020                 E1000_WRITE_REG(hw, E1000_SYSTIMR, 0x0);
5021                 /* fall-through */
5022         case e1000_82576:
5023                 E1000_WRITE_REG(hw, E1000_SYSTIML, 0x0);
5024                 E1000_WRITE_REG(hw, E1000_SYSTIMH, 0x0);
5025                 break;
5026         default:
5027                 /* Not supported. */
5028                 return -ENOTSUP;
5029         }
5030
5031         /* Enable system time for it isn't on by default. */
5032         tsauxc = E1000_READ_REG(hw, E1000_TSAUXC);
5033         tsauxc &= ~E1000_TSAUXC_DISABLE_SYSTIME;
5034         E1000_WRITE_REG(hw, E1000_TSAUXC, tsauxc);
5035
5036         igb_start_timecounters(dev);
5037
5038         /* Enable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
5039         E1000_WRITE_REG(hw, E1000_ETQF(E1000_ETQF_FILTER_1588),
5040                         (ETHER_TYPE_1588 |
5041                          E1000_ETQF_FILTER_ENABLE |
5042                          E1000_ETQF_1588));
5043
5044         /* Enable timestamping of received PTP packets. */
5045         tsync_ctl = E1000_READ_REG(hw, E1000_TSYNCRXCTL);
5046         tsync_ctl |= E1000_TSYNCRXCTL_ENABLED;
5047         E1000_WRITE_REG(hw, E1000_TSYNCRXCTL, tsync_ctl);
5048
5049         /* Enable Timestamping of transmitted PTP packets. */
5050         tsync_ctl = E1000_READ_REG(hw, E1000_TSYNCTXCTL);
5051         tsync_ctl |= E1000_TSYNCTXCTL_ENABLED;
5052         E1000_WRITE_REG(hw, E1000_TSYNCTXCTL, tsync_ctl);
5053
5054         return 0;
5055 }
5056
5057 static int
5058 igb_timesync_disable(struct rte_eth_dev *dev)
5059 {
5060         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5061         uint32_t tsync_ctl;
5062
5063         /* Disable timestamping of transmitted PTP packets. */
5064         tsync_ctl = E1000_READ_REG(hw, E1000_TSYNCTXCTL);
5065         tsync_ctl &= ~E1000_TSYNCTXCTL_ENABLED;
5066         E1000_WRITE_REG(hw, E1000_TSYNCTXCTL, tsync_ctl);
5067
5068         /* Disable timestamping of received PTP packets. */
5069         tsync_ctl = E1000_READ_REG(hw, E1000_TSYNCRXCTL);
5070         tsync_ctl &= ~E1000_TSYNCRXCTL_ENABLED;
5071         E1000_WRITE_REG(hw, E1000_TSYNCRXCTL, tsync_ctl);
5072
5073         /* Disable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
5074         E1000_WRITE_REG(hw, E1000_ETQF(E1000_ETQF_FILTER_1588), 0);
5075
5076         /* Stop incrementating the System Time registers. */
5077         E1000_WRITE_REG(hw, E1000_TIMINCA, 0);
5078
5079         return 0;
5080 }
5081
5082 static int
5083 igb_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
5084                                struct timespec *timestamp,
5085                                uint32_t flags __rte_unused)
5086 {
5087         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5088         struct e1000_adapter *adapter =
5089                         (struct e1000_adapter *)dev->data->dev_private;
5090         uint32_t tsync_rxctl;
5091         uint64_t rx_tstamp_cycles;
5092         uint64_t ns;
5093
5094         tsync_rxctl = E1000_READ_REG(hw, E1000_TSYNCRXCTL);
5095         if ((tsync_rxctl & E1000_TSYNCRXCTL_VALID) == 0)
5096                 return -EINVAL;
5097
5098         rx_tstamp_cycles = igb_read_rx_tstamp_cyclecounter(dev);
5099         ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles);
5100         *timestamp = rte_ns_to_timespec(ns);
5101
5102         return  0;
5103 }
5104
5105 static int
5106 igb_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
5107                                struct timespec *timestamp)
5108 {
5109         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5110         struct e1000_adapter *adapter =
5111                         (struct e1000_adapter *)dev->data->dev_private;
5112         uint32_t tsync_txctl;
5113         uint64_t tx_tstamp_cycles;
5114         uint64_t ns;
5115
5116         tsync_txctl = E1000_READ_REG(hw, E1000_TSYNCTXCTL);
5117         if ((tsync_txctl & E1000_TSYNCTXCTL_VALID) == 0)
5118                 return -EINVAL;
5119
5120         tx_tstamp_cycles = igb_read_tx_tstamp_cyclecounter(dev);
5121         ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles);
5122         *timestamp = rte_ns_to_timespec(ns);
5123
5124         return  0;
5125 }
5126
5127 static int
5128 eth_igb_get_reg_length(struct rte_eth_dev *dev __rte_unused)
5129 {
5130         int count = 0;
5131         int g_ind = 0;
5132         const struct reg_info *reg_group;
5133
5134         while ((reg_group = igb_regs[g_ind++]))
5135                 count += igb_reg_group_count(reg_group);
5136
5137         return count;
5138 }
5139
5140 static int
5141 igbvf_get_reg_length(struct rte_eth_dev *dev __rte_unused)
5142 {
5143         int count = 0;
5144         int g_ind = 0;
5145         const struct reg_info *reg_group;
5146
5147         while ((reg_group = igbvf_regs[g_ind++]))
5148                 count += igb_reg_group_count(reg_group);
5149
5150         return count;
5151 }
5152
5153 static int
5154 eth_igb_get_regs(struct rte_eth_dev *dev,
5155         struct rte_dev_reg_info *regs)
5156 {
5157         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5158         uint32_t *data = regs->data;
5159         int g_ind = 0;
5160         int count = 0;
5161         const struct reg_info *reg_group;
5162
5163         if (data == NULL) {
5164                 regs->length = eth_igb_get_reg_length(dev);
5165                 regs->width = sizeof(uint32_t);
5166                 return 0;
5167         }
5168
5169         /* Support only full register dump */
5170         if ((regs->length == 0) ||
5171             (regs->length == (uint32_t)eth_igb_get_reg_length(dev))) {
5172                 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
5173                         hw->device_id;
5174                 while ((reg_group = igb_regs[g_ind++]))
5175                         count += igb_read_regs_group(dev, &data[count],
5176                                                         reg_group);
5177                 return 0;
5178         }
5179
5180         return -ENOTSUP;
5181 }
5182
5183 static int
5184 igbvf_get_regs(struct rte_eth_dev *dev,
5185         struct rte_dev_reg_info *regs)
5186 {
5187         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5188         uint32_t *data = regs->data;
5189         int g_ind = 0;
5190         int count = 0;
5191         const struct reg_info *reg_group;
5192
5193         if (data == NULL) {
5194                 regs->length = igbvf_get_reg_length(dev);
5195                 regs->width = sizeof(uint32_t);
5196                 return 0;
5197         }
5198
5199         /* Support only full register dump */
5200         if ((regs->length == 0) ||
5201             (regs->length == (uint32_t)igbvf_get_reg_length(dev))) {
5202                 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
5203                         hw->device_id;
5204                 while ((reg_group = igbvf_regs[g_ind++]))
5205                         count += igb_read_regs_group(dev, &data[count],
5206                                                         reg_group);
5207                 return 0;
5208         }
5209
5210         return -ENOTSUP;
5211 }
5212
5213 static int
5214 eth_igb_get_eeprom_length(struct rte_eth_dev *dev)
5215 {
5216         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5217
5218         /* Return unit is byte count */
5219         return hw->nvm.word_size * 2;
5220 }
5221
5222 static int
5223 eth_igb_get_eeprom(struct rte_eth_dev *dev,
5224         struct rte_dev_eeprom_info *in_eeprom)
5225 {
5226         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5227         struct e1000_nvm_info *nvm = &hw->nvm;
5228         uint16_t *data = in_eeprom->data;
5229         int first, length;
5230
5231         first = in_eeprom->offset >> 1;
5232         length = in_eeprom->length >> 1;
5233         if ((first >= hw->nvm.word_size) ||
5234             ((first + length) >= hw->nvm.word_size))
5235                 return -EINVAL;
5236
5237         in_eeprom->magic = hw->vendor_id |
5238                 ((uint32_t)hw->device_id << 16);
5239
5240         if ((nvm->ops.read) == NULL)
5241                 return -ENOTSUP;
5242
5243         return nvm->ops.read(hw, first, length, data);
5244 }
5245
5246 static int
5247 eth_igb_set_eeprom(struct rte_eth_dev *dev,
5248         struct rte_dev_eeprom_info *in_eeprom)
5249 {
5250         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5251         struct e1000_nvm_info *nvm = &hw->nvm;
5252         uint16_t *data = in_eeprom->data;
5253         int first, length;
5254
5255         first = in_eeprom->offset >> 1;
5256         length = in_eeprom->length >> 1;
5257         if ((first >= hw->nvm.word_size) ||
5258             ((first + length) >= hw->nvm.word_size))
5259                 return -EINVAL;
5260
5261         in_eeprom->magic = (uint32_t)hw->vendor_id |
5262                 ((uint32_t)hw->device_id << 16);
5263
5264         if ((nvm->ops.write) == NULL)
5265                 return -ENOTSUP;
5266         return nvm->ops.write(hw,  first, length, data);
5267 }
5268
5269 static int
5270 eth_igb_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
5271 {
5272         struct e1000_hw *hw =
5273                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5274         uint32_t mask = 1 << queue_id;
5275
5276         E1000_WRITE_REG(hw, E1000_EIMC, mask);
5277         E1000_WRITE_FLUSH(hw);
5278
5279         return 0;
5280 }
5281
5282 static int
5283 eth_igb_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
5284 {
5285         struct e1000_hw *hw =
5286                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5287         struct rte_pci_device *pci_dev = E1000_DEV_TO_PCI(dev);
5288         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5289         uint32_t mask = 1 << queue_id;
5290         uint32_t regval;
5291
5292         regval = E1000_READ_REG(hw, E1000_EIMS);
5293         E1000_WRITE_REG(hw, E1000_EIMS, regval | mask);
5294         E1000_WRITE_FLUSH(hw);
5295
5296         rte_intr_enable(intr_handle);
5297
5298         return 0;
5299 }
5300
5301 static void
5302 eth_igb_write_ivar(struct e1000_hw *hw, uint8_t  msix_vector,
5303                    uint8_t index, uint8_t offset)
5304 {
5305         uint32_t val = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index);
5306
5307         /* clear bits */
5308         val &= ~((uint32_t)0xFF << offset);
5309
5310         /* write vector and valid bit */
5311         val |= (msix_vector | E1000_IVAR_VALID) << offset;
5312
5313         E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, val);
5314 }
5315
5316 static void
5317 eth_igb_assign_msix_vector(struct e1000_hw *hw, int8_t direction,
5318                            uint8_t queue, uint8_t msix_vector)
5319 {
5320         uint32_t tmp = 0;
5321
5322         if (hw->mac.type == e1000_82575) {
5323                 if (direction == 0)
5324                         tmp = E1000_EICR_RX_QUEUE0 << queue;
5325                 else if (direction == 1)
5326                         tmp = E1000_EICR_TX_QUEUE0 << queue;
5327                 E1000_WRITE_REG(hw, E1000_MSIXBM(msix_vector), tmp);
5328         } else if (hw->mac.type == e1000_82576) {
5329                 if ((direction == 0) || (direction == 1))
5330                         eth_igb_write_ivar(hw, msix_vector, queue & 0x7,
5331                                            ((queue & 0x8) << 1) +
5332                                            8 * direction);
5333         } else if ((hw->mac.type == e1000_82580) ||
5334                         (hw->mac.type == e1000_i350) ||
5335                         (hw->mac.type == e1000_i354) ||
5336                         (hw->mac.type == e1000_i210) ||
5337                         (hw->mac.type == e1000_i211)) {
5338                 if ((direction == 0) || (direction == 1))
5339                         eth_igb_write_ivar(hw, msix_vector,
5340                                            queue >> 1,
5341                                            ((queue & 0x1) << 4) +
5342                                            8 * direction);
5343         }
5344 }
5345
5346 /* Sets up the hardware to generate MSI-X interrupts properly
5347  * @hw
5348  *  board private structure
5349  */
5350 static void
5351 eth_igb_configure_msix_intr(struct rte_eth_dev *dev)
5352 {
5353         int queue_id;
5354         uint32_t tmpval, regval, intr_mask;
5355         struct e1000_hw *hw =
5356                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5357         uint32_t vec = E1000_MISC_VEC_ID;
5358         uint32_t base = E1000_MISC_VEC_ID;
5359         uint32_t misc_shift = 0;
5360         struct rte_pci_device *pci_dev = E1000_DEV_TO_PCI(dev);
5361         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5362
5363         /* won't configure msix register if no mapping is done
5364          * between intr vector and event fd
5365          */
5366         if (!rte_intr_dp_is_en(intr_handle))
5367                 return;
5368
5369         if (rte_intr_allow_others(intr_handle)) {
5370                 vec = base = E1000_RX_VEC_START;
5371                 misc_shift = 1;
5372         }
5373
5374         /* set interrupt vector for other causes */
5375         if (hw->mac.type == e1000_82575) {
5376                 tmpval = E1000_READ_REG(hw, E1000_CTRL_EXT);
5377                 /* enable MSI-X PBA support */
5378                 tmpval |= E1000_CTRL_EXT_PBA_CLR;
5379
5380                 /* Auto-Mask interrupts upon ICR read */
5381                 tmpval |= E1000_CTRL_EXT_EIAME;
5382                 tmpval |= E1000_CTRL_EXT_IRCA;
5383
5384                 E1000_WRITE_REG(hw, E1000_CTRL_EXT, tmpval);
5385
5386                 /* enable msix_other interrupt */
5387                 E1000_WRITE_REG_ARRAY(hw, E1000_MSIXBM(0), 0, E1000_EIMS_OTHER);
5388                 regval = E1000_READ_REG(hw, E1000_EIAC);
5389                 E1000_WRITE_REG(hw, E1000_EIAC, regval | E1000_EIMS_OTHER);
5390                 regval = E1000_READ_REG(hw, E1000_EIAM);
5391                 E1000_WRITE_REG(hw, E1000_EIMS, regval | E1000_EIMS_OTHER);
5392         } else if ((hw->mac.type == e1000_82576) ||
5393                         (hw->mac.type == e1000_82580) ||
5394                         (hw->mac.type == e1000_i350) ||
5395                         (hw->mac.type == e1000_i354) ||
5396                         (hw->mac.type == e1000_i210) ||
5397                         (hw->mac.type == e1000_i211)) {
5398                 /* turn on MSI-X capability first */
5399                 E1000_WRITE_REG(hw, E1000_GPIE, E1000_GPIE_MSIX_MODE |
5400                                         E1000_GPIE_PBA | E1000_GPIE_EIAME |
5401                                         E1000_GPIE_NSICR);
5402                 intr_mask = RTE_LEN2MASK(intr_handle->nb_efd, uint32_t) <<
5403                         misc_shift;
5404                 regval = E1000_READ_REG(hw, E1000_EIAC);
5405                 E1000_WRITE_REG(hw, E1000_EIAC, regval | intr_mask);
5406
5407                 /* enable msix_other interrupt */
5408                 regval = E1000_READ_REG(hw, E1000_EIMS);
5409                 E1000_WRITE_REG(hw, E1000_EIMS, regval | intr_mask);
5410                 tmpval = (dev->data->nb_rx_queues | E1000_IVAR_VALID) << 8;
5411                 E1000_WRITE_REG(hw, E1000_IVAR_MISC, tmpval);
5412         }
5413
5414         /* use EIAM to auto-mask when MSI-X interrupt
5415          * is asserted, this saves a register write for every interrupt
5416          */
5417         intr_mask = RTE_LEN2MASK(intr_handle->nb_efd, uint32_t) <<
5418                 misc_shift;
5419         regval = E1000_READ_REG(hw, E1000_EIAM);
5420         E1000_WRITE_REG(hw, E1000_EIAM, regval | intr_mask);
5421
5422         for (queue_id = 0; queue_id < dev->data->nb_rx_queues; queue_id++) {
5423                 eth_igb_assign_msix_vector(hw, 0, queue_id, vec);
5424                 intr_handle->intr_vec[queue_id] = vec;
5425                 if (vec < base + intr_handle->nb_efd - 1)
5426                         vec++;
5427         }
5428
5429         E1000_WRITE_FLUSH(hw);
5430 }
5431
5432 RTE_PMD_REGISTER_PCI(net_e1000_igb, rte_igb_pmd);
5433 RTE_PMD_REGISTER_PCI_TABLE(net_e1000_igb, pci_id_igb_map);
5434 RTE_PMD_REGISTER_KMOD_DEP(net_e1000_igb, "* igb_uio | uio_pci_generic | vfio-pci");
5435 RTE_PMD_REGISTER_PCI(net_e1000_igb_vf, rte_igbvf_pmd);
5436 RTE_PMD_REGISTER_PCI_TABLE(net_e1000_igb_vf, pci_id_igbvf_map);
5437 RTE_PMD_REGISTER_KMOD_DEP(net_e1000_igb_vf, "* igb_uio | vfio-pci");