drivers/net/e1000/igb_ethdev.c

   1 /*-
   2  *   BSD LICENSE
   3  *
   4  *   Copyright(c) 2010-2016 Intel Corporation. All rights reserved.
   5  *   All rights reserved.
   6  *
   7  *   Redistribution and use in source and binary forms, with or without
   8  *   modification, are permitted provided that the following conditions
   9  *   are met:
  10  *
  11  *     * Redistributions of source code must retain the above copyright
  12  *       notice, this list of conditions and the following disclaimer.
  13  *     * Redistributions in binary form must reproduce the above copyright
  14  *       notice, this list of conditions and the following disclaimer in
  15  *       the documentation and/or other materials provided with the
  16  *       distribution.
  17  *     * Neither the name of Intel Corporation nor the names of its
  18  *       contributors may be used to endorse or promote products derived
  19  *       from this software without specific prior written permission.
  20  *
  21  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 #include <sys/queue.h>
  35 #include <stdio.h>
  36 #include <errno.h>
  37 #include <stdint.h>
  38 #include <stdarg.h>
  39
  40 #include <rte_common.h>
  41 #include <rte_interrupts.h>
  42 #include <rte_byteorder.h>
  43 #include <rte_log.h>
  44 #include <rte_debug.h>
  45 #include <rte_pci.h>
  46 #include <rte_ether.h>
  47 #include <rte_ethdev.h>
  48 #include <rte_memory.h>
  49 #include <rte_memzone.h>
  50 #include <rte_eal.h>
  51 #include <rte_atomic.h>
  52 #include <rte_malloc.h>
  53 #include <rte_dev.h>
  54
  55 #include "e1000_logs.h"
  56 #include "base/e1000_api.h"
  57 #include "e1000_ethdev.h"
  58 #include "igb_regs.h"
  59
  60 /*
  61  * Default values for port configuration
  62  */
  63 #define IGB_DEFAULT_RX_FREE_THRESH  32
  64
  65 #define IGB_DEFAULT_RX_PTHRESH      ((hw->mac.type == e1000_i354) ? 12 : 8)
  66 #define IGB_DEFAULT_RX_HTHRESH      8
  67 #define IGB_DEFAULT_RX_WTHRESH      ((hw->mac.type == e1000_82576) ? 1 : 4)
  68
  69 #define IGB_DEFAULT_TX_PTHRESH      ((hw->mac.type == e1000_i354) ? 20 : 8)
  70 #define IGB_DEFAULT_TX_HTHRESH      1
  71 #define IGB_DEFAULT_TX_WTHRESH      ((hw->mac.type == e1000_82576) ? 1 : 16)
  72
  73 #define IGB_HKEY_MAX_INDEX 10
  74
  75 /* Bit shift and mask */
  76 #define IGB_4_BIT_WIDTH  (CHAR_BIT / 2)
  77 #define IGB_4_BIT_MASK   RTE_LEN2MASK(IGB_4_BIT_WIDTH, uint8_t)
  78 #define IGB_8_BIT_WIDTH  CHAR_BIT
  79 #define IGB_8_BIT_MASK   UINT8_MAX
  80
  81 /* Additional timesync values. */
  82 #define E1000_CYCLECOUNTER_MASK      0xffffffffffffffffULL
  83 #define E1000_ETQF_FILTER_1588       3
  84 #define IGB_82576_TSYNC_SHIFT        16
  85 #define E1000_INCPERIOD_82576        (1 << E1000_TIMINCA_16NS_SHIFT)
  86 #define E1000_INCVALUE_82576         (16 << IGB_82576_TSYNC_SHIFT)
  87 #define E1000_TSAUXC_DISABLE_SYSTIME 0x80000000
  88
  89 #define E1000_VTIVAR_MISC                0x01740
  90 #define E1000_VTIVAR_MISC_MASK           0xFF
  91 #define E1000_VTIVAR_VALID               0x80
  92 #define E1000_VTIVAR_MISC_MAILBOX        0
  93 #define E1000_VTIVAR_MISC_INTR_MASK      0x3
  94
  95 /* External VLAN Enable bit mask */
  96 #define E1000_CTRL_EXT_EXT_VLAN      (1 << 26)
  97
  98 /* External VLAN Ether Type bit mask and shift */
  99 #define E1000_VET_VET_EXT            0xFFFF0000
 100 #define E1000_VET_VET_EXT_SHIFT      16
 101
 102 static int  eth_igb_configure(struct rte_eth_dev *dev);
 103 static int  eth_igb_start(struct rte_eth_dev *dev);
 104 static void eth_igb_stop(struct rte_eth_dev *dev);
 105 static int  eth_igb_dev_set_link_up(struct rte_eth_dev *dev);
 106 static int  eth_igb_dev_set_link_down(struct rte_eth_dev *dev);
 107 static void eth_igb_close(struct rte_eth_dev *dev);
 108 static void eth_igb_promiscuous_enable(struct rte_eth_dev *dev);
 109 static void eth_igb_promiscuous_disable(struct rte_eth_dev *dev);
 110 static void eth_igb_allmulticast_enable(struct rte_eth_dev *dev);
 111 static void eth_igb_allmulticast_disable(struct rte_eth_dev *dev);
 112 static int  eth_igb_link_update(struct rte_eth_dev *dev,
 113                                 int wait_to_complete);
 114 static void eth_igb_stats_get(struct rte_eth_dev *dev,
 115                                 struct rte_eth_stats *rte_stats);
 116 static int eth_igb_xstats_get(struct rte_eth_dev *dev,
 117                               struct rte_eth_xstat *xstats, unsigned n);
 118 static int eth_igb_xstats_get_names(struct rte_eth_dev *dev,
 119                                     struct rte_eth_xstat_name *xstats_names,
 120                                     unsigned limit);
 121 static void eth_igb_stats_reset(struct rte_eth_dev *dev);
 122 static void eth_igb_xstats_reset(struct rte_eth_dev *dev);
 123 static void eth_igb_infos_get(struct rte_eth_dev *dev,
 124                               struct rte_eth_dev_info *dev_info);
 125 static const uint32_t *eth_igb_supported_ptypes_get(struct rte_eth_dev *dev);
 126 static void eth_igbvf_infos_get(struct rte_eth_dev *dev,
 127                                 struct rte_eth_dev_info *dev_info);
 128 static int  eth_igb_flow_ctrl_get(struct rte_eth_dev *dev,
 129                                 struct rte_eth_fc_conf *fc_conf);
 130 static int  eth_igb_flow_ctrl_set(struct rte_eth_dev *dev,
 131                                 struct rte_eth_fc_conf *fc_conf);
 132 static int eth_igb_lsc_interrupt_setup(struct rte_eth_dev *dev);
 133 static int eth_igb_rxq_interrupt_setup(struct rte_eth_dev *dev);
 134 static int eth_igb_interrupt_get_status(struct rte_eth_dev *dev);
 135 static int eth_igb_interrupt_action(struct rte_eth_dev *dev);
 136 static void eth_igb_interrupt_handler(struct rte_intr_handle *handle,
 137                                                         void *param);
 138 static int  igb_hardware_init(struct e1000_hw *hw);
 139 static void igb_hw_control_acquire(struct e1000_hw *hw);
 140 static void igb_hw_control_release(struct e1000_hw *hw);
 141 static void igb_init_manageability(struct e1000_hw *hw);
 142 static void igb_release_manageability(struct e1000_hw *hw);
 143
 144 static int  eth_igb_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
 145
 146 static int eth_igb_vlan_filter_set(struct rte_eth_dev *dev,
 147                 uint16_t vlan_id, int on);
 148 static int eth_igb_vlan_tpid_set(struct rte_eth_dev *dev,
 149                                  enum rte_vlan_type vlan_type,
 150                                  uint16_t tpid_id);
 151 static void eth_igb_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 152
 153 static void igb_vlan_hw_filter_enable(struct rte_eth_dev *dev);
 154 static void igb_vlan_hw_filter_disable(struct rte_eth_dev *dev);
 155 static void igb_vlan_hw_strip_enable(struct rte_eth_dev *dev);
 156 static void igb_vlan_hw_strip_disable(struct rte_eth_dev *dev);
 157 static void igb_vlan_hw_extend_enable(struct rte_eth_dev *dev);
 158 static void igb_vlan_hw_extend_disable(struct rte_eth_dev *dev);
 159
 160 static int eth_igb_led_on(struct rte_eth_dev *dev);
 161 static int eth_igb_led_off(struct rte_eth_dev *dev);
 162
 163 static void igb_intr_disable(struct e1000_hw *hw);
 164 static int  igb_get_rx_buffer_size(struct e1000_hw *hw);
 165 static void eth_igb_rar_set(struct rte_eth_dev *dev,
 166                 struct ether_addr *mac_addr,
 167                 uint32_t index, uint32_t pool);
 168 static void eth_igb_rar_clear(struct rte_eth_dev *dev, uint32_t index);
 169 static void eth_igb_default_mac_addr_set(struct rte_eth_dev *dev,
 170                 struct ether_addr *addr);
 171
 172 static void igbvf_intr_disable(struct e1000_hw *hw);
 173 static int igbvf_dev_configure(struct rte_eth_dev *dev);
 174 static int igbvf_dev_start(struct rte_eth_dev *dev);
 175 static void igbvf_dev_stop(struct rte_eth_dev *dev);
 176 static void igbvf_dev_close(struct rte_eth_dev *dev);
 177 static void igbvf_promiscuous_enable(struct rte_eth_dev *dev);
 178 static void igbvf_promiscuous_disable(struct rte_eth_dev *dev);
 179 static void igbvf_allmulticast_enable(struct rte_eth_dev *dev);
 180 static void igbvf_allmulticast_disable(struct rte_eth_dev *dev);
 181 static int eth_igbvf_link_update(struct e1000_hw *hw);
 182 static void eth_igbvf_stats_get(struct rte_eth_dev *dev,
 183                                 struct rte_eth_stats *rte_stats);
 184 static int eth_igbvf_xstats_get(struct rte_eth_dev *dev,
 185                                 struct rte_eth_xstat *xstats, unsigned n);
 186 static int eth_igbvf_xstats_get_names(struct rte_eth_dev *dev,
 187                                       struct rte_eth_xstat_name *xstats_names,
 188                                       unsigned limit);
 189 static void eth_igbvf_stats_reset(struct rte_eth_dev *dev);
 190 static int igbvf_vlan_filter_set(struct rte_eth_dev *dev,
 191                 uint16_t vlan_id, int on);
 192 static int igbvf_set_vfta(struct e1000_hw *hw, uint16_t vid, bool on);
 193 static void igbvf_set_vfta_all(struct rte_eth_dev *dev, bool on);
 194 static void igbvf_default_mac_addr_set(struct rte_eth_dev *dev,
 195                 struct ether_addr *addr);
 196 static int igbvf_get_reg_length(struct rte_eth_dev *dev);
 197 static int igbvf_get_regs(struct rte_eth_dev *dev,
 198                 struct rte_dev_reg_info *regs);
 199
 200 static int eth_igb_rss_reta_update(struct rte_eth_dev *dev,
 201                                    struct rte_eth_rss_reta_entry64 *reta_conf,
 202                                    uint16_t reta_size);
 203 static int eth_igb_rss_reta_query(struct rte_eth_dev *dev,
 204                                   struct rte_eth_rss_reta_entry64 *reta_conf,
 205                                   uint16_t reta_size);
 206
 207 static int eth_igb_syn_filter_set(struct rte_eth_dev *dev,
 208                         struct rte_eth_syn_filter *filter,
 209                         bool add);
 210 static int eth_igb_syn_filter_get(struct rte_eth_dev *dev,
 211                         struct rte_eth_syn_filter *filter);
 212 static int eth_igb_syn_filter_handle(struct rte_eth_dev *dev,
 213                         enum rte_filter_op filter_op,
 214                         void *arg);
 215 static int igb_add_2tuple_filter(struct rte_eth_dev *dev,
 216                         struct rte_eth_ntuple_filter *ntuple_filter);
 217 static int igb_remove_2tuple_filter(struct rte_eth_dev *dev,
 218                         struct rte_eth_ntuple_filter *ntuple_filter);
 219 static int eth_igb_add_del_flex_filter(struct rte_eth_dev *dev,
 220                         struct rte_eth_flex_filter *filter,
 221                         bool add);
 222 static int eth_igb_get_flex_filter(struct rte_eth_dev *dev,
 223                         struct rte_eth_flex_filter *filter);
 224 static int eth_igb_flex_filter_handle(struct rte_eth_dev *dev,
 225                         enum rte_filter_op filter_op,
 226                         void *arg);
 227 static int igb_add_5tuple_filter_82576(struct rte_eth_dev *dev,
 228                         struct rte_eth_ntuple_filter *ntuple_filter);
 229 static int igb_remove_5tuple_filter_82576(struct rte_eth_dev *dev,
 230                         struct rte_eth_ntuple_filter *ntuple_filter);
 231 static int igb_add_del_ntuple_filter(struct rte_eth_dev *dev,
 232                         struct rte_eth_ntuple_filter *filter,
 233                         bool add);
 234 static int igb_get_ntuple_filter(struct rte_eth_dev *dev,
 235                         struct rte_eth_ntuple_filter *filter);
 236 static int igb_ntuple_filter_handle(struct rte_eth_dev *dev,
 237                                 enum rte_filter_op filter_op,
 238                                 void *arg);
 239 static int igb_add_del_ethertype_filter(struct rte_eth_dev *dev,
 240                         struct rte_eth_ethertype_filter *filter,
 241                         bool add);
 242 static int igb_ethertype_filter_handle(struct rte_eth_dev *dev,
 243                                 enum rte_filter_op filter_op,
 244                                 void *arg);
 245 static int igb_get_ethertype_filter(struct rte_eth_dev *dev,
 246                         struct rte_eth_ethertype_filter *filter);
 247 static int eth_igb_filter_ctrl(struct rte_eth_dev *dev,
 248                      enum rte_filter_type filter_type,
 249                      enum rte_filter_op filter_op,
 250                      void *arg);
 251 static int eth_igb_get_reg_length(struct rte_eth_dev *dev);
 252 static int eth_igb_get_regs(struct rte_eth_dev *dev,
 253                 struct rte_dev_reg_info *regs);
 254 static int eth_igb_get_eeprom_length(struct rte_eth_dev *dev);
 255 static int eth_igb_get_eeprom(struct rte_eth_dev *dev,
 256                 struct rte_dev_eeprom_info *eeprom);
 257 static int eth_igb_set_eeprom(struct rte_eth_dev *dev,
 258                 struct rte_dev_eeprom_info *eeprom);
 259 static int eth_igb_set_mc_addr_list(struct rte_eth_dev *dev,
 260                                     struct ether_addr *mc_addr_set,
 261                                     uint32_t nb_mc_addr);
 262 static int igb_timesync_enable(struct rte_eth_dev *dev);
 263 static int igb_timesync_disable(struct rte_eth_dev *dev);
 264 static int igb_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
 265                                           struct timespec *timestamp,
 266                                           uint32_t flags);
 267 static int igb_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
 268                                           struct timespec *timestamp);
 269 static int igb_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);
 270 static int igb_timesync_read_time(struct rte_eth_dev *dev,
 271                                   struct timespec *timestamp);
 272 static int igb_timesync_write_time(struct rte_eth_dev *dev,
 273                                    const struct timespec *timestamp);
 274 static int eth_igb_rx_queue_intr_enable(struct rte_eth_dev *dev,
 275                                         uint16_t queue_id);
 276 static int eth_igb_rx_queue_intr_disable(struct rte_eth_dev *dev,
 277                                          uint16_t queue_id);
 278 static void eth_igb_assign_msix_vector(struct e1000_hw *hw, int8_t direction,
 279                                        uint8_t queue, uint8_t msix_vector);
 280 static void eth_igb_write_ivar(struct e1000_hw *hw, uint8_t msix_vector,
 281                                uint8_t index, uint8_t offset);
 282 static void eth_igb_configure_msix_intr(struct rte_eth_dev *dev);
 283 static void eth_igbvf_interrupt_handler(struct rte_intr_handle *handle,
 284                                         void *param);
 285 static void igbvf_mbx_process(struct rte_eth_dev *dev);
 286
 287 /*
 288  * Define VF Stats MACRO for Non "cleared on read" register
 289  */
 290 #define UPDATE_VF_STAT(reg, last, cur)            \
 291 {                                                 \
 292         u32 latest = E1000_READ_REG(hw, reg);     \
 293         cur += (latest - last) & UINT_MAX;        \
 294         last = latest;                            \
 295 }
 296
 297 #define IGB_FC_PAUSE_TIME 0x0680
 298 #define IGB_LINK_UPDATE_CHECK_TIMEOUT  90  /* 9s */
 299 #define IGB_LINK_UPDATE_CHECK_INTERVAL 100 /* ms */
 300
 301 #define IGBVF_PMD_NAME "rte_igbvf_pmd"     /* PMD name */
 302
 303 static enum e1000_fc_mode igb_fc_setting = e1000_fc_full;
 304
 305 /*
 306  * The set of PCI devices this driver supports
 307  */
 308 static const struct rte_pci_id pci_id_igb_map[] = {
 309
 310 #define RTE_PCI_DEV_ID_DECL_IGB(vend, dev) {RTE_PCI_DEVICE(vend, dev)},
 311 #include "rte_pci_dev_ids.h"
 312
 313 {0},
 314 };
 315
 316 /*
 317  * The set of PCI devices this driver supports (for 82576&I350 VF)
 318  */
 319 static const struct rte_pci_id pci_id_igbvf_map[] = {
 320
 321 #define RTE_PCI_DEV_ID_DECL_IGBVF(vend, dev) {RTE_PCI_DEVICE(vend, dev)},
 322 #include "rte_pci_dev_ids.h"
 323
 324 {0},
 325 };
 326
 327 static const struct rte_eth_desc_lim rx_desc_lim = {
 328         .nb_max = E1000_MAX_RING_DESC,
 329         .nb_min = E1000_MIN_RING_DESC,
 330         .nb_align = IGB_RXD_ALIGN,
 331 };
 332
 333 static const struct rte_eth_desc_lim tx_desc_lim = {
 334         .nb_max = E1000_MAX_RING_DESC,
 335         .nb_min = E1000_MIN_RING_DESC,
 336         .nb_align = IGB_RXD_ALIGN,
 337 };
 338
 339 static const struct eth_dev_ops eth_igb_ops = {
 340         .dev_configure        = eth_igb_configure,
 341         .dev_start            = eth_igb_start,
 342         .dev_stop             = eth_igb_stop,
 343         .dev_set_link_up      = eth_igb_dev_set_link_up,
 344         .dev_set_link_down    = eth_igb_dev_set_link_down,
 345         .dev_close            = eth_igb_close,
 346         .promiscuous_enable   = eth_igb_promiscuous_enable,
 347         .promiscuous_disable  = eth_igb_promiscuous_disable,
 348         .allmulticast_enable  = eth_igb_allmulticast_enable,
 349         .allmulticast_disable = eth_igb_allmulticast_disable,
 350         .link_update          = eth_igb_link_update,
 351         .stats_get            = eth_igb_stats_get,
 352         .xstats_get           = eth_igb_xstats_get,
 353         .xstats_get_names     = eth_igb_xstats_get_names,
 354         .stats_reset          = eth_igb_stats_reset,
 355         .xstats_reset         = eth_igb_xstats_reset,
 356         .dev_infos_get        = eth_igb_infos_get,
 357         .dev_supported_ptypes_get = eth_igb_supported_ptypes_get,
 358         .mtu_set              = eth_igb_mtu_set,
 359         .vlan_filter_set      = eth_igb_vlan_filter_set,
 360         .vlan_tpid_set        = eth_igb_vlan_tpid_set,
 361         .vlan_offload_set     = eth_igb_vlan_offload_set,
 362         .rx_queue_setup       = eth_igb_rx_queue_setup,
 363         .rx_queue_intr_enable = eth_igb_rx_queue_intr_enable,
 364         .rx_queue_intr_disable = eth_igb_rx_queue_intr_disable,
 365         .rx_queue_release     = eth_igb_rx_queue_release,
 366         .rx_queue_count       = eth_igb_rx_queue_count,
 367         .rx_descriptor_done   = eth_igb_rx_descriptor_done,
 368         .tx_queue_setup       = eth_igb_tx_queue_setup,
 369         .tx_queue_release     = eth_igb_tx_queue_release,
 370         .dev_led_on           = eth_igb_led_on,
 371         .dev_led_off          = eth_igb_led_off,
 372         .flow_ctrl_get        = eth_igb_flow_ctrl_get,
 373         .flow_ctrl_set        = eth_igb_flow_ctrl_set,
 374         .mac_addr_add         = eth_igb_rar_set,
 375         .mac_addr_remove      = eth_igb_rar_clear,
 376         .mac_addr_set         = eth_igb_default_mac_addr_set,
 377         .reta_update          = eth_igb_rss_reta_update,
 378         .reta_query           = eth_igb_rss_reta_query,
 379         .rss_hash_update      = eth_igb_rss_hash_update,
 380         .rss_hash_conf_get    = eth_igb_rss_hash_conf_get,
 381         .filter_ctrl          = eth_igb_filter_ctrl,
 382         .set_mc_addr_list     = eth_igb_set_mc_addr_list,
 383         .rxq_info_get         = igb_rxq_info_get,
 384         .txq_info_get         = igb_txq_info_get,
 385         .timesync_enable      = igb_timesync_enable,
 386         .timesync_disable     = igb_timesync_disable,
 387         .timesync_read_rx_timestamp = igb_timesync_read_rx_timestamp,
 388         .timesync_read_tx_timestamp = igb_timesync_read_tx_timestamp,
 389         .get_reg_length       = eth_igb_get_reg_length,
 390         .get_reg              = eth_igb_get_regs,
 391         .get_eeprom_length    = eth_igb_get_eeprom_length,
 392         .get_eeprom           = eth_igb_get_eeprom,
 393         .set_eeprom           = eth_igb_set_eeprom,
 394         .timesync_adjust_time = igb_timesync_adjust_time,
 395         .timesync_read_time   = igb_timesync_read_time,
 396         .timesync_write_time  = igb_timesync_write_time,
 397 };
 398
 399 /*
 400  * dev_ops for virtual function, bare necessities for basic vf
 401  * operation have been implemented
 402  */
 403 static const struct eth_dev_ops igbvf_eth_dev_ops = {
 404         .dev_configure        = igbvf_dev_configure,
 405         .dev_start            = igbvf_dev_start,
 406         .dev_stop             = igbvf_dev_stop,
 407         .dev_close            = igbvf_dev_close,
 408         .promiscuous_enable   = igbvf_promiscuous_enable,
 409         .promiscuous_disable  = igbvf_promiscuous_disable,
 410         .allmulticast_enable  = igbvf_allmulticast_enable,
 411         .allmulticast_disable = igbvf_allmulticast_disable,
 412         .link_update          = eth_igb_link_update,
 413         .stats_get            = eth_igbvf_stats_get,
 414         .xstats_get           = eth_igbvf_xstats_get,
 415         .xstats_get_names     = eth_igbvf_xstats_get_names,
 416         .stats_reset          = eth_igbvf_stats_reset,
 417         .xstats_reset         = eth_igbvf_stats_reset,
 418         .vlan_filter_set      = igbvf_vlan_filter_set,
 419         .dev_infos_get        = eth_igbvf_infos_get,
 420         .dev_supported_ptypes_get = eth_igb_supported_ptypes_get,
 421         .rx_queue_setup       = eth_igb_rx_queue_setup,
 422         .rx_queue_release     = eth_igb_rx_queue_release,
 423         .tx_queue_setup       = eth_igb_tx_queue_setup,
 424         .tx_queue_release     = eth_igb_tx_queue_release,
 425         .set_mc_addr_list     = eth_igb_set_mc_addr_list,
 426         .rxq_info_get         = igb_rxq_info_get,
 427         .txq_info_get         = igb_txq_info_get,
 428         .mac_addr_set         = igbvf_default_mac_addr_set,
 429         .get_reg_length       = igbvf_get_reg_length,
 430         .get_reg              = igbvf_get_regs,
 431 };
 432
 433 /* store statistics names and its offset in stats structure */
 434 struct rte_igb_xstats_name_off {
 435         char name[RTE_ETH_XSTATS_NAME_SIZE];
 436         unsigned offset;
 437 };
 438
 439 static const struct rte_igb_xstats_name_off rte_igb_stats_strings[] = {
 440         {"rx_crc_errors", offsetof(struct e1000_hw_stats, crcerrs)},
 441         {"rx_align_errors", offsetof(struct e1000_hw_stats, algnerrc)},
 442         {"rx_symbol_errors", offsetof(struct e1000_hw_stats, symerrs)},
 443         {"rx_missed_packets", offsetof(struct e1000_hw_stats, mpc)},
 444         {"tx_single_collision_packets", offsetof(struct e1000_hw_stats, scc)},
 445         {"tx_multiple_collision_packets", offsetof(struct e1000_hw_stats, mcc)},
 446         {"tx_excessive_collision_packets", offsetof(struct e1000_hw_stats,
 447                 ecol)},
 448         {"tx_late_collisions", offsetof(struct e1000_hw_stats, latecol)},
 449         {"tx_total_collisions", offsetof(struct e1000_hw_stats, colc)},
 450         {"tx_deferred_packets", offsetof(struct e1000_hw_stats, dc)},
 451         {"tx_no_carrier_sense_packets", offsetof(struct e1000_hw_stats, tncrs)},
 452         {"rx_carrier_ext_errors", offsetof(struct e1000_hw_stats, cexterr)},
 453         {"rx_length_errors", offsetof(struct e1000_hw_stats, rlec)},
 454         {"rx_xon_packets", offsetof(struct e1000_hw_stats, xonrxc)},
 455         {"tx_xon_packets", offsetof(struct e1000_hw_stats, xontxc)},
 456         {"rx_xoff_packets", offsetof(struct e1000_hw_stats, xoffrxc)},
 457         {"tx_xoff_packets", offsetof(struct e1000_hw_stats, xofftxc)},
 458         {"rx_flow_control_unsupported_packets", offsetof(struct e1000_hw_stats,
 459                 fcruc)},
 460         {"rx_size_64_packets", offsetof(struct e1000_hw_stats, prc64)},
 461         {"rx_size_65_to_127_packets", offsetof(struct e1000_hw_stats, prc127)},
 462         {"rx_size_128_to_255_packets", offsetof(struct e1000_hw_stats, prc255)},
 463         {"rx_size_256_to_511_packets", offsetof(struct e1000_hw_stats, prc511)},
 464         {"rx_size_512_to_1023_packets", offsetof(struct e1000_hw_stats,
 465                 prc1023)},
 466         {"rx_size_1024_to_max_packets", offsetof(struct e1000_hw_stats,
 467                 prc1522)},
 468         {"rx_broadcast_packets", offsetof(struct e1000_hw_stats, bprc)},
 469         {"rx_multicast_packets", offsetof(struct e1000_hw_stats, mprc)},
 470         {"rx_undersize_errors", offsetof(struct e1000_hw_stats, ruc)},
 471         {"rx_fragment_errors", offsetof(struct e1000_hw_stats, rfc)},
 472         {"rx_oversize_errors", offsetof(struct e1000_hw_stats, roc)},
 473         {"rx_jabber_errors", offsetof(struct e1000_hw_stats, rjc)},
 474         {"rx_management_packets", offsetof(struct e1000_hw_stats, mgprc)},
 475         {"rx_management_dropped", offsetof(struct e1000_hw_stats, mgpdc)},
 476         {"tx_management_packets", offsetof(struct e1000_hw_stats, mgptc)},
 477         {"rx_total_packets", offsetof(struct e1000_hw_stats, tpr)},
 478         {"tx_total_packets", offsetof(struct e1000_hw_stats, tpt)},
 479         {"rx_total_bytes", offsetof(struct e1000_hw_stats, tor)},
 480         {"tx_total_bytes", offsetof(struct e1000_hw_stats, tot)},
 481         {"tx_size_64_packets", offsetof(struct e1000_hw_stats, ptc64)},
 482         {"tx_size_65_to_127_packets", offsetof(struct e1000_hw_stats, ptc127)},
 483         {"tx_size_128_to_255_packets", offsetof(struct e1000_hw_stats, ptc255)},
 484         {"tx_size_256_to_511_packets", offsetof(struct e1000_hw_stats, ptc511)},
 485         {"tx_size_512_to_1023_packets", offsetof(struct e1000_hw_stats,
 486                 ptc1023)},
 487         {"tx_size_1023_to_max_packets", offsetof(struct e1000_hw_stats,
 488                 ptc1522)},
 489         {"tx_multicast_packets", offsetof(struct e1000_hw_stats, mptc)},
 490         {"tx_broadcast_packets", offsetof(struct e1000_hw_stats, bptc)},
 491         {"tx_tso_packets", offsetof(struct e1000_hw_stats, tsctc)},
 492         {"tx_tso_errors", offsetof(struct e1000_hw_stats, tsctfc)},
 493         {"rx_sent_to_host_packets", offsetof(struct e1000_hw_stats, rpthc)},
 494         {"tx_sent_by_host_packets", offsetof(struct e1000_hw_stats, hgptc)},
 495         {"rx_code_violation_packets", offsetof(struct e1000_hw_stats, scvpc)},
 496
 497         {"interrupt_assert_count", offsetof(struct e1000_hw_stats, iac)},
 498 };
 499
 500 #define IGB_NB_XSTATS (sizeof(rte_igb_stats_strings) / \
 501                 sizeof(rte_igb_stats_strings[0]))
 502
 503 static const struct rte_igb_xstats_name_off rte_igbvf_stats_strings[] = {
 504         {"rx_multicast_packets", offsetof(struct e1000_vf_stats, mprc)},
 505         {"rx_good_loopback_packets", offsetof(struct e1000_vf_stats, gprlbc)},
 506         {"tx_good_loopback_packets", offsetof(struct e1000_vf_stats, gptlbc)},
 507         {"rx_good_loopback_bytes", offsetof(struct e1000_vf_stats, gorlbc)},
 508         {"tx_good_loopback_bytes", offsetof(struct e1000_vf_stats, gotlbc)},
 509 };
 510
 511 #define IGBVF_NB_XSTATS (sizeof(rte_igbvf_stats_strings) / \
 512                 sizeof(rte_igbvf_stats_strings[0]))
 513
 514 /**
 515  * Atomically reads the link status information from global
 516  * structure rte_eth_dev.
 517  *
 518  * @param dev
 519  *   - Pointer to the structure rte_eth_dev to read from.
 520  *   - Pointer to the buffer to be saved with the link status.
 521  *
 522  * @return
 523  *   - On success, zero.
 524  *   - On failure, negative value.
 525  */
 526 static inline int
 527 rte_igb_dev_atomic_read_link_status(struct rte_eth_dev *dev,
 528                                 struct rte_eth_link *link)
 529 {
 530         struct rte_eth_link *dst = link;
 531         struct rte_eth_link *src = &(dev->data->dev_link);
 532
 533         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 534                                         *(uint64_t *)src) == 0)
 535                 return -1;
 536
 537         return 0;
 538 }
 539
 540 /**
 541  * Atomically writes the link status information into global
 542  * structure rte_eth_dev.
 543  *
 544  * @param dev
 545  *   - Pointer to the structure rte_eth_dev to read from.
 546  *   - Pointer to the buffer to be saved with the link status.
 547  *
 548  * @return
 549  *   - On success, zero.
 550  *   - On failure, negative value.
 551  */
 552 static inline int
 553 rte_igb_dev_atomic_write_link_status(struct rte_eth_dev *dev,
 554                                 struct rte_eth_link *link)
 555 {
 556         struct rte_eth_link *dst = &(dev->data->dev_link);
 557         struct rte_eth_link *src = link;
 558
 559         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 560                                         *(uint64_t *)src) == 0)
 561                 return -1;
 562
 563         return 0;
 564 }
 565
 566 static inline void
 567 igb_intr_enable(struct rte_eth_dev *dev)
 568 {
 569         struct e1000_interrupt *intr =
 570                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
 571         struct e1000_hw *hw =
 572                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 573
 574         E1000_WRITE_REG(hw, E1000_IMS, intr->mask);
 575         E1000_WRITE_FLUSH(hw);
 576 }
 577
 578 static void
 579 igb_intr_disable(struct e1000_hw *hw)
 580 {
 581         E1000_WRITE_REG(hw, E1000_IMC, ~0);
 582         E1000_WRITE_FLUSH(hw);
 583 }
 584
 585 static inline void
 586 igbvf_intr_enable(struct rte_eth_dev *dev)
 587 {
 588         struct e1000_hw *hw =
 589                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 590
 591         /* only for mailbox */
 592         E1000_WRITE_REG(hw, E1000_EIAM, 1 << E1000_VTIVAR_MISC_MAILBOX);
 593         E1000_WRITE_REG(hw, E1000_EIAC, 1 << E1000_VTIVAR_MISC_MAILBOX);
 594         E1000_WRITE_REG(hw, E1000_EIMS, 1 << E1000_VTIVAR_MISC_MAILBOX);
 595         E1000_WRITE_FLUSH(hw);
 596 }
 597
 598 /* only for mailbox now. If RX/TX needed, should extend this function.  */
 599 static void
 600 igbvf_set_ivar_map(struct e1000_hw *hw, uint8_t msix_vector)
 601 {
 602         uint32_t tmp = 0;
 603
 604         /* mailbox */
 605         tmp |= (msix_vector & E1000_VTIVAR_MISC_INTR_MASK);
 606         tmp |= E1000_VTIVAR_VALID;
 607         E1000_WRITE_REG(hw, E1000_VTIVAR_MISC, tmp);
 608 }
 609
 610 static void
 611 eth_igbvf_configure_msix_intr(struct rte_eth_dev *dev)
 612 {
 613         struct e1000_hw *hw =
 614                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 615
 616         /* Configure VF other cause ivar */
 617         igbvf_set_ivar_map(hw, E1000_VTIVAR_MISC_MAILBOX);
 618 }
 619
 620 static inline int32_t
 621 igb_pf_reset_hw(struct e1000_hw *hw)
 622 {
 623         uint32_t ctrl_ext;
 624         int32_t status;
 625
 626         status = e1000_reset_hw(hw);
 627
 628         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
 629         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
 630         ctrl_ext |= E1000_CTRL_EXT_PFRSTD;
 631         E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
 632         E1000_WRITE_FLUSH(hw);
 633
 634         return status;
 635 }
 636
 637 static void
 638 igb_identify_hardware(struct rte_eth_dev *dev)
 639 {
 640         struct e1000_hw *hw =
 641                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 642
 643         hw->vendor_id = dev->pci_dev->id.vendor_id;
 644         hw->device_id = dev->pci_dev->id.device_id;
 645         hw->subsystem_vendor_id = dev->pci_dev->id.subsystem_vendor_id;
 646         hw->subsystem_device_id = dev->pci_dev->id.subsystem_device_id;
 647
 648         e1000_set_mac_type(hw);
 649
 650         /* need to check if it is a vf device below */
 651 }
 652
 653 static int
 654 igb_reset_swfw_lock(struct e1000_hw *hw)
 655 {
 656         int ret_val;
 657
 658         /*
 659          * Do mac ops initialization manually here, since we will need
 660          * some function pointers set by this call.
 661          */
 662         ret_val = e1000_init_mac_params(hw);
 663         if (ret_val)
 664                 return ret_val;
 665
 666         /*
 667          * SMBI lock should not fail in this early stage. If this is the case,
 668          * it is due to an improper exit of the application.
 669          * So force the release of the faulty lock.
 670          */
 671         if (e1000_get_hw_semaphore_generic(hw) < 0) {
 672                 PMD_DRV_LOG(DEBUG, "SMBI lock released");
 673         }
 674         e1000_put_hw_semaphore_generic(hw);
 675
 676         if (hw->mac.ops.acquire_swfw_sync != NULL) {
 677                 uint16_t mask;
 678
 679                 /*
 680                  * Phy lock should not fail in this early stage. If this is the case,
 681                  * it is due to an improper exit of the application.
 682                  * So force the release of the faulty lock.
 683                  */
 684                 mask = E1000_SWFW_PHY0_SM << hw->bus.func;
 685                 if (hw->bus.func > E1000_FUNC_1)
 686                         mask <<= 2;
 687                 if (hw->mac.ops.acquire_swfw_sync(hw, mask) < 0) {
 688                         PMD_DRV_LOG(DEBUG, "SWFW phy%d lock released",
 689                                     hw->bus.func);
 690                 }
 691                 hw->mac.ops.release_swfw_sync(hw, mask);
 692
 693                 /*
 694                  * This one is more tricky since it is common to all ports; but
 695                  * swfw_sync retries last long enough (1s) to be almost sure that if
 696                  * lock can not be taken it is due to an improper lock of the
 697                  * semaphore.
 698                  */
 699                 mask = E1000_SWFW_EEP_SM;
 700                 if (hw->mac.ops.acquire_swfw_sync(hw, mask) < 0) {
 701                         PMD_DRV_LOG(DEBUG, "SWFW common locks released");
 702                 }
 703                 hw->mac.ops.release_swfw_sync(hw, mask);
 704         }
 705
 706         return E1000_SUCCESS;
 707 }
 708
 709 static int
 710 eth_igb_dev_init(struct rte_eth_dev *eth_dev)
 711 {
 712         int error = 0;
 713         struct rte_pci_device *pci_dev;
 714         struct e1000_hw *hw =
 715                 E1000_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 716         struct e1000_vfta * shadow_vfta =
 717                 E1000_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
 718         struct e1000_filter_info *filter_info =
 719                 E1000_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
 720         struct e1000_adapter *adapter =
 721                 E1000_DEV_PRIVATE(eth_dev->data->dev_private);
 722
 723         uint32_t ctrl_ext;
 724
 725         pci_dev = eth_dev->pci_dev;
 726
 727         eth_dev->dev_ops = &eth_igb_ops;
 728         eth_dev->rx_pkt_burst = &eth_igb_recv_pkts;
 729         eth_dev->tx_pkt_burst = &eth_igb_xmit_pkts;
 730
 731         /* for secondary processes, we don't initialise any further as primary
 732          * has already done this work. Only check we don't need a different
 733          * RX function */
 734         if (rte_eal_process_type() != RTE_PROC_PRIMARY){
 735                 if (eth_dev->data->scattered_rx)
 736                         eth_dev->rx_pkt_burst = &eth_igb_recv_scattered_pkts;
 737                 return 0;
 738         }
 739
 740         rte_eth_copy_pci_info(eth_dev, pci_dev);
 741
 742         hw->hw_addr= (void *)pci_dev->mem_resource[0].addr;
 743
 744         igb_identify_hardware(eth_dev);
 745         if (e1000_setup_init_funcs(hw, FALSE) != E1000_SUCCESS) {
 746                 error = -EIO;
 747                 goto err_late;
 748         }
 749
 750         e1000_get_bus_info(hw);
 751
 752         /* Reset any pending lock */
 753         if (igb_reset_swfw_lock(hw) != E1000_SUCCESS) {
 754                 error = -EIO;
 755                 goto err_late;
 756         }
 757
 758         /* Finish initialization */
 759         if (e1000_setup_init_funcs(hw, TRUE) != E1000_SUCCESS) {
 760                 error = -EIO;
 761                 goto err_late;
 762         }
 763
 764         hw->mac.autoneg = 1;
 765         hw->phy.autoneg_wait_to_complete = 0;
 766         hw->phy.autoneg_advertised = E1000_ALL_SPEED_DUPLEX;
 767
 768         /* Copper options */
 769         if (hw->phy.media_type == e1000_media_type_copper) {
 770                 hw->phy.mdix = 0; /* AUTO_ALL_MODES */
 771                 hw->phy.disable_polarity_correction = 0;
 772                 hw->phy.ms_type = e1000_ms_hw_default;
 773         }
 774
 775         /*
 776          * Start from a known state, this is important in reading the nvm
 777          * and mac from that.
 778          */
 779         igb_pf_reset_hw(hw);
 780
 781         /* Make sure we have a good EEPROM before we read from it */
 782         if (e1000_validate_nvm_checksum(hw) < 0) {
 783                 /*
 784                  * Some PCI-E parts fail the first check due to
 785                  * the link being in sleep state, call it again,
 786                  * if it fails a second time its a real issue.
 787                  */
 788                 if (e1000_validate_nvm_checksum(hw) < 0) {
 789                         PMD_INIT_LOG(ERR, "EEPROM checksum invalid");
 790                         error = -EIO;
 791                         goto err_late;
 792                 }
 793         }
 794
 795         /* Read the permanent MAC address out of the EEPROM */
 796         if (e1000_read_mac_addr(hw) != 0) {
 797                 PMD_INIT_LOG(ERR, "EEPROM error while reading MAC address");
 798                 error = -EIO;
 799                 goto err_late;
 800         }
 801
 802         /* Allocate memory for storing MAC addresses */
 803         eth_dev->data->mac_addrs = rte_zmalloc("e1000",
 804                 ETHER_ADDR_LEN * hw->mac.rar_entry_count, 0);
 805         if (eth_dev->data->mac_addrs == NULL) {
 806                 PMD_INIT_LOG(ERR, "Failed to allocate %d bytes needed to "
 807                                                 "store MAC addresses",
 808                                 ETHER_ADDR_LEN * hw->mac.rar_entry_count);
 809                 error = -ENOMEM;
 810                 goto err_late;
 811         }
 812
 813         /* Copy the permanent MAC address */
 814         ether_addr_copy((struct ether_addr *)hw->mac.addr, &eth_dev->data->mac_addrs[0]);
 815
 816         /* initialize the vfta */
 817         memset(shadow_vfta, 0, sizeof(*shadow_vfta));
 818
 819         /* Now initialize the hardware */
 820         if (igb_hardware_init(hw) != 0) {
 821                 PMD_INIT_LOG(ERR, "Hardware initialization failed");
 822                 rte_free(eth_dev->data->mac_addrs);
 823                 eth_dev->data->mac_addrs = NULL;
 824                 error = -ENODEV;
 825                 goto err_late;
 826         }
 827         hw->mac.get_link_status = 1;
 828         adapter->stopped = 0;
 829
 830         /* Indicate SOL/IDER usage */
 831         if (e1000_check_reset_block(hw) < 0) {
 832                 PMD_INIT_LOG(ERR, "PHY reset is blocked due to"
 833                                         "SOL/IDER session");
 834         }
 835
 836         /* initialize PF if max_vfs not zero */
 837         igb_pf_host_init(eth_dev);
 838
 839         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
 840         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
 841         ctrl_ext |= E1000_CTRL_EXT_PFRSTD;
 842         E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
 843         E1000_WRITE_FLUSH(hw);
 844
 845         PMD_INIT_LOG(DEBUG, "port_id %d vendorID=0x%x deviceID=0x%x",
 846                      eth_dev->data->port_id, pci_dev->id.vendor_id,
 847                      pci_dev->id.device_id);
 848
 849         rte_intr_callback_register(&pci_dev->intr_handle,
 850                                    eth_igb_interrupt_handler,
 851                                    (void *)eth_dev);
 852
 853         /* enable uio/vfio intr/eventfd mapping */
 854         rte_intr_enable(&pci_dev->intr_handle);
 855
 856         /* enable support intr */
 857         igb_intr_enable(eth_dev);
 858
 859         TAILQ_INIT(&filter_info->flex_list);
 860         filter_info->flex_mask = 0;
 861         TAILQ_INIT(&filter_info->twotuple_list);
 862         filter_info->twotuple_mask = 0;
 863         TAILQ_INIT(&filter_info->fivetuple_list);
 864         filter_info->fivetuple_mask = 0;
 865
 866         return 0;
 867
 868 err_late:
 869         igb_hw_control_release(hw);
 870
 871         return error;
 872 }
 873
 874 static int
 875 eth_igb_dev_uninit(struct rte_eth_dev *eth_dev)
 876 {
 877         struct rte_pci_device *pci_dev;
 878         struct e1000_hw *hw;
 879         struct e1000_adapter *adapter =
 880                 E1000_DEV_PRIVATE(eth_dev->data->dev_private);
 881
 882         PMD_INIT_FUNC_TRACE();
 883
 884         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
 885                 return -EPERM;
 886
 887         hw = E1000_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 888         pci_dev = eth_dev->pci_dev;
 889
 890         if (adapter->stopped == 0)
 891                 eth_igb_close(eth_dev);
 892
 893         eth_dev->dev_ops = NULL;
 894         eth_dev->rx_pkt_burst = NULL;
 895         eth_dev->tx_pkt_burst = NULL;
 896
 897         /* Reset any pending lock */
 898         igb_reset_swfw_lock(hw);
 899
 900         rte_free(eth_dev->data->mac_addrs);
 901         eth_dev->data->mac_addrs = NULL;
 902
 903         /* uninitialize PF if max_vfs not zero */
 904         igb_pf_host_uninit(eth_dev);
 905
 906         /* disable uio intr before callback unregister */
 907         rte_intr_disable(&(pci_dev->intr_handle));
 908         rte_intr_callback_unregister(&(pci_dev->intr_handle),
 909                 eth_igb_interrupt_handler, (void *)eth_dev);
 910
 911         return 0;
 912 }
 913
 914 /*
 915  * Virtual Function device init
 916  */
 917 static int
 918 eth_igbvf_dev_init(struct rte_eth_dev *eth_dev)
 919 {
 920         struct rte_pci_device *pci_dev;
 921         struct e1000_adapter *adapter =
 922                 E1000_DEV_PRIVATE(eth_dev->data->dev_private);
 923         struct e1000_hw *hw =
 924                 E1000_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 925         int diag;
 926         struct ether_addr *perm_addr = (struct ether_addr *)hw->mac.perm_addr;
 927
 928         PMD_INIT_FUNC_TRACE();
 929
 930         eth_dev->dev_ops = &igbvf_eth_dev_ops;
 931         eth_dev->rx_pkt_burst = &eth_igb_recv_pkts;
 932         eth_dev->tx_pkt_burst = &eth_igb_xmit_pkts;
 933
 934         /* for secondary processes, we don't initialise any further as primary
 935          * has already done this work. Only check we don't need a different
 936          * RX function */
 937         if (rte_eal_process_type() != RTE_PROC_PRIMARY){
 938                 if (eth_dev->data->scattered_rx)
 939                         eth_dev->rx_pkt_burst = &eth_igb_recv_scattered_pkts;
 940                 return 0;
 941         }
 942
 943         pci_dev = eth_dev->pci_dev;
 944
 945         rte_eth_copy_pci_info(eth_dev, pci_dev);
 946
 947         hw->device_id = pci_dev->id.device_id;
 948         hw->vendor_id = pci_dev->id.vendor_id;
 949         hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
 950         adapter->stopped = 0;
 951
 952         /* Initialize the shared code (base driver) */
 953         diag = e1000_setup_init_funcs(hw, TRUE);
 954         if (diag != 0) {
 955                 PMD_INIT_LOG(ERR, "Shared code init failed for igbvf: %d",
 956                         diag);
 957                 return -EIO;
 958         }
 959
 960         /* init_mailbox_params */
 961         hw->mbx.ops.init_params(hw);
 962
 963         /* Disable the interrupts for VF */
 964         igbvf_intr_disable(hw);
 965
 966         diag = hw->mac.ops.reset_hw(hw);
 967
 968         /* Allocate memory for storing MAC addresses */
 969         eth_dev->data->mac_addrs = rte_zmalloc("igbvf", ETHER_ADDR_LEN *
 970                 hw->mac.rar_entry_count, 0);
 971         if (eth_dev->data->mac_addrs == NULL) {
 972                 PMD_INIT_LOG(ERR,
 973                         "Failed to allocate %d bytes needed to store MAC "
 974                         "addresses",
 975                         ETHER_ADDR_LEN * hw->mac.rar_entry_count);
 976                 return -ENOMEM;
 977         }
 978
 979         /* Generate a random MAC address, if none was assigned by PF. */
 980         if (is_zero_ether_addr(perm_addr)) {
 981                 eth_random_addr(perm_addr->addr_bytes);
 982                 diag = e1000_rar_set(hw, perm_addr->addr_bytes, 0);
 983                 if (diag) {
 984                         rte_free(eth_dev->data->mac_addrs);
 985                         eth_dev->data->mac_addrs = NULL;
 986                         return diag;
 987                 }
 988                 PMD_INIT_LOG(INFO, "\tVF MAC address not assigned by Host PF");
 989                 PMD_INIT_LOG(INFO, "\tAssign randomly generated MAC address "
 990                              "%02x:%02x:%02x:%02x:%02x:%02x",
 991                              perm_addr->addr_bytes[0],
 992                              perm_addr->addr_bytes[1],
 993                              perm_addr->addr_bytes[2],
 994                              perm_addr->addr_bytes[3],
 995                              perm_addr->addr_bytes[4],
 996                              perm_addr->addr_bytes[5]);
 997         }
 998
 999         /* Copy the permanent MAC address */
1000         ether_addr_copy((struct ether_addr *) hw->mac.perm_addr,
1001                         &eth_dev->data->mac_addrs[0]);
1002
1003         PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x "
1004                      "mac.type=%s",
1005                      eth_dev->data->port_id, pci_dev->id.vendor_id,
1006                      pci_dev->id.device_id, "igb_mac_82576_vf");
1007
1008         rte_intr_callback_register(&pci_dev->intr_handle,
1009                                    eth_igbvf_interrupt_handler,
1010                                    (void *)eth_dev);
1011
1012         return 0;
1013 }
1014
1015 static int
1016 eth_igbvf_dev_uninit(struct rte_eth_dev *eth_dev)
1017 {
1018         struct e1000_adapter *adapter =
1019                 E1000_DEV_PRIVATE(eth_dev->data->dev_private);
1020         struct rte_pci_device *pci_dev = eth_dev->pci_dev;
1021
1022         PMD_INIT_FUNC_TRACE();
1023
1024         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1025                 return -EPERM;
1026
1027         if (adapter->stopped == 0)
1028                 igbvf_dev_close(eth_dev);
1029
1030         eth_dev->dev_ops = NULL;
1031         eth_dev->rx_pkt_burst = NULL;
1032         eth_dev->tx_pkt_burst = NULL;
1033
1034         rte_free(eth_dev->data->mac_addrs);
1035         eth_dev->data->mac_addrs = NULL;
1036
1037         /* disable uio intr before callback unregister */
1038         rte_intr_disable(&pci_dev->intr_handle);
1039         rte_intr_callback_unregister(&pci_dev->intr_handle,
1040                                      eth_igbvf_interrupt_handler,
1041                                      (void *)eth_dev);
1042
1043         return 0;
1044 }
1045
1046 static struct eth_driver rte_igb_pmd = {
1047         .pci_drv = {
1048                 .name = "rte_igb_pmd",
1049                 .id_table = pci_id_igb_map,
1050                 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC |
1051                         RTE_PCI_DRV_DETACHABLE,
1052         },
1053         .eth_dev_init = eth_igb_dev_init,
1054         .eth_dev_uninit = eth_igb_dev_uninit,
1055         .dev_private_size = sizeof(struct e1000_adapter),
1056 };
1057
1058 /*
1059  * virtual function driver struct
1060  */
1061 static struct eth_driver rte_igbvf_pmd = {
1062         .pci_drv = {
1063                 .name = "rte_igbvf_pmd",
1064                 .id_table = pci_id_igbvf_map,
1065                 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_DETACHABLE,
1066         },
1067         .eth_dev_init = eth_igbvf_dev_init,
1068         .eth_dev_uninit = eth_igbvf_dev_uninit,
1069         .dev_private_size = sizeof(struct e1000_adapter),
1070 };
1071
1072 static int
1073 rte_igb_pmd_init(const char *name __rte_unused, const char *params __rte_unused)
1074 {
1075         rte_eth_driver_register(&rte_igb_pmd);
1076         return 0;
1077 }
1078
1079 static void
1080 igb_vmdq_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1081 {
1082         struct e1000_hw *hw =
1083                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1084         /* RCTL: enable VLAN filter since VMDq always use VLAN filter */
1085         uint32_t rctl = E1000_READ_REG(hw, E1000_RCTL);
1086         rctl |= E1000_RCTL_VFE;
1087         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1088 }
1089
1090 /*
1091  * VF Driver initialization routine.
1092  * Invoked one at EAL init time.
1093  * Register itself as the [Virtual Poll Mode] Driver of PCI IGB devices.
1094  */
1095 static int
1096 rte_igbvf_pmd_init(const char *name __rte_unused, const char *params __rte_unused)
1097 {
1098         PMD_INIT_FUNC_TRACE();
1099
1100         rte_eth_driver_register(&rte_igbvf_pmd);
1101         return 0;
1102 }
1103
1104 static int
1105 igb_check_mq_mode(struct rte_eth_dev *dev)
1106 {
1107         enum rte_eth_rx_mq_mode rx_mq_mode = dev->data->dev_conf.rxmode.mq_mode;
1108         enum rte_eth_tx_mq_mode tx_mq_mode = dev->data->dev_conf.txmode.mq_mode;
1109         uint16_t nb_rx_q = dev->data->nb_rx_queues;
1110         uint16_t nb_tx_q = dev->data->nb_rx_queues;
1111
1112         if ((rx_mq_mode & ETH_MQ_RX_DCB_FLAG) ||
1113             tx_mq_mode == ETH_MQ_TX_DCB ||
1114             tx_mq_mode == ETH_MQ_TX_VMDQ_DCB) {
1115                 PMD_INIT_LOG(ERR, "DCB mode is not supported.");
1116                 return -EINVAL;
1117         }
1118         if (RTE_ETH_DEV_SRIOV(dev).active != 0) {
1119                 /* Check multi-queue mode.
1120                  * To no break software we accept ETH_MQ_RX_NONE as this might
1121                  * be used to turn off VLAN filter.
1122                  */
1123
1124                 if (rx_mq_mode == ETH_MQ_RX_NONE ||
1125                     rx_mq_mode == ETH_MQ_RX_VMDQ_ONLY) {
1126                         dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_ONLY;
1127                         RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool = 1;
1128                 } else {
1129                         /* Only support one queue on VFs.
1130                          * RSS together with SRIOV is not supported.
1131                          */
1132                         PMD_INIT_LOG(ERR, "SRIOV is active,"
1133                                         " wrong mq_mode rx %d.",
1134                                         rx_mq_mode);
1135                         return -EINVAL;
1136                 }
1137                 /* TX mode is not used here, so mode might be ignored.*/
1138                 if (tx_mq_mode != ETH_MQ_TX_VMDQ_ONLY) {
1139                         /* SRIOV only works in VMDq enable mode */
1140                         PMD_INIT_LOG(WARNING, "SRIOV is active,"
1141                                         " TX mode %d is not supported. "
1142                                         " Driver will behave as %d mode.",
1143                                         tx_mq_mode, ETH_MQ_TX_VMDQ_ONLY);
1144                 }
1145
1146                 /* check valid queue number */
1147                 if ((nb_rx_q > 1) || (nb_tx_q > 1)) {
1148                         PMD_INIT_LOG(ERR, "SRIOV is active,"
1149                                         " only support one queue on VFs.");
1150                         return -EINVAL;
1151                 }
1152         } else {
1153                 /* To no break software that set invalid mode, only display
1154                  * warning if invalid mode is used.
1155                  */
1156                 if (rx_mq_mode != ETH_MQ_RX_NONE &&
1157                     rx_mq_mode != ETH_MQ_RX_VMDQ_ONLY &&
1158                     rx_mq_mode != ETH_MQ_RX_RSS) {
1159                         /* RSS together with VMDq not supported*/
1160                         PMD_INIT_LOG(ERR, "RX mode %d is not supported.",
1161                                      rx_mq_mode);
1162                         return -EINVAL;
1163                 }
1164
1165                 if (tx_mq_mode != ETH_MQ_TX_NONE &&
1166                     tx_mq_mode != ETH_MQ_TX_VMDQ_ONLY) {
1167                         PMD_INIT_LOG(WARNING, "TX mode %d is not supported."
1168                                         " Due to txmode is meaningless in this"
1169                                         " driver, just ignore.",
1170                                         tx_mq_mode);
1171                 }
1172         }
1173         return 0;
1174 }
1175
1176 static int
1177 eth_igb_configure(struct rte_eth_dev *dev)
1178 {
1179         struct e1000_interrupt *intr =
1180                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
1181         int ret;
1182
1183         PMD_INIT_FUNC_TRACE();
1184
1185         /* multipe queue mode checking */
1186         ret  = igb_check_mq_mode(dev);
1187         if (ret != 0) {
1188                 PMD_DRV_LOG(ERR, "igb_check_mq_mode fails with %d.",
1189                             ret);
1190                 return ret;
1191         }
1192
1193         intr->flags |= E1000_FLAG_NEED_LINK_UPDATE;
1194         PMD_INIT_FUNC_TRACE();
1195
1196         return 0;
1197 }
1198
1199 static int
1200 eth_igb_start(struct rte_eth_dev *dev)
1201 {
1202         struct e1000_hw *hw =
1203                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1204         struct e1000_adapter *adapter =
1205                 E1000_DEV_PRIVATE(dev->data->dev_private);
1206         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
1207         int ret, mask;
1208         uint32_t intr_vector = 0;
1209         uint32_t ctrl_ext;
1210         uint32_t *speeds;
1211         int num_speeds;
1212         bool autoneg;
1213
1214         PMD_INIT_FUNC_TRACE();
1215
1216         /* disable uio/vfio intr/eventfd mapping */
1217         rte_intr_disable(intr_handle);
1218
1219         /* Power up the phy. Needed to make the link go Up */
1220         eth_igb_dev_set_link_up(dev);
1221
1222         /*
1223          * Packet Buffer Allocation (PBA)
1224          * Writing PBA sets the receive portion of the buffer
1225          * the remainder is used for the transmit buffer.
1226          */
1227         if (hw->mac.type == e1000_82575) {
1228                 uint32_t pba;
1229
1230                 pba = E1000_PBA_32K; /* 32K for Rx, 16K for Tx */
1231                 E1000_WRITE_REG(hw, E1000_PBA, pba);
1232         }
1233
1234         /* Put the address into the Receive Address Array */
1235         e1000_rar_set(hw, hw->mac.addr, 0);
1236
1237         /* Initialize the hardware */
1238         if (igb_hardware_init(hw)) {
1239                 PMD_INIT_LOG(ERR, "Unable to initialize the hardware");
1240                 return -EIO;
1241         }
1242         adapter->stopped = 0;
1243
1244         E1000_WRITE_REG(hw, E1000_VET, ETHER_TYPE_VLAN << 16 | ETHER_TYPE_VLAN);
1245
1246         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
1247         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
1248         ctrl_ext |= E1000_CTRL_EXT_PFRSTD;
1249         E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
1250         E1000_WRITE_FLUSH(hw);
1251
1252         /* configure PF module if SRIOV enabled */
1253         igb_pf_host_configure(dev);
1254
1255         /* check and configure queue intr-vector mapping */
1256         if ((rte_intr_cap_multiple(intr_handle) ||
1257              !RTE_ETH_DEV_SRIOV(dev).active) &&
1258             dev->data->dev_conf.intr_conf.rxq != 0) {
1259                 intr_vector = dev->data->nb_rx_queues;
1260                 if (rte_intr_efd_enable(intr_handle, intr_vector))
1261                         return -1;
1262         }
1263
1264         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
1265                 intr_handle->intr_vec =
1266                         rte_zmalloc("intr_vec",
1267                                     dev->data->nb_rx_queues * sizeof(int), 0);
1268                 if (intr_handle->intr_vec == NULL) {
1269                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
1270                                      " intr_vec\n", dev->data->nb_rx_queues);
1271                         return -ENOMEM;
1272                 }
1273         }
1274
1275         /* confiugre msix for rx interrupt */
1276         eth_igb_configure_msix_intr(dev);
1277
1278         /* Configure for OS presence */
1279         igb_init_manageability(hw);
1280
1281         eth_igb_tx_init(dev);
1282
1283         /* This can fail when allocating mbufs for descriptor rings */
1284         ret = eth_igb_rx_init(dev);
1285         if (ret) {
1286                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
1287                 igb_dev_clear_queues(dev);
1288                 return ret;
1289         }
1290
1291         e1000_clear_hw_cntrs_base_generic(hw);
1292
1293         /*
1294          * VLAN Offload Settings
1295          */
1296         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK | \
1297                         ETH_VLAN_EXTEND_MASK;
1298         eth_igb_vlan_offload_set(dev, mask);
1299
1300         if (dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_VMDQ_ONLY) {
1301                 /* Enable VLAN filter since VMDq always use VLAN filter */
1302                 igb_vmdq_vlan_hw_filter_enable(dev);
1303         }
1304
1305         if ((hw->mac.type == e1000_82576) || (hw->mac.type == e1000_82580) ||
1306                 (hw->mac.type == e1000_i350) || (hw->mac.type == e1000_i210) ||
1307                 (hw->mac.type == e1000_i211)) {
1308                 /* Configure EITR with the maximum possible value (0xFFFF) */
1309                 E1000_WRITE_REG(hw, E1000_EITR(0), 0xFFFF);
1310         }
1311
1312         /* Setup link speed and duplex */
1313         speeds = &dev->data->dev_conf.link_speeds;
1314         if (*speeds == ETH_LINK_SPEED_AUTONEG) {
1315                 hw->phy.autoneg_advertised = E1000_ALL_SPEED_DUPLEX;
1316         } else {
1317                 num_speeds = 0;
1318                 autoneg = (*speeds & ETH_LINK_SPEED_FIXED) == 0;
1319
1320                 /* Reset */
1321                 hw->phy.autoneg_advertised = 0;
1322
1323                 if (*speeds & ~(ETH_LINK_SPEED_10M_HD | ETH_LINK_SPEED_10M |
1324                                 ETH_LINK_SPEED_100M_HD | ETH_LINK_SPEED_100M |
1325                                 ETH_LINK_SPEED_1G | ETH_LINK_SPEED_FIXED)) {
1326                         num_speeds = -1;
1327                         goto error_invalid_config;
1328                 }
1329                 if (*speeds & ETH_LINK_SPEED_10M_HD) {
1330                         hw->phy.autoneg_advertised |= ADVERTISE_10_HALF;
1331                         num_speeds++;
1332                 }
1333                 if (*speeds & ETH_LINK_SPEED_10M) {
1334                         hw->phy.autoneg_advertised |= ADVERTISE_10_FULL;
1335                         num_speeds++;
1336                 }
1337                 if (*speeds & ETH_LINK_SPEED_100M_HD) {
1338                         hw->phy.autoneg_advertised |= ADVERTISE_100_HALF;
1339                         num_speeds++;
1340                 }
1341                 if (*speeds & ETH_LINK_SPEED_100M) {
1342                         hw->phy.autoneg_advertised |= ADVERTISE_100_FULL;
1343                         num_speeds++;
1344                 }
1345                 if (*speeds & ETH_LINK_SPEED_1G) {
1346                         hw->phy.autoneg_advertised |= ADVERTISE_1000_FULL;
1347                         num_speeds++;
1348                 }
1349                 if (num_speeds == 0 || (!autoneg && (num_speeds > 1)))
1350                         goto error_invalid_config;
1351         }
1352
1353         e1000_setup_link(hw);
1354
1355         if (rte_intr_allow_others(intr_handle)) {
1356                 /* check if lsc interrupt is enabled */
1357                 if (dev->data->dev_conf.intr_conf.lsc != 0)
1358                         eth_igb_lsc_interrupt_setup(dev);
1359         } else {
1360                 rte_intr_callback_unregister(intr_handle,
1361                                              eth_igb_interrupt_handler,
1362                                              (void *)dev);
1363                 if (dev->data->dev_conf.intr_conf.lsc != 0)
1364                         PMD_INIT_LOG(INFO, "lsc won't enable because of"
1365                                      " no intr multiplex\n");
1366         }
1367
1368         /* check if rxq interrupt is enabled */
1369         if (dev->data->dev_conf.intr_conf.rxq != 0 &&
1370             rte_intr_dp_is_en(intr_handle))
1371                 eth_igb_rxq_interrupt_setup(dev);
1372
1373         /* enable uio/vfio intr/eventfd mapping */
1374         rte_intr_enable(intr_handle);
1375
1376         /* resume enabled intr since hw reset */
1377         igb_intr_enable(dev);
1378
1379         PMD_INIT_LOG(DEBUG, "<<");
1380
1381         return 0;
1382
1383 error_invalid_config:
1384         PMD_INIT_LOG(ERR, "Invalid advertised speeds (%u) for port %u",
1385                      dev->data->dev_conf.link_speeds, dev->data->port_id);
1386         igb_dev_clear_queues(dev);
1387         return -EINVAL;
1388 }
1389
1390 /*********************************************************************
1391  *
1392  *  This routine disables all traffic on the adapter by issuing a
1393  *  global reset on the MAC.
1394  *
1395  **********************************************************************/
1396 static void
1397 eth_igb_stop(struct rte_eth_dev *dev)
1398 {
1399         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1400         struct e1000_filter_info *filter_info =
1401                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
1402         struct rte_eth_link link;
1403         struct e1000_flex_filter *p_flex;
1404         struct e1000_5tuple_filter *p_5tuple, *p_5tuple_next;
1405         struct e1000_2tuple_filter *p_2tuple, *p_2tuple_next;
1406         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
1407
1408         igb_intr_disable(hw);
1409
1410         /* disable intr eventfd mapping */
1411         rte_intr_disable(intr_handle);
1412
1413         igb_pf_reset_hw(hw);
1414         E1000_WRITE_REG(hw, E1000_WUC, 0);
1415
1416         /* Set bit for Go Link disconnect */
1417         if (hw->mac.type >= e1000_82580) {
1418                 uint32_t phpm_reg;
1419
1420                 phpm_reg = E1000_READ_REG(hw, E1000_82580_PHY_POWER_MGMT);
1421                 phpm_reg |= E1000_82580_PM_GO_LINKD;
1422                 E1000_WRITE_REG(hw, E1000_82580_PHY_POWER_MGMT, phpm_reg);
1423         }
1424
1425         /* Power down the phy. Needed to make the link go Down */
1426         eth_igb_dev_set_link_down(dev);
1427
1428         igb_dev_clear_queues(dev);
1429
1430         /* clear the recorded link status */
1431         memset(&link, 0, sizeof(link));
1432         rte_igb_dev_atomic_write_link_status(dev, &link);
1433
1434         /* Remove all flex filters of the device */
1435         while ((p_flex = TAILQ_FIRST(&filter_info->flex_list))) {
1436                 TAILQ_REMOVE(&filter_info->flex_list, p_flex, entries);
1437                 rte_free(p_flex);
1438         }
1439         filter_info->flex_mask = 0;
1440
1441         /* Remove all ntuple filters of the device */
1442         for (p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list);
1443              p_5tuple != NULL; p_5tuple = p_5tuple_next) {
1444                 p_5tuple_next = TAILQ_NEXT(p_5tuple, entries);
1445                 TAILQ_REMOVE(&filter_info->fivetuple_list,
1446                              p_5tuple, entries);
1447                 rte_free(p_5tuple);
1448         }
1449         filter_info->fivetuple_mask = 0;
1450         for (p_2tuple = TAILQ_FIRST(&filter_info->twotuple_list);
1451              p_2tuple != NULL; p_2tuple = p_2tuple_next) {
1452                 p_2tuple_next = TAILQ_NEXT(p_2tuple, entries);
1453                 TAILQ_REMOVE(&filter_info->twotuple_list,
1454                              p_2tuple, entries);
1455                 rte_free(p_2tuple);
1456         }
1457         filter_info->twotuple_mask = 0;
1458
1459         if (!rte_intr_allow_others(intr_handle))
1460                 /* resume to the default handler */
1461                 rte_intr_callback_register(intr_handle,
1462                                            eth_igb_interrupt_handler,
1463                                            (void *)dev);
1464
1465         /* Clean datapath event and queue/vec mapping */
1466         rte_intr_efd_disable(intr_handle);
1467         if (intr_handle->intr_vec != NULL) {
1468                 rte_free(intr_handle->intr_vec);
1469                 intr_handle->intr_vec = NULL;
1470         }
1471 }
1472
1473 static int
1474 eth_igb_dev_set_link_up(struct rte_eth_dev *dev)
1475 {
1476         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1477
1478         if (hw->phy.media_type == e1000_media_type_copper)
1479                 e1000_power_up_phy(hw);
1480         else
1481                 e1000_power_up_fiber_serdes_link(hw);
1482
1483         return 0;
1484 }
1485
1486 static int
1487 eth_igb_dev_set_link_down(struct rte_eth_dev *dev)
1488 {
1489         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1490
1491         if (hw->phy.media_type == e1000_media_type_copper)
1492                 e1000_power_down_phy(hw);
1493         else
1494                 e1000_shutdown_fiber_serdes_link(hw);
1495
1496         return 0;
1497 }
1498
1499 static void
1500 eth_igb_close(struct rte_eth_dev *dev)
1501 {
1502         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1503         struct e1000_adapter *adapter =
1504                 E1000_DEV_PRIVATE(dev->data->dev_private);
1505         struct rte_eth_link link;
1506         struct rte_pci_device *pci_dev;
1507
1508         eth_igb_stop(dev);
1509         adapter->stopped = 1;
1510
1511         e1000_phy_hw_reset(hw);
1512         igb_release_manageability(hw);
1513         igb_hw_control_release(hw);
1514
1515         /* Clear bit for Go Link disconnect */
1516         if (hw->mac.type >= e1000_82580) {
1517                 uint32_t phpm_reg;
1518
1519                 phpm_reg = E1000_READ_REG(hw, E1000_82580_PHY_POWER_MGMT);
1520                 phpm_reg &= ~E1000_82580_PM_GO_LINKD;
1521                 E1000_WRITE_REG(hw, E1000_82580_PHY_POWER_MGMT, phpm_reg);
1522         }
1523
1524         igb_dev_free_queues(dev);
1525
1526         pci_dev = dev->pci_dev;
1527         if (pci_dev->intr_handle.intr_vec) {
1528                 rte_free(pci_dev->intr_handle.intr_vec);
1529                 pci_dev->intr_handle.intr_vec = NULL;
1530         }
1531
1532         memset(&link, 0, sizeof(link));
1533         rte_igb_dev_atomic_write_link_status(dev, &link);
1534 }
1535
1536 static int
1537 igb_get_rx_buffer_size(struct e1000_hw *hw)
1538 {
1539         uint32_t rx_buf_size;
1540         if (hw->mac.type == e1000_82576) {
1541                 rx_buf_size = (E1000_READ_REG(hw, E1000_RXPBS) & 0xffff) << 10;
1542         } else if (hw->mac.type == e1000_82580 || hw->mac.type == e1000_i350) {
1543                 /* PBS needs to be translated according to a lookup table */
1544                 rx_buf_size = (E1000_READ_REG(hw, E1000_RXPBS) & 0xf);
1545                 rx_buf_size = (uint32_t) e1000_rxpbs_adjust_82580(rx_buf_size);
1546                 rx_buf_size = (rx_buf_size << 10);
1547         } else if (hw->mac.type == e1000_i210 || hw->mac.type == e1000_i211) {
1548                 rx_buf_size = (E1000_READ_REG(hw, E1000_RXPBS) & 0x3f) << 10;
1549         } else {
1550                 rx_buf_size = (E1000_READ_REG(hw, E1000_PBA) & 0xffff) << 10;
1551         }
1552
1553         return rx_buf_size;
1554 }
1555
1556 /*********************************************************************
1557  *
1558  *  Initialize the hardware
1559  *
1560  **********************************************************************/
1561 static int
1562 igb_hardware_init(struct e1000_hw *hw)
1563 {
1564         uint32_t rx_buf_size;
1565         int diag;
1566
1567         /* Let the firmware know the OS is in control */
1568         igb_hw_control_acquire(hw);
1569
1570         /*
1571          * These parameters control the automatic generation (Tx) and
1572          * response (Rx) to Ethernet PAUSE frames.
1573          * - High water mark should allow for at least two standard size (1518)
1574          *   frames to be received after sending an XOFF.
1575          * - Low water mark works best when it is very near the high water mark.
1576          *   This allows the receiver to restart by sending XON when it has
1577          *   drained a bit. Here we use an arbitrary value of 1500 which will
1578          *   restart after one full frame is pulled from the buffer. There
1579          *   could be several smaller frames in the buffer and if so they will
1580          *   not trigger the XON until their total number reduces the buffer
1581          *   by 1500.
1582          * - The pause time is fairly large at 1000 x 512ns = 512 usec.
1583          */
1584         rx_buf_size = igb_get_rx_buffer_size(hw);
1585
1586         hw->fc.high_water = rx_buf_size - (ETHER_MAX_LEN * 2);
1587         hw->fc.low_water = hw->fc.high_water - 1500;
1588         hw->fc.pause_time = IGB_FC_PAUSE_TIME;
1589         hw->fc.send_xon = 1;
1590
1591         /* Set Flow control, use the tunable location if sane */
1592         if ((igb_fc_setting != e1000_fc_none) && (igb_fc_setting < 4))
1593                 hw->fc.requested_mode = igb_fc_setting;
1594         else
1595                 hw->fc.requested_mode = e1000_fc_none;
1596
1597         /* Issue a global reset */
1598         igb_pf_reset_hw(hw);
1599         E1000_WRITE_REG(hw, E1000_WUC, 0);
1600
1601         diag = e1000_init_hw(hw);
1602         if (diag < 0)
1603                 return diag;
1604
1605         E1000_WRITE_REG(hw, E1000_VET, ETHER_TYPE_VLAN << 16 | ETHER_TYPE_VLAN);
1606         e1000_get_phy_info(hw);
1607         e1000_check_for_link(hw);
1608
1609         return 0;
1610 }
1611
1612 /* This function is based on igb_update_stats_counters() in igb/if_igb.c */
1613 static void
1614 igb_read_stats_registers(struct e1000_hw *hw, struct e1000_hw_stats *stats)
1615 {
1616         int pause_frames;
1617
1618         uint64_t old_gprc  = stats->gprc;
1619         uint64_t old_gptc  = stats->gptc;
1620         uint64_t old_tpr   = stats->tpr;
1621         uint64_t old_tpt   = stats->tpt;
1622         uint64_t old_rpthc = stats->rpthc;
1623         uint64_t old_hgptc = stats->hgptc;
1624
1625         if(hw->phy.media_type == e1000_media_type_copper ||
1626             (E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU)) {
1627                 stats->symerrs +=
1628                     E1000_READ_REG(hw,E1000_SYMERRS);
1629                 stats->sec += E1000_READ_REG(hw, E1000_SEC);
1630         }
1631
1632         stats->crcerrs += E1000_READ_REG(hw, E1000_CRCERRS);
1633         stats->mpc += E1000_READ_REG(hw, E1000_MPC);
1634         stats->scc += E1000_READ_REG(hw, E1000_SCC);
1635         stats->ecol += E1000_READ_REG(hw, E1000_ECOL);
1636
1637         stats->mcc += E1000_READ_REG(hw, E1000_MCC);
1638         stats->latecol += E1000_READ_REG(hw, E1000_LATECOL);
1639         stats->colc += E1000_READ_REG(hw, E1000_COLC);
1640         stats->dc += E1000_READ_REG(hw, E1000_DC);
1641         stats->rlec += E1000_READ_REG(hw, E1000_RLEC);
1642         stats->xonrxc += E1000_READ_REG(hw, E1000_XONRXC);
1643         stats->xontxc += E1000_READ_REG(hw, E1000_XONTXC);
1644         /*
1645         ** For watchdog management we need to know if we have been
1646         ** paused during the last interval, so capture that here.
1647         */
1648         pause_frames = E1000_READ_REG(hw, E1000_XOFFRXC);
1649         stats->xoffrxc += pause_frames;
1650         stats->xofftxc += E1000_READ_REG(hw, E1000_XOFFTXC);
1651         stats->fcruc += E1000_READ_REG(hw, E1000_FCRUC);
1652         stats->prc64 += E1000_READ_REG(hw, E1000_PRC64);
1653         stats->prc127 += E1000_READ_REG(hw, E1000_PRC127);
1654         stats->prc255 += E1000_READ_REG(hw, E1000_PRC255);
1655         stats->prc511 += E1000_READ_REG(hw, E1000_PRC511);
1656         stats->prc1023 += E1000_READ_REG(hw, E1000_PRC1023);
1657         stats->prc1522 += E1000_READ_REG(hw, E1000_PRC1522);
1658         stats->gprc += E1000_READ_REG(hw, E1000_GPRC);
1659         stats->bprc += E1000_READ_REG(hw, E1000_BPRC);
1660         stats->mprc += E1000_READ_REG(hw, E1000_MPRC);
1661         stats->gptc += E1000_READ_REG(hw, E1000_GPTC);
1662
1663         /* For the 64-bit byte counters the low dword must be read first. */
1664         /* Both registers clear on the read of the high dword */
1665
1666         /* Workaround CRC bytes included in size, take away 4 bytes/packet */
1667         stats->gorc += E1000_READ_REG(hw, E1000_GORCL);
1668         stats->gorc += ((uint64_t)E1000_READ_REG(hw, E1000_GORCH) << 32);
1669         stats->gorc -= (stats->gprc - old_gprc) * ETHER_CRC_LEN;
1670         stats->gotc += E1000_READ_REG(hw, E1000_GOTCL);
1671         stats->gotc += ((uint64_t)E1000_READ_REG(hw, E1000_GOTCH) << 32);
1672         stats->gotc -= (stats->gptc - old_gptc) * ETHER_CRC_LEN;
1673
1674         stats->rnbc += E1000_READ_REG(hw, E1000_RNBC);
1675         stats->ruc += E1000_READ_REG(hw, E1000_RUC);
1676         stats->rfc += E1000_READ_REG(hw, E1000_RFC);
1677         stats->roc += E1000_READ_REG(hw, E1000_ROC);
1678         stats->rjc += E1000_READ_REG(hw, E1000_RJC);
1679
1680         stats->tpr += E1000_READ_REG(hw, E1000_TPR);
1681         stats->tpt += E1000_READ_REG(hw, E1000_TPT);
1682
1683         stats->tor += E1000_READ_REG(hw, E1000_TORL);
1684         stats->tor += ((uint64_t)E1000_READ_REG(hw, E1000_TORH) << 32);
1685         stats->tor -= (stats->tpr - old_tpr) * ETHER_CRC_LEN;
1686         stats->tot += E1000_READ_REG(hw, E1000_TOTL);
1687         stats->tot += ((uint64_t)E1000_READ_REG(hw, E1000_TOTH) << 32);
1688         stats->tot -= (stats->tpt - old_tpt) * ETHER_CRC_LEN;
1689
1690         stats->ptc64 += E1000_READ_REG(hw, E1000_PTC64);
1691         stats->ptc127 += E1000_READ_REG(hw, E1000_PTC127);
1692         stats->ptc255 += E1000_READ_REG(hw, E1000_PTC255);
1693         stats->ptc511 += E1000_READ_REG(hw, E1000_PTC511);
1694         stats->ptc1023 += E1000_READ_REG(hw, E1000_PTC1023);
1695         stats->ptc1522 += E1000_READ_REG(hw, E1000_PTC1522);
1696         stats->mptc += E1000_READ_REG(hw, E1000_MPTC);
1697         stats->bptc += E1000_READ_REG(hw, E1000_BPTC);
1698
1699         /* Interrupt Counts */
1700
1701         stats->iac += E1000_READ_REG(hw, E1000_IAC);
1702         stats->icrxptc += E1000_READ_REG(hw, E1000_ICRXPTC);
1703         stats->icrxatc += E1000_READ_REG(hw, E1000_ICRXATC);
1704         stats->ictxptc += E1000_READ_REG(hw, E1000_ICTXPTC);
1705         stats->ictxatc += E1000_READ_REG(hw, E1000_ICTXATC);
1706         stats->ictxqec += E1000_READ_REG(hw, E1000_ICTXQEC);
1707         stats->ictxqmtc += E1000_READ_REG(hw, E1000_ICTXQMTC);
1708         stats->icrxdmtc += E1000_READ_REG(hw, E1000_ICRXDMTC);
1709         stats->icrxoc += E1000_READ_REG(hw, E1000_ICRXOC);
1710
1711         /* Host to Card Statistics */
1712
1713         stats->cbtmpc += E1000_READ_REG(hw, E1000_CBTMPC);
1714         stats->htdpmc += E1000_READ_REG(hw, E1000_HTDPMC);
1715         stats->cbrdpc += E1000_READ_REG(hw, E1000_CBRDPC);
1716         stats->cbrmpc += E1000_READ_REG(hw, E1000_CBRMPC);
1717         stats->rpthc += E1000_READ_REG(hw, E1000_RPTHC);
1718         stats->hgptc += E1000_READ_REG(hw, E1000_HGPTC);
1719         stats->htcbdpc += E1000_READ_REG(hw, E1000_HTCBDPC);
1720         stats->hgorc += E1000_READ_REG(hw, E1000_HGORCL);
1721         stats->hgorc += ((uint64_t)E1000_READ_REG(hw, E1000_HGORCH) << 32);
1722         stats->hgorc -= (stats->rpthc - old_rpthc) * ETHER_CRC_LEN;
1723         stats->hgotc += E1000_READ_REG(hw, E1000_HGOTCL);
1724         stats->hgotc += ((uint64_t)E1000_READ_REG(hw, E1000_HGOTCH) << 32);
1725         stats->hgotc -= (stats->hgptc - old_hgptc) * ETHER_CRC_LEN;
1726         stats->lenerrs += E1000_READ_REG(hw, E1000_LENERRS);
1727         stats->scvpc += E1000_READ_REG(hw, E1000_SCVPC);
1728         stats->hrmpc += E1000_READ_REG(hw, E1000_HRMPC);
1729
1730         stats->algnerrc += E1000_READ_REG(hw, E1000_ALGNERRC);
1731         stats->rxerrc += E1000_READ_REG(hw, E1000_RXERRC);
1732         stats->tncrs += E1000_READ_REG(hw, E1000_TNCRS);
1733         stats->cexterr += E1000_READ_REG(hw, E1000_CEXTERR);
1734         stats->tsctc += E1000_READ_REG(hw, E1000_TSCTC);
1735         stats->tsctfc += E1000_READ_REG(hw, E1000_TSCTFC);
1736 }
1737
1738 static void
1739 eth_igb_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *rte_stats)
1740 {
1741         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1742         struct e1000_hw_stats *stats =
1743                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1744
1745         igb_read_stats_registers(hw, stats);
1746
1747         if (rte_stats == NULL)
1748                 return;
1749
1750         /* Rx Errors */
1751         rte_stats->imissed = stats->mpc;
1752         rte_stats->ierrors = stats->crcerrs +
1753                              stats->rlec + stats->ruc + stats->roc +
1754                              stats->rxerrc + stats->algnerrc + stats->cexterr;
1755
1756         /* Tx Errors */
1757         rte_stats->oerrors = stats->ecol + stats->latecol;
1758
1759         rte_stats->ipackets = stats->gprc;
1760         rte_stats->opackets = stats->gptc;
1761         rte_stats->ibytes   = stats->gorc;
1762         rte_stats->obytes   = stats->gotc;
1763 }
1764
1765 static void
1766 eth_igb_stats_reset(struct rte_eth_dev *dev)
1767 {
1768         struct e1000_hw_stats *hw_stats =
1769                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1770
1771         /* HW registers are cleared on read */
1772         eth_igb_stats_get(dev, NULL);
1773
1774         /* Reset software totals */
1775         memset(hw_stats, 0, sizeof(*hw_stats));
1776 }
1777
1778 static void
1779 eth_igb_xstats_reset(struct rte_eth_dev *dev)
1780 {
1781         struct e1000_hw_stats *stats =
1782                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1783
1784         /* HW registers are cleared on read */
1785         eth_igb_xstats_get(dev, NULL, IGB_NB_XSTATS);
1786
1787         /* Reset software totals */
1788         memset(stats, 0, sizeof(*stats));
1789 }
1790
1791 static int eth_igb_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
1792         struct rte_eth_xstat_name *xstats_names,
1793         __rte_unused unsigned limit)
1794 {
1795         unsigned i;
1796
1797         if (xstats_names == NULL)
1798                 return IGB_NB_XSTATS;
1799
1800         /* Note: limit checked in rte_eth_xstats_names() */
1801
1802         for (i = 0; i < IGB_NB_XSTATS; i++) {
1803                 snprintf(xstats_names[i].name, sizeof(xstats_names[i].name),
1804                          "%s", rte_igb_stats_strings[i].name);
1805         }
1806
1807         return IGB_NB_XSTATS;
1808 }
1809
1810 static int
1811 eth_igb_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
1812                    unsigned n)
1813 {
1814         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1815         struct e1000_hw_stats *hw_stats =
1816                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1817         unsigned i;
1818
1819         if (n < IGB_NB_XSTATS)
1820                 return IGB_NB_XSTATS;
1821
1822         igb_read_stats_registers(hw, hw_stats);
1823
1824         /* If this is a reset xstats is NULL, and we have cleared the
1825          * registers by reading them.
1826          */
1827         if (!xstats)
1828                 return 0;
1829
1830         /* Extended stats */
1831         for (i = 0; i < IGB_NB_XSTATS; i++) {
1832                 xstats[i].id = i;
1833                 xstats[i].value = *(uint64_t *)(((char *)hw_stats) +
1834                         rte_igb_stats_strings[i].offset);
1835         }
1836
1837         return IGB_NB_XSTATS;
1838 }
1839
1840 static void
1841 igbvf_read_stats_registers(struct e1000_hw *hw, struct e1000_vf_stats *hw_stats)
1842 {
1843         /* Good Rx packets, include VF loopback */
1844         UPDATE_VF_STAT(E1000_VFGPRC,
1845             hw_stats->last_gprc, hw_stats->gprc);
1846
1847         /* Good Rx octets, include VF loopback */
1848         UPDATE_VF_STAT(E1000_VFGORC,
1849             hw_stats->last_gorc, hw_stats->gorc);
1850
1851         /* Good Tx packets, include VF loopback */
1852         UPDATE_VF_STAT(E1000_VFGPTC,
1853             hw_stats->last_gptc, hw_stats->gptc);
1854
1855         /* Good Tx octets, include VF loopback */
1856         UPDATE_VF_STAT(E1000_VFGOTC,
1857             hw_stats->last_gotc, hw_stats->gotc);
1858
1859         /* Rx Multicst packets */
1860         UPDATE_VF_STAT(E1000_VFMPRC,
1861             hw_stats->last_mprc, hw_stats->mprc);
1862
1863         /* Good Rx loopback packets */
1864         UPDATE_VF_STAT(E1000_VFGPRLBC,
1865             hw_stats->last_gprlbc, hw_stats->gprlbc);
1866
1867         /* Good Rx loopback octets */
1868         UPDATE_VF_STAT(E1000_VFGORLBC,
1869             hw_stats->last_gorlbc, hw_stats->gorlbc);
1870
1871         /* Good Tx loopback packets */
1872         UPDATE_VF_STAT(E1000_VFGPTLBC,
1873             hw_stats->last_gptlbc, hw_stats->gptlbc);
1874
1875         /* Good Tx loopback octets */
1876         UPDATE_VF_STAT(E1000_VFGOTLBC,
1877             hw_stats->last_gotlbc, hw_stats->gotlbc);
1878 }
1879
1880 static int eth_igbvf_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
1881                                      struct rte_eth_xstat_name *xstats_names,
1882                                      __rte_unused unsigned limit)
1883 {
1884         unsigned i;
1885
1886         if (xstats_names != NULL)
1887                 for (i = 0; i < IGBVF_NB_XSTATS; i++) {
1888                         snprintf(xstats_names[i].name,
1889                                 sizeof(xstats_names[i].name), "%s",
1890                                 rte_igbvf_stats_strings[i].name);
1891                 }
1892         return IGBVF_NB_XSTATS;
1893 }
1894
1895 static int
1896 eth_igbvf_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
1897                      unsigned n)
1898 {
1899         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1900         struct e1000_vf_stats *hw_stats = (struct e1000_vf_stats *)
1901                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1902         unsigned i;
1903
1904         if (n < IGBVF_NB_XSTATS)
1905                 return IGBVF_NB_XSTATS;
1906
1907         igbvf_read_stats_registers(hw, hw_stats);
1908
1909         if (!xstats)
1910                 return 0;
1911
1912         for (i = 0; i < IGBVF_NB_XSTATS; i++) {
1913                 xstats[i].id = i;
1914                 xstats[i].value = *(uint64_t *)(((char *)hw_stats) +
1915                         rte_igbvf_stats_strings[i].offset);
1916         }
1917
1918         return IGBVF_NB_XSTATS;
1919 }
1920
1921 static void
1922 eth_igbvf_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *rte_stats)
1923 {
1924         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1925         struct e1000_vf_stats *hw_stats = (struct e1000_vf_stats *)
1926                           E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1927
1928         igbvf_read_stats_registers(hw, hw_stats);
1929
1930         if (rte_stats == NULL)
1931                 return;
1932
1933         rte_stats->ipackets = hw_stats->gprc;
1934         rte_stats->ibytes = hw_stats->gorc;
1935         rte_stats->opackets = hw_stats->gptc;
1936         rte_stats->obytes = hw_stats->gotc;
1937 }
1938
1939 static void
1940 eth_igbvf_stats_reset(struct rte_eth_dev *dev)
1941 {
1942         struct e1000_vf_stats *hw_stats = (struct e1000_vf_stats*)
1943                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1944
1945         /* Sync HW register to the last stats */
1946         eth_igbvf_stats_get(dev, NULL);
1947
1948         /* reset HW current stats*/
1949         memset(&hw_stats->gprc, 0, sizeof(*hw_stats) -
1950                offsetof(struct e1000_vf_stats, gprc));
1951 }
1952
1953 static void
1954 eth_igb_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
1955 {
1956         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1957
1958         dev_info->min_rx_bufsize = 256; /* See BSIZE field of RCTL register. */
1959         dev_info->max_rx_pktlen  = 0x3FFF; /* See RLPML register. */
1960         dev_info->max_mac_addrs = hw->mac.rar_entry_count;
1961         dev_info->rx_offload_capa =
1962                 DEV_RX_OFFLOAD_VLAN_STRIP |
1963                 DEV_RX_OFFLOAD_IPV4_CKSUM |
1964                 DEV_RX_OFFLOAD_UDP_CKSUM  |
1965                 DEV_RX_OFFLOAD_TCP_CKSUM;
1966         dev_info->tx_offload_capa =
1967                 DEV_TX_OFFLOAD_VLAN_INSERT |
1968                 DEV_TX_OFFLOAD_IPV4_CKSUM  |
1969                 DEV_TX_OFFLOAD_UDP_CKSUM   |
1970                 DEV_TX_OFFLOAD_TCP_CKSUM   |
1971                 DEV_TX_OFFLOAD_SCTP_CKSUM  |
1972                 DEV_TX_OFFLOAD_TCP_TSO;
1973
1974         switch (hw->mac.type) {
1975         case e1000_82575:
1976                 dev_info->max_rx_queues = 4;
1977                 dev_info->max_tx_queues = 4;
1978                 dev_info->max_vmdq_pools = 0;
1979                 break;
1980
1981         case e1000_82576:
1982                 dev_info->max_rx_queues = 16;
1983                 dev_info->max_tx_queues = 16;
1984                 dev_info->max_vmdq_pools = ETH_8_POOLS;
1985                 dev_info->vmdq_queue_num = 16;
1986                 break;
1987
1988         case e1000_82580:
1989                 dev_info->max_rx_queues = 8;
1990                 dev_info->max_tx_queues = 8;
1991                 dev_info->max_vmdq_pools = ETH_8_POOLS;
1992                 dev_info->vmdq_queue_num = 8;
1993                 break;
1994
1995         case e1000_i350:
1996                 dev_info->max_rx_queues = 8;
1997                 dev_info->max_tx_queues = 8;
1998                 dev_info->max_vmdq_pools = ETH_8_POOLS;
1999                 dev_info->vmdq_queue_num = 8;
2000                 break;
2001
2002         case e1000_i354:
2003                 dev_info->max_rx_queues = 8;
2004                 dev_info->max_tx_queues = 8;
2005                 break;
2006
2007         case e1000_i210:
2008                 dev_info->max_rx_queues = 4;
2009                 dev_info->max_tx_queues = 4;
2010                 dev_info->max_vmdq_pools = 0;
2011                 break;
2012
2013         case e1000_i211:
2014                 dev_info->max_rx_queues = 2;
2015                 dev_info->max_tx_queues = 2;
2016                 dev_info->max_vmdq_pools = 0;
2017                 break;
2018
2019         default:
2020                 /* Should not happen */
2021                 break;
2022         }
2023         dev_info->hash_key_size = IGB_HKEY_MAX_INDEX * sizeof(uint32_t);
2024         dev_info->reta_size = ETH_RSS_RETA_SIZE_128;
2025         dev_info->flow_type_rss_offloads = IGB_RSS_OFFLOAD_ALL;
2026
2027         dev_info->default_rxconf = (struct rte_eth_rxconf) {
2028                 .rx_thresh = {
2029                         .pthresh = IGB_DEFAULT_RX_PTHRESH,
2030                         .hthresh = IGB_DEFAULT_RX_HTHRESH,
2031                         .wthresh = IGB_DEFAULT_RX_WTHRESH,
2032                 },
2033                 .rx_free_thresh = IGB_DEFAULT_RX_FREE_THRESH,
2034                 .rx_drop_en = 0,
2035         };
2036
2037         dev_info->default_txconf = (struct rte_eth_txconf) {
2038                 .tx_thresh = {
2039                         .pthresh = IGB_DEFAULT_TX_PTHRESH,
2040                         .hthresh = IGB_DEFAULT_TX_HTHRESH,
2041                         .wthresh = IGB_DEFAULT_TX_WTHRESH,
2042                 },
2043                 .txq_flags = 0,
2044         };
2045
2046         dev_info->rx_desc_lim = rx_desc_lim;
2047         dev_info->tx_desc_lim = tx_desc_lim;
2048
2049         dev_info->speed_capa = ETH_LINK_SPEED_10M_HD | ETH_LINK_SPEED_10M |
2050                         ETH_LINK_SPEED_100M_HD | ETH_LINK_SPEED_100M |
2051                         ETH_LINK_SPEED_1G;
2052 }
2053
2054 static const uint32_t *
2055 eth_igb_supported_ptypes_get(struct rte_eth_dev *dev)
2056 {
2057         static const uint32_t ptypes[] = {
2058                 /* refers to igb_rxd_pkt_info_to_pkt_type() */
2059                 RTE_PTYPE_L2_ETHER,
2060                 RTE_PTYPE_L3_IPV4,
2061                 RTE_PTYPE_L3_IPV4_EXT,
2062                 RTE_PTYPE_L3_IPV6,
2063                 RTE_PTYPE_L3_IPV6_EXT,
2064                 RTE_PTYPE_L4_TCP,
2065                 RTE_PTYPE_L4_UDP,
2066                 RTE_PTYPE_L4_SCTP,
2067                 RTE_PTYPE_TUNNEL_IP,
2068                 RTE_PTYPE_INNER_L3_IPV6,
2069                 RTE_PTYPE_INNER_L3_IPV6_EXT,
2070                 RTE_PTYPE_INNER_L4_TCP,
2071                 RTE_PTYPE_INNER_L4_UDP,
2072                 RTE_PTYPE_UNKNOWN
2073         };
2074
2075         if (dev->rx_pkt_burst == eth_igb_recv_pkts ||
2076             dev->rx_pkt_burst == eth_igb_recv_scattered_pkts)
2077                 return ptypes;
2078         return NULL;
2079 }
2080
2081 static void
2082 eth_igbvf_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
2083 {
2084         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2085
2086         dev_info->min_rx_bufsize = 256; /* See BSIZE field of RCTL register. */
2087         dev_info->max_rx_pktlen  = 0x3FFF; /* See RLPML register. */
2088         dev_info->max_mac_addrs = hw->mac.rar_entry_count;
2089         dev_info->rx_offload_capa = DEV_RX_OFFLOAD_VLAN_STRIP |
2090                                 DEV_RX_OFFLOAD_IPV4_CKSUM |
2091                                 DEV_RX_OFFLOAD_UDP_CKSUM  |
2092                                 DEV_RX_OFFLOAD_TCP_CKSUM;
2093         dev_info->tx_offload_capa = DEV_TX_OFFLOAD_VLAN_INSERT |
2094                                 DEV_TX_OFFLOAD_IPV4_CKSUM  |
2095                                 DEV_TX_OFFLOAD_UDP_CKSUM   |
2096                                 DEV_TX_OFFLOAD_TCP_CKSUM   |
2097                                 DEV_TX_OFFLOAD_SCTP_CKSUM  |
2098                                 DEV_TX_OFFLOAD_TCP_TSO;
2099         switch (hw->mac.type) {
2100         case e1000_vfadapt:
2101                 dev_info->max_rx_queues = 2;
2102                 dev_info->max_tx_queues = 2;
2103                 break;
2104         case e1000_vfadapt_i350:
2105                 dev_info->max_rx_queues = 1;
2106                 dev_info->max_tx_queues = 1;
2107                 break;
2108         default:
2109                 /* Should not happen */
2110                 break;
2111         }
2112
2113         dev_info->default_rxconf = (struct rte_eth_rxconf) {
2114                 .rx_thresh = {
2115                         .pthresh = IGB_DEFAULT_RX_PTHRESH,
2116                         .hthresh = IGB_DEFAULT_RX_HTHRESH,
2117                         .wthresh = IGB_DEFAULT_RX_WTHRESH,
2118                 },
2119                 .rx_free_thresh = IGB_DEFAULT_RX_FREE_THRESH,
2120                 .rx_drop_en = 0,
2121         };
2122
2123         dev_info->default_txconf = (struct rte_eth_txconf) {
2124                 .tx_thresh = {
2125                         .pthresh = IGB_DEFAULT_TX_PTHRESH,
2126                         .hthresh = IGB_DEFAULT_TX_HTHRESH,
2127                         .wthresh = IGB_DEFAULT_TX_WTHRESH,
2128                 },
2129                 .txq_flags = 0,
2130         };
2131
2132         dev_info->rx_desc_lim = rx_desc_lim;
2133         dev_info->tx_desc_lim = tx_desc_lim;
2134 }
2135
2136 /* return 0 means link status changed, -1 means not changed */
2137 static int
2138 eth_igb_link_update(struct rte_eth_dev *dev, int wait_to_complete)
2139 {
2140         struct e1000_hw *hw =
2141                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2142         struct rte_eth_link link, old;
2143         int link_check, count;
2144
2145         link_check = 0;
2146         hw->mac.get_link_status = 1;
2147
2148         /* possible wait-to-complete in up to 9 seconds */
2149         for (count = 0; count < IGB_LINK_UPDATE_CHECK_TIMEOUT; count ++) {
2150                 /* Read the real link status */
2151                 switch (hw->phy.media_type) {
2152                 case e1000_media_type_copper:
2153                         /* Do the work to read phy */
2154                         e1000_check_for_link(hw);
2155                         link_check = !hw->mac.get_link_status;
2156                         break;
2157
2158                 case e1000_media_type_fiber:
2159                         e1000_check_for_link(hw);
2160                         link_check = (E1000_READ_REG(hw, E1000_STATUS) &
2161                                       E1000_STATUS_LU);
2162                         break;
2163
2164                 case e1000_media_type_internal_serdes:
2165                         e1000_check_for_link(hw);
2166                         link_check = hw->mac.serdes_has_link;
2167                         break;
2168
2169                 /* VF device is type_unknown */
2170                 case e1000_media_type_unknown:
2171                         eth_igbvf_link_update(hw);
2172                         link_check = !hw->mac.get_link_status;
2173                         break;
2174
2175                 default:
2176                         break;
2177                 }
2178                 if (link_check || wait_to_complete == 0)
2179                         break;
2180                 rte_delay_ms(IGB_LINK_UPDATE_CHECK_INTERVAL);
2181         }
2182         memset(&link, 0, sizeof(link));
2183         rte_igb_dev_atomic_read_link_status(dev, &link);
2184         old = link;
2185
2186         /* Now we check if a transition has happened */
2187         if (link_check) {
2188                 uint16_t duplex, speed;
2189                 hw->mac.ops.get_link_up_info(hw, &speed, &duplex);
2190                 link.link_duplex = (duplex == FULL_DUPLEX) ?
2191                                 ETH_LINK_FULL_DUPLEX :
2192                                 ETH_LINK_HALF_DUPLEX;
2193                 link.link_speed = speed;
2194                 link.link_status = ETH_LINK_UP;
2195                 link.link_autoneg = !(dev->data->dev_conf.link_speeds &
2196                                 ETH_LINK_SPEED_FIXED);
2197         } else if (!link_check) {
2198                 link.link_speed = 0;
2199                 link.link_duplex = ETH_LINK_HALF_DUPLEX;
2200                 link.link_status = ETH_LINK_DOWN;
2201                 link.link_autoneg = ETH_LINK_SPEED_FIXED;
2202         }
2203         rte_igb_dev_atomic_write_link_status(dev, &link);
2204
2205         /* not changed */
2206         if (old.link_status == link.link_status)
2207                 return -1;
2208
2209         /* changed */
2210         return 0;
2211 }
2212
2213 /*
2214  * igb_hw_control_acquire sets CTRL_EXT:DRV_LOAD bit.
2215  * For ASF and Pass Through versions of f/w this means
2216  * that the driver is loaded.
2217  */
2218 static void
2219 igb_hw_control_acquire(struct e1000_hw *hw)
2220 {
2221         uint32_t ctrl_ext;
2222
2223         /* Let firmware know the driver has taken over */
2224         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
2225         E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
2226 }
2227
2228 /*
2229  * igb_hw_control_release resets CTRL_EXT:DRV_LOAD bit.
2230  * For ASF and Pass Through versions of f/w this means that the
2231  * driver is no longer loaded.
2232  */
2233 static void
2234 igb_hw_control_release(struct e1000_hw *hw)
2235 {
2236         uint32_t ctrl_ext;
2237
2238         /* Let firmware taken over control of h/w */
2239         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
2240         E1000_WRITE_REG(hw, E1000_CTRL_EXT,
2241                         ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
2242 }
2243
2244 /*
2245  * Bit of a misnomer, what this really means is
2246  * to enable OS management of the system... aka
2247  * to disable special hardware management features.
2248  */
2249 static void
2250 igb_init_manageability(struct e1000_hw *hw)
2251 {
2252         if (e1000_enable_mng_pass_thru(hw)) {
2253                 uint32_t manc2h = E1000_READ_REG(hw, E1000_MANC2H);
2254                 uint32_t manc = E1000_READ_REG(hw, E1000_MANC);
2255
2256                 /* disable hardware interception of ARP */
2257                 manc &= ~(E1000_MANC_ARP_EN);
2258
2259                 /* enable receiving management packets to the host */
2260                 manc |= E1000_MANC_EN_MNG2HOST;
2261                 manc2h |= 1 << 5;  /* Mng Port 623 */
2262                 manc2h |= 1 << 6;  /* Mng Port 664 */
2263                 E1000_WRITE_REG(hw, E1000_MANC2H, manc2h);
2264                 E1000_WRITE_REG(hw, E1000_MANC, manc);
2265         }
2266 }
2267
2268 static void
2269 igb_release_manageability(struct e1000_hw *hw)
2270 {
2271         if (e1000_enable_mng_pass_thru(hw)) {
2272                 uint32_t manc = E1000_READ_REG(hw, E1000_MANC);
2273
2274                 manc |= E1000_MANC_ARP_EN;
2275                 manc &= ~E1000_MANC_EN_MNG2HOST;
2276
2277                 E1000_WRITE_REG(hw, E1000_MANC, manc);
2278         }
2279 }
2280
2281 static void
2282 eth_igb_promiscuous_enable(struct rte_eth_dev *dev)
2283 {
2284         struct e1000_hw *hw =
2285                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2286         uint32_t rctl;
2287
2288         rctl = E1000_READ_REG(hw, E1000_RCTL);
2289         rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
2290         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2291 }
2292
2293 static void
2294 eth_igb_promiscuous_disable(struct rte_eth_dev *dev)
2295 {
2296         struct e1000_hw *hw =
2297                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2298         uint32_t rctl;
2299
2300         rctl = E1000_READ_REG(hw, E1000_RCTL);
2301         rctl &= (~E1000_RCTL_UPE);
2302         if (dev->data->all_multicast == 1)
2303                 rctl |= E1000_RCTL_MPE;
2304         else
2305                 rctl &= (~E1000_RCTL_MPE);
2306         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2307 }
2308
2309 static void
2310 eth_igb_allmulticast_enable(struct rte_eth_dev *dev)
2311 {
2312         struct e1000_hw *hw =
2313                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2314         uint32_t rctl;
2315
2316         rctl = E1000_READ_REG(hw, E1000_RCTL);
2317         rctl |= E1000_RCTL_MPE;
2318         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2319 }
2320
2321 static void
2322 eth_igb_allmulticast_disable(struct rte_eth_dev *dev)
2323 {
2324         struct e1000_hw *hw =
2325                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2326         uint32_t rctl;
2327
2328         if (dev->data->promiscuous == 1)
2329                 return; /* must remain in all_multicast mode */
2330         rctl = E1000_READ_REG(hw, E1000_RCTL);
2331         rctl &= (~E1000_RCTL_MPE);
2332         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2333 }
2334
2335 static int
2336 eth_igb_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
2337 {
2338         struct e1000_hw *hw =
2339                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2340         struct e1000_vfta * shadow_vfta =
2341                 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
2342         uint32_t vfta;
2343         uint32_t vid_idx;
2344         uint32_t vid_bit;
2345
2346         vid_idx = (uint32_t) ((vlan_id >> E1000_VFTA_ENTRY_SHIFT) &
2347                               E1000_VFTA_ENTRY_MASK);
2348         vid_bit = (uint32_t) (1 << (vlan_id & E1000_VFTA_ENTRY_BIT_SHIFT_MASK));
2349         vfta = E1000_READ_REG_ARRAY(hw, E1000_VFTA, vid_idx);
2350         if (on)
2351                 vfta |= vid_bit;
2352         else
2353                 vfta &= ~vid_bit;
2354         E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, vid_idx, vfta);
2355
2356         /* update local VFTA copy */
2357         shadow_vfta->vfta[vid_idx] = vfta;
2358
2359         return 0;
2360 }
2361
2362 static int
2363 eth_igb_vlan_tpid_set(struct rte_eth_dev *dev,
2364                       enum rte_vlan_type vlan_type,
2365                       uint16_t tpid)
2366 {
2367         struct e1000_hw *hw =
2368                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2369         uint32_t reg, qinq;
2370
2371         qinq = E1000_READ_REG(hw, E1000_CTRL_EXT);
2372         qinq &= E1000_CTRL_EXT_EXT_VLAN;
2373
2374         /* only outer TPID of double VLAN can be configured*/
2375         if (qinq && vlan_type == ETH_VLAN_TYPE_OUTER) {
2376                 reg = E1000_READ_REG(hw, E1000_VET);
2377                 reg = (reg & (~E1000_VET_VET_EXT)) |
2378                         ((uint32_t)tpid << E1000_VET_VET_EXT_SHIFT);
2379                 E1000_WRITE_REG(hw, E1000_VET, reg);
2380
2381                 return 0;
2382         }
2383
2384         /* all other TPID values are read-only*/
2385         PMD_DRV_LOG(ERR, "Not supported");
2386
2387         return -ENOTSUP;
2388 }
2389
2390 static void
2391 igb_vlan_hw_filter_disable(struct rte_eth_dev *dev)
2392 {
2393         struct e1000_hw *hw =
2394                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2395         uint32_t reg;
2396
2397         /* Filter Table Disable */
2398         reg = E1000_READ_REG(hw, E1000_RCTL);
2399         reg &= ~E1000_RCTL_CFIEN;
2400         reg &= ~E1000_RCTL_VFE;
2401         E1000_WRITE_REG(hw, E1000_RCTL, reg);
2402 }
2403
2404 static void
2405 igb_vlan_hw_filter_enable(struct rte_eth_dev *dev)
2406 {
2407         struct e1000_hw *hw =
2408                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2409         struct e1000_vfta * shadow_vfta =
2410                 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
2411         uint32_t reg;
2412         int i;
2413
2414         /* Filter Table Enable, CFI not used for packet acceptance */
2415         reg = E1000_READ_REG(hw, E1000_RCTL);
2416         reg &= ~E1000_RCTL_CFIEN;
2417         reg |= E1000_RCTL_VFE;
2418         E1000_WRITE_REG(hw, E1000_RCTL, reg);
2419
2420         /* restore VFTA table */
2421         for (i = 0; i < IGB_VFTA_SIZE; i++)
2422                 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, i, shadow_vfta->vfta[i]);
2423 }
2424
2425 static void
2426 igb_vlan_hw_strip_disable(struct rte_eth_dev *dev)
2427 {
2428         struct e1000_hw *hw =
2429                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2430         uint32_t reg;
2431
2432         /* VLAN Mode Disable */
2433         reg = E1000_READ_REG(hw, E1000_CTRL);
2434         reg &= ~E1000_CTRL_VME;
2435         E1000_WRITE_REG(hw, E1000_CTRL, reg);
2436 }
2437
2438 static void
2439 igb_vlan_hw_strip_enable(struct rte_eth_dev *dev)
2440 {
2441         struct e1000_hw *hw =
2442                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2443         uint32_t reg;
2444
2445         /* VLAN Mode Enable */
2446         reg = E1000_READ_REG(hw, E1000_CTRL);
2447         reg |= E1000_CTRL_VME;
2448         E1000_WRITE_REG(hw, E1000_CTRL, reg);
2449 }
2450
2451 static void
2452 igb_vlan_hw_extend_disable(struct rte_eth_dev *dev)
2453 {
2454         struct e1000_hw *hw =
2455                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2456         uint32_t reg;
2457
2458         /* CTRL_EXT: Extended VLAN */
2459         reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
2460         reg &= ~E1000_CTRL_EXT_EXTEND_VLAN;
2461         E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg);
2462
2463         /* Update maximum packet length */
2464         if (dev->data->dev_conf.rxmode.jumbo_frame == 1)
2465                 E1000_WRITE_REG(hw, E1000_RLPML,
2466                         dev->data->dev_conf.rxmode.max_rx_pkt_len +
2467                                                 VLAN_TAG_SIZE);
2468 }
2469
2470 static void
2471 igb_vlan_hw_extend_enable(struct rte_eth_dev *dev)
2472 {
2473         struct e1000_hw *hw =
2474                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2475         uint32_t reg;
2476
2477         /* CTRL_EXT: Extended VLAN */
2478         reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
2479         reg |= E1000_CTRL_EXT_EXTEND_VLAN;
2480         E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg);
2481
2482         /* Update maximum packet length */
2483         if (dev->data->dev_conf.rxmode.jumbo_frame == 1)
2484                 E1000_WRITE_REG(hw, E1000_RLPML,
2485                         dev->data->dev_conf.rxmode.max_rx_pkt_len +
2486                                                 2 * VLAN_TAG_SIZE);
2487 }
2488
2489 static void
2490 eth_igb_vlan_offload_set(struct rte_eth_dev *dev, int mask)
2491 {
2492         if(mask & ETH_VLAN_STRIP_MASK){
2493                 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
2494                         igb_vlan_hw_strip_enable(dev);
2495                 else
2496                         igb_vlan_hw_strip_disable(dev);
2497         }
2498
2499         if(mask & ETH_VLAN_FILTER_MASK){
2500                 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
2501                         igb_vlan_hw_filter_enable(dev);
2502                 else
2503                         igb_vlan_hw_filter_disable(dev);
2504         }
2505
2506         if(mask & ETH_VLAN_EXTEND_MASK){
2507                 if (dev->data->dev_conf.rxmode.hw_vlan_extend)
2508                         igb_vlan_hw_extend_enable(dev);
2509                 else
2510                         igb_vlan_hw_extend_disable(dev);
2511         }
2512 }
2513
2514
2515 /**
2516  * It enables the interrupt mask and then enable the interrupt.
2517  *
2518  * @param dev
2519  *  Pointer to struct rte_eth_dev.
2520  *
2521  * @return
2522  *  - On success, zero.
2523  *  - On failure, a negative value.
2524  */
2525 static int
2526 eth_igb_lsc_interrupt_setup(struct rte_eth_dev *dev)
2527 {
2528         struct e1000_interrupt *intr =
2529                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2530
2531         intr->mask |= E1000_ICR_LSC;
2532
2533         return 0;
2534 }
2535
2536 /* It clears the interrupt causes and enables the interrupt.
2537  * It will be called once only during nic initialized.
2538  *
2539  * @param dev
2540  *  Pointer to struct rte_eth_dev.
2541  *
2542  * @return
2543  *  - On success, zero.
2544  *  - On failure, a negative value.
2545  */
2546 static int eth_igb_rxq_interrupt_setup(struct rte_eth_dev *dev)
2547 {
2548         uint32_t mask, regval;
2549         struct e1000_hw *hw =
2550                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2551         struct rte_eth_dev_info dev_info;
2552
2553         memset(&dev_info, 0, sizeof(dev_info));
2554         eth_igb_infos_get(dev, &dev_info);
2555
2556         mask = 0xFFFFFFFF >> (32 - dev_info.max_rx_queues);
2557         regval = E1000_READ_REG(hw, E1000_EIMS);
2558         E1000_WRITE_REG(hw, E1000_EIMS, regval | mask);
2559
2560         return 0;
2561 }
2562
2563 /*
2564  * It reads ICR and gets interrupt causes, check it and set a bit flag
2565  * to update link status.
2566  *
2567  * @param dev
2568  *  Pointer to struct rte_eth_dev.
2569  *
2570  * @return
2571  *  - On success, zero.
2572  *  - On failure, a negative value.
2573  */
2574 static int
2575 eth_igb_interrupt_get_status(struct rte_eth_dev *dev)
2576 {
2577         uint32_t icr;
2578         struct e1000_hw *hw =
2579                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2580         struct e1000_interrupt *intr =
2581                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2582
2583         igb_intr_disable(hw);
2584
2585         /* read-on-clear nic registers here */
2586         icr = E1000_READ_REG(hw, E1000_ICR);
2587
2588         intr->flags = 0;
2589         if (icr & E1000_ICR_LSC) {
2590                 intr->flags |= E1000_FLAG_NEED_LINK_UPDATE;
2591         }
2592
2593         if (icr & E1000_ICR_VMMB)
2594                 intr->flags |= E1000_FLAG_MAILBOX;
2595
2596         return 0;
2597 }
2598
2599 /*
2600  * It executes link_update after knowing an interrupt is prsent.
2601  *
2602  * @param dev
2603  *  Pointer to struct rte_eth_dev.
2604  *
2605  * @return
2606  *  - On success, zero.
2607  *  - On failure, a negative value.
2608  */
2609 static int
2610 eth_igb_interrupt_action(struct rte_eth_dev *dev)
2611 {
2612         struct e1000_hw *hw =
2613                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2614         struct e1000_interrupt *intr =
2615                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2616         uint32_t tctl, rctl;
2617         struct rte_eth_link link;
2618         int ret;
2619
2620         if (intr->flags & E1000_FLAG_MAILBOX) {
2621                 igb_pf_mbx_process(dev);
2622                 intr->flags &= ~E1000_FLAG_MAILBOX;
2623         }
2624
2625         igb_intr_enable(dev);
2626         rte_intr_enable(&(dev->pci_dev->intr_handle));
2627
2628         if (intr->flags & E1000_FLAG_NEED_LINK_UPDATE) {
2629                 intr->flags &= ~E1000_FLAG_NEED_LINK_UPDATE;
2630
2631                 /* set get_link_status to check register later */
2632                 hw->mac.get_link_status = 1;
2633                 ret = eth_igb_link_update(dev, 0);
2634
2635                 /* check if link has changed */
2636                 if (ret < 0)
2637                         return 0;
2638
2639                 memset(&link, 0, sizeof(link));
2640                 rte_igb_dev_atomic_read_link_status(dev, &link);
2641                 if (link.link_status) {
2642                         PMD_INIT_LOG(INFO,
2643                                      " Port %d: Link Up - speed %u Mbps - %s",
2644                                      dev->data->port_id,
2645                                      (unsigned)link.link_speed,
2646                                      link.link_duplex == ETH_LINK_FULL_DUPLEX ?
2647                                      "full-duplex" : "half-duplex");
2648                 } else {
2649                         PMD_INIT_LOG(INFO, " Port %d: Link Down",
2650                                      dev->data->port_id);
2651                 }
2652
2653                 PMD_INIT_LOG(DEBUG, "PCI Address: %04d:%02d:%02d:%d",
2654                              dev->pci_dev->addr.domain,
2655                              dev->pci_dev->addr.bus,
2656                              dev->pci_dev->addr.devid,
2657                              dev->pci_dev->addr.function);
2658                 tctl = E1000_READ_REG(hw, E1000_TCTL);
2659                 rctl = E1000_READ_REG(hw, E1000_RCTL);
2660                 if (link.link_status) {
2661                         /* enable Tx/Rx */
2662                         tctl |= E1000_TCTL_EN;
2663                         rctl |= E1000_RCTL_EN;
2664                 } else {
2665                         /* disable Tx/Rx */
2666                         tctl &= ~E1000_TCTL_EN;
2667                         rctl &= ~E1000_RCTL_EN;
2668                 }
2669                 E1000_WRITE_REG(hw, E1000_TCTL, tctl);
2670                 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2671                 E1000_WRITE_FLUSH(hw);
2672                 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC);
2673         }
2674
2675         return 0;
2676 }
2677
2678 /**
2679  * Interrupt handler which shall be registered at first.
2680  *
2681  * @param handle
2682  *  Pointer to interrupt handle.
2683  * @param param
2684  *  The address of parameter (struct rte_eth_dev *) regsitered before.
2685  *
2686  * @return
2687  *  void
2688  */
2689 static void
2690 eth_igb_interrupt_handler(__rte_unused struct rte_intr_handle *handle,
2691                                                         void *param)
2692 {
2693         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
2694
2695         eth_igb_interrupt_get_status(dev);
2696         eth_igb_interrupt_action(dev);
2697 }
2698
2699 static int
2700 eth_igbvf_interrupt_get_status(struct rte_eth_dev *dev)
2701 {
2702         uint32_t eicr;
2703         struct e1000_hw *hw =
2704                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2705         struct e1000_interrupt *intr =
2706                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2707
2708         igbvf_intr_disable(hw);
2709
2710         /* read-on-clear nic registers here */
2711         eicr = E1000_READ_REG(hw, E1000_EICR);
2712         intr->flags = 0;
2713
2714         if (eicr == E1000_VTIVAR_MISC_MAILBOX)
2715                 intr->flags |= E1000_FLAG_MAILBOX;
2716
2717         return 0;
2718 }
2719
2720 void igbvf_mbx_process(struct rte_eth_dev *dev)
2721 {
2722         struct e1000_hw *hw =
2723                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2724         struct e1000_mbx_info *mbx = &hw->mbx;
2725         u32 in_msg = 0;
2726
2727         if (mbx->ops.read(hw, &in_msg, 1, 0))
2728                 return;
2729
2730         /* PF reset VF event */
2731         if (in_msg == E1000_PF_CONTROL_MSG)
2732                 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_RESET);
2733 }
2734
2735 static int
2736 eth_igbvf_interrupt_action(struct rte_eth_dev *dev)
2737 {
2738         struct e1000_interrupt *intr =
2739                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2740
2741         if (intr->flags & E1000_FLAG_MAILBOX) {
2742                 igbvf_mbx_process(dev);
2743                 intr->flags &= ~E1000_FLAG_MAILBOX;
2744         }
2745
2746         igbvf_intr_enable(dev);
2747         rte_intr_enable(&dev->pci_dev->intr_handle);
2748
2749         return 0;
2750 }
2751
2752 static void
2753 eth_igbvf_interrupt_handler(__rte_unused struct rte_intr_handle *handle,
2754                             void *param)
2755 {
2756         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
2757
2758         eth_igbvf_interrupt_get_status(dev);
2759         eth_igbvf_interrupt_action(dev);
2760 }
2761
2762 static int
2763 eth_igb_led_on(struct rte_eth_dev *dev)
2764 {
2765         struct e1000_hw *hw;
2766
2767         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2768         return e1000_led_on(hw) == E1000_SUCCESS ? 0 : -ENOTSUP;
2769 }
2770
2771 static int
2772 eth_igb_led_off(struct rte_eth_dev *dev)
2773 {
2774         struct e1000_hw *hw;
2775
2776         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2777         return e1000_led_off(hw) == E1000_SUCCESS ? 0 : -ENOTSUP;
2778 }
2779
2780 static int
2781 eth_igb_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
2782 {
2783         struct e1000_hw *hw;
2784         uint32_t ctrl;
2785         int tx_pause;
2786         int rx_pause;
2787
2788         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2789         fc_conf->pause_time = hw->fc.pause_time;
2790         fc_conf->high_water = hw->fc.high_water;
2791         fc_conf->low_water = hw->fc.low_water;
2792         fc_conf->send_xon = hw->fc.send_xon;
2793         fc_conf->autoneg = hw->mac.autoneg;
2794
2795         /*
2796          * Return rx_pause and tx_pause status according to actual setting of
2797          * the TFCE and RFCE bits in the CTRL register.
2798          */
2799         ctrl = E1000_READ_REG(hw, E1000_CTRL);
2800         if (ctrl & E1000_CTRL_TFCE)
2801                 tx_pause = 1;
2802         else
2803                 tx_pause = 0;
2804
2805         if (ctrl & E1000_CTRL_RFCE)
2806                 rx_pause = 1;
2807         else
2808                 rx_pause = 0;
2809
2810         if (rx_pause && tx_pause)
2811                 fc_conf->mode = RTE_FC_FULL;
2812         else if (rx_pause)
2813                 fc_conf->mode = RTE_FC_RX_PAUSE;
2814         else if (tx_pause)
2815                 fc_conf->mode = RTE_FC_TX_PAUSE;
2816         else
2817                 fc_conf->mode = RTE_FC_NONE;
2818
2819         return 0;
2820 }
2821
2822 static int
2823 eth_igb_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
2824 {
2825         struct e1000_hw *hw;
2826         int err;
2827         enum e1000_fc_mode rte_fcmode_2_e1000_fcmode[] = {
2828                 e1000_fc_none,
2829                 e1000_fc_rx_pause,
2830                 e1000_fc_tx_pause,
2831                 e1000_fc_full
2832         };
2833         uint32_t rx_buf_size;
2834         uint32_t max_high_water;
2835         uint32_t rctl;
2836
2837         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2838         if (fc_conf->autoneg != hw->mac.autoneg)
2839                 return -ENOTSUP;
2840         rx_buf_size = igb_get_rx_buffer_size(hw);
2841         PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
2842
2843         /* At least reserve one Ethernet frame for watermark */
2844         max_high_water = rx_buf_size - ETHER_MAX_LEN;
2845         if ((fc_conf->high_water > max_high_water) ||
2846             (fc_conf->high_water < fc_conf->low_water)) {
2847                 PMD_INIT_LOG(ERR, "e1000 incorrect high/low water value");
2848                 PMD_INIT_LOG(ERR, "high water must <=  0x%x", max_high_water);
2849                 return -EINVAL;
2850         }
2851
2852         hw->fc.requested_mode = rte_fcmode_2_e1000_fcmode[fc_conf->mode];
2853         hw->fc.pause_time     = fc_conf->pause_time;
2854         hw->fc.high_water     = fc_conf->high_water;
2855         hw->fc.low_water      = fc_conf->low_water;
2856         hw->fc.send_xon       = fc_conf->send_xon;
2857
2858         err = e1000_setup_link_generic(hw);
2859         if (err == E1000_SUCCESS) {
2860
2861                 /* check if we want to forward MAC frames - driver doesn't have native
2862                  * capability to do that, so we'll write the registers ourselves */
2863
2864                 rctl = E1000_READ_REG(hw, E1000_RCTL);
2865
2866                 /* set or clear MFLCN.PMCF bit depending on configuration */
2867                 if (fc_conf->mac_ctrl_frame_fwd != 0)
2868                         rctl |= E1000_RCTL_PMCF;
2869                 else
2870                         rctl &= ~E1000_RCTL_PMCF;
2871
2872                 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2873                 E1000_WRITE_FLUSH(hw);
2874
2875                 return 0;
2876         }
2877
2878         PMD_INIT_LOG(ERR, "e1000_setup_link_generic = 0x%x", err);
2879         return -EIO;
2880 }
2881
2882 #define E1000_RAH_POOLSEL_SHIFT      (18)
2883 static void
2884 eth_igb_rar_set(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
2885                 uint32_t index, __rte_unused uint32_t pool)
2886 {
2887         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2888         uint32_t rah;
2889
2890         e1000_rar_set(hw, mac_addr->addr_bytes, index);
2891         rah = E1000_READ_REG(hw, E1000_RAH(index));
2892         rah |= (0x1 << (E1000_RAH_POOLSEL_SHIFT + pool));
2893         E1000_WRITE_REG(hw, E1000_RAH(index), rah);
2894 }
2895
2896 static void
2897 eth_igb_rar_clear(struct rte_eth_dev *dev, uint32_t index)
2898 {
2899         uint8_t addr[ETHER_ADDR_LEN];
2900         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2901
2902         memset(addr, 0, sizeof(addr));
2903
2904         e1000_rar_set(hw, addr, index);
2905 }
2906
2907 static void
2908 eth_igb_default_mac_addr_set(struct rte_eth_dev *dev,
2909                                 struct ether_addr *addr)
2910 {
2911         eth_igb_rar_clear(dev, 0);
2912
2913         eth_igb_rar_set(dev, (void *)addr, 0, 0);
2914 }
2915 /*
2916  * Virtual Function operations
2917  */
2918 static void
2919 igbvf_intr_disable(struct e1000_hw *hw)
2920 {
2921         PMD_INIT_FUNC_TRACE();
2922
2923         /* Clear interrupt mask to stop from interrupts being generated */
2924         E1000_WRITE_REG(hw, E1000_EIMC, 0xFFFF);
2925
2926         E1000_WRITE_FLUSH(hw);
2927 }
2928
2929 static void
2930 igbvf_stop_adapter(struct rte_eth_dev *dev)
2931 {
2932         u32 reg_val;
2933         u16 i;
2934         struct rte_eth_dev_info dev_info;
2935         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2936
2937         memset(&dev_info, 0, sizeof(dev_info));
2938         eth_igbvf_infos_get(dev, &dev_info);
2939
2940         /* Clear interrupt mask to stop from interrupts being generated */
2941         igbvf_intr_disable(hw);
2942
2943         /* Clear any pending interrupts, flush previous writes */
2944         E1000_READ_REG(hw, E1000_EICR);
2945
2946         /* Disable the transmit unit.  Each queue must be disabled. */
2947         for (i = 0; i < dev_info.max_tx_queues; i++)
2948                 E1000_WRITE_REG(hw, E1000_TXDCTL(i), E1000_TXDCTL_SWFLSH);
2949
2950         /* Disable the receive unit by stopping each queue */
2951         for (i = 0; i < dev_info.max_rx_queues; i++) {
2952                 reg_val = E1000_READ_REG(hw, E1000_RXDCTL(i));
2953                 reg_val &= ~E1000_RXDCTL_QUEUE_ENABLE;
2954                 E1000_WRITE_REG(hw, E1000_RXDCTL(i), reg_val);
2955                 while (E1000_READ_REG(hw, E1000_RXDCTL(i)) & E1000_RXDCTL_QUEUE_ENABLE)
2956                         ;
2957         }
2958
2959         /* flush all queues disables */
2960         E1000_WRITE_FLUSH(hw);
2961         msec_delay(2);
2962 }
2963
2964 static int eth_igbvf_link_update(struct e1000_hw *hw)
2965 {
2966         struct e1000_mbx_info *mbx = &hw->mbx;
2967         struct e1000_mac_info *mac = &hw->mac;
2968         int ret_val = E1000_SUCCESS;
2969
2970         PMD_INIT_LOG(DEBUG, "e1000_check_for_link_vf");
2971
2972         /*
2973          * We only want to run this if there has been a rst asserted.
2974          * in this case that could mean a link change, device reset,
2975          * or a virtual function reset
2976          */
2977
2978         /* If we were hit with a reset or timeout drop the link */
2979         if (!e1000_check_for_rst(hw, 0) || !mbx->timeout)
2980                 mac->get_link_status = TRUE;
2981
2982         if (!mac->get_link_status)
2983                 goto out;
2984
2985         /* if link status is down no point in checking to see if pf is up */
2986         if (!(E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU))
2987                 goto out;
2988
2989         /* if we passed all the tests above then the link is up and we no
2990          * longer need to check for link */
2991         mac->get_link_status = FALSE;
2992
2993 out:
2994         return ret_val;
2995 }
2996
2997
2998 static int
2999 igbvf_dev_configure(struct rte_eth_dev *dev)
3000 {
3001         struct rte_eth_conf* conf = &dev->data->dev_conf;
3002
3003         PMD_INIT_LOG(DEBUG, "Configured Virtual Function port id: %d",
3004                      dev->data->port_id);
3005
3006         /*
3007          * VF has no ability to enable/disable HW CRC
3008          * Keep the persistent behavior the same as Host PF
3009          */
3010 #ifndef RTE_LIBRTE_E1000_PF_DISABLE_STRIP_CRC
3011         if (!conf->rxmode.hw_strip_crc) {
3012                 PMD_INIT_LOG(NOTICE, "VF can't disable HW CRC Strip");
3013                 conf->rxmode.hw_strip_crc = 1;
3014         }
3015 #else
3016         if (conf->rxmode.hw_strip_crc) {
3017                 PMD_INIT_LOG(NOTICE, "VF can't enable HW CRC Strip");
3018                 conf->rxmode.hw_strip_crc = 0;
3019         }
3020 #endif
3021
3022         return 0;
3023 }
3024
3025 static int
3026 igbvf_dev_start(struct rte_eth_dev *dev)
3027 {
3028         struct e1000_hw *hw =
3029                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3030         struct e1000_adapter *adapter =
3031                 E1000_DEV_PRIVATE(dev->data->dev_private);
3032         int ret;
3033         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
3034         uint32_t intr_vector = 0;
3035
3036         PMD_INIT_FUNC_TRACE();
3037
3038         hw->mac.ops.reset_hw(hw);
3039         adapter->stopped = 0;
3040
3041         /* Set all vfta */
3042         igbvf_set_vfta_all(dev,1);
3043
3044         eth_igbvf_tx_init(dev);
3045
3046         /* This can fail when allocating mbufs for descriptor rings */
3047         ret = eth_igbvf_rx_init(dev);
3048         if (ret) {
3049                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
3050                 igb_dev_clear_queues(dev);
3051                 return ret;
3052         }
3053
3054         /* check and configure queue intr-vector mapping */
3055         if (dev->data->dev_conf.intr_conf.rxq != 0) {
3056                 intr_vector = dev->data->nb_rx_queues;
3057                 ret = rte_intr_efd_enable(intr_handle, intr_vector);
3058                 if (ret)
3059                         return ret;
3060         }
3061
3062         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
3063                 intr_handle->intr_vec =
3064                         rte_zmalloc("intr_vec",
3065                                     dev->data->nb_rx_queues * sizeof(int), 0);
3066                 if (!intr_handle->intr_vec) {
3067                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
3068                                      " intr_vec\n", dev->data->nb_rx_queues);
3069                         return -ENOMEM;
3070                 }
3071         }
3072
3073         eth_igbvf_configure_msix_intr(dev);
3074
3075         /* enable uio/vfio intr/eventfd mapping */
3076         rte_intr_enable(intr_handle);
3077
3078         /* resume enabled intr since hw reset */
3079         igbvf_intr_enable(dev);
3080
3081         return 0;
3082 }
3083
3084 static void
3085 igbvf_dev_stop(struct rte_eth_dev *dev)
3086 {
3087         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
3088
3089         PMD_INIT_FUNC_TRACE();
3090
3091         igbvf_stop_adapter(dev);
3092
3093         /*
3094           * Clear what we set, but we still keep shadow_vfta to
3095           * restore after device starts
3096           */
3097         igbvf_set_vfta_all(dev,0);
3098
3099         igb_dev_clear_queues(dev);
3100
3101         /* disable intr eventfd mapping */
3102         rte_intr_disable(intr_handle);
3103
3104         /* Clean datapath event and queue/vec mapping */
3105         rte_intr_efd_disable(intr_handle);
3106         if (intr_handle->intr_vec) {
3107                 rte_free(intr_handle->intr_vec);
3108                 intr_handle->intr_vec = NULL;
3109         }
3110 }
3111
3112 static void
3113 igbvf_dev_close(struct rte_eth_dev *dev)
3114 {
3115         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3116         struct e1000_adapter *adapter =
3117                 E1000_DEV_PRIVATE(dev->data->dev_private);
3118         struct ether_addr addr;
3119
3120         PMD_INIT_FUNC_TRACE();
3121
3122         e1000_reset_hw(hw);
3123
3124         igbvf_dev_stop(dev);
3125         adapter->stopped = 1;
3126         igb_dev_free_queues(dev);
3127
3128         /**
3129          * reprogram the RAR with a zero mac address,
3130          * to ensure that the VF traffic goes to the PF
3131          * after stop, close and detach of the VF.
3132          **/
3133
3134         memset(&addr, 0, sizeof(addr));
3135         igbvf_default_mac_addr_set(dev, &addr);
3136 }
3137
3138 static void
3139 igbvf_promiscuous_enable(struct rte_eth_dev *dev)
3140 {
3141         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3142
3143         /* Set both unicast and multicast promisc */
3144         e1000_promisc_set_vf(hw, e1000_promisc_enabled);
3145 }
3146
3147 static void
3148 igbvf_promiscuous_disable(struct rte_eth_dev *dev)
3149 {
3150         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3151
3152         /* If in allmulticast mode leave multicast promisc */
3153         if (dev->data->all_multicast == 1)
3154                 e1000_promisc_set_vf(hw, e1000_promisc_multicast);
3155         else
3156                 e1000_promisc_set_vf(hw, e1000_promisc_disabled);
3157 }
3158
3159 static void
3160 igbvf_allmulticast_enable(struct rte_eth_dev *dev)
3161 {
3162         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3163
3164         /* In promiscuous mode multicast promisc already set */
3165         if (dev->data->promiscuous == 0)
3166                 e1000_promisc_set_vf(hw, e1000_promisc_multicast);
3167 }
3168
3169 static void
3170 igbvf_allmulticast_disable(struct rte_eth_dev *dev)
3171 {
3172         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3173
3174         /* In promiscuous mode leave multicast promisc enabled */
3175         if (dev->data->promiscuous == 0)
3176                 e1000_promisc_set_vf(hw, e1000_promisc_disabled);
3177 }
3178
3179 static int igbvf_set_vfta(struct e1000_hw *hw, uint16_t vid, bool on)
3180 {
3181         struct e1000_mbx_info *mbx = &hw->mbx;
3182         uint32_t msgbuf[2];
3183         s32 err;
3184
3185         /* After set vlan, vlan strip will also be enabled in igb driver*/
3186         msgbuf[0] = E1000_VF_SET_VLAN;
3187         msgbuf[1] = vid;
3188         /* Setting the 8 bit field MSG INFO to TRUE indicates "add" */
3189         if (on)
3190                 msgbuf[0] |= E1000_VF_SET_VLAN_ADD;
3191
3192         err = mbx->ops.write_posted(hw, msgbuf, 2, 0);
3193         if (err)
3194                 goto mbx_err;
3195
3196         err = mbx->ops.read_posted(hw, msgbuf, 2, 0);
3197         if (err)
3198                 goto mbx_err;
3199
3200         msgbuf[0] &= ~E1000_VT_MSGTYPE_CTS;
3201         if (msgbuf[0] == (E1000_VF_SET_VLAN | E1000_VT_MSGTYPE_NACK))
3202                 err = -EINVAL;
3203
3204 mbx_err:
3205         return err;
3206 }
3207
3208 static void igbvf_set_vfta_all(struct rte_eth_dev *dev, bool on)
3209 {
3210         struct e1000_hw *hw =
3211                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3212         struct e1000_vfta * shadow_vfta =
3213                 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
3214         int i = 0, j = 0, vfta = 0, mask = 1;
3215
3216         for (i = 0; i < IGB_VFTA_SIZE; i++){
3217                 vfta = shadow_vfta->vfta[i];
3218                 if(vfta){
3219                         mask = 1;
3220                         for (j = 0; j < 32; j++){
3221                                 if(vfta & mask)
3222                                         igbvf_set_vfta(hw,
3223                                                 (uint16_t)((i<<5)+j), on);
3224                                 mask<<=1;
3225                         }
3226                 }
3227         }
3228
3229 }
3230
3231 static int
3232 igbvf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
3233 {
3234         struct e1000_hw *hw =
3235                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3236         struct e1000_vfta * shadow_vfta =
3237                 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
3238         uint32_t vid_idx = 0;
3239         uint32_t vid_bit = 0;
3240         int ret = 0;
3241
3242         PMD_INIT_FUNC_TRACE();
3243
3244         /*vind is not used in VF driver, set to 0, check ixgbe_set_vfta_vf*/
3245         ret = igbvf_set_vfta(hw, vlan_id, !!on);
3246         if(ret){
3247                 PMD_INIT_LOG(ERR, "Unable to set VF vlan");
3248                 return ret;
3249         }
3250         vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
3251         vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
3252
3253         /*Save what we set and retore it after device reset*/
3254         if (on)
3255                 shadow_vfta->vfta[vid_idx] |= vid_bit;
3256         else
3257                 shadow_vfta->vfta[vid_idx] &= ~vid_bit;
3258
3259         return 0;
3260 }
3261
3262 static void
3263 igbvf_default_mac_addr_set(struct rte_eth_dev *dev, struct ether_addr *addr)
3264 {
3265         struct e1000_hw *hw =
3266                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3267
3268         /* index is not used by rar_set() */
3269         hw->mac.ops.rar_set(hw, (void *)addr, 0);
3270 }
3271
3272
3273 static int
3274 eth_igb_rss_reta_update(struct rte_eth_dev *dev,
3275                         struct rte_eth_rss_reta_entry64 *reta_conf,
3276                         uint16_t reta_size)
3277 {
3278         uint8_t i, j, mask;
3279         uint32_t reta, r;
3280         uint16_t idx, shift;
3281         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3282
3283         if (reta_size != ETH_RSS_RETA_SIZE_128) {
3284                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
3285                         "(%d) doesn't match the number hardware can supported "
3286                         "(%d)\n", reta_size, ETH_RSS_RETA_SIZE_128);
3287                 return -EINVAL;
3288         }
3289
3290         for (i = 0; i < reta_size; i += IGB_4_BIT_WIDTH) {
3291                 idx = i / RTE_RETA_GROUP_SIZE;
3292                 shift = i % RTE_RETA_GROUP_SIZE;
3293                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
3294                                                 IGB_4_BIT_MASK);
3295                 if (!mask)
3296                         continue;
3297                 if (mask == IGB_4_BIT_MASK)
3298                         r = 0;
3299                 else
3300                         r = E1000_READ_REG(hw, E1000_RETA(i >> 2));
3301                 for (j = 0, reta = 0; j < IGB_4_BIT_WIDTH; j++) {
3302                         if (mask & (0x1 << j))
3303                                 reta |= reta_conf[idx].reta[shift + j] <<
3304                                                         (CHAR_BIT * j);
3305                         else
3306                                 reta |= r & (IGB_8_BIT_MASK << (CHAR_BIT * j));
3307                 }
3308                 E1000_WRITE_REG(hw, E1000_RETA(i >> 2), reta);
3309         }
3310
3311         return 0;
3312 }
3313
3314 static int
3315 eth_igb_rss_reta_query(struct rte_eth_dev *dev,
3316                        struct rte_eth_rss_reta_entry64 *reta_conf,
3317                        uint16_t reta_size)
3318 {
3319         uint8_t i, j, mask;
3320         uint32_t reta;
3321         uint16_t idx, shift;
3322         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3323
3324         if (reta_size != ETH_RSS_RETA_SIZE_128) {
3325                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
3326                         "(%d) doesn't match the number hardware can supported "
3327                         "(%d)\n", reta_size, ETH_RSS_RETA_SIZE_128);
3328                 return -EINVAL;
3329         }
3330
3331         for (i = 0; i < reta_size; i += IGB_4_BIT_WIDTH) {
3332                 idx = i / RTE_RETA_GROUP_SIZE;
3333                 shift = i % RTE_RETA_GROUP_SIZE;
3334                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
3335                                                 IGB_4_BIT_MASK);
3336                 if (!mask)
3337                         continue;
3338                 reta = E1000_READ_REG(hw, E1000_RETA(i >> 2));
3339                 for (j = 0; j < IGB_4_BIT_WIDTH; j++) {
3340                         if (mask & (0x1 << j))
3341                                 reta_conf[idx].reta[shift + j] =
3342                                         ((reta >> (CHAR_BIT * j)) &
3343                                                 IGB_8_BIT_MASK);
3344                 }
3345         }
3346
3347         return 0;
3348 }
3349
3350 #define MAC_TYPE_FILTER_SUP(type)    do {\
3351         if ((type) != e1000_82580 && (type) != e1000_i350 &&\
3352                 (type) != e1000_82576)\
3353                 return -ENOTSUP;\
3354 } while (0)
3355
3356 static int
3357 eth_igb_syn_filter_set(struct rte_eth_dev *dev,
3358                         struct rte_eth_syn_filter *filter,
3359                         bool add)
3360 {
3361         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3362         uint32_t synqf, rfctl;
3363
3364         if (filter->queue >= IGB_MAX_RX_QUEUE_NUM)
3365                 return -EINVAL;
3366
3367         synqf = E1000_READ_REG(hw, E1000_SYNQF(0));
3368
3369         if (add) {
3370                 if (synqf & E1000_SYN_FILTER_ENABLE)
3371                         return -EINVAL;
3372
3373                 synqf = (uint32_t)(((filter->queue << E1000_SYN_FILTER_QUEUE_SHIFT) &
3374                         E1000_SYN_FILTER_QUEUE) | E1000_SYN_FILTER_ENABLE);
3375
3376                 rfctl = E1000_READ_REG(hw, E1000_RFCTL);
3377                 if (filter->hig_pri)
3378                         rfctl |= E1000_RFCTL_SYNQFP;
3379                 else
3380                         rfctl &= ~E1000_RFCTL_SYNQFP;
3381
3382                 E1000_WRITE_REG(hw, E1000_RFCTL, rfctl);
3383         } else {
3384                 if (!(synqf & E1000_SYN_FILTER_ENABLE))
3385                         return -ENOENT;
3386                 synqf = 0;
3387         }
3388
3389         E1000_WRITE_REG(hw, E1000_SYNQF(0), synqf);
3390         E1000_WRITE_FLUSH(hw);
3391         return 0;
3392 }
3393
3394 static int
3395 eth_igb_syn_filter_get(struct rte_eth_dev *dev,
3396                         struct rte_eth_syn_filter *filter)
3397 {
3398         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3399         uint32_t synqf, rfctl;
3400
3401         synqf = E1000_READ_REG(hw, E1000_SYNQF(0));
3402         if (synqf & E1000_SYN_FILTER_ENABLE) {
3403                 rfctl = E1000_READ_REG(hw, E1000_RFCTL);
3404                 filter->hig_pri = (rfctl & E1000_RFCTL_SYNQFP) ? 1 : 0;
3405                 filter->queue = (uint8_t)((synqf & E1000_SYN_FILTER_QUEUE) >>
3406                                 E1000_SYN_FILTER_QUEUE_SHIFT);
3407                 return 0;
3408         }
3409
3410         return -ENOENT;
3411 }
3412
3413 static int
3414 eth_igb_syn_filter_handle(struct rte_eth_dev *dev,
3415                         enum rte_filter_op filter_op,
3416                         void *arg)
3417 {
3418         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3419         int ret;
3420
3421         MAC_TYPE_FILTER_SUP(hw->mac.type);
3422
3423         if (filter_op == RTE_ETH_FILTER_NOP)
3424                 return 0;
3425
3426         if (arg == NULL) {
3427                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
3428                             filter_op);
3429                 return -EINVAL;
3430         }
3431
3432         switch (filter_op) {
3433         case RTE_ETH_FILTER_ADD:
3434                 ret = eth_igb_syn_filter_set(dev,
3435                                 (struct rte_eth_syn_filter *)arg,
3436                                 TRUE);
3437                 break;
3438         case RTE_ETH_FILTER_DELETE:
3439                 ret = eth_igb_syn_filter_set(dev,
3440                                 (struct rte_eth_syn_filter *)arg,
3441                                 FALSE);
3442                 break;
3443         case RTE_ETH_FILTER_GET:
3444                 ret = eth_igb_syn_filter_get(dev,
3445                                 (struct rte_eth_syn_filter *)arg);
3446                 break;
3447         default:
3448                 PMD_DRV_LOG(ERR, "unsupported operation %u\n", filter_op);
3449                 ret = -EINVAL;
3450                 break;
3451         }
3452
3453         return ret;
3454 }
3455
3456 #define MAC_TYPE_FILTER_SUP_EXT(type)    do {\
3457         if ((type) != e1000_82580 && (type) != e1000_i350)\
3458                 return -ENOSYS; \
3459 } while (0)
3460
3461 /* translate elements in struct rte_eth_ntuple_filter to struct e1000_2tuple_filter_info*/
3462 static inline int
3463 ntuple_filter_to_2tuple(struct rte_eth_ntuple_filter *filter,
3464                         struct e1000_2tuple_filter_info *filter_info)
3465 {
3466         if (filter->queue >= IGB_MAX_RX_QUEUE_NUM)
3467                 return -EINVAL;
3468         if (filter->priority > E1000_2TUPLE_MAX_PRI)
3469                 return -EINVAL;  /* filter index is out of range. */
3470         if (filter->tcp_flags > TCP_FLAG_ALL)
3471                 return -EINVAL;  /* flags is invalid. */
3472
3473         switch (filter->dst_port_mask) {
3474         case UINT16_MAX:
3475                 filter_info->dst_port_mask = 0;
3476                 filter_info->dst_port = filter->dst_port;
3477                 break;
3478         case 0:
3479                 filter_info->dst_port_mask = 1;
3480                 break;
3481         default:
3482                 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
3483                 return -EINVAL;
3484         }
3485
3486         switch (filter->proto_mask) {
3487         case UINT8_MAX:
3488                 filter_info->proto_mask = 0;
3489                 filter_info->proto = filter->proto;
3490                 break;
3491         case 0:
3492                 filter_info->proto_mask = 1;
3493                 break;
3494         default:
3495                 PMD_DRV_LOG(ERR, "invalid protocol mask.");
3496                 return -EINVAL;
3497         }
3498
3499         filter_info->priority = (uint8_t)filter->priority;
3500         if (filter->flags & RTE_NTUPLE_FLAGS_TCP_FLAG)
3501                 filter_info->tcp_flags = filter->tcp_flags;
3502         else
3503                 filter_info->tcp_flags = 0;
3504
3505         return 0;
3506 }
3507
3508 static inline struct e1000_2tuple_filter *
3509 igb_2tuple_filter_lookup(struct e1000_2tuple_filter_list *filter_list,
3510                         struct e1000_2tuple_filter_info *key)
3511 {
3512         struct e1000_2tuple_filter *it;
3513
3514         TAILQ_FOREACH(it, filter_list, entries) {
3515                 if (memcmp(key, &it->filter_info,
3516                         sizeof(struct e1000_2tuple_filter_info)) == 0) {
3517                         return it;
3518                 }
3519         }
3520         return NULL;
3521 }
3522
3523 /*
3524  * igb_add_2tuple_filter - add a 2tuple filter
3525  *
3526  * @param
3527  * dev: Pointer to struct rte_eth_dev.
3528  * ntuple_filter: ponter to the filter that will be added.
3529  *
3530  * @return
3531  *    - On success, zero.
3532  *    - On failure, a negative value.
3533  */
3534 static int
3535 igb_add_2tuple_filter(struct rte_eth_dev *dev,
3536                         struct rte_eth_ntuple_filter *ntuple_filter)
3537 {
3538         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3539         struct e1000_filter_info *filter_info =
3540                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3541         struct e1000_2tuple_filter *filter;
3542         uint32_t ttqf = E1000_TTQF_DISABLE_MASK;
3543         uint32_t imir, imir_ext = E1000_IMIREXT_SIZE_BP;
3544         int i, ret;
3545
3546         filter = rte_zmalloc("e1000_2tuple_filter",
3547                         sizeof(struct e1000_2tuple_filter), 0);
3548         if (filter == NULL)
3549                 return -ENOMEM;
3550
3551         ret = ntuple_filter_to_2tuple(ntuple_filter,
3552                                       &filter->filter_info);
3553         if (ret < 0) {
3554                 rte_free(filter);
3555                 return ret;
3556         }
3557         if (igb_2tuple_filter_lookup(&filter_info->twotuple_list,
3558                                          &filter->filter_info) != NULL) {
3559                 PMD_DRV_LOG(ERR, "filter exists.");
3560                 rte_free(filter);
3561                 return -EEXIST;
3562         }
3563         filter->queue = ntuple_filter->queue;
3564
3565         /*
3566          * look for an unused 2tuple filter index,
3567          * and insert the filter to list.
3568          */
3569         for (i = 0; i < E1000_MAX_TTQF_FILTERS; i++) {
3570                 if (!(filter_info->twotuple_mask & (1 << i))) {
3571                         filter_info->twotuple_mask |= 1 << i;
3572                         filter->index = i;
3573                         TAILQ_INSERT_TAIL(&filter_info->twotuple_list,
3574                                           filter,
3575                                           entries);
3576                         break;
3577                 }
3578         }
3579         if (i >= E1000_MAX_TTQF_FILTERS) {
3580                 PMD_DRV_LOG(ERR, "2tuple filters are full.");
3581                 rte_free(filter);
3582                 return -ENOSYS;
3583         }
3584
3585         imir = (uint32_t)(filter->filter_info.dst_port & E1000_IMIR_DSTPORT);
3586         if (filter->filter_info.dst_port_mask == 1) /* 1b means not compare. */
3587                 imir |= E1000_IMIR_PORT_BP;
3588         else
3589                 imir &= ~E1000_IMIR_PORT_BP;
3590
3591         imir |= filter->filter_info.priority << E1000_IMIR_PRIORITY_SHIFT;
3592
3593         ttqf |= E1000_TTQF_QUEUE_ENABLE;
3594         ttqf |= (uint32_t)(filter->queue << E1000_TTQF_QUEUE_SHIFT);
3595         ttqf |= (uint32_t)(filter->filter_info.proto & E1000_TTQF_PROTOCOL_MASK);
3596         if (filter->filter_info.proto_mask == 0)
3597                 ttqf &= ~E1000_TTQF_MASK_ENABLE;
3598
3599         /* tcp flags bits setting. */
3600         if (filter->filter_info.tcp_flags & TCP_FLAG_ALL) {
3601                 if (filter->filter_info.tcp_flags & TCP_URG_FLAG)
3602                         imir_ext |= E1000_IMIREXT_CTRL_URG;
3603                 if (filter->filter_info.tcp_flags & TCP_ACK_FLAG)
3604                         imir_ext |= E1000_IMIREXT_CTRL_ACK;
3605                 if (filter->filter_info.tcp_flags & TCP_PSH_FLAG)
3606                         imir_ext |= E1000_IMIREXT_CTRL_PSH;
3607                 if (filter->filter_info.tcp_flags & TCP_RST_FLAG)
3608                         imir_ext |= E1000_IMIREXT_CTRL_RST;
3609                 if (filter->filter_info.tcp_flags & TCP_SYN_FLAG)
3610                         imir_ext |= E1000_IMIREXT_CTRL_SYN;
3611                 if (filter->filter_info.tcp_flags & TCP_FIN_FLAG)
3612                         imir_ext |= E1000_IMIREXT_CTRL_FIN;
3613         } else
3614                 imir_ext |= E1000_IMIREXT_CTRL_BP;
3615         E1000_WRITE_REG(hw, E1000_IMIR(i), imir);
3616         E1000_WRITE_REG(hw, E1000_TTQF(i), ttqf);
3617         E1000_WRITE_REG(hw, E1000_IMIREXT(i), imir_ext);
3618         return 0;
3619 }
3620
3621 /*
3622  * igb_remove_2tuple_filter - remove a 2tuple filter
3623  *
3624  * @param
3625  * dev: Pointer to struct rte_eth_dev.
3626  * ntuple_filter: ponter to the filter that will be removed.
3627  *
3628  * @return
3629  *    - On success, zero.
3630  *    - On failure, a negative value.
3631  */
3632 static int
3633 igb_remove_2tuple_filter(struct rte_eth_dev *dev,
3634                         struct rte_eth_ntuple_filter *ntuple_filter)
3635 {
3636         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3637         struct e1000_filter_info *filter_info =
3638                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3639         struct e1000_2tuple_filter_info filter_2tuple;
3640         struct e1000_2tuple_filter *filter;
3641         int ret;
3642
3643         memset(&filter_2tuple, 0, sizeof(struct e1000_2tuple_filter_info));
3644         ret = ntuple_filter_to_2tuple(ntuple_filter,
3645                                       &filter_2tuple);
3646         if (ret < 0)
3647                 return ret;
3648
3649         filter = igb_2tuple_filter_lookup(&filter_info->twotuple_list,
3650                                          &filter_2tuple);
3651         if (filter == NULL) {
3652                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
3653                 return -ENOENT;
3654         }
3655
3656         filter_info->twotuple_mask &= ~(1 << filter->index);
3657         TAILQ_REMOVE(&filter_info->twotuple_list, filter, entries);
3658         rte_free(filter);
3659
3660         E1000_WRITE_REG(hw, E1000_TTQF(filter->index), E1000_TTQF_DISABLE_MASK);
3661         E1000_WRITE_REG(hw, E1000_IMIR(filter->index), 0);
3662         E1000_WRITE_REG(hw, E1000_IMIREXT(filter->index), 0);
3663         return 0;
3664 }
3665
3666 static inline struct e1000_flex_filter *
3667 eth_igb_flex_filter_lookup(struct e1000_flex_filter_list *filter_list,
3668                         struct e1000_flex_filter_info *key)
3669 {
3670         struct e1000_flex_filter *it;
3671
3672         TAILQ_FOREACH(it, filter_list, entries) {
3673                 if (memcmp(key, &it->filter_info,
3674                         sizeof(struct e1000_flex_filter_info)) == 0)
3675                         return it;
3676         }
3677
3678         return NULL;
3679 }
3680
3681 static int
3682 eth_igb_add_del_flex_filter(struct rte_eth_dev *dev,
3683                         struct rte_eth_flex_filter *filter,
3684                         bool add)
3685 {
3686         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3687         struct e1000_filter_info *filter_info =
3688                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3689         struct e1000_flex_filter *flex_filter, *it;
3690         uint32_t wufc, queueing, mask;
3691         uint32_t reg_off;
3692         uint8_t shift, i, j = 0;
3693
3694         flex_filter = rte_zmalloc("e1000_flex_filter",
3695                         sizeof(struct e1000_flex_filter), 0);
3696         if (flex_filter == NULL)
3697                 return -ENOMEM;
3698
3699         flex_filter->filter_info.len = filter->len;
3700         flex_filter->filter_info.priority = filter->priority;
3701         memcpy(flex_filter->filter_info.dwords, filter->bytes, filter->len);
3702         for (i = 0; i < RTE_ALIGN(filter->len, CHAR_BIT) / CHAR_BIT; i++) {
3703                 mask = 0;
3704                 /* reverse bits in flex filter's mask*/
3705                 for (shift = 0; shift < CHAR_BIT; shift++) {
3706                         if (filter->mask[i] & (0x01 << shift))
3707                                 mask |= (0x80 >> shift);
3708                 }
3709                 flex_filter->filter_info.mask[i] = mask;
3710         }
3711
3712         wufc = E1000_READ_REG(hw, E1000_WUFC);
3713         if (flex_filter->index < E1000_MAX_FHFT)
3714                 reg_off = E1000_FHFT(flex_filter->index);
3715         else
3716                 reg_off = E1000_FHFT_EXT(flex_filter->index - E1000_MAX_FHFT);
3717
3718         if (add) {
3719                 if (eth_igb_flex_filter_lookup(&filter_info->flex_list,
3720                                 &flex_filter->filter_info) != NULL) {
3721                         PMD_DRV_LOG(ERR, "filter exists.");
3722                         rte_free(flex_filter);
3723                         return -EEXIST;
3724                 }
3725                 flex_filter->queue = filter->queue;
3726                 /*
3727                  * look for an unused flex filter index
3728                  * and insert the filter into the list.
3729                  */
3730                 for (i = 0; i < E1000_MAX_FLEX_FILTERS; i++) {
3731                         if (!(filter_info->flex_mask & (1 << i))) {
3732                                 filter_info->flex_mask |= 1 << i;
3733                                 flex_filter->index = i;
3734                                 TAILQ_INSERT_TAIL(&filter_info->flex_list,
3735                                         flex_filter,
3736                                         entries);
3737                                 break;
3738                         }
3739                 }
3740                 if (i >= E1000_MAX_FLEX_FILTERS) {
3741                         PMD_DRV_LOG(ERR, "flex filters are full.");
3742                         rte_free(flex_filter);
3743                         return -ENOSYS;
3744                 }
3745
3746                 E1000_WRITE_REG(hw, E1000_WUFC, wufc | E1000_WUFC_FLEX_HQ |
3747                                 (E1000_WUFC_FLX0 << flex_filter->index));
3748                 queueing = filter->len |
3749                         (filter->queue << E1000_FHFT_QUEUEING_QUEUE_SHIFT) |
3750                         (filter->priority << E1000_FHFT_QUEUEING_PRIO_SHIFT);
3751                 E1000_WRITE_REG(hw, reg_off + E1000_FHFT_QUEUEING_OFFSET,
3752                                 queueing);
3753                 for (i = 0; i < E1000_FLEX_FILTERS_MASK_SIZE; i++) {
3754                         E1000_WRITE_REG(hw, reg_off,
3755                                         flex_filter->filter_info.dwords[j]);
3756                         reg_off += sizeof(uint32_t);
3757                         E1000_WRITE_REG(hw, reg_off,
3758                                         flex_filter->filter_info.dwords[++j]);
3759                         reg_off += sizeof(uint32_t);
3760                         E1000_WRITE_REG(hw, reg_off,
3761                                 (uint32_t)flex_filter->filter_info.mask[i]);
3762                         reg_off += sizeof(uint32_t) * 2;
3763                         ++j;
3764                 }
3765         } else {
3766                 it = eth_igb_flex_filter_lookup(&filter_info->flex_list,
3767                                 &flex_filter->filter_info);
3768                 if (it == NULL) {
3769                         PMD_DRV_LOG(ERR, "filter doesn't exist.");
3770                         rte_free(flex_filter);
3771                         return -ENOENT;
3772                 }
3773
3774                 for (i = 0; i < E1000_FHFT_SIZE_IN_DWD; i++)
3775                         E1000_WRITE_REG(hw, reg_off + i * sizeof(uint32_t), 0);
3776                 E1000_WRITE_REG(hw, E1000_WUFC, wufc &
3777                         (~(E1000_WUFC_FLX0 << it->index)));
3778
3779                 filter_info->flex_mask &= ~(1 << it->index);
3780                 TAILQ_REMOVE(&filter_info->flex_list, it, entries);
3781                 rte_free(it);
3782                 rte_free(flex_filter);
3783         }
3784
3785         return 0;
3786 }
3787
3788 static int
3789 eth_igb_get_flex_filter(struct rte_eth_dev *dev,
3790                         struct rte_eth_flex_filter *filter)
3791 {
3792         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3793         struct e1000_filter_info *filter_info =
3794                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3795         struct e1000_flex_filter flex_filter, *it;
3796         uint32_t wufc, queueing, wufc_en = 0;
3797
3798         memset(&flex_filter, 0, sizeof(struct e1000_flex_filter));
3799         flex_filter.filter_info.len = filter->len;
3800         flex_filter.filter_info.priority = filter->priority;
3801         memcpy(flex_filter.filter_info.dwords, filter->bytes, filter->len);
3802         memcpy(flex_filter.filter_info.mask, filter->mask,
3803                         RTE_ALIGN(filter->len, sizeof(char)) / sizeof(char));
3804
3805         it = eth_igb_flex_filter_lookup(&filter_info->flex_list,
3806                                 &flex_filter.filter_info);
3807         if (it == NULL) {
3808                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
3809                 return -ENOENT;
3810         }
3811
3812         wufc = E1000_READ_REG(hw, E1000_WUFC);
3813         wufc_en = E1000_WUFC_FLEX_HQ | (E1000_WUFC_FLX0 << it->index);
3814
3815         if ((wufc & wufc_en) == wufc_en) {
3816                 uint32_t reg_off = 0;
3817                 if (it->index < E1000_MAX_FHFT)
3818                         reg_off = E1000_FHFT(it->index);
3819                 else
3820                         reg_off = E1000_FHFT_EXT(it->index - E1000_MAX_FHFT);
3821
3822                 queueing = E1000_READ_REG(hw,
3823                                 reg_off + E1000_FHFT_QUEUEING_OFFSET);
3824                 filter->len = queueing & E1000_FHFT_QUEUEING_LEN;
3825                 filter->priority = (queueing & E1000_FHFT_QUEUEING_PRIO) >>
3826                         E1000_FHFT_QUEUEING_PRIO_SHIFT;
3827                 filter->queue = (queueing & E1000_FHFT_QUEUEING_QUEUE) >>
3828                         E1000_FHFT_QUEUEING_QUEUE_SHIFT;
3829                 return 0;
3830         }
3831         return -ENOENT;
3832 }
3833
3834 static int
3835 eth_igb_flex_filter_handle(struct rte_eth_dev *dev,
3836                         enum rte_filter_op filter_op,
3837                         void *arg)
3838 {
3839         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3840         struct rte_eth_flex_filter *filter;
3841         int ret = 0;
3842
3843         MAC_TYPE_FILTER_SUP_EXT(hw->mac.type);
3844
3845         if (filter_op == RTE_ETH_FILTER_NOP)
3846                 return ret;
3847
3848         if (arg == NULL) {
3849                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
3850                             filter_op);
3851                 return -EINVAL;
3852         }
3853
3854         filter = (struct rte_eth_flex_filter *)arg;
3855         if (filter->len == 0 || filter->len > E1000_MAX_FLEX_FILTER_LEN
3856             || filter->len % sizeof(uint64_t) != 0) {
3857                 PMD_DRV_LOG(ERR, "filter's length is out of range");
3858                 return -EINVAL;
3859         }
3860         if (filter->priority > E1000_MAX_FLEX_FILTER_PRI) {
3861                 PMD_DRV_LOG(ERR, "filter's priority is out of range");
3862                 return -EINVAL;
3863         }
3864
3865         switch (filter_op) {
3866         case RTE_ETH_FILTER_ADD:
3867                 ret = eth_igb_add_del_flex_filter(dev, filter, TRUE);
3868                 break;
3869         case RTE_ETH_FILTER_DELETE:
3870                 ret = eth_igb_add_del_flex_filter(dev, filter, FALSE);
3871                 break;
3872         case RTE_ETH_FILTER_GET:
3873                 ret = eth_igb_get_flex_filter(dev, filter);
3874                 break;
3875         default:
3876                 PMD_DRV_LOG(ERR, "unsupported operation %u", filter_op);
3877                 ret = -EINVAL;
3878                 break;
3879         }
3880
3881         return ret;
3882 }
3883
3884 /* translate elements in struct rte_eth_ntuple_filter to struct e1000_5tuple_filter_info*/
3885 static inline int
3886 ntuple_filter_to_5tuple_82576(struct rte_eth_ntuple_filter *filter,
3887                         struct e1000_5tuple_filter_info *filter_info)
3888 {
3889         if (filter->queue >= IGB_MAX_RX_QUEUE_NUM_82576)
3890                 return -EINVAL;
3891         if (filter->priority > E1000_2TUPLE_MAX_PRI)
3892                 return -EINVAL;  /* filter index is out of range. */
3893         if (filter->tcp_flags > TCP_FLAG_ALL)
3894                 return -EINVAL;  /* flags is invalid. */
3895
3896         switch (filter->dst_ip_mask) {
3897         case UINT32_MAX:
3898                 filter_info->dst_ip_mask = 0;
3899                 filter_info->dst_ip = filter->dst_ip;
3900                 break;
3901         case 0:
3902                 filter_info->dst_ip_mask = 1;
3903                 break;
3904         default:
3905                 PMD_DRV_LOG(ERR, "invalid dst_ip mask.");
3906                 return -EINVAL;
3907         }
3908
3909         switch (filter->src_ip_mask) {
3910         case UINT32_MAX:
3911                 filter_info->src_ip_mask = 0;
3912                 filter_info->src_ip = filter->src_ip;
3913                 break;
3914         case 0:
3915                 filter_info->src_ip_mask = 1;
3916                 break;
3917         default:
3918                 PMD_DRV_LOG(ERR, "invalid src_ip mask.");
3919                 return -EINVAL;
3920         }
3921
3922         switch (filter->dst_port_mask) {
3923         case UINT16_MAX:
3924                 filter_info->dst_port_mask = 0;
3925                 filter_info->dst_port = filter->dst_port;
3926                 break;
3927         case 0:
3928                 filter_info->dst_port_mask = 1;
3929                 break;
3930         default:
3931                 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
3932                 return -EINVAL;
3933         }
3934
3935         switch (filter->src_port_mask) {
3936         case UINT16_MAX:
3937                 filter_info->src_port_mask = 0;
3938                 filter_info->src_port = filter->src_port;
3939                 break;
3940         case 0:
3941                 filter_info->src_port_mask = 1;
3942                 break;
3943         default:
3944                 PMD_DRV_LOG(ERR, "invalid src_port mask.");
3945                 return -EINVAL;
3946         }
3947
3948         switch (filter->proto_mask) {
3949         case UINT8_MAX:
3950                 filter_info->proto_mask = 0;
3951                 filter_info->proto = filter->proto;
3952                 break;
3953         case 0:
3954                 filter_info->proto_mask = 1;
3955                 break;
3956         default:
3957                 PMD_DRV_LOG(ERR, "invalid protocol mask.");
3958                 return -EINVAL;
3959         }
3960
3961         filter_info->priority = (uint8_t)filter->priority;
3962         if (filter->flags & RTE_NTUPLE_FLAGS_TCP_FLAG)
3963                 filter_info->tcp_flags = filter->tcp_flags;
3964         else
3965                 filter_info->tcp_flags = 0;
3966
3967         return 0;
3968 }
3969
3970 static inline struct e1000_5tuple_filter *
3971 igb_5tuple_filter_lookup_82576(struct e1000_5tuple_filter_list *filter_list,
3972                         struct e1000_5tuple_filter_info *key)
3973 {
3974         struct e1000_5tuple_filter *it;
3975
3976         TAILQ_FOREACH(it, filter_list, entries) {
3977                 if (memcmp(key, &it->filter_info,
3978                         sizeof(struct e1000_5tuple_filter_info)) == 0) {
3979                         return it;
3980                 }
3981         }
3982         return NULL;
3983 }
3984
3985 /*
3986  * igb_add_5tuple_filter_82576 - add a 5tuple filter
3987  *
3988  * @param
3989  * dev: Pointer to struct rte_eth_dev.
3990  * ntuple_filter: ponter to the filter that will be added.
3991  *
3992  * @return
3993  *    - On success, zero.
3994  *    - On failure, a negative value.
3995  */
3996 static int
3997 igb_add_5tuple_filter_82576(struct rte_eth_dev *dev,
3998                         struct rte_eth_ntuple_filter *ntuple_filter)
3999 {
4000         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4001         struct e1000_filter_info *filter_info =
4002                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4003         struct e1000_5tuple_filter *filter;
4004         uint32_t ftqf = E1000_FTQF_VF_BP | E1000_FTQF_MASK;
4005         uint32_t spqf, imir, imir_ext = E1000_IMIREXT_SIZE_BP;
4006         uint8_t i;
4007         int ret;
4008
4009         filter = rte_zmalloc("e1000_5tuple_filter",
4010                         sizeof(struct e1000_5tuple_filter), 0);
4011         if (filter == NULL)
4012                 return -ENOMEM;
4013
4014         ret = ntuple_filter_to_5tuple_82576(ntuple_filter,
4015                                             &filter->filter_info);
4016         if (ret < 0) {
4017                 rte_free(filter);
4018                 return ret;
4019         }
4020
4021         if (igb_5tuple_filter_lookup_82576(&filter_info->fivetuple_list,
4022                                          &filter->filter_info) != NULL) {
4023                 PMD_DRV_LOG(ERR, "filter exists.");
4024                 rte_free(filter);
4025                 return -EEXIST;
4026         }
4027         filter->queue = ntuple_filter->queue;
4028
4029         /*
4030          * look for an unused 5tuple filter index,
4031          * and insert the filter to list.
4032          */
4033         for (i = 0; i < E1000_MAX_FTQF_FILTERS; i++) {
4034                 if (!(filter_info->fivetuple_mask & (1 << i))) {
4035                         filter_info->fivetuple_mask |= 1 << i;
4036                         filter->index = i;
4037                         TAILQ_INSERT_TAIL(&filter_info->fivetuple_list,
4038                                           filter,
4039                                           entries);
4040                         break;
4041                 }
4042         }
4043         if (i >= E1000_MAX_FTQF_FILTERS) {
4044                 PMD_DRV_LOG(ERR, "5tuple filters are full.");
4045                 rte_free(filter);
4046                 return -ENOSYS;
4047         }
4048
4049         ftqf |= filter->filter_info.proto & E1000_FTQF_PROTOCOL_MASK;
4050         if (filter->filter_info.src_ip_mask == 0) /* 0b means compare. */
4051                 ftqf &= ~E1000_FTQF_MASK_SOURCE_ADDR_BP;
4052         if (filter->filter_info.dst_ip_mask == 0)
4053                 ftqf &= ~E1000_FTQF_MASK_DEST_ADDR_BP;
4054         if (filter->filter_info.src_port_mask == 0)
4055                 ftqf &= ~E1000_FTQF_MASK_SOURCE_PORT_BP;
4056         if (filter->filter_info.proto_mask == 0)
4057                 ftqf &= ~E1000_FTQF_MASK_PROTO_BP;
4058         ftqf |= (filter->queue << E1000_FTQF_QUEUE_SHIFT) &
4059                 E1000_FTQF_QUEUE_MASK;
4060         ftqf |= E1000_FTQF_QUEUE_ENABLE;
4061         E1000_WRITE_REG(hw, E1000_FTQF(i), ftqf);
4062         E1000_WRITE_REG(hw, E1000_DAQF(i), filter->filter_info.dst_ip);
4063         E1000_WRITE_REG(hw, E1000_SAQF(i), filter->filter_info.src_ip);
4064
4065         spqf = filter->filter_info.src_port & E1000_SPQF_SRCPORT;
4066         E1000_WRITE_REG(hw, E1000_SPQF(i), spqf);
4067
4068         imir = (uint32_t)(filter->filter_info.dst_port & E1000_IMIR_DSTPORT);
4069         if (filter->filter_info.dst_port_mask == 1) /* 1b means not compare. */
4070                 imir |= E1000_IMIR_PORT_BP;
4071         else
4072                 imir &= ~E1000_IMIR_PORT_BP;
4073         imir |= filter->filter_info.priority << E1000_IMIR_PRIORITY_SHIFT;
4074
4075         /* tcp flags bits setting. */
4076         if (filter->filter_info.tcp_flags & TCP_FLAG_ALL) {
4077                 if (filter->filter_info.tcp_flags & TCP_URG_FLAG)
4078                         imir_ext |= E1000_IMIREXT_CTRL_URG;
4079                 if (filter->filter_info.tcp_flags & TCP_ACK_FLAG)
4080                         imir_ext |= E1000_IMIREXT_CTRL_ACK;
4081                 if (filter->filter_info.tcp_flags & TCP_PSH_FLAG)
4082                         imir_ext |= E1000_IMIREXT_CTRL_PSH;
4083                 if (filter->filter_info.tcp_flags & TCP_RST_FLAG)
4084                         imir_ext |= E1000_IMIREXT_CTRL_RST;
4085                 if (filter->filter_info.tcp_flags & TCP_SYN_FLAG)
4086                         imir_ext |= E1000_IMIREXT_CTRL_SYN;
4087                 if (filter->filter_info.tcp_flags & TCP_FIN_FLAG)
4088                         imir_ext |= E1000_IMIREXT_CTRL_FIN;
4089         } else
4090                 imir_ext |= E1000_IMIREXT_CTRL_BP;
4091         E1000_WRITE_REG(hw, E1000_IMIR(i), imir);
4092         E1000_WRITE_REG(hw, E1000_IMIREXT(i), imir_ext);
4093         return 0;
4094 }
4095
4096 /*
4097  * igb_remove_5tuple_filter_82576 - remove a 5tuple filter
4098  *
4099  * @param
4100  * dev: Pointer to struct rte_eth_dev.
4101  * ntuple_filter: ponter to the filter that will be removed.
4102  *
4103  * @return
4104  *    - On success, zero.
4105  *    - On failure, a negative value.
4106  */
4107 static int
4108 igb_remove_5tuple_filter_82576(struct rte_eth_dev *dev,
4109                                 struct rte_eth_ntuple_filter *ntuple_filter)
4110 {
4111         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4112         struct e1000_filter_info *filter_info =
4113                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4114         struct e1000_5tuple_filter_info filter_5tuple;
4115         struct e1000_5tuple_filter *filter;
4116         int ret;
4117
4118         memset(&filter_5tuple, 0, sizeof(struct e1000_5tuple_filter_info));
4119         ret = ntuple_filter_to_5tuple_82576(ntuple_filter,
4120                                             &filter_5tuple);
4121         if (ret < 0)
4122                 return ret;
4123
4124         filter = igb_5tuple_filter_lookup_82576(&filter_info->fivetuple_list,
4125                                          &filter_5tuple);
4126         if (filter == NULL) {
4127                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
4128                 return -ENOENT;
4129         }
4130
4131         filter_info->fivetuple_mask &= ~(1 << filter->index);
4132         TAILQ_REMOVE(&filter_info->fivetuple_list, filter, entries);
4133         rte_free(filter);
4134
4135         E1000_WRITE_REG(hw, E1000_FTQF(filter->index),
4136                         E1000_FTQF_VF_BP | E1000_FTQF_MASK);
4137         E1000_WRITE_REG(hw, E1000_DAQF(filter->index), 0);
4138         E1000_WRITE_REG(hw, E1000_SAQF(filter->index), 0);
4139         E1000_WRITE_REG(hw, E1000_SPQF(filter->index), 0);
4140         E1000_WRITE_REG(hw, E1000_IMIR(filter->index), 0);
4141         E1000_WRITE_REG(hw, E1000_IMIREXT(filter->index), 0);
4142         return 0;
4143 }
4144
4145 static int
4146 eth_igb_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
4147 {
4148         uint32_t rctl;
4149         struct e1000_hw *hw;
4150         struct rte_eth_dev_info dev_info;
4151         uint32_t frame_size = mtu + (ETHER_HDR_LEN + ETHER_CRC_LEN +
4152                                      VLAN_TAG_SIZE);
4153
4154         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4155
4156 #ifdef RTE_LIBRTE_82571_SUPPORT
4157         /* XXX: not bigger than max_rx_pktlen */
4158         if (hw->mac.type == e1000_82571)
4159                 return -ENOTSUP;
4160 #endif
4161         eth_igb_infos_get(dev, &dev_info);
4162
4163         /* check that mtu is within the allowed range */
4164         if ((mtu < ETHER_MIN_MTU) ||
4165             (frame_size > dev_info.max_rx_pktlen))
4166                 return -EINVAL;
4167
4168         /* refuse mtu that requires the support of scattered packets when this
4169          * feature has not been enabled before. */
4170         if (!dev->data->scattered_rx &&
4171             frame_size > dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)
4172                 return -EINVAL;
4173
4174         rctl = E1000_READ_REG(hw, E1000_RCTL);
4175
4176         /* switch to jumbo mode if needed */
4177         if (frame_size > ETHER_MAX_LEN) {
4178                 dev->data->dev_conf.rxmode.jumbo_frame = 1;
4179                 rctl |= E1000_RCTL_LPE;
4180         } else {
4181                 dev->data->dev_conf.rxmode.jumbo_frame = 0;
4182                 rctl &= ~E1000_RCTL_LPE;
4183         }
4184         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
4185
4186         /* update max frame size */
4187         dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
4188
4189         E1000_WRITE_REG(hw, E1000_RLPML,
4190                         dev->data->dev_conf.rxmode.max_rx_pkt_len);
4191
4192         return 0;
4193 }
4194
4195 /*
4196  * igb_add_del_ntuple_filter - add or delete a ntuple filter
4197  *
4198  * @param
4199  * dev: Pointer to struct rte_eth_dev.
4200  * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
4201  * add: if true, add filter, if false, remove filter
4202  *
4203  * @return
4204  *    - On success, zero.
4205  *    - On failure, a negative value.
4206  */
4207 static int
4208 igb_add_del_ntuple_filter(struct rte_eth_dev *dev,
4209                         struct rte_eth_ntuple_filter *ntuple_filter,
4210                         bool add)
4211 {
4212         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4213         int ret;
4214
4215         switch (ntuple_filter->flags) {
4216         case RTE_5TUPLE_FLAGS:
4217         case (RTE_5TUPLE_FLAGS | RTE_NTUPLE_FLAGS_TCP_FLAG):
4218                 if (hw->mac.type != e1000_82576)
4219                         return -ENOTSUP;
4220                 if (add)
4221                         ret = igb_add_5tuple_filter_82576(dev,
4222                                                           ntuple_filter);
4223                 else
4224                         ret = igb_remove_5tuple_filter_82576(dev,
4225                                                              ntuple_filter);
4226                 break;
4227         case RTE_2TUPLE_FLAGS:
4228         case (RTE_2TUPLE_FLAGS | RTE_NTUPLE_FLAGS_TCP_FLAG):
4229                 if (hw->mac.type != e1000_82580 && hw->mac.type != e1000_i350)
4230                         return -ENOTSUP;
4231                 if (add)
4232                         ret = igb_add_2tuple_filter(dev, ntuple_filter);
4233                 else
4234                         ret = igb_remove_2tuple_filter(dev, ntuple_filter);
4235                 break;
4236         default:
4237                 ret = -EINVAL;
4238                 break;
4239         }
4240
4241         return ret;
4242 }
4243
4244 /*
4245  * igb_get_ntuple_filter - get a ntuple filter
4246  *
4247  * @param
4248  * dev: Pointer to struct rte_eth_dev.
4249  * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
4250  *
4251  * @return
4252  *    - On success, zero.
4253  *    - On failure, a negative value.
4254  */
4255 static int
4256 igb_get_ntuple_filter(struct rte_eth_dev *dev,
4257                         struct rte_eth_ntuple_filter *ntuple_filter)
4258 {
4259         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4260         struct e1000_filter_info *filter_info =
4261                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4262         struct e1000_5tuple_filter_info filter_5tuple;
4263         struct e1000_2tuple_filter_info filter_2tuple;
4264         struct e1000_5tuple_filter *p_5tuple_filter;
4265         struct e1000_2tuple_filter *p_2tuple_filter;
4266         int ret;
4267
4268         switch (ntuple_filter->flags) {
4269         case RTE_5TUPLE_FLAGS:
4270         case (RTE_5TUPLE_FLAGS | RTE_NTUPLE_FLAGS_TCP_FLAG):
4271                 if (hw->mac.type != e1000_82576)
4272                         return -ENOTSUP;
4273                 memset(&filter_5tuple,
4274                         0,
4275                         sizeof(struct e1000_5tuple_filter_info));
4276                 ret = ntuple_filter_to_5tuple_82576(ntuple_filter,
4277                                                     &filter_5tuple);
4278                 if (ret < 0)
4279                         return ret;
4280                 p_5tuple_filter = igb_5tuple_filter_lookup_82576(
4281                                         &filter_info->fivetuple_list,
4282                                         &filter_5tuple);
4283                 if (p_5tuple_filter == NULL) {
4284                         PMD_DRV_LOG(ERR, "filter doesn't exist.");
4285                         return -ENOENT;
4286                 }
4287                 ntuple_filter->queue = p_5tuple_filter->queue;
4288                 break;
4289         case RTE_2TUPLE_FLAGS:
4290         case (RTE_2TUPLE_FLAGS | RTE_NTUPLE_FLAGS_TCP_FLAG):
4291                 if (hw->mac.type != e1000_82580 && hw->mac.type != e1000_i350)
4292                         return -ENOTSUP;
4293                 memset(&filter_2tuple,
4294                         0,
4295                         sizeof(struct e1000_2tuple_filter_info));
4296                 ret = ntuple_filter_to_2tuple(ntuple_filter, &filter_2tuple);
4297                 if (ret < 0)
4298                         return ret;
4299                 p_2tuple_filter = igb_2tuple_filter_lookup(
4300                                         &filter_info->twotuple_list,
4301                                         &filter_2tuple);
4302                 if (p_2tuple_filter == NULL) {
4303                         PMD_DRV_LOG(ERR, "filter doesn't exist.");
4304                         return -ENOENT;
4305                 }
4306                 ntuple_filter->queue = p_2tuple_filter->queue;
4307                 break;
4308         default:
4309                 ret = -EINVAL;
4310                 break;
4311         }
4312
4313         return 0;
4314 }
4315
4316 /*
4317  * igb_ntuple_filter_handle - Handle operations for ntuple filter.
4318  * @dev: pointer to rte_eth_dev structure
4319  * @filter_op:operation will be taken.
4320  * @arg: a pointer to specific structure corresponding to the filter_op
4321  */
4322 static int
4323 igb_ntuple_filter_handle(struct rte_eth_dev *dev,
4324                                 enum rte_filter_op filter_op,
4325                                 void *arg)
4326 {
4327         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4328         int ret;
4329
4330         MAC_TYPE_FILTER_SUP(hw->mac.type);
4331
4332         if (filter_op == RTE_ETH_FILTER_NOP)
4333                 return 0;
4334
4335         if (arg == NULL) {
4336                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
4337                             filter_op);
4338                 return -EINVAL;
4339         }
4340
4341         switch (filter_op) {
4342         case RTE_ETH_FILTER_ADD:
4343                 ret = igb_add_del_ntuple_filter(dev,
4344                         (struct rte_eth_ntuple_filter *)arg,
4345                         TRUE);
4346                 break;
4347         case RTE_ETH_FILTER_DELETE:
4348                 ret = igb_add_del_ntuple_filter(dev,
4349                         (struct rte_eth_ntuple_filter *)arg,
4350                         FALSE);
4351                 break;
4352         case RTE_ETH_FILTER_GET:
4353                 ret = igb_get_ntuple_filter(dev,
4354                         (struct rte_eth_ntuple_filter *)arg);
4355                 break;
4356         default:
4357                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
4358                 ret = -EINVAL;
4359                 break;
4360         }
4361         return ret;
4362 }
4363
4364 static inline int
4365 igb_ethertype_filter_lookup(struct e1000_filter_info *filter_info,
4366                         uint16_t ethertype)
4367 {
4368         int i;
4369
4370         for (i = 0; i < E1000_MAX_ETQF_FILTERS; i++) {
4371                 if (filter_info->ethertype_filters[i] == ethertype &&
4372                     (filter_info->ethertype_mask & (1 << i)))
4373                         return i;
4374         }
4375         return -1;
4376 }
4377
4378 static inline int
4379 igb_ethertype_filter_insert(struct e1000_filter_info *filter_info,
4380                         uint16_t ethertype)
4381 {
4382         int i;
4383
4384         for (i = 0; i < E1000_MAX_ETQF_FILTERS; i++) {
4385                 if (!(filter_info->ethertype_mask & (1 << i))) {
4386                         filter_info->ethertype_mask |= 1 << i;
4387                         filter_info->ethertype_filters[i] = ethertype;
4388                         return i;
4389                 }
4390         }
4391         return -1;
4392 }
4393
4394 static inline int
4395 igb_ethertype_filter_remove(struct e1000_filter_info *filter_info,
4396                         uint8_t idx)
4397 {
4398         if (idx >= E1000_MAX_ETQF_FILTERS)
4399                 return -1;
4400         filter_info->ethertype_mask &= ~(1 << idx);
4401         filter_info->ethertype_filters[idx] = 0;
4402         return idx;
4403 }
4404
4405
4406 static int
4407 igb_add_del_ethertype_filter(struct rte_eth_dev *dev,
4408                         struct rte_eth_ethertype_filter *filter,
4409                         bool add)
4410 {
4411         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4412         struct e1000_filter_info *filter_info =
4413                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4414         uint32_t etqf = 0;
4415         int ret;
4416
4417         if (filter->ether_type == ETHER_TYPE_IPv4 ||
4418                 filter->ether_type == ETHER_TYPE_IPv6) {
4419                 PMD_DRV_LOG(ERR, "unsupported ether_type(0x%04x) in"
4420                         " ethertype filter.", filter->ether_type);
4421                 return -EINVAL;
4422         }
4423
4424         if (filter->flags & RTE_ETHTYPE_FLAGS_MAC) {
4425                 PMD_DRV_LOG(ERR, "mac compare is unsupported.");
4426                 return -EINVAL;
4427         }
4428         if (filter->flags & RTE_ETHTYPE_FLAGS_DROP) {
4429                 PMD_DRV_LOG(ERR, "drop option is unsupported.");
4430                 return -EINVAL;
4431         }
4432
4433         ret = igb_ethertype_filter_lookup(filter_info, filter->ether_type);
4434         if (ret >= 0 && add) {
4435                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter exists.",
4436                             filter->ether_type);
4437                 return -EEXIST;
4438         }
4439         if (ret < 0 && !add) {
4440                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
4441                             filter->ether_type);
4442                 return -ENOENT;
4443         }
4444
4445         if (add) {
4446                 ret = igb_ethertype_filter_insert(filter_info,
4447                         filter->ether_type);
4448                 if (ret < 0) {
4449                         PMD_DRV_LOG(ERR, "ethertype filters are full.");
4450                         return -ENOSYS;
4451                 }
4452
4453                 etqf |= E1000_ETQF_FILTER_ENABLE | E1000_ETQF_QUEUE_ENABLE;
4454                 etqf |= (uint32_t)(filter->ether_type & E1000_ETQF_ETHERTYPE);
4455                 etqf |= filter->queue << E1000_ETQF_QUEUE_SHIFT;
4456         } else {
4457                 ret = igb_ethertype_filter_remove(filter_info, (uint8_t)ret);
4458                 if (ret < 0)
4459                         return -ENOSYS;
4460         }
4461         E1000_WRITE_REG(hw, E1000_ETQF(ret), etqf);
4462         E1000_WRITE_FLUSH(hw);
4463
4464         return 0;
4465 }
4466
4467 static int
4468 igb_get_ethertype_filter(struct rte_eth_dev *dev,
4469                         struct rte_eth_ethertype_filter *filter)
4470 {
4471         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4472         struct e1000_filter_info *filter_info =
4473                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4474         uint32_t etqf;
4475         int ret;
4476
4477         ret = igb_ethertype_filter_lookup(filter_info, filter->ether_type);
4478         if (ret < 0) {
4479                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
4480                             filter->ether_type);
4481                 return -ENOENT;
4482         }
4483
4484         etqf = E1000_READ_REG(hw, E1000_ETQF(ret));
4485         if (etqf & E1000_ETQF_FILTER_ENABLE) {
4486                 filter->ether_type = etqf & E1000_ETQF_ETHERTYPE;
4487                 filter->flags = 0;
4488                 filter->queue = (etqf & E1000_ETQF_QUEUE) >>
4489                                 E1000_ETQF_QUEUE_SHIFT;
4490                 return 0;
4491         }
4492
4493         return -ENOENT;
4494 }
4495
4496 /*
4497  * igb_ethertype_filter_handle - Handle operations for ethertype filter.
4498  * @dev: pointer to rte_eth_dev structure
4499  * @filter_op:operation will be taken.
4500  * @arg: a pointer to specific structure corresponding to the filter_op
4501  */
4502 static int
4503 igb_ethertype_filter_handle(struct rte_eth_dev *dev,
4504                                 enum rte_filter_op filter_op,
4505                                 void *arg)
4506 {
4507         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4508         int ret;
4509
4510         MAC_TYPE_FILTER_SUP(hw->mac.type);
4511
4512         if (filter_op == RTE_ETH_FILTER_NOP)
4513                 return 0;
4514
4515         if (arg == NULL) {
4516                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
4517                             filter_op);
4518                 return -EINVAL;
4519         }
4520
4521         switch (filter_op) {
4522         case RTE_ETH_FILTER_ADD:
4523                 ret = igb_add_del_ethertype_filter(dev,
4524                         (struct rte_eth_ethertype_filter *)arg,
4525                         TRUE);
4526                 break;
4527         case RTE_ETH_FILTER_DELETE:
4528                 ret = igb_add_del_ethertype_filter(dev,
4529                         (struct rte_eth_ethertype_filter *)arg,
4530                         FALSE);
4531                 break;
4532         case RTE_ETH_FILTER_GET:
4533                 ret = igb_get_ethertype_filter(dev,
4534                         (struct rte_eth_ethertype_filter *)arg);
4535                 break;
4536         default:
4537                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
4538                 ret = -EINVAL;
4539                 break;
4540         }
4541         return ret;
4542 }
4543
4544 static int
4545 eth_igb_filter_ctrl(struct rte_eth_dev *dev,
4546                      enum rte_filter_type filter_type,
4547                      enum rte_filter_op filter_op,
4548                      void *arg)
4549 {
4550         int ret = -EINVAL;
4551
4552         switch (filter_type) {
4553         case RTE_ETH_FILTER_NTUPLE:
4554                 ret = igb_ntuple_filter_handle(dev, filter_op, arg);
4555                 break;
4556         case RTE_ETH_FILTER_ETHERTYPE:
4557                 ret = igb_ethertype_filter_handle(dev, filter_op, arg);
4558                 break;
4559         case RTE_ETH_FILTER_SYN:
4560                 ret = eth_igb_syn_filter_handle(dev, filter_op, arg);
4561                 break;
4562         case RTE_ETH_FILTER_FLEXIBLE:
4563                 ret = eth_igb_flex_filter_handle(dev, filter_op, arg);
4564                 break;
4565         default:
4566                 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
4567                                                         filter_type);
4568                 break;
4569         }
4570
4571         return ret;
4572 }
4573
4574 static int
4575 eth_igb_set_mc_addr_list(struct rte_eth_dev *dev,
4576                          struct ether_addr *mc_addr_set,
4577                          uint32_t nb_mc_addr)
4578 {
4579         struct e1000_hw *hw;
4580
4581         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4582         e1000_update_mc_addr_list(hw, (u8 *)mc_addr_set, nb_mc_addr);
4583         return 0;
4584 }
4585
4586 static uint64_t
4587 igb_read_systime_cyclecounter(struct rte_eth_dev *dev)
4588 {
4589         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4590         uint64_t systime_cycles;
4591
4592         switch (hw->mac.type) {
4593         case e1000_i210:
4594         case e1000_i211:
4595                 /*
4596                  * Need to read System Time Residue Register to be able
4597                  * to read the other two registers.
4598                  */
4599                 E1000_READ_REG(hw, E1000_SYSTIMR);
4600                 /* SYSTIMEL stores ns and SYSTIMEH stores seconds. */
4601                 systime_cycles = (uint64_t)E1000_READ_REG(hw, E1000_SYSTIML);
4602                 systime_cycles += (uint64_t)E1000_READ_REG(hw, E1000_SYSTIMH)
4603                                 * NSEC_PER_SEC;
4604                 break;
4605         case e1000_82580:
4606         case e1000_i350:
4607         case e1000_i354:
4608                 /*
4609                  * Need to read System Time Residue Register to be able
4610                  * to read the other two registers.
4611                  */
4612                 E1000_READ_REG(hw, E1000_SYSTIMR);
4613                 systime_cycles = (uint64_t)E1000_READ_REG(hw, E1000_SYSTIML);
4614                 /* Only the 8 LSB are valid. */
4615                 systime_cycles |= (uint64_t)(E1000_READ_REG(hw, E1000_SYSTIMH)
4616                                 & 0xff) << 32;
4617                 break;
4618         default:
4619                 systime_cycles = (uint64_t)E1000_READ_REG(hw, E1000_SYSTIML);
4620                 systime_cycles |= (uint64_t)E1000_READ_REG(hw, E1000_SYSTIMH)
4621                                 << 32;
4622                 break;
4623         }
4624
4625         return systime_cycles;
4626 }
4627
4628 static uint64_t
4629 igb_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev)
4630 {
4631         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4632         uint64_t rx_tstamp_cycles;
4633
4634         switch (hw->mac.type) {
4635         case e1000_i210:
4636         case e1000_i211:
4637                 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
4638                 rx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_RXSTMPL);
4639                 rx_tstamp_cycles += (uint64_t)E1000_READ_REG(hw, E1000_RXSTMPH)
4640                                 * NSEC_PER_SEC;
4641                 break;
4642         case e1000_82580:
4643         case e1000_i350:
4644         case e1000_i354:
4645                 rx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_RXSTMPL);
4646                 /* Only the 8 LSB are valid. */
4647                 rx_tstamp_cycles |= (uint64_t)(E1000_READ_REG(hw, E1000_RXSTMPH)
4648                                 & 0xff) << 32;
4649                 break;
4650         default:
4651                 rx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_RXSTMPL);
4652                 rx_tstamp_cycles |= (uint64_t)E1000_READ_REG(hw, E1000_RXSTMPH)
4653                                 << 32;
4654                 break;
4655         }
4656
4657         return rx_tstamp_cycles;
4658 }
4659
4660 static uint64_t
4661 igb_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev)
4662 {
4663         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4664         uint64_t tx_tstamp_cycles;
4665
4666         switch (hw->mac.type) {
4667         case e1000_i210:
4668         case e1000_i211:
4669                 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
4670                 tx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_TXSTMPL);
4671                 tx_tstamp_cycles += (uint64_t)E1000_READ_REG(hw, E1000_TXSTMPH)
4672                                 * NSEC_PER_SEC;
4673                 break;
4674         case e1000_82580:
4675         case e1000_i350:
4676         case e1000_i354:
4677                 tx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_TXSTMPL);
4678                 /* Only the 8 LSB are valid. */
4679                 tx_tstamp_cycles |= (uint64_t)(E1000_READ_REG(hw, E1000_TXSTMPH)
4680                                 & 0xff) << 32;
4681                 break;
4682         default:
4683                 tx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_TXSTMPL);
4684                 tx_tstamp_cycles |= (uint64_t)E1000_READ_REG(hw, E1000_TXSTMPH)
4685                                 << 32;
4686                 break;
4687         }
4688
4689         return tx_tstamp_cycles;
4690 }
4691
4692 static void
4693 igb_start_timecounters(struct rte_eth_dev *dev)
4694 {
4695         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4696         struct e1000_adapter *adapter =
4697                 (struct e1000_adapter *)dev->data->dev_private;
4698         uint32_t incval = 1;
4699         uint32_t shift = 0;
4700         uint64_t mask = E1000_CYCLECOUNTER_MASK;
4701
4702         switch (hw->mac.type) {
4703         case e1000_82580:
4704         case e1000_i350:
4705         case e1000_i354:
4706                 /* 32 LSB bits + 8 MSB bits = 40 bits */
4707                 mask = (1ULL << 40) - 1;
4708                 /* fall-through */
4709         case e1000_i210:
4710         case e1000_i211:
4711                 /*
4712                  * Start incrementing the register
4713                  * used to timestamp PTP packets.
4714                  */
4715                 E1000_WRITE_REG(hw, E1000_TIMINCA, incval);
4716                 break;
4717         case e1000_82576:
4718                 incval = E1000_INCVALUE_82576;
4719                 shift = IGB_82576_TSYNC_SHIFT;
4720                 E1000_WRITE_REG(hw, E1000_TIMINCA,
4721                                 E1000_INCPERIOD_82576 | incval);
4722                 break;
4723         default:
4724                 /* Not supported */
4725                 return;
4726         }
4727
4728         memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter));
4729         memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
4730         memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
4731
4732         adapter->systime_tc.cc_mask = mask;
4733         adapter->systime_tc.cc_shift = shift;
4734         adapter->systime_tc.nsec_mask = (1ULL << shift) - 1;
4735
4736         adapter->rx_tstamp_tc.cc_mask = mask;
4737         adapter->rx_tstamp_tc.cc_shift = shift;
4738         adapter->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
4739
4740         adapter->tx_tstamp_tc.cc_mask = mask;
4741         adapter->tx_tstamp_tc.cc_shift = shift;
4742         adapter->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
4743 }
4744
4745 static int
4746 igb_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
4747 {
4748         struct e1000_adapter *adapter =
4749                         (struct e1000_adapter *)dev->data->dev_private;
4750
4751         adapter->systime_tc.nsec += delta;
4752         adapter->rx_tstamp_tc.nsec += delta;
4753         adapter->tx_tstamp_tc.nsec += delta;
4754
4755         return 0;
4756 }
4757
4758 static int
4759 igb_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
4760 {
4761         uint64_t ns;
4762         struct e1000_adapter *adapter =
4763                         (struct e1000_adapter *)dev->data->dev_private;
4764
4765         ns = rte_timespec_to_ns(ts);
4766
4767         /* Set the timecounters to a new value. */
4768         adapter->systime_tc.nsec = ns;
4769         adapter->rx_tstamp_tc.nsec = ns;
4770         adapter->tx_tstamp_tc.nsec = ns;
4771
4772         return 0;
4773 }
4774
4775 static int
4776 igb_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
4777 {
4778         uint64_t ns, systime_cycles;
4779         struct e1000_adapter *adapter =
4780                         (struct e1000_adapter *)dev->data->dev_private;
4781
4782         systime_cycles = igb_read_systime_cyclecounter(dev);
4783         ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles);
4784         *ts = rte_ns_to_timespec(ns);
4785
4786         return 0;
4787 }
4788
4789 static int
4790 igb_timesync_enable(struct rte_eth_dev *dev)
4791 {
4792         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4793         uint32_t tsync_ctl;
4794         uint32_t tsauxc;
4795
4796         /* Stop the timesync system time. */
4797         E1000_WRITE_REG(hw, E1000_TIMINCA, 0x0);
4798         /* Reset the timesync system time value. */
4799         switch (hw->mac.type) {
4800         case e1000_82580:
4801         case e1000_i350:
4802         case e1000_i354:
4803         case e1000_i210:
4804         case e1000_i211:
4805                 E1000_WRITE_REG(hw, E1000_SYSTIMR, 0x0);
4806                 /* fall-through */
4807         case e1000_82576:
4808                 E1000_WRITE_REG(hw, E1000_SYSTIML, 0x0);
4809                 E1000_WRITE_REG(hw, E1000_SYSTIMH, 0x0);
4810                 break;
4811         default:
4812                 /* Not supported. */
4813                 return -ENOTSUP;
4814         }
4815
4816         /* Enable system time for it isn't on by default. */
4817         tsauxc = E1000_READ_REG(hw, E1000_TSAUXC);
4818         tsauxc &= ~E1000_TSAUXC_DISABLE_SYSTIME;
4819         E1000_WRITE_REG(hw, E1000_TSAUXC, tsauxc);
4820
4821         igb_start_timecounters(dev);
4822
4823         /* Enable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
4824         E1000_WRITE_REG(hw, E1000_ETQF(E1000_ETQF_FILTER_1588),
4825                         (ETHER_TYPE_1588 |
4826                          E1000_ETQF_FILTER_ENABLE |
4827                          E1000_ETQF_1588));
4828
4829         /* Enable timestamping of received PTP packets. */
4830         tsync_ctl = E1000_READ_REG(hw, E1000_TSYNCRXCTL);
4831         tsync_ctl |= E1000_TSYNCRXCTL_ENABLED;
4832         E1000_WRITE_REG(hw, E1000_TSYNCRXCTL, tsync_ctl);
4833
4834         /* Enable Timestamping of transmitted PTP packets. */
4835         tsync_ctl = E1000_READ_REG(hw, E1000_TSYNCTXCTL);
4836         tsync_ctl |= E1000_TSYNCTXCTL_ENABLED;
4837         E1000_WRITE_REG(hw, E1000_TSYNCTXCTL, tsync_ctl);
4838
4839         return 0;
4840 }
4841
4842 static int
4843 igb_timesync_disable(struct rte_eth_dev *dev)
4844 {
4845         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4846         uint32_t tsync_ctl;
4847
4848         /* Disable timestamping of transmitted PTP packets. */
4849         tsync_ctl = E1000_READ_REG(hw, E1000_TSYNCTXCTL);
4850         tsync_ctl &= ~E1000_TSYNCTXCTL_ENABLED;
4851         E1000_WRITE_REG(hw, E1000_TSYNCTXCTL, tsync_ctl);
4852
4853         /* Disable timestamping of received PTP packets. */
4854         tsync_ctl = E1000_READ_REG(hw, E1000_TSYNCRXCTL);
4855         tsync_ctl &= ~E1000_TSYNCRXCTL_ENABLED;
4856         E1000_WRITE_REG(hw, E1000_TSYNCRXCTL, tsync_ctl);
4857
4858         /* Disable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
4859         E1000_WRITE_REG(hw, E1000_ETQF(E1000_ETQF_FILTER_1588), 0);
4860
4861         /* Stop incrementating the System Time registers. */
4862         E1000_WRITE_REG(hw, E1000_TIMINCA, 0);
4863
4864         return 0;
4865 }
4866
4867 static int
4868 igb_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
4869                                struct timespec *timestamp,
4870                                uint32_t flags __rte_unused)
4871 {
4872         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4873         struct e1000_adapter *adapter =
4874                         (struct e1000_adapter *)dev->data->dev_private;
4875         uint32_t tsync_rxctl;
4876         uint64_t rx_tstamp_cycles;
4877         uint64_t ns;
4878
4879         tsync_rxctl = E1000_READ_REG(hw, E1000_TSYNCRXCTL);
4880         if ((tsync_rxctl & E1000_TSYNCRXCTL_VALID) == 0)
4881                 return -EINVAL;
4882
4883         rx_tstamp_cycles = igb_read_rx_tstamp_cyclecounter(dev);
4884         ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles);
4885         *timestamp = rte_ns_to_timespec(ns);
4886
4887         return  0;
4888 }
4889
4890 static int
4891 igb_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
4892                                struct timespec *timestamp)
4893 {
4894         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4895         struct e1000_adapter *adapter =
4896                         (struct e1000_adapter *)dev->data->dev_private;
4897         uint32_t tsync_txctl;
4898         uint64_t tx_tstamp_cycles;
4899         uint64_t ns;
4900
4901         tsync_txctl = E1000_READ_REG(hw, E1000_TSYNCTXCTL);
4902         if ((tsync_txctl & E1000_TSYNCTXCTL_VALID) == 0)
4903                 return -EINVAL;
4904
4905         tx_tstamp_cycles = igb_read_tx_tstamp_cyclecounter(dev);
4906         ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles);
4907         *timestamp = rte_ns_to_timespec(ns);
4908
4909         return  0;
4910 }
4911
4912 static int
4913 eth_igb_get_reg_length(struct rte_eth_dev *dev __rte_unused)
4914 {
4915         int count = 0;
4916         int g_ind = 0;
4917         const struct reg_info *reg_group;
4918
4919         while ((reg_group = igb_regs[g_ind++]))
4920                 count += igb_reg_group_count(reg_group);
4921
4922         return count;
4923 }
4924
4925 static int
4926 igbvf_get_reg_length(struct rte_eth_dev *dev __rte_unused)
4927 {
4928         int count = 0;
4929         int g_ind = 0;
4930         const struct reg_info *reg_group;
4931
4932         while ((reg_group = igbvf_regs[g_ind++]))
4933                 count += igb_reg_group_count(reg_group);
4934
4935         return count;
4936 }
4937
4938 static int
4939 eth_igb_get_regs(struct rte_eth_dev *dev,
4940         struct rte_dev_reg_info *regs)
4941 {
4942         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4943         uint32_t *data = regs->data;
4944         int g_ind = 0;
4945         int count = 0;
4946         const struct reg_info *reg_group;
4947
4948         /* Support only full register dump */
4949         if ((regs->length == 0) ||
4950             (regs->length == (uint32_t)eth_igb_get_reg_length(dev))) {
4951                 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
4952                         hw->device_id;
4953                 while ((reg_group = igb_regs[g_ind++]))
4954                         count += igb_read_regs_group(dev, &data[count],
4955                                                         reg_group);
4956                 return 0;
4957         }
4958
4959         return -ENOTSUP;
4960 }
4961
4962 static int
4963 igbvf_get_regs(struct rte_eth_dev *dev,
4964         struct rte_dev_reg_info *regs)
4965 {
4966         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4967         uint32_t *data = regs->data;
4968         int g_ind = 0;
4969         int count = 0;
4970         const struct reg_info *reg_group;
4971
4972         /* Support only full register dump */
4973         if ((regs->length == 0) ||
4974             (regs->length == (uint32_t)igbvf_get_reg_length(dev))) {
4975                 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
4976                         hw->device_id;
4977                 while ((reg_group = igbvf_regs[g_ind++]))
4978                         count += igb_read_regs_group(dev, &data[count],
4979                                                         reg_group);
4980                 return 0;
4981         }
4982
4983         return -ENOTSUP;
4984 }
4985
4986 static int
4987 eth_igb_get_eeprom_length(struct rte_eth_dev *dev)
4988 {
4989         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4990
4991         /* Return unit is byte count */
4992         return hw->nvm.word_size * 2;
4993 }
4994
4995 static int
4996 eth_igb_get_eeprom(struct rte_eth_dev *dev,
4997         struct rte_dev_eeprom_info *in_eeprom)
4998 {
4999         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5000         struct e1000_nvm_info *nvm = &hw->nvm;
5001         uint16_t *data = in_eeprom->data;
5002         int first, length;
5003
5004         first = in_eeprom->offset >> 1;
5005         length = in_eeprom->length >> 1;
5006         if ((first >= hw->nvm.word_size) ||
5007             ((first + length) >= hw->nvm.word_size))
5008                 return -EINVAL;
5009
5010         in_eeprom->magic = hw->vendor_id |
5011                 ((uint32_t)hw->device_id << 16);
5012
5013         if ((nvm->ops.read) == NULL)
5014                 return -ENOTSUP;
5015
5016         return nvm->ops.read(hw, first, length, data);
5017 }
5018
5019 static int
5020 eth_igb_set_eeprom(struct rte_eth_dev *dev,
5021         struct rte_dev_eeprom_info *in_eeprom)
5022 {
5023         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5024         struct e1000_nvm_info *nvm = &hw->nvm;
5025         uint16_t *data = in_eeprom->data;
5026         int first, length;
5027
5028         first = in_eeprom->offset >> 1;
5029         length = in_eeprom->length >> 1;
5030         if ((first >= hw->nvm.word_size) ||
5031             ((first + length) >= hw->nvm.word_size))
5032                 return -EINVAL;
5033
5034         in_eeprom->magic = (uint32_t)hw->vendor_id |
5035                 ((uint32_t)hw->device_id << 16);
5036
5037         if ((nvm->ops.write) == NULL)
5038                 return -ENOTSUP;
5039         return nvm->ops.write(hw,  first, length, data);
5040 }
5041
5042 static struct rte_driver pmd_igb_drv = {
5043         .type = PMD_PDEV,
5044         .init = rte_igb_pmd_init,
5045 };
5046
5047 static struct rte_driver pmd_igbvf_drv = {
5048         .type = PMD_PDEV,
5049         .init = rte_igbvf_pmd_init,
5050 };
5051
5052 static int
5053 eth_igb_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
5054 {
5055         struct e1000_hw *hw =
5056                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5057         uint32_t mask = 1 << queue_id;
5058
5059         E1000_WRITE_REG(hw, E1000_EIMC, mask);
5060         E1000_WRITE_FLUSH(hw);
5061
5062         return 0;
5063 }
5064
5065 static int
5066 eth_igb_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
5067 {
5068         struct e1000_hw *hw =
5069                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5070         uint32_t mask = 1 << queue_id;
5071         uint32_t regval;
5072
5073         regval = E1000_READ_REG(hw, E1000_EIMS);
5074         E1000_WRITE_REG(hw, E1000_EIMS, regval | mask);
5075         E1000_WRITE_FLUSH(hw);
5076
5077         rte_intr_enable(&dev->pci_dev->intr_handle);
5078
5079         return 0;
5080 }
5081
5082 static void
5083 eth_igb_write_ivar(struct e1000_hw *hw, uint8_t  msix_vector,
5084                    uint8_t index, uint8_t offset)
5085 {
5086         uint32_t val = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index);
5087
5088         /* clear bits */
5089         val &= ~((uint32_t)0xFF << offset);
5090
5091         /* write vector and valid bit */
5092         val |= (msix_vector | E1000_IVAR_VALID) << offset;
5093
5094         E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, val);
5095 }
5096
5097 static void
5098 eth_igb_assign_msix_vector(struct e1000_hw *hw, int8_t direction,
5099                            uint8_t queue, uint8_t msix_vector)
5100 {
5101         uint32_t tmp = 0;
5102
5103         if (hw->mac.type == e1000_82575) {
5104                 if (direction == 0)
5105                         tmp = E1000_EICR_RX_QUEUE0 << queue;
5106                 else if (direction == 1)
5107                         tmp = E1000_EICR_TX_QUEUE0 << queue;
5108                 E1000_WRITE_REG(hw, E1000_MSIXBM(msix_vector), tmp);
5109         } else if (hw->mac.type == e1000_82576) {
5110                 if ((direction == 0) || (direction == 1))
5111                         eth_igb_write_ivar(hw, msix_vector, queue & 0x7,
5112                                            ((queue & 0x8) << 1) +
5113                                            8 * direction);
5114         } else if ((hw->mac.type == e1000_82580) ||
5115                         (hw->mac.type == e1000_i350) ||
5116                         (hw->mac.type == e1000_i354) ||
5117                         (hw->mac.type == e1000_i210) ||
5118                         (hw->mac.type == e1000_i211)) {
5119                 if ((direction == 0) || (direction == 1))
5120                         eth_igb_write_ivar(hw, msix_vector,
5121                                            queue >> 1,
5122                                            ((queue & 0x1) << 4) +
5123                                            8 * direction);
5124         }
5125 }
5126
5127 /* Sets up the hardware to generate MSI-X interrupts properly
5128  * @hw
5129  *  board private structure
5130  */
5131 static void
5132 eth_igb_configure_msix_intr(struct rte_eth_dev *dev)
5133 {
5134         int queue_id;
5135         uint32_t tmpval, regval, intr_mask;
5136         struct e1000_hw *hw =
5137                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5138         uint32_t vec = E1000_MISC_VEC_ID;
5139         uint32_t base = E1000_MISC_VEC_ID;
5140         uint32_t misc_shift = 0;
5141
5142         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
5143
5144         /* won't configure msix register if no mapping is done
5145          * between intr vector and event fd
5146          */
5147         if (!rte_intr_dp_is_en(intr_handle))
5148                 return;
5149
5150         if (rte_intr_allow_others(intr_handle)) {
5151                 vec = base = E1000_RX_VEC_START;
5152                 misc_shift = 1;
5153         }
5154
5155         /* set interrupt vector for other causes */
5156         if (hw->mac.type == e1000_82575) {
5157                 tmpval = E1000_READ_REG(hw, E1000_CTRL_EXT);
5158                 /* enable MSI-X PBA support */
5159                 tmpval |= E1000_CTRL_EXT_PBA_CLR;
5160
5161                 /* Auto-Mask interrupts upon ICR read */
5162                 tmpval |= E1000_CTRL_EXT_EIAME;
5163                 tmpval |= E1000_CTRL_EXT_IRCA;
5164
5165                 E1000_WRITE_REG(hw, E1000_CTRL_EXT, tmpval);
5166
5167                 /* enable msix_other interrupt */
5168                 E1000_WRITE_REG_ARRAY(hw, E1000_MSIXBM(0), 0, E1000_EIMS_OTHER);
5169                 regval = E1000_READ_REG(hw, E1000_EIAC);
5170                 E1000_WRITE_REG(hw, E1000_EIAC, regval | E1000_EIMS_OTHER);
5171                 regval = E1000_READ_REG(hw, E1000_EIAM);
5172                 E1000_WRITE_REG(hw, E1000_EIMS, regval | E1000_EIMS_OTHER);
5173         } else if ((hw->mac.type == e1000_82576) ||
5174                         (hw->mac.type == e1000_82580) ||
5175                         (hw->mac.type == e1000_i350) ||
5176                         (hw->mac.type == e1000_i354) ||
5177                         (hw->mac.type == e1000_i210) ||
5178                         (hw->mac.type == e1000_i211)) {
5179                 /* turn on MSI-X capability first */
5180                 E1000_WRITE_REG(hw, E1000_GPIE, E1000_GPIE_MSIX_MODE |
5181                                         E1000_GPIE_PBA | E1000_GPIE_EIAME |
5182                                         E1000_GPIE_NSICR);
5183                 intr_mask = RTE_LEN2MASK(intr_handle->nb_efd, uint32_t) <<
5184                         misc_shift;
5185                 regval = E1000_READ_REG(hw, E1000_EIAC);
5186                 E1000_WRITE_REG(hw, E1000_EIAC, regval | intr_mask);
5187
5188                 /* enable msix_other interrupt */
5189                 regval = E1000_READ_REG(hw, E1000_EIMS);
5190                 E1000_WRITE_REG(hw, E1000_EIMS, regval | intr_mask);
5191                 tmpval = (dev->data->nb_rx_queues | E1000_IVAR_VALID) << 8;
5192                 E1000_WRITE_REG(hw, E1000_IVAR_MISC, tmpval);
5193         }
5194
5195         /* use EIAM to auto-mask when MSI-X interrupt
5196          * is asserted, this saves a register write for every interrupt
5197          */
5198         intr_mask = RTE_LEN2MASK(intr_handle->nb_efd, uint32_t) <<
5199                 misc_shift;
5200         regval = E1000_READ_REG(hw, E1000_EIAM);
5201         E1000_WRITE_REG(hw, E1000_EIAM, regval | intr_mask);
5202
5203         for (queue_id = 0; queue_id < dev->data->nb_rx_queues; queue_id++) {
5204                 eth_igb_assign_msix_vector(hw, 0, queue_id, vec);
5205                 intr_handle->intr_vec[queue_id] = vec;
5206                 if (vec < base + intr_handle->nb_efd - 1)
5207                         vec++;
5208         }
5209
5210         E1000_WRITE_FLUSH(hw);
5211 }
5212
5213 PMD_REGISTER_DRIVER(pmd_igb_drv);
5214 PMD_REGISTER_DRIVER(pmd_igbvf_drv);