drivers/net/e1000/igb_ethdev.c

   1 /*-
   2  *   BSD LICENSE
   3  *
   4  *   Copyright(c) 2010-2016 Intel Corporation. All rights reserved.
   5  *   All rights reserved.
   6  *
   7  *   Redistribution and use in source and binary forms, with or without
   8  *   modification, are permitted provided that the following conditions
   9  *   are met:
  10  *
  11  *     * Redistributions of source code must retain the above copyright
  12  *       notice, this list of conditions and the following disclaimer.
  13  *     * Redistributions in binary form must reproduce the above copyright
  14  *       notice, this list of conditions and the following disclaimer in
  15  *       the documentation and/or other materials provided with the
  16  *       distribution.
  17  *     * Neither the name of Intel Corporation nor the names of its
  18  *       contributors may be used to endorse or promote products derived
  19  *       from this software without specific prior written permission.
  20  *
  21  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 #include <sys/queue.h>
  35 #include <stdio.h>
  36 #include <errno.h>
  37 #include <stdint.h>
  38 #include <stdarg.h>
  39
  40 #include <rte_common.h>
  41 #include <rte_interrupts.h>
  42 #include <rte_byteorder.h>
  43 #include <rte_log.h>
  44 #include <rte_debug.h>
  45 #include <rte_pci.h>
  46 #include <rte_ether.h>
  47 #include <rte_ethdev.h>
  48 #include <rte_memory.h>
  49 #include <rte_memzone.h>
  50 #include <rte_eal.h>
  51 #include <rte_atomic.h>
  52 #include <rte_malloc.h>
  53 #include <rte_dev.h>
  54
  55 #include "e1000_logs.h"
  56 #include "base/e1000_api.h"
  57 #include "e1000_ethdev.h"
  58 #include "igb_regs.h"
  59
  60 /*
  61  * Default values for port configuration
  62  */
  63 #define IGB_DEFAULT_RX_FREE_THRESH  32
  64
  65 #define IGB_DEFAULT_RX_PTHRESH      ((hw->mac.type == e1000_i354) ? 12 : 8)
  66 #define IGB_DEFAULT_RX_HTHRESH      8
  67 #define IGB_DEFAULT_RX_WTHRESH      ((hw->mac.type == e1000_82576) ? 1 : 4)
  68
  69 #define IGB_DEFAULT_TX_PTHRESH      ((hw->mac.type == e1000_i354) ? 20 : 8)
  70 #define IGB_DEFAULT_TX_HTHRESH      1
  71 #define IGB_DEFAULT_TX_WTHRESH      ((hw->mac.type == e1000_82576) ? 1 : 16)
  72
  73 #define IGB_HKEY_MAX_INDEX 10
  74
  75 /* Bit shift and mask */
  76 #define IGB_4_BIT_WIDTH  (CHAR_BIT / 2)
  77 #define IGB_4_BIT_MASK   RTE_LEN2MASK(IGB_4_BIT_WIDTH, uint8_t)
  78 #define IGB_8_BIT_WIDTH  CHAR_BIT
  79 #define IGB_8_BIT_MASK   UINT8_MAX
  80
  81 /* Additional timesync values. */
  82 #define E1000_CYCLECOUNTER_MASK      0xffffffffffffffffULL
  83 #define E1000_ETQF_FILTER_1588       3
  84 #define IGB_82576_TSYNC_SHIFT        16
  85 #define E1000_INCPERIOD_82576        (1 << E1000_TIMINCA_16NS_SHIFT)
  86 #define E1000_INCVALUE_82576         (16 << IGB_82576_TSYNC_SHIFT)
  87 #define E1000_TSAUXC_DISABLE_SYSTIME 0x80000000
  88
  89 #define E1000_VTIVAR_MISC                0x01740
  90 #define E1000_VTIVAR_MISC_MASK           0xFF
  91 #define E1000_VTIVAR_VALID               0x80
  92 #define E1000_VTIVAR_MISC_MAILBOX        0
  93 #define E1000_VTIVAR_MISC_INTR_MASK      0x3
  94
  95 /* External VLAN Enable bit mask */
  96 #define E1000_CTRL_EXT_EXT_VLAN      (1 << 26)
  97
  98 /* External VLAN Ether Type bit mask and shift */
  99 #define E1000_VET_VET_EXT            0xFFFF0000
 100 #define E1000_VET_VET_EXT_SHIFT      16
 101
 102 static int  eth_igb_configure(struct rte_eth_dev *dev);
 103 static int  eth_igb_start(struct rte_eth_dev *dev);
 104 static void eth_igb_stop(struct rte_eth_dev *dev);
 105 static int  eth_igb_dev_set_link_up(struct rte_eth_dev *dev);
 106 static int  eth_igb_dev_set_link_down(struct rte_eth_dev *dev);
 107 static void eth_igb_close(struct rte_eth_dev *dev);
 108 static void eth_igb_promiscuous_enable(struct rte_eth_dev *dev);
 109 static void eth_igb_promiscuous_disable(struct rte_eth_dev *dev);
 110 static void eth_igb_allmulticast_enable(struct rte_eth_dev *dev);
 111 static void eth_igb_allmulticast_disable(struct rte_eth_dev *dev);
 112 static int  eth_igb_link_update(struct rte_eth_dev *dev,
 113                                 int wait_to_complete);
 114 static void eth_igb_stats_get(struct rte_eth_dev *dev,
 115                                 struct rte_eth_stats *rte_stats);
 116 static int eth_igb_xstats_get(struct rte_eth_dev *dev,
 117                               struct rte_eth_xstat *xstats, unsigned n);
 118 static int eth_igb_xstats_get_names(struct rte_eth_dev *dev,
 119                                     struct rte_eth_xstat_name *xstats_names,
 120                                     unsigned limit);
 121 static void eth_igb_stats_reset(struct rte_eth_dev *dev);
 122 static void eth_igb_xstats_reset(struct rte_eth_dev *dev);
 123 static void eth_igb_infos_get(struct rte_eth_dev *dev,
 124                               struct rte_eth_dev_info *dev_info);
 125 static const uint32_t *eth_igb_supported_ptypes_get(struct rte_eth_dev *dev);
 126 static void eth_igbvf_infos_get(struct rte_eth_dev *dev,
 127                                 struct rte_eth_dev_info *dev_info);
 128 static int  eth_igb_flow_ctrl_get(struct rte_eth_dev *dev,
 129                                 struct rte_eth_fc_conf *fc_conf);
 130 static int  eth_igb_flow_ctrl_set(struct rte_eth_dev *dev,
 131                                 struct rte_eth_fc_conf *fc_conf);
 132 static int eth_igb_lsc_interrupt_setup(struct rte_eth_dev *dev, uint8_t on);
 133 static int eth_igb_rxq_interrupt_setup(struct rte_eth_dev *dev);
 134 static int eth_igb_interrupt_get_status(struct rte_eth_dev *dev);
 135 static int eth_igb_interrupt_action(struct rte_eth_dev *dev);
 136 static void eth_igb_interrupt_handler(struct rte_intr_handle *handle,
 137                                                         void *param);
 138 static int  igb_hardware_init(struct e1000_hw *hw);
 139 static void igb_hw_control_acquire(struct e1000_hw *hw);
 140 static void igb_hw_control_release(struct e1000_hw *hw);
 141 static void igb_init_manageability(struct e1000_hw *hw);
 142 static void igb_release_manageability(struct e1000_hw *hw);
 143
 144 static int  eth_igb_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
 145
 146 static int eth_igb_vlan_filter_set(struct rte_eth_dev *dev,
 147                 uint16_t vlan_id, int on);
 148 static int eth_igb_vlan_tpid_set(struct rte_eth_dev *dev,
 149                                  enum rte_vlan_type vlan_type,
 150                                  uint16_t tpid_id);
 151 static void eth_igb_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 152
 153 static void igb_vlan_hw_filter_enable(struct rte_eth_dev *dev);
 154 static void igb_vlan_hw_filter_disable(struct rte_eth_dev *dev);
 155 static void igb_vlan_hw_strip_enable(struct rte_eth_dev *dev);
 156 static void igb_vlan_hw_strip_disable(struct rte_eth_dev *dev);
 157 static void igb_vlan_hw_extend_enable(struct rte_eth_dev *dev);
 158 static void igb_vlan_hw_extend_disable(struct rte_eth_dev *dev);
 159
 160 static int eth_igb_led_on(struct rte_eth_dev *dev);
 161 static int eth_igb_led_off(struct rte_eth_dev *dev);
 162
 163 static void igb_intr_disable(struct e1000_hw *hw);
 164 static int  igb_get_rx_buffer_size(struct e1000_hw *hw);
 165 static void eth_igb_rar_set(struct rte_eth_dev *dev,
 166                 struct ether_addr *mac_addr,
 167                 uint32_t index, uint32_t pool);
 168 static void eth_igb_rar_clear(struct rte_eth_dev *dev, uint32_t index);
 169 static void eth_igb_default_mac_addr_set(struct rte_eth_dev *dev,
 170                 struct ether_addr *addr);
 171
 172 static void igbvf_intr_disable(struct e1000_hw *hw);
 173 static int igbvf_dev_configure(struct rte_eth_dev *dev);
 174 static int igbvf_dev_start(struct rte_eth_dev *dev);
 175 static void igbvf_dev_stop(struct rte_eth_dev *dev);
 176 static void igbvf_dev_close(struct rte_eth_dev *dev);
 177 static void igbvf_promiscuous_enable(struct rte_eth_dev *dev);
 178 static void igbvf_promiscuous_disable(struct rte_eth_dev *dev);
 179 static void igbvf_allmulticast_enable(struct rte_eth_dev *dev);
 180 static void igbvf_allmulticast_disable(struct rte_eth_dev *dev);
 181 static int eth_igbvf_link_update(struct e1000_hw *hw);
 182 static void eth_igbvf_stats_get(struct rte_eth_dev *dev,
 183                                 struct rte_eth_stats *rte_stats);
 184 static int eth_igbvf_xstats_get(struct rte_eth_dev *dev,
 185                                 struct rte_eth_xstat *xstats, unsigned n);
 186 static int eth_igbvf_xstats_get_names(struct rte_eth_dev *dev,
 187                                       struct rte_eth_xstat_name *xstats_names,
 188                                       unsigned limit);
 189 static void eth_igbvf_stats_reset(struct rte_eth_dev *dev);
 190 static int igbvf_vlan_filter_set(struct rte_eth_dev *dev,
 191                 uint16_t vlan_id, int on);
 192 static int igbvf_set_vfta(struct e1000_hw *hw, uint16_t vid, bool on);
 193 static void igbvf_set_vfta_all(struct rte_eth_dev *dev, bool on);
 194 static void igbvf_default_mac_addr_set(struct rte_eth_dev *dev,
 195                 struct ether_addr *addr);
 196 static int igbvf_get_reg_length(struct rte_eth_dev *dev);
 197 static int igbvf_get_regs(struct rte_eth_dev *dev,
 198                 struct rte_dev_reg_info *regs);
 199
 200 static int eth_igb_rss_reta_update(struct rte_eth_dev *dev,
 201                                    struct rte_eth_rss_reta_entry64 *reta_conf,
 202                                    uint16_t reta_size);
 203 static int eth_igb_rss_reta_query(struct rte_eth_dev *dev,
 204                                   struct rte_eth_rss_reta_entry64 *reta_conf,
 205                                   uint16_t reta_size);
 206
 207 static int eth_igb_syn_filter_set(struct rte_eth_dev *dev,
 208                         struct rte_eth_syn_filter *filter,
 209                         bool add);
 210 static int eth_igb_syn_filter_get(struct rte_eth_dev *dev,
 211                         struct rte_eth_syn_filter *filter);
 212 static int eth_igb_syn_filter_handle(struct rte_eth_dev *dev,
 213                         enum rte_filter_op filter_op,
 214                         void *arg);
 215 static int igb_add_2tuple_filter(struct rte_eth_dev *dev,
 216                         struct rte_eth_ntuple_filter *ntuple_filter);
 217 static int igb_remove_2tuple_filter(struct rte_eth_dev *dev,
 218                         struct rte_eth_ntuple_filter *ntuple_filter);
 219 static int eth_igb_add_del_flex_filter(struct rte_eth_dev *dev,
 220                         struct rte_eth_flex_filter *filter,
 221                         bool add);
 222 static int eth_igb_get_flex_filter(struct rte_eth_dev *dev,
 223                         struct rte_eth_flex_filter *filter);
 224 static int eth_igb_flex_filter_handle(struct rte_eth_dev *dev,
 225                         enum rte_filter_op filter_op,
 226                         void *arg);
 227 static int igb_add_5tuple_filter_82576(struct rte_eth_dev *dev,
 228                         struct rte_eth_ntuple_filter *ntuple_filter);
 229 static int igb_remove_5tuple_filter_82576(struct rte_eth_dev *dev,
 230                         struct rte_eth_ntuple_filter *ntuple_filter);
 231 static int igb_add_del_ntuple_filter(struct rte_eth_dev *dev,
 232                         struct rte_eth_ntuple_filter *filter,
 233                         bool add);
 234 static int igb_get_ntuple_filter(struct rte_eth_dev *dev,
 235                         struct rte_eth_ntuple_filter *filter);
 236 static int igb_ntuple_filter_handle(struct rte_eth_dev *dev,
 237                                 enum rte_filter_op filter_op,
 238                                 void *arg);
 239 static int igb_add_del_ethertype_filter(struct rte_eth_dev *dev,
 240                         struct rte_eth_ethertype_filter *filter,
 241                         bool add);
 242 static int igb_ethertype_filter_handle(struct rte_eth_dev *dev,
 243                                 enum rte_filter_op filter_op,
 244                                 void *arg);
 245 static int igb_get_ethertype_filter(struct rte_eth_dev *dev,
 246                         struct rte_eth_ethertype_filter *filter);
 247 static int eth_igb_filter_ctrl(struct rte_eth_dev *dev,
 248                      enum rte_filter_type filter_type,
 249                      enum rte_filter_op filter_op,
 250                      void *arg);
 251 static int eth_igb_get_reg_length(struct rte_eth_dev *dev);
 252 static int eth_igb_get_regs(struct rte_eth_dev *dev,
 253                 struct rte_dev_reg_info *regs);
 254 static int eth_igb_get_eeprom_length(struct rte_eth_dev *dev);
 255 static int eth_igb_get_eeprom(struct rte_eth_dev *dev,
 256                 struct rte_dev_eeprom_info *eeprom);
 257 static int eth_igb_set_eeprom(struct rte_eth_dev *dev,
 258                 struct rte_dev_eeprom_info *eeprom);
 259 static int eth_igb_set_mc_addr_list(struct rte_eth_dev *dev,
 260                                     struct ether_addr *mc_addr_set,
 261                                     uint32_t nb_mc_addr);
 262 static int igb_timesync_enable(struct rte_eth_dev *dev);
 263 static int igb_timesync_disable(struct rte_eth_dev *dev);
 264 static int igb_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
 265                                           struct timespec *timestamp,
 266                                           uint32_t flags);
 267 static int igb_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
 268                                           struct timespec *timestamp);
 269 static int igb_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);
 270 static int igb_timesync_read_time(struct rte_eth_dev *dev,
 271                                   struct timespec *timestamp);
 272 static int igb_timesync_write_time(struct rte_eth_dev *dev,
 273                                    const struct timespec *timestamp);
 274 static int eth_igb_rx_queue_intr_enable(struct rte_eth_dev *dev,
 275                                         uint16_t queue_id);
 276 static int eth_igb_rx_queue_intr_disable(struct rte_eth_dev *dev,
 277                                          uint16_t queue_id);
 278 static void eth_igb_assign_msix_vector(struct e1000_hw *hw, int8_t direction,
 279                                        uint8_t queue, uint8_t msix_vector);
 280 static void eth_igb_write_ivar(struct e1000_hw *hw, uint8_t msix_vector,
 281                                uint8_t index, uint8_t offset);
 282 static void eth_igb_configure_msix_intr(struct rte_eth_dev *dev);
 283 static void eth_igbvf_interrupt_handler(struct rte_intr_handle *handle,
 284                                         void *param);
 285 static void igbvf_mbx_process(struct rte_eth_dev *dev);
 286
 287 /*
 288  * Define VF Stats MACRO for Non "cleared on read" register
 289  */
 290 #define UPDATE_VF_STAT(reg, last, cur)            \
 291 {                                                 \
 292         u32 latest = E1000_READ_REG(hw, reg);     \
 293         cur += (latest - last) & UINT_MAX;        \
 294         last = latest;                            \
 295 }
 296
 297 #define IGB_FC_PAUSE_TIME 0x0680
 298 #define IGB_LINK_UPDATE_CHECK_TIMEOUT  90  /* 9s */
 299 #define IGB_LINK_UPDATE_CHECK_INTERVAL 100 /* ms */
 300
 301 #define IGBVF_PMD_NAME "rte_igbvf_pmd"     /* PMD name */
 302
 303 static enum e1000_fc_mode igb_fc_setting = e1000_fc_full;
 304
 305 /*
 306  * The set of PCI devices this driver supports
 307  */
 308 static const struct rte_pci_id pci_id_igb_map[] = {
 309         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576) },
 310         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_FIBER) },
 311         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_SERDES) },
 312         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_QUAD_COPPER) },
 313         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_QUAD_COPPER_ET2) },
 314         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_NS) },
 315         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_NS_SERDES) },
 316         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_SERDES_QUAD) },
 317
 318         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82575EB_COPPER) },
 319         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82575EB_FIBER_SERDES) },
 320         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82575GB_QUAD_COPPER) },
 321
 322         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82580_COPPER) },
 323         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82580_FIBER) },
 324         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82580_SERDES) },
 325         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82580_SGMII) },
 326         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82580_COPPER_DUAL) },
 327         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82580_QUAD_FIBER) },
 328
 329         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_COPPER) },
 330         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_FIBER) },
 331         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_SERDES) },
 332         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_SGMII) },
 333         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_DA4) },
 334         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_COPPER) },
 335         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_COPPER_OEM1) },
 336         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_COPPER_IT) },
 337         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_FIBER) },
 338         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_SERDES) },
 339         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_SGMII) },
 340         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I211_COPPER) },
 341         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I354_BACKPLANE_1GBPS) },
 342         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I354_SGMII) },
 343         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I354_BACKPLANE_2_5GBPS) },
 344         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_DH89XXCC_SGMII) },
 345         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_DH89XXCC_SERDES) },
 346         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_DH89XXCC_BACKPLANE) },
 347         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_DH89XXCC_SFP) },
 348         { .vendor_id = 0, /* sentinel */ },
 349 };
 350
 351 /*
 352  * The set of PCI devices this driver supports (for 82576&I350 VF)
 353  */
 354 static const struct rte_pci_id pci_id_igbvf_map[] = {
 355         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_VF) },
 356         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_VF_HV) },
 357         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_VF) },
 358         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_VF_HV) },
 359         { .vendor_id = 0, /* sentinel */ },
 360 };
 361
 362 static const struct rte_eth_desc_lim rx_desc_lim = {
 363         .nb_max = E1000_MAX_RING_DESC,
 364         .nb_min = E1000_MIN_RING_DESC,
 365         .nb_align = IGB_RXD_ALIGN,
 366 };
 367
 368 static const struct rte_eth_desc_lim tx_desc_lim = {
 369         .nb_max = E1000_MAX_RING_DESC,
 370         .nb_min = E1000_MIN_RING_DESC,
 371         .nb_align = IGB_RXD_ALIGN,
 372 };
 373
 374 static const struct eth_dev_ops eth_igb_ops = {
 375         .dev_configure        = eth_igb_configure,
 376         .dev_start            = eth_igb_start,
 377         .dev_stop             = eth_igb_stop,
 378         .dev_set_link_up      = eth_igb_dev_set_link_up,
 379         .dev_set_link_down    = eth_igb_dev_set_link_down,
 380         .dev_close            = eth_igb_close,
 381         .promiscuous_enable   = eth_igb_promiscuous_enable,
 382         .promiscuous_disable  = eth_igb_promiscuous_disable,
 383         .allmulticast_enable  = eth_igb_allmulticast_enable,
 384         .allmulticast_disable = eth_igb_allmulticast_disable,
 385         .link_update          = eth_igb_link_update,
 386         .stats_get            = eth_igb_stats_get,
 387         .xstats_get           = eth_igb_xstats_get,
 388         .xstats_get_names     = eth_igb_xstats_get_names,
 389         .stats_reset          = eth_igb_stats_reset,
 390         .xstats_reset         = eth_igb_xstats_reset,
 391         .dev_infos_get        = eth_igb_infos_get,
 392         .dev_supported_ptypes_get = eth_igb_supported_ptypes_get,
 393         .mtu_set              = eth_igb_mtu_set,
 394         .vlan_filter_set      = eth_igb_vlan_filter_set,
 395         .vlan_tpid_set        = eth_igb_vlan_tpid_set,
 396         .vlan_offload_set     = eth_igb_vlan_offload_set,
 397         .rx_queue_setup       = eth_igb_rx_queue_setup,
 398         .rx_queue_intr_enable = eth_igb_rx_queue_intr_enable,
 399         .rx_queue_intr_disable = eth_igb_rx_queue_intr_disable,
 400         .rx_queue_release     = eth_igb_rx_queue_release,
 401         .rx_queue_count       = eth_igb_rx_queue_count,
 402         .rx_descriptor_done   = eth_igb_rx_descriptor_done,
 403         .tx_queue_setup       = eth_igb_tx_queue_setup,
 404         .tx_queue_release     = eth_igb_tx_queue_release,
 405         .dev_led_on           = eth_igb_led_on,
 406         .dev_led_off          = eth_igb_led_off,
 407         .flow_ctrl_get        = eth_igb_flow_ctrl_get,
 408         .flow_ctrl_set        = eth_igb_flow_ctrl_set,
 409         .mac_addr_add         = eth_igb_rar_set,
 410         .mac_addr_remove      = eth_igb_rar_clear,
 411         .mac_addr_set         = eth_igb_default_mac_addr_set,
 412         .reta_update          = eth_igb_rss_reta_update,
 413         .reta_query           = eth_igb_rss_reta_query,
 414         .rss_hash_update      = eth_igb_rss_hash_update,
 415         .rss_hash_conf_get    = eth_igb_rss_hash_conf_get,
 416         .filter_ctrl          = eth_igb_filter_ctrl,
 417         .set_mc_addr_list     = eth_igb_set_mc_addr_list,
 418         .rxq_info_get         = igb_rxq_info_get,
 419         .txq_info_get         = igb_txq_info_get,
 420         .timesync_enable      = igb_timesync_enable,
 421         .timesync_disable     = igb_timesync_disable,
 422         .timesync_read_rx_timestamp = igb_timesync_read_rx_timestamp,
 423         .timesync_read_tx_timestamp = igb_timesync_read_tx_timestamp,
 424         .get_reg              = eth_igb_get_regs,
 425         .get_eeprom_length    = eth_igb_get_eeprom_length,
 426         .get_eeprom           = eth_igb_get_eeprom,
 427         .set_eeprom           = eth_igb_set_eeprom,
 428         .timesync_adjust_time = igb_timesync_adjust_time,
 429         .timesync_read_time   = igb_timesync_read_time,
 430         .timesync_write_time  = igb_timesync_write_time,
 431 };
 432
 433 /*
 434  * dev_ops for virtual function, bare necessities for basic vf
 435  * operation have been implemented
 436  */
 437 static const struct eth_dev_ops igbvf_eth_dev_ops = {
 438         .dev_configure        = igbvf_dev_configure,
 439         .dev_start            = igbvf_dev_start,
 440         .dev_stop             = igbvf_dev_stop,
 441         .dev_close            = igbvf_dev_close,
 442         .promiscuous_enable   = igbvf_promiscuous_enable,
 443         .promiscuous_disable  = igbvf_promiscuous_disable,
 444         .allmulticast_enable  = igbvf_allmulticast_enable,
 445         .allmulticast_disable = igbvf_allmulticast_disable,
 446         .link_update          = eth_igb_link_update,
 447         .stats_get            = eth_igbvf_stats_get,
 448         .xstats_get           = eth_igbvf_xstats_get,
 449         .xstats_get_names     = eth_igbvf_xstats_get_names,
 450         .stats_reset          = eth_igbvf_stats_reset,
 451         .xstats_reset         = eth_igbvf_stats_reset,
 452         .vlan_filter_set      = igbvf_vlan_filter_set,
 453         .dev_infos_get        = eth_igbvf_infos_get,
 454         .dev_supported_ptypes_get = eth_igb_supported_ptypes_get,
 455         .rx_queue_setup       = eth_igb_rx_queue_setup,
 456         .rx_queue_release     = eth_igb_rx_queue_release,
 457         .tx_queue_setup       = eth_igb_tx_queue_setup,
 458         .tx_queue_release     = eth_igb_tx_queue_release,
 459         .set_mc_addr_list     = eth_igb_set_mc_addr_list,
 460         .rxq_info_get         = igb_rxq_info_get,
 461         .txq_info_get         = igb_txq_info_get,
 462         .mac_addr_set         = igbvf_default_mac_addr_set,
 463         .get_reg              = igbvf_get_regs,
 464 };
 465
 466 /* store statistics names and its offset in stats structure */
 467 struct rte_igb_xstats_name_off {
 468         char name[RTE_ETH_XSTATS_NAME_SIZE];
 469         unsigned offset;
 470 };
 471
 472 static const struct rte_igb_xstats_name_off rte_igb_stats_strings[] = {
 473         {"rx_crc_errors", offsetof(struct e1000_hw_stats, crcerrs)},
 474         {"rx_align_errors", offsetof(struct e1000_hw_stats, algnerrc)},
 475         {"rx_symbol_errors", offsetof(struct e1000_hw_stats, symerrs)},
 476         {"rx_missed_packets", offsetof(struct e1000_hw_stats, mpc)},
 477         {"tx_single_collision_packets", offsetof(struct e1000_hw_stats, scc)},
 478         {"tx_multiple_collision_packets", offsetof(struct e1000_hw_stats, mcc)},
 479         {"tx_excessive_collision_packets", offsetof(struct e1000_hw_stats,
 480                 ecol)},
 481         {"tx_late_collisions", offsetof(struct e1000_hw_stats, latecol)},
 482         {"tx_total_collisions", offsetof(struct e1000_hw_stats, colc)},
 483         {"tx_deferred_packets", offsetof(struct e1000_hw_stats, dc)},
 484         {"tx_no_carrier_sense_packets", offsetof(struct e1000_hw_stats, tncrs)},
 485         {"rx_carrier_ext_errors", offsetof(struct e1000_hw_stats, cexterr)},
 486         {"rx_length_errors", offsetof(struct e1000_hw_stats, rlec)},
 487         {"rx_xon_packets", offsetof(struct e1000_hw_stats, xonrxc)},
 488         {"tx_xon_packets", offsetof(struct e1000_hw_stats, xontxc)},
 489         {"rx_xoff_packets", offsetof(struct e1000_hw_stats, xoffrxc)},
 490         {"tx_xoff_packets", offsetof(struct e1000_hw_stats, xofftxc)},
 491         {"rx_flow_control_unsupported_packets", offsetof(struct e1000_hw_stats,
 492                 fcruc)},
 493         {"rx_size_64_packets", offsetof(struct e1000_hw_stats, prc64)},
 494         {"rx_size_65_to_127_packets", offsetof(struct e1000_hw_stats, prc127)},
 495         {"rx_size_128_to_255_packets", offsetof(struct e1000_hw_stats, prc255)},
 496         {"rx_size_256_to_511_packets", offsetof(struct e1000_hw_stats, prc511)},
 497         {"rx_size_512_to_1023_packets", offsetof(struct e1000_hw_stats,
 498                 prc1023)},
 499         {"rx_size_1024_to_max_packets", offsetof(struct e1000_hw_stats,
 500                 prc1522)},
 501         {"rx_broadcast_packets", offsetof(struct e1000_hw_stats, bprc)},
 502         {"rx_multicast_packets", offsetof(struct e1000_hw_stats, mprc)},
 503         {"rx_undersize_errors", offsetof(struct e1000_hw_stats, ruc)},
 504         {"rx_fragment_errors", offsetof(struct e1000_hw_stats, rfc)},
 505         {"rx_oversize_errors", offsetof(struct e1000_hw_stats, roc)},
 506         {"rx_jabber_errors", offsetof(struct e1000_hw_stats, rjc)},
 507         {"rx_management_packets", offsetof(struct e1000_hw_stats, mgprc)},
 508         {"rx_management_dropped", offsetof(struct e1000_hw_stats, mgpdc)},
 509         {"tx_management_packets", offsetof(struct e1000_hw_stats, mgptc)},
 510         {"rx_total_packets", offsetof(struct e1000_hw_stats, tpr)},
 511         {"tx_total_packets", offsetof(struct e1000_hw_stats, tpt)},
 512         {"rx_total_bytes", offsetof(struct e1000_hw_stats, tor)},
 513         {"tx_total_bytes", offsetof(struct e1000_hw_stats, tot)},
 514         {"tx_size_64_packets", offsetof(struct e1000_hw_stats, ptc64)},
 515         {"tx_size_65_to_127_packets", offsetof(struct e1000_hw_stats, ptc127)},
 516         {"tx_size_128_to_255_packets", offsetof(struct e1000_hw_stats, ptc255)},
 517         {"tx_size_256_to_511_packets", offsetof(struct e1000_hw_stats, ptc511)},
 518         {"tx_size_512_to_1023_packets", offsetof(struct e1000_hw_stats,
 519                 ptc1023)},
 520         {"tx_size_1023_to_max_packets", offsetof(struct e1000_hw_stats,
 521                 ptc1522)},
 522         {"tx_multicast_packets", offsetof(struct e1000_hw_stats, mptc)},
 523         {"tx_broadcast_packets", offsetof(struct e1000_hw_stats, bptc)},
 524         {"tx_tso_packets", offsetof(struct e1000_hw_stats, tsctc)},
 525         {"tx_tso_errors", offsetof(struct e1000_hw_stats, tsctfc)},
 526         {"rx_sent_to_host_packets", offsetof(struct e1000_hw_stats, rpthc)},
 527         {"tx_sent_by_host_packets", offsetof(struct e1000_hw_stats, hgptc)},
 528         {"rx_code_violation_packets", offsetof(struct e1000_hw_stats, scvpc)},
 529
 530         {"interrupt_assert_count", offsetof(struct e1000_hw_stats, iac)},
 531 };
 532
 533 #define IGB_NB_XSTATS (sizeof(rte_igb_stats_strings) / \
 534                 sizeof(rte_igb_stats_strings[0]))
 535
 536 static const struct rte_igb_xstats_name_off rte_igbvf_stats_strings[] = {
 537         {"rx_multicast_packets", offsetof(struct e1000_vf_stats, mprc)},
 538         {"rx_good_loopback_packets", offsetof(struct e1000_vf_stats, gprlbc)},
 539         {"tx_good_loopback_packets", offsetof(struct e1000_vf_stats, gptlbc)},
 540         {"rx_good_loopback_bytes", offsetof(struct e1000_vf_stats, gorlbc)},
 541         {"tx_good_loopback_bytes", offsetof(struct e1000_vf_stats, gotlbc)},
 542 };
 543
 544 #define IGBVF_NB_XSTATS (sizeof(rte_igbvf_stats_strings) / \
 545                 sizeof(rte_igbvf_stats_strings[0]))
 546
 547 /**
 548  * Atomically reads the link status information from global
 549  * structure rte_eth_dev.
 550  *
 551  * @param dev
 552  *   - Pointer to the structure rte_eth_dev to read from.
 553  *   - Pointer to the buffer to be saved with the link status.
 554  *
 555  * @return
 556  *   - On success, zero.
 557  *   - On failure, negative value.
 558  */
 559 static inline int
 560 rte_igb_dev_atomic_read_link_status(struct rte_eth_dev *dev,
 561                                 struct rte_eth_link *link)
 562 {
 563         struct rte_eth_link *dst = link;
 564         struct rte_eth_link *src = &(dev->data->dev_link);
 565
 566         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 567                                         *(uint64_t *)src) == 0)
 568                 return -1;
 569
 570         return 0;
 571 }
 572
 573 /**
 574  * Atomically writes the link status information into global
 575  * structure rte_eth_dev.
 576  *
 577  * @param dev
 578  *   - Pointer to the structure rte_eth_dev to read from.
 579  *   - Pointer to the buffer to be saved with the link status.
 580  *
 581  * @return
 582  *   - On success, zero.
 583  *   - On failure, negative value.
 584  */
 585 static inline int
 586 rte_igb_dev_atomic_write_link_status(struct rte_eth_dev *dev,
 587                                 struct rte_eth_link *link)
 588 {
 589         struct rte_eth_link *dst = &(dev->data->dev_link);
 590         struct rte_eth_link *src = link;
 591
 592         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 593                                         *(uint64_t *)src) == 0)
 594                 return -1;
 595
 596         return 0;
 597 }
 598
 599 static inline void
 600 igb_intr_enable(struct rte_eth_dev *dev)
 601 {
 602         struct e1000_interrupt *intr =
 603                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
 604         struct e1000_hw *hw =
 605                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 606
 607         E1000_WRITE_REG(hw, E1000_IMS, intr->mask);
 608         E1000_WRITE_FLUSH(hw);
 609 }
 610
 611 static void
 612 igb_intr_disable(struct e1000_hw *hw)
 613 {
 614         E1000_WRITE_REG(hw, E1000_IMC, ~0);
 615         E1000_WRITE_FLUSH(hw);
 616 }
 617
 618 static inline void
 619 igbvf_intr_enable(struct rte_eth_dev *dev)
 620 {
 621         struct e1000_hw *hw =
 622                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 623
 624         /* only for mailbox */
 625         E1000_WRITE_REG(hw, E1000_EIAM, 1 << E1000_VTIVAR_MISC_MAILBOX);
 626         E1000_WRITE_REG(hw, E1000_EIAC, 1 << E1000_VTIVAR_MISC_MAILBOX);
 627         E1000_WRITE_REG(hw, E1000_EIMS, 1 << E1000_VTIVAR_MISC_MAILBOX);
 628         E1000_WRITE_FLUSH(hw);
 629 }
 630
 631 /* only for mailbox now. If RX/TX needed, should extend this function.  */
 632 static void
 633 igbvf_set_ivar_map(struct e1000_hw *hw, uint8_t msix_vector)
 634 {
 635         uint32_t tmp = 0;
 636
 637         /* mailbox */
 638         tmp |= (msix_vector & E1000_VTIVAR_MISC_INTR_MASK);
 639         tmp |= E1000_VTIVAR_VALID;
 640         E1000_WRITE_REG(hw, E1000_VTIVAR_MISC, tmp);
 641 }
 642
 643 static void
 644 eth_igbvf_configure_msix_intr(struct rte_eth_dev *dev)
 645 {
 646         struct e1000_hw *hw =
 647                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 648
 649         /* Configure VF other cause ivar */
 650         igbvf_set_ivar_map(hw, E1000_VTIVAR_MISC_MAILBOX);
 651 }
 652
 653 static inline int32_t
 654 igb_pf_reset_hw(struct e1000_hw *hw)
 655 {
 656         uint32_t ctrl_ext;
 657         int32_t status;
 658
 659         status = e1000_reset_hw(hw);
 660
 661         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
 662         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
 663         ctrl_ext |= E1000_CTRL_EXT_PFRSTD;
 664         E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
 665         E1000_WRITE_FLUSH(hw);
 666
 667         return status;
 668 }
 669
 670 static void
 671 igb_identify_hardware(struct rte_eth_dev *dev)
 672 {
 673         struct e1000_hw *hw =
 674                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 675
 676         hw->vendor_id = dev->pci_dev->id.vendor_id;
 677         hw->device_id = dev->pci_dev->id.device_id;
 678         hw->subsystem_vendor_id = dev->pci_dev->id.subsystem_vendor_id;
 679         hw->subsystem_device_id = dev->pci_dev->id.subsystem_device_id;
 680
 681         e1000_set_mac_type(hw);
 682
 683         /* need to check if it is a vf device below */
 684 }
 685
 686 static int
 687 igb_reset_swfw_lock(struct e1000_hw *hw)
 688 {
 689         int ret_val;
 690
 691         /*
 692          * Do mac ops initialization manually here, since we will need
 693          * some function pointers set by this call.
 694          */
 695         ret_val = e1000_init_mac_params(hw);
 696         if (ret_val)
 697                 return ret_val;
 698
 699         /*
 700          * SMBI lock should not fail in this early stage. If this is the case,
 701          * it is due to an improper exit of the application.
 702          * So force the release of the faulty lock.
 703          */
 704         if (e1000_get_hw_semaphore_generic(hw) < 0) {
 705                 PMD_DRV_LOG(DEBUG, "SMBI lock released");
 706         }
 707         e1000_put_hw_semaphore_generic(hw);
 708
 709         if (hw->mac.ops.acquire_swfw_sync != NULL) {
 710                 uint16_t mask;
 711
 712                 /*
 713                  * Phy lock should not fail in this early stage. If this is the case,
 714                  * it is due to an improper exit of the application.
 715                  * So force the release of the faulty lock.
 716                  */
 717                 mask = E1000_SWFW_PHY0_SM << hw->bus.func;
 718                 if (hw->bus.func > E1000_FUNC_1)
 719                         mask <<= 2;
 720                 if (hw->mac.ops.acquire_swfw_sync(hw, mask) < 0) {
 721                         PMD_DRV_LOG(DEBUG, "SWFW phy%d lock released",
 722                                     hw->bus.func);
 723                 }
 724                 hw->mac.ops.release_swfw_sync(hw, mask);
 725
 726                 /*
 727                  * This one is more tricky since it is common to all ports; but
 728                  * swfw_sync retries last long enough (1s) to be almost sure that if
 729                  * lock can not be taken it is due to an improper lock of the
 730                  * semaphore.
 731                  */
 732                 mask = E1000_SWFW_EEP_SM;
 733                 if (hw->mac.ops.acquire_swfw_sync(hw, mask) < 0) {
 734                         PMD_DRV_LOG(DEBUG, "SWFW common locks released");
 735                 }
 736                 hw->mac.ops.release_swfw_sync(hw, mask);
 737         }
 738
 739         return E1000_SUCCESS;
 740 }
 741
 742 static int
 743 eth_igb_dev_init(struct rte_eth_dev *eth_dev)
 744 {
 745         int error = 0;
 746         struct rte_pci_device *pci_dev;
 747         struct e1000_hw *hw =
 748                 E1000_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 749         struct e1000_vfta * shadow_vfta =
 750                 E1000_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
 751         struct e1000_filter_info *filter_info =
 752                 E1000_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
 753         struct e1000_adapter *adapter =
 754                 E1000_DEV_PRIVATE(eth_dev->data->dev_private);
 755
 756         uint32_t ctrl_ext;
 757
 758         pci_dev = eth_dev->pci_dev;
 759
 760         eth_dev->dev_ops = &eth_igb_ops;
 761         eth_dev->rx_pkt_burst = &eth_igb_recv_pkts;
 762         eth_dev->tx_pkt_burst = &eth_igb_xmit_pkts;
 763
 764         /* for secondary processes, we don't initialise any further as primary
 765          * has already done this work. Only check we don't need a different
 766          * RX function */
 767         if (rte_eal_process_type() != RTE_PROC_PRIMARY){
 768                 if (eth_dev->data->scattered_rx)
 769                         eth_dev->rx_pkt_burst = &eth_igb_recv_scattered_pkts;
 770                 return 0;
 771         }
 772
 773         rte_eth_copy_pci_info(eth_dev, pci_dev);
 774
 775         hw->hw_addr= (void *)pci_dev->mem_resource[0].addr;
 776
 777         igb_identify_hardware(eth_dev);
 778         if (e1000_setup_init_funcs(hw, FALSE) != E1000_SUCCESS) {
 779                 error = -EIO;
 780                 goto err_late;
 781         }
 782
 783         e1000_get_bus_info(hw);
 784
 785         /* Reset any pending lock */
 786         if (igb_reset_swfw_lock(hw) != E1000_SUCCESS) {
 787                 error = -EIO;
 788                 goto err_late;
 789         }
 790
 791         /* Finish initialization */
 792         if (e1000_setup_init_funcs(hw, TRUE) != E1000_SUCCESS) {
 793                 error = -EIO;
 794                 goto err_late;
 795         }
 796
 797         hw->mac.autoneg = 1;
 798         hw->phy.autoneg_wait_to_complete = 0;
 799         hw->phy.autoneg_advertised = E1000_ALL_SPEED_DUPLEX;
 800
 801         /* Copper options */
 802         if (hw->phy.media_type == e1000_media_type_copper) {
 803                 hw->phy.mdix = 0; /* AUTO_ALL_MODES */
 804                 hw->phy.disable_polarity_correction = 0;
 805                 hw->phy.ms_type = e1000_ms_hw_default;
 806         }
 807
 808         /*
 809          * Start from a known state, this is important in reading the nvm
 810          * and mac from that.
 811          */
 812         igb_pf_reset_hw(hw);
 813
 814         /* Make sure we have a good EEPROM before we read from it */
 815         if (e1000_validate_nvm_checksum(hw) < 0) {
 816                 /*
 817                  * Some PCI-E parts fail the first check due to
 818                  * the link being in sleep state, call it again,
 819                  * if it fails a second time its a real issue.
 820                  */
 821                 if (e1000_validate_nvm_checksum(hw) < 0) {
 822                         PMD_INIT_LOG(ERR, "EEPROM checksum invalid");
 823                         error = -EIO;
 824                         goto err_late;
 825                 }
 826         }
 827
 828         /* Read the permanent MAC address out of the EEPROM */
 829         if (e1000_read_mac_addr(hw) != 0) {
 830                 PMD_INIT_LOG(ERR, "EEPROM error while reading MAC address");
 831                 error = -EIO;
 832                 goto err_late;
 833         }
 834
 835         /* Allocate memory for storing MAC addresses */
 836         eth_dev->data->mac_addrs = rte_zmalloc("e1000",
 837                 ETHER_ADDR_LEN * hw->mac.rar_entry_count, 0);
 838         if (eth_dev->data->mac_addrs == NULL) {
 839                 PMD_INIT_LOG(ERR, "Failed to allocate %d bytes needed to "
 840                                                 "store MAC addresses",
 841                                 ETHER_ADDR_LEN * hw->mac.rar_entry_count);
 842                 error = -ENOMEM;
 843                 goto err_late;
 844         }
 845
 846         /* Copy the permanent MAC address */
 847         ether_addr_copy((struct ether_addr *)hw->mac.addr, &eth_dev->data->mac_addrs[0]);
 848
 849         /* initialize the vfta */
 850         memset(shadow_vfta, 0, sizeof(*shadow_vfta));
 851
 852         /* Now initialize the hardware */
 853         if (igb_hardware_init(hw) != 0) {
 854                 PMD_INIT_LOG(ERR, "Hardware initialization failed");
 855                 rte_free(eth_dev->data->mac_addrs);
 856                 eth_dev->data->mac_addrs = NULL;
 857                 error = -ENODEV;
 858                 goto err_late;
 859         }
 860         hw->mac.get_link_status = 1;
 861         adapter->stopped = 0;
 862
 863         /* Indicate SOL/IDER usage */
 864         if (e1000_check_reset_block(hw) < 0) {
 865                 PMD_INIT_LOG(ERR, "PHY reset is blocked due to"
 866                                         "SOL/IDER session");
 867         }
 868
 869         /* initialize PF if max_vfs not zero */
 870         igb_pf_host_init(eth_dev);
 871
 872         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
 873         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
 874         ctrl_ext |= E1000_CTRL_EXT_PFRSTD;
 875         E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
 876         E1000_WRITE_FLUSH(hw);
 877
 878         PMD_INIT_LOG(DEBUG, "port_id %d vendorID=0x%x deviceID=0x%x",
 879                      eth_dev->data->port_id, pci_dev->id.vendor_id,
 880                      pci_dev->id.device_id);
 881
 882         rte_intr_callback_register(&pci_dev->intr_handle,
 883                                    eth_igb_interrupt_handler,
 884                                    (void *)eth_dev);
 885
 886         /* enable uio/vfio intr/eventfd mapping */
 887         rte_intr_enable(&pci_dev->intr_handle);
 888
 889         /* enable support intr */
 890         igb_intr_enable(eth_dev);
 891
 892         TAILQ_INIT(&filter_info->flex_list);
 893         filter_info->flex_mask = 0;
 894         TAILQ_INIT(&filter_info->twotuple_list);
 895         filter_info->twotuple_mask = 0;
 896         TAILQ_INIT(&filter_info->fivetuple_list);
 897         filter_info->fivetuple_mask = 0;
 898
 899         return 0;
 900
 901 err_late:
 902         igb_hw_control_release(hw);
 903
 904         return error;
 905 }
 906
 907 static int
 908 eth_igb_dev_uninit(struct rte_eth_dev *eth_dev)
 909 {
 910         struct rte_pci_device *pci_dev;
 911         struct e1000_hw *hw;
 912         struct e1000_adapter *adapter =
 913                 E1000_DEV_PRIVATE(eth_dev->data->dev_private);
 914
 915         PMD_INIT_FUNC_TRACE();
 916
 917         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
 918                 return -EPERM;
 919
 920         hw = E1000_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 921         pci_dev = eth_dev->pci_dev;
 922
 923         if (adapter->stopped == 0)
 924                 eth_igb_close(eth_dev);
 925
 926         eth_dev->dev_ops = NULL;
 927         eth_dev->rx_pkt_burst = NULL;
 928         eth_dev->tx_pkt_burst = NULL;
 929
 930         /* Reset any pending lock */
 931         igb_reset_swfw_lock(hw);
 932
 933         rte_free(eth_dev->data->mac_addrs);
 934         eth_dev->data->mac_addrs = NULL;
 935
 936         /* uninitialize PF if max_vfs not zero */
 937         igb_pf_host_uninit(eth_dev);
 938
 939         /* disable uio intr before callback unregister */
 940         rte_intr_disable(&(pci_dev->intr_handle));
 941         rte_intr_callback_unregister(&(pci_dev->intr_handle),
 942                 eth_igb_interrupt_handler, (void *)eth_dev);
 943
 944         return 0;
 945 }
 946
 947 /*
 948  * Virtual Function device init
 949  */
 950 static int
 951 eth_igbvf_dev_init(struct rte_eth_dev *eth_dev)
 952 {
 953         struct rte_pci_device *pci_dev;
 954         struct e1000_adapter *adapter =
 955                 E1000_DEV_PRIVATE(eth_dev->data->dev_private);
 956         struct e1000_hw *hw =
 957                 E1000_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 958         int diag;
 959         struct ether_addr *perm_addr = (struct ether_addr *)hw->mac.perm_addr;
 960
 961         PMD_INIT_FUNC_TRACE();
 962
 963         eth_dev->dev_ops = &igbvf_eth_dev_ops;
 964         eth_dev->rx_pkt_burst = &eth_igb_recv_pkts;
 965         eth_dev->tx_pkt_burst = &eth_igb_xmit_pkts;
 966
 967         /* for secondary processes, we don't initialise any further as primary
 968          * has already done this work. Only check we don't need a different
 969          * RX function */
 970         if (rte_eal_process_type() != RTE_PROC_PRIMARY){
 971                 if (eth_dev->data->scattered_rx)
 972                         eth_dev->rx_pkt_burst = &eth_igb_recv_scattered_pkts;
 973                 return 0;
 974         }
 975
 976         pci_dev = eth_dev->pci_dev;
 977
 978         rte_eth_copy_pci_info(eth_dev, pci_dev);
 979
 980         hw->device_id = pci_dev->id.device_id;
 981         hw->vendor_id = pci_dev->id.vendor_id;
 982         hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
 983         adapter->stopped = 0;
 984
 985         /* Initialize the shared code (base driver) */
 986         diag = e1000_setup_init_funcs(hw, TRUE);
 987         if (diag != 0) {
 988                 PMD_INIT_LOG(ERR, "Shared code init failed for igbvf: %d",
 989                         diag);
 990                 return -EIO;
 991         }
 992
 993         /* init_mailbox_params */
 994         hw->mbx.ops.init_params(hw);
 995
 996         /* Disable the interrupts for VF */
 997         igbvf_intr_disable(hw);
 998
 999         diag = hw->mac.ops.reset_hw(hw);
1000
1001         /* Allocate memory for storing MAC addresses */
1002         eth_dev->data->mac_addrs = rte_zmalloc("igbvf", ETHER_ADDR_LEN *
1003                 hw->mac.rar_entry_count, 0);
1004         if (eth_dev->data->mac_addrs == NULL) {
1005                 PMD_INIT_LOG(ERR,
1006                         "Failed to allocate %d bytes needed to store MAC "
1007                         "addresses",
1008                         ETHER_ADDR_LEN * hw->mac.rar_entry_count);
1009                 return -ENOMEM;
1010         }
1011
1012         /* Generate a random MAC address, if none was assigned by PF. */
1013         if (is_zero_ether_addr(perm_addr)) {
1014                 eth_random_addr(perm_addr->addr_bytes);
1015                 PMD_INIT_LOG(INFO, "\tVF MAC address not assigned by Host PF");
1016                 PMD_INIT_LOG(INFO, "\tAssign randomly generated MAC address "
1017                              "%02x:%02x:%02x:%02x:%02x:%02x",
1018                              perm_addr->addr_bytes[0],
1019                              perm_addr->addr_bytes[1],
1020                              perm_addr->addr_bytes[2],
1021                              perm_addr->addr_bytes[3],
1022                              perm_addr->addr_bytes[4],
1023                              perm_addr->addr_bytes[5]);
1024         }
1025
1026         diag = e1000_rar_set(hw, perm_addr->addr_bytes, 0);
1027         if (diag) {
1028                 rte_free(eth_dev->data->mac_addrs);
1029                 eth_dev->data->mac_addrs = NULL;
1030                 return diag;
1031         }
1032         /* Copy the permanent MAC address */
1033         ether_addr_copy((struct ether_addr *) hw->mac.perm_addr,
1034                         &eth_dev->data->mac_addrs[0]);
1035
1036         PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x "
1037                      "mac.type=%s",
1038                      eth_dev->data->port_id, pci_dev->id.vendor_id,
1039                      pci_dev->id.device_id, "igb_mac_82576_vf");
1040
1041         rte_intr_callback_register(&pci_dev->intr_handle,
1042                                    eth_igbvf_interrupt_handler,
1043                                    (void *)eth_dev);
1044
1045         return 0;
1046 }
1047
1048 static int
1049 eth_igbvf_dev_uninit(struct rte_eth_dev *eth_dev)
1050 {
1051         struct e1000_adapter *adapter =
1052                 E1000_DEV_PRIVATE(eth_dev->data->dev_private);
1053         struct rte_pci_device *pci_dev = eth_dev->pci_dev;
1054
1055         PMD_INIT_FUNC_TRACE();
1056
1057         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1058                 return -EPERM;
1059
1060         if (adapter->stopped == 0)
1061                 igbvf_dev_close(eth_dev);
1062
1063         eth_dev->dev_ops = NULL;
1064         eth_dev->rx_pkt_burst = NULL;
1065         eth_dev->tx_pkt_burst = NULL;
1066
1067         rte_free(eth_dev->data->mac_addrs);
1068         eth_dev->data->mac_addrs = NULL;
1069
1070         /* disable uio intr before callback unregister */
1071         rte_intr_disable(&pci_dev->intr_handle);
1072         rte_intr_callback_unregister(&pci_dev->intr_handle,
1073                                      eth_igbvf_interrupt_handler,
1074                                      (void *)eth_dev);
1075
1076         return 0;
1077 }
1078
1079 static struct eth_driver rte_igb_pmd = {
1080         .pci_drv = {
1081                 .id_table = pci_id_igb_map,
1082                 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC |
1083                         RTE_PCI_DRV_DETACHABLE,
1084                 .probe = rte_eth_dev_pci_probe,
1085                 .remove = rte_eth_dev_pci_remove,
1086         },
1087         .eth_dev_init = eth_igb_dev_init,
1088         .eth_dev_uninit = eth_igb_dev_uninit,
1089         .dev_private_size = sizeof(struct e1000_adapter),
1090 };
1091
1092 /*
1093  * virtual function driver struct
1094  */
1095 static struct eth_driver rte_igbvf_pmd = {
1096         .pci_drv = {
1097                 .id_table = pci_id_igbvf_map,
1098                 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_DETACHABLE,
1099                 .probe = rte_eth_dev_pci_probe,
1100                 .remove = rte_eth_dev_pci_remove,
1101         },
1102         .eth_dev_init = eth_igbvf_dev_init,
1103         .eth_dev_uninit = eth_igbvf_dev_uninit,
1104         .dev_private_size = sizeof(struct e1000_adapter),
1105 };
1106
1107 static void
1108 igb_vmdq_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1109 {
1110         struct e1000_hw *hw =
1111                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1112         /* RCTL: enable VLAN filter since VMDq always use VLAN filter */
1113         uint32_t rctl = E1000_READ_REG(hw, E1000_RCTL);
1114         rctl |= E1000_RCTL_VFE;
1115         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1116 }
1117
1118 static int
1119 igb_check_mq_mode(struct rte_eth_dev *dev)
1120 {
1121         enum rte_eth_rx_mq_mode rx_mq_mode = dev->data->dev_conf.rxmode.mq_mode;
1122         enum rte_eth_tx_mq_mode tx_mq_mode = dev->data->dev_conf.txmode.mq_mode;
1123         uint16_t nb_rx_q = dev->data->nb_rx_queues;
1124         uint16_t nb_tx_q = dev->data->nb_tx_queues;
1125
1126         if ((rx_mq_mode & ETH_MQ_RX_DCB_FLAG) ||
1127             tx_mq_mode == ETH_MQ_TX_DCB ||
1128             tx_mq_mode == ETH_MQ_TX_VMDQ_DCB) {
1129                 PMD_INIT_LOG(ERR, "DCB mode is not supported.");
1130                 return -EINVAL;
1131         }
1132         if (RTE_ETH_DEV_SRIOV(dev).active != 0) {
1133                 /* Check multi-queue mode.
1134                  * To no break software we accept ETH_MQ_RX_NONE as this might
1135                  * be used to turn off VLAN filter.
1136                  */
1137
1138                 if (rx_mq_mode == ETH_MQ_RX_NONE ||
1139                     rx_mq_mode == ETH_MQ_RX_VMDQ_ONLY) {
1140                         dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_ONLY;
1141                         RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool = 1;
1142                 } else {
1143                         /* Only support one queue on VFs.
1144                          * RSS together with SRIOV is not supported.
1145                          */
1146                         PMD_INIT_LOG(ERR, "SRIOV is active,"
1147                                         " wrong mq_mode rx %d.",
1148                                         rx_mq_mode);
1149                         return -EINVAL;
1150                 }
1151                 /* TX mode is not used here, so mode might be ignored.*/
1152                 if (tx_mq_mode != ETH_MQ_TX_VMDQ_ONLY) {
1153                         /* SRIOV only works in VMDq enable mode */
1154                         PMD_INIT_LOG(WARNING, "SRIOV is active,"
1155                                         " TX mode %d is not supported. "
1156                                         " Driver will behave as %d mode.",
1157                                         tx_mq_mode, ETH_MQ_TX_VMDQ_ONLY);
1158                 }
1159
1160                 /* check valid queue number */
1161                 if ((nb_rx_q > 1) || (nb_tx_q > 1)) {
1162                         PMD_INIT_LOG(ERR, "SRIOV is active,"
1163                                         " only support one queue on VFs.");
1164                         return -EINVAL;
1165                 }
1166         } else {
1167                 /* To no break software that set invalid mode, only display
1168                  * warning if invalid mode is used.
1169                  */
1170                 if (rx_mq_mode != ETH_MQ_RX_NONE &&
1171                     rx_mq_mode != ETH_MQ_RX_VMDQ_ONLY &&
1172                     rx_mq_mode != ETH_MQ_RX_RSS) {
1173                         /* RSS together with VMDq not supported*/
1174                         PMD_INIT_LOG(ERR, "RX mode %d is not supported.",
1175                                      rx_mq_mode);
1176                         return -EINVAL;
1177                 }
1178
1179                 if (tx_mq_mode != ETH_MQ_TX_NONE &&
1180                     tx_mq_mode != ETH_MQ_TX_VMDQ_ONLY) {
1181                         PMD_INIT_LOG(WARNING, "TX mode %d is not supported."
1182                                         " Due to txmode is meaningless in this"
1183                                         " driver, just ignore.",
1184                                         tx_mq_mode);
1185                 }
1186         }
1187         return 0;
1188 }
1189
1190 static int
1191 eth_igb_configure(struct rte_eth_dev *dev)
1192 {
1193         struct e1000_interrupt *intr =
1194                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
1195         int ret;
1196
1197         PMD_INIT_FUNC_TRACE();
1198
1199         /* multipe queue mode checking */
1200         ret  = igb_check_mq_mode(dev);
1201         if (ret != 0) {
1202                 PMD_DRV_LOG(ERR, "igb_check_mq_mode fails with %d.",
1203                             ret);
1204                 return ret;
1205         }
1206
1207         intr->flags |= E1000_FLAG_NEED_LINK_UPDATE;
1208         PMD_INIT_FUNC_TRACE();
1209
1210         return 0;
1211 }
1212
1213 static int
1214 eth_igb_start(struct rte_eth_dev *dev)
1215 {
1216         struct e1000_hw *hw =
1217                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1218         struct e1000_adapter *adapter =
1219                 E1000_DEV_PRIVATE(dev->data->dev_private);
1220         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
1221         int ret, mask;
1222         uint32_t intr_vector = 0;
1223         uint32_t ctrl_ext;
1224         uint32_t *speeds;
1225         int num_speeds;
1226         bool autoneg;
1227
1228         PMD_INIT_FUNC_TRACE();
1229
1230         /* disable uio/vfio intr/eventfd mapping */
1231         rte_intr_disable(intr_handle);
1232
1233         /* Power up the phy. Needed to make the link go Up */
1234         eth_igb_dev_set_link_up(dev);
1235
1236         /*
1237          * Packet Buffer Allocation (PBA)
1238          * Writing PBA sets the receive portion of the buffer
1239          * the remainder is used for the transmit buffer.
1240          */
1241         if (hw->mac.type == e1000_82575) {
1242                 uint32_t pba;
1243
1244                 pba = E1000_PBA_32K; /* 32K for Rx, 16K for Tx */
1245                 E1000_WRITE_REG(hw, E1000_PBA, pba);
1246         }
1247
1248         /* Put the address into the Receive Address Array */
1249         e1000_rar_set(hw, hw->mac.addr, 0);
1250
1251         /* Initialize the hardware */
1252         if (igb_hardware_init(hw)) {
1253                 PMD_INIT_LOG(ERR, "Unable to initialize the hardware");
1254                 return -EIO;
1255         }
1256         adapter->stopped = 0;
1257
1258         E1000_WRITE_REG(hw, E1000_VET, ETHER_TYPE_VLAN << 16 | ETHER_TYPE_VLAN);
1259
1260         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
1261         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
1262         ctrl_ext |= E1000_CTRL_EXT_PFRSTD;
1263         E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
1264         E1000_WRITE_FLUSH(hw);
1265
1266         /* configure PF module if SRIOV enabled */
1267         igb_pf_host_configure(dev);
1268
1269         /* check and configure queue intr-vector mapping */
1270         if ((rte_intr_cap_multiple(intr_handle) ||
1271              !RTE_ETH_DEV_SRIOV(dev).active) &&
1272             dev->data->dev_conf.intr_conf.rxq != 0) {
1273                 intr_vector = dev->data->nb_rx_queues;
1274                 if (rte_intr_efd_enable(intr_handle, intr_vector))
1275                         return -1;
1276         }
1277
1278         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
1279                 intr_handle->intr_vec =
1280                         rte_zmalloc("intr_vec",
1281                                     dev->data->nb_rx_queues * sizeof(int), 0);
1282                 if (intr_handle->intr_vec == NULL) {
1283                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
1284                                      " intr_vec\n", dev->data->nb_rx_queues);
1285                         return -ENOMEM;
1286                 }
1287         }
1288
1289         /* confiugre msix for rx interrupt */
1290         eth_igb_configure_msix_intr(dev);
1291
1292         /* Configure for OS presence */
1293         igb_init_manageability(hw);
1294
1295         eth_igb_tx_init(dev);
1296
1297         /* This can fail when allocating mbufs for descriptor rings */
1298         ret = eth_igb_rx_init(dev);
1299         if (ret) {
1300                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
1301                 igb_dev_clear_queues(dev);
1302                 return ret;
1303         }
1304
1305         e1000_clear_hw_cntrs_base_generic(hw);
1306
1307         /*
1308          * VLAN Offload Settings
1309          */
1310         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK | \
1311                         ETH_VLAN_EXTEND_MASK;
1312         eth_igb_vlan_offload_set(dev, mask);
1313
1314         if (dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_VMDQ_ONLY) {
1315                 /* Enable VLAN filter since VMDq always use VLAN filter */
1316                 igb_vmdq_vlan_hw_filter_enable(dev);
1317         }
1318
1319         if ((hw->mac.type == e1000_82576) || (hw->mac.type == e1000_82580) ||
1320                 (hw->mac.type == e1000_i350) || (hw->mac.type == e1000_i210) ||
1321                 (hw->mac.type == e1000_i211)) {
1322                 /* Configure EITR with the maximum possible value (0xFFFF) */
1323                 E1000_WRITE_REG(hw, E1000_EITR(0), 0xFFFF);
1324         }
1325
1326         /* Setup link speed and duplex */
1327         speeds = &dev->data->dev_conf.link_speeds;
1328         if (*speeds == ETH_LINK_SPEED_AUTONEG) {
1329                 hw->phy.autoneg_advertised = E1000_ALL_SPEED_DUPLEX;
1330                 hw->mac.autoneg = 1;
1331         } else {
1332                 num_speeds = 0;
1333                 autoneg = (*speeds & ETH_LINK_SPEED_FIXED) == 0;
1334
1335                 /* Reset */
1336                 hw->phy.autoneg_advertised = 0;
1337
1338                 if (*speeds & ~(ETH_LINK_SPEED_10M_HD | ETH_LINK_SPEED_10M |
1339                                 ETH_LINK_SPEED_100M_HD | ETH_LINK_SPEED_100M |
1340                                 ETH_LINK_SPEED_1G | ETH_LINK_SPEED_FIXED)) {
1341                         num_speeds = -1;
1342                         goto error_invalid_config;
1343                 }
1344                 if (*speeds & ETH_LINK_SPEED_10M_HD) {
1345                         hw->phy.autoneg_advertised |= ADVERTISE_10_HALF;
1346                         num_speeds++;
1347                 }
1348                 if (*speeds & ETH_LINK_SPEED_10M) {
1349                         hw->phy.autoneg_advertised |= ADVERTISE_10_FULL;
1350                         num_speeds++;
1351                 }
1352                 if (*speeds & ETH_LINK_SPEED_100M_HD) {
1353                         hw->phy.autoneg_advertised |= ADVERTISE_100_HALF;
1354                         num_speeds++;
1355                 }
1356                 if (*speeds & ETH_LINK_SPEED_100M) {
1357                         hw->phy.autoneg_advertised |= ADVERTISE_100_FULL;
1358                         num_speeds++;
1359                 }
1360                 if (*speeds & ETH_LINK_SPEED_1G) {
1361                         hw->phy.autoneg_advertised |= ADVERTISE_1000_FULL;
1362                         num_speeds++;
1363                 }
1364                 if (num_speeds == 0 || (!autoneg && (num_speeds > 1)))
1365                         goto error_invalid_config;
1366
1367                 /* Set/reset the mac.autoneg based on the link speed,
1368                  * fixed or not
1369                  */
1370                 if (!autoneg) {
1371                         hw->mac.autoneg = 0;
1372                         hw->mac.forced_speed_duplex =
1373                                         hw->phy.autoneg_advertised;
1374                 } else {
1375                         hw->mac.autoneg = 1;
1376                 }
1377         }
1378
1379         e1000_setup_link(hw);
1380
1381         if (rte_intr_allow_others(intr_handle)) {
1382                 /* check if lsc interrupt is enabled */
1383                 if (dev->data->dev_conf.intr_conf.lsc != 0)
1384                         eth_igb_lsc_interrupt_setup(dev, TRUE);
1385                 else
1386                         eth_igb_lsc_interrupt_setup(dev, FALSE);
1387         } else {
1388                 rte_intr_callback_unregister(intr_handle,
1389                                              eth_igb_interrupt_handler,
1390                                              (void *)dev);
1391                 if (dev->data->dev_conf.intr_conf.lsc != 0)
1392                         PMD_INIT_LOG(INFO, "lsc won't enable because of"
1393                                      " no intr multiplex\n");
1394         }
1395
1396         /* check if rxq interrupt is enabled */
1397         if (dev->data->dev_conf.intr_conf.rxq != 0 &&
1398             rte_intr_dp_is_en(intr_handle))
1399                 eth_igb_rxq_interrupt_setup(dev);
1400
1401         /* enable uio/vfio intr/eventfd mapping */
1402         rte_intr_enable(intr_handle);
1403
1404         /* resume enabled intr since hw reset */
1405         igb_intr_enable(dev);
1406
1407         PMD_INIT_LOG(DEBUG, "<<");
1408
1409         return 0;
1410
1411 error_invalid_config:
1412         PMD_INIT_LOG(ERR, "Invalid advertised speeds (%u) for port %u",
1413                      dev->data->dev_conf.link_speeds, dev->data->port_id);
1414         igb_dev_clear_queues(dev);
1415         return -EINVAL;
1416 }
1417
1418 /*********************************************************************
1419  *
1420  *  This routine disables all traffic on the adapter by issuing a
1421  *  global reset on the MAC.
1422  *
1423  **********************************************************************/
1424 static void
1425 eth_igb_stop(struct rte_eth_dev *dev)
1426 {
1427         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1428         struct e1000_filter_info *filter_info =
1429                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
1430         struct rte_eth_link link;
1431         struct e1000_flex_filter *p_flex;
1432         struct e1000_5tuple_filter *p_5tuple, *p_5tuple_next;
1433         struct e1000_2tuple_filter *p_2tuple, *p_2tuple_next;
1434         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
1435
1436         igb_intr_disable(hw);
1437
1438         /* disable intr eventfd mapping */
1439         rte_intr_disable(intr_handle);
1440
1441         igb_pf_reset_hw(hw);
1442         E1000_WRITE_REG(hw, E1000_WUC, 0);
1443
1444         /* Set bit for Go Link disconnect */
1445         if (hw->mac.type >= e1000_82580) {
1446                 uint32_t phpm_reg;
1447
1448                 phpm_reg = E1000_READ_REG(hw, E1000_82580_PHY_POWER_MGMT);
1449                 phpm_reg |= E1000_82580_PM_GO_LINKD;
1450                 E1000_WRITE_REG(hw, E1000_82580_PHY_POWER_MGMT, phpm_reg);
1451         }
1452
1453         /* Power down the phy. Needed to make the link go Down */
1454         eth_igb_dev_set_link_down(dev);
1455
1456         igb_dev_clear_queues(dev);
1457
1458         /* clear the recorded link status */
1459         memset(&link, 0, sizeof(link));
1460         rte_igb_dev_atomic_write_link_status(dev, &link);
1461
1462         /* Remove all flex filters of the device */
1463         while ((p_flex = TAILQ_FIRST(&filter_info->flex_list))) {
1464                 TAILQ_REMOVE(&filter_info->flex_list, p_flex, entries);
1465                 rte_free(p_flex);
1466         }
1467         filter_info->flex_mask = 0;
1468
1469         /* Remove all ntuple filters of the device */
1470         for (p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list);
1471              p_5tuple != NULL; p_5tuple = p_5tuple_next) {
1472                 p_5tuple_next = TAILQ_NEXT(p_5tuple, entries);
1473                 TAILQ_REMOVE(&filter_info->fivetuple_list,
1474                              p_5tuple, entries);
1475                 rte_free(p_5tuple);
1476         }
1477         filter_info->fivetuple_mask = 0;
1478         for (p_2tuple = TAILQ_FIRST(&filter_info->twotuple_list);
1479              p_2tuple != NULL; p_2tuple = p_2tuple_next) {
1480                 p_2tuple_next = TAILQ_NEXT(p_2tuple, entries);
1481                 TAILQ_REMOVE(&filter_info->twotuple_list,
1482                              p_2tuple, entries);
1483                 rte_free(p_2tuple);
1484         }
1485         filter_info->twotuple_mask = 0;
1486
1487         if (!rte_intr_allow_others(intr_handle))
1488                 /* resume to the default handler */
1489                 rte_intr_callback_register(intr_handle,
1490                                            eth_igb_interrupt_handler,
1491                                            (void *)dev);
1492
1493         /* Clean datapath event and queue/vec mapping */
1494         rte_intr_efd_disable(intr_handle);
1495         if (intr_handle->intr_vec != NULL) {
1496                 rte_free(intr_handle->intr_vec);
1497                 intr_handle->intr_vec = NULL;
1498         }
1499 }
1500
1501 static int
1502 eth_igb_dev_set_link_up(struct rte_eth_dev *dev)
1503 {
1504         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1505
1506         if (hw->phy.media_type == e1000_media_type_copper)
1507                 e1000_power_up_phy(hw);
1508         else
1509                 e1000_power_up_fiber_serdes_link(hw);
1510
1511         return 0;
1512 }
1513
1514 static int
1515 eth_igb_dev_set_link_down(struct rte_eth_dev *dev)
1516 {
1517         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1518
1519         if (hw->phy.media_type == e1000_media_type_copper)
1520                 e1000_power_down_phy(hw);
1521         else
1522                 e1000_shutdown_fiber_serdes_link(hw);
1523
1524         return 0;
1525 }
1526
1527 static void
1528 eth_igb_close(struct rte_eth_dev *dev)
1529 {
1530         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1531         struct e1000_adapter *adapter =
1532                 E1000_DEV_PRIVATE(dev->data->dev_private);
1533         struct rte_eth_link link;
1534         struct rte_pci_device *pci_dev;
1535
1536         eth_igb_stop(dev);
1537         adapter->stopped = 1;
1538
1539         e1000_phy_hw_reset(hw);
1540         igb_release_manageability(hw);
1541         igb_hw_control_release(hw);
1542
1543         /* Clear bit for Go Link disconnect */
1544         if (hw->mac.type >= e1000_82580) {
1545                 uint32_t phpm_reg;
1546
1547                 phpm_reg = E1000_READ_REG(hw, E1000_82580_PHY_POWER_MGMT);
1548                 phpm_reg &= ~E1000_82580_PM_GO_LINKD;
1549                 E1000_WRITE_REG(hw, E1000_82580_PHY_POWER_MGMT, phpm_reg);
1550         }
1551
1552         igb_dev_free_queues(dev);
1553
1554         pci_dev = dev->pci_dev;
1555         if (pci_dev->intr_handle.intr_vec) {
1556                 rte_free(pci_dev->intr_handle.intr_vec);
1557                 pci_dev->intr_handle.intr_vec = NULL;
1558         }
1559
1560         memset(&link, 0, sizeof(link));
1561         rte_igb_dev_atomic_write_link_status(dev, &link);
1562 }
1563
1564 static int
1565 igb_get_rx_buffer_size(struct e1000_hw *hw)
1566 {
1567         uint32_t rx_buf_size;
1568         if (hw->mac.type == e1000_82576) {
1569                 rx_buf_size = (E1000_READ_REG(hw, E1000_RXPBS) & 0xffff) << 10;
1570         } else if (hw->mac.type == e1000_82580 || hw->mac.type == e1000_i350) {
1571                 /* PBS needs to be translated according to a lookup table */
1572                 rx_buf_size = (E1000_READ_REG(hw, E1000_RXPBS) & 0xf);
1573                 rx_buf_size = (uint32_t) e1000_rxpbs_adjust_82580(rx_buf_size);
1574                 rx_buf_size = (rx_buf_size << 10);
1575         } else if (hw->mac.type == e1000_i210 || hw->mac.type == e1000_i211) {
1576                 rx_buf_size = (E1000_READ_REG(hw, E1000_RXPBS) & 0x3f) << 10;
1577         } else {
1578                 rx_buf_size = (E1000_READ_REG(hw, E1000_PBA) & 0xffff) << 10;
1579         }
1580
1581         return rx_buf_size;
1582 }
1583
1584 /*********************************************************************
1585  *
1586  *  Initialize the hardware
1587  *
1588  **********************************************************************/
1589 static int
1590 igb_hardware_init(struct e1000_hw *hw)
1591 {
1592         uint32_t rx_buf_size;
1593         int diag;
1594
1595         /* Let the firmware know the OS is in control */
1596         igb_hw_control_acquire(hw);
1597
1598         /*
1599          * These parameters control the automatic generation (Tx) and
1600          * response (Rx) to Ethernet PAUSE frames.
1601          * - High water mark should allow for at least two standard size (1518)
1602          *   frames to be received after sending an XOFF.
1603          * - Low water mark works best when it is very near the high water mark.
1604          *   This allows the receiver to restart by sending XON when it has
1605          *   drained a bit. Here we use an arbitrary value of 1500 which will
1606          *   restart after one full frame is pulled from the buffer. There
1607          *   could be several smaller frames in the buffer and if so they will
1608          *   not trigger the XON until their total number reduces the buffer
1609          *   by 1500.
1610          * - The pause time is fairly large at 1000 x 512ns = 512 usec.
1611          */
1612         rx_buf_size = igb_get_rx_buffer_size(hw);
1613
1614         hw->fc.high_water = rx_buf_size - (ETHER_MAX_LEN * 2);
1615         hw->fc.low_water = hw->fc.high_water - 1500;
1616         hw->fc.pause_time = IGB_FC_PAUSE_TIME;
1617         hw->fc.send_xon = 1;
1618
1619         /* Set Flow control, use the tunable location if sane */
1620         if ((igb_fc_setting != e1000_fc_none) && (igb_fc_setting < 4))
1621                 hw->fc.requested_mode = igb_fc_setting;
1622         else
1623                 hw->fc.requested_mode = e1000_fc_none;
1624
1625         /* Issue a global reset */
1626         igb_pf_reset_hw(hw);
1627         E1000_WRITE_REG(hw, E1000_WUC, 0);
1628
1629         diag = e1000_init_hw(hw);
1630         if (diag < 0)
1631                 return diag;
1632
1633         E1000_WRITE_REG(hw, E1000_VET, ETHER_TYPE_VLAN << 16 | ETHER_TYPE_VLAN);
1634         e1000_get_phy_info(hw);
1635         e1000_check_for_link(hw);
1636
1637         return 0;
1638 }
1639
1640 /* This function is based on igb_update_stats_counters() in igb/if_igb.c */
1641 static void
1642 igb_read_stats_registers(struct e1000_hw *hw, struct e1000_hw_stats *stats)
1643 {
1644         int pause_frames;
1645
1646         uint64_t old_gprc  = stats->gprc;
1647         uint64_t old_gptc  = stats->gptc;
1648         uint64_t old_tpr   = stats->tpr;
1649         uint64_t old_tpt   = stats->tpt;
1650         uint64_t old_rpthc = stats->rpthc;
1651         uint64_t old_hgptc = stats->hgptc;
1652
1653         if(hw->phy.media_type == e1000_media_type_copper ||
1654             (E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU)) {
1655                 stats->symerrs +=
1656                     E1000_READ_REG(hw,E1000_SYMERRS);
1657                 stats->sec += E1000_READ_REG(hw, E1000_SEC);
1658         }
1659
1660         stats->crcerrs += E1000_READ_REG(hw, E1000_CRCERRS);
1661         stats->mpc += E1000_READ_REG(hw, E1000_MPC);
1662         stats->scc += E1000_READ_REG(hw, E1000_SCC);
1663         stats->ecol += E1000_READ_REG(hw, E1000_ECOL);
1664
1665         stats->mcc += E1000_READ_REG(hw, E1000_MCC);
1666         stats->latecol += E1000_READ_REG(hw, E1000_LATECOL);
1667         stats->colc += E1000_READ_REG(hw, E1000_COLC);
1668         stats->dc += E1000_READ_REG(hw, E1000_DC);
1669         stats->rlec += E1000_READ_REG(hw, E1000_RLEC);
1670         stats->xonrxc += E1000_READ_REG(hw, E1000_XONRXC);
1671         stats->xontxc += E1000_READ_REG(hw, E1000_XONTXC);
1672         /*
1673         ** For watchdog management we need to know if we have been
1674         ** paused during the last interval, so capture that here.
1675         */
1676         pause_frames = E1000_READ_REG(hw, E1000_XOFFRXC);
1677         stats->xoffrxc += pause_frames;
1678         stats->xofftxc += E1000_READ_REG(hw, E1000_XOFFTXC);
1679         stats->fcruc += E1000_READ_REG(hw, E1000_FCRUC);
1680         stats->prc64 += E1000_READ_REG(hw, E1000_PRC64);
1681         stats->prc127 += E1000_READ_REG(hw, E1000_PRC127);
1682         stats->prc255 += E1000_READ_REG(hw, E1000_PRC255);
1683         stats->prc511 += E1000_READ_REG(hw, E1000_PRC511);
1684         stats->prc1023 += E1000_READ_REG(hw, E1000_PRC1023);
1685         stats->prc1522 += E1000_READ_REG(hw, E1000_PRC1522);
1686         stats->gprc += E1000_READ_REG(hw, E1000_GPRC);
1687         stats->bprc += E1000_READ_REG(hw, E1000_BPRC);
1688         stats->mprc += E1000_READ_REG(hw, E1000_MPRC);
1689         stats->gptc += E1000_READ_REG(hw, E1000_GPTC);
1690
1691         /* For the 64-bit byte counters the low dword must be read first. */
1692         /* Both registers clear on the read of the high dword */
1693
1694         /* Workaround CRC bytes included in size, take away 4 bytes/packet */
1695         stats->gorc += E1000_READ_REG(hw, E1000_GORCL);
1696         stats->gorc += ((uint64_t)E1000_READ_REG(hw, E1000_GORCH) << 32);
1697         stats->gorc -= (stats->gprc - old_gprc) * ETHER_CRC_LEN;
1698         stats->gotc += E1000_READ_REG(hw, E1000_GOTCL);
1699         stats->gotc += ((uint64_t)E1000_READ_REG(hw, E1000_GOTCH) << 32);
1700         stats->gotc -= (stats->gptc - old_gptc) * ETHER_CRC_LEN;
1701
1702         stats->rnbc += E1000_READ_REG(hw, E1000_RNBC);
1703         stats->ruc += E1000_READ_REG(hw, E1000_RUC);
1704         stats->rfc += E1000_READ_REG(hw, E1000_RFC);
1705         stats->roc += E1000_READ_REG(hw, E1000_ROC);
1706         stats->rjc += E1000_READ_REG(hw, E1000_RJC);
1707
1708         stats->tpr += E1000_READ_REG(hw, E1000_TPR);
1709         stats->tpt += E1000_READ_REG(hw, E1000_TPT);
1710
1711         stats->tor += E1000_READ_REG(hw, E1000_TORL);
1712         stats->tor += ((uint64_t)E1000_READ_REG(hw, E1000_TORH) << 32);
1713         stats->tor -= (stats->tpr - old_tpr) * ETHER_CRC_LEN;
1714         stats->tot += E1000_READ_REG(hw, E1000_TOTL);
1715         stats->tot += ((uint64_t)E1000_READ_REG(hw, E1000_TOTH) << 32);
1716         stats->tot -= (stats->tpt - old_tpt) * ETHER_CRC_LEN;
1717
1718         stats->ptc64 += E1000_READ_REG(hw, E1000_PTC64);
1719         stats->ptc127 += E1000_READ_REG(hw, E1000_PTC127);
1720         stats->ptc255 += E1000_READ_REG(hw, E1000_PTC255);
1721         stats->ptc511 += E1000_READ_REG(hw, E1000_PTC511);
1722         stats->ptc1023 += E1000_READ_REG(hw, E1000_PTC1023);
1723         stats->ptc1522 += E1000_READ_REG(hw, E1000_PTC1522);
1724         stats->mptc += E1000_READ_REG(hw, E1000_MPTC);
1725         stats->bptc += E1000_READ_REG(hw, E1000_BPTC);
1726
1727         /* Interrupt Counts */
1728
1729         stats->iac += E1000_READ_REG(hw, E1000_IAC);
1730         stats->icrxptc += E1000_READ_REG(hw, E1000_ICRXPTC);
1731         stats->icrxatc += E1000_READ_REG(hw, E1000_ICRXATC);
1732         stats->ictxptc += E1000_READ_REG(hw, E1000_ICTXPTC);
1733         stats->ictxatc += E1000_READ_REG(hw, E1000_ICTXATC);
1734         stats->ictxqec += E1000_READ_REG(hw, E1000_ICTXQEC);
1735         stats->ictxqmtc += E1000_READ_REG(hw, E1000_ICTXQMTC);
1736         stats->icrxdmtc += E1000_READ_REG(hw, E1000_ICRXDMTC);
1737         stats->icrxoc += E1000_READ_REG(hw, E1000_ICRXOC);
1738
1739         /* Host to Card Statistics */
1740
1741         stats->cbtmpc += E1000_READ_REG(hw, E1000_CBTMPC);
1742         stats->htdpmc += E1000_READ_REG(hw, E1000_HTDPMC);
1743         stats->cbrdpc += E1000_READ_REG(hw, E1000_CBRDPC);
1744         stats->cbrmpc += E1000_READ_REG(hw, E1000_CBRMPC);
1745         stats->rpthc += E1000_READ_REG(hw, E1000_RPTHC);
1746         stats->hgptc += E1000_READ_REG(hw, E1000_HGPTC);
1747         stats->htcbdpc += E1000_READ_REG(hw, E1000_HTCBDPC);
1748         stats->hgorc += E1000_READ_REG(hw, E1000_HGORCL);
1749         stats->hgorc += ((uint64_t)E1000_READ_REG(hw, E1000_HGORCH) << 32);
1750         stats->hgorc -= (stats->rpthc - old_rpthc) * ETHER_CRC_LEN;
1751         stats->hgotc += E1000_READ_REG(hw, E1000_HGOTCL);
1752         stats->hgotc += ((uint64_t)E1000_READ_REG(hw, E1000_HGOTCH) << 32);
1753         stats->hgotc -= (stats->hgptc - old_hgptc) * ETHER_CRC_LEN;
1754         stats->lenerrs += E1000_READ_REG(hw, E1000_LENERRS);
1755         stats->scvpc += E1000_READ_REG(hw, E1000_SCVPC);
1756         stats->hrmpc += E1000_READ_REG(hw, E1000_HRMPC);
1757
1758         stats->algnerrc += E1000_READ_REG(hw, E1000_ALGNERRC);
1759         stats->rxerrc += E1000_READ_REG(hw, E1000_RXERRC);
1760         stats->tncrs += E1000_READ_REG(hw, E1000_TNCRS);
1761         stats->cexterr += E1000_READ_REG(hw, E1000_CEXTERR);
1762         stats->tsctc += E1000_READ_REG(hw, E1000_TSCTC);
1763         stats->tsctfc += E1000_READ_REG(hw, E1000_TSCTFC);
1764 }
1765
1766 static void
1767 eth_igb_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *rte_stats)
1768 {
1769         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1770         struct e1000_hw_stats *stats =
1771                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1772
1773         igb_read_stats_registers(hw, stats);
1774
1775         if (rte_stats == NULL)
1776                 return;
1777
1778         /* Rx Errors */
1779         rte_stats->imissed = stats->mpc;
1780         rte_stats->ierrors = stats->crcerrs +
1781                              stats->rlec + stats->ruc + stats->roc +
1782                              stats->rxerrc + stats->algnerrc + stats->cexterr;
1783
1784         /* Tx Errors */
1785         rte_stats->oerrors = stats->ecol + stats->latecol;
1786
1787         rte_stats->ipackets = stats->gprc;
1788         rte_stats->opackets = stats->gptc;
1789         rte_stats->ibytes   = stats->gorc;
1790         rte_stats->obytes   = stats->gotc;
1791 }
1792
1793 static void
1794 eth_igb_stats_reset(struct rte_eth_dev *dev)
1795 {
1796         struct e1000_hw_stats *hw_stats =
1797                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1798
1799         /* HW registers are cleared on read */
1800         eth_igb_stats_get(dev, NULL);
1801
1802         /* Reset software totals */
1803         memset(hw_stats, 0, sizeof(*hw_stats));
1804 }
1805
1806 static void
1807 eth_igb_xstats_reset(struct rte_eth_dev *dev)
1808 {
1809         struct e1000_hw_stats *stats =
1810                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1811
1812         /* HW registers are cleared on read */
1813         eth_igb_xstats_get(dev, NULL, IGB_NB_XSTATS);
1814
1815         /* Reset software totals */
1816         memset(stats, 0, sizeof(*stats));
1817 }
1818
1819 static int eth_igb_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
1820         struct rte_eth_xstat_name *xstats_names,
1821         __rte_unused unsigned limit)
1822 {
1823         unsigned i;
1824
1825         if (xstats_names == NULL)
1826                 return IGB_NB_XSTATS;
1827
1828         /* Note: limit checked in rte_eth_xstats_names() */
1829
1830         for (i = 0; i < IGB_NB_XSTATS; i++) {
1831                 snprintf(xstats_names[i].name, sizeof(xstats_names[i].name),
1832                          "%s", rte_igb_stats_strings[i].name);
1833         }
1834
1835         return IGB_NB_XSTATS;
1836 }
1837
1838 static int
1839 eth_igb_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
1840                    unsigned n)
1841 {
1842         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1843         struct e1000_hw_stats *hw_stats =
1844                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1845         unsigned i;
1846
1847         if (n < IGB_NB_XSTATS)
1848                 return IGB_NB_XSTATS;
1849
1850         igb_read_stats_registers(hw, hw_stats);
1851
1852         /* If this is a reset xstats is NULL, and we have cleared the
1853          * registers by reading them.
1854          */
1855         if (!xstats)
1856                 return 0;
1857
1858         /* Extended stats */
1859         for (i = 0; i < IGB_NB_XSTATS; i++) {
1860                 xstats[i].id = i;
1861                 xstats[i].value = *(uint64_t *)(((char *)hw_stats) +
1862                         rte_igb_stats_strings[i].offset);
1863         }
1864
1865         return IGB_NB_XSTATS;
1866 }
1867
1868 static void
1869 igbvf_read_stats_registers(struct e1000_hw *hw, struct e1000_vf_stats *hw_stats)
1870 {
1871         /* Good Rx packets, include VF loopback */
1872         UPDATE_VF_STAT(E1000_VFGPRC,
1873             hw_stats->last_gprc, hw_stats->gprc);
1874
1875         /* Good Rx octets, include VF loopback */
1876         UPDATE_VF_STAT(E1000_VFGORC,
1877             hw_stats->last_gorc, hw_stats->gorc);
1878
1879         /* Good Tx packets, include VF loopback */
1880         UPDATE_VF_STAT(E1000_VFGPTC,
1881             hw_stats->last_gptc, hw_stats->gptc);
1882
1883         /* Good Tx octets, include VF loopback */
1884         UPDATE_VF_STAT(E1000_VFGOTC,
1885             hw_stats->last_gotc, hw_stats->gotc);
1886
1887         /* Rx Multicst packets */
1888         UPDATE_VF_STAT(E1000_VFMPRC,
1889             hw_stats->last_mprc, hw_stats->mprc);
1890
1891         /* Good Rx loopback packets */
1892         UPDATE_VF_STAT(E1000_VFGPRLBC,
1893             hw_stats->last_gprlbc, hw_stats->gprlbc);
1894
1895         /* Good Rx loopback octets */
1896         UPDATE_VF_STAT(E1000_VFGORLBC,
1897             hw_stats->last_gorlbc, hw_stats->gorlbc);
1898
1899         /* Good Tx loopback packets */
1900         UPDATE_VF_STAT(E1000_VFGPTLBC,
1901             hw_stats->last_gptlbc, hw_stats->gptlbc);
1902
1903         /* Good Tx loopback octets */
1904         UPDATE_VF_STAT(E1000_VFGOTLBC,
1905             hw_stats->last_gotlbc, hw_stats->gotlbc);
1906 }
1907
1908 static int eth_igbvf_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
1909                                      struct rte_eth_xstat_name *xstats_names,
1910                                      __rte_unused unsigned limit)
1911 {
1912         unsigned i;
1913
1914         if (xstats_names != NULL)
1915                 for (i = 0; i < IGBVF_NB_XSTATS; i++) {
1916                         snprintf(xstats_names[i].name,
1917                                 sizeof(xstats_names[i].name), "%s",
1918                                 rte_igbvf_stats_strings[i].name);
1919                 }
1920         return IGBVF_NB_XSTATS;
1921 }
1922
1923 static int
1924 eth_igbvf_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
1925                      unsigned n)
1926 {
1927         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1928         struct e1000_vf_stats *hw_stats = (struct e1000_vf_stats *)
1929                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1930         unsigned i;
1931
1932         if (n < IGBVF_NB_XSTATS)
1933                 return IGBVF_NB_XSTATS;
1934
1935         igbvf_read_stats_registers(hw, hw_stats);
1936
1937         if (!xstats)
1938                 return 0;
1939
1940         for (i = 0; i < IGBVF_NB_XSTATS; i++) {
1941                 xstats[i].id = i;
1942                 xstats[i].value = *(uint64_t *)(((char *)hw_stats) +
1943                         rte_igbvf_stats_strings[i].offset);
1944         }
1945
1946         return IGBVF_NB_XSTATS;
1947 }
1948
1949 static void
1950 eth_igbvf_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *rte_stats)
1951 {
1952         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1953         struct e1000_vf_stats *hw_stats = (struct e1000_vf_stats *)
1954                           E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1955
1956         igbvf_read_stats_registers(hw, hw_stats);
1957
1958         if (rte_stats == NULL)
1959                 return;
1960
1961         rte_stats->ipackets = hw_stats->gprc;
1962         rte_stats->ibytes = hw_stats->gorc;
1963         rte_stats->opackets = hw_stats->gptc;
1964         rte_stats->obytes = hw_stats->gotc;
1965 }
1966
1967 static void
1968 eth_igbvf_stats_reset(struct rte_eth_dev *dev)
1969 {
1970         struct e1000_vf_stats *hw_stats = (struct e1000_vf_stats*)
1971                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1972
1973         /* Sync HW register to the last stats */
1974         eth_igbvf_stats_get(dev, NULL);
1975
1976         /* reset HW current stats*/
1977         memset(&hw_stats->gprc, 0, sizeof(*hw_stats) -
1978                offsetof(struct e1000_vf_stats, gprc));
1979 }
1980
1981 static void
1982 eth_igb_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
1983 {
1984         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1985
1986         dev_info->min_rx_bufsize = 256; /* See BSIZE field of RCTL register. */
1987         dev_info->max_rx_pktlen  = 0x3FFF; /* See RLPML register. */
1988         dev_info->max_mac_addrs = hw->mac.rar_entry_count;
1989         dev_info->rx_offload_capa =
1990                 DEV_RX_OFFLOAD_VLAN_STRIP |
1991                 DEV_RX_OFFLOAD_IPV4_CKSUM |
1992                 DEV_RX_OFFLOAD_UDP_CKSUM  |
1993                 DEV_RX_OFFLOAD_TCP_CKSUM;
1994         dev_info->tx_offload_capa =
1995                 DEV_TX_OFFLOAD_VLAN_INSERT |
1996                 DEV_TX_OFFLOAD_IPV4_CKSUM  |
1997                 DEV_TX_OFFLOAD_UDP_CKSUM   |
1998                 DEV_TX_OFFLOAD_TCP_CKSUM   |
1999                 DEV_TX_OFFLOAD_SCTP_CKSUM  |
2000                 DEV_TX_OFFLOAD_TCP_TSO;
2001
2002         switch (hw->mac.type) {
2003         case e1000_82575:
2004                 dev_info->max_rx_queues = 4;
2005                 dev_info->max_tx_queues = 4;
2006                 dev_info->max_vmdq_pools = 0;
2007                 break;
2008
2009         case e1000_82576:
2010                 dev_info->max_rx_queues = 16;
2011                 dev_info->max_tx_queues = 16;
2012                 dev_info->max_vmdq_pools = ETH_8_POOLS;
2013                 dev_info->vmdq_queue_num = 16;
2014                 break;
2015
2016         case e1000_82580:
2017                 dev_info->max_rx_queues = 8;
2018                 dev_info->max_tx_queues = 8;
2019                 dev_info->max_vmdq_pools = ETH_8_POOLS;
2020                 dev_info->vmdq_queue_num = 8;
2021                 break;
2022
2023         case e1000_i350:
2024                 dev_info->max_rx_queues = 8;
2025                 dev_info->max_tx_queues = 8;
2026                 dev_info->max_vmdq_pools = ETH_8_POOLS;
2027                 dev_info->vmdq_queue_num = 8;
2028                 break;
2029
2030         case e1000_i354:
2031                 dev_info->max_rx_queues = 8;
2032                 dev_info->max_tx_queues = 8;
2033                 break;
2034
2035         case e1000_i210:
2036                 dev_info->max_rx_queues = 4;
2037                 dev_info->max_tx_queues = 4;
2038                 dev_info->max_vmdq_pools = 0;
2039                 break;
2040
2041         case e1000_i211:
2042                 dev_info->max_rx_queues = 2;
2043                 dev_info->max_tx_queues = 2;
2044                 dev_info->max_vmdq_pools = 0;
2045                 break;
2046
2047         default:
2048                 /* Should not happen */
2049                 break;
2050         }
2051         dev_info->hash_key_size = IGB_HKEY_MAX_INDEX * sizeof(uint32_t);
2052         dev_info->reta_size = ETH_RSS_RETA_SIZE_128;
2053         dev_info->flow_type_rss_offloads = IGB_RSS_OFFLOAD_ALL;
2054
2055         dev_info->default_rxconf = (struct rte_eth_rxconf) {
2056                 .rx_thresh = {
2057                         .pthresh = IGB_DEFAULT_RX_PTHRESH,
2058                         .hthresh = IGB_DEFAULT_RX_HTHRESH,
2059                         .wthresh = IGB_DEFAULT_RX_WTHRESH,
2060                 },
2061                 .rx_free_thresh = IGB_DEFAULT_RX_FREE_THRESH,
2062                 .rx_drop_en = 0,
2063         };
2064
2065         dev_info->default_txconf = (struct rte_eth_txconf) {
2066                 .tx_thresh = {
2067                         .pthresh = IGB_DEFAULT_TX_PTHRESH,
2068                         .hthresh = IGB_DEFAULT_TX_HTHRESH,
2069                         .wthresh = IGB_DEFAULT_TX_WTHRESH,
2070                 },
2071                 .txq_flags = 0,
2072         };
2073
2074         dev_info->rx_desc_lim = rx_desc_lim;
2075         dev_info->tx_desc_lim = tx_desc_lim;
2076
2077         dev_info->speed_capa = ETH_LINK_SPEED_10M_HD | ETH_LINK_SPEED_10M |
2078                         ETH_LINK_SPEED_100M_HD | ETH_LINK_SPEED_100M |
2079                         ETH_LINK_SPEED_1G;
2080 }
2081
2082 static const uint32_t *
2083 eth_igb_supported_ptypes_get(struct rte_eth_dev *dev)
2084 {
2085         static const uint32_t ptypes[] = {
2086                 /* refers to igb_rxd_pkt_info_to_pkt_type() */
2087                 RTE_PTYPE_L2_ETHER,
2088                 RTE_PTYPE_L3_IPV4,
2089                 RTE_PTYPE_L3_IPV4_EXT,
2090                 RTE_PTYPE_L3_IPV6,
2091                 RTE_PTYPE_L3_IPV6_EXT,
2092                 RTE_PTYPE_L4_TCP,
2093                 RTE_PTYPE_L4_UDP,
2094                 RTE_PTYPE_L4_SCTP,
2095                 RTE_PTYPE_TUNNEL_IP,
2096                 RTE_PTYPE_INNER_L3_IPV6,
2097                 RTE_PTYPE_INNER_L3_IPV6_EXT,
2098                 RTE_PTYPE_INNER_L4_TCP,
2099                 RTE_PTYPE_INNER_L4_UDP,
2100                 RTE_PTYPE_UNKNOWN
2101         };
2102
2103         if (dev->rx_pkt_burst == eth_igb_recv_pkts ||
2104             dev->rx_pkt_burst == eth_igb_recv_scattered_pkts)
2105                 return ptypes;
2106         return NULL;
2107 }
2108
2109 static void
2110 eth_igbvf_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
2111 {
2112         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2113
2114         dev_info->min_rx_bufsize = 256; /* See BSIZE field of RCTL register. */
2115         dev_info->max_rx_pktlen  = 0x3FFF; /* See RLPML register. */
2116         dev_info->max_mac_addrs = hw->mac.rar_entry_count;
2117         dev_info->rx_offload_capa = DEV_RX_OFFLOAD_VLAN_STRIP |
2118                                 DEV_RX_OFFLOAD_IPV4_CKSUM |
2119                                 DEV_RX_OFFLOAD_UDP_CKSUM  |
2120                                 DEV_RX_OFFLOAD_TCP_CKSUM;
2121         dev_info->tx_offload_capa = DEV_TX_OFFLOAD_VLAN_INSERT |
2122                                 DEV_TX_OFFLOAD_IPV4_CKSUM  |
2123                                 DEV_TX_OFFLOAD_UDP_CKSUM   |
2124                                 DEV_TX_OFFLOAD_TCP_CKSUM   |
2125                                 DEV_TX_OFFLOAD_SCTP_CKSUM  |
2126                                 DEV_TX_OFFLOAD_TCP_TSO;
2127         switch (hw->mac.type) {
2128         case e1000_vfadapt:
2129                 dev_info->max_rx_queues = 2;
2130                 dev_info->max_tx_queues = 2;
2131                 break;
2132         case e1000_vfadapt_i350:
2133                 dev_info->max_rx_queues = 1;
2134                 dev_info->max_tx_queues = 1;
2135                 break;
2136         default:
2137                 /* Should not happen */
2138                 break;
2139         }
2140
2141         dev_info->default_rxconf = (struct rte_eth_rxconf) {
2142                 .rx_thresh = {
2143                         .pthresh = IGB_DEFAULT_RX_PTHRESH,
2144                         .hthresh = IGB_DEFAULT_RX_HTHRESH,
2145                         .wthresh = IGB_DEFAULT_RX_WTHRESH,
2146                 },
2147                 .rx_free_thresh = IGB_DEFAULT_RX_FREE_THRESH,
2148                 .rx_drop_en = 0,
2149         };
2150
2151         dev_info->default_txconf = (struct rte_eth_txconf) {
2152                 .tx_thresh = {
2153                         .pthresh = IGB_DEFAULT_TX_PTHRESH,
2154                         .hthresh = IGB_DEFAULT_TX_HTHRESH,
2155                         .wthresh = IGB_DEFAULT_TX_WTHRESH,
2156                 },
2157                 .txq_flags = 0,
2158         };
2159
2160         dev_info->rx_desc_lim = rx_desc_lim;
2161         dev_info->tx_desc_lim = tx_desc_lim;
2162 }
2163
2164 /* return 0 means link status changed, -1 means not changed */
2165 static int
2166 eth_igb_link_update(struct rte_eth_dev *dev, int wait_to_complete)
2167 {
2168         struct e1000_hw *hw =
2169                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2170         struct rte_eth_link link, old;
2171         int link_check, count;
2172
2173         link_check = 0;
2174         hw->mac.get_link_status = 1;
2175
2176         /* possible wait-to-complete in up to 9 seconds */
2177         for (count = 0; count < IGB_LINK_UPDATE_CHECK_TIMEOUT; count ++) {
2178                 /* Read the real link status */
2179                 switch (hw->phy.media_type) {
2180                 case e1000_media_type_copper:
2181                         /* Do the work to read phy */
2182                         e1000_check_for_link(hw);
2183                         link_check = !hw->mac.get_link_status;
2184                         break;
2185
2186                 case e1000_media_type_fiber:
2187                         e1000_check_for_link(hw);
2188                         link_check = (E1000_READ_REG(hw, E1000_STATUS) &
2189                                       E1000_STATUS_LU);
2190                         break;
2191
2192                 case e1000_media_type_internal_serdes:
2193                         e1000_check_for_link(hw);
2194                         link_check = hw->mac.serdes_has_link;
2195                         break;
2196
2197                 /* VF device is type_unknown */
2198                 case e1000_media_type_unknown:
2199                         eth_igbvf_link_update(hw);
2200                         link_check = !hw->mac.get_link_status;
2201                         break;
2202
2203                 default:
2204                         break;
2205                 }
2206                 if (link_check || wait_to_complete == 0)
2207                         break;
2208                 rte_delay_ms(IGB_LINK_UPDATE_CHECK_INTERVAL);
2209         }
2210         memset(&link, 0, sizeof(link));
2211         rte_igb_dev_atomic_read_link_status(dev, &link);
2212         old = link;
2213
2214         /* Now we check if a transition has happened */
2215         if (link_check) {
2216                 uint16_t duplex, speed;
2217                 hw->mac.ops.get_link_up_info(hw, &speed, &duplex);
2218                 link.link_duplex = (duplex == FULL_DUPLEX) ?
2219                                 ETH_LINK_FULL_DUPLEX :
2220                                 ETH_LINK_HALF_DUPLEX;
2221                 link.link_speed = speed;
2222                 link.link_status = ETH_LINK_UP;
2223                 link.link_autoneg = !(dev->data->dev_conf.link_speeds &
2224                                 ETH_LINK_SPEED_FIXED);
2225         } else if (!link_check) {
2226                 link.link_speed = 0;
2227                 link.link_duplex = ETH_LINK_HALF_DUPLEX;
2228                 link.link_status = ETH_LINK_DOWN;
2229                 link.link_autoneg = ETH_LINK_FIXED;
2230         }
2231         rte_igb_dev_atomic_write_link_status(dev, &link);
2232
2233         /* not changed */
2234         if (old.link_status == link.link_status)
2235                 return -1;
2236
2237         /* changed */
2238         return 0;
2239 }
2240
2241 /*
2242  * igb_hw_control_acquire sets CTRL_EXT:DRV_LOAD bit.
2243  * For ASF and Pass Through versions of f/w this means
2244  * that the driver is loaded.
2245  */
2246 static void
2247 igb_hw_control_acquire(struct e1000_hw *hw)
2248 {
2249         uint32_t ctrl_ext;
2250
2251         /* Let firmware know the driver has taken over */
2252         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
2253         E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
2254 }
2255
2256 /*
2257  * igb_hw_control_release resets CTRL_EXT:DRV_LOAD bit.
2258  * For ASF and Pass Through versions of f/w this means that the
2259  * driver is no longer loaded.
2260  */
2261 static void
2262 igb_hw_control_release(struct e1000_hw *hw)
2263 {
2264         uint32_t ctrl_ext;
2265
2266         /* Let firmware taken over control of h/w */
2267         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
2268         E1000_WRITE_REG(hw, E1000_CTRL_EXT,
2269                         ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
2270 }
2271
2272 /*
2273  * Bit of a misnomer, what this really means is
2274  * to enable OS management of the system... aka
2275  * to disable special hardware management features.
2276  */
2277 static void
2278 igb_init_manageability(struct e1000_hw *hw)
2279 {
2280         if (e1000_enable_mng_pass_thru(hw)) {
2281                 uint32_t manc2h = E1000_READ_REG(hw, E1000_MANC2H);
2282                 uint32_t manc = E1000_READ_REG(hw, E1000_MANC);
2283
2284                 /* disable hardware interception of ARP */
2285                 manc &= ~(E1000_MANC_ARP_EN);
2286
2287                 /* enable receiving management packets to the host */
2288                 manc |= E1000_MANC_EN_MNG2HOST;
2289                 manc2h |= 1 << 5;  /* Mng Port 623 */
2290                 manc2h |= 1 << 6;  /* Mng Port 664 */
2291                 E1000_WRITE_REG(hw, E1000_MANC2H, manc2h);
2292                 E1000_WRITE_REG(hw, E1000_MANC, manc);
2293         }
2294 }
2295
2296 static void
2297 igb_release_manageability(struct e1000_hw *hw)
2298 {
2299         if (e1000_enable_mng_pass_thru(hw)) {
2300                 uint32_t manc = E1000_READ_REG(hw, E1000_MANC);
2301
2302                 manc |= E1000_MANC_ARP_EN;
2303                 manc &= ~E1000_MANC_EN_MNG2HOST;
2304
2305                 E1000_WRITE_REG(hw, E1000_MANC, manc);
2306         }
2307 }
2308
2309 static void
2310 eth_igb_promiscuous_enable(struct rte_eth_dev *dev)
2311 {
2312         struct e1000_hw *hw =
2313                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2314         uint32_t rctl;
2315
2316         rctl = E1000_READ_REG(hw, E1000_RCTL);
2317         rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
2318         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2319 }
2320
2321 static void
2322 eth_igb_promiscuous_disable(struct rte_eth_dev *dev)
2323 {
2324         struct e1000_hw *hw =
2325                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2326         uint32_t rctl;
2327
2328         rctl = E1000_READ_REG(hw, E1000_RCTL);
2329         rctl &= (~E1000_RCTL_UPE);
2330         if (dev->data->all_multicast == 1)
2331                 rctl |= E1000_RCTL_MPE;
2332         else
2333                 rctl &= (~E1000_RCTL_MPE);
2334         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2335 }
2336
2337 static void
2338 eth_igb_allmulticast_enable(struct rte_eth_dev *dev)
2339 {
2340         struct e1000_hw *hw =
2341                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2342         uint32_t rctl;
2343
2344         rctl = E1000_READ_REG(hw, E1000_RCTL);
2345         rctl |= E1000_RCTL_MPE;
2346         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2347 }
2348
2349 static void
2350 eth_igb_allmulticast_disable(struct rte_eth_dev *dev)
2351 {
2352         struct e1000_hw *hw =
2353                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2354         uint32_t rctl;
2355
2356         if (dev->data->promiscuous == 1)
2357                 return; /* must remain in all_multicast mode */
2358         rctl = E1000_READ_REG(hw, E1000_RCTL);
2359         rctl &= (~E1000_RCTL_MPE);
2360         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2361 }
2362
2363 static int
2364 eth_igb_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
2365 {
2366         struct e1000_hw *hw =
2367                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2368         struct e1000_vfta * shadow_vfta =
2369                 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
2370         uint32_t vfta;
2371         uint32_t vid_idx;
2372         uint32_t vid_bit;
2373
2374         vid_idx = (uint32_t) ((vlan_id >> E1000_VFTA_ENTRY_SHIFT) &
2375                               E1000_VFTA_ENTRY_MASK);
2376         vid_bit = (uint32_t) (1 << (vlan_id & E1000_VFTA_ENTRY_BIT_SHIFT_MASK));
2377         vfta = E1000_READ_REG_ARRAY(hw, E1000_VFTA, vid_idx);
2378         if (on)
2379                 vfta |= vid_bit;
2380         else
2381                 vfta &= ~vid_bit;
2382         E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, vid_idx, vfta);
2383
2384         /* update local VFTA copy */
2385         shadow_vfta->vfta[vid_idx] = vfta;
2386
2387         return 0;
2388 }
2389
2390 static int
2391 eth_igb_vlan_tpid_set(struct rte_eth_dev *dev,
2392                       enum rte_vlan_type vlan_type,
2393                       uint16_t tpid)
2394 {
2395         struct e1000_hw *hw =
2396                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2397         uint32_t reg, qinq;
2398
2399         qinq = E1000_READ_REG(hw, E1000_CTRL_EXT);
2400         qinq &= E1000_CTRL_EXT_EXT_VLAN;
2401
2402         /* only outer TPID of double VLAN can be configured*/
2403         if (qinq && vlan_type == ETH_VLAN_TYPE_OUTER) {
2404                 reg = E1000_READ_REG(hw, E1000_VET);
2405                 reg = (reg & (~E1000_VET_VET_EXT)) |
2406                         ((uint32_t)tpid << E1000_VET_VET_EXT_SHIFT);
2407                 E1000_WRITE_REG(hw, E1000_VET, reg);
2408
2409                 return 0;
2410         }
2411
2412         /* all other TPID values are read-only*/
2413         PMD_DRV_LOG(ERR, "Not supported");
2414
2415         return -ENOTSUP;
2416 }
2417
2418 static void
2419 igb_vlan_hw_filter_disable(struct rte_eth_dev *dev)
2420 {
2421         struct e1000_hw *hw =
2422                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2423         uint32_t reg;
2424
2425         /* Filter Table Disable */
2426         reg = E1000_READ_REG(hw, E1000_RCTL);
2427         reg &= ~E1000_RCTL_CFIEN;
2428         reg &= ~E1000_RCTL_VFE;
2429         E1000_WRITE_REG(hw, E1000_RCTL, reg);
2430 }
2431
2432 static void
2433 igb_vlan_hw_filter_enable(struct rte_eth_dev *dev)
2434 {
2435         struct e1000_hw *hw =
2436                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2437         struct e1000_vfta * shadow_vfta =
2438                 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
2439         uint32_t reg;
2440         int i;
2441
2442         /* Filter Table Enable, CFI not used for packet acceptance */
2443         reg = E1000_READ_REG(hw, E1000_RCTL);
2444         reg &= ~E1000_RCTL_CFIEN;
2445         reg |= E1000_RCTL_VFE;
2446         E1000_WRITE_REG(hw, E1000_RCTL, reg);
2447
2448         /* restore VFTA table */
2449         for (i = 0; i < IGB_VFTA_SIZE; i++)
2450                 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, i, shadow_vfta->vfta[i]);
2451 }
2452
2453 static void
2454 igb_vlan_hw_strip_disable(struct rte_eth_dev *dev)
2455 {
2456         struct e1000_hw *hw =
2457                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2458         uint32_t reg;
2459
2460         /* VLAN Mode Disable */
2461         reg = E1000_READ_REG(hw, E1000_CTRL);
2462         reg &= ~E1000_CTRL_VME;
2463         E1000_WRITE_REG(hw, E1000_CTRL, reg);
2464 }
2465
2466 static void
2467 igb_vlan_hw_strip_enable(struct rte_eth_dev *dev)
2468 {
2469         struct e1000_hw *hw =
2470                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2471         uint32_t reg;
2472
2473         /* VLAN Mode Enable */
2474         reg = E1000_READ_REG(hw, E1000_CTRL);
2475         reg |= E1000_CTRL_VME;
2476         E1000_WRITE_REG(hw, E1000_CTRL, reg);
2477 }
2478
2479 static void
2480 igb_vlan_hw_extend_disable(struct rte_eth_dev *dev)
2481 {
2482         struct e1000_hw *hw =
2483                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2484         uint32_t reg;
2485
2486         /* CTRL_EXT: Extended VLAN */
2487         reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
2488         reg &= ~E1000_CTRL_EXT_EXTEND_VLAN;
2489         E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg);
2490
2491         /* Update maximum packet length */
2492         if (dev->data->dev_conf.rxmode.jumbo_frame == 1)
2493                 E1000_WRITE_REG(hw, E1000_RLPML,
2494                         dev->data->dev_conf.rxmode.max_rx_pkt_len +
2495                                                 VLAN_TAG_SIZE);
2496 }
2497
2498 static void
2499 igb_vlan_hw_extend_enable(struct rte_eth_dev *dev)
2500 {
2501         struct e1000_hw *hw =
2502                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2503         uint32_t reg;
2504
2505         /* CTRL_EXT: Extended VLAN */
2506         reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
2507         reg |= E1000_CTRL_EXT_EXTEND_VLAN;
2508         E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg);
2509
2510         /* Update maximum packet length */
2511         if (dev->data->dev_conf.rxmode.jumbo_frame == 1)
2512                 E1000_WRITE_REG(hw, E1000_RLPML,
2513                         dev->data->dev_conf.rxmode.max_rx_pkt_len +
2514                                                 2 * VLAN_TAG_SIZE);
2515 }
2516
2517 static void
2518 eth_igb_vlan_offload_set(struct rte_eth_dev *dev, int mask)
2519 {
2520         if(mask & ETH_VLAN_STRIP_MASK){
2521                 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
2522                         igb_vlan_hw_strip_enable(dev);
2523                 else
2524                         igb_vlan_hw_strip_disable(dev);
2525         }
2526
2527         if(mask & ETH_VLAN_FILTER_MASK){
2528                 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
2529                         igb_vlan_hw_filter_enable(dev);
2530                 else
2531                         igb_vlan_hw_filter_disable(dev);
2532         }
2533
2534         if(mask & ETH_VLAN_EXTEND_MASK){
2535                 if (dev->data->dev_conf.rxmode.hw_vlan_extend)
2536                         igb_vlan_hw_extend_enable(dev);
2537                 else
2538                         igb_vlan_hw_extend_disable(dev);
2539         }
2540 }
2541
2542
2543 /**
2544  * It enables the interrupt mask and then enable the interrupt.
2545  *
2546  * @param dev
2547  *  Pointer to struct rte_eth_dev.
2548  * @param on
2549  *  Enable or Disable
2550  *
2551  * @return
2552  *  - On success, zero.
2553  *  - On failure, a negative value.
2554  */
2555 static int
2556 eth_igb_lsc_interrupt_setup(struct rte_eth_dev *dev, uint8_t on)
2557 {
2558         struct e1000_interrupt *intr =
2559                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2560
2561         if (on)
2562                 intr->mask |= E1000_ICR_LSC;
2563         else
2564                 intr->mask &= ~E1000_ICR_LSC;
2565
2566         return 0;
2567 }
2568
2569 /* It clears the interrupt causes and enables the interrupt.
2570  * It will be called once only during nic initialized.
2571  *
2572  * @param dev
2573  *  Pointer to struct rte_eth_dev.
2574  *
2575  * @return
2576  *  - On success, zero.
2577  *  - On failure, a negative value.
2578  */
2579 static int eth_igb_rxq_interrupt_setup(struct rte_eth_dev *dev)
2580 {
2581         uint32_t mask, regval;
2582         struct e1000_hw *hw =
2583                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2584         struct rte_eth_dev_info dev_info;
2585
2586         memset(&dev_info, 0, sizeof(dev_info));
2587         eth_igb_infos_get(dev, &dev_info);
2588
2589         mask = 0xFFFFFFFF >> (32 - dev_info.max_rx_queues);
2590         regval = E1000_READ_REG(hw, E1000_EIMS);
2591         E1000_WRITE_REG(hw, E1000_EIMS, regval | mask);
2592
2593         return 0;
2594 }
2595
2596 /*
2597  * It reads ICR and gets interrupt causes, check it and set a bit flag
2598  * to update link status.
2599  *
2600  * @param dev
2601  *  Pointer to struct rte_eth_dev.
2602  *
2603  * @return
2604  *  - On success, zero.
2605  *  - On failure, a negative value.
2606  */
2607 static int
2608 eth_igb_interrupt_get_status(struct rte_eth_dev *dev)
2609 {
2610         uint32_t icr;
2611         struct e1000_hw *hw =
2612                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2613         struct e1000_interrupt *intr =
2614                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2615
2616         igb_intr_disable(hw);
2617
2618         /* read-on-clear nic registers here */
2619         icr = E1000_READ_REG(hw, E1000_ICR);
2620
2621         intr->flags = 0;
2622         if (icr & E1000_ICR_LSC) {
2623                 intr->flags |= E1000_FLAG_NEED_LINK_UPDATE;
2624         }
2625
2626         if (icr & E1000_ICR_VMMB)
2627                 intr->flags |= E1000_FLAG_MAILBOX;
2628
2629         return 0;
2630 }
2631
2632 /*
2633  * It executes link_update after knowing an interrupt is prsent.
2634  *
2635  * @param dev
2636  *  Pointer to struct rte_eth_dev.
2637  *
2638  * @return
2639  *  - On success, zero.
2640  *  - On failure, a negative value.
2641  */
2642 static int
2643 eth_igb_interrupt_action(struct rte_eth_dev *dev)
2644 {
2645         struct e1000_hw *hw =
2646                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2647         struct e1000_interrupt *intr =
2648                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2649         uint32_t tctl, rctl;
2650         struct rte_eth_link link;
2651         int ret;
2652
2653         if (intr->flags & E1000_FLAG_MAILBOX) {
2654                 igb_pf_mbx_process(dev);
2655                 intr->flags &= ~E1000_FLAG_MAILBOX;
2656         }
2657
2658         igb_intr_enable(dev);
2659         rte_intr_enable(&(dev->pci_dev->intr_handle));
2660
2661         if (intr->flags & E1000_FLAG_NEED_LINK_UPDATE) {
2662                 intr->flags &= ~E1000_FLAG_NEED_LINK_UPDATE;
2663
2664                 /* set get_link_status to check register later */
2665                 hw->mac.get_link_status = 1;
2666                 ret = eth_igb_link_update(dev, 0);
2667
2668                 /* check if link has changed */
2669                 if (ret < 0)
2670                         return 0;
2671
2672                 memset(&link, 0, sizeof(link));
2673                 rte_igb_dev_atomic_read_link_status(dev, &link);
2674                 if (link.link_status) {
2675                         PMD_INIT_LOG(INFO,
2676                                      " Port %d: Link Up - speed %u Mbps - %s",
2677                                      dev->data->port_id,
2678                                      (unsigned)link.link_speed,
2679                                      link.link_duplex == ETH_LINK_FULL_DUPLEX ?
2680                                      "full-duplex" : "half-duplex");
2681                 } else {
2682                         PMD_INIT_LOG(INFO, " Port %d: Link Down",
2683                                      dev->data->port_id);
2684                 }
2685
2686                 PMD_INIT_LOG(DEBUG, "PCI Address: %04d:%02d:%02d:%d",
2687                              dev->pci_dev->addr.domain,
2688                              dev->pci_dev->addr.bus,
2689                              dev->pci_dev->addr.devid,
2690                              dev->pci_dev->addr.function);
2691                 tctl = E1000_READ_REG(hw, E1000_TCTL);
2692                 rctl = E1000_READ_REG(hw, E1000_RCTL);
2693                 if (link.link_status) {
2694                         /* enable Tx/Rx */
2695                         tctl |= E1000_TCTL_EN;
2696                         rctl |= E1000_RCTL_EN;
2697                 } else {
2698                         /* disable Tx/Rx */
2699                         tctl &= ~E1000_TCTL_EN;
2700                         rctl &= ~E1000_RCTL_EN;
2701                 }
2702                 E1000_WRITE_REG(hw, E1000_TCTL, tctl);
2703                 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2704                 E1000_WRITE_FLUSH(hw);
2705                 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC, NULL);
2706         }
2707
2708         return 0;
2709 }
2710
2711 /**
2712  * Interrupt handler which shall be registered at first.
2713  *
2714  * @param handle
2715  *  Pointer to interrupt handle.
2716  * @param param
2717  *  The address of parameter (struct rte_eth_dev *) regsitered before.
2718  *
2719  * @return
2720  *  void
2721  */
2722 static void
2723 eth_igb_interrupt_handler(__rte_unused struct rte_intr_handle *handle,
2724                                                         void *param)
2725 {
2726         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
2727
2728         eth_igb_interrupt_get_status(dev);
2729         eth_igb_interrupt_action(dev);
2730 }
2731
2732 static int
2733 eth_igbvf_interrupt_get_status(struct rte_eth_dev *dev)
2734 {
2735         uint32_t eicr;
2736         struct e1000_hw *hw =
2737                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2738         struct e1000_interrupt *intr =
2739                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2740
2741         igbvf_intr_disable(hw);
2742
2743         /* read-on-clear nic registers here */
2744         eicr = E1000_READ_REG(hw, E1000_EICR);
2745         intr->flags = 0;
2746
2747         if (eicr == E1000_VTIVAR_MISC_MAILBOX)
2748                 intr->flags |= E1000_FLAG_MAILBOX;
2749
2750         return 0;
2751 }
2752
2753 void igbvf_mbx_process(struct rte_eth_dev *dev)
2754 {
2755         struct e1000_hw *hw =
2756                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2757         struct e1000_mbx_info *mbx = &hw->mbx;
2758         u32 in_msg = 0;
2759
2760         /* peek the message first */
2761         in_msg = E1000_READ_REG(hw, E1000_VMBMEM(0));
2762
2763         /* PF reset VF event */
2764         if (in_msg == E1000_PF_CONTROL_MSG) {
2765                 /* dummy mbx read to ack pf */
2766                 if (mbx->ops.read(hw, &in_msg, 1, 0))
2767                         return;
2768                 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_RESET,
2769                                               NULL);
2770         }
2771 }
2772
2773 static int
2774 eth_igbvf_interrupt_action(struct rte_eth_dev *dev)
2775 {
2776         struct e1000_interrupt *intr =
2777                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2778
2779         if (intr->flags & E1000_FLAG_MAILBOX) {
2780                 igbvf_mbx_process(dev);
2781                 intr->flags &= ~E1000_FLAG_MAILBOX;
2782         }
2783
2784         igbvf_intr_enable(dev);
2785         rte_intr_enable(&dev->pci_dev->intr_handle);
2786
2787         return 0;
2788 }
2789
2790 static void
2791 eth_igbvf_interrupt_handler(__rte_unused struct rte_intr_handle *handle,
2792                             void *param)
2793 {
2794         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
2795
2796         eth_igbvf_interrupt_get_status(dev);
2797         eth_igbvf_interrupt_action(dev);
2798 }
2799
2800 static int
2801 eth_igb_led_on(struct rte_eth_dev *dev)
2802 {
2803         struct e1000_hw *hw;
2804
2805         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2806         return e1000_led_on(hw) == E1000_SUCCESS ? 0 : -ENOTSUP;
2807 }
2808
2809 static int
2810 eth_igb_led_off(struct rte_eth_dev *dev)
2811 {
2812         struct e1000_hw *hw;
2813
2814         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2815         return e1000_led_off(hw) == E1000_SUCCESS ? 0 : -ENOTSUP;
2816 }
2817
2818 static int
2819 eth_igb_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
2820 {
2821         struct e1000_hw *hw;
2822         uint32_t ctrl;
2823         int tx_pause;
2824         int rx_pause;
2825
2826         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2827         fc_conf->pause_time = hw->fc.pause_time;
2828         fc_conf->high_water = hw->fc.high_water;
2829         fc_conf->low_water = hw->fc.low_water;
2830         fc_conf->send_xon = hw->fc.send_xon;
2831         fc_conf->autoneg = hw->mac.autoneg;
2832
2833         /*
2834          * Return rx_pause and tx_pause status according to actual setting of
2835          * the TFCE and RFCE bits in the CTRL register.
2836          */
2837         ctrl = E1000_READ_REG(hw, E1000_CTRL);
2838         if (ctrl & E1000_CTRL_TFCE)
2839                 tx_pause = 1;
2840         else
2841                 tx_pause = 0;
2842
2843         if (ctrl & E1000_CTRL_RFCE)
2844                 rx_pause = 1;
2845         else
2846                 rx_pause = 0;
2847
2848         if (rx_pause && tx_pause)
2849                 fc_conf->mode = RTE_FC_FULL;
2850         else if (rx_pause)
2851                 fc_conf->mode = RTE_FC_RX_PAUSE;
2852         else if (tx_pause)
2853                 fc_conf->mode = RTE_FC_TX_PAUSE;
2854         else
2855                 fc_conf->mode = RTE_FC_NONE;
2856
2857         return 0;
2858 }
2859
2860 static int
2861 eth_igb_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
2862 {
2863         struct e1000_hw *hw;
2864         int err;
2865         enum e1000_fc_mode rte_fcmode_2_e1000_fcmode[] = {
2866                 e1000_fc_none,
2867                 e1000_fc_rx_pause,
2868                 e1000_fc_tx_pause,
2869                 e1000_fc_full
2870         };
2871         uint32_t rx_buf_size;
2872         uint32_t max_high_water;
2873         uint32_t rctl;
2874
2875         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2876         if (fc_conf->autoneg != hw->mac.autoneg)
2877                 return -ENOTSUP;
2878         rx_buf_size = igb_get_rx_buffer_size(hw);
2879         PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
2880
2881         /* At least reserve one Ethernet frame for watermark */
2882         max_high_water = rx_buf_size - ETHER_MAX_LEN;
2883         if ((fc_conf->high_water > max_high_water) ||
2884             (fc_conf->high_water < fc_conf->low_water)) {
2885                 PMD_INIT_LOG(ERR, "e1000 incorrect high/low water value");
2886                 PMD_INIT_LOG(ERR, "high water must <=  0x%x", max_high_water);
2887                 return -EINVAL;
2888         }
2889
2890         hw->fc.requested_mode = rte_fcmode_2_e1000_fcmode[fc_conf->mode];
2891         hw->fc.pause_time     = fc_conf->pause_time;
2892         hw->fc.high_water     = fc_conf->high_water;
2893         hw->fc.low_water      = fc_conf->low_water;
2894         hw->fc.send_xon       = fc_conf->send_xon;
2895
2896         err = e1000_setup_link_generic(hw);
2897         if (err == E1000_SUCCESS) {
2898
2899                 /* check if we want to forward MAC frames - driver doesn't have native
2900                  * capability to do that, so we'll write the registers ourselves */
2901
2902                 rctl = E1000_READ_REG(hw, E1000_RCTL);
2903
2904                 /* set or clear MFLCN.PMCF bit depending on configuration */
2905                 if (fc_conf->mac_ctrl_frame_fwd != 0)
2906                         rctl |= E1000_RCTL_PMCF;
2907                 else
2908                         rctl &= ~E1000_RCTL_PMCF;
2909
2910                 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2911                 E1000_WRITE_FLUSH(hw);
2912
2913                 return 0;
2914         }
2915
2916         PMD_INIT_LOG(ERR, "e1000_setup_link_generic = 0x%x", err);
2917         return -EIO;
2918 }
2919
2920 #define E1000_RAH_POOLSEL_SHIFT      (18)
2921 static void
2922 eth_igb_rar_set(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
2923                 uint32_t index, __rte_unused uint32_t pool)
2924 {
2925         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2926         uint32_t rah;
2927
2928         e1000_rar_set(hw, mac_addr->addr_bytes, index);
2929         rah = E1000_READ_REG(hw, E1000_RAH(index));
2930         rah |= (0x1 << (E1000_RAH_POOLSEL_SHIFT + pool));
2931         E1000_WRITE_REG(hw, E1000_RAH(index), rah);
2932 }
2933
2934 static void
2935 eth_igb_rar_clear(struct rte_eth_dev *dev, uint32_t index)
2936 {
2937         uint8_t addr[ETHER_ADDR_LEN];
2938         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2939
2940         memset(addr, 0, sizeof(addr));
2941
2942         e1000_rar_set(hw, addr, index);
2943 }
2944
2945 static void
2946 eth_igb_default_mac_addr_set(struct rte_eth_dev *dev,
2947                                 struct ether_addr *addr)
2948 {
2949         eth_igb_rar_clear(dev, 0);
2950
2951         eth_igb_rar_set(dev, (void *)addr, 0, 0);
2952 }
2953 /*
2954  * Virtual Function operations
2955  */
2956 static void
2957 igbvf_intr_disable(struct e1000_hw *hw)
2958 {
2959         PMD_INIT_FUNC_TRACE();
2960
2961         /* Clear interrupt mask to stop from interrupts being generated */
2962         E1000_WRITE_REG(hw, E1000_EIMC, 0xFFFF);
2963
2964         E1000_WRITE_FLUSH(hw);
2965 }
2966
2967 static void
2968 igbvf_stop_adapter(struct rte_eth_dev *dev)
2969 {
2970         u32 reg_val;
2971         u16 i;
2972         struct rte_eth_dev_info dev_info;
2973         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2974
2975         memset(&dev_info, 0, sizeof(dev_info));
2976         eth_igbvf_infos_get(dev, &dev_info);
2977
2978         /* Clear interrupt mask to stop from interrupts being generated */
2979         igbvf_intr_disable(hw);
2980
2981         /* Clear any pending interrupts, flush previous writes */
2982         E1000_READ_REG(hw, E1000_EICR);
2983
2984         /* Disable the transmit unit.  Each queue must be disabled. */
2985         for (i = 0; i < dev_info.max_tx_queues; i++)
2986                 E1000_WRITE_REG(hw, E1000_TXDCTL(i), E1000_TXDCTL_SWFLSH);
2987
2988         /* Disable the receive unit by stopping each queue */
2989         for (i = 0; i < dev_info.max_rx_queues; i++) {
2990                 reg_val = E1000_READ_REG(hw, E1000_RXDCTL(i));
2991                 reg_val &= ~E1000_RXDCTL_QUEUE_ENABLE;
2992                 E1000_WRITE_REG(hw, E1000_RXDCTL(i), reg_val);
2993                 while (E1000_READ_REG(hw, E1000_RXDCTL(i)) & E1000_RXDCTL_QUEUE_ENABLE)
2994                         ;
2995         }
2996
2997         /* flush all queues disables */
2998         E1000_WRITE_FLUSH(hw);
2999         msec_delay(2);
3000 }
3001
3002 static int eth_igbvf_link_update(struct e1000_hw *hw)
3003 {
3004         struct e1000_mbx_info *mbx = &hw->mbx;
3005         struct e1000_mac_info *mac = &hw->mac;
3006         int ret_val = E1000_SUCCESS;
3007
3008         PMD_INIT_LOG(DEBUG, "e1000_check_for_link_vf");
3009
3010         /*
3011          * We only want to run this if there has been a rst asserted.
3012          * in this case that could mean a link change, device reset,
3013          * or a virtual function reset
3014          */
3015
3016         /* If we were hit with a reset or timeout drop the link */
3017         if (!e1000_check_for_rst(hw, 0) || !mbx->timeout)
3018                 mac->get_link_status = TRUE;
3019
3020         if (!mac->get_link_status)
3021                 goto out;
3022
3023         /* if link status is down no point in checking to see if pf is up */
3024         if (!(E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU))
3025                 goto out;
3026
3027         /* if we passed all the tests above then the link is up and we no
3028          * longer need to check for link */
3029         mac->get_link_status = FALSE;
3030
3031 out:
3032         return ret_val;
3033 }
3034
3035
3036 static int
3037 igbvf_dev_configure(struct rte_eth_dev *dev)
3038 {
3039         struct rte_eth_conf* conf = &dev->data->dev_conf;
3040
3041         PMD_INIT_LOG(DEBUG, "Configured Virtual Function port id: %d",
3042                      dev->data->port_id);
3043
3044         /*
3045          * VF has no ability to enable/disable HW CRC
3046          * Keep the persistent behavior the same as Host PF
3047          */
3048 #ifndef RTE_LIBRTE_E1000_PF_DISABLE_STRIP_CRC
3049         if (!conf->rxmode.hw_strip_crc) {
3050                 PMD_INIT_LOG(NOTICE, "VF can't disable HW CRC Strip");
3051                 conf->rxmode.hw_strip_crc = 1;
3052         }
3053 #else
3054         if (conf->rxmode.hw_strip_crc) {
3055                 PMD_INIT_LOG(NOTICE, "VF can't enable HW CRC Strip");
3056                 conf->rxmode.hw_strip_crc = 0;
3057         }
3058 #endif
3059
3060         return 0;
3061 }
3062
3063 static int
3064 igbvf_dev_start(struct rte_eth_dev *dev)
3065 {
3066         struct e1000_hw *hw =
3067                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3068         struct e1000_adapter *adapter =
3069                 E1000_DEV_PRIVATE(dev->data->dev_private);
3070         int ret;
3071         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
3072         uint32_t intr_vector = 0;
3073
3074         PMD_INIT_FUNC_TRACE();
3075
3076         hw->mac.ops.reset_hw(hw);
3077         adapter->stopped = 0;
3078
3079         /* Set all vfta */
3080         igbvf_set_vfta_all(dev,1);
3081
3082         eth_igbvf_tx_init(dev);
3083
3084         /* This can fail when allocating mbufs for descriptor rings */
3085         ret = eth_igbvf_rx_init(dev);
3086         if (ret) {
3087                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
3088                 igb_dev_clear_queues(dev);
3089                 return ret;
3090         }
3091
3092         /* check and configure queue intr-vector mapping */
3093         if (rte_intr_cap_multiple(intr_handle) &&
3094             dev->data->dev_conf.intr_conf.rxq) {
3095                 intr_vector = dev->data->nb_rx_queues;
3096                 ret = rte_intr_efd_enable(intr_handle, intr_vector);
3097                 if (ret)
3098                         return ret;
3099         }
3100
3101         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
3102                 intr_handle->intr_vec =
3103                         rte_zmalloc("intr_vec",
3104                                     dev->data->nb_rx_queues * sizeof(int), 0);
3105                 if (!intr_handle->intr_vec) {
3106                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
3107                                      " intr_vec\n", dev->data->nb_rx_queues);
3108                         return -ENOMEM;
3109                 }
3110         }
3111
3112         eth_igbvf_configure_msix_intr(dev);
3113
3114         /* enable uio/vfio intr/eventfd mapping */
3115         rte_intr_enable(intr_handle);
3116
3117         /* resume enabled intr since hw reset */
3118         igbvf_intr_enable(dev);
3119
3120         return 0;
3121 }
3122
3123 static void
3124 igbvf_dev_stop(struct rte_eth_dev *dev)
3125 {
3126         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
3127
3128         PMD_INIT_FUNC_TRACE();
3129
3130         igbvf_stop_adapter(dev);
3131
3132         /*
3133           * Clear what we set, but we still keep shadow_vfta to
3134           * restore after device starts
3135           */
3136         igbvf_set_vfta_all(dev,0);
3137
3138         igb_dev_clear_queues(dev);
3139
3140         /* disable intr eventfd mapping */
3141         rte_intr_disable(intr_handle);
3142
3143         /* Clean datapath event and queue/vec mapping */
3144         rte_intr_efd_disable(intr_handle);
3145         if (intr_handle->intr_vec) {
3146                 rte_free(intr_handle->intr_vec);
3147                 intr_handle->intr_vec = NULL;
3148         }
3149 }
3150
3151 static void
3152 igbvf_dev_close(struct rte_eth_dev *dev)
3153 {
3154         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3155         struct e1000_adapter *adapter =
3156                 E1000_DEV_PRIVATE(dev->data->dev_private);
3157         struct ether_addr addr;
3158
3159         PMD_INIT_FUNC_TRACE();
3160
3161         e1000_reset_hw(hw);
3162
3163         igbvf_dev_stop(dev);
3164         adapter->stopped = 1;
3165         igb_dev_free_queues(dev);
3166
3167         /**
3168          * reprogram the RAR with a zero mac address,
3169          * to ensure that the VF traffic goes to the PF
3170          * after stop, close and detach of the VF.
3171          **/
3172
3173         memset(&addr, 0, sizeof(addr));
3174         igbvf_default_mac_addr_set(dev, &addr);
3175 }
3176
3177 static void
3178 igbvf_promiscuous_enable(struct rte_eth_dev *dev)
3179 {
3180         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3181
3182         /* Set both unicast and multicast promisc */
3183         e1000_promisc_set_vf(hw, e1000_promisc_enabled);
3184 }
3185
3186 static void
3187 igbvf_promiscuous_disable(struct rte_eth_dev *dev)
3188 {
3189         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3190
3191         /* If in allmulticast mode leave multicast promisc */
3192         if (dev->data->all_multicast == 1)
3193                 e1000_promisc_set_vf(hw, e1000_promisc_multicast);
3194         else
3195                 e1000_promisc_set_vf(hw, e1000_promisc_disabled);
3196 }
3197
3198 static void
3199 igbvf_allmulticast_enable(struct rte_eth_dev *dev)
3200 {
3201         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3202
3203         /* In promiscuous mode multicast promisc already set */
3204         if (dev->data->promiscuous == 0)
3205                 e1000_promisc_set_vf(hw, e1000_promisc_multicast);
3206 }
3207
3208 static void
3209 igbvf_allmulticast_disable(struct rte_eth_dev *dev)
3210 {
3211         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3212
3213         /* In promiscuous mode leave multicast promisc enabled */
3214         if (dev->data->promiscuous == 0)
3215                 e1000_promisc_set_vf(hw, e1000_promisc_disabled);
3216 }
3217
3218 static int igbvf_set_vfta(struct e1000_hw *hw, uint16_t vid, bool on)
3219 {
3220         struct e1000_mbx_info *mbx = &hw->mbx;
3221         uint32_t msgbuf[2];
3222         s32 err;
3223
3224         /* After set vlan, vlan strip will also be enabled in igb driver*/
3225         msgbuf[0] = E1000_VF_SET_VLAN;
3226         msgbuf[1] = vid;
3227         /* Setting the 8 bit field MSG INFO to TRUE indicates "add" */
3228         if (on)
3229                 msgbuf[0] |= E1000_VF_SET_VLAN_ADD;
3230
3231         err = mbx->ops.write_posted(hw, msgbuf, 2, 0);
3232         if (err)
3233                 goto mbx_err;
3234
3235         err = mbx->ops.read_posted(hw, msgbuf, 2, 0);
3236         if (err)
3237                 goto mbx_err;
3238
3239         msgbuf[0] &= ~E1000_VT_MSGTYPE_CTS;
3240         if (msgbuf[0] == (E1000_VF_SET_VLAN | E1000_VT_MSGTYPE_NACK))
3241                 err = -EINVAL;
3242
3243 mbx_err:
3244         return err;
3245 }
3246
3247 static void igbvf_set_vfta_all(struct rte_eth_dev *dev, bool on)
3248 {
3249         struct e1000_hw *hw =
3250                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3251         struct e1000_vfta * shadow_vfta =
3252                 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
3253         int i = 0, j = 0, vfta = 0, mask = 1;
3254
3255         for (i = 0; i < IGB_VFTA_SIZE; i++){
3256                 vfta = shadow_vfta->vfta[i];
3257                 if(vfta){
3258                         mask = 1;
3259                         for (j = 0; j < 32; j++){
3260                                 if(vfta & mask)
3261                                         igbvf_set_vfta(hw,
3262                                                 (uint16_t)((i<<5)+j), on);
3263                                 mask<<=1;
3264                         }
3265                 }
3266         }
3267
3268 }
3269
3270 static int
3271 igbvf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
3272 {
3273         struct e1000_hw *hw =
3274                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3275         struct e1000_vfta * shadow_vfta =
3276                 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
3277         uint32_t vid_idx = 0;
3278         uint32_t vid_bit = 0;
3279         int ret = 0;
3280
3281         PMD_INIT_FUNC_TRACE();
3282
3283         /*vind is not used in VF driver, set to 0, check ixgbe_set_vfta_vf*/
3284         ret = igbvf_set_vfta(hw, vlan_id, !!on);
3285         if(ret){
3286                 PMD_INIT_LOG(ERR, "Unable to set VF vlan");
3287                 return ret;
3288         }
3289         vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
3290         vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
3291
3292         /*Save what we set and retore it after device reset*/
3293         if (on)
3294                 shadow_vfta->vfta[vid_idx] |= vid_bit;
3295         else
3296                 shadow_vfta->vfta[vid_idx] &= ~vid_bit;
3297
3298         return 0;
3299 }
3300
3301 static void
3302 igbvf_default_mac_addr_set(struct rte_eth_dev *dev, struct ether_addr *addr)
3303 {
3304         struct e1000_hw *hw =
3305                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3306
3307         /* index is not used by rar_set() */
3308         hw->mac.ops.rar_set(hw, (void *)addr, 0);
3309 }
3310
3311
3312 static int
3313 eth_igb_rss_reta_update(struct rte_eth_dev *dev,
3314                         struct rte_eth_rss_reta_entry64 *reta_conf,
3315                         uint16_t reta_size)
3316 {
3317         uint8_t i, j, mask;
3318         uint32_t reta, r;
3319         uint16_t idx, shift;
3320         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3321
3322         if (reta_size != ETH_RSS_RETA_SIZE_128) {
3323                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
3324                         "(%d) doesn't match the number hardware can supported "
3325                         "(%d)\n", reta_size, ETH_RSS_RETA_SIZE_128);
3326                 return -EINVAL;
3327         }
3328
3329         for (i = 0; i < reta_size; i += IGB_4_BIT_WIDTH) {
3330                 idx = i / RTE_RETA_GROUP_SIZE;
3331                 shift = i % RTE_RETA_GROUP_SIZE;
3332                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
3333                                                 IGB_4_BIT_MASK);
3334                 if (!mask)
3335                         continue;
3336                 if (mask == IGB_4_BIT_MASK)
3337                         r = 0;
3338                 else
3339                         r = E1000_READ_REG(hw, E1000_RETA(i >> 2));
3340                 for (j = 0, reta = 0; j < IGB_4_BIT_WIDTH; j++) {
3341                         if (mask & (0x1 << j))
3342                                 reta |= reta_conf[idx].reta[shift + j] <<
3343                                                         (CHAR_BIT * j);
3344                         else
3345                                 reta |= r & (IGB_8_BIT_MASK << (CHAR_BIT * j));
3346                 }
3347                 E1000_WRITE_REG(hw, E1000_RETA(i >> 2), reta);
3348         }
3349
3350         return 0;
3351 }
3352
3353 static int
3354 eth_igb_rss_reta_query(struct rte_eth_dev *dev,
3355                        struct rte_eth_rss_reta_entry64 *reta_conf,
3356                        uint16_t reta_size)
3357 {
3358         uint8_t i, j, mask;
3359         uint32_t reta;
3360         uint16_t idx, shift;
3361         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3362
3363         if (reta_size != ETH_RSS_RETA_SIZE_128) {
3364                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
3365                         "(%d) doesn't match the number hardware can supported "
3366                         "(%d)\n", reta_size, ETH_RSS_RETA_SIZE_128);
3367                 return -EINVAL;
3368         }
3369
3370         for (i = 0; i < reta_size; i += IGB_4_BIT_WIDTH) {
3371                 idx = i / RTE_RETA_GROUP_SIZE;
3372                 shift = i % RTE_RETA_GROUP_SIZE;
3373                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
3374                                                 IGB_4_BIT_MASK);
3375                 if (!mask)
3376                         continue;
3377                 reta = E1000_READ_REG(hw, E1000_RETA(i >> 2));
3378                 for (j = 0; j < IGB_4_BIT_WIDTH; j++) {
3379                         if (mask & (0x1 << j))
3380                                 reta_conf[idx].reta[shift + j] =
3381                                         ((reta >> (CHAR_BIT * j)) &
3382                                                 IGB_8_BIT_MASK);
3383                 }
3384         }
3385
3386         return 0;
3387 }
3388
3389 #define MAC_TYPE_FILTER_SUP(type)    do {\
3390         if ((type) != e1000_82580 && (type) != e1000_i350 &&\
3391                 (type) != e1000_82576)\
3392                 return -ENOTSUP;\
3393 } while (0)
3394
3395 static int
3396 eth_igb_syn_filter_set(struct rte_eth_dev *dev,
3397                         struct rte_eth_syn_filter *filter,
3398                         bool add)
3399 {
3400         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3401         uint32_t synqf, rfctl;
3402
3403         if (filter->queue >= IGB_MAX_RX_QUEUE_NUM)
3404                 return -EINVAL;
3405
3406         synqf = E1000_READ_REG(hw, E1000_SYNQF(0));
3407
3408         if (add) {
3409                 if (synqf & E1000_SYN_FILTER_ENABLE)
3410                         return -EINVAL;
3411
3412                 synqf = (uint32_t)(((filter->queue << E1000_SYN_FILTER_QUEUE_SHIFT) &
3413                         E1000_SYN_FILTER_QUEUE) | E1000_SYN_FILTER_ENABLE);
3414
3415                 rfctl = E1000_READ_REG(hw, E1000_RFCTL);
3416                 if (filter->hig_pri)
3417                         rfctl |= E1000_RFCTL_SYNQFP;
3418                 else
3419                         rfctl &= ~E1000_RFCTL_SYNQFP;
3420
3421                 E1000_WRITE_REG(hw, E1000_RFCTL, rfctl);
3422         } else {
3423                 if (!(synqf & E1000_SYN_FILTER_ENABLE))
3424                         return -ENOENT;
3425                 synqf = 0;
3426         }
3427
3428         E1000_WRITE_REG(hw, E1000_SYNQF(0), synqf);
3429         E1000_WRITE_FLUSH(hw);
3430         return 0;
3431 }
3432
3433 static int
3434 eth_igb_syn_filter_get(struct rte_eth_dev *dev,
3435                         struct rte_eth_syn_filter *filter)
3436 {
3437         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3438         uint32_t synqf, rfctl;
3439
3440         synqf = E1000_READ_REG(hw, E1000_SYNQF(0));
3441         if (synqf & E1000_SYN_FILTER_ENABLE) {
3442                 rfctl = E1000_READ_REG(hw, E1000_RFCTL);
3443                 filter->hig_pri = (rfctl & E1000_RFCTL_SYNQFP) ? 1 : 0;
3444                 filter->queue = (uint8_t)((synqf & E1000_SYN_FILTER_QUEUE) >>
3445                                 E1000_SYN_FILTER_QUEUE_SHIFT);
3446                 return 0;
3447         }
3448
3449         return -ENOENT;
3450 }
3451
3452 static int
3453 eth_igb_syn_filter_handle(struct rte_eth_dev *dev,
3454                         enum rte_filter_op filter_op,
3455                         void *arg)
3456 {
3457         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3458         int ret;
3459
3460         MAC_TYPE_FILTER_SUP(hw->mac.type);
3461
3462         if (filter_op == RTE_ETH_FILTER_NOP)
3463                 return 0;
3464
3465         if (arg == NULL) {
3466                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
3467                             filter_op);
3468                 return -EINVAL;
3469         }
3470
3471         switch (filter_op) {
3472         case RTE_ETH_FILTER_ADD:
3473                 ret = eth_igb_syn_filter_set(dev,
3474                                 (struct rte_eth_syn_filter *)arg,
3475                                 TRUE);
3476                 break;
3477         case RTE_ETH_FILTER_DELETE:
3478                 ret = eth_igb_syn_filter_set(dev,
3479                                 (struct rte_eth_syn_filter *)arg,
3480                                 FALSE);
3481                 break;
3482         case RTE_ETH_FILTER_GET:
3483                 ret = eth_igb_syn_filter_get(dev,
3484                                 (struct rte_eth_syn_filter *)arg);
3485                 break;
3486         default:
3487                 PMD_DRV_LOG(ERR, "unsupported operation %u\n", filter_op);
3488                 ret = -EINVAL;
3489                 break;
3490         }
3491
3492         return ret;
3493 }
3494
3495 #define MAC_TYPE_FILTER_SUP_EXT(type)    do {\
3496         if ((type) != e1000_82580 && (type) != e1000_i350)\
3497                 return -ENOSYS; \
3498 } while (0)
3499
3500 /* translate elements in struct rte_eth_ntuple_filter to struct e1000_2tuple_filter_info*/
3501 static inline int
3502 ntuple_filter_to_2tuple(struct rte_eth_ntuple_filter *filter,
3503                         struct e1000_2tuple_filter_info *filter_info)
3504 {
3505         if (filter->queue >= IGB_MAX_RX_QUEUE_NUM)
3506                 return -EINVAL;
3507         if (filter->priority > E1000_2TUPLE_MAX_PRI)
3508                 return -EINVAL;  /* filter index is out of range. */
3509         if (filter->tcp_flags > TCP_FLAG_ALL)
3510                 return -EINVAL;  /* flags is invalid. */
3511
3512         switch (filter->dst_port_mask) {
3513         case UINT16_MAX:
3514                 filter_info->dst_port_mask = 0;
3515                 filter_info->dst_port = filter->dst_port;
3516                 break;
3517         case 0:
3518                 filter_info->dst_port_mask = 1;
3519                 break;
3520         default:
3521                 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
3522                 return -EINVAL;
3523         }
3524
3525         switch (filter->proto_mask) {
3526         case UINT8_MAX:
3527                 filter_info->proto_mask = 0;
3528                 filter_info->proto = filter->proto;
3529                 break;
3530         case 0:
3531                 filter_info->proto_mask = 1;
3532                 break;
3533         default:
3534                 PMD_DRV_LOG(ERR, "invalid protocol mask.");
3535                 return -EINVAL;
3536         }
3537
3538         filter_info->priority = (uint8_t)filter->priority;
3539         if (filter->flags & RTE_NTUPLE_FLAGS_TCP_FLAG)
3540                 filter_info->tcp_flags = filter->tcp_flags;
3541         else
3542                 filter_info->tcp_flags = 0;
3543
3544         return 0;
3545 }
3546
3547 static inline struct e1000_2tuple_filter *
3548 igb_2tuple_filter_lookup(struct e1000_2tuple_filter_list *filter_list,
3549                         struct e1000_2tuple_filter_info *key)
3550 {
3551         struct e1000_2tuple_filter *it;
3552
3553         TAILQ_FOREACH(it, filter_list, entries) {
3554                 if (memcmp(key, &it->filter_info,
3555                         sizeof(struct e1000_2tuple_filter_info)) == 0) {
3556                         return it;
3557                 }
3558         }
3559         return NULL;
3560 }
3561
3562 /*
3563  * igb_add_2tuple_filter - add a 2tuple filter
3564  *
3565  * @param
3566  * dev: Pointer to struct rte_eth_dev.
3567  * ntuple_filter: ponter to the filter that will be added.
3568  *
3569  * @return
3570  *    - On success, zero.
3571  *    - On failure, a negative value.
3572  */
3573 static int
3574 igb_add_2tuple_filter(struct rte_eth_dev *dev,
3575                         struct rte_eth_ntuple_filter *ntuple_filter)
3576 {
3577         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3578         struct e1000_filter_info *filter_info =
3579                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3580         struct e1000_2tuple_filter *filter;
3581         uint32_t ttqf = E1000_TTQF_DISABLE_MASK;
3582         uint32_t imir, imir_ext = E1000_IMIREXT_SIZE_BP;
3583         int i, ret;
3584
3585         filter = rte_zmalloc("e1000_2tuple_filter",
3586                         sizeof(struct e1000_2tuple_filter), 0);
3587         if (filter == NULL)
3588                 return -ENOMEM;
3589
3590         ret = ntuple_filter_to_2tuple(ntuple_filter,
3591                                       &filter->filter_info);
3592         if (ret < 0) {
3593                 rte_free(filter);
3594                 return ret;
3595         }
3596         if (igb_2tuple_filter_lookup(&filter_info->twotuple_list,
3597                                          &filter->filter_info) != NULL) {
3598                 PMD_DRV_LOG(ERR, "filter exists.");
3599                 rte_free(filter);
3600                 return -EEXIST;
3601         }
3602         filter->queue = ntuple_filter->queue;
3603
3604         /*
3605          * look for an unused 2tuple filter index,
3606          * and insert the filter to list.
3607          */
3608         for (i = 0; i < E1000_MAX_TTQF_FILTERS; i++) {
3609                 if (!(filter_info->twotuple_mask & (1 << i))) {
3610                         filter_info->twotuple_mask |= 1 << i;
3611                         filter->index = i;
3612                         TAILQ_INSERT_TAIL(&filter_info->twotuple_list,
3613                                           filter,
3614                                           entries);
3615                         break;
3616                 }
3617         }
3618         if (i >= E1000_MAX_TTQF_FILTERS) {
3619                 PMD_DRV_LOG(ERR, "2tuple filters are full.");
3620                 rte_free(filter);
3621                 return -ENOSYS;
3622         }
3623
3624         imir = (uint32_t)(filter->filter_info.dst_port & E1000_IMIR_DSTPORT);
3625         if (filter->filter_info.dst_port_mask == 1) /* 1b means not compare. */
3626                 imir |= E1000_IMIR_PORT_BP;
3627         else
3628                 imir &= ~E1000_IMIR_PORT_BP;
3629
3630         imir |= filter->filter_info.priority << E1000_IMIR_PRIORITY_SHIFT;
3631
3632         ttqf |= E1000_TTQF_QUEUE_ENABLE;
3633         ttqf |= (uint32_t)(filter->queue << E1000_TTQF_QUEUE_SHIFT);
3634         ttqf |= (uint32_t)(filter->filter_info.proto & E1000_TTQF_PROTOCOL_MASK);
3635         if (filter->filter_info.proto_mask == 0)
3636                 ttqf &= ~E1000_TTQF_MASK_ENABLE;
3637
3638         /* tcp flags bits setting. */
3639         if (filter->filter_info.tcp_flags & TCP_FLAG_ALL) {
3640                 if (filter->filter_info.tcp_flags & TCP_URG_FLAG)
3641                         imir_ext |= E1000_IMIREXT_CTRL_URG;
3642                 if (filter->filter_info.tcp_flags & TCP_ACK_FLAG)
3643                         imir_ext |= E1000_IMIREXT_CTRL_ACK;
3644                 if (filter->filter_info.tcp_flags & TCP_PSH_FLAG)
3645                         imir_ext |= E1000_IMIREXT_CTRL_PSH;
3646                 if (filter->filter_info.tcp_flags & TCP_RST_FLAG)
3647                         imir_ext |= E1000_IMIREXT_CTRL_RST;
3648                 if (filter->filter_info.tcp_flags & TCP_SYN_FLAG)
3649                         imir_ext |= E1000_IMIREXT_CTRL_SYN;
3650                 if (filter->filter_info.tcp_flags & TCP_FIN_FLAG)
3651                         imir_ext |= E1000_IMIREXT_CTRL_FIN;
3652         } else
3653                 imir_ext |= E1000_IMIREXT_CTRL_BP;
3654         E1000_WRITE_REG(hw, E1000_IMIR(i), imir);
3655         E1000_WRITE_REG(hw, E1000_TTQF(i), ttqf);
3656         E1000_WRITE_REG(hw, E1000_IMIREXT(i), imir_ext);
3657         return 0;
3658 }
3659
3660 /*
3661  * igb_remove_2tuple_filter - remove a 2tuple filter
3662  *
3663  * @param
3664  * dev: Pointer to struct rte_eth_dev.
3665  * ntuple_filter: ponter to the filter that will be removed.
3666  *
3667  * @return
3668  *    - On success, zero.
3669  *    - On failure, a negative value.
3670  */
3671 static int
3672 igb_remove_2tuple_filter(struct rte_eth_dev *dev,
3673                         struct rte_eth_ntuple_filter *ntuple_filter)
3674 {
3675         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3676         struct e1000_filter_info *filter_info =
3677                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3678         struct e1000_2tuple_filter_info filter_2tuple;
3679         struct e1000_2tuple_filter *filter;
3680         int ret;
3681
3682         memset(&filter_2tuple, 0, sizeof(struct e1000_2tuple_filter_info));
3683         ret = ntuple_filter_to_2tuple(ntuple_filter,
3684                                       &filter_2tuple);
3685         if (ret < 0)
3686                 return ret;
3687
3688         filter = igb_2tuple_filter_lookup(&filter_info->twotuple_list,
3689                                          &filter_2tuple);
3690         if (filter == NULL) {
3691                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
3692                 return -ENOENT;
3693         }
3694
3695         filter_info->twotuple_mask &= ~(1 << filter->index);
3696         TAILQ_REMOVE(&filter_info->twotuple_list, filter, entries);
3697         rte_free(filter);
3698
3699         E1000_WRITE_REG(hw, E1000_TTQF(filter->index), E1000_TTQF_DISABLE_MASK);
3700         E1000_WRITE_REG(hw, E1000_IMIR(filter->index), 0);
3701         E1000_WRITE_REG(hw, E1000_IMIREXT(filter->index), 0);
3702         return 0;
3703 }
3704
3705 static inline struct e1000_flex_filter *
3706 eth_igb_flex_filter_lookup(struct e1000_flex_filter_list *filter_list,
3707                         struct e1000_flex_filter_info *key)
3708 {
3709         struct e1000_flex_filter *it;
3710
3711         TAILQ_FOREACH(it, filter_list, entries) {
3712                 if (memcmp(key, &it->filter_info,
3713                         sizeof(struct e1000_flex_filter_info)) == 0)
3714                         return it;
3715         }
3716
3717         return NULL;
3718 }
3719
3720 static int
3721 eth_igb_add_del_flex_filter(struct rte_eth_dev *dev,
3722                         struct rte_eth_flex_filter *filter,
3723                         bool add)
3724 {
3725         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3726         struct e1000_filter_info *filter_info =
3727                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3728         struct e1000_flex_filter *flex_filter, *it;
3729         uint32_t wufc, queueing, mask;
3730         uint32_t reg_off;
3731         uint8_t shift, i, j = 0;
3732
3733         flex_filter = rte_zmalloc("e1000_flex_filter",
3734                         sizeof(struct e1000_flex_filter), 0);
3735         if (flex_filter == NULL)
3736                 return -ENOMEM;
3737
3738         flex_filter->filter_info.len = filter->len;
3739         flex_filter->filter_info.priority = filter->priority;
3740         memcpy(flex_filter->filter_info.dwords, filter->bytes, filter->len);
3741         for (i = 0; i < RTE_ALIGN(filter->len, CHAR_BIT) / CHAR_BIT; i++) {
3742                 mask = 0;
3743                 /* reverse bits in flex filter's mask*/
3744                 for (shift = 0; shift < CHAR_BIT; shift++) {
3745                         if (filter->mask[i] & (0x01 << shift))
3746                                 mask |= (0x80 >> shift);
3747                 }
3748                 flex_filter->filter_info.mask[i] = mask;
3749         }
3750
3751         wufc = E1000_READ_REG(hw, E1000_WUFC);
3752
3753         if (add) {
3754                 if (eth_igb_flex_filter_lookup(&filter_info->flex_list,
3755                                 &flex_filter->filter_info) != NULL) {
3756                         PMD_DRV_LOG(ERR, "filter exists.");
3757                         rte_free(flex_filter);
3758                         return -EEXIST;
3759                 }
3760                 flex_filter->queue = filter->queue;
3761                 /*
3762                  * look for an unused flex filter index
3763                  * and insert the filter into the list.
3764                  */
3765                 for (i = 0; i < E1000_MAX_FLEX_FILTERS; i++) {
3766                         if (!(filter_info->flex_mask & (1 << i))) {
3767                                 filter_info->flex_mask |= 1 << i;
3768                                 flex_filter->index = i;
3769                                 TAILQ_INSERT_TAIL(&filter_info->flex_list,
3770                                         flex_filter,
3771                                         entries);
3772                                 break;
3773                         }
3774                 }
3775                 if (i >= E1000_MAX_FLEX_FILTERS) {
3776                         PMD_DRV_LOG(ERR, "flex filters are full.");
3777                         rte_free(flex_filter);
3778                         return -ENOSYS;
3779                 }
3780
3781                 if (flex_filter->index < E1000_MAX_FHFT)
3782                         reg_off = E1000_FHFT(flex_filter->index);
3783                 else
3784                         reg_off = E1000_FHFT_EXT(flex_filter->index - E1000_MAX_FHFT);
3785
3786                 E1000_WRITE_REG(hw, E1000_WUFC, wufc | E1000_WUFC_FLEX_HQ |
3787                                 (E1000_WUFC_FLX0 << flex_filter->index));
3788                 queueing = filter->len |
3789                         (filter->queue << E1000_FHFT_QUEUEING_QUEUE_SHIFT) |
3790                         (filter->priority << E1000_FHFT_QUEUEING_PRIO_SHIFT);
3791                 E1000_WRITE_REG(hw, reg_off + E1000_FHFT_QUEUEING_OFFSET,
3792                                 queueing);
3793                 for (i = 0; i < E1000_FLEX_FILTERS_MASK_SIZE; i++) {
3794                         E1000_WRITE_REG(hw, reg_off,
3795                                         flex_filter->filter_info.dwords[j]);
3796                         reg_off += sizeof(uint32_t);
3797                         E1000_WRITE_REG(hw, reg_off,
3798                                         flex_filter->filter_info.dwords[++j]);
3799                         reg_off += sizeof(uint32_t);
3800                         E1000_WRITE_REG(hw, reg_off,
3801                                 (uint32_t)flex_filter->filter_info.mask[i]);
3802                         reg_off += sizeof(uint32_t) * 2;
3803                         ++j;
3804                 }
3805         } else {
3806                 it = eth_igb_flex_filter_lookup(&filter_info->flex_list,
3807                                 &flex_filter->filter_info);
3808                 if (it == NULL) {
3809                         PMD_DRV_LOG(ERR, "filter doesn't exist.");
3810                         rte_free(flex_filter);
3811                         return -ENOENT;
3812                 }
3813
3814                 if (it->index < E1000_MAX_FHFT)
3815                         reg_off = E1000_FHFT(it->index);
3816                 else
3817                         reg_off = E1000_FHFT_EXT(it->index - E1000_MAX_FHFT);
3818
3819                 for (i = 0; i < E1000_FHFT_SIZE_IN_DWD; i++)
3820                         E1000_WRITE_REG(hw, reg_off + i * sizeof(uint32_t), 0);
3821                 E1000_WRITE_REG(hw, E1000_WUFC, wufc &
3822                         (~(E1000_WUFC_FLX0 << it->index)));
3823
3824                 filter_info->flex_mask &= ~(1 << it->index);
3825                 TAILQ_REMOVE(&filter_info->flex_list, it, entries);
3826                 rte_free(it);
3827                 rte_free(flex_filter);
3828         }
3829
3830         return 0;
3831 }
3832
3833 static int
3834 eth_igb_get_flex_filter(struct rte_eth_dev *dev,
3835                         struct rte_eth_flex_filter *filter)
3836 {
3837         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3838         struct e1000_filter_info *filter_info =
3839                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3840         struct e1000_flex_filter flex_filter, *it;
3841         uint32_t wufc, queueing, wufc_en = 0;
3842
3843         memset(&flex_filter, 0, sizeof(struct e1000_flex_filter));
3844         flex_filter.filter_info.len = filter->len;
3845         flex_filter.filter_info.priority = filter->priority;
3846         memcpy(flex_filter.filter_info.dwords, filter->bytes, filter->len);
3847         memcpy(flex_filter.filter_info.mask, filter->mask,
3848                         RTE_ALIGN(filter->len, CHAR_BIT) / CHAR_BIT);
3849
3850         it = eth_igb_flex_filter_lookup(&filter_info->flex_list,
3851                                 &flex_filter.filter_info);
3852         if (it == NULL) {
3853                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
3854                 return -ENOENT;
3855         }
3856
3857         wufc = E1000_READ_REG(hw, E1000_WUFC);
3858         wufc_en = E1000_WUFC_FLEX_HQ | (E1000_WUFC_FLX0 << it->index);
3859
3860         if ((wufc & wufc_en) == wufc_en) {
3861                 uint32_t reg_off = 0;
3862                 if (it->index < E1000_MAX_FHFT)
3863                         reg_off = E1000_FHFT(it->index);
3864                 else
3865                         reg_off = E1000_FHFT_EXT(it->index - E1000_MAX_FHFT);
3866
3867                 queueing = E1000_READ_REG(hw,
3868                                 reg_off + E1000_FHFT_QUEUEING_OFFSET);
3869                 filter->len = queueing & E1000_FHFT_QUEUEING_LEN;
3870                 filter->priority = (queueing & E1000_FHFT_QUEUEING_PRIO) >>
3871                         E1000_FHFT_QUEUEING_PRIO_SHIFT;
3872                 filter->queue = (queueing & E1000_FHFT_QUEUEING_QUEUE) >>
3873                         E1000_FHFT_QUEUEING_QUEUE_SHIFT;
3874                 return 0;
3875         }
3876         return -ENOENT;
3877 }
3878
3879 static int
3880 eth_igb_flex_filter_handle(struct rte_eth_dev *dev,
3881                         enum rte_filter_op filter_op,
3882                         void *arg)
3883 {
3884         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3885         struct rte_eth_flex_filter *filter;
3886         int ret = 0;
3887
3888         MAC_TYPE_FILTER_SUP_EXT(hw->mac.type);
3889
3890         if (filter_op == RTE_ETH_FILTER_NOP)
3891                 return ret;
3892
3893         if (arg == NULL) {
3894                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
3895                             filter_op);
3896                 return -EINVAL;
3897         }
3898
3899         filter = (struct rte_eth_flex_filter *)arg;
3900         if (filter->len == 0 || filter->len > E1000_MAX_FLEX_FILTER_LEN
3901             || filter->len % sizeof(uint64_t) != 0) {
3902                 PMD_DRV_LOG(ERR, "filter's length is out of range");
3903                 return -EINVAL;
3904         }
3905         if (filter->priority > E1000_MAX_FLEX_FILTER_PRI) {
3906                 PMD_DRV_LOG(ERR, "filter's priority is out of range");
3907                 return -EINVAL;
3908         }
3909
3910         switch (filter_op) {
3911         case RTE_ETH_FILTER_ADD:
3912                 ret = eth_igb_add_del_flex_filter(dev, filter, TRUE);
3913                 break;
3914         case RTE_ETH_FILTER_DELETE:
3915                 ret = eth_igb_add_del_flex_filter(dev, filter, FALSE);
3916                 break;
3917         case RTE_ETH_FILTER_GET:
3918                 ret = eth_igb_get_flex_filter(dev, filter);
3919                 break;
3920         default:
3921                 PMD_DRV_LOG(ERR, "unsupported operation %u", filter_op);
3922                 ret = -EINVAL;
3923                 break;
3924         }
3925
3926         return ret;
3927 }
3928
3929 /* translate elements in struct rte_eth_ntuple_filter to struct e1000_5tuple_filter_info*/
3930 static inline int
3931 ntuple_filter_to_5tuple_82576(struct rte_eth_ntuple_filter *filter,
3932                         struct e1000_5tuple_filter_info *filter_info)
3933 {
3934         if (filter->queue >= IGB_MAX_RX_QUEUE_NUM_82576)
3935                 return -EINVAL;
3936         if (filter->priority > E1000_2TUPLE_MAX_PRI)
3937                 return -EINVAL;  /* filter index is out of range. */
3938         if (filter->tcp_flags > TCP_FLAG_ALL)
3939                 return -EINVAL;  /* flags is invalid. */
3940
3941         switch (filter->dst_ip_mask) {
3942         case UINT32_MAX:
3943                 filter_info->dst_ip_mask = 0;
3944                 filter_info->dst_ip = filter->dst_ip;
3945                 break;
3946         case 0:
3947                 filter_info->dst_ip_mask = 1;
3948                 break;
3949         default:
3950                 PMD_DRV_LOG(ERR, "invalid dst_ip mask.");
3951                 return -EINVAL;
3952         }
3953
3954         switch (filter->src_ip_mask) {
3955         case UINT32_MAX:
3956                 filter_info->src_ip_mask = 0;
3957                 filter_info->src_ip = filter->src_ip;
3958                 break;
3959         case 0:
3960                 filter_info->src_ip_mask = 1;
3961                 break;
3962         default:
3963                 PMD_DRV_LOG(ERR, "invalid src_ip mask.");
3964                 return -EINVAL;
3965         }
3966
3967         switch (filter->dst_port_mask) {
3968         case UINT16_MAX:
3969                 filter_info->dst_port_mask = 0;
3970                 filter_info->dst_port = filter->dst_port;
3971                 break;
3972         case 0:
3973                 filter_info->dst_port_mask = 1;
3974                 break;
3975         default:
3976                 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
3977                 return -EINVAL;
3978         }
3979
3980         switch (filter->src_port_mask) {
3981         case UINT16_MAX:
3982                 filter_info->src_port_mask = 0;
3983                 filter_info->src_port = filter->src_port;
3984                 break;
3985         case 0:
3986                 filter_info->src_port_mask = 1;
3987                 break;
3988         default:
3989                 PMD_DRV_LOG(ERR, "invalid src_port mask.");
3990                 return -EINVAL;
3991         }
3992
3993         switch (filter->proto_mask) {
3994         case UINT8_MAX:
3995                 filter_info->proto_mask = 0;
3996                 filter_info->proto = filter->proto;
3997                 break;
3998         case 0:
3999                 filter_info->proto_mask = 1;
4000                 break;
4001         default:
4002                 PMD_DRV_LOG(ERR, "invalid protocol mask.");
4003                 return -EINVAL;
4004         }
4005
4006         filter_info->priority = (uint8_t)filter->priority;
4007         if (filter->flags & RTE_NTUPLE_FLAGS_TCP_FLAG)
4008                 filter_info->tcp_flags = filter->tcp_flags;
4009         else
4010                 filter_info->tcp_flags = 0;
4011
4012         return 0;
4013 }
4014
4015 static inline struct e1000_5tuple_filter *
4016 igb_5tuple_filter_lookup_82576(struct e1000_5tuple_filter_list *filter_list,
4017                         struct e1000_5tuple_filter_info *key)
4018 {
4019         struct e1000_5tuple_filter *it;
4020
4021         TAILQ_FOREACH(it, filter_list, entries) {
4022                 if (memcmp(key, &it->filter_info,
4023                         sizeof(struct e1000_5tuple_filter_info)) == 0) {
4024                         return it;
4025                 }
4026         }
4027         return NULL;
4028 }
4029
4030 /*
4031  * igb_add_5tuple_filter_82576 - add a 5tuple filter
4032  *
4033  * @param
4034  * dev: Pointer to struct rte_eth_dev.
4035  * ntuple_filter: ponter to the filter that will be added.
4036  *
4037  * @return
4038  *    - On success, zero.
4039  *    - On failure, a negative value.
4040  */
4041 static int
4042 igb_add_5tuple_filter_82576(struct rte_eth_dev *dev,
4043                         struct rte_eth_ntuple_filter *ntuple_filter)
4044 {
4045         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4046         struct e1000_filter_info *filter_info =
4047                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4048         struct e1000_5tuple_filter *filter;
4049         uint32_t ftqf = E1000_FTQF_VF_BP | E1000_FTQF_MASK;
4050         uint32_t spqf, imir, imir_ext = E1000_IMIREXT_SIZE_BP;
4051         uint8_t i;
4052         int ret;
4053
4054         filter = rte_zmalloc("e1000_5tuple_filter",
4055                         sizeof(struct e1000_5tuple_filter), 0);
4056         if (filter == NULL)
4057                 return -ENOMEM;
4058
4059         ret = ntuple_filter_to_5tuple_82576(ntuple_filter,
4060                                             &filter->filter_info);
4061         if (ret < 0) {
4062                 rte_free(filter);
4063                 return ret;
4064         }
4065
4066         if (igb_5tuple_filter_lookup_82576(&filter_info->fivetuple_list,
4067                                          &filter->filter_info) != NULL) {
4068                 PMD_DRV_LOG(ERR, "filter exists.");
4069                 rte_free(filter);
4070                 return -EEXIST;
4071         }
4072         filter->queue = ntuple_filter->queue;
4073
4074         /*
4075          * look for an unused 5tuple filter index,
4076          * and insert the filter to list.
4077          */
4078         for (i = 0; i < E1000_MAX_FTQF_FILTERS; i++) {
4079                 if (!(filter_info->fivetuple_mask & (1 << i))) {
4080                         filter_info->fivetuple_mask |= 1 << i;
4081                         filter->index = i;
4082                         TAILQ_INSERT_TAIL(&filter_info->fivetuple_list,
4083                                           filter,
4084                                           entries);
4085                         break;
4086                 }
4087         }
4088         if (i >= E1000_MAX_FTQF_FILTERS) {
4089                 PMD_DRV_LOG(ERR, "5tuple filters are full.");
4090                 rte_free(filter);
4091                 return -ENOSYS;
4092         }
4093
4094         ftqf |= filter->filter_info.proto & E1000_FTQF_PROTOCOL_MASK;
4095         if (filter->filter_info.src_ip_mask == 0) /* 0b means compare. */
4096                 ftqf &= ~E1000_FTQF_MASK_SOURCE_ADDR_BP;
4097         if (filter->filter_info.dst_ip_mask == 0)
4098                 ftqf &= ~E1000_FTQF_MASK_DEST_ADDR_BP;
4099         if (filter->filter_info.src_port_mask == 0)
4100                 ftqf &= ~E1000_FTQF_MASK_SOURCE_PORT_BP;
4101         if (filter->filter_info.proto_mask == 0)
4102                 ftqf &= ~E1000_FTQF_MASK_PROTO_BP;
4103         ftqf |= (filter->queue << E1000_FTQF_QUEUE_SHIFT) &
4104                 E1000_FTQF_QUEUE_MASK;
4105         ftqf |= E1000_FTQF_QUEUE_ENABLE;
4106         E1000_WRITE_REG(hw, E1000_FTQF(i), ftqf);
4107         E1000_WRITE_REG(hw, E1000_DAQF(i), filter->filter_info.dst_ip);
4108         E1000_WRITE_REG(hw, E1000_SAQF(i), filter->filter_info.src_ip);
4109
4110         spqf = filter->filter_info.src_port & E1000_SPQF_SRCPORT;
4111         E1000_WRITE_REG(hw, E1000_SPQF(i), spqf);
4112
4113         imir = (uint32_t)(filter->filter_info.dst_port & E1000_IMIR_DSTPORT);
4114         if (filter->filter_info.dst_port_mask == 1) /* 1b means not compare. */
4115                 imir |= E1000_IMIR_PORT_BP;
4116         else
4117                 imir &= ~E1000_IMIR_PORT_BP;
4118         imir |= filter->filter_info.priority << E1000_IMIR_PRIORITY_SHIFT;
4119
4120         /* tcp flags bits setting. */
4121         if (filter->filter_info.tcp_flags & TCP_FLAG_ALL) {
4122                 if (filter->filter_info.tcp_flags & TCP_URG_FLAG)
4123                         imir_ext |= E1000_IMIREXT_CTRL_URG;
4124                 if (filter->filter_info.tcp_flags & TCP_ACK_FLAG)
4125                         imir_ext |= E1000_IMIREXT_CTRL_ACK;
4126                 if (filter->filter_info.tcp_flags & TCP_PSH_FLAG)
4127                         imir_ext |= E1000_IMIREXT_CTRL_PSH;
4128                 if (filter->filter_info.tcp_flags & TCP_RST_FLAG)
4129                         imir_ext |= E1000_IMIREXT_CTRL_RST;
4130                 if (filter->filter_info.tcp_flags & TCP_SYN_FLAG)
4131                         imir_ext |= E1000_IMIREXT_CTRL_SYN;
4132                 if (filter->filter_info.tcp_flags & TCP_FIN_FLAG)
4133                         imir_ext |= E1000_IMIREXT_CTRL_FIN;
4134         } else
4135                 imir_ext |= E1000_IMIREXT_CTRL_BP;
4136         E1000_WRITE_REG(hw, E1000_IMIR(i), imir);
4137         E1000_WRITE_REG(hw, E1000_IMIREXT(i), imir_ext);
4138         return 0;
4139 }
4140
4141 /*
4142  * igb_remove_5tuple_filter_82576 - remove a 5tuple filter
4143  *
4144  * @param
4145  * dev: Pointer to struct rte_eth_dev.
4146  * ntuple_filter: ponter to the filter that will be removed.
4147  *
4148  * @return
4149  *    - On success, zero.
4150  *    - On failure, a negative value.
4151  */
4152 static int
4153 igb_remove_5tuple_filter_82576(struct rte_eth_dev *dev,
4154                                 struct rte_eth_ntuple_filter *ntuple_filter)
4155 {
4156         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4157         struct e1000_filter_info *filter_info =
4158                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4159         struct e1000_5tuple_filter_info filter_5tuple;
4160         struct e1000_5tuple_filter *filter;
4161         int ret;
4162
4163         memset(&filter_5tuple, 0, sizeof(struct e1000_5tuple_filter_info));
4164         ret = ntuple_filter_to_5tuple_82576(ntuple_filter,
4165                                             &filter_5tuple);
4166         if (ret < 0)
4167                 return ret;
4168
4169         filter = igb_5tuple_filter_lookup_82576(&filter_info->fivetuple_list,
4170                                          &filter_5tuple);
4171         if (filter == NULL) {
4172                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
4173                 return -ENOENT;
4174         }
4175
4176         filter_info->fivetuple_mask &= ~(1 << filter->index);
4177         TAILQ_REMOVE(&filter_info->fivetuple_list, filter, entries);
4178         rte_free(filter);
4179
4180         E1000_WRITE_REG(hw, E1000_FTQF(filter->index),
4181                         E1000_FTQF_VF_BP | E1000_FTQF_MASK);
4182         E1000_WRITE_REG(hw, E1000_DAQF(filter->index), 0);
4183         E1000_WRITE_REG(hw, E1000_SAQF(filter->index), 0);
4184         E1000_WRITE_REG(hw, E1000_SPQF(filter->index), 0);
4185         E1000_WRITE_REG(hw, E1000_IMIR(filter->index), 0);
4186         E1000_WRITE_REG(hw, E1000_IMIREXT(filter->index), 0);
4187         return 0;
4188 }
4189
4190 static int
4191 eth_igb_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
4192 {
4193         uint32_t rctl;
4194         struct e1000_hw *hw;
4195         struct rte_eth_dev_info dev_info;
4196         uint32_t frame_size = mtu + (ETHER_HDR_LEN + ETHER_CRC_LEN +
4197                                      VLAN_TAG_SIZE);
4198
4199         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4200
4201 #ifdef RTE_LIBRTE_82571_SUPPORT
4202         /* XXX: not bigger than max_rx_pktlen */
4203         if (hw->mac.type == e1000_82571)
4204                 return -ENOTSUP;
4205 #endif
4206         eth_igb_infos_get(dev, &dev_info);
4207
4208         /* check that mtu is within the allowed range */
4209         if ((mtu < ETHER_MIN_MTU) ||
4210             (frame_size > dev_info.max_rx_pktlen))
4211                 return -EINVAL;
4212
4213         /* refuse mtu that requires the support of scattered packets when this
4214          * feature has not been enabled before. */
4215         if (!dev->data->scattered_rx &&
4216             frame_size > dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)
4217                 return -EINVAL;
4218
4219         rctl = E1000_READ_REG(hw, E1000_RCTL);
4220
4221         /* switch to jumbo mode if needed */
4222         if (frame_size > ETHER_MAX_LEN) {
4223                 dev->data->dev_conf.rxmode.jumbo_frame = 1;
4224                 rctl |= E1000_RCTL_LPE;
4225         } else {
4226                 dev->data->dev_conf.rxmode.jumbo_frame = 0;
4227                 rctl &= ~E1000_RCTL_LPE;
4228         }
4229         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
4230
4231         /* update max frame size */
4232         dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
4233
4234         E1000_WRITE_REG(hw, E1000_RLPML,
4235                         dev->data->dev_conf.rxmode.max_rx_pkt_len);
4236
4237         return 0;
4238 }
4239
4240 /*
4241  * igb_add_del_ntuple_filter - add or delete a ntuple filter
4242  *
4243  * @param
4244  * dev: Pointer to struct rte_eth_dev.
4245  * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
4246  * add: if true, add filter, if false, remove filter
4247  *
4248  * @return
4249  *    - On success, zero.
4250  *    - On failure, a negative value.
4251  */
4252 static int
4253 igb_add_del_ntuple_filter(struct rte_eth_dev *dev,
4254                         struct rte_eth_ntuple_filter *ntuple_filter,
4255                         bool add)
4256 {
4257         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4258         int ret;
4259
4260         switch (ntuple_filter->flags) {
4261         case RTE_5TUPLE_FLAGS:
4262         case (RTE_5TUPLE_FLAGS | RTE_NTUPLE_FLAGS_TCP_FLAG):
4263                 if (hw->mac.type != e1000_82576)
4264                         return -ENOTSUP;
4265                 if (add)
4266                         ret = igb_add_5tuple_filter_82576(dev,
4267                                                           ntuple_filter);
4268                 else
4269                         ret = igb_remove_5tuple_filter_82576(dev,
4270                                                              ntuple_filter);
4271                 break;
4272         case RTE_2TUPLE_FLAGS:
4273         case (RTE_2TUPLE_FLAGS | RTE_NTUPLE_FLAGS_TCP_FLAG):
4274                 if (hw->mac.type != e1000_82580 && hw->mac.type != e1000_i350)
4275                         return -ENOTSUP;
4276                 if (add)
4277                         ret = igb_add_2tuple_filter(dev, ntuple_filter);
4278                 else
4279                         ret = igb_remove_2tuple_filter(dev, ntuple_filter);
4280                 break;
4281         default:
4282                 ret = -EINVAL;
4283                 break;
4284         }
4285
4286         return ret;
4287 }
4288
4289 /*
4290  * igb_get_ntuple_filter - get a ntuple filter
4291  *
4292  * @param
4293  * dev: Pointer to struct rte_eth_dev.
4294  * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
4295  *
4296  * @return
4297  *    - On success, zero.
4298  *    - On failure, a negative value.
4299  */
4300 static int
4301 igb_get_ntuple_filter(struct rte_eth_dev *dev,
4302                         struct rte_eth_ntuple_filter *ntuple_filter)
4303 {
4304         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4305         struct e1000_filter_info *filter_info =
4306                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4307         struct e1000_5tuple_filter_info filter_5tuple;
4308         struct e1000_2tuple_filter_info filter_2tuple;
4309         struct e1000_5tuple_filter *p_5tuple_filter;
4310         struct e1000_2tuple_filter *p_2tuple_filter;
4311         int ret;
4312
4313         switch (ntuple_filter->flags) {
4314         case RTE_5TUPLE_FLAGS:
4315         case (RTE_5TUPLE_FLAGS | RTE_NTUPLE_FLAGS_TCP_FLAG):
4316                 if (hw->mac.type != e1000_82576)
4317                         return -ENOTSUP;
4318                 memset(&filter_5tuple,
4319                         0,
4320                         sizeof(struct e1000_5tuple_filter_info));
4321                 ret = ntuple_filter_to_5tuple_82576(ntuple_filter,
4322                                                     &filter_5tuple);
4323                 if (ret < 0)
4324                         return ret;
4325                 p_5tuple_filter = igb_5tuple_filter_lookup_82576(
4326                                         &filter_info->fivetuple_list,
4327                                         &filter_5tuple);
4328                 if (p_5tuple_filter == NULL) {
4329                         PMD_DRV_LOG(ERR, "filter doesn't exist.");
4330                         return -ENOENT;
4331                 }
4332                 ntuple_filter->queue = p_5tuple_filter->queue;
4333                 break;
4334         case RTE_2TUPLE_FLAGS:
4335         case (RTE_2TUPLE_FLAGS | RTE_NTUPLE_FLAGS_TCP_FLAG):
4336                 if (hw->mac.type != e1000_82580 && hw->mac.type != e1000_i350)
4337                         return -ENOTSUP;
4338                 memset(&filter_2tuple,
4339                         0,
4340                         sizeof(struct e1000_2tuple_filter_info));
4341                 ret = ntuple_filter_to_2tuple(ntuple_filter, &filter_2tuple);
4342                 if (ret < 0)
4343                         return ret;
4344                 p_2tuple_filter = igb_2tuple_filter_lookup(
4345                                         &filter_info->twotuple_list,
4346                                         &filter_2tuple);
4347                 if (p_2tuple_filter == NULL) {
4348                         PMD_DRV_LOG(ERR, "filter doesn't exist.");
4349                         return -ENOENT;
4350                 }
4351                 ntuple_filter->queue = p_2tuple_filter->queue;
4352                 break;
4353         default:
4354                 ret = -EINVAL;
4355                 break;
4356         }
4357
4358         return 0;
4359 }
4360
4361 /*
4362  * igb_ntuple_filter_handle - Handle operations for ntuple filter.
4363  * @dev: pointer to rte_eth_dev structure
4364  * @filter_op:operation will be taken.
4365  * @arg: a pointer to specific structure corresponding to the filter_op
4366  */
4367 static int
4368 igb_ntuple_filter_handle(struct rte_eth_dev *dev,
4369                                 enum rte_filter_op filter_op,
4370                                 void *arg)
4371 {
4372         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4373         int ret;
4374
4375         MAC_TYPE_FILTER_SUP(hw->mac.type);
4376
4377         if (filter_op == RTE_ETH_FILTER_NOP)
4378                 return 0;
4379
4380         if (arg == NULL) {
4381                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
4382                             filter_op);
4383                 return -EINVAL;
4384         }
4385
4386         switch (filter_op) {
4387         case RTE_ETH_FILTER_ADD:
4388                 ret = igb_add_del_ntuple_filter(dev,
4389                         (struct rte_eth_ntuple_filter *)arg,
4390                         TRUE);
4391                 break;
4392         case RTE_ETH_FILTER_DELETE:
4393                 ret = igb_add_del_ntuple_filter(dev,
4394                         (struct rte_eth_ntuple_filter *)arg,
4395                         FALSE);
4396                 break;
4397         case RTE_ETH_FILTER_GET:
4398                 ret = igb_get_ntuple_filter(dev,
4399                         (struct rte_eth_ntuple_filter *)arg);
4400                 break;
4401         default:
4402                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
4403                 ret = -EINVAL;
4404                 break;
4405         }
4406         return ret;
4407 }
4408
4409 static inline int
4410 igb_ethertype_filter_lookup(struct e1000_filter_info *filter_info,
4411                         uint16_t ethertype)
4412 {
4413         int i;
4414
4415         for (i = 0; i < E1000_MAX_ETQF_FILTERS; i++) {
4416                 if (filter_info->ethertype_filters[i] == ethertype &&
4417                     (filter_info->ethertype_mask & (1 << i)))
4418                         return i;
4419         }
4420         return -1;
4421 }
4422
4423 static inline int
4424 igb_ethertype_filter_insert(struct e1000_filter_info *filter_info,
4425                         uint16_t ethertype)
4426 {
4427         int i;
4428
4429         for (i = 0; i < E1000_MAX_ETQF_FILTERS; i++) {
4430                 if (!(filter_info->ethertype_mask & (1 << i))) {
4431                         filter_info->ethertype_mask |= 1 << i;
4432                         filter_info->ethertype_filters[i] = ethertype;
4433                         return i;
4434                 }
4435         }
4436         return -1;
4437 }
4438
4439 static inline int
4440 igb_ethertype_filter_remove(struct e1000_filter_info *filter_info,
4441                         uint8_t idx)
4442 {
4443         if (idx >= E1000_MAX_ETQF_FILTERS)
4444                 return -1;
4445         filter_info->ethertype_mask &= ~(1 << idx);
4446         filter_info->ethertype_filters[idx] = 0;
4447         return idx;
4448 }
4449
4450
4451 static int
4452 igb_add_del_ethertype_filter(struct rte_eth_dev *dev,
4453                         struct rte_eth_ethertype_filter *filter,
4454                         bool add)
4455 {
4456         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4457         struct e1000_filter_info *filter_info =
4458                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4459         uint32_t etqf = 0;
4460         int ret;
4461
4462         if (filter->ether_type == ETHER_TYPE_IPv4 ||
4463                 filter->ether_type == ETHER_TYPE_IPv6) {
4464                 PMD_DRV_LOG(ERR, "unsupported ether_type(0x%04x) in"
4465                         " ethertype filter.", filter->ether_type);
4466                 return -EINVAL;
4467         }
4468
4469         if (filter->flags & RTE_ETHTYPE_FLAGS_MAC) {
4470                 PMD_DRV_LOG(ERR, "mac compare is unsupported.");
4471                 return -EINVAL;
4472         }
4473         if (filter->flags & RTE_ETHTYPE_FLAGS_DROP) {
4474                 PMD_DRV_LOG(ERR, "drop option is unsupported.");
4475                 return -EINVAL;
4476         }
4477
4478         ret = igb_ethertype_filter_lookup(filter_info, filter->ether_type);
4479         if (ret >= 0 && add) {
4480                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter exists.",
4481                             filter->ether_type);
4482                 return -EEXIST;
4483         }
4484         if (ret < 0 && !add) {
4485                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
4486                             filter->ether_type);
4487                 return -ENOENT;
4488         }
4489
4490         if (add) {
4491                 ret = igb_ethertype_filter_insert(filter_info,
4492                         filter->ether_type);
4493                 if (ret < 0) {
4494                         PMD_DRV_LOG(ERR, "ethertype filters are full.");
4495                         return -ENOSYS;
4496                 }
4497
4498                 etqf |= E1000_ETQF_FILTER_ENABLE | E1000_ETQF_QUEUE_ENABLE;
4499                 etqf |= (uint32_t)(filter->ether_type & E1000_ETQF_ETHERTYPE);
4500                 etqf |= filter->queue << E1000_ETQF_QUEUE_SHIFT;
4501         } else {
4502                 ret = igb_ethertype_filter_remove(filter_info, (uint8_t)ret);
4503                 if (ret < 0)
4504                         return -ENOSYS;
4505         }
4506         E1000_WRITE_REG(hw, E1000_ETQF(ret), etqf);
4507         E1000_WRITE_FLUSH(hw);
4508
4509         return 0;
4510 }
4511
4512 static int
4513 igb_get_ethertype_filter(struct rte_eth_dev *dev,
4514                         struct rte_eth_ethertype_filter *filter)
4515 {
4516         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4517         struct e1000_filter_info *filter_info =
4518                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4519         uint32_t etqf;
4520         int ret;
4521
4522         ret = igb_ethertype_filter_lookup(filter_info, filter->ether_type);
4523         if (ret < 0) {
4524                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
4525                             filter->ether_type);
4526                 return -ENOENT;
4527         }
4528
4529         etqf = E1000_READ_REG(hw, E1000_ETQF(ret));
4530         if (etqf & E1000_ETQF_FILTER_ENABLE) {
4531                 filter->ether_type = etqf & E1000_ETQF_ETHERTYPE;
4532                 filter->flags = 0;
4533                 filter->queue = (etqf & E1000_ETQF_QUEUE) >>
4534                                 E1000_ETQF_QUEUE_SHIFT;
4535                 return 0;
4536         }
4537
4538         return -ENOENT;
4539 }
4540
4541 /*
4542  * igb_ethertype_filter_handle - Handle operations for ethertype filter.
4543  * @dev: pointer to rte_eth_dev structure
4544  * @filter_op:operation will be taken.
4545  * @arg: a pointer to specific structure corresponding to the filter_op
4546  */
4547 static int
4548 igb_ethertype_filter_handle(struct rte_eth_dev *dev,
4549                                 enum rte_filter_op filter_op,
4550                                 void *arg)
4551 {
4552         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4553         int ret;
4554
4555         MAC_TYPE_FILTER_SUP(hw->mac.type);
4556
4557         if (filter_op == RTE_ETH_FILTER_NOP)
4558                 return 0;
4559
4560         if (arg == NULL) {
4561                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
4562                             filter_op);
4563                 return -EINVAL;
4564         }
4565
4566         switch (filter_op) {
4567         case RTE_ETH_FILTER_ADD:
4568                 ret = igb_add_del_ethertype_filter(dev,
4569                         (struct rte_eth_ethertype_filter *)arg,
4570                         TRUE);
4571                 break;
4572         case RTE_ETH_FILTER_DELETE:
4573                 ret = igb_add_del_ethertype_filter(dev,
4574                         (struct rte_eth_ethertype_filter *)arg,
4575                         FALSE);
4576                 break;
4577         case RTE_ETH_FILTER_GET:
4578                 ret = igb_get_ethertype_filter(dev,
4579                         (struct rte_eth_ethertype_filter *)arg);
4580                 break;
4581         default:
4582                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
4583                 ret = -EINVAL;
4584                 break;
4585         }
4586         return ret;
4587 }
4588
4589 static int
4590 eth_igb_filter_ctrl(struct rte_eth_dev *dev,
4591                      enum rte_filter_type filter_type,
4592                      enum rte_filter_op filter_op,
4593                      void *arg)
4594 {
4595         int ret = -EINVAL;
4596
4597         switch (filter_type) {
4598         case RTE_ETH_FILTER_NTUPLE:
4599                 ret = igb_ntuple_filter_handle(dev, filter_op, arg);
4600                 break;
4601         case RTE_ETH_FILTER_ETHERTYPE:
4602                 ret = igb_ethertype_filter_handle(dev, filter_op, arg);
4603                 break;
4604         case RTE_ETH_FILTER_SYN:
4605                 ret = eth_igb_syn_filter_handle(dev, filter_op, arg);
4606                 break;
4607         case RTE_ETH_FILTER_FLEXIBLE:
4608                 ret = eth_igb_flex_filter_handle(dev, filter_op, arg);
4609                 break;
4610         default:
4611                 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
4612                                                         filter_type);
4613                 break;
4614         }
4615
4616         return ret;
4617 }
4618
4619 static int
4620 eth_igb_set_mc_addr_list(struct rte_eth_dev *dev,
4621                          struct ether_addr *mc_addr_set,
4622                          uint32_t nb_mc_addr)
4623 {
4624         struct e1000_hw *hw;
4625
4626         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4627         e1000_update_mc_addr_list(hw, (u8 *)mc_addr_set, nb_mc_addr);
4628         return 0;
4629 }
4630
4631 static uint64_t
4632 igb_read_systime_cyclecounter(struct rte_eth_dev *dev)
4633 {
4634         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4635         uint64_t systime_cycles;
4636
4637         switch (hw->mac.type) {
4638         case e1000_i210:
4639         case e1000_i211:
4640                 /*
4641                  * Need to read System Time Residue Register to be able
4642                  * to read the other two registers.
4643                  */
4644                 E1000_READ_REG(hw, E1000_SYSTIMR);
4645                 /* SYSTIMEL stores ns and SYSTIMEH stores seconds. */
4646                 systime_cycles = (uint64_t)E1000_READ_REG(hw, E1000_SYSTIML);
4647                 systime_cycles += (uint64_t)E1000_READ_REG(hw, E1000_SYSTIMH)
4648                                 * NSEC_PER_SEC;
4649                 break;
4650         case e1000_82580:
4651         case e1000_i350:
4652         case e1000_i354:
4653                 /*
4654                  * Need to read System Time Residue Register to be able
4655                  * to read the other two registers.
4656                  */
4657                 E1000_READ_REG(hw, E1000_SYSTIMR);
4658                 systime_cycles = (uint64_t)E1000_READ_REG(hw, E1000_SYSTIML);
4659                 /* Only the 8 LSB are valid. */
4660                 systime_cycles |= (uint64_t)(E1000_READ_REG(hw, E1000_SYSTIMH)
4661                                 & 0xff) << 32;
4662                 break;
4663         default:
4664                 systime_cycles = (uint64_t)E1000_READ_REG(hw, E1000_SYSTIML);
4665                 systime_cycles |= (uint64_t)E1000_READ_REG(hw, E1000_SYSTIMH)
4666                                 << 32;
4667                 break;
4668         }
4669
4670         return systime_cycles;
4671 }
4672
4673 static uint64_t
4674 igb_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev)
4675 {
4676         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4677         uint64_t rx_tstamp_cycles;
4678
4679         switch (hw->mac.type) {
4680         case e1000_i210:
4681         case e1000_i211:
4682                 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
4683                 rx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_RXSTMPL);
4684                 rx_tstamp_cycles += (uint64_t)E1000_READ_REG(hw, E1000_RXSTMPH)
4685                                 * NSEC_PER_SEC;
4686                 break;
4687         case e1000_82580:
4688         case e1000_i350:
4689         case e1000_i354:
4690                 rx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_RXSTMPL);
4691                 /* Only the 8 LSB are valid. */
4692                 rx_tstamp_cycles |= (uint64_t)(E1000_READ_REG(hw, E1000_RXSTMPH)
4693                                 & 0xff) << 32;
4694                 break;
4695         default:
4696                 rx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_RXSTMPL);
4697                 rx_tstamp_cycles |= (uint64_t)E1000_READ_REG(hw, E1000_RXSTMPH)
4698                                 << 32;
4699                 break;
4700         }
4701
4702         return rx_tstamp_cycles;
4703 }
4704
4705 static uint64_t
4706 igb_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev)
4707 {
4708         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4709         uint64_t tx_tstamp_cycles;
4710
4711         switch (hw->mac.type) {
4712         case e1000_i210:
4713         case e1000_i211:
4714                 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
4715                 tx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_TXSTMPL);
4716                 tx_tstamp_cycles += (uint64_t)E1000_READ_REG(hw, E1000_TXSTMPH)
4717                                 * NSEC_PER_SEC;
4718                 break;
4719         case e1000_82580:
4720         case e1000_i350:
4721         case e1000_i354:
4722                 tx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_TXSTMPL);
4723                 /* Only the 8 LSB are valid. */
4724                 tx_tstamp_cycles |= (uint64_t)(E1000_READ_REG(hw, E1000_TXSTMPH)
4725                                 & 0xff) << 32;
4726                 break;
4727         default:
4728                 tx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_TXSTMPL);
4729                 tx_tstamp_cycles |= (uint64_t)E1000_READ_REG(hw, E1000_TXSTMPH)
4730                                 << 32;
4731                 break;
4732         }
4733
4734         return tx_tstamp_cycles;
4735 }
4736
4737 static void
4738 igb_start_timecounters(struct rte_eth_dev *dev)
4739 {
4740         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4741         struct e1000_adapter *adapter =
4742                 (struct e1000_adapter *)dev->data->dev_private;
4743         uint32_t incval = 1;
4744         uint32_t shift = 0;
4745         uint64_t mask = E1000_CYCLECOUNTER_MASK;
4746
4747         switch (hw->mac.type) {
4748         case e1000_82580:
4749         case e1000_i350:
4750         case e1000_i354:
4751                 /* 32 LSB bits + 8 MSB bits = 40 bits */
4752                 mask = (1ULL << 40) - 1;
4753                 /* fall-through */
4754         case e1000_i210:
4755         case e1000_i211:
4756                 /*
4757                  * Start incrementing the register
4758                  * used to timestamp PTP packets.
4759                  */
4760                 E1000_WRITE_REG(hw, E1000_TIMINCA, incval);
4761                 break;
4762         case e1000_82576:
4763                 incval = E1000_INCVALUE_82576;
4764                 shift = IGB_82576_TSYNC_SHIFT;
4765                 E1000_WRITE_REG(hw, E1000_TIMINCA,
4766                                 E1000_INCPERIOD_82576 | incval);
4767                 break;
4768         default:
4769                 /* Not supported */
4770                 return;
4771         }
4772
4773         memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter));
4774         memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
4775         memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
4776
4777         adapter->systime_tc.cc_mask = mask;
4778         adapter->systime_tc.cc_shift = shift;
4779         adapter->systime_tc.nsec_mask = (1ULL << shift) - 1;
4780
4781         adapter->rx_tstamp_tc.cc_mask = mask;
4782         adapter->rx_tstamp_tc.cc_shift = shift;
4783         adapter->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
4784
4785         adapter->tx_tstamp_tc.cc_mask = mask;
4786         adapter->tx_tstamp_tc.cc_shift = shift;
4787         adapter->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
4788 }
4789
4790 static int
4791 igb_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
4792 {
4793         struct e1000_adapter *adapter =
4794                         (struct e1000_adapter *)dev->data->dev_private;
4795
4796         adapter->systime_tc.nsec += delta;
4797         adapter->rx_tstamp_tc.nsec += delta;
4798         adapter->tx_tstamp_tc.nsec += delta;
4799
4800         return 0;
4801 }
4802
4803 static int
4804 igb_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
4805 {
4806         uint64_t ns;
4807         struct e1000_adapter *adapter =
4808                         (struct e1000_adapter *)dev->data->dev_private;
4809
4810         ns = rte_timespec_to_ns(ts);
4811
4812         /* Set the timecounters to a new value. */
4813         adapter->systime_tc.nsec = ns;
4814         adapter->rx_tstamp_tc.nsec = ns;
4815         adapter->tx_tstamp_tc.nsec = ns;
4816
4817         return 0;
4818 }
4819
4820 static int
4821 igb_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
4822 {
4823         uint64_t ns, systime_cycles;
4824         struct e1000_adapter *adapter =
4825                         (struct e1000_adapter *)dev->data->dev_private;
4826
4827         systime_cycles = igb_read_systime_cyclecounter(dev);
4828         ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles);
4829         *ts = rte_ns_to_timespec(ns);
4830
4831         return 0;
4832 }
4833
4834 static int
4835 igb_timesync_enable(struct rte_eth_dev *dev)
4836 {
4837         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4838         uint32_t tsync_ctl;
4839         uint32_t tsauxc;
4840
4841         /* Stop the timesync system time. */
4842         E1000_WRITE_REG(hw, E1000_TIMINCA, 0x0);
4843         /* Reset the timesync system time value. */
4844         switch (hw->mac.type) {
4845         case e1000_82580:
4846         case e1000_i350:
4847         case e1000_i354:
4848         case e1000_i210:
4849         case e1000_i211:
4850                 E1000_WRITE_REG(hw, E1000_SYSTIMR, 0x0);
4851                 /* fall-through */
4852         case e1000_82576:
4853                 E1000_WRITE_REG(hw, E1000_SYSTIML, 0x0);
4854                 E1000_WRITE_REG(hw, E1000_SYSTIMH, 0x0);
4855                 break;
4856         default:
4857                 /* Not supported. */
4858                 return -ENOTSUP;
4859         }
4860
4861         /* Enable system time for it isn't on by default. */
4862         tsauxc = E1000_READ_REG(hw, E1000_TSAUXC);
4863         tsauxc &= ~E1000_TSAUXC_DISABLE_SYSTIME;
4864         E1000_WRITE_REG(hw, E1000_TSAUXC, tsauxc);
4865
4866         igb_start_timecounters(dev);
4867
4868         /* Enable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
4869         E1000_WRITE_REG(hw, E1000_ETQF(E1000_ETQF_FILTER_1588),
4870                         (ETHER_TYPE_1588 |
4871                          E1000_ETQF_FILTER_ENABLE |
4872                          E1000_ETQF_1588));
4873
4874         /* Enable timestamping of received PTP packets. */
4875         tsync_ctl = E1000_READ_REG(hw, E1000_TSYNCRXCTL);
4876         tsync_ctl |= E1000_TSYNCRXCTL_ENABLED;
4877         E1000_WRITE_REG(hw, E1000_TSYNCRXCTL, tsync_ctl);
4878
4879         /* Enable Timestamping of transmitted PTP packets. */
4880         tsync_ctl = E1000_READ_REG(hw, E1000_TSYNCTXCTL);
4881         tsync_ctl |= E1000_TSYNCTXCTL_ENABLED;
4882         E1000_WRITE_REG(hw, E1000_TSYNCTXCTL, tsync_ctl);
4883
4884         return 0;
4885 }
4886
4887 static int
4888 igb_timesync_disable(struct rte_eth_dev *dev)
4889 {
4890         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4891         uint32_t tsync_ctl;
4892
4893         /* Disable timestamping of transmitted PTP packets. */
4894         tsync_ctl = E1000_READ_REG(hw, E1000_TSYNCTXCTL);
4895         tsync_ctl &= ~E1000_TSYNCTXCTL_ENABLED;
4896         E1000_WRITE_REG(hw, E1000_TSYNCTXCTL, tsync_ctl);
4897
4898         /* Disable timestamping of received PTP packets. */
4899         tsync_ctl = E1000_READ_REG(hw, E1000_TSYNCRXCTL);
4900         tsync_ctl &= ~E1000_TSYNCRXCTL_ENABLED;
4901         E1000_WRITE_REG(hw, E1000_TSYNCRXCTL, tsync_ctl);
4902
4903         /* Disable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
4904         E1000_WRITE_REG(hw, E1000_ETQF(E1000_ETQF_FILTER_1588), 0);
4905
4906         /* Stop incrementating the System Time registers. */
4907         E1000_WRITE_REG(hw, E1000_TIMINCA, 0);
4908
4909         return 0;
4910 }
4911
4912 static int
4913 igb_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
4914                                struct timespec *timestamp,
4915                                uint32_t flags __rte_unused)
4916 {
4917         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4918         struct e1000_adapter *adapter =
4919                         (struct e1000_adapter *)dev->data->dev_private;
4920         uint32_t tsync_rxctl;
4921         uint64_t rx_tstamp_cycles;
4922         uint64_t ns;
4923
4924         tsync_rxctl = E1000_READ_REG(hw, E1000_TSYNCRXCTL);
4925         if ((tsync_rxctl & E1000_TSYNCRXCTL_VALID) == 0)
4926                 return -EINVAL;
4927
4928         rx_tstamp_cycles = igb_read_rx_tstamp_cyclecounter(dev);
4929         ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles);
4930         *timestamp = rte_ns_to_timespec(ns);
4931
4932         return  0;
4933 }
4934
4935 static int
4936 igb_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
4937                                struct timespec *timestamp)
4938 {
4939         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4940         struct e1000_adapter *adapter =
4941                         (struct e1000_adapter *)dev->data->dev_private;
4942         uint32_t tsync_txctl;
4943         uint64_t tx_tstamp_cycles;
4944         uint64_t ns;
4945
4946         tsync_txctl = E1000_READ_REG(hw, E1000_TSYNCTXCTL);
4947         if ((tsync_txctl & E1000_TSYNCTXCTL_VALID) == 0)
4948                 return -EINVAL;
4949
4950         tx_tstamp_cycles = igb_read_tx_tstamp_cyclecounter(dev);
4951         ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles);
4952         *timestamp = rte_ns_to_timespec(ns);
4953
4954         return  0;
4955 }
4956
4957 static int
4958 eth_igb_get_reg_length(struct rte_eth_dev *dev __rte_unused)
4959 {
4960         int count = 0;
4961         int g_ind = 0;
4962         const struct reg_info *reg_group;
4963
4964         while ((reg_group = igb_regs[g_ind++]))
4965                 count += igb_reg_group_count(reg_group);
4966
4967         return count;
4968 }
4969
4970 static int
4971 igbvf_get_reg_length(struct rte_eth_dev *dev __rte_unused)
4972 {
4973         int count = 0;
4974         int g_ind = 0;
4975         const struct reg_info *reg_group;
4976
4977         while ((reg_group = igbvf_regs[g_ind++]))
4978                 count += igb_reg_group_count(reg_group);
4979
4980         return count;
4981 }
4982
4983 static int
4984 eth_igb_get_regs(struct rte_eth_dev *dev,
4985         struct rte_dev_reg_info *regs)
4986 {
4987         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4988         uint32_t *data = regs->data;
4989         int g_ind = 0;
4990         int count = 0;
4991         const struct reg_info *reg_group;
4992
4993         if (data == NULL) {
4994                 regs->length = eth_igb_get_reg_length(dev);
4995                 regs->width = sizeof(uint32_t);
4996                 return 0;
4997         }
4998
4999         /* Support only full register dump */
5000         if ((regs->length == 0) ||
5001             (regs->length == (uint32_t)eth_igb_get_reg_length(dev))) {
5002                 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
5003                         hw->device_id;
5004                 while ((reg_group = igb_regs[g_ind++]))
5005                         count += igb_read_regs_group(dev, &data[count],
5006                                                         reg_group);
5007                 return 0;
5008         }
5009
5010         return -ENOTSUP;
5011 }
5012
5013 static int
5014 igbvf_get_regs(struct rte_eth_dev *dev,
5015         struct rte_dev_reg_info *regs)
5016 {
5017         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5018         uint32_t *data = regs->data;
5019         int g_ind = 0;
5020         int count = 0;
5021         const struct reg_info *reg_group;
5022
5023         if (data == NULL) {
5024                 regs->length = igbvf_get_reg_length(dev);
5025                 regs->width = sizeof(uint32_t);
5026                 return 0;
5027         }
5028
5029         /* Support only full register dump */
5030         if ((regs->length == 0) ||
5031             (regs->length == (uint32_t)igbvf_get_reg_length(dev))) {
5032                 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
5033                         hw->device_id;
5034                 while ((reg_group = igbvf_regs[g_ind++]))
5035                         count += igb_read_regs_group(dev, &data[count],
5036                                                         reg_group);
5037                 return 0;
5038         }
5039
5040         return -ENOTSUP;
5041 }
5042
5043 static int
5044 eth_igb_get_eeprom_length(struct rte_eth_dev *dev)
5045 {
5046         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5047
5048         /* Return unit is byte count */
5049         return hw->nvm.word_size * 2;
5050 }
5051
5052 static int
5053 eth_igb_get_eeprom(struct rte_eth_dev *dev,
5054         struct rte_dev_eeprom_info *in_eeprom)
5055 {
5056         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5057         struct e1000_nvm_info *nvm = &hw->nvm;
5058         uint16_t *data = in_eeprom->data;
5059         int first, length;
5060
5061         first = in_eeprom->offset >> 1;
5062         length = in_eeprom->length >> 1;
5063         if ((first >= hw->nvm.word_size) ||
5064             ((first + length) >= hw->nvm.word_size))
5065                 return -EINVAL;
5066
5067         in_eeprom->magic = hw->vendor_id |
5068                 ((uint32_t)hw->device_id << 16);
5069
5070         if ((nvm->ops.read) == NULL)
5071                 return -ENOTSUP;
5072
5073         return nvm->ops.read(hw, first, length, data);
5074 }
5075
5076 static int
5077 eth_igb_set_eeprom(struct rte_eth_dev *dev,
5078         struct rte_dev_eeprom_info *in_eeprom)
5079 {
5080         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5081         struct e1000_nvm_info *nvm = &hw->nvm;
5082         uint16_t *data = in_eeprom->data;
5083         int first, length;
5084
5085         first = in_eeprom->offset >> 1;
5086         length = in_eeprom->length >> 1;
5087         if ((first >= hw->nvm.word_size) ||
5088             ((first + length) >= hw->nvm.word_size))
5089                 return -EINVAL;
5090
5091         in_eeprom->magic = (uint32_t)hw->vendor_id |
5092                 ((uint32_t)hw->device_id << 16);
5093
5094         if ((nvm->ops.write) == NULL)
5095                 return -ENOTSUP;
5096         return nvm->ops.write(hw,  first, length, data);
5097 }
5098
5099 static int
5100 eth_igb_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
5101 {
5102         struct e1000_hw *hw =
5103                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5104         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
5105         uint32_t vec = E1000_MISC_VEC_ID;
5106
5107         if (rte_intr_allow_others(intr_handle))
5108                 vec = E1000_RX_VEC_START;
5109
5110         uint32_t mask = 1 << (queue_id + vec);
5111
5112         E1000_WRITE_REG(hw, E1000_EIMC, mask);
5113         E1000_WRITE_FLUSH(hw);
5114
5115         return 0;
5116 }
5117
5118 static int
5119 eth_igb_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
5120 {
5121         struct e1000_hw *hw =
5122                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5123         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
5124         uint32_t vec = E1000_MISC_VEC_ID;
5125
5126         if (rte_intr_allow_others(intr_handle))
5127                 vec = E1000_RX_VEC_START;
5128
5129         uint32_t mask = 1 << (queue_id + vec);
5130         uint32_t regval;
5131
5132         regval = E1000_READ_REG(hw, E1000_EIMS);
5133         E1000_WRITE_REG(hw, E1000_EIMS, regval | mask);
5134         E1000_WRITE_FLUSH(hw);
5135
5136         rte_intr_enable(&dev->pci_dev->intr_handle);
5137
5138         return 0;
5139 }
5140
5141 static void
5142 eth_igb_write_ivar(struct e1000_hw *hw, uint8_t  msix_vector,
5143                    uint8_t index, uint8_t offset)
5144 {
5145         uint32_t val = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index);
5146
5147         /* clear bits */
5148         val &= ~((uint32_t)0xFF << offset);
5149
5150         /* write vector and valid bit */
5151         val |= (msix_vector | E1000_IVAR_VALID) << offset;
5152
5153         E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, val);
5154 }
5155
5156 static void
5157 eth_igb_assign_msix_vector(struct e1000_hw *hw, int8_t direction,
5158                            uint8_t queue, uint8_t msix_vector)
5159 {
5160         uint32_t tmp = 0;
5161
5162         if (hw->mac.type == e1000_82575) {
5163                 if (direction == 0)
5164                         tmp = E1000_EICR_RX_QUEUE0 << queue;
5165                 else if (direction == 1)
5166                         tmp = E1000_EICR_TX_QUEUE0 << queue;
5167                 E1000_WRITE_REG(hw, E1000_MSIXBM(msix_vector), tmp);
5168         } else if (hw->mac.type == e1000_82576) {
5169                 if ((direction == 0) || (direction == 1))
5170                         eth_igb_write_ivar(hw, msix_vector, queue & 0x7,
5171                                            ((queue & 0x8) << 1) +
5172                                            8 * direction);
5173         } else if ((hw->mac.type == e1000_82580) ||
5174                         (hw->mac.type == e1000_i350) ||
5175                         (hw->mac.type == e1000_i354) ||
5176                         (hw->mac.type == e1000_i210) ||
5177                         (hw->mac.type == e1000_i211)) {
5178                 if ((direction == 0) || (direction == 1))
5179                         eth_igb_write_ivar(hw, msix_vector,
5180                                            queue >> 1,
5181                                            ((queue & 0x1) << 4) +
5182                                            8 * direction);
5183         }
5184 }
5185
5186 /* Sets up the hardware to generate MSI-X interrupts properly
5187  * @hw
5188  *  board private structure
5189  */
5190 static void
5191 eth_igb_configure_msix_intr(struct rte_eth_dev *dev)
5192 {
5193         int queue_id;
5194         uint32_t tmpval, regval, intr_mask;
5195         struct e1000_hw *hw =
5196                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5197         uint32_t vec = E1000_MISC_VEC_ID;
5198         uint32_t base = E1000_MISC_VEC_ID;
5199         uint32_t misc_shift = 0;
5200
5201         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
5202
5203         /* won't configure msix register if no mapping is done
5204          * between intr vector and event fd
5205          */
5206         if (!rte_intr_dp_is_en(intr_handle))
5207                 return;
5208
5209         if (rte_intr_allow_others(intr_handle)) {
5210                 vec = base = E1000_RX_VEC_START;
5211                 misc_shift = 1;
5212         }
5213
5214         /* set interrupt vector for other causes */
5215         if (hw->mac.type == e1000_82575) {
5216                 tmpval = E1000_READ_REG(hw, E1000_CTRL_EXT);
5217                 /* enable MSI-X PBA support */
5218                 tmpval |= E1000_CTRL_EXT_PBA_CLR;
5219
5220                 /* Auto-Mask interrupts upon ICR read */
5221                 tmpval |= E1000_CTRL_EXT_EIAME;
5222                 tmpval |= E1000_CTRL_EXT_IRCA;
5223
5224                 E1000_WRITE_REG(hw, E1000_CTRL_EXT, tmpval);
5225
5226                 /* enable msix_other interrupt */
5227                 E1000_WRITE_REG_ARRAY(hw, E1000_MSIXBM(0), 0, E1000_EIMS_OTHER);
5228                 regval = E1000_READ_REG(hw, E1000_EIAC);
5229                 E1000_WRITE_REG(hw, E1000_EIAC, regval | E1000_EIMS_OTHER);
5230                 regval = E1000_READ_REG(hw, E1000_EIAM);
5231                 E1000_WRITE_REG(hw, E1000_EIMS, regval | E1000_EIMS_OTHER);
5232         } else if ((hw->mac.type == e1000_82576) ||
5233                         (hw->mac.type == e1000_82580) ||
5234                         (hw->mac.type == e1000_i350) ||
5235                         (hw->mac.type == e1000_i354) ||
5236                         (hw->mac.type == e1000_i210) ||
5237                         (hw->mac.type == e1000_i211)) {
5238                 /* turn on MSI-X capability first */
5239                 E1000_WRITE_REG(hw, E1000_GPIE, E1000_GPIE_MSIX_MODE |
5240                                         E1000_GPIE_PBA | E1000_GPIE_EIAME |
5241                                         E1000_GPIE_NSICR);
5242                 intr_mask = RTE_LEN2MASK(intr_handle->nb_efd, uint32_t) <<
5243                         misc_shift;
5244                 regval = E1000_READ_REG(hw, E1000_EIAC);
5245                 E1000_WRITE_REG(hw, E1000_EIAC, regval | intr_mask);
5246
5247                 /* enable msix_other interrupt */
5248                 regval = E1000_READ_REG(hw, E1000_EIMS);
5249                 E1000_WRITE_REG(hw, E1000_EIMS, regval | intr_mask);
5250                 tmpval = (dev->data->nb_rx_queues | E1000_IVAR_VALID) << 8;
5251                 E1000_WRITE_REG(hw, E1000_IVAR_MISC, tmpval);
5252         }
5253
5254         /* use EIAM to auto-mask when MSI-X interrupt
5255          * is asserted, this saves a register write for every interrupt
5256          */
5257         intr_mask = RTE_LEN2MASK(intr_handle->nb_efd, uint32_t) <<
5258                 misc_shift;
5259         regval = E1000_READ_REG(hw, E1000_EIAM);
5260         E1000_WRITE_REG(hw, E1000_EIAM, regval | intr_mask);
5261
5262         for (queue_id = 0; queue_id < dev->data->nb_rx_queues; queue_id++) {
5263                 eth_igb_assign_msix_vector(hw, 0, queue_id, vec);
5264                 intr_handle->intr_vec[queue_id] = vec;
5265                 if (vec < base + intr_handle->nb_efd - 1)
5266                         vec++;
5267         }
5268
5269         E1000_WRITE_FLUSH(hw);
5270 }
5271
5272 RTE_PMD_REGISTER_PCI(net_e1000_igb, rte_igb_pmd.pci_drv);
5273 RTE_PMD_REGISTER_PCI_TABLE(net_e1000_igb, pci_id_igb_map);
5274 RTE_PMD_REGISTER_PCI(net_e1000_igb_vf, rte_igbvf_pmd.pci_drv);
5275 RTE_PMD_REGISTER_PCI_TABLE(net_e1000_igb_vf, pci_id_igbvf_map);