drivers/net/e1000/igb_ethdev.c

   1 /*-
   2  *   BSD LICENSE
   3  *
   4  *   Copyright(c) 2010-2016 Intel Corporation. All rights reserved.
   5  *   All rights reserved.
   6  *
   7  *   Redistribution and use in source and binary forms, with or without
   8  *   modification, are permitted provided that the following conditions
   9  *   are met:
  10  *
  11  *     * Redistributions of source code must retain the above copyright
  12  *       notice, this list of conditions and the following disclaimer.
  13  *     * Redistributions in binary form must reproduce the above copyright
  14  *       notice, this list of conditions and the following disclaimer in
  15  *       the documentation and/or other materials provided with the
  16  *       distribution.
  17  *     * Neither the name of Intel Corporation nor the names of its
  18  *       contributors may be used to endorse or promote products derived
  19  *       from this software without specific prior written permission.
  20  *
  21  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 #include <sys/queue.h>
  35 #include <stdio.h>
  36 #include <errno.h>
  37 #include <stdint.h>
  38 #include <stdarg.h>
  39
  40 #include <rte_common.h>
  41 #include <rte_interrupts.h>
  42 #include <rte_byteorder.h>
  43 #include <rte_log.h>
  44 #include <rte_debug.h>
  45 #include <rte_pci.h>
  46 #include <rte_ether.h>
  47 #include <rte_ethdev.h>
  48 #include <rte_memory.h>
  49 #include <rte_memzone.h>
  50 #include <rte_eal.h>
  51 #include <rte_atomic.h>
  52 #include <rte_malloc.h>
  53 #include <rte_dev.h>
  54
  55 #include "e1000_logs.h"
  56 #include "base/e1000_api.h"
  57 #include "e1000_ethdev.h"
  58 #include "igb_regs.h"
  59
  60 /*
  61  * Default values for port configuration
  62  */
  63 #define IGB_DEFAULT_RX_FREE_THRESH  32
  64
  65 #define IGB_DEFAULT_RX_PTHRESH      ((hw->mac.type == e1000_i354) ? 12 : 8)
  66 #define IGB_DEFAULT_RX_HTHRESH      8
  67 #define IGB_DEFAULT_RX_WTHRESH      ((hw->mac.type == e1000_82576) ? 1 : 4)
  68
  69 #define IGB_DEFAULT_TX_PTHRESH      ((hw->mac.type == e1000_i354) ? 20 : 8)
  70 #define IGB_DEFAULT_TX_HTHRESH      1
  71 #define IGB_DEFAULT_TX_WTHRESH      ((hw->mac.type == e1000_82576) ? 1 : 16)
  72
  73 #define IGB_HKEY_MAX_INDEX 10
  74
  75 /* Bit shift and mask */
  76 #define IGB_4_BIT_WIDTH  (CHAR_BIT / 2)
  77 #define IGB_4_BIT_MASK   RTE_LEN2MASK(IGB_4_BIT_WIDTH, uint8_t)
  78 #define IGB_8_BIT_WIDTH  CHAR_BIT
  79 #define IGB_8_BIT_MASK   UINT8_MAX
  80
  81 /* Additional timesync values. */
  82 #define E1000_CYCLECOUNTER_MASK      0xffffffffffffffffULL
  83 #define E1000_ETQF_FILTER_1588       3
  84 #define IGB_82576_TSYNC_SHIFT        16
  85 #define E1000_INCPERIOD_82576        (1 << E1000_TIMINCA_16NS_SHIFT)
  86 #define E1000_INCVALUE_82576         (16 << IGB_82576_TSYNC_SHIFT)
  87 #define E1000_TSAUXC_DISABLE_SYSTIME 0x80000000
  88
  89 #define E1000_VTIVAR_MISC                0x01740
  90 #define E1000_VTIVAR_MISC_MASK           0xFF
  91 #define E1000_VTIVAR_VALID               0x80
  92 #define E1000_VTIVAR_MISC_MAILBOX        0
  93 #define E1000_VTIVAR_MISC_INTR_MASK      0x3
  94
  95 /* External VLAN Enable bit mask */
  96 #define E1000_CTRL_EXT_EXT_VLAN      (1 << 26)
  97
  98 /* External VLAN Ether Type bit mask and shift */
  99 #define E1000_VET_VET_EXT            0xFFFF0000
 100 #define E1000_VET_VET_EXT_SHIFT      16
 101
 102 static int  eth_igb_configure(struct rte_eth_dev *dev);
 103 static int  eth_igb_start(struct rte_eth_dev *dev);
 104 static void eth_igb_stop(struct rte_eth_dev *dev);
 105 static int  eth_igb_dev_set_link_up(struct rte_eth_dev *dev);
 106 static int  eth_igb_dev_set_link_down(struct rte_eth_dev *dev);
 107 static void eth_igb_close(struct rte_eth_dev *dev);
 108 static void eth_igb_promiscuous_enable(struct rte_eth_dev *dev);
 109 static void eth_igb_promiscuous_disable(struct rte_eth_dev *dev);
 110 static void eth_igb_allmulticast_enable(struct rte_eth_dev *dev);
 111 static void eth_igb_allmulticast_disable(struct rte_eth_dev *dev);
 112 static int  eth_igb_link_update(struct rte_eth_dev *dev,
 113                                 int wait_to_complete);
 114 static void eth_igb_stats_get(struct rte_eth_dev *dev,
 115                                 struct rte_eth_stats *rte_stats);
 116 static int eth_igb_xstats_get(struct rte_eth_dev *dev,
 117                               struct rte_eth_xstat *xstats, unsigned n);
 118 static int eth_igb_xstats_get_names(struct rte_eth_dev *dev,
 119                                     struct rte_eth_xstat_name *xstats_names,
 120                                     unsigned limit);
 121 static void eth_igb_stats_reset(struct rte_eth_dev *dev);
 122 static void eth_igb_xstats_reset(struct rte_eth_dev *dev);
 123 static void eth_igb_infos_get(struct rte_eth_dev *dev,
 124                               struct rte_eth_dev_info *dev_info);
 125 static const uint32_t *eth_igb_supported_ptypes_get(struct rte_eth_dev *dev);
 126 static void eth_igbvf_infos_get(struct rte_eth_dev *dev,
 127                                 struct rte_eth_dev_info *dev_info);
 128 static int  eth_igb_flow_ctrl_get(struct rte_eth_dev *dev,
 129                                 struct rte_eth_fc_conf *fc_conf);
 130 static int  eth_igb_flow_ctrl_set(struct rte_eth_dev *dev,
 131                                 struct rte_eth_fc_conf *fc_conf);
 132 static int eth_igb_lsc_interrupt_setup(struct rte_eth_dev *dev, uint8_t on);
 133 static int eth_igb_rxq_interrupt_setup(struct rte_eth_dev *dev);
 134 static int eth_igb_interrupt_get_status(struct rte_eth_dev *dev);
 135 static int eth_igb_interrupt_action(struct rte_eth_dev *dev);
 136 static void eth_igb_interrupt_handler(struct rte_intr_handle *handle,
 137                                                         void *param);
 138 static int  igb_hardware_init(struct e1000_hw *hw);
 139 static void igb_hw_control_acquire(struct e1000_hw *hw);
 140 static void igb_hw_control_release(struct e1000_hw *hw);
 141 static void igb_init_manageability(struct e1000_hw *hw);
 142 static void igb_release_manageability(struct e1000_hw *hw);
 143
 144 static int  eth_igb_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
 145
 146 static int eth_igb_vlan_filter_set(struct rte_eth_dev *dev,
 147                 uint16_t vlan_id, int on);
 148 static int eth_igb_vlan_tpid_set(struct rte_eth_dev *dev,
 149                                  enum rte_vlan_type vlan_type,
 150                                  uint16_t tpid_id);
 151 static void eth_igb_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 152
 153 static void igb_vlan_hw_filter_enable(struct rte_eth_dev *dev);
 154 static void igb_vlan_hw_filter_disable(struct rte_eth_dev *dev);
 155 static void igb_vlan_hw_strip_enable(struct rte_eth_dev *dev);
 156 static void igb_vlan_hw_strip_disable(struct rte_eth_dev *dev);
 157 static void igb_vlan_hw_extend_enable(struct rte_eth_dev *dev);
 158 static void igb_vlan_hw_extend_disable(struct rte_eth_dev *dev);
 159
 160 static int eth_igb_led_on(struct rte_eth_dev *dev);
 161 static int eth_igb_led_off(struct rte_eth_dev *dev);
 162
 163 static void igb_intr_disable(struct e1000_hw *hw);
 164 static int  igb_get_rx_buffer_size(struct e1000_hw *hw);
 165 static void eth_igb_rar_set(struct rte_eth_dev *dev,
 166                 struct ether_addr *mac_addr,
 167                 uint32_t index, uint32_t pool);
 168 static void eth_igb_rar_clear(struct rte_eth_dev *dev, uint32_t index);
 169 static void eth_igb_default_mac_addr_set(struct rte_eth_dev *dev,
 170                 struct ether_addr *addr);
 171
 172 static void igbvf_intr_disable(struct e1000_hw *hw);
 173 static int igbvf_dev_configure(struct rte_eth_dev *dev);
 174 static int igbvf_dev_start(struct rte_eth_dev *dev);
 175 static void igbvf_dev_stop(struct rte_eth_dev *dev);
 176 static void igbvf_dev_close(struct rte_eth_dev *dev);
 177 static void igbvf_promiscuous_enable(struct rte_eth_dev *dev);
 178 static void igbvf_promiscuous_disable(struct rte_eth_dev *dev);
 179 static void igbvf_allmulticast_enable(struct rte_eth_dev *dev);
 180 static void igbvf_allmulticast_disable(struct rte_eth_dev *dev);
 181 static int eth_igbvf_link_update(struct e1000_hw *hw);
 182 static void eth_igbvf_stats_get(struct rte_eth_dev *dev,
 183                                 struct rte_eth_stats *rte_stats);
 184 static int eth_igbvf_xstats_get(struct rte_eth_dev *dev,
 185                                 struct rte_eth_xstat *xstats, unsigned n);
 186 static int eth_igbvf_xstats_get_names(struct rte_eth_dev *dev,
 187                                       struct rte_eth_xstat_name *xstats_names,
 188                                       unsigned limit);
 189 static void eth_igbvf_stats_reset(struct rte_eth_dev *dev);
 190 static int igbvf_vlan_filter_set(struct rte_eth_dev *dev,
 191                 uint16_t vlan_id, int on);
 192 static int igbvf_set_vfta(struct e1000_hw *hw, uint16_t vid, bool on);
 193 static void igbvf_set_vfta_all(struct rte_eth_dev *dev, bool on);
 194 static void igbvf_default_mac_addr_set(struct rte_eth_dev *dev,
 195                 struct ether_addr *addr);
 196 static int igbvf_get_reg_length(struct rte_eth_dev *dev);
 197 static int igbvf_get_regs(struct rte_eth_dev *dev,
 198                 struct rte_dev_reg_info *regs);
 199
 200 static int eth_igb_rss_reta_update(struct rte_eth_dev *dev,
 201                                    struct rte_eth_rss_reta_entry64 *reta_conf,
 202                                    uint16_t reta_size);
 203 static int eth_igb_rss_reta_query(struct rte_eth_dev *dev,
 204                                   struct rte_eth_rss_reta_entry64 *reta_conf,
 205                                   uint16_t reta_size);
 206
 207 static int eth_igb_syn_filter_set(struct rte_eth_dev *dev,
 208                         struct rte_eth_syn_filter *filter,
 209                         bool add);
 210 static int eth_igb_syn_filter_get(struct rte_eth_dev *dev,
 211                         struct rte_eth_syn_filter *filter);
 212 static int eth_igb_syn_filter_handle(struct rte_eth_dev *dev,
 213                         enum rte_filter_op filter_op,
 214                         void *arg);
 215 static int igb_add_2tuple_filter(struct rte_eth_dev *dev,
 216                         struct rte_eth_ntuple_filter *ntuple_filter);
 217 static int igb_remove_2tuple_filter(struct rte_eth_dev *dev,
 218                         struct rte_eth_ntuple_filter *ntuple_filter);
 219 static int eth_igb_add_del_flex_filter(struct rte_eth_dev *dev,
 220                         struct rte_eth_flex_filter *filter,
 221                         bool add);
 222 static int eth_igb_get_flex_filter(struct rte_eth_dev *dev,
 223                         struct rte_eth_flex_filter *filter);
 224 static int eth_igb_flex_filter_handle(struct rte_eth_dev *dev,
 225                         enum rte_filter_op filter_op,
 226                         void *arg);
 227 static int igb_add_5tuple_filter_82576(struct rte_eth_dev *dev,
 228                         struct rte_eth_ntuple_filter *ntuple_filter);
 229 static int igb_remove_5tuple_filter_82576(struct rte_eth_dev *dev,
 230                         struct rte_eth_ntuple_filter *ntuple_filter);
 231 static int igb_add_del_ntuple_filter(struct rte_eth_dev *dev,
 232                         struct rte_eth_ntuple_filter *filter,
 233                         bool add);
 234 static int igb_get_ntuple_filter(struct rte_eth_dev *dev,
 235                         struct rte_eth_ntuple_filter *filter);
 236 static int igb_ntuple_filter_handle(struct rte_eth_dev *dev,
 237                                 enum rte_filter_op filter_op,
 238                                 void *arg);
 239 static int igb_add_del_ethertype_filter(struct rte_eth_dev *dev,
 240                         struct rte_eth_ethertype_filter *filter,
 241                         bool add);
 242 static int igb_ethertype_filter_handle(struct rte_eth_dev *dev,
 243                                 enum rte_filter_op filter_op,
 244                                 void *arg);
 245 static int igb_get_ethertype_filter(struct rte_eth_dev *dev,
 246                         struct rte_eth_ethertype_filter *filter);
 247 static int eth_igb_filter_ctrl(struct rte_eth_dev *dev,
 248                      enum rte_filter_type filter_type,
 249                      enum rte_filter_op filter_op,
 250                      void *arg);
 251 static int eth_igb_get_reg_length(struct rte_eth_dev *dev);
 252 static int eth_igb_get_regs(struct rte_eth_dev *dev,
 253                 struct rte_dev_reg_info *regs);
 254 static int eth_igb_get_eeprom_length(struct rte_eth_dev *dev);
 255 static int eth_igb_get_eeprom(struct rte_eth_dev *dev,
 256                 struct rte_dev_eeprom_info *eeprom);
 257 static int eth_igb_set_eeprom(struct rte_eth_dev *dev,
 258                 struct rte_dev_eeprom_info *eeprom);
 259 static int eth_igb_set_mc_addr_list(struct rte_eth_dev *dev,
 260                                     struct ether_addr *mc_addr_set,
 261                                     uint32_t nb_mc_addr);
 262 static int igb_timesync_enable(struct rte_eth_dev *dev);
 263 static int igb_timesync_disable(struct rte_eth_dev *dev);
 264 static int igb_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
 265                                           struct timespec *timestamp,
 266                                           uint32_t flags);
 267 static int igb_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
 268                                           struct timespec *timestamp);
 269 static int igb_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);
 270 static int igb_timesync_read_time(struct rte_eth_dev *dev,
 271                                   struct timespec *timestamp);
 272 static int igb_timesync_write_time(struct rte_eth_dev *dev,
 273                                    const struct timespec *timestamp);
 274 static int eth_igb_rx_queue_intr_enable(struct rte_eth_dev *dev,
 275                                         uint16_t queue_id);
 276 static int eth_igb_rx_queue_intr_disable(struct rte_eth_dev *dev,
 277                                          uint16_t queue_id);
 278 static void eth_igb_assign_msix_vector(struct e1000_hw *hw, int8_t direction,
 279                                        uint8_t queue, uint8_t msix_vector);
 280 static void eth_igb_write_ivar(struct e1000_hw *hw, uint8_t msix_vector,
 281                                uint8_t index, uint8_t offset);
 282 static void eth_igb_configure_msix_intr(struct rte_eth_dev *dev);
 283 static void eth_igbvf_interrupt_handler(struct rte_intr_handle *handle,
 284                                         void *param);
 285 static void igbvf_mbx_process(struct rte_eth_dev *dev);
 286
 287 /*
 288  * Define VF Stats MACRO for Non "cleared on read" register
 289  */
 290 #define UPDATE_VF_STAT(reg, last, cur)            \
 291 {                                                 \
 292         u32 latest = E1000_READ_REG(hw, reg);     \
 293         cur += (latest - last) & UINT_MAX;        \
 294         last = latest;                            \
 295 }
 296
 297 #define IGB_FC_PAUSE_TIME 0x0680
 298 #define IGB_LINK_UPDATE_CHECK_TIMEOUT  90  /* 9s */
 299 #define IGB_LINK_UPDATE_CHECK_INTERVAL 100 /* ms */
 300
 301 #define IGBVF_PMD_NAME "rte_igbvf_pmd"     /* PMD name */
 302
 303 static enum e1000_fc_mode igb_fc_setting = e1000_fc_full;
 304
 305 /*
 306  * The set of PCI devices this driver supports
 307  */
 308 static const struct rte_pci_id pci_id_igb_map[] = {
 309         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576) },
 310         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_FIBER) },
 311         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_SERDES) },
 312         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_QUAD_COPPER) },
 313         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_QUAD_COPPER_ET2) },
 314         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_NS) },
 315         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_NS_SERDES) },
 316         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_SERDES_QUAD) },
 317
 318         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82575EB_COPPER) },
 319         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82575EB_FIBER_SERDES) },
 320         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82575GB_QUAD_COPPER) },
 321
 322         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82580_COPPER) },
 323         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82580_FIBER) },
 324         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82580_SERDES) },
 325         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82580_SGMII) },
 326         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82580_COPPER_DUAL) },
 327         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82580_QUAD_FIBER) },
 328
 329         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_COPPER) },
 330         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_FIBER) },
 331         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_SERDES) },
 332         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_SGMII) },
 333         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_DA4) },
 334         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_COPPER) },
 335         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_COPPER_OEM1) },
 336         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_COPPER_IT) },
 337         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_FIBER) },
 338         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_SERDES) },
 339         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_SGMII) },
 340         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I211_COPPER) },
 341         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I354_BACKPLANE_1GBPS) },
 342         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I354_SGMII) },
 343         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I354_BACKPLANE_2_5GBPS) },
 344         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_DH89XXCC_SGMII) },
 345         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_DH89XXCC_SERDES) },
 346         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_DH89XXCC_BACKPLANE) },
 347         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_DH89XXCC_SFP) },
 348         { .vendor_id = 0, /* sentinel */ },
 349 };
 350
 351 /*
 352  * The set of PCI devices this driver supports (for 82576&I350 VF)
 353  */
 354 static const struct rte_pci_id pci_id_igbvf_map[] = {
 355         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_VF) },
 356         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_VF_HV) },
 357         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_VF) },
 358         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_VF_HV) },
 359         { .vendor_id = 0, /* sentinel */ },
 360 };
 361
 362 static const struct rte_eth_desc_lim rx_desc_lim = {
 363         .nb_max = E1000_MAX_RING_DESC,
 364         .nb_min = E1000_MIN_RING_DESC,
 365         .nb_align = IGB_RXD_ALIGN,
 366 };
 367
 368 static const struct rte_eth_desc_lim tx_desc_lim = {
 369         .nb_max = E1000_MAX_RING_DESC,
 370         .nb_min = E1000_MIN_RING_DESC,
 371         .nb_align = IGB_RXD_ALIGN,
 372 };
 373
 374 static const struct eth_dev_ops eth_igb_ops = {
 375         .dev_configure        = eth_igb_configure,
 376         .dev_start            = eth_igb_start,
 377         .dev_stop             = eth_igb_stop,
 378         .dev_set_link_up      = eth_igb_dev_set_link_up,
 379         .dev_set_link_down    = eth_igb_dev_set_link_down,
 380         .dev_close            = eth_igb_close,
 381         .promiscuous_enable   = eth_igb_promiscuous_enable,
 382         .promiscuous_disable  = eth_igb_promiscuous_disable,
 383         .allmulticast_enable  = eth_igb_allmulticast_enable,
 384         .allmulticast_disable = eth_igb_allmulticast_disable,
 385         .link_update          = eth_igb_link_update,
 386         .stats_get            = eth_igb_stats_get,
 387         .xstats_get           = eth_igb_xstats_get,
 388         .xstats_get_names     = eth_igb_xstats_get_names,
 389         .stats_reset          = eth_igb_stats_reset,
 390         .xstats_reset         = eth_igb_xstats_reset,
 391         .dev_infos_get        = eth_igb_infos_get,
 392         .dev_supported_ptypes_get = eth_igb_supported_ptypes_get,
 393         .mtu_set              = eth_igb_mtu_set,
 394         .vlan_filter_set      = eth_igb_vlan_filter_set,
 395         .vlan_tpid_set        = eth_igb_vlan_tpid_set,
 396         .vlan_offload_set     = eth_igb_vlan_offload_set,
 397         .rx_queue_setup       = eth_igb_rx_queue_setup,
 398         .rx_queue_intr_enable = eth_igb_rx_queue_intr_enable,
 399         .rx_queue_intr_disable = eth_igb_rx_queue_intr_disable,
 400         .rx_queue_release     = eth_igb_rx_queue_release,
 401         .rx_queue_count       = eth_igb_rx_queue_count,
 402         .rx_descriptor_done   = eth_igb_rx_descriptor_done,
 403         .tx_queue_setup       = eth_igb_tx_queue_setup,
 404         .tx_queue_release     = eth_igb_tx_queue_release,
 405         .dev_led_on           = eth_igb_led_on,
 406         .dev_led_off          = eth_igb_led_off,
 407         .flow_ctrl_get        = eth_igb_flow_ctrl_get,
 408         .flow_ctrl_set        = eth_igb_flow_ctrl_set,
 409         .mac_addr_add         = eth_igb_rar_set,
 410         .mac_addr_remove      = eth_igb_rar_clear,
 411         .mac_addr_set         = eth_igb_default_mac_addr_set,
 412         .reta_update          = eth_igb_rss_reta_update,
 413         .reta_query           = eth_igb_rss_reta_query,
 414         .rss_hash_update      = eth_igb_rss_hash_update,
 415         .rss_hash_conf_get    = eth_igb_rss_hash_conf_get,
 416         .filter_ctrl          = eth_igb_filter_ctrl,
 417         .set_mc_addr_list     = eth_igb_set_mc_addr_list,
 418         .rxq_info_get         = igb_rxq_info_get,
 419         .txq_info_get         = igb_txq_info_get,
 420         .timesync_enable      = igb_timesync_enable,
 421         .timesync_disable     = igb_timesync_disable,
 422         .timesync_read_rx_timestamp = igb_timesync_read_rx_timestamp,
 423         .timesync_read_tx_timestamp = igb_timesync_read_tx_timestamp,
 424         .get_reg              = eth_igb_get_regs,
 425         .get_eeprom_length    = eth_igb_get_eeprom_length,
 426         .get_eeprom           = eth_igb_get_eeprom,
 427         .set_eeprom           = eth_igb_set_eeprom,
 428         .timesync_adjust_time = igb_timesync_adjust_time,
 429         .timesync_read_time   = igb_timesync_read_time,
 430         .timesync_write_time  = igb_timesync_write_time,
 431 };
 432
 433 /*
 434  * dev_ops for virtual function, bare necessities for basic vf
 435  * operation have been implemented
 436  */
 437 static const struct eth_dev_ops igbvf_eth_dev_ops = {
 438         .dev_configure        = igbvf_dev_configure,
 439         .dev_start            = igbvf_dev_start,
 440         .dev_stop             = igbvf_dev_stop,
 441         .dev_close            = igbvf_dev_close,
 442         .promiscuous_enable   = igbvf_promiscuous_enable,
 443         .promiscuous_disable  = igbvf_promiscuous_disable,
 444         .allmulticast_enable  = igbvf_allmulticast_enable,
 445         .allmulticast_disable = igbvf_allmulticast_disable,
 446         .link_update          = eth_igb_link_update,
 447         .stats_get            = eth_igbvf_stats_get,
 448         .xstats_get           = eth_igbvf_xstats_get,
 449         .xstats_get_names     = eth_igbvf_xstats_get_names,
 450         .stats_reset          = eth_igbvf_stats_reset,
 451         .xstats_reset         = eth_igbvf_stats_reset,
 452         .vlan_filter_set      = igbvf_vlan_filter_set,
 453         .dev_infos_get        = eth_igbvf_infos_get,
 454         .dev_supported_ptypes_get = eth_igb_supported_ptypes_get,
 455         .rx_queue_setup       = eth_igb_rx_queue_setup,
 456         .rx_queue_release     = eth_igb_rx_queue_release,
 457         .tx_queue_setup       = eth_igb_tx_queue_setup,
 458         .tx_queue_release     = eth_igb_tx_queue_release,
 459         .set_mc_addr_list     = eth_igb_set_mc_addr_list,
 460         .rxq_info_get         = igb_rxq_info_get,
 461         .txq_info_get         = igb_txq_info_get,
 462         .mac_addr_set         = igbvf_default_mac_addr_set,
 463         .get_reg              = igbvf_get_regs,
 464 };
 465
 466 /* store statistics names and its offset in stats structure */
 467 struct rte_igb_xstats_name_off {
 468         char name[RTE_ETH_XSTATS_NAME_SIZE];
 469         unsigned offset;
 470 };
 471
 472 static const struct rte_igb_xstats_name_off rte_igb_stats_strings[] = {
 473         {"rx_crc_errors", offsetof(struct e1000_hw_stats, crcerrs)},
 474         {"rx_align_errors", offsetof(struct e1000_hw_stats, algnerrc)},
 475         {"rx_symbol_errors", offsetof(struct e1000_hw_stats, symerrs)},
 476         {"rx_missed_packets", offsetof(struct e1000_hw_stats, mpc)},
 477         {"tx_single_collision_packets", offsetof(struct e1000_hw_stats, scc)},
 478         {"tx_multiple_collision_packets", offsetof(struct e1000_hw_stats, mcc)},
 479         {"tx_excessive_collision_packets", offsetof(struct e1000_hw_stats,
 480                 ecol)},
 481         {"tx_late_collisions", offsetof(struct e1000_hw_stats, latecol)},
 482         {"tx_total_collisions", offsetof(struct e1000_hw_stats, colc)},
 483         {"tx_deferred_packets", offsetof(struct e1000_hw_stats, dc)},
 484         {"tx_no_carrier_sense_packets", offsetof(struct e1000_hw_stats, tncrs)},
 485         {"rx_carrier_ext_errors", offsetof(struct e1000_hw_stats, cexterr)},
 486         {"rx_length_errors", offsetof(struct e1000_hw_stats, rlec)},
 487         {"rx_xon_packets", offsetof(struct e1000_hw_stats, xonrxc)},
 488         {"tx_xon_packets", offsetof(struct e1000_hw_stats, xontxc)},
 489         {"rx_xoff_packets", offsetof(struct e1000_hw_stats, xoffrxc)},
 490         {"tx_xoff_packets", offsetof(struct e1000_hw_stats, xofftxc)},
 491         {"rx_flow_control_unsupported_packets", offsetof(struct e1000_hw_stats,
 492                 fcruc)},
 493         {"rx_size_64_packets", offsetof(struct e1000_hw_stats, prc64)},
 494         {"rx_size_65_to_127_packets", offsetof(struct e1000_hw_stats, prc127)},
 495         {"rx_size_128_to_255_packets", offsetof(struct e1000_hw_stats, prc255)},
 496         {"rx_size_256_to_511_packets", offsetof(struct e1000_hw_stats, prc511)},
 497         {"rx_size_512_to_1023_packets", offsetof(struct e1000_hw_stats,
 498                 prc1023)},
 499         {"rx_size_1024_to_max_packets", offsetof(struct e1000_hw_stats,
 500                 prc1522)},
 501         {"rx_broadcast_packets", offsetof(struct e1000_hw_stats, bprc)},
 502         {"rx_multicast_packets", offsetof(struct e1000_hw_stats, mprc)},
 503         {"rx_undersize_errors", offsetof(struct e1000_hw_stats, ruc)},
 504         {"rx_fragment_errors", offsetof(struct e1000_hw_stats, rfc)},
 505         {"rx_oversize_errors", offsetof(struct e1000_hw_stats, roc)},
 506         {"rx_jabber_errors", offsetof(struct e1000_hw_stats, rjc)},
 507         {"rx_management_packets", offsetof(struct e1000_hw_stats, mgprc)},
 508         {"rx_management_dropped", offsetof(struct e1000_hw_stats, mgpdc)},
 509         {"tx_management_packets", offsetof(struct e1000_hw_stats, mgptc)},
 510         {"rx_total_packets", offsetof(struct e1000_hw_stats, tpr)},
 511         {"tx_total_packets", offsetof(struct e1000_hw_stats, tpt)},
 512         {"rx_total_bytes", offsetof(struct e1000_hw_stats, tor)},
 513         {"tx_total_bytes", offsetof(struct e1000_hw_stats, tot)},
 514         {"tx_size_64_packets", offsetof(struct e1000_hw_stats, ptc64)},
 515         {"tx_size_65_to_127_packets", offsetof(struct e1000_hw_stats, ptc127)},
 516         {"tx_size_128_to_255_packets", offsetof(struct e1000_hw_stats, ptc255)},
 517         {"tx_size_256_to_511_packets", offsetof(struct e1000_hw_stats, ptc511)},
 518         {"tx_size_512_to_1023_packets", offsetof(struct e1000_hw_stats,
 519                 ptc1023)},
 520         {"tx_size_1023_to_max_packets", offsetof(struct e1000_hw_stats,
 521                 ptc1522)},
 522         {"tx_multicast_packets", offsetof(struct e1000_hw_stats, mptc)},
 523         {"tx_broadcast_packets", offsetof(struct e1000_hw_stats, bptc)},
 524         {"tx_tso_packets", offsetof(struct e1000_hw_stats, tsctc)},
 525         {"tx_tso_errors", offsetof(struct e1000_hw_stats, tsctfc)},
 526         {"rx_sent_to_host_packets", offsetof(struct e1000_hw_stats, rpthc)},
 527         {"tx_sent_by_host_packets", offsetof(struct e1000_hw_stats, hgptc)},
 528         {"rx_code_violation_packets", offsetof(struct e1000_hw_stats, scvpc)},
 529
 530         {"interrupt_assert_count", offsetof(struct e1000_hw_stats, iac)},
 531 };
 532
 533 #define IGB_NB_XSTATS (sizeof(rte_igb_stats_strings) / \
 534                 sizeof(rte_igb_stats_strings[0]))
 535
 536 static const struct rte_igb_xstats_name_off rte_igbvf_stats_strings[] = {
 537         {"rx_multicast_packets", offsetof(struct e1000_vf_stats, mprc)},
 538         {"rx_good_loopback_packets", offsetof(struct e1000_vf_stats, gprlbc)},
 539         {"tx_good_loopback_packets", offsetof(struct e1000_vf_stats, gptlbc)},
 540         {"rx_good_loopback_bytes", offsetof(struct e1000_vf_stats, gorlbc)},
 541         {"tx_good_loopback_bytes", offsetof(struct e1000_vf_stats, gotlbc)},
 542 };
 543
 544 #define IGBVF_NB_XSTATS (sizeof(rte_igbvf_stats_strings) / \
 545                 sizeof(rte_igbvf_stats_strings[0]))
 546
 547 /**
 548  * Atomically reads the link status information from global
 549  * structure rte_eth_dev.
 550  *
 551  * @param dev
 552  *   - Pointer to the structure rte_eth_dev to read from.
 553  *   - Pointer to the buffer to be saved with the link status.
 554  *
 555  * @return
 556  *   - On success, zero.
 557  *   - On failure, negative value.
 558  */
 559 static inline int
 560 rte_igb_dev_atomic_read_link_status(struct rte_eth_dev *dev,
 561                                 struct rte_eth_link *link)
 562 {
 563         struct rte_eth_link *dst = link;
 564         struct rte_eth_link *src = &(dev->data->dev_link);
 565
 566         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 567                                         *(uint64_t *)src) == 0)
 568                 return -1;
 569
 570         return 0;
 571 }
 572
 573 /**
 574  * Atomically writes the link status information into global
 575  * structure rte_eth_dev.
 576  *
 577  * @param dev
 578  *   - Pointer to the structure rte_eth_dev to read from.
 579  *   - Pointer to the buffer to be saved with the link status.
 580  *
 581  * @return
 582  *   - On success, zero.
 583  *   - On failure, negative value.
 584  */
 585 static inline int
 586 rte_igb_dev_atomic_write_link_status(struct rte_eth_dev *dev,
 587                                 struct rte_eth_link *link)
 588 {
 589         struct rte_eth_link *dst = &(dev->data->dev_link);
 590         struct rte_eth_link *src = link;
 591
 592         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 593                                         *(uint64_t *)src) == 0)
 594                 return -1;
 595
 596         return 0;
 597 }
 598
 599 static inline void
 600 igb_intr_enable(struct rte_eth_dev *dev)
 601 {
 602         struct e1000_interrupt *intr =
 603                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
 604         struct e1000_hw *hw =
 605                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 606
 607         E1000_WRITE_REG(hw, E1000_IMS, intr->mask);
 608         E1000_WRITE_FLUSH(hw);
 609 }
 610
 611 static void
 612 igb_intr_disable(struct e1000_hw *hw)
 613 {
 614         E1000_WRITE_REG(hw, E1000_IMC, ~0);
 615         E1000_WRITE_FLUSH(hw);
 616 }
 617
 618 static inline void
 619 igbvf_intr_enable(struct rte_eth_dev *dev)
 620 {
 621         struct e1000_hw *hw =
 622                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 623
 624         /* only for mailbox */
 625         E1000_WRITE_REG(hw, E1000_EIAM, 1 << E1000_VTIVAR_MISC_MAILBOX);
 626         E1000_WRITE_REG(hw, E1000_EIAC, 1 << E1000_VTIVAR_MISC_MAILBOX);
 627         E1000_WRITE_REG(hw, E1000_EIMS, 1 << E1000_VTIVAR_MISC_MAILBOX);
 628         E1000_WRITE_FLUSH(hw);
 629 }
 630
 631 /* only for mailbox now. If RX/TX needed, should extend this function.  */
 632 static void
 633 igbvf_set_ivar_map(struct e1000_hw *hw, uint8_t msix_vector)
 634 {
 635         uint32_t tmp = 0;
 636
 637         /* mailbox */
 638         tmp |= (msix_vector & E1000_VTIVAR_MISC_INTR_MASK);
 639         tmp |= E1000_VTIVAR_VALID;
 640         E1000_WRITE_REG(hw, E1000_VTIVAR_MISC, tmp);
 641 }
 642
 643 static void
 644 eth_igbvf_configure_msix_intr(struct rte_eth_dev *dev)
 645 {
 646         struct e1000_hw *hw =
 647                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 648
 649         /* Configure VF other cause ivar */
 650         igbvf_set_ivar_map(hw, E1000_VTIVAR_MISC_MAILBOX);
 651 }
 652
 653 static inline int32_t
 654 igb_pf_reset_hw(struct e1000_hw *hw)
 655 {
 656         uint32_t ctrl_ext;
 657         int32_t status;
 658
 659         status = e1000_reset_hw(hw);
 660
 661         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
 662         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
 663         ctrl_ext |= E1000_CTRL_EXT_PFRSTD;
 664         E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
 665         E1000_WRITE_FLUSH(hw);
 666
 667         return status;
 668 }
 669
 670 static void
 671 igb_identify_hardware(struct rte_eth_dev *dev)
 672 {
 673         struct e1000_hw *hw =
 674                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 675
 676         hw->vendor_id = dev->pci_dev->id.vendor_id;
 677         hw->device_id = dev->pci_dev->id.device_id;
 678         hw->subsystem_vendor_id = dev->pci_dev->id.subsystem_vendor_id;
 679         hw->subsystem_device_id = dev->pci_dev->id.subsystem_device_id;
 680
 681         e1000_set_mac_type(hw);
 682
 683         /* need to check if it is a vf device below */
 684 }
 685
 686 static int
 687 igb_reset_swfw_lock(struct e1000_hw *hw)
 688 {
 689         int ret_val;
 690
 691         /*
 692          * Do mac ops initialization manually here, since we will need
 693          * some function pointers set by this call.
 694          */
 695         ret_val = e1000_init_mac_params(hw);
 696         if (ret_val)
 697                 return ret_val;
 698
 699         /*
 700          * SMBI lock should not fail in this early stage. If this is the case,
 701          * it is due to an improper exit of the application.
 702          * So force the release of the faulty lock.
 703          */
 704         if (e1000_get_hw_semaphore_generic(hw) < 0) {
 705                 PMD_DRV_LOG(DEBUG, "SMBI lock released");
 706         }
 707         e1000_put_hw_semaphore_generic(hw);
 708
 709         if (hw->mac.ops.acquire_swfw_sync != NULL) {
 710                 uint16_t mask;
 711
 712                 /*
 713                  * Phy lock should not fail in this early stage. If this is the case,
 714                  * it is due to an improper exit of the application.
 715                  * So force the release of the faulty lock.
 716                  */
 717                 mask = E1000_SWFW_PHY0_SM << hw->bus.func;
 718                 if (hw->bus.func > E1000_FUNC_1)
 719                         mask <<= 2;
 720                 if (hw->mac.ops.acquire_swfw_sync(hw, mask) < 0) {
 721                         PMD_DRV_LOG(DEBUG, "SWFW phy%d lock released",
 722                                     hw->bus.func);
 723                 }
 724                 hw->mac.ops.release_swfw_sync(hw, mask);
 725
 726                 /*
 727                  * This one is more tricky since it is common to all ports; but
 728                  * swfw_sync retries last long enough (1s) to be almost sure that if
 729                  * lock can not be taken it is due to an improper lock of the
 730                  * semaphore.
 731                  */
 732                 mask = E1000_SWFW_EEP_SM;
 733                 if (hw->mac.ops.acquire_swfw_sync(hw, mask) < 0) {
 734                         PMD_DRV_LOG(DEBUG, "SWFW common locks released");
 735                 }
 736                 hw->mac.ops.release_swfw_sync(hw, mask);
 737         }
 738
 739         return E1000_SUCCESS;
 740 }
 741
 742 static int
 743 eth_igb_dev_init(struct rte_eth_dev *eth_dev)
 744 {
 745         int error = 0;
 746         struct rte_pci_device *pci_dev;
 747         struct e1000_hw *hw =
 748                 E1000_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 749         struct e1000_vfta * shadow_vfta =
 750                 E1000_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
 751         struct e1000_filter_info *filter_info =
 752                 E1000_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
 753         struct e1000_adapter *adapter =
 754                 E1000_DEV_PRIVATE(eth_dev->data->dev_private);
 755
 756         uint32_t ctrl_ext;
 757
 758         pci_dev = eth_dev->pci_dev;
 759
 760         eth_dev->dev_ops = &eth_igb_ops;
 761         eth_dev->rx_pkt_burst = &eth_igb_recv_pkts;
 762         eth_dev->tx_pkt_burst = &eth_igb_xmit_pkts;
 763
 764         /* for secondary processes, we don't initialise any further as primary
 765          * has already done this work. Only check we don't need a different
 766          * RX function */
 767         if (rte_eal_process_type() != RTE_PROC_PRIMARY){
 768                 if (eth_dev->data->scattered_rx)
 769                         eth_dev->rx_pkt_burst = &eth_igb_recv_scattered_pkts;
 770                 return 0;
 771         }
 772
 773         rte_eth_copy_pci_info(eth_dev, pci_dev);
 774
 775         hw->hw_addr= (void *)pci_dev->mem_resource[0].addr;
 776
 777         igb_identify_hardware(eth_dev);
 778         if (e1000_setup_init_funcs(hw, FALSE) != E1000_SUCCESS) {
 779                 error = -EIO;
 780                 goto err_late;
 781         }
 782
 783         e1000_get_bus_info(hw);
 784
 785         /* Reset any pending lock */
 786         if (igb_reset_swfw_lock(hw) != E1000_SUCCESS) {
 787                 error = -EIO;
 788                 goto err_late;
 789         }
 790
 791         /* Finish initialization */
 792         if (e1000_setup_init_funcs(hw, TRUE) != E1000_SUCCESS) {
 793                 error = -EIO;
 794                 goto err_late;
 795         }
 796
 797         hw->mac.autoneg = 1;
 798         hw->phy.autoneg_wait_to_complete = 0;
 799         hw->phy.autoneg_advertised = E1000_ALL_SPEED_DUPLEX;
 800
 801         /* Copper options */
 802         if (hw->phy.media_type == e1000_media_type_copper) {
 803                 hw->phy.mdix = 0; /* AUTO_ALL_MODES */
 804                 hw->phy.disable_polarity_correction = 0;
 805                 hw->phy.ms_type = e1000_ms_hw_default;
 806         }
 807
 808         /*
 809          * Start from a known state, this is important in reading the nvm
 810          * and mac from that.
 811          */
 812         igb_pf_reset_hw(hw);
 813
 814         /* Make sure we have a good EEPROM before we read from it */
 815         if (e1000_validate_nvm_checksum(hw) < 0) {
 816                 /*
 817                  * Some PCI-E parts fail the first check due to
 818                  * the link being in sleep state, call it again,
 819                  * if it fails a second time its a real issue.
 820                  */
 821                 if (e1000_validate_nvm_checksum(hw) < 0) {
 822                         PMD_INIT_LOG(ERR, "EEPROM checksum invalid");
 823                         error = -EIO;
 824                         goto err_late;
 825                 }
 826         }
 827
 828         /* Read the permanent MAC address out of the EEPROM */
 829         if (e1000_read_mac_addr(hw) != 0) {
 830                 PMD_INIT_LOG(ERR, "EEPROM error while reading MAC address");
 831                 error = -EIO;
 832                 goto err_late;
 833         }
 834
 835         /* Allocate memory for storing MAC addresses */
 836         eth_dev->data->mac_addrs = rte_zmalloc("e1000",
 837                 ETHER_ADDR_LEN * hw->mac.rar_entry_count, 0);
 838         if (eth_dev->data->mac_addrs == NULL) {
 839                 PMD_INIT_LOG(ERR, "Failed to allocate %d bytes needed to "
 840                                                 "store MAC addresses",
 841                                 ETHER_ADDR_LEN * hw->mac.rar_entry_count);
 842                 error = -ENOMEM;
 843                 goto err_late;
 844         }
 845
 846         /* Copy the permanent MAC address */
 847         ether_addr_copy((struct ether_addr *)hw->mac.addr, &eth_dev->data->mac_addrs[0]);
 848
 849         /* initialize the vfta */
 850         memset(shadow_vfta, 0, sizeof(*shadow_vfta));
 851
 852         /* Now initialize the hardware */
 853         if (igb_hardware_init(hw) != 0) {
 854                 PMD_INIT_LOG(ERR, "Hardware initialization failed");
 855                 rte_free(eth_dev->data->mac_addrs);
 856                 eth_dev->data->mac_addrs = NULL;
 857                 error = -ENODEV;
 858                 goto err_late;
 859         }
 860         hw->mac.get_link_status = 1;
 861         adapter->stopped = 0;
 862
 863         /* Indicate SOL/IDER usage */
 864         if (e1000_check_reset_block(hw) < 0) {
 865                 PMD_INIT_LOG(ERR, "PHY reset is blocked due to"
 866                                         "SOL/IDER session");
 867         }
 868
 869         /* initialize PF if max_vfs not zero */
 870         igb_pf_host_init(eth_dev);
 871
 872         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
 873         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
 874         ctrl_ext |= E1000_CTRL_EXT_PFRSTD;
 875         E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
 876         E1000_WRITE_FLUSH(hw);
 877
 878         PMD_INIT_LOG(DEBUG, "port_id %d vendorID=0x%x deviceID=0x%x",
 879                      eth_dev->data->port_id, pci_dev->id.vendor_id,
 880                      pci_dev->id.device_id);
 881
 882         rte_intr_callback_register(&pci_dev->intr_handle,
 883                                    eth_igb_interrupt_handler,
 884                                    (void *)eth_dev);
 885
 886         /* enable uio/vfio intr/eventfd mapping */
 887         rte_intr_enable(&pci_dev->intr_handle);
 888
 889         /* enable support intr */
 890         igb_intr_enable(eth_dev);
 891
 892         TAILQ_INIT(&filter_info->flex_list);
 893         filter_info->flex_mask = 0;
 894         TAILQ_INIT(&filter_info->twotuple_list);
 895         filter_info->twotuple_mask = 0;
 896         TAILQ_INIT(&filter_info->fivetuple_list);
 897         filter_info->fivetuple_mask = 0;
 898
 899         return 0;
 900
 901 err_late:
 902         igb_hw_control_release(hw);
 903
 904         return error;
 905 }
 906
 907 static int
 908 eth_igb_dev_uninit(struct rte_eth_dev *eth_dev)
 909 {
 910         struct rte_pci_device *pci_dev;
 911         struct e1000_hw *hw;
 912         struct e1000_adapter *adapter =
 913                 E1000_DEV_PRIVATE(eth_dev->data->dev_private);
 914
 915         PMD_INIT_FUNC_TRACE();
 916
 917         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
 918                 return -EPERM;
 919
 920         hw = E1000_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 921         pci_dev = eth_dev->pci_dev;
 922
 923         if (adapter->stopped == 0)
 924                 eth_igb_close(eth_dev);
 925
 926         eth_dev->dev_ops = NULL;
 927         eth_dev->rx_pkt_burst = NULL;
 928         eth_dev->tx_pkt_burst = NULL;
 929
 930         /* Reset any pending lock */
 931         igb_reset_swfw_lock(hw);
 932
 933         rte_free(eth_dev->data->mac_addrs);
 934         eth_dev->data->mac_addrs = NULL;
 935
 936         /* uninitialize PF if max_vfs not zero */
 937         igb_pf_host_uninit(eth_dev);
 938
 939         /* disable uio intr before callback unregister */
 940         rte_intr_disable(&(pci_dev->intr_handle));
 941         rte_intr_callback_unregister(&(pci_dev->intr_handle),
 942                 eth_igb_interrupt_handler, (void *)eth_dev);
 943
 944         return 0;
 945 }
 946
 947 /*
 948  * Virtual Function device init
 949  */
 950 static int
 951 eth_igbvf_dev_init(struct rte_eth_dev *eth_dev)
 952 {
 953         struct rte_pci_device *pci_dev;
 954         struct e1000_adapter *adapter =
 955                 E1000_DEV_PRIVATE(eth_dev->data->dev_private);
 956         struct e1000_hw *hw =
 957                 E1000_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 958         int diag;
 959         struct ether_addr *perm_addr = (struct ether_addr *)hw->mac.perm_addr;
 960
 961         PMD_INIT_FUNC_TRACE();
 962
 963         eth_dev->dev_ops = &igbvf_eth_dev_ops;
 964         eth_dev->rx_pkt_burst = &eth_igb_recv_pkts;
 965         eth_dev->tx_pkt_burst = &eth_igb_xmit_pkts;
 966
 967         /* for secondary processes, we don't initialise any further as primary
 968          * has already done this work. Only check we don't need a different
 969          * RX function */
 970         if (rte_eal_process_type() != RTE_PROC_PRIMARY){
 971                 if (eth_dev->data->scattered_rx)
 972                         eth_dev->rx_pkt_burst = &eth_igb_recv_scattered_pkts;
 973                 return 0;
 974         }
 975
 976         pci_dev = eth_dev->pci_dev;
 977
 978         rte_eth_copy_pci_info(eth_dev, pci_dev);
 979
 980         hw->device_id = pci_dev->id.device_id;
 981         hw->vendor_id = pci_dev->id.vendor_id;
 982         hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
 983         adapter->stopped = 0;
 984
 985         /* Initialize the shared code (base driver) */
 986         diag = e1000_setup_init_funcs(hw, TRUE);
 987         if (diag != 0) {
 988                 PMD_INIT_LOG(ERR, "Shared code init failed for igbvf: %d",
 989                         diag);
 990                 return -EIO;
 991         }
 992
 993         /* init_mailbox_params */
 994         hw->mbx.ops.init_params(hw);
 995
 996         /* Disable the interrupts for VF */
 997         igbvf_intr_disable(hw);
 998
 999         diag = hw->mac.ops.reset_hw(hw);
1000
1001         /* Allocate memory for storing MAC addresses */
1002         eth_dev->data->mac_addrs = rte_zmalloc("igbvf", ETHER_ADDR_LEN *
1003                 hw->mac.rar_entry_count, 0);
1004         if (eth_dev->data->mac_addrs == NULL) {
1005                 PMD_INIT_LOG(ERR,
1006                         "Failed to allocate %d bytes needed to store MAC "
1007                         "addresses",
1008                         ETHER_ADDR_LEN * hw->mac.rar_entry_count);
1009                 return -ENOMEM;
1010         }
1011
1012         /* Generate a random MAC address, if none was assigned by PF. */
1013         if (is_zero_ether_addr(perm_addr)) {
1014                 eth_random_addr(perm_addr->addr_bytes);
1015                 PMD_INIT_LOG(INFO, "\tVF MAC address not assigned by Host PF");
1016                 PMD_INIT_LOG(INFO, "\tAssign randomly generated MAC address "
1017                              "%02x:%02x:%02x:%02x:%02x:%02x",
1018                              perm_addr->addr_bytes[0],
1019                              perm_addr->addr_bytes[1],
1020                              perm_addr->addr_bytes[2],
1021                              perm_addr->addr_bytes[3],
1022                              perm_addr->addr_bytes[4],
1023                              perm_addr->addr_bytes[5]);
1024         }
1025
1026         diag = e1000_rar_set(hw, perm_addr->addr_bytes, 0);
1027         if (diag) {
1028                 rte_free(eth_dev->data->mac_addrs);
1029                 eth_dev->data->mac_addrs = NULL;
1030                 return diag;
1031         }
1032         /* Copy the permanent MAC address */
1033         ether_addr_copy((struct ether_addr *) hw->mac.perm_addr,
1034                         &eth_dev->data->mac_addrs[0]);
1035
1036         PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x "
1037                      "mac.type=%s",
1038                      eth_dev->data->port_id, pci_dev->id.vendor_id,
1039                      pci_dev->id.device_id, "igb_mac_82576_vf");
1040
1041         rte_intr_callback_register(&pci_dev->intr_handle,
1042                                    eth_igbvf_interrupt_handler,
1043                                    (void *)eth_dev);
1044
1045         return 0;
1046 }
1047
1048 static int
1049 eth_igbvf_dev_uninit(struct rte_eth_dev *eth_dev)
1050 {
1051         struct e1000_adapter *adapter =
1052                 E1000_DEV_PRIVATE(eth_dev->data->dev_private);
1053         struct rte_pci_device *pci_dev = eth_dev->pci_dev;
1054
1055         PMD_INIT_FUNC_TRACE();
1056
1057         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1058                 return -EPERM;
1059
1060         if (adapter->stopped == 0)
1061                 igbvf_dev_close(eth_dev);
1062
1063         eth_dev->dev_ops = NULL;
1064         eth_dev->rx_pkt_burst = NULL;
1065         eth_dev->tx_pkt_burst = NULL;
1066
1067         rte_free(eth_dev->data->mac_addrs);
1068         eth_dev->data->mac_addrs = NULL;
1069
1070         /* disable uio intr before callback unregister */
1071         rte_intr_disable(&pci_dev->intr_handle);
1072         rte_intr_callback_unregister(&pci_dev->intr_handle,
1073                                      eth_igbvf_interrupt_handler,
1074                                      (void *)eth_dev);
1075
1076         return 0;
1077 }
1078
1079 static struct eth_driver rte_igb_pmd = {
1080         .pci_drv = {
1081                 .id_table = pci_id_igb_map,
1082                 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC |
1083                         RTE_PCI_DRV_DETACHABLE,
1084                 .probe = rte_eth_dev_pci_probe,
1085                 .remove = rte_eth_dev_pci_remove,
1086         },
1087         .eth_dev_init = eth_igb_dev_init,
1088         .eth_dev_uninit = eth_igb_dev_uninit,
1089         .dev_private_size = sizeof(struct e1000_adapter),
1090 };
1091
1092 /*
1093  * virtual function driver struct
1094  */
1095 static struct eth_driver rte_igbvf_pmd = {
1096         .pci_drv = {
1097                 .id_table = pci_id_igbvf_map,
1098                 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_DETACHABLE,
1099                 .probe = rte_eth_dev_pci_probe,
1100                 .remove = rte_eth_dev_pci_remove,
1101         },
1102         .eth_dev_init = eth_igbvf_dev_init,
1103         .eth_dev_uninit = eth_igbvf_dev_uninit,
1104         .dev_private_size = sizeof(struct e1000_adapter),
1105 };
1106
1107 static void
1108 igb_vmdq_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1109 {
1110         struct e1000_hw *hw =
1111                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1112         /* RCTL: enable VLAN filter since VMDq always use VLAN filter */
1113         uint32_t rctl = E1000_READ_REG(hw, E1000_RCTL);
1114         rctl |= E1000_RCTL_VFE;
1115         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1116 }
1117
1118 static int
1119 igb_check_mq_mode(struct rte_eth_dev *dev)
1120 {
1121         enum rte_eth_rx_mq_mode rx_mq_mode = dev->data->dev_conf.rxmode.mq_mode;
1122         enum rte_eth_tx_mq_mode tx_mq_mode = dev->data->dev_conf.txmode.mq_mode;
1123         uint16_t nb_rx_q = dev->data->nb_rx_queues;
1124         uint16_t nb_tx_q = dev->data->nb_rx_queues;
1125
1126         if ((rx_mq_mode & ETH_MQ_RX_DCB_FLAG) ||
1127             tx_mq_mode == ETH_MQ_TX_DCB ||
1128             tx_mq_mode == ETH_MQ_TX_VMDQ_DCB) {
1129                 PMD_INIT_LOG(ERR, "DCB mode is not supported.");
1130                 return -EINVAL;
1131         }
1132         if (RTE_ETH_DEV_SRIOV(dev).active != 0) {
1133                 /* Check multi-queue mode.
1134                  * To no break software we accept ETH_MQ_RX_NONE as this might
1135                  * be used to turn off VLAN filter.
1136                  */
1137
1138                 if (rx_mq_mode == ETH_MQ_RX_NONE ||
1139                     rx_mq_mode == ETH_MQ_RX_VMDQ_ONLY) {
1140                         dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_ONLY;
1141                         RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool = 1;
1142                 } else {
1143                         /* Only support one queue on VFs.
1144                          * RSS together with SRIOV is not supported.
1145                          */
1146                         PMD_INIT_LOG(ERR, "SRIOV is active,"
1147                                         " wrong mq_mode rx %d.",
1148                                         rx_mq_mode);
1149                         return -EINVAL;
1150                 }
1151                 /* TX mode is not used here, so mode might be ignored.*/
1152                 if (tx_mq_mode != ETH_MQ_TX_VMDQ_ONLY) {
1153                         /* SRIOV only works in VMDq enable mode */
1154                         PMD_INIT_LOG(WARNING, "SRIOV is active,"
1155                                         " TX mode %d is not supported. "
1156                                         " Driver will behave as %d mode.",
1157                                         tx_mq_mode, ETH_MQ_TX_VMDQ_ONLY);
1158                 }
1159
1160                 /* check valid queue number */
1161                 if ((nb_rx_q > 1) || (nb_tx_q > 1)) {
1162                         PMD_INIT_LOG(ERR, "SRIOV is active,"
1163                                         " only support one queue on VFs.");
1164                         return -EINVAL;
1165                 }
1166         } else {
1167                 /* To no break software that set invalid mode, only display
1168                  * warning if invalid mode is used.
1169                  */
1170                 if (rx_mq_mode != ETH_MQ_RX_NONE &&
1171                     rx_mq_mode != ETH_MQ_RX_VMDQ_ONLY &&
1172                     rx_mq_mode != ETH_MQ_RX_RSS) {
1173                         /* RSS together with VMDq not supported*/
1174                         PMD_INIT_LOG(ERR, "RX mode %d is not supported.",
1175                                      rx_mq_mode);
1176                         return -EINVAL;
1177                 }
1178
1179                 if (tx_mq_mode != ETH_MQ_TX_NONE &&
1180                     tx_mq_mode != ETH_MQ_TX_VMDQ_ONLY) {
1181                         PMD_INIT_LOG(WARNING, "TX mode %d is not supported."
1182                                         " Due to txmode is meaningless in this"
1183                                         " driver, just ignore.",
1184                                         tx_mq_mode);
1185                 }
1186         }
1187         return 0;
1188 }
1189
1190 static int
1191 eth_igb_configure(struct rte_eth_dev *dev)
1192 {
1193         struct e1000_interrupt *intr =
1194                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
1195         int ret;
1196
1197         PMD_INIT_FUNC_TRACE();
1198
1199         /* multipe queue mode checking */
1200         ret  = igb_check_mq_mode(dev);
1201         if (ret != 0) {
1202                 PMD_DRV_LOG(ERR, "igb_check_mq_mode fails with %d.",
1203                             ret);
1204                 return ret;
1205         }
1206
1207         intr->flags |= E1000_FLAG_NEED_LINK_UPDATE;
1208         PMD_INIT_FUNC_TRACE();
1209
1210         return 0;
1211 }
1212
1213 static int
1214 eth_igb_start(struct rte_eth_dev *dev)
1215 {
1216         struct e1000_hw *hw =
1217                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1218         struct e1000_adapter *adapter =
1219                 E1000_DEV_PRIVATE(dev->data->dev_private);
1220         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
1221         int ret, mask;
1222         uint32_t intr_vector = 0;
1223         uint32_t ctrl_ext;
1224         uint32_t *speeds;
1225         int num_speeds;
1226         bool autoneg;
1227
1228         PMD_INIT_FUNC_TRACE();
1229
1230         /* disable uio/vfio intr/eventfd mapping */
1231         rte_intr_disable(intr_handle);
1232
1233         /* Power up the phy. Needed to make the link go Up */
1234         eth_igb_dev_set_link_up(dev);
1235
1236         /*
1237          * Packet Buffer Allocation (PBA)
1238          * Writing PBA sets the receive portion of the buffer
1239          * the remainder is used for the transmit buffer.
1240          */
1241         if (hw->mac.type == e1000_82575) {
1242                 uint32_t pba;
1243
1244                 pba = E1000_PBA_32K; /* 32K for Rx, 16K for Tx */
1245                 E1000_WRITE_REG(hw, E1000_PBA, pba);
1246         }
1247
1248         /* Put the address into the Receive Address Array */
1249         e1000_rar_set(hw, hw->mac.addr, 0);
1250
1251         /* Initialize the hardware */
1252         if (igb_hardware_init(hw)) {
1253                 PMD_INIT_LOG(ERR, "Unable to initialize the hardware");
1254                 return -EIO;
1255         }
1256         adapter->stopped = 0;
1257
1258         E1000_WRITE_REG(hw, E1000_VET, ETHER_TYPE_VLAN << 16 | ETHER_TYPE_VLAN);
1259
1260         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
1261         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
1262         ctrl_ext |= E1000_CTRL_EXT_PFRSTD;
1263         E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
1264         E1000_WRITE_FLUSH(hw);
1265
1266         /* configure PF module if SRIOV enabled */
1267         igb_pf_host_configure(dev);
1268
1269         /* check and configure queue intr-vector mapping */
1270         if ((rte_intr_cap_multiple(intr_handle) ||
1271              !RTE_ETH_DEV_SRIOV(dev).active) &&
1272             dev->data->dev_conf.intr_conf.rxq != 0) {
1273                 intr_vector = dev->data->nb_rx_queues;
1274                 if (rte_intr_efd_enable(intr_handle, intr_vector))
1275                         return -1;
1276         }
1277
1278         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
1279                 intr_handle->intr_vec =
1280                         rte_zmalloc("intr_vec",
1281                                     dev->data->nb_rx_queues * sizeof(int), 0);
1282                 if (intr_handle->intr_vec == NULL) {
1283                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
1284                                      " intr_vec\n", dev->data->nb_rx_queues);
1285                         return -ENOMEM;
1286                 }
1287         }
1288
1289         /* confiugre msix for rx interrupt */
1290         eth_igb_configure_msix_intr(dev);
1291
1292         /* Configure for OS presence */
1293         igb_init_manageability(hw);
1294
1295         eth_igb_tx_init(dev);
1296
1297         /* This can fail when allocating mbufs for descriptor rings */
1298         ret = eth_igb_rx_init(dev);
1299         if (ret) {
1300                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
1301                 igb_dev_clear_queues(dev);
1302                 return ret;
1303         }
1304
1305         e1000_clear_hw_cntrs_base_generic(hw);
1306
1307         /*
1308          * VLAN Offload Settings
1309          */
1310         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK | \
1311                         ETH_VLAN_EXTEND_MASK;
1312         eth_igb_vlan_offload_set(dev, mask);
1313
1314         if (dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_VMDQ_ONLY) {
1315                 /* Enable VLAN filter since VMDq always use VLAN filter */
1316                 igb_vmdq_vlan_hw_filter_enable(dev);
1317         }
1318
1319         if ((hw->mac.type == e1000_82576) || (hw->mac.type == e1000_82580) ||
1320                 (hw->mac.type == e1000_i350) || (hw->mac.type == e1000_i210) ||
1321                 (hw->mac.type == e1000_i211)) {
1322                 /* Configure EITR with the maximum possible value (0xFFFF) */
1323                 E1000_WRITE_REG(hw, E1000_EITR(0), 0xFFFF);
1324         }
1325
1326         /* Setup link speed and duplex */
1327         speeds = &dev->data->dev_conf.link_speeds;
1328         if (*speeds == ETH_LINK_SPEED_AUTONEG) {
1329                 hw->phy.autoneg_advertised = E1000_ALL_SPEED_DUPLEX;
1330                 hw->mac.autoneg = 1;
1331         } else {
1332                 num_speeds = 0;
1333                 autoneg = (*speeds & ETH_LINK_SPEED_FIXED) == 0;
1334
1335                 /* Reset */
1336                 hw->phy.autoneg_advertised = 0;
1337
1338                 if (*speeds & ~(ETH_LINK_SPEED_10M_HD | ETH_LINK_SPEED_10M |
1339                                 ETH_LINK_SPEED_100M_HD | ETH_LINK_SPEED_100M |
1340                                 ETH_LINK_SPEED_1G | ETH_LINK_SPEED_FIXED)) {
1341                         num_speeds = -1;
1342                         goto error_invalid_config;
1343                 }
1344                 if (*speeds & ETH_LINK_SPEED_10M_HD) {
1345                         hw->phy.autoneg_advertised |= ADVERTISE_10_HALF;
1346                         num_speeds++;
1347                 }
1348                 if (*speeds & ETH_LINK_SPEED_10M) {
1349                         hw->phy.autoneg_advertised |= ADVERTISE_10_FULL;
1350                         num_speeds++;
1351                 }
1352                 if (*speeds & ETH_LINK_SPEED_100M_HD) {
1353                         hw->phy.autoneg_advertised |= ADVERTISE_100_HALF;
1354                         num_speeds++;
1355                 }
1356                 if (*speeds & ETH_LINK_SPEED_100M) {
1357                         hw->phy.autoneg_advertised |= ADVERTISE_100_FULL;
1358                         num_speeds++;
1359                 }
1360                 if (*speeds & ETH_LINK_SPEED_1G) {
1361                         hw->phy.autoneg_advertised |= ADVERTISE_1000_FULL;
1362                         num_speeds++;
1363                 }
1364                 if (num_speeds == 0 || (!autoneg && (num_speeds > 1)))
1365                         goto error_invalid_config;
1366
1367                 /* Set/reset the mac.autoneg based on the link speed,
1368                  * fixed or not
1369                  */
1370                 if (!autoneg) {
1371                         hw->mac.autoneg = 0;
1372                         hw->mac.forced_speed_duplex =
1373                                         hw->phy.autoneg_advertised;
1374                 } else {
1375                         hw->mac.autoneg = 1;
1376                 }
1377         }
1378
1379         e1000_setup_link(hw);
1380
1381         if (rte_intr_allow_others(intr_handle)) {
1382                 /* check if lsc interrupt is enabled */
1383                 if (dev->data->dev_conf.intr_conf.lsc != 0)
1384                         eth_igb_lsc_interrupt_setup(dev, TRUE);
1385                 else
1386                         eth_igb_lsc_interrupt_setup(dev, FALSE);
1387         } else {
1388                 rte_intr_callback_unregister(intr_handle,
1389                                              eth_igb_interrupt_handler,
1390                                              (void *)dev);
1391                 if (dev->data->dev_conf.intr_conf.lsc != 0)
1392                         PMD_INIT_LOG(INFO, "lsc won't enable because of"
1393                                      " no intr multiplex\n");
1394         }
1395
1396         /* check if rxq interrupt is enabled */
1397         if (dev->data->dev_conf.intr_conf.rxq != 0 &&
1398             rte_intr_dp_is_en(intr_handle))
1399                 eth_igb_rxq_interrupt_setup(dev);
1400
1401         /* enable uio/vfio intr/eventfd mapping */
1402         rte_intr_enable(intr_handle);
1403
1404         /* resume enabled intr since hw reset */
1405         igb_intr_enable(dev);
1406
1407         PMD_INIT_LOG(DEBUG, "<<");
1408
1409         return 0;
1410
1411 error_invalid_config:
1412         PMD_INIT_LOG(ERR, "Invalid advertised speeds (%u) for port %u",
1413                      dev->data->dev_conf.link_speeds, dev->data->port_id);
1414         igb_dev_clear_queues(dev);
1415         return -EINVAL;
1416 }
1417
1418 /*********************************************************************
1419  *
1420  *  This routine disables all traffic on the adapter by issuing a
1421  *  global reset on the MAC.
1422  *
1423  **********************************************************************/
1424 static void
1425 eth_igb_stop(struct rte_eth_dev *dev)
1426 {
1427         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1428         struct e1000_filter_info *filter_info =
1429                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
1430         struct rte_eth_link link;
1431         struct e1000_flex_filter *p_flex;
1432         struct e1000_5tuple_filter *p_5tuple, *p_5tuple_next;
1433         struct e1000_2tuple_filter *p_2tuple, *p_2tuple_next;
1434         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
1435
1436         igb_intr_disable(hw);
1437
1438         /* disable intr eventfd mapping */
1439         rte_intr_disable(intr_handle);
1440
1441         igb_pf_reset_hw(hw);
1442         E1000_WRITE_REG(hw, E1000_WUC, 0);
1443
1444         /* Set bit for Go Link disconnect */
1445         if (hw->mac.type >= e1000_82580) {
1446                 uint32_t phpm_reg;
1447
1448                 phpm_reg = E1000_READ_REG(hw, E1000_82580_PHY_POWER_MGMT);
1449                 phpm_reg |= E1000_82580_PM_GO_LINKD;
1450                 E1000_WRITE_REG(hw, E1000_82580_PHY_POWER_MGMT, phpm_reg);
1451         }
1452
1453         /* Power down the phy. Needed to make the link go Down */
1454         eth_igb_dev_set_link_down(dev);
1455
1456         igb_dev_clear_queues(dev);
1457
1458         /* clear the recorded link status */
1459         memset(&link, 0, sizeof(link));
1460         rte_igb_dev_atomic_write_link_status(dev, &link);
1461
1462         /* Remove all flex filters of the device */
1463         while ((p_flex = TAILQ_FIRST(&filter_info->flex_list))) {
1464                 TAILQ_REMOVE(&filter_info->flex_list, p_flex, entries);
1465                 rte_free(p_flex);
1466         }
1467         filter_info->flex_mask = 0;
1468
1469         /* Remove all ntuple filters of the device */
1470         for (p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list);
1471              p_5tuple != NULL; p_5tuple = p_5tuple_next) {
1472                 p_5tuple_next = TAILQ_NEXT(p_5tuple, entries);
1473                 TAILQ_REMOVE(&filter_info->fivetuple_list,
1474                              p_5tuple, entries);
1475                 rte_free(p_5tuple);
1476         }
1477         filter_info->fivetuple_mask = 0;
1478         for (p_2tuple = TAILQ_FIRST(&filter_info->twotuple_list);
1479              p_2tuple != NULL; p_2tuple = p_2tuple_next) {
1480                 p_2tuple_next = TAILQ_NEXT(p_2tuple, entries);
1481                 TAILQ_REMOVE(&filter_info->twotuple_list,
1482                              p_2tuple, entries);
1483                 rte_free(p_2tuple);
1484         }
1485         filter_info->twotuple_mask = 0;
1486
1487         if (!rte_intr_allow_others(intr_handle))
1488                 /* resume to the default handler */
1489                 rte_intr_callback_register(intr_handle,
1490                                            eth_igb_interrupt_handler,
1491                                            (void *)dev);
1492
1493         /* Clean datapath event and queue/vec mapping */
1494         rte_intr_efd_disable(intr_handle);
1495         if (intr_handle->intr_vec != NULL) {
1496                 rte_free(intr_handle->intr_vec);
1497                 intr_handle->intr_vec = NULL;
1498         }
1499 }
1500
1501 static int
1502 eth_igb_dev_set_link_up(struct rte_eth_dev *dev)
1503 {
1504         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1505
1506         if (hw->phy.media_type == e1000_media_type_copper)
1507                 e1000_power_up_phy(hw);
1508         else
1509                 e1000_power_up_fiber_serdes_link(hw);
1510
1511         return 0;
1512 }
1513
1514 static int
1515 eth_igb_dev_set_link_down(struct rte_eth_dev *dev)
1516 {
1517         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1518
1519         if (hw->phy.media_type == e1000_media_type_copper)
1520                 e1000_power_down_phy(hw);
1521         else
1522                 e1000_shutdown_fiber_serdes_link(hw);
1523
1524         return 0;
1525 }
1526
1527 static void
1528 eth_igb_close(struct rte_eth_dev *dev)
1529 {
1530         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1531         struct e1000_adapter *adapter =
1532                 E1000_DEV_PRIVATE(dev->data->dev_private);
1533         struct rte_eth_link link;
1534         struct rte_pci_device *pci_dev;
1535
1536         eth_igb_stop(dev);
1537         adapter->stopped = 1;
1538
1539         e1000_phy_hw_reset(hw);
1540         igb_release_manageability(hw);
1541         igb_hw_control_release(hw);
1542
1543         /* Clear bit for Go Link disconnect */
1544         if (hw->mac.type >= e1000_82580) {
1545                 uint32_t phpm_reg;
1546
1547                 phpm_reg = E1000_READ_REG(hw, E1000_82580_PHY_POWER_MGMT);
1548                 phpm_reg &= ~E1000_82580_PM_GO_LINKD;
1549                 E1000_WRITE_REG(hw, E1000_82580_PHY_POWER_MGMT, phpm_reg);
1550         }
1551
1552         igb_dev_free_queues(dev);
1553
1554         pci_dev = dev->pci_dev;
1555         if (pci_dev->intr_handle.intr_vec) {
1556                 rte_free(pci_dev->intr_handle.intr_vec);
1557                 pci_dev->intr_handle.intr_vec = NULL;
1558         }
1559
1560         memset(&link, 0, sizeof(link));
1561         rte_igb_dev_atomic_write_link_status(dev, &link);
1562 }
1563
1564 static int
1565 igb_get_rx_buffer_size(struct e1000_hw *hw)
1566 {
1567         uint32_t rx_buf_size;
1568         if (hw->mac.type == e1000_82576) {
1569                 rx_buf_size = (E1000_READ_REG(hw, E1000_RXPBS) & 0xffff) << 10;
1570         } else if (hw->mac.type == e1000_82580 || hw->mac.type == e1000_i350) {
1571                 /* PBS needs to be translated according to a lookup table */
1572                 rx_buf_size = (E1000_READ_REG(hw, E1000_RXPBS) & 0xf);
1573                 rx_buf_size = (uint32_t) e1000_rxpbs_adjust_82580(rx_buf_size);
1574                 rx_buf_size = (rx_buf_size << 10);
1575         } else if (hw->mac.type == e1000_i210 || hw->mac.type == e1000_i211) {
1576                 rx_buf_size = (E1000_READ_REG(hw, E1000_RXPBS) & 0x3f) << 10;
1577         } else {
1578                 rx_buf_size = (E1000_READ_REG(hw, E1000_PBA) & 0xffff) << 10;
1579         }
1580
1581         return rx_buf_size;
1582 }
1583
1584 /*********************************************************************
1585  *
1586  *  Initialize the hardware
1587  *
1588  **********************************************************************/
1589 static int
1590 igb_hardware_init(struct e1000_hw *hw)
1591 {
1592         uint32_t rx_buf_size;
1593         int diag;
1594
1595         /* Let the firmware know the OS is in control */
1596         igb_hw_control_acquire(hw);
1597
1598         /*
1599          * These parameters control the automatic generation (Tx) and
1600          * response (Rx) to Ethernet PAUSE frames.
1601          * - High water mark should allow for at least two standard size (1518)
1602          *   frames to be received after sending an XOFF.
1603          * - Low water mark works best when it is very near the high water mark.
1604          *   This allows the receiver to restart by sending XON when it has
1605          *   drained a bit. Here we use an arbitrary value of 1500 which will
1606          *   restart after one full frame is pulled from the buffer. There
1607          *   could be several smaller frames in the buffer and if so they will
1608          *   not trigger the XON until their total number reduces the buffer
1609          *   by 1500.
1610          * - The pause time is fairly large at 1000 x 512ns = 512 usec.
1611          */
1612         rx_buf_size = igb_get_rx_buffer_size(hw);
1613
1614         hw->fc.high_water = rx_buf_size - (ETHER_MAX_LEN * 2);
1615         hw->fc.low_water = hw->fc.high_water - 1500;
1616         hw->fc.pause_time = IGB_FC_PAUSE_TIME;
1617         hw->fc.send_xon = 1;
1618
1619         /* Set Flow control, use the tunable location if sane */
1620         if ((igb_fc_setting != e1000_fc_none) && (igb_fc_setting < 4))
1621                 hw->fc.requested_mode = igb_fc_setting;
1622         else
1623                 hw->fc.requested_mode = e1000_fc_none;
1624
1625         /* Issue a global reset */
1626         igb_pf_reset_hw(hw);
1627         E1000_WRITE_REG(hw, E1000_WUC, 0);
1628
1629         diag = e1000_init_hw(hw);
1630         if (diag < 0)
1631                 return diag;
1632
1633         E1000_WRITE_REG(hw, E1000_VET, ETHER_TYPE_VLAN << 16 | ETHER_TYPE_VLAN);
1634         e1000_get_phy_info(hw);
1635         e1000_check_for_link(hw);
1636
1637         return 0;
1638 }
1639
1640 /* This function is based on igb_update_stats_counters() in igb/if_igb.c */
1641 static void
1642 igb_read_stats_registers(struct e1000_hw *hw, struct e1000_hw_stats *stats)
1643 {
1644         int pause_frames;
1645
1646         uint64_t old_gprc  = stats->gprc;
1647         uint64_t old_gptc  = stats->gptc;
1648         uint64_t old_tpr   = stats->tpr;
1649         uint64_t old_tpt   = stats->tpt;
1650         uint64_t old_rpthc = stats->rpthc;
1651         uint64_t old_hgptc = stats->hgptc;
1652
1653         if(hw->phy.media_type == e1000_media_type_copper ||
1654             (E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU)) {
1655                 stats->symerrs +=
1656                     E1000_READ_REG(hw,E1000_SYMERRS);
1657                 stats->sec += E1000_READ_REG(hw, E1000_SEC);
1658         }
1659
1660         stats->crcerrs += E1000_READ_REG(hw, E1000_CRCERRS);
1661         stats->mpc += E1000_READ_REG(hw, E1000_MPC);
1662         stats->scc += E1000_READ_REG(hw, E1000_SCC);
1663         stats->ecol += E1000_READ_REG(hw, E1000_ECOL);
1664
1665         stats->mcc += E1000_READ_REG(hw, E1000_MCC);
1666         stats->latecol += E1000_READ_REG(hw, E1000_LATECOL);
1667         stats->colc += E1000_READ_REG(hw, E1000_COLC);
1668         stats->dc += E1000_READ_REG(hw, E1000_DC);
1669         stats->rlec += E1000_READ_REG(hw, E1000_RLEC);
1670         stats->xonrxc += E1000_READ_REG(hw, E1000_XONRXC);
1671         stats->xontxc += E1000_READ_REG(hw, E1000_XONTXC);
1672         /*
1673         ** For watchdog management we need to know if we have been
1674         ** paused during the last interval, so capture that here.
1675         */
1676         pause_frames = E1000_READ_REG(hw, E1000_XOFFRXC);
1677         stats->xoffrxc += pause_frames;
1678         stats->xofftxc += E1000_READ_REG(hw, E1000_XOFFTXC);
1679         stats->fcruc += E1000_READ_REG(hw, E1000_FCRUC);
1680         stats->prc64 += E1000_READ_REG(hw, E1000_PRC64);
1681         stats->prc127 += E1000_READ_REG(hw, E1000_PRC127);
1682         stats->prc255 += E1000_READ_REG(hw, E1000_PRC255);
1683         stats->prc511 += E1000_READ_REG(hw, E1000_PRC511);
1684         stats->prc1023 += E1000_READ_REG(hw, E1000_PRC1023);
1685         stats->prc1522 += E1000_READ_REG(hw, E1000_PRC1522);
1686         stats->gprc += E1000_READ_REG(hw, E1000_GPRC);
1687         stats->bprc += E1000_READ_REG(hw, E1000_BPRC);
1688         stats->mprc += E1000_READ_REG(hw, E1000_MPRC);
1689         stats->gptc += E1000_READ_REG(hw, E1000_GPTC);
1690
1691         /* For the 64-bit byte counters the low dword must be read first. */
1692         /* Both registers clear on the read of the high dword */
1693
1694         /* Workaround CRC bytes included in size, take away 4 bytes/packet */
1695         stats->gorc += E1000_READ_REG(hw, E1000_GORCL);
1696         stats->gorc += ((uint64_t)E1000_READ_REG(hw, E1000_GORCH) << 32);
1697         stats->gorc -= (stats->gprc - old_gprc) * ETHER_CRC_LEN;
1698         stats->gotc += E1000_READ_REG(hw, E1000_GOTCL);
1699         stats->gotc += ((uint64_t)E1000_READ_REG(hw, E1000_GOTCH) << 32);
1700         stats->gotc -= (stats->gptc - old_gptc) * ETHER_CRC_LEN;
1701
1702         stats->rnbc += E1000_READ_REG(hw, E1000_RNBC);
1703         stats->ruc += E1000_READ_REG(hw, E1000_RUC);
1704         stats->rfc += E1000_READ_REG(hw, E1000_RFC);
1705         stats->roc += E1000_READ_REG(hw, E1000_ROC);
1706         stats->rjc += E1000_READ_REG(hw, E1000_RJC);
1707
1708         stats->tpr += E1000_READ_REG(hw, E1000_TPR);
1709         stats->tpt += E1000_READ_REG(hw, E1000_TPT);
1710
1711         stats->tor += E1000_READ_REG(hw, E1000_TORL);
1712         stats->tor += ((uint64_t)E1000_READ_REG(hw, E1000_TORH) << 32);
1713         stats->tor -= (stats->tpr - old_tpr) * ETHER_CRC_LEN;
1714         stats->tot += E1000_READ_REG(hw, E1000_TOTL);
1715         stats->tot += ((uint64_t)E1000_READ_REG(hw, E1000_TOTH) << 32);
1716         stats->tot -= (stats->tpt - old_tpt) * ETHER_CRC_LEN;
1717
1718         stats->ptc64 += E1000_READ_REG(hw, E1000_PTC64);
1719         stats->ptc127 += E1000_READ_REG(hw, E1000_PTC127);
1720         stats->ptc255 += E1000_READ_REG(hw, E1000_PTC255);
1721         stats->ptc511 += E1000_READ_REG(hw, E1000_PTC511);
1722         stats->ptc1023 += E1000_READ_REG(hw, E1000_PTC1023);
1723         stats->ptc1522 += E1000_READ_REG(hw, E1000_PTC1522);
1724         stats->mptc += E1000_READ_REG(hw, E1000_MPTC);
1725         stats->bptc += E1000_READ_REG(hw, E1000_BPTC);
1726
1727         /* Interrupt Counts */
1728
1729         stats->iac += E1000_READ_REG(hw, E1000_IAC);
1730         stats->icrxptc += E1000_READ_REG(hw, E1000_ICRXPTC);
1731         stats->icrxatc += E1000_READ_REG(hw, E1000_ICRXATC);
1732         stats->ictxptc += E1000_READ_REG(hw, E1000_ICTXPTC);
1733         stats->ictxatc += E1000_READ_REG(hw, E1000_ICTXATC);
1734         stats->ictxqec += E1000_READ_REG(hw, E1000_ICTXQEC);
1735         stats->ictxqmtc += E1000_READ_REG(hw, E1000_ICTXQMTC);
1736         stats->icrxdmtc += E1000_READ_REG(hw, E1000_ICRXDMTC);
1737         stats->icrxoc += E1000_READ_REG(hw, E1000_ICRXOC);
1738
1739         /* Host to Card Statistics */
1740
1741         stats->cbtmpc += E1000_READ_REG(hw, E1000_CBTMPC);
1742         stats->htdpmc += E1000_READ_REG(hw, E1000_HTDPMC);
1743         stats->cbrdpc += E1000_READ_REG(hw, E1000_CBRDPC);
1744         stats->cbrmpc += E1000_READ_REG(hw, E1000_CBRMPC);
1745         stats->rpthc += E1000_READ_REG(hw, E1000_RPTHC);
1746         stats->hgptc += E1000_READ_REG(hw, E1000_HGPTC);
1747         stats->htcbdpc += E1000_READ_REG(hw, E1000_HTCBDPC);
1748         stats->hgorc += E1000_READ_REG(hw, E1000_HGORCL);
1749         stats->hgorc += ((uint64_t)E1000_READ_REG(hw, E1000_HGORCH) << 32);
1750         stats->hgorc -= (stats->rpthc - old_rpthc) * ETHER_CRC_LEN;
1751         stats->hgotc += E1000_READ_REG(hw, E1000_HGOTCL);
1752         stats->hgotc += ((uint64_t)E1000_READ_REG(hw, E1000_HGOTCH) << 32);
1753         stats->hgotc -= (stats->hgptc - old_hgptc) * ETHER_CRC_LEN;
1754         stats->lenerrs += E1000_READ_REG(hw, E1000_LENERRS);
1755         stats->scvpc += E1000_READ_REG(hw, E1000_SCVPC);
1756         stats->hrmpc += E1000_READ_REG(hw, E1000_HRMPC);
1757
1758         stats->algnerrc += E1000_READ_REG(hw, E1000_ALGNERRC);
1759         stats->rxerrc += E1000_READ_REG(hw, E1000_RXERRC);
1760         stats->tncrs += E1000_READ_REG(hw, E1000_TNCRS);
1761         stats->cexterr += E1000_READ_REG(hw, E1000_CEXTERR);
1762         stats->tsctc += E1000_READ_REG(hw, E1000_TSCTC);
1763         stats->tsctfc += E1000_READ_REG(hw, E1000_TSCTFC);
1764 }
1765
1766 static void
1767 eth_igb_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *rte_stats)
1768 {
1769         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1770         struct e1000_hw_stats *stats =
1771                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1772
1773         igb_read_stats_registers(hw, stats);
1774
1775         if (rte_stats == NULL)
1776                 return;
1777
1778         /* Rx Errors */
1779         rte_stats->imissed = stats->mpc;
1780         rte_stats->ierrors = stats->crcerrs +
1781                              stats->rlec + stats->ruc + stats->roc +
1782                              stats->rxerrc + stats->algnerrc + stats->cexterr;
1783
1784         /* Tx Errors */
1785         rte_stats->oerrors = stats->ecol + stats->latecol;
1786
1787         rte_stats->ipackets = stats->gprc;
1788         rte_stats->opackets = stats->gptc;
1789         rte_stats->ibytes   = stats->gorc;
1790         rte_stats->obytes   = stats->gotc;
1791 }
1792
1793 static void
1794 eth_igb_stats_reset(struct rte_eth_dev *dev)
1795 {
1796         struct e1000_hw_stats *hw_stats =
1797                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1798
1799         /* HW registers are cleared on read */
1800         eth_igb_stats_get(dev, NULL);
1801
1802         /* Reset software totals */
1803         memset(hw_stats, 0, sizeof(*hw_stats));
1804 }
1805
1806 static void
1807 eth_igb_xstats_reset(struct rte_eth_dev *dev)
1808 {
1809         struct e1000_hw_stats *stats =
1810                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1811
1812         /* HW registers are cleared on read */
1813         eth_igb_xstats_get(dev, NULL, IGB_NB_XSTATS);
1814
1815         /* Reset software totals */
1816         memset(stats, 0, sizeof(*stats));
1817 }
1818
1819 static int eth_igb_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
1820         struct rte_eth_xstat_name *xstats_names,
1821         __rte_unused unsigned limit)
1822 {
1823         unsigned i;
1824
1825         if (xstats_names == NULL)
1826                 return IGB_NB_XSTATS;
1827
1828         /* Note: limit checked in rte_eth_xstats_names() */
1829
1830         for (i = 0; i < IGB_NB_XSTATS; i++) {
1831                 snprintf(xstats_names[i].name, sizeof(xstats_names[i].name),
1832                          "%s", rte_igb_stats_strings[i].name);
1833         }
1834
1835         return IGB_NB_XSTATS;
1836 }
1837
1838 static int
1839 eth_igb_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
1840                    unsigned n)
1841 {
1842         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1843         struct e1000_hw_stats *hw_stats =
1844                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1845         unsigned i;
1846
1847         if (n < IGB_NB_XSTATS)
1848                 return IGB_NB_XSTATS;
1849
1850         igb_read_stats_registers(hw, hw_stats);
1851
1852         /* If this is a reset xstats is NULL, and we have cleared the
1853          * registers by reading them.
1854          */
1855         if (!xstats)
1856                 return 0;
1857
1858         /* Extended stats */
1859         for (i = 0; i < IGB_NB_XSTATS; i++) {
1860                 xstats[i].id = i;
1861                 xstats[i].value = *(uint64_t *)(((char *)hw_stats) +
1862                         rte_igb_stats_strings[i].offset);
1863         }
1864
1865         return IGB_NB_XSTATS;
1866 }
1867
1868 static void
1869 igbvf_read_stats_registers(struct e1000_hw *hw, struct e1000_vf_stats *hw_stats)
1870 {
1871         /* Good Rx packets, include VF loopback */
1872         UPDATE_VF_STAT(E1000_VFGPRC,
1873             hw_stats->last_gprc, hw_stats->gprc);
1874
1875         /* Good Rx octets, include VF loopback */
1876         UPDATE_VF_STAT(E1000_VFGORC,
1877             hw_stats->last_gorc, hw_stats->gorc);
1878
1879         /* Good Tx packets, include VF loopback */
1880         UPDATE_VF_STAT(E1000_VFGPTC,
1881             hw_stats->last_gptc, hw_stats->gptc);
1882
1883         /* Good Tx octets, include VF loopback */
1884         UPDATE_VF_STAT(E1000_VFGOTC,
1885             hw_stats->last_gotc, hw_stats->gotc);
1886
1887         /* Rx Multicst packets */
1888         UPDATE_VF_STAT(E1000_VFMPRC,
1889             hw_stats->last_mprc, hw_stats->mprc);
1890
1891         /* Good Rx loopback packets */
1892         UPDATE_VF_STAT(E1000_VFGPRLBC,
1893             hw_stats->last_gprlbc, hw_stats->gprlbc);
1894
1895         /* Good Rx loopback octets */
1896         UPDATE_VF_STAT(E1000_VFGORLBC,
1897             hw_stats->last_gorlbc, hw_stats->gorlbc);
1898
1899         /* Good Tx loopback packets */
1900         UPDATE_VF_STAT(E1000_VFGPTLBC,
1901             hw_stats->last_gptlbc, hw_stats->gptlbc);
1902
1903         /* Good Tx loopback octets */
1904         UPDATE_VF_STAT(E1000_VFGOTLBC,
1905             hw_stats->last_gotlbc, hw_stats->gotlbc);
1906 }
1907
1908 static int eth_igbvf_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
1909                                      struct rte_eth_xstat_name *xstats_names,
1910                                      __rte_unused unsigned limit)
1911 {
1912         unsigned i;
1913
1914         if (xstats_names != NULL)
1915                 for (i = 0; i < IGBVF_NB_XSTATS; i++) {
1916                         snprintf(xstats_names[i].name,
1917                                 sizeof(xstats_names[i].name), "%s",
1918                                 rte_igbvf_stats_strings[i].name);
1919                 }
1920         return IGBVF_NB_XSTATS;
1921 }
1922
1923 static int
1924 eth_igbvf_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
1925                      unsigned n)
1926 {
1927         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1928         struct e1000_vf_stats *hw_stats = (struct e1000_vf_stats *)
1929                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1930         unsigned i;
1931
1932         if (n < IGBVF_NB_XSTATS)
1933                 return IGBVF_NB_XSTATS;
1934
1935         igbvf_read_stats_registers(hw, hw_stats);
1936
1937         if (!xstats)
1938                 return 0;
1939
1940         for (i = 0; i < IGBVF_NB_XSTATS; i++) {
1941                 xstats[i].id = i;
1942                 xstats[i].value = *(uint64_t *)(((char *)hw_stats) +
1943                         rte_igbvf_stats_strings[i].offset);
1944         }
1945
1946         return IGBVF_NB_XSTATS;
1947 }
1948
1949 static void
1950 eth_igbvf_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *rte_stats)
1951 {
1952         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1953         struct e1000_vf_stats *hw_stats = (struct e1000_vf_stats *)
1954                           E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1955
1956         igbvf_read_stats_registers(hw, hw_stats);
1957
1958         if (rte_stats == NULL)
1959                 return;
1960
1961         rte_stats->ipackets = hw_stats->gprc;
1962         rte_stats->ibytes = hw_stats->gorc;
1963         rte_stats->opackets = hw_stats->gptc;
1964         rte_stats->obytes = hw_stats->gotc;
1965 }
1966
1967 static void
1968 eth_igbvf_stats_reset(struct rte_eth_dev *dev)
1969 {
1970         struct e1000_vf_stats *hw_stats = (struct e1000_vf_stats*)
1971                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1972
1973         /* Sync HW register to the last stats */
1974         eth_igbvf_stats_get(dev, NULL);
1975
1976         /* reset HW current stats*/
1977         memset(&hw_stats->gprc, 0, sizeof(*hw_stats) -
1978                offsetof(struct e1000_vf_stats, gprc));
1979 }
1980
1981 static void
1982 eth_igb_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
1983 {
1984         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1985
1986         dev_info->min_rx_bufsize = 256; /* See BSIZE field of RCTL register. */
1987         dev_info->max_rx_pktlen  = 0x3FFF; /* See RLPML register. */
1988         dev_info->max_mac_addrs = hw->mac.rar_entry_count;
1989         dev_info->rx_offload_capa =
1990                 DEV_RX_OFFLOAD_VLAN_STRIP |
1991                 DEV_RX_OFFLOAD_IPV4_CKSUM |
1992                 DEV_RX_OFFLOAD_UDP_CKSUM  |
1993                 DEV_RX_OFFLOAD_TCP_CKSUM;
1994         dev_info->tx_offload_capa =
1995                 DEV_TX_OFFLOAD_VLAN_INSERT |
1996                 DEV_TX_OFFLOAD_IPV4_CKSUM  |
1997                 DEV_TX_OFFLOAD_UDP_CKSUM   |
1998                 DEV_TX_OFFLOAD_TCP_CKSUM   |
1999                 DEV_TX_OFFLOAD_SCTP_CKSUM  |
2000                 DEV_TX_OFFLOAD_TCP_TSO;
2001
2002         switch (hw->mac.type) {
2003         case e1000_82575:
2004                 dev_info->max_rx_queues = 4;
2005                 dev_info->max_tx_queues = 4;
2006                 dev_info->max_vmdq_pools = 0;
2007                 break;
2008
2009         case e1000_82576:
2010                 dev_info->max_rx_queues = 16;
2011                 dev_info->max_tx_queues = 16;
2012                 dev_info->max_vmdq_pools = ETH_8_POOLS;
2013                 dev_info->vmdq_queue_num = 16;
2014                 break;
2015
2016         case e1000_82580:
2017                 dev_info->max_rx_queues = 8;
2018                 dev_info->max_tx_queues = 8;
2019                 dev_info->max_vmdq_pools = ETH_8_POOLS;
2020                 dev_info->vmdq_queue_num = 8;
2021                 break;
2022
2023         case e1000_i350:
2024                 dev_info->max_rx_queues = 8;
2025                 dev_info->max_tx_queues = 8;
2026                 dev_info->max_vmdq_pools = ETH_8_POOLS;
2027                 dev_info->vmdq_queue_num = 8;
2028                 break;
2029
2030         case e1000_i354:
2031                 dev_info->max_rx_queues = 8;
2032                 dev_info->max_tx_queues = 8;
2033                 break;
2034
2035         case e1000_i210:
2036                 dev_info->max_rx_queues = 4;
2037                 dev_info->max_tx_queues = 4;
2038                 dev_info->max_vmdq_pools = 0;
2039                 break;
2040
2041         case e1000_i211:
2042                 dev_info->max_rx_queues = 2;
2043                 dev_info->max_tx_queues = 2;
2044                 dev_info->max_vmdq_pools = 0;
2045                 break;
2046
2047         default:
2048                 /* Should not happen */
2049                 break;
2050         }
2051         dev_info->hash_key_size = IGB_HKEY_MAX_INDEX * sizeof(uint32_t);
2052         dev_info->reta_size = ETH_RSS_RETA_SIZE_128;
2053         dev_info->flow_type_rss_offloads = IGB_RSS_OFFLOAD_ALL;
2054
2055         dev_info->default_rxconf = (struct rte_eth_rxconf) {
2056                 .rx_thresh = {
2057                         .pthresh = IGB_DEFAULT_RX_PTHRESH,
2058                         .hthresh = IGB_DEFAULT_RX_HTHRESH,
2059                         .wthresh = IGB_DEFAULT_RX_WTHRESH,
2060                 },
2061                 .rx_free_thresh = IGB_DEFAULT_RX_FREE_THRESH,
2062                 .rx_drop_en = 0,
2063         };
2064
2065         dev_info->default_txconf = (struct rte_eth_txconf) {
2066                 .tx_thresh = {
2067                         .pthresh = IGB_DEFAULT_TX_PTHRESH,
2068                         .hthresh = IGB_DEFAULT_TX_HTHRESH,
2069                         .wthresh = IGB_DEFAULT_TX_WTHRESH,
2070                 },
2071                 .txq_flags = 0,
2072         };
2073
2074         dev_info->rx_desc_lim = rx_desc_lim;
2075         dev_info->tx_desc_lim = tx_desc_lim;
2076
2077         dev_info->speed_capa = ETH_LINK_SPEED_10M_HD | ETH_LINK_SPEED_10M |
2078                         ETH_LINK_SPEED_100M_HD | ETH_LINK_SPEED_100M |
2079                         ETH_LINK_SPEED_1G;
2080 }
2081
2082 static const uint32_t *
2083 eth_igb_supported_ptypes_get(struct rte_eth_dev *dev)
2084 {
2085         static const uint32_t ptypes[] = {
2086                 /* refers to igb_rxd_pkt_info_to_pkt_type() */
2087                 RTE_PTYPE_L2_ETHER,
2088                 RTE_PTYPE_L3_IPV4,
2089                 RTE_PTYPE_L3_IPV4_EXT,
2090                 RTE_PTYPE_L3_IPV6,
2091                 RTE_PTYPE_L3_IPV6_EXT,
2092                 RTE_PTYPE_L4_TCP,
2093                 RTE_PTYPE_L4_UDP,
2094                 RTE_PTYPE_L4_SCTP,
2095                 RTE_PTYPE_TUNNEL_IP,
2096                 RTE_PTYPE_INNER_L3_IPV6,
2097                 RTE_PTYPE_INNER_L3_IPV6_EXT,
2098                 RTE_PTYPE_INNER_L4_TCP,
2099                 RTE_PTYPE_INNER_L4_UDP,
2100                 RTE_PTYPE_UNKNOWN
2101         };
2102
2103         if (dev->rx_pkt_burst == eth_igb_recv_pkts ||
2104             dev->rx_pkt_burst == eth_igb_recv_scattered_pkts)
2105                 return ptypes;
2106         return NULL;
2107 }
2108
2109 static void
2110 eth_igbvf_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
2111 {
2112         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2113
2114         dev_info->min_rx_bufsize = 256; /* See BSIZE field of RCTL register. */
2115         dev_info->max_rx_pktlen  = 0x3FFF; /* See RLPML register. */
2116         dev_info->max_mac_addrs = hw->mac.rar_entry_count;
2117         dev_info->rx_offload_capa = DEV_RX_OFFLOAD_VLAN_STRIP |
2118                                 DEV_RX_OFFLOAD_IPV4_CKSUM |
2119                                 DEV_RX_OFFLOAD_UDP_CKSUM  |
2120                                 DEV_RX_OFFLOAD_TCP_CKSUM;
2121         dev_info->tx_offload_capa = DEV_TX_OFFLOAD_VLAN_INSERT |
2122                                 DEV_TX_OFFLOAD_IPV4_CKSUM  |
2123                                 DEV_TX_OFFLOAD_UDP_CKSUM   |
2124                                 DEV_TX_OFFLOAD_TCP_CKSUM   |
2125                                 DEV_TX_OFFLOAD_SCTP_CKSUM  |
2126                                 DEV_TX_OFFLOAD_TCP_TSO;
2127         switch (hw->mac.type) {
2128         case e1000_vfadapt:
2129                 dev_info->max_rx_queues = 2;
2130                 dev_info->max_tx_queues = 2;
2131                 break;
2132         case e1000_vfadapt_i350:
2133                 dev_info->max_rx_queues = 1;
2134                 dev_info->max_tx_queues = 1;
2135                 break;
2136         default:
2137                 /* Should not happen */
2138                 break;
2139         }
2140
2141         dev_info->default_rxconf = (struct rte_eth_rxconf) {
2142                 .rx_thresh = {
2143                         .pthresh = IGB_DEFAULT_RX_PTHRESH,
2144                         .hthresh = IGB_DEFAULT_RX_HTHRESH,
2145                         .wthresh = IGB_DEFAULT_RX_WTHRESH,
2146                 },
2147                 .rx_free_thresh = IGB_DEFAULT_RX_FREE_THRESH,
2148                 .rx_drop_en = 0,
2149         };
2150
2151         dev_info->default_txconf = (struct rte_eth_txconf) {
2152                 .tx_thresh = {
2153                         .pthresh = IGB_DEFAULT_TX_PTHRESH,
2154                         .hthresh = IGB_DEFAULT_TX_HTHRESH,
2155                         .wthresh = IGB_DEFAULT_TX_WTHRESH,
2156                 },
2157                 .txq_flags = 0,
2158         };
2159
2160         dev_info->rx_desc_lim = rx_desc_lim;
2161         dev_info->tx_desc_lim = tx_desc_lim;
2162 }
2163
2164 /* return 0 means link status changed, -1 means not changed */
2165 static int
2166 eth_igb_link_update(struct rte_eth_dev *dev, int wait_to_complete)
2167 {
2168         struct e1000_hw *hw =
2169                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2170         struct rte_eth_link link, old;
2171         int link_check, count;
2172
2173         link_check = 0;
2174         hw->mac.get_link_status = 1;
2175
2176         /* possible wait-to-complete in up to 9 seconds */
2177         for (count = 0; count < IGB_LINK_UPDATE_CHECK_TIMEOUT; count ++) {
2178                 /* Read the real link status */
2179                 switch (hw->phy.media_type) {
2180                 case e1000_media_type_copper:
2181                         /* Do the work to read phy */
2182                         e1000_check_for_link(hw);
2183                         link_check = !hw->mac.get_link_status;
2184                         break;
2185
2186                 case e1000_media_type_fiber:
2187                         e1000_check_for_link(hw);
2188                         link_check = (E1000_READ_REG(hw, E1000_STATUS) &
2189                                       E1000_STATUS_LU);
2190                         break;
2191
2192                 case e1000_media_type_internal_serdes:
2193                         e1000_check_for_link(hw);
2194                         link_check = hw->mac.serdes_has_link;
2195                         break;
2196
2197                 /* VF device is type_unknown */
2198                 case e1000_media_type_unknown:
2199                         eth_igbvf_link_update(hw);
2200                         link_check = !hw->mac.get_link_status;
2201                         break;
2202
2203                 default:
2204                         break;
2205                 }
2206                 if (link_check || wait_to_complete == 0)
2207                         break;
2208                 rte_delay_ms(IGB_LINK_UPDATE_CHECK_INTERVAL);
2209         }
2210         memset(&link, 0, sizeof(link));
2211         rte_igb_dev_atomic_read_link_status(dev, &link);
2212         old = link;
2213
2214         /* Now we check if a transition has happened */
2215         if (link_check) {
2216                 uint16_t duplex, speed;
2217                 hw->mac.ops.get_link_up_info(hw, &speed, &duplex);
2218                 link.link_duplex = (duplex == FULL_DUPLEX) ?
2219                                 ETH_LINK_FULL_DUPLEX :
2220                                 ETH_LINK_HALF_DUPLEX;
2221                 link.link_speed = speed;
2222                 link.link_status = ETH_LINK_UP;
2223                 link.link_autoneg = !(dev->data->dev_conf.link_speeds &
2224                                 ETH_LINK_SPEED_FIXED);
2225         } else if (!link_check) {
2226                 link.link_speed = 0;
2227                 link.link_duplex = ETH_LINK_HALF_DUPLEX;
2228                 link.link_status = ETH_LINK_DOWN;
2229                 link.link_autoneg = ETH_LINK_SPEED_FIXED;
2230         }
2231         rte_igb_dev_atomic_write_link_status(dev, &link);
2232
2233         /* not changed */
2234         if (old.link_status == link.link_status)
2235                 return -1;
2236
2237         /* changed */
2238         return 0;
2239 }
2240
2241 /*
2242  * igb_hw_control_acquire sets CTRL_EXT:DRV_LOAD bit.
2243  * For ASF and Pass Through versions of f/w this means
2244  * that the driver is loaded.
2245  */
2246 static void
2247 igb_hw_control_acquire(struct e1000_hw *hw)
2248 {
2249         uint32_t ctrl_ext;
2250
2251         /* Let firmware know the driver has taken over */
2252         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
2253         E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
2254 }
2255
2256 /*
2257  * igb_hw_control_release resets CTRL_EXT:DRV_LOAD bit.
2258  * For ASF and Pass Through versions of f/w this means that the
2259  * driver is no longer loaded.
2260  */
2261 static void
2262 igb_hw_control_release(struct e1000_hw *hw)
2263 {
2264         uint32_t ctrl_ext;
2265
2266         /* Let firmware taken over control of h/w */
2267         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
2268         E1000_WRITE_REG(hw, E1000_CTRL_EXT,
2269                         ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
2270 }
2271
2272 /*
2273  * Bit of a misnomer, what this really means is
2274  * to enable OS management of the system... aka
2275  * to disable special hardware management features.
2276  */
2277 static void
2278 igb_init_manageability(struct e1000_hw *hw)
2279 {
2280         if (e1000_enable_mng_pass_thru(hw)) {
2281                 uint32_t manc2h = E1000_READ_REG(hw, E1000_MANC2H);
2282                 uint32_t manc = E1000_READ_REG(hw, E1000_MANC);
2283
2284                 /* disable hardware interception of ARP */
2285                 manc &= ~(E1000_MANC_ARP_EN);
2286
2287                 /* enable receiving management packets to the host */
2288                 manc |= E1000_MANC_EN_MNG2HOST;
2289                 manc2h |= 1 << 5;  /* Mng Port 623 */
2290                 manc2h |= 1 << 6;  /* Mng Port 664 */
2291                 E1000_WRITE_REG(hw, E1000_MANC2H, manc2h);
2292                 E1000_WRITE_REG(hw, E1000_MANC, manc);
2293         }
2294 }
2295
2296 static void
2297 igb_release_manageability(struct e1000_hw *hw)
2298 {
2299         if (e1000_enable_mng_pass_thru(hw)) {
2300                 uint32_t manc = E1000_READ_REG(hw, E1000_MANC);
2301
2302                 manc |= E1000_MANC_ARP_EN;
2303                 manc &= ~E1000_MANC_EN_MNG2HOST;
2304
2305                 E1000_WRITE_REG(hw, E1000_MANC, manc);
2306         }
2307 }
2308
2309 static void
2310 eth_igb_promiscuous_enable(struct rte_eth_dev *dev)
2311 {
2312         struct e1000_hw *hw =
2313                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2314         uint32_t rctl;
2315
2316         rctl = E1000_READ_REG(hw, E1000_RCTL);
2317         rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
2318         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2319 }
2320
2321 static void
2322 eth_igb_promiscuous_disable(struct rte_eth_dev *dev)
2323 {
2324         struct e1000_hw *hw =
2325                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2326         uint32_t rctl;
2327
2328         rctl = E1000_READ_REG(hw, E1000_RCTL);
2329         rctl &= (~E1000_RCTL_UPE);
2330         if (dev->data->all_multicast == 1)
2331                 rctl |= E1000_RCTL_MPE;
2332         else
2333                 rctl &= (~E1000_RCTL_MPE);
2334         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2335 }
2336
2337 static void
2338 eth_igb_allmulticast_enable(struct rte_eth_dev *dev)
2339 {
2340         struct e1000_hw *hw =
2341                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2342         uint32_t rctl;
2343
2344         rctl = E1000_READ_REG(hw, E1000_RCTL);
2345         rctl |= E1000_RCTL_MPE;
2346         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2347 }
2348
2349 static void
2350 eth_igb_allmulticast_disable(struct rte_eth_dev *dev)
2351 {
2352         struct e1000_hw *hw =
2353                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2354         uint32_t rctl;
2355
2356         if (dev->data->promiscuous == 1)
2357                 return; /* must remain in all_multicast mode */
2358         rctl = E1000_READ_REG(hw, E1000_RCTL);
2359         rctl &= (~E1000_RCTL_MPE);
2360         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2361 }
2362
2363 static int
2364 eth_igb_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
2365 {
2366         struct e1000_hw *hw =
2367                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2368         struct e1000_vfta * shadow_vfta =
2369                 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
2370         uint32_t vfta;
2371         uint32_t vid_idx;
2372         uint32_t vid_bit;
2373
2374         vid_idx = (uint32_t) ((vlan_id >> E1000_VFTA_ENTRY_SHIFT) &
2375                               E1000_VFTA_ENTRY_MASK);
2376         vid_bit = (uint32_t) (1 << (vlan_id & E1000_VFTA_ENTRY_BIT_SHIFT_MASK));
2377         vfta = E1000_READ_REG_ARRAY(hw, E1000_VFTA, vid_idx);
2378         if (on)
2379                 vfta |= vid_bit;
2380         else
2381                 vfta &= ~vid_bit;
2382         E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, vid_idx, vfta);
2383
2384         /* update local VFTA copy */
2385         shadow_vfta->vfta[vid_idx] = vfta;
2386
2387         return 0;
2388 }
2389
2390 static int
2391 eth_igb_vlan_tpid_set(struct rte_eth_dev *dev,
2392                       enum rte_vlan_type vlan_type,
2393                       uint16_t tpid)
2394 {
2395         struct e1000_hw *hw =
2396                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2397         uint32_t reg, qinq;
2398
2399         qinq = E1000_READ_REG(hw, E1000_CTRL_EXT);
2400         qinq &= E1000_CTRL_EXT_EXT_VLAN;
2401
2402         /* only outer TPID of double VLAN can be configured*/
2403         if (qinq && vlan_type == ETH_VLAN_TYPE_OUTER) {
2404                 reg = E1000_READ_REG(hw, E1000_VET);
2405                 reg = (reg & (~E1000_VET_VET_EXT)) |
2406                         ((uint32_t)tpid << E1000_VET_VET_EXT_SHIFT);
2407                 E1000_WRITE_REG(hw, E1000_VET, reg);
2408
2409                 return 0;
2410         }
2411
2412         /* all other TPID values are read-only*/
2413         PMD_DRV_LOG(ERR, "Not supported");
2414
2415         return -ENOTSUP;
2416 }
2417
2418 static void
2419 igb_vlan_hw_filter_disable(struct rte_eth_dev *dev)
2420 {
2421         struct e1000_hw *hw =
2422                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2423         uint32_t reg;
2424
2425         /* Filter Table Disable */
2426         reg = E1000_READ_REG(hw, E1000_RCTL);
2427         reg &= ~E1000_RCTL_CFIEN;
2428         reg &= ~E1000_RCTL_VFE;
2429         E1000_WRITE_REG(hw, E1000_RCTL, reg);
2430 }
2431
2432 static void
2433 igb_vlan_hw_filter_enable(struct rte_eth_dev *dev)
2434 {
2435         struct e1000_hw *hw =
2436                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2437         struct e1000_vfta * shadow_vfta =
2438                 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
2439         uint32_t reg;
2440         int i;
2441
2442         /* Filter Table Enable, CFI not used for packet acceptance */
2443         reg = E1000_READ_REG(hw, E1000_RCTL);
2444         reg &= ~E1000_RCTL_CFIEN;
2445         reg |= E1000_RCTL_VFE;
2446         E1000_WRITE_REG(hw, E1000_RCTL, reg);
2447
2448         /* restore VFTA table */
2449         for (i = 0; i < IGB_VFTA_SIZE; i++)
2450                 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, i, shadow_vfta->vfta[i]);
2451 }
2452
2453 static void
2454 igb_vlan_hw_strip_disable(struct rte_eth_dev *dev)
2455 {
2456         struct e1000_hw *hw =
2457                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2458         uint32_t reg;
2459
2460         /* VLAN Mode Disable */
2461         reg = E1000_READ_REG(hw, E1000_CTRL);
2462         reg &= ~E1000_CTRL_VME;
2463         E1000_WRITE_REG(hw, E1000_CTRL, reg);
2464 }
2465
2466 static void
2467 igb_vlan_hw_strip_enable(struct rte_eth_dev *dev)
2468 {
2469         struct e1000_hw *hw =
2470                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2471         uint32_t reg;
2472
2473         /* VLAN Mode Enable */
2474         reg = E1000_READ_REG(hw, E1000_CTRL);
2475         reg |= E1000_CTRL_VME;
2476         E1000_WRITE_REG(hw, E1000_CTRL, reg);
2477 }
2478
2479 static void
2480 igb_vlan_hw_extend_disable(struct rte_eth_dev *dev)
2481 {
2482         struct e1000_hw *hw =
2483                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2484         uint32_t reg;
2485
2486         /* CTRL_EXT: Extended VLAN */
2487         reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
2488         reg &= ~E1000_CTRL_EXT_EXTEND_VLAN;
2489         E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg);
2490
2491         /* Update maximum packet length */
2492         if (dev->data->dev_conf.rxmode.jumbo_frame == 1)
2493                 E1000_WRITE_REG(hw, E1000_RLPML,
2494                         dev->data->dev_conf.rxmode.max_rx_pkt_len +
2495                                                 VLAN_TAG_SIZE);
2496 }
2497
2498 static void
2499 igb_vlan_hw_extend_enable(struct rte_eth_dev *dev)
2500 {
2501         struct e1000_hw *hw =
2502                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2503         uint32_t reg;
2504
2505         /* CTRL_EXT: Extended VLAN */
2506         reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
2507         reg |= E1000_CTRL_EXT_EXTEND_VLAN;
2508         E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg);
2509
2510         /* Update maximum packet length */
2511         if (dev->data->dev_conf.rxmode.jumbo_frame == 1)
2512                 E1000_WRITE_REG(hw, E1000_RLPML,
2513                         dev->data->dev_conf.rxmode.max_rx_pkt_len +
2514                                                 2 * VLAN_TAG_SIZE);
2515 }
2516
2517 static void
2518 eth_igb_vlan_offload_set(struct rte_eth_dev *dev, int mask)
2519 {
2520         if(mask & ETH_VLAN_STRIP_MASK){
2521                 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
2522                         igb_vlan_hw_strip_enable(dev);
2523                 else
2524                         igb_vlan_hw_strip_disable(dev);
2525         }
2526
2527         if(mask & ETH_VLAN_FILTER_MASK){
2528                 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
2529                         igb_vlan_hw_filter_enable(dev);
2530                 else
2531                         igb_vlan_hw_filter_disable(dev);
2532         }
2533
2534         if(mask & ETH_VLAN_EXTEND_MASK){
2535                 if (dev->data->dev_conf.rxmode.hw_vlan_extend)
2536                         igb_vlan_hw_extend_enable(dev);
2537                 else
2538                         igb_vlan_hw_extend_disable(dev);
2539         }
2540 }
2541
2542
2543 /**
2544  * It enables the interrupt mask and then enable the interrupt.
2545  *
2546  * @param dev
2547  *  Pointer to struct rte_eth_dev.
2548  * @param on
2549  *  Enable or Disable
2550  *
2551  * @return
2552  *  - On success, zero.
2553  *  - On failure, a negative value.
2554  */
2555 static int
2556 eth_igb_lsc_interrupt_setup(struct rte_eth_dev *dev, uint8_t on)
2557 {
2558         struct e1000_interrupt *intr =
2559                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2560
2561         if (on)
2562                 intr->mask |= E1000_ICR_LSC;
2563         else
2564                 intr->mask &= ~E1000_ICR_LSC;
2565
2566         return 0;
2567 }
2568
2569 /* It clears the interrupt causes and enables the interrupt.
2570  * It will be called once only during nic initialized.
2571  *
2572  * @param dev
2573  *  Pointer to struct rte_eth_dev.
2574  *
2575  * @return
2576  *  - On success, zero.
2577  *  - On failure, a negative value.
2578  */
2579 static int eth_igb_rxq_interrupt_setup(struct rte_eth_dev *dev)
2580 {
2581         uint32_t mask, regval;
2582         struct e1000_hw *hw =
2583                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2584         struct rte_eth_dev_info dev_info;
2585
2586         memset(&dev_info, 0, sizeof(dev_info));
2587         eth_igb_infos_get(dev, &dev_info);
2588
2589         mask = 0xFFFFFFFF >> (32 - dev_info.max_rx_queues);
2590         regval = E1000_READ_REG(hw, E1000_EIMS);
2591         E1000_WRITE_REG(hw, E1000_EIMS, regval | mask);
2592
2593         return 0;
2594 }
2595
2596 /*
2597  * It reads ICR and gets interrupt causes, check it and set a bit flag
2598  * to update link status.
2599  *
2600  * @param dev
2601  *  Pointer to struct rte_eth_dev.
2602  *
2603  * @return
2604  *  - On success, zero.
2605  *  - On failure, a negative value.
2606  */
2607 static int
2608 eth_igb_interrupt_get_status(struct rte_eth_dev *dev)
2609 {
2610         uint32_t icr;
2611         struct e1000_hw *hw =
2612                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2613         struct e1000_interrupt *intr =
2614                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2615
2616         igb_intr_disable(hw);
2617
2618         /* read-on-clear nic registers here */
2619         icr = E1000_READ_REG(hw, E1000_ICR);
2620
2621         intr->flags = 0;
2622         if (icr & E1000_ICR_LSC) {
2623                 intr->flags |= E1000_FLAG_NEED_LINK_UPDATE;
2624         }
2625
2626         if (icr & E1000_ICR_VMMB)
2627                 intr->flags |= E1000_FLAG_MAILBOX;
2628
2629         return 0;
2630 }
2631
2632 /*
2633  * It executes link_update after knowing an interrupt is prsent.
2634  *
2635  * @param dev
2636  *  Pointer to struct rte_eth_dev.
2637  *
2638  * @return
2639  *  - On success, zero.
2640  *  - On failure, a negative value.
2641  */
2642 static int
2643 eth_igb_interrupt_action(struct rte_eth_dev *dev)
2644 {
2645         struct e1000_hw *hw =
2646                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2647         struct e1000_interrupt *intr =
2648                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2649         uint32_t tctl, rctl;
2650         struct rte_eth_link link;
2651         int ret;
2652
2653         if (intr->flags & E1000_FLAG_MAILBOX) {
2654                 igb_pf_mbx_process(dev);
2655                 intr->flags &= ~E1000_FLAG_MAILBOX;
2656         }
2657
2658         igb_intr_enable(dev);
2659         rte_intr_enable(&(dev->pci_dev->intr_handle));
2660
2661         if (intr->flags & E1000_FLAG_NEED_LINK_UPDATE) {
2662                 intr->flags &= ~E1000_FLAG_NEED_LINK_UPDATE;
2663
2664                 /* set get_link_status to check register later */
2665                 hw->mac.get_link_status = 1;
2666                 ret = eth_igb_link_update(dev, 0);
2667
2668                 /* check if link has changed */
2669                 if (ret < 0)
2670                         return 0;
2671
2672                 memset(&link, 0, sizeof(link));
2673                 rte_igb_dev_atomic_read_link_status(dev, &link);
2674                 if (link.link_status) {
2675                         PMD_INIT_LOG(INFO,
2676                                      " Port %d: Link Up - speed %u Mbps - %s",
2677                                      dev->data->port_id,
2678                                      (unsigned)link.link_speed,
2679                                      link.link_duplex == ETH_LINK_FULL_DUPLEX ?
2680                                      "full-duplex" : "half-duplex");
2681                 } else {
2682                         PMD_INIT_LOG(INFO, " Port %d: Link Down",
2683                                      dev->data->port_id);
2684                 }
2685
2686                 PMD_INIT_LOG(DEBUG, "PCI Address: %04d:%02d:%02d:%d",
2687                              dev->pci_dev->addr.domain,
2688                              dev->pci_dev->addr.bus,
2689                              dev->pci_dev->addr.devid,
2690                              dev->pci_dev->addr.function);
2691                 tctl = E1000_READ_REG(hw, E1000_TCTL);
2692                 rctl = E1000_READ_REG(hw, E1000_RCTL);
2693                 if (link.link_status) {
2694                         /* enable Tx/Rx */
2695                         tctl |= E1000_TCTL_EN;
2696                         rctl |= E1000_RCTL_EN;
2697                 } else {
2698                         /* disable Tx/Rx */
2699                         tctl &= ~E1000_TCTL_EN;
2700                         rctl &= ~E1000_RCTL_EN;
2701                 }
2702                 E1000_WRITE_REG(hw, E1000_TCTL, tctl);
2703                 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2704                 E1000_WRITE_FLUSH(hw);
2705                 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC, NULL);
2706         }
2707
2708         return 0;
2709 }
2710
2711 /**
2712  * Interrupt handler which shall be registered at first.
2713  *
2714  * @param handle
2715  *  Pointer to interrupt handle.
2716  * @param param
2717  *  The address of parameter (struct rte_eth_dev *) regsitered before.
2718  *
2719  * @return
2720  *  void
2721  */
2722 static void
2723 eth_igb_interrupt_handler(__rte_unused struct rte_intr_handle *handle,
2724                                                         void *param)
2725 {
2726         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
2727
2728         eth_igb_interrupt_get_status(dev);
2729         eth_igb_interrupt_action(dev);
2730 }
2731
2732 static int
2733 eth_igbvf_interrupt_get_status(struct rte_eth_dev *dev)
2734 {
2735         uint32_t eicr;
2736         struct e1000_hw *hw =
2737                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2738         struct e1000_interrupt *intr =
2739                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2740
2741         igbvf_intr_disable(hw);
2742
2743         /* read-on-clear nic registers here */
2744         eicr = E1000_READ_REG(hw, E1000_EICR);
2745         intr->flags = 0;
2746
2747         if (eicr == E1000_VTIVAR_MISC_MAILBOX)
2748                 intr->flags |= E1000_FLAG_MAILBOX;
2749
2750         return 0;
2751 }
2752
2753 void igbvf_mbx_process(struct rte_eth_dev *dev)
2754 {
2755         struct e1000_hw *hw =
2756                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2757         struct e1000_mbx_info *mbx = &hw->mbx;
2758         u32 in_msg = 0;
2759
2760         if (mbx->ops.read(hw, &in_msg, 1, 0))
2761                 return;
2762
2763         /* PF reset VF event */
2764         if (in_msg == E1000_PF_CONTROL_MSG)
2765                 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_RESET, NULL);
2766 }
2767
2768 static int
2769 eth_igbvf_interrupt_action(struct rte_eth_dev *dev)
2770 {
2771         struct e1000_interrupt *intr =
2772                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2773
2774         if (intr->flags & E1000_FLAG_MAILBOX) {
2775                 igbvf_mbx_process(dev);
2776                 intr->flags &= ~E1000_FLAG_MAILBOX;
2777         }
2778
2779         igbvf_intr_enable(dev);
2780         rte_intr_enable(&dev->pci_dev->intr_handle);
2781
2782         return 0;
2783 }
2784
2785 static void
2786 eth_igbvf_interrupt_handler(__rte_unused struct rte_intr_handle *handle,
2787                             void *param)
2788 {
2789         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
2790
2791         eth_igbvf_interrupt_get_status(dev);
2792         eth_igbvf_interrupt_action(dev);
2793 }
2794
2795 static int
2796 eth_igb_led_on(struct rte_eth_dev *dev)
2797 {
2798         struct e1000_hw *hw;
2799
2800         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2801         return e1000_led_on(hw) == E1000_SUCCESS ? 0 : -ENOTSUP;
2802 }
2803
2804 static int
2805 eth_igb_led_off(struct rte_eth_dev *dev)
2806 {
2807         struct e1000_hw *hw;
2808
2809         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2810         return e1000_led_off(hw) == E1000_SUCCESS ? 0 : -ENOTSUP;
2811 }
2812
2813 static int
2814 eth_igb_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
2815 {
2816         struct e1000_hw *hw;
2817         uint32_t ctrl;
2818         int tx_pause;
2819         int rx_pause;
2820
2821         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2822         fc_conf->pause_time = hw->fc.pause_time;
2823         fc_conf->high_water = hw->fc.high_water;
2824         fc_conf->low_water = hw->fc.low_water;
2825         fc_conf->send_xon = hw->fc.send_xon;
2826         fc_conf->autoneg = hw->mac.autoneg;
2827
2828         /*
2829          * Return rx_pause and tx_pause status according to actual setting of
2830          * the TFCE and RFCE bits in the CTRL register.
2831          */
2832         ctrl = E1000_READ_REG(hw, E1000_CTRL);
2833         if (ctrl & E1000_CTRL_TFCE)
2834                 tx_pause = 1;
2835         else
2836                 tx_pause = 0;
2837
2838         if (ctrl & E1000_CTRL_RFCE)
2839                 rx_pause = 1;
2840         else
2841                 rx_pause = 0;
2842
2843         if (rx_pause && tx_pause)
2844                 fc_conf->mode = RTE_FC_FULL;
2845         else if (rx_pause)
2846                 fc_conf->mode = RTE_FC_RX_PAUSE;
2847         else if (tx_pause)
2848                 fc_conf->mode = RTE_FC_TX_PAUSE;
2849         else
2850                 fc_conf->mode = RTE_FC_NONE;
2851
2852         return 0;
2853 }
2854
2855 static int
2856 eth_igb_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
2857 {
2858         struct e1000_hw *hw;
2859         int err;
2860         enum e1000_fc_mode rte_fcmode_2_e1000_fcmode[] = {
2861                 e1000_fc_none,
2862                 e1000_fc_rx_pause,
2863                 e1000_fc_tx_pause,
2864                 e1000_fc_full
2865         };
2866         uint32_t rx_buf_size;
2867         uint32_t max_high_water;
2868         uint32_t rctl;
2869
2870         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2871         if (fc_conf->autoneg != hw->mac.autoneg)
2872                 return -ENOTSUP;
2873         rx_buf_size = igb_get_rx_buffer_size(hw);
2874         PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
2875
2876         /* At least reserve one Ethernet frame for watermark */
2877         max_high_water = rx_buf_size - ETHER_MAX_LEN;
2878         if ((fc_conf->high_water > max_high_water) ||
2879             (fc_conf->high_water < fc_conf->low_water)) {
2880                 PMD_INIT_LOG(ERR, "e1000 incorrect high/low water value");
2881                 PMD_INIT_LOG(ERR, "high water must <=  0x%x", max_high_water);
2882                 return -EINVAL;
2883         }
2884
2885         hw->fc.requested_mode = rte_fcmode_2_e1000_fcmode[fc_conf->mode];
2886         hw->fc.pause_time     = fc_conf->pause_time;
2887         hw->fc.high_water     = fc_conf->high_water;
2888         hw->fc.low_water      = fc_conf->low_water;
2889         hw->fc.send_xon       = fc_conf->send_xon;
2890
2891         err = e1000_setup_link_generic(hw);
2892         if (err == E1000_SUCCESS) {
2893
2894                 /* check if we want to forward MAC frames - driver doesn't have native
2895                  * capability to do that, so we'll write the registers ourselves */
2896
2897                 rctl = E1000_READ_REG(hw, E1000_RCTL);
2898
2899                 /* set or clear MFLCN.PMCF bit depending on configuration */
2900                 if (fc_conf->mac_ctrl_frame_fwd != 0)
2901                         rctl |= E1000_RCTL_PMCF;
2902                 else
2903                         rctl &= ~E1000_RCTL_PMCF;
2904
2905                 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2906                 E1000_WRITE_FLUSH(hw);
2907
2908                 return 0;
2909         }
2910
2911         PMD_INIT_LOG(ERR, "e1000_setup_link_generic = 0x%x", err);
2912         return -EIO;
2913 }
2914
2915 #define E1000_RAH_POOLSEL_SHIFT      (18)
2916 static void
2917 eth_igb_rar_set(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
2918                 uint32_t index, __rte_unused uint32_t pool)
2919 {
2920         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2921         uint32_t rah;
2922
2923         e1000_rar_set(hw, mac_addr->addr_bytes, index);
2924         rah = E1000_READ_REG(hw, E1000_RAH(index));
2925         rah |= (0x1 << (E1000_RAH_POOLSEL_SHIFT + pool));
2926         E1000_WRITE_REG(hw, E1000_RAH(index), rah);
2927 }
2928
2929 static void
2930 eth_igb_rar_clear(struct rte_eth_dev *dev, uint32_t index)
2931 {
2932         uint8_t addr[ETHER_ADDR_LEN];
2933         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2934
2935         memset(addr, 0, sizeof(addr));
2936
2937         e1000_rar_set(hw, addr, index);
2938 }
2939
2940 static void
2941 eth_igb_default_mac_addr_set(struct rte_eth_dev *dev,
2942                                 struct ether_addr *addr)
2943 {
2944         eth_igb_rar_clear(dev, 0);
2945
2946         eth_igb_rar_set(dev, (void *)addr, 0, 0);
2947 }
2948 /*
2949  * Virtual Function operations
2950  */
2951 static void
2952 igbvf_intr_disable(struct e1000_hw *hw)
2953 {
2954         PMD_INIT_FUNC_TRACE();
2955
2956         /* Clear interrupt mask to stop from interrupts being generated */
2957         E1000_WRITE_REG(hw, E1000_EIMC, 0xFFFF);
2958
2959         E1000_WRITE_FLUSH(hw);
2960 }
2961
2962 static void
2963 igbvf_stop_adapter(struct rte_eth_dev *dev)
2964 {
2965         u32 reg_val;
2966         u16 i;
2967         struct rte_eth_dev_info dev_info;
2968         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2969
2970         memset(&dev_info, 0, sizeof(dev_info));
2971         eth_igbvf_infos_get(dev, &dev_info);
2972
2973         /* Clear interrupt mask to stop from interrupts being generated */
2974         igbvf_intr_disable(hw);
2975
2976         /* Clear any pending interrupts, flush previous writes */
2977         E1000_READ_REG(hw, E1000_EICR);
2978
2979         /* Disable the transmit unit.  Each queue must be disabled. */
2980         for (i = 0; i < dev_info.max_tx_queues; i++)
2981                 E1000_WRITE_REG(hw, E1000_TXDCTL(i), E1000_TXDCTL_SWFLSH);
2982
2983         /* Disable the receive unit by stopping each queue */
2984         for (i = 0; i < dev_info.max_rx_queues; i++) {
2985                 reg_val = E1000_READ_REG(hw, E1000_RXDCTL(i));
2986                 reg_val &= ~E1000_RXDCTL_QUEUE_ENABLE;
2987                 E1000_WRITE_REG(hw, E1000_RXDCTL(i), reg_val);
2988                 while (E1000_READ_REG(hw, E1000_RXDCTL(i)) & E1000_RXDCTL_QUEUE_ENABLE)
2989                         ;
2990         }
2991
2992         /* flush all queues disables */
2993         E1000_WRITE_FLUSH(hw);
2994         msec_delay(2);
2995 }
2996
2997 static int eth_igbvf_link_update(struct e1000_hw *hw)
2998 {
2999         struct e1000_mbx_info *mbx = &hw->mbx;
3000         struct e1000_mac_info *mac = &hw->mac;
3001         int ret_val = E1000_SUCCESS;
3002
3003         PMD_INIT_LOG(DEBUG, "e1000_check_for_link_vf");
3004
3005         /*
3006          * We only want to run this if there has been a rst asserted.
3007          * in this case that could mean a link change, device reset,
3008          * or a virtual function reset
3009          */
3010
3011         /* If we were hit with a reset or timeout drop the link */
3012         if (!e1000_check_for_rst(hw, 0) || !mbx->timeout)
3013                 mac->get_link_status = TRUE;
3014
3015         if (!mac->get_link_status)
3016                 goto out;
3017
3018         /* if link status is down no point in checking to see if pf is up */
3019         if (!(E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU))
3020                 goto out;
3021
3022         /* if we passed all the tests above then the link is up and we no
3023          * longer need to check for link */
3024         mac->get_link_status = FALSE;
3025
3026 out:
3027         return ret_val;
3028 }
3029
3030
3031 static int
3032 igbvf_dev_configure(struct rte_eth_dev *dev)
3033 {
3034         struct rte_eth_conf* conf = &dev->data->dev_conf;
3035
3036         PMD_INIT_LOG(DEBUG, "Configured Virtual Function port id: %d",
3037                      dev->data->port_id);
3038
3039         /*
3040          * VF has no ability to enable/disable HW CRC
3041          * Keep the persistent behavior the same as Host PF
3042          */
3043 #ifndef RTE_LIBRTE_E1000_PF_DISABLE_STRIP_CRC
3044         if (!conf->rxmode.hw_strip_crc) {
3045                 PMD_INIT_LOG(NOTICE, "VF can't disable HW CRC Strip");
3046                 conf->rxmode.hw_strip_crc = 1;
3047         }
3048 #else
3049         if (conf->rxmode.hw_strip_crc) {
3050                 PMD_INIT_LOG(NOTICE, "VF can't enable HW CRC Strip");
3051                 conf->rxmode.hw_strip_crc = 0;
3052         }
3053 #endif
3054
3055         return 0;
3056 }
3057
3058 static int
3059 igbvf_dev_start(struct rte_eth_dev *dev)
3060 {
3061         struct e1000_hw *hw =
3062                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3063         struct e1000_adapter *adapter =
3064                 E1000_DEV_PRIVATE(dev->data->dev_private);
3065         int ret;
3066         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
3067         uint32_t intr_vector = 0;
3068
3069         PMD_INIT_FUNC_TRACE();
3070
3071         hw->mac.ops.reset_hw(hw);
3072         adapter->stopped = 0;
3073
3074         /* Set all vfta */
3075         igbvf_set_vfta_all(dev,1);
3076
3077         eth_igbvf_tx_init(dev);
3078
3079         /* This can fail when allocating mbufs for descriptor rings */
3080         ret = eth_igbvf_rx_init(dev);
3081         if (ret) {
3082                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
3083                 igb_dev_clear_queues(dev);
3084                 return ret;
3085         }
3086
3087         /* check and configure queue intr-vector mapping */
3088         if (dev->data->dev_conf.intr_conf.rxq != 0) {
3089                 intr_vector = dev->data->nb_rx_queues;
3090                 ret = rte_intr_efd_enable(intr_handle, intr_vector);
3091                 if (ret)
3092                         return ret;
3093         }
3094
3095         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
3096                 intr_handle->intr_vec =
3097                         rte_zmalloc("intr_vec",
3098                                     dev->data->nb_rx_queues * sizeof(int), 0);
3099                 if (!intr_handle->intr_vec) {
3100                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
3101                                      " intr_vec\n", dev->data->nb_rx_queues);
3102                         return -ENOMEM;
3103                 }
3104         }
3105
3106         eth_igbvf_configure_msix_intr(dev);
3107
3108         /* enable uio/vfio intr/eventfd mapping */
3109         rte_intr_enable(intr_handle);
3110
3111         /* resume enabled intr since hw reset */
3112         igbvf_intr_enable(dev);
3113
3114         return 0;
3115 }
3116
3117 static void
3118 igbvf_dev_stop(struct rte_eth_dev *dev)
3119 {
3120         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
3121
3122         PMD_INIT_FUNC_TRACE();
3123
3124         igbvf_stop_adapter(dev);
3125
3126         /*
3127           * Clear what we set, but we still keep shadow_vfta to
3128           * restore after device starts
3129           */
3130         igbvf_set_vfta_all(dev,0);
3131
3132         igb_dev_clear_queues(dev);
3133
3134         /* disable intr eventfd mapping */
3135         rte_intr_disable(intr_handle);
3136
3137         /* Clean datapath event and queue/vec mapping */
3138         rte_intr_efd_disable(intr_handle);
3139         if (intr_handle->intr_vec) {
3140                 rte_free(intr_handle->intr_vec);
3141                 intr_handle->intr_vec = NULL;
3142         }
3143 }
3144
3145 static void
3146 igbvf_dev_close(struct rte_eth_dev *dev)
3147 {
3148         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3149         struct e1000_adapter *adapter =
3150                 E1000_DEV_PRIVATE(dev->data->dev_private);
3151         struct ether_addr addr;
3152
3153         PMD_INIT_FUNC_TRACE();
3154
3155         e1000_reset_hw(hw);
3156
3157         igbvf_dev_stop(dev);
3158         adapter->stopped = 1;
3159         igb_dev_free_queues(dev);
3160
3161         /**
3162          * reprogram the RAR with a zero mac address,
3163          * to ensure that the VF traffic goes to the PF
3164          * after stop, close and detach of the VF.
3165          **/
3166
3167         memset(&addr, 0, sizeof(addr));
3168         igbvf_default_mac_addr_set(dev, &addr);
3169 }
3170
3171 static void
3172 igbvf_promiscuous_enable(struct rte_eth_dev *dev)
3173 {
3174         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3175
3176         /* Set both unicast and multicast promisc */
3177         e1000_promisc_set_vf(hw, e1000_promisc_enabled);
3178 }
3179
3180 static void
3181 igbvf_promiscuous_disable(struct rte_eth_dev *dev)
3182 {
3183         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3184
3185         /* If in allmulticast mode leave multicast promisc */
3186         if (dev->data->all_multicast == 1)
3187                 e1000_promisc_set_vf(hw, e1000_promisc_multicast);
3188         else
3189                 e1000_promisc_set_vf(hw, e1000_promisc_disabled);
3190 }
3191
3192 static void
3193 igbvf_allmulticast_enable(struct rte_eth_dev *dev)
3194 {
3195         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3196
3197         /* In promiscuous mode multicast promisc already set */
3198         if (dev->data->promiscuous == 0)
3199                 e1000_promisc_set_vf(hw, e1000_promisc_multicast);
3200 }
3201
3202 static void
3203 igbvf_allmulticast_disable(struct rte_eth_dev *dev)
3204 {
3205         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3206
3207         /* In promiscuous mode leave multicast promisc enabled */
3208         if (dev->data->promiscuous == 0)
3209                 e1000_promisc_set_vf(hw, e1000_promisc_disabled);
3210 }
3211
3212 static int igbvf_set_vfta(struct e1000_hw *hw, uint16_t vid, bool on)
3213 {
3214         struct e1000_mbx_info *mbx = &hw->mbx;
3215         uint32_t msgbuf[2];
3216         s32 err;
3217
3218         /* After set vlan, vlan strip will also be enabled in igb driver*/
3219         msgbuf[0] = E1000_VF_SET_VLAN;
3220         msgbuf[1] = vid;
3221         /* Setting the 8 bit field MSG INFO to TRUE indicates "add" */
3222         if (on)
3223                 msgbuf[0] |= E1000_VF_SET_VLAN_ADD;
3224
3225         err = mbx->ops.write_posted(hw, msgbuf, 2, 0);
3226         if (err)
3227                 goto mbx_err;
3228
3229         err = mbx->ops.read_posted(hw, msgbuf, 2, 0);
3230         if (err)
3231                 goto mbx_err;
3232
3233         msgbuf[0] &= ~E1000_VT_MSGTYPE_CTS;
3234         if (msgbuf[0] == (E1000_VF_SET_VLAN | E1000_VT_MSGTYPE_NACK))
3235                 err = -EINVAL;
3236
3237 mbx_err:
3238         return err;
3239 }
3240
3241 static void igbvf_set_vfta_all(struct rte_eth_dev *dev, bool on)
3242 {
3243         struct e1000_hw *hw =
3244                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3245         struct e1000_vfta * shadow_vfta =
3246                 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
3247         int i = 0, j = 0, vfta = 0, mask = 1;
3248
3249         for (i = 0; i < IGB_VFTA_SIZE; i++){
3250                 vfta = shadow_vfta->vfta[i];
3251                 if(vfta){
3252                         mask = 1;
3253                         for (j = 0; j < 32; j++){
3254                                 if(vfta & mask)
3255                                         igbvf_set_vfta(hw,
3256                                                 (uint16_t)((i<<5)+j), on);
3257                                 mask<<=1;
3258                         }
3259                 }
3260         }
3261
3262 }
3263
3264 static int
3265 igbvf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
3266 {
3267         struct e1000_hw *hw =
3268                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3269         struct e1000_vfta * shadow_vfta =
3270                 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
3271         uint32_t vid_idx = 0;
3272         uint32_t vid_bit = 0;
3273         int ret = 0;
3274
3275         PMD_INIT_FUNC_TRACE();
3276
3277         /*vind is not used in VF driver, set to 0, check ixgbe_set_vfta_vf*/
3278         ret = igbvf_set_vfta(hw, vlan_id, !!on);
3279         if(ret){
3280                 PMD_INIT_LOG(ERR, "Unable to set VF vlan");
3281                 return ret;
3282         }
3283         vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
3284         vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
3285
3286         /*Save what we set and retore it after device reset*/
3287         if (on)
3288                 shadow_vfta->vfta[vid_idx] |= vid_bit;
3289         else
3290                 shadow_vfta->vfta[vid_idx] &= ~vid_bit;
3291
3292         return 0;
3293 }
3294
3295 static void
3296 igbvf_default_mac_addr_set(struct rte_eth_dev *dev, struct ether_addr *addr)
3297 {
3298         struct e1000_hw *hw =
3299                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3300
3301         /* index is not used by rar_set() */
3302         hw->mac.ops.rar_set(hw, (void *)addr, 0);
3303 }
3304
3305
3306 static int
3307 eth_igb_rss_reta_update(struct rte_eth_dev *dev,
3308                         struct rte_eth_rss_reta_entry64 *reta_conf,
3309                         uint16_t reta_size)
3310 {
3311         uint8_t i, j, mask;
3312         uint32_t reta, r;
3313         uint16_t idx, shift;
3314         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3315
3316         if (reta_size != ETH_RSS_RETA_SIZE_128) {
3317                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
3318                         "(%d) doesn't match the number hardware can supported "
3319                         "(%d)\n", reta_size, ETH_RSS_RETA_SIZE_128);
3320                 return -EINVAL;
3321         }
3322
3323         for (i = 0; i < reta_size; i += IGB_4_BIT_WIDTH) {
3324                 idx = i / RTE_RETA_GROUP_SIZE;
3325                 shift = i % RTE_RETA_GROUP_SIZE;
3326                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
3327                                                 IGB_4_BIT_MASK);
3328                 if (!mask)
3329                         continue;
3330                 if (mask == IGB_4_BIT_MASK)
3331                         r = 0;
3332                 else
3333                         r = E1000_READ_REG(hw, E1000_RETA(i >> 2));
3334                 for (j = 0, reta = 0; j < IGB_4_BIT_WIDTH; j++) {
3335                         if (mask & (0x1 << j))
3336                                 reta |= reta_conf[idx].reta[shift + j] <<
3337                                                         (CHAR_BIT * j);
3338                         else
3339                                 reta |= r & (IGB_8_BIT_MASK << (CHAR_BIT * j));
3340                 }
3341                 E1000_WRITE_REG(hw, E1000_RETA(i >> 2), reta);
3342         }
3343
3344         return 0;
3345 }
3346
3347 static int
3348 eth_igb_rss_reta_query(struct rte_eth_dev *dev,
3349                        struct rte_eth_rss_reta_entry64 *reta_conf,
3350                        uint16_t reta_size)
3351 {
3352         uint8_t i, j, mask;
3353         uint32_t reta;
3354         uint16_t idx, shift;
3355         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3356
3357         if (reta_size != ETH_RSS_RETA_SIZE_128) {
3358                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
3359                         "(%d) doesn't match the number hardware can supported "
3360                         "(%d)\n", reta_size, ETH_RSS_RETA_SIZE_128);
3361                 return -EINVAL;
3362         }
3363
3364         for (i = 0; i < reta_size; i += IGB_4_BIT_WIDTH) {
3365                 idx = i / RTE_RETA_GROUP_SIZE;
3366                 shift = i % RTE_RETA_GROUP_SIZE;
3367                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
3368                                                 IGB_4_BIT_MASK);
3369                 if (!mask)
3370                         continue;
3371                 reta = E1000_READ_REG(hw, E1000_RETA(i >> 2));
3372                 for (j = 0; j < IGB_4_BIT_WIDTH; j++) {
3373                         if (mask & (0x1 << j))
3374                                 reta_conf[idx].reta[shift + j] =
3375                                         ((reta >> (CHAR_BIT * j)) &
3376                                                 IGB_8_BIT_MASK);
3377                 }
3378         }
3379
3380         return 0;
3381 }
3382
3383 #define MAC_TYPE_FILTER_SUP(type)    do {\
3384         if ((type) != e1000_82580 && (type) != e1000_i350 &&\
3385                 (type) != e1000_82576)\
3386                 return -ENOTSUP;\
3387 } while (0)
3388
3389 static int
3390 eth_igb_syn_filter_set(struct rte_eth_dev *dev,
3391                         struct rte_eth_syn_filter *filter,
3392                         bool add)
3393 {
3394         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3395         uint32_t synqf, rfctl;
3396
3397         if (filter->queue >= IGB_MAX_RX_QUEUE_NUM)
3398                 return -EINVAL;
3399
3400         synqf = E1000_READ_REG(hw, E1000_SYNQF(0));
3401
3402         if (add) {
3403                 if (synqf & E1000_SYN_FILTER_ENABLE)
3404                         return -EINVAL;
3405
3406                 synqf = (uint32_t)(((filter->queue << E1000_SYN_FILTER_QUEUE_SHIFT) &
3407                         E1000_SYN_FILTER_QUEUE) | E1000_SYN_FILTER_ENABLE);
3408
3409                 rfctl = E1000_READ_REG(hw, E1000_RFCTL);
3410                 if (filter->hig_pri)
3411                         rfctl |= E1000_RFCTL_SYNQFP;
3412                 else
3413                         rfctl &= ~E1000_RFCTL_SYNQFP;
3414
3415                 E1000_WRITE_REG(hw, E1000_RFCTL, rfctl);
3416         } else {
3417                 if (!(synqf & E1000_SYN_FILTER_ENABLE))
3418                         return -ENOENT;
3419                 synqf = 0;
3420         }
3421
3422         E1000_WRITE_REG(hw, E1000_SYNQF(0), synqf);
3423         E1000_WRITE_FLUSH(hw);
3424         return 0;
3425 }
3426
3427 static int
3428 eth_igb_syn_filter_get(struct rte_eth_dev *dev,
3429                         struct rte_eth_syn_filter *filter)
3430 {
3431         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3432         uint32_t synqf, rfctl;
3433
3434         synqf = E1000_READ_REG(hw, E1000_SYNQF(0));
3435         if (synqf & E1000_SYN_FILTER_ENABLE) {
3436                 rfctl = E1000_READ_REG(hw, E1000_RFCTL);
3437                 filter->hig_pri = (rfctl & E1000_RFCTL_SYNQFP) ? 1 : 0;
3438                 filter->queue = (uint8_t)((synqf & E1000_SYN_FILTER_QUEUE) >>
3439                                 E1000_SYN_FILTER_QUEUE_SHIFT);
3440                 return 0;
3441         }
3442
3443         return -ENOENT;
3444 }
3445
3446 static int
3447 eth_igb_syn_filter_handle(struct rte_eth_dev *dev,
3448                         enum rte_filter_op filter_op,
3449                         void *arg)
3450 {
3451         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3452         int ret;
3453
3454         MAC_TYPE_FILTER_SUP(hw->mac.type);
3455
3456         if (filter_op == RTE_ETH_FILTER_NOP)
3457                 return 0;
3458
3459         if (arg == NULL) {
3460                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
3461                             filter_op);
3462                 return -EINVAL;
3463         }
3464
3465         switch (filter_op) {
3466         case RTE_ETH_FILTER_ADD:
3467                 ret = eth_igb_syn_filter_set(dev,
3468                                 (struct rte_eth_syn_filter *)arg,
3469                                 TRUE);
3470                 break;
3471         case RTE_ETH_FILTER_DELETE:
3472                 ret = eth_igb_syn_filter_set(dev,
3473                                 (struct rte_eth_syn_filter *)arg,
3474                                 FALSE);
3475                 break;
3476         case RTE_ETH_FILTER_GET:
3477                 ret = eth_igb_syn_filter_get(dev,
3478                                 (struct rte_eth_syn_filter *)arg);
3479                 break;
3480         default:
3481                 PMD_DRV_LOG(ERR, "unsupported operation %u\n", filter_op);
3482                 ret = -EINVAL;
3483                 break;
3484         }
3485
3486         return ret;
3487 }
3488
3489 #define MAC_TYPE_FILTER_SUP_EXT(type)    do {\
3490         if ((type) != e1000_82580 && (type) != e1000_i350)\
3491                 return -ENOSYS; \
3492 } while (0)
3493
3494 /* translate elements in struct rte_eth_ntuple_filter to struct e1000_2tuple_filter_info*/
3495 static inline int
3496 ntuple_filter_to_2tuple(struct rte_eth_ntuple_filter *filter,
3497                         struct e1000_2tuple_filter_info *filter_info)
3498 {
3499         if (filter->queue >= IGB_MAX_RX_QUEUE_NUM)
3500                 return -EINVAL;
3501         if (filter->priority > E1000_2TUPLE_MAX_PRI)
3502                 return -EINVAL;  /* filter index is out of range. */
3503         if (filter->tcp_flags > TCP_FLAG_ALL)
3504                 return -EINVAL;  /* flags is invalid. */
3505
3506         switch (filter->dst_port_mask) {
3507         case UINT16_MAX:
3508                 filter_info->dst_port_mask = 0;
3509                 filter_info->dst_port = filter->dst_port;
3510                 break;
3511         case 0:
3512                 filter_info->dst_port_mask = 1;
3513                 break;
3514         default:
3515                 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
3516                 return -EINVAL;
3517         }
3518
3519         switch (filter->proto_mask) {
3520         case UINT8_MAX:
3521                 filter_info->proto_mask = 0;
3522                 filter_info->proto = filter->proto;
3523                 break;
3524         case 0:
3525                 filter_info->proto_mask = 1;
3526                 break;
3527         default:
3528                 PMD_DRV_LOG(ERR, "invalid protocol mask.");
3529                 return -EINVAL;
3530         }
3531
3532         filter_info->priority = (uint8_t)filter->priority;
3533         if (filter->flags & RTE_NTUPLE_FLAGS_TCP_FLAG)
3534                 filter_info->tcp_flags = filter->tcp_flags;
3535         else
3536                 filter_info->tcp_flags = 0;
3537
3538         return 0;
3539 }
3540
3541 static inline struct e1000_2tuple_filter *
3542 igb_2tuple_filter_lookup(struct e1000_2tuple_filter_list *filter_list,
3543                         struct e1000_2tuple_filter_info *key)
3544 {
3545         struct e1000_2tuple_filter *it;
3546
3547         TAILQ_FOREACH(it, filter_list, entries) {
3548                 if (memcmp(key, &it->filter_info,
3549                         sizeof(struct e1000_2tuple_filter_info)) == 0) {
3550                         return it;
3551                 }
3552         }
3553         return NULL;
3554 }
3555
3556 /*
3557  * igb_add_2tuple_filter - add a 2tuple filter
3558  *
3559  * @param
3560  * dev: Pointer to struct rte_eth_dev.
3561  * ntuple_filter: ponter to the filter that will be added.
3562  *
3563  * @return
3564  *    - On success, zero.
3565  *    - On failure, a negative value.
3566  */
3567 static int
3568 igb_add_2tuple_filter(struct rte_eth_dev *dev,
3569                         struct rte_eth_ntuple_filter *ntuple_filter)
3570 {
3571         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3572         struct e1000_filter_info *filter_info =
3573                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3574         struct e1000_2tuple_filter *filter;
3575         uint32_t ttqf = E1000_TTQF_DISABLE_MASK;
3576         uint32_t imir, imir_ext = E1000_IMIREXT_SIZE_BP;
3577         int i, ret;
3578
3579         filter = rte_zmalloc("e1000_2tuple_filter",
3580                         sizeof(struct e1000_2tuple_filter), 0);
3581         if (filter == NULL)
3582                 return -ENOMEM;
3583
3584         ret = ntuple_filter_to_2tuple(ntuple_filter,
3585                                       &filter->filter_info);
3586         if (ret < 0) {
3587                 rte_free(filter);
3588                 return ret;
3589         }
3590         if (igb_2tuple_filter_lookup(&filter_info->twotuple_list,
3591                                          &filter->filter_info) != NULL) {
3592                 PMD_DRV_LOG(ERR, "filter exists.");
3593                 rte_free(filter);
3594                 return -EEXIST;
3595         }
3596         filter->queue = ntuple_filter->queue;
3597
3598         /*
3599          * look for an unused 2tuple filter index,
3600          * and insert the filter to list.
3601          */
3602         for (i = 0; i < E1000_MAX_TTQF_FILTERS; i++) {
3603                 if (!(filter_info->twotuple_mask & (1 << i))) {
3604                         filter_info->twotuple_mask |= 1 << i;
3605                         filter->index = i;
3606                         TAILQ_INSERT_TAIL(&filter_info->twotuple_list,
3607                                           filter,
3608                                           entries);
3609                         break;
3610                 }
3611         }
3612         if (i >= E1000_MAX_TTQF_FILTERS) {
3613                 PMD_DRV_LOG(ERR, "2tuple filters are full.");
3614                 rte_free(filter);
3615                 return -ENOSYS;
3616         }
3617
3618         imir = (uint32_t)(filter->filter_info.dst_port & E1000_IMIR_DSTPORT);
3619         if (filter->filter_info.dst_port_mask == 1) /* 1b means not compare. */
3620                 imir |= E1000_IMIR_PORT_BP;
3621         else
3622                 imir &= ~E1000_IMIR_PORT_BP;
3623
3624         imir |= filter->filter_info.priority << E1000_IMIR_PRIORITY_SHIFT;
3625
3626         ttqf |= E1000_TTQF_QUEUE_ENABLE;
3627         ttqf |= (uint32_t)(filter->queue << E1000_TTQF_QUEUE_SHIFT);
3628         ttqf |= (uint32_t)(filter->filter_info.proto & E1000_TTQF_PROTOCOL_MASK);
3629         if (filter->filter_info.proto_mask == 0)
3630                 ttqf &= ~E1000_TTQF_MASK_ENABLE;
3631
3632         /* tcp flags bits setting. */
3633         if (filter->filter_info.tcp_flags & TCP_FLAG_ALL) {
3634                 if (filter->filter_info.tcp_flags & TCP_URG_FLAG)
3635                         imir_ext |= E1000_IMIREXT_CTRL_URG;
3636                 if (filter->filter_info.tcp_flags & TCP_ACK_FLAG)
3637                         imir_ext |= E1000_IMIREXT_CTRL_ACK;
3638                 if (filter->filter_info.tcp_flags & TCP_PSH_FLAG)
3639                         imir_ext |= E1000_IMIREXT_CTRL_PSH;
3640                 if (filter->filter_info.tcp_flags & TCP_RST_FLAG)
3641                         imir_ext |= E1000_IMIREXT_CTRL_RST;
3642                 if (filter->filter_info.tcp_flags & TCP_SYN_FLAG)
3643                         imir_ext |= E1000_IMIREXT_CTRL_SYN;
3644                 if (filter->filter_info.tcp_flags & TCP_FIN_FLAG)
3645                         imir_ext |= E1000_IMIREXT_CTRL_FIN;
3646         } else
3647                 imir_ext |= E1000_IMIREXT_CTRL_BP;
3648         E1000_WRITE_REG(hw, E1000_IMIR(i), imir);
3649         E1000_WRITE_REG(hw, E1000_TTQF(i), ttqf);
3650         E1000_WRITE_REG(hw, E1000_IMIREXT(i), imir_ext);
3651         return 0;
3652 }
3653
3654 /*
3655  * igb_remove_2tuple_filter - remove a 2tuple filter
3656  *
3657  * @param
3658  * dev: Pointer to struct rte_eth_dev.
3659  * ntuple_filter: ponter to the filter that will be removed.
3660  *
3661  * @return
3662  *    - On success, zero.
3663  *    - On failure, a negative value.
3664  */
3665 static int
3666 igb_remove_2tuple_filter(struct rte_eth_dev *dev,
3667                         struct rte_eth_ntuple_filter *ntuple_filter)
3668 {
3669         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3670         struct e1000_filter_info *filter_info =
3671                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3672         struct e1000_2tuple_filter_info filter_2tuple;
3673         struct e1000_2tuple_filter *filter;
3674         int ret;
3675
3676         memset(&filter_2tuple, 0, sizeof(struct e1000_2tuple_filter_info));
3677         ret = ntuple_filter_to_2tuple(ntuple_filter,
3678                                       &filter_2tuple);
3679         if (ret < 0)
3680                 return ret;
3681
3682         filter = igb_2tuple_filter_lookup(&filter_info->twotuple_list,
3683                                          &filter_2tuple);
3684         if (filter == NULL) {
3685                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
3686                 return -ENOENT;
3687         }
3688
3689         filter_info->twotuple_mask &= ~(1 << filter->index);
3690         TAILQ_REMOVE(&filter_info->twotuple_list, filter, entries);
3691         rte_free(filter);
3692
3693         E1000_WRITE_REG(hw, E1000_TTQF(filter->index), E1000_TTQF_DISABLE_MASK);
3694         E1000_WRITE_REG(hw, E1000_IMIR(filter->index), 0);
3695         E1000_WRITE_REG(hw, E1000_IMIREXT(filter->index), 0);
3696         return 0;
3697 }
3698
3699 static inline struct e1000_flex_filter *
3700 eth_igb_flex_filter_lookup(struct e1000_flex_filter_list *filter_list,
3701                         struct e1000_flex_filter_info *key)
3702 {
3703         struct e1000_flex_filter *it;
3704
3705         TAILQ_FOREACH(it, filter_list, entries) {
3706                 if (memcmp(key, &it->filter_info,
3707                         sizeof(struct e1000_flex_filter_info)) == 0)
3708                         return it;
3709         }
3710
3711         return NULL;
3712 }
3713
3714 static int
3715 eth_igb_add_del_flex_filter(struct rte_eth_dev *dev,
3716                         struct rte_eth_flex_filter *filter,
3717                         bool add)
3718 {
3719         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3720         struct e1000_filter_info *filter_info =
3721                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3722         struct e1000_flex_filter *flex_filter, *it;
3723         uint32_t wufc, queueing, mask;
3724         uint32_t reg_off;
3725         uint8_t shift, i, j = 0;
3726
3727         flex_filter = rte_zmalloc("e1000_flex_filter",
3728                         sizeof(struct e1000_flex_filter), 0);
3729         if (flex_filter == NULL)
3730                 return -ENOMEM;
3731
3732         flex_filter->filter_info.len = filter->len;
3733         flex_filter->filter_info.priority = filter->priority;
3734         memcpy(flex_filter->filter_info.dwords, filter->bytes, filter->len);
3735         for (i = 0; i < RTE_ALIGN(filter->len, CHAR_BIT) / CHAR_BIT; i++) {
3736                 mask = 0;
3737                 /* reverse bits in flex filter's mask*/
3738                 for (shift = 0; shift < CHAR_BIT; shift++) {
3739                         if (filter->mask[i] & (0x01 << shift))
3740                                 mask |= (0x80 >> shift);
3741                 }
3742                 flex_filter->filter_info.mask[i] = mask;
3743         }
3744
3745         wufc = E1000_READ_REG(hw, E1000_WUFC);
3746
3747         if (add) {
3748                 if (eth_igb_flex_filter_lookup(&filter_info->flex_list,
3749                                 &flex_filter->filter_info) != NULL) {
3750                         PMD_DRV_LOG(ERR, "filter exists.");
3751                         rte_free(flex_filter);
3752                         return -EEXIST;
3753                 }
3754                 flex_filter->queue = filter->queue;
3755                 /*
3756                  * look for an unused flex filter index
3757                  * and insert the filter into the list.
3758                  */
3759                 for (i = 0; i < E1000_MAX_FLEX_FILTERS; i++) {
3760                         if (!(filter_info->flex_mask & (1 << i))) {
3761                                 filter_info->flex_mask |= 1 << i;
3762                                 flex_filter->index = i;
3763                                 TAILQ_INSERT_TAIL(&filter_info->flex_list,
3764                                         flex_filter,
3765                                         entries);
3766                                 break;
3767                         }
3768                 }
3769                 if (i >= E1000_MAX_FLEX_FILTERS) {
3770                         PMD_DRV_LOG(ERR, "flex filters are full.");
3771                         rte_free(flex_filter);
3772                         return -ENOSYS;
3773                 }
3774
3775                 if (flex_filter->index < E1000_MAX_FHFT)
3776                         reg_off = E1000_FHFT(flex_filter->index);
3777                 else
3778                         reg_off = E1000_FHFT_EXT(flex_filter->index - E1000_MAX_FHFT);
3779
3780                 E1000_WRITE_REG(hw, E1000_WUFC, wufc | E1000_WUFC_FLEX_HQ |
3781                                 (E1000_WUFC_FLX0 << flex_filter->index));
3782                 queueing = filter->len |
3783                         (filter->queue << E1000_FHFT_QUEUEING_QUEUE_SHIFT) |
3784                         (filter->priority << E1000_FHFT_QUEUEING_PRIO_SHIFT);
3785                 E1000_WRITE_REG(hw, reg_off + E1000_FHFT_QUEUEING_OFFSET,
3786                                 queueing);
3787                 for (i = 0; i < E1000_FLEX_FILTERS_MASK_SIZE; i++) {
3788                         E1000_WRITE_REG(hw, reg_off,
3789                                         flex_filter->filter_info.dwords[j]);
3790                         reg_off += sizeof(uint32_t);
3791                         E1000_WRITE_REG(hw, reg_off,
3792                                         flex_filter->filter_info.dwords[++j]);
3793                         reg_off += sizeof(uint32_t);
3794                         E1000_WRITE_REG(hw, reg_off,
3795                                 (uint32_t)flex_filter->filter_info.mask[i]);
3796                         reg_off += sizeof(uint32_t) * 2;
3797                         ++j;
3798                 }
3799         } else {
3800                 it = eth_igb_flex_filter_lookup(&filter_info->flex_list,
3801                                 &flex_filter->filter_info);
3802                 if (it == NULL) {
3803                         PMD_DRV_LOG(ERR, "filter doesn't exist.");
3804                         rte_free(flex_filter);
3805                         return -ENOENT;
3806                 }
3807
3808                 if (it->index < E1000_MAX_FHFT)
3809                         reg_off = E1000_FHFT(it->index);
3810                 else
3811                         reg_off = E1000_FHFT_EXT(it->index - E1000_MAX_FHFT);
3812
3813                 for (i = 0; i < E1000_FHFT_SIZE_IN_DWD; i++)
3814                         E1000_WRITE_REG(hw, reg_off + i * sizeof(uint32_t), 0);
3815                 E1000_WRITE_REG(hw, E1000_WUFC, wufc &
3816                         (~(E1000_WUFC_FLX0 << it->index)));
3817
3818                 filter_info->flex_mask &= ~(1 << it->index);
3819                 TAILQ_REMOVE(&filter_info->flex_list, it, entries);
3820                 rte_free(it);
3821                 rte_free(flex_filter);
3822         }
3823
3824         return 0;
3825 }
3826
3827 static int
3828 eth_igb_get_flex_filter(struct rte_eth_dev *dev,
3829                         struct rte_eth_flex_filter *filter)
3830 {
3831         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3832         struct e1000_filter_info *filter_info =
3833                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3834         struct e1000_flex_filter flex_filter, *it;
3835         uint32_t wufc, queueing, wufc_en = 0;
3836
3837         memset(&flex_filter, 0, sizeof(struct e1000_flex_filter));
3838         flex_filter.filter_info.len = filter->len;
3839         flex_filter.filter_info.priority = filter->priority;
3840         memcpy(flex_filter.filter_info.dwords, filter->bytes, filter->len);
3841         memcpy(flex_filter.filter_info.mask, filter->mask,
3842                         RTE_ALIGN(filter->len, sizeof(char)) / sizeof(char));
3843
3844         it = eth_igb_flex_filter_lookup(&filter_info->flex_list,
3845                                 &flex_filter.filter_info);
3846         if (it == NULL) {
3847                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
3848                 return -ENOENT;
3849         }
3850
3851         wufc = E1000_READ_REG(hw, E1000_WUFC);
3852         wufc_en = E1000_WUFC_FLEX_HQ | (E1000_WUFC_FLX0 << it->index);
3853
3854         if ((wufc & wufc_en) == wufc_en) {
3855                 uint32_t reg_off = 0;
3856                 if (it->index < E1000_MAX_FHFT)
3857                         reg_off = E1000_FHFT(it->index);
3858                 else
3859                         reg_off = E1000_FHFT_EXT(it->index - E1000_MAX_FHFT);
3860
3861                 queueing = E1000_READ_REG(hw,
3862                                 reg_off + E1000_FHFT_QUEUEING_OFFSET);
3863                 filter->len = queueing & E1000_FHFT_QUEUEING_LEN;
3864                 filter->priority = (queueing & E1000_FHFT_QUEUEING_PRIO) >>
3865                         E1000_FHFT_QUEUEING_PRIO_SHIFT;
3866                 filter->queue = (queueing & E1000_FHFT_QUEUEING_QUEUE) >>
3867                         E1000_FHFT_QUEUEING_QUEUE_SHIFT;
3868                 return 0;
3869         }
3870         return -ENOENT;
3871 }
3872
3873 static int
3874 eth_igb_flex_filter_handle(struct rte_eth_dev *dev,
3875                         enum rte_filter_op filter_op,
3876                         void *arg)
3877 {
3878         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3879         struct rte_eth_flex_filter *filter;
3880         int ret = 0;
3881
3882         MAC_TYPE_FILTER_SUP_EXT(hw->mac.type);
3883
3884         if (filter_op == RTE_ETH_FILTER_NOP)
3885                 return ret;
3886
3887         if (arg == NULL) {
3888                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
3889                             filter_op);
3890                 return -EINVAL;
3891         }
3892
3893         filter = (struct rte_eth_flex_filter *)arg;
3894         if (filter->len == 0 || filter->len > E1000_MAX_FLEX_FILTER_LEN
3895             || filter->len % sizeof(uint64_t) != 0) {
3896                 PMD_DRV_LOG(ERR, "filter's length is out of range");
3897                 return -EINVAL;
3898         }
3899         if (filter->priority > E1000_MAX_FLEX_FILTER_PRI) {
3900                 PMD_DRV_LOG(ERR, "filter's priority is out of range");
3901                 return -EINVAL;
3902         }
3903
3904         switch (filter_op) {
3905         case RTE_ETH_FILTER_ADD:
3906                 ret = eth_igb_add_del_flex_filter(dev, filter, TRUE);
3907                 break;
3908         case RTE_ETH_FILTER_DELETE:
3909                 ret = eth_igb_add_del_flex_filter(dev, filter, FALSE);
3910                 break;
3911         case RTE_ETH_FILTER_GET:
3912                 ret = eth_igb_get_flex_filter(dev, filter);
3913                 break;
3914         default:
3915                 PMD_DRV_LOG(ERR, "unsupported operation %u", filter_op);
3916                 ret = -EINVAL;
3917                 break;
3918         }
3919
3920         return ret;
3921 }
3922
3923 /* translate elements in struct rte_eth_ntuple_filter to struct e1000_5tuple_filter_info*/
3924 static inline int
3925 ntuple_filter_to_5tuple_82576(struct rte_eth_ntuple_filter *filter,
3926                         struct e1000_5tuple_filter_info *filter_info)
3927 {
3928         if (filter->queue >= IGB_MAX_RX_QUEUE_NUM_82576)
3929                 return -EINVAL;
3930         if (filter->priority > E1000_2TUPLE_MAX_PRI)
3931                 return -EINVAL;  /* filter index is out of range. */
3932         if (filter->tcp_flags > TCP_FLAG_ALL)
3933                 return -EINVAL;  /* flags is invalid. */
3934
3935         switch (filter->dst_ip_mask) {
3936         case UINT32_MAX:
3937                 filter_info->dst_ip_mask = 0;
3938                 filter_info->dst_ip = filter->dst_ip;
3939                 break;
3940         case 0:
3941                 filter_info->dst_ip_mask = 1;
3942                 break;
3943         default:
3944                 PMD_DRV_LOG(ERR, "invalid dst_ip mask.");
3945                 return -EINVAL;
3946         }
3947
3948         switch (filter->src_ip_mask) {
3949         case UINT32_MAX:
3950                 filter_info->src_ip_mask = 0;
3951                 filter_info->src_ip = filter->src_ip;
3952                 break;
3953         case 0:
3954                 filter_info->src_ip_mask = 1;
3955                 break;
3956         default:
3957                 PMD_DRV_LOG(ERR, "invalid src_ip mask.");
3958                 return -EINVAL;
3959         }
3960
3961         switch (filter->dst_port_mask) {
3962         case UINT16_MAX:
3963                 filter_info->dst_port_mask = 0;
3964                 filter_info->dst_port = filter->dst_port;
3965                 break;
3966         case 0:
3967                 filter_info->dst_port_mask = 1;
3968                 break;
3969         default:
3970                 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
3971                 return -EINVAL;
3972         }
3973
3974         switch (filter->src_port_mask) {
3975         case UINT16_MAX:
3976                 filter_info->src_port_mask = 0;
3977                 filter_info->src_port = filter->src_port;
3978                 break;
3979         case 0:
3980                 filter_info->src_port_mask = 1;
3981                 break;
3982         default:
3983                 PMD_DRV_LOG(ERR, "invalid src_port mask.");
3984                 return -EINVAL;
3985         }
3986
3987         switch (filter->proto_mask) {
3988         case UINT8_MAX:
3989                 filter_info->proto_mask = 0;
3990                 filter_info->proto = filter->proto;
3991                 break;
3992         case 0:
3993                 filter_info->proto_mask = 1;
3994                 break;
3995         default:
3996                 PMD_DRV_LOG(ERR, "invalid protocol mask.");
3997                 return -EINVAL;
3998         }
3999
4000         filter_info->priority = (uint8_t)filter->priority;
4001         if (filter->flags & RTE_NTUPLE_FLAGS_TCP_FLAG)
4002                 filter_info->tcp_flags = filter->tcp_flags;
4003         else
4004                 filter_info->tcp_flags = 0;
4005
4006         return 0;
4007 }
4008
4009 static inline struct e1000_5tuple_filter *
4010 igb_5tuple_filter_lookup_82576(struct e1000_5tuple_filter_list *filter_list,
4011                         struct e1000_5tuple_filter_info *key)
4012 {
4013         struct e1000_5tuple_filter *it;
4014
4015         TAILQ_FOREACH(it, filter_list, entries) {
4016                 if (memcmp(key, &it->filter_info,
4017                         sizeof(struct e1000_5tuple_filter_info)) == 0) {
4018                         return it;
4019                 }
4020         }
4021         return NULL;
4022 }
4023
4024 /*
4025  * igb_add_5tuple_filter_82576 - add a 5tuple filter
4026  *
4027  * @param
4028  * dev: Pointer to struct rte_eth_dev.
4029  * ntuple_filter: ponter to the filter that will be added.
4030  *
4031  * @return
4032  *    - On success, zero.
4033  *    - On failure, a negative value.
4034  */
4035 static int
4036 igb_add_5tuple_filter_82576(struct rte_eth_dev *dev,
4037                         struct rte_eth_ntuple_filter *ntuple_filter)
4038 {
4039         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4040         struct e1000_filter_info *filter_info =
4041                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4042         struct e1000_5tuple_filter *filter;
4043         uint32_t ftqf = E1000_FTQF_VF_BP | E1000_FTQF_MASK;
4044         uint32_t spqf, imir, imir_ext = E1000_IMIREXT_SIZE_BP;
4045         uint8_t i;
4046         int ret;
4047
4048         filter = rte_zmalloc("e1000_5tuple_filter",
4049                         sizeof(struct e1000_5tuple_filter), 0);
4050         if (filter == NULL)
4051                 return -ENOMEM;
4052
4053         ret = ntuple_filter_to_5tuple_82576(ntuple_filter,
4054                                             &filter->filter_info);
4055         if (ret < 0) {
4056                 rte_free(filter);
4057                 return ret;
4058         }
4059
4060         if (igb_5tuple_filter_lookup_82576(&filter_info->fivetuple_list,
4061                                          &filter->filter_info) != NULL) {
4062                 PMD_DRV_LOG(ERR, "filter exists.");
4063                 rte_free(filter);
4064                 return -EEXIST;
4065         }
4066         filter->queue = ntuple_filter->queue;
4067
4068         /*
4069          * look for an unused 5tuple filter index,
4070          * and insert the filter to list.
4071          */
4072         for (i = 0; i < E1000_MAX_FTQF_FILTERS; i++) {
4073                 if (!(filter_info->fivetuple_mask & (1 << i))) {
4074                         filter_info->fivetuple_mask |= 1 << i;
4075                         filter->index = i;
4076                         TAILQ_INSERT_TAIL(&filter_info->fivetuple_list,
4077                                           filter,
4078                                           entries);
4079                         break;
4080                 }
4081         }
4082         if (i >= E1000_MAX_FTQF_FILTERS) {
4083                 PMD_DRV_LOG(ERR, "5tuple filters are full.");
4084                 rte_free(filter);
4085                 return -ENOSYS;
4086         }
4087
4088         ftqf |= filter->filter_info.proto & E1000_FTQF_PROTOCOL_MASK;
4089         if (filter->filter_info.src_ip_mask == 0) /* 0b means compare. */
4090                 ftqf &= ~E1000_FTQF_MASK_SOURCE_ADDR_BP;
4091         if (filter->filter_info.dst_ip_mask == 0)
4092                 ftqf &= ~E1000_FTQF_MASK_DEST_ADDR_BP;
4093         if (filter->filter_info.src_port_mask == 0)
4094                 ftqf &= ~E1000_FTQF_MASK_SOURCE_PORT_BP;
4095         if (filter->filter_info.proto_mask == 0)
4096                 ftqf &= ~E1000_FTQF_MASK_PROTO_BP;
4097         ftqf |= (filter->queue << E1000_FTQF_QUEUE_SHIFT) &
4098                 E1000_FTQF_QUEUE_MASK;
4099         ftqf |= E1000_FTQF_QUEUE_ENABLE;
4100         E1000_WRITE_REG(hw, E1000_FTQF(i), ftqf);
4101         E1000_WRITE_REG(hw, E1000_DAQF(i), filter->filter_info.dst_ip);
4102         E1000_WRITE_REG(hw, E1000_SAQF(i), filter->filter_info.src_ip);
4103
4104         spqf = filter->filter_info.src_port & E1000_SPQF_SRCPORT;
4105         E1000_WRITE_REG(hw, E1000_SPQF(i), spqf);
4106
4107         imir = (uint32_t)(filter->filter_info.dst_port & E1000_IMIR_DSTPORT);
4108         if (filter->filter_info.dst_port_mask == 1) /* 1b means not compare. */
4109                 imir |= E1000_IMIR_PORT_BP;
4110         else
4111                 imir &= ~E1000_IMIR_PORT_BP;
4112         imir |= filter->filter_info.priority << E1000_IMIR_PRIORITY_SHIFT;
4113
4114         /* tcp flags bits setting. */
4115         if (filter->filter_info.tcp_flags & TCP_FLAG_ALL) {
4116                 if (filter->filter_info.tcp_flags & TCP_URG_FLAG)
4117                         imir_ext |= E1000_IMIREXT_CTRL_URG;
4118                 if (filter->filter_info.tcp_flags & TCP_ACK_FLAG)
4119                         imir_ext |= E1000_IMIREXT_CTRL_ACK;
4120                 if (filter->filter_info.tcp_flags & TCP_PSH_FLAG)
4121                         imir_ext |= E1000_IMIREXT_CTRL_PSH;
4122                 if (filter->filter_info.tcp_flags & TCP_RST_FLAG)
4123                         imir_ext |= E1000_IMIREXT_CTRL_RST;
4124                 if (filter->filter_info.tcp_flags & TCP_SYN_FLAG)
4125                         imir_ext |= E1000_IMIREXT_CTRL_SYN;
4126                 if (filter->filter_info.tcp_flags & TCP_FIN_FLAG)
4127                         imir_ext |= E1000_IMIREXT_CTRL_FIN;
4128         } else
4129                 imir_ext |= E1000_IMIREXT_CTRL_BP;
4130         E1000_WRITE_REG(hw, E1000_IMIR(i), imir);
4131         E1000_WRITE_REG(hw, E1000_IMIREXT(i), imir_ext);
4132         return 0;
4133 }
4134
4135 /*
4136  * igb_remove_5tuple_filter_82576 - remove a 5tuple filter
4137  *
4138  * @param
4139  * dev: Pointer to struct rte_eth_dev.
4140  * ntuple_filter: ponter to the filter that will be removed.
4141  *
4142  * @return
4143  *    - On success, zero.
4144  *    - On failure, a negative value.
4145  */
4146 static int
4147 igb_remove_5tuple_filter_82576(struct rte_eth_dev *dev,
4148                                 struct rte_eth_ntuple_filter *ntuple_filter)
4149 {
4150         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4151         struct e1000_filter_info *filter_info =
4152                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4153         struct e1000_5tuple_filter_info filter_5tuple;
4154         struct e1000_5tuple_filter *filter;
4155         int ret;
4156
4157         memset(&filter_5tuple, 0, sizeof(struct e1000_5tuple_filter_info));
4158         ret = ntuple_filter_to_5tuple_82576(ntuple_filter,
4159                                             &filter_5tuple);
4160         if (ret < 0)
4161                 return ret;
4162
4163         filter = igb_5tuple_filter_lookup_82576(&filter_info->fivetuple_list,
4164                                          &filter_5tuple);
4165         if (filter == NULL) {
4166                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
4167                 return -ENOENT;
4168         }
4169
4170         filter_info->fivetuple_mask &= ~(1 << filter->index);
4171         TAILQ_REMOVE(&filter_info->fivetuple_list, filter, entries);
4172         rte_free(filter);
4173
4174         E1000_WRITE_REG(hw, E1000_FTQF(filter->index),
4175                         E1000_FTQF_VF_BP | E1000_FTQF_MASK);
4176         E1000_WRITE_REG(hw, E1000_DAQF(filter->index), 0);
4177         E1000_WRITE_REG(hw, E1000_SAQF(filter->index), 0);
4178         E1000_WRITE_REG(hw, E1000_SPQF(filter->index), 0);
4179         E1000_WRITE_REG(hw, E1000_IMIR(filter->index), 0);
4180         E1000_WRITE_REG(hw, E1000_IMIREXT(filter->index), 0);
4181         return 0;
4182 }
4183
4184 static int
4185 eth_igb_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
4186 {
4187         uint32_t rctl;
4188         struct e1000_hw *hw;
4189         struct rte_eth_dev_info dev_info;
4190         uint32_t frame_size = mtu + (ETHER_HDR_LEN + ETHER_CRC_LEN +
4191                                      VLAN_TAG_SIZE);
4192
4193         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4194
4195 #ifdef RTE_LIBRTE_82571_SUPPORT
4196         /* XXX: not bigger than max_rx_pktlen */
4197         if (hw->mac.type == e1000_82571)
4198                 return -ENOTSUP;
4199 #endif
4200         eth_igb_infos_get(dev, &dev_info);
4201
4202         /* check that mtu is within the allowed range */
4203         if ((mtu < ETHER_MIN_MTU) ||
4204             (frame_size > dev_info.max_rx_pktlen))
4205                 return -EINVAL;
4206
4207         /* refuse mtu that requires the support of scattered packets when this
4208          * feature has not been enabled before. */
4209         if (!dev->data->scattered_rx &&
4210             frame_size > dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)
4211                 return -EINVAL;
4212
4213         rctl = E1000_READ_REG(hw, E1000_RCTL);
4214
4215         /* switch to jumbo mode if needed */
4216         if (frame_size > ETHER_MAX_LEN) {
4217                 dev->data->dev_conf.rxmode.jumbo_frame = 1;
4218                 rctl |= E1000_RCTL_LPE;
4219         } else {
4220                 dev->data->dev_conf.rxmode.jumbo_frame = 0;
4221                 rctl &= ~E1000_RCTL_LPE;
4222         }
4223         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
4224
4225         /* update max frame size */
4226         dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
4227
4228         E1000_WRITE_REG(hw, E1000_RLPML,
4229                         dev->data->dev_conf.rxmode.max_rx_pkt_len);
4230
4231         return 0;
4232 }
4233
4234 /*
4235  * igb_add_del_ntuple_filter - add or delete a ntuple filter
4236  *
4237  * @param
4238  * dev: Pointer to struct rte_eth_dev.
4239  * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
4240  * add: if true, add filter, if false, remove filter
4241  *
4242  * @return
4243  *    - On success, zero.
4244  *    - On failure, a negative value.
4245  */
4246 static int
4247 igb_add_del_ntuple_filter(struct rte_eth_dev *dev,
4248                         struct rte_eth_ntuple_filter *ntuple_filter,
4249                         bool add)
4250 {
4251         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4252         int ret;
4253
4254         switch (ntuple_filter->flags) {
4255         case RTE_5TUPLE_FLAGS:
4256         case (RTE_5TUPLE_FLAGS | RTE_NTUPLE_FLAGS_TCP_FLAG):
4257                 if (hw->mac.type != e1000_82576)
4258                         return -ENOTSUP;
4259                 if (add)
4260                         ret = igb_add_5tuple_filter_82576(dev,
4261                                                           ntuple_filter);
4262                 else
4263                         ret = igb_remove_5tuple_filter_82576(dev,
4264                                                              ntuple_filter);
4265                 break;
4266         case RTE_2TUPLE_FLAGS:
4267         case (RTE_2TUPLE_FLAGS | RTE_NTUPLE_FLAGS_TCP_FLAG):
4268                 if (hw->mac.type != e1000_82580 && hw->mac.type != e1000_i350)
4269                         return -ENOTSUP;
4270                 if (add)
4271                         ret = igb_add_2tuple_filter(dev, ntuple_filter);
4272                 else
4273                         ret = igb_remove_2tuple_filter(dev, ntuple_filter);
4274                 break;
4275         default:
4276                 ret = -EINVAL;
4277                 break;
4278         }
4279
4280         return ret;
4281 }
4282
4283 /*
4284  * igb_get_ntuple_filter - get a ntuple filter
4285  *
4286  * @param
4287  * dev: Pointer to struct rte_eth_dev.
4288  * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
4289  *
4290  * @return
4291  *    - On success, zero.
4292  *    - On failure, a negative value.
4293  */
4294 static int
4295 igb_get_ntuple_filter(struct rte_eth_dev *dev,
4296                         struct rte_eth_ntuple_filter *ntuple_filter)
4297 {
4298         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4299         struct e1000_filter_info *filter_info =
4300                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4301         struct e1000_5tuple_filter_info filter_5tuple;
4302         struct e1000_2tuple_filter_info filter_2tuple;
4303         struct e1000_5tuple_filter *p_5tuple_filter;
4304         struct e1000_2tuple_filter *p_2tuple_filter;
4305         int ret;
4306
4307         switch (ntuple_filter->flags) {
4308         case RTE_5TUPLE_FLAGS:
4309         case (RTE_5TUPLE_FLAGS | RTE_NTUPLE_FLAGS_TCP_FLAG):
4310                 if (hw->mac.type != e1000_82576)
4311                         return -ENOTSUP;
4312                 memset(&filter_5tuple,
4313                         0,
4314                         sizeof(struct e1000_5tuple_filter_info));
4315                 ret = ntuple_filter_to_5tuple_82576(ntuple_filter,
4316                                                     &filter_5tuple);
4317                 if (ret < 0)
4318                         return ret;
4319                 p_5tuple_filter = igb_5tuple_filter_lookup_82576(
4320                                         &filter_info->fivetuple_list,
4321                                         &filter_5tuple);
4322                 if (p_5tuple_filter == NULL) {
4323                         PMD_DRV_LOG(ERR, "filter doesn't exist.");
4324                         return -ENOENT;
4325                 }
4326                 ntuple_filter->queue = p_5tuple_filter->queue;
4327                 break;
4328         case RTE_2TUPLE_FLAGS:
4329         case (RTE_2TUPLE_FLAGS | RTE_NTUPLE_FLAGS_TCP_FLAG):
4330                 if (hw->mac.type != e1000_82580 && hw->mac.type != e1000_i350)
4331                         return -ENOTSUP;
4332                 memset(&filter_2tuple,
4333                         0,
4334                         sizeof(struct e1000_2tuple_filter_info));
4335                 ret = ntuple_filter_to_2tuple(ntuple_filter, &filter_2tuple);
4336                 if (ret < 0)
4337                         return ret;
4338                 p_2tuple_filter = igb_2tuple_filter_lookup(
4339                                         &filter_info->twotuple_list,
4340                                         &filter_2tuple);
4341                 if (p_2tuple_filter == NULL) {
4342                         PMD_DRV_LOG(ERR, "filter doesn't exist.");
4343                         return -ENOENT;
4344                 }
4345                 ntuple_filter->queue = p_2tuple_filter->queue;
4346                 break;
4347         default:
4348                 ret = -EINVAL;
4349                 break;
4350         }
4351
4352         return 0;
4353 }
4354
4355 /*
4356  * igb_ntuple_filter_handle - Handle operations for ntuple filter.
4357  * @dev: pointer to rte_eth_dev structure
4358  * @filter_op:operation will be taken.
4359  * @arg: a pointer to specific structure corresponding to the filter_op
4360  */
4361 static int
4362 igb_ntuple_filter_handle(struct rte_eth_dev *dev,
4363                                 enum rte_filter_op filter_op,
4364                                 void *arg)
4365 {
4366         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4367         int ret;
4368
4369         MAC_TYPE_FILTER_SUP(hw->mac.type);
4370
4371         if (filter_op == RTE_ETH_FILTER_NOP)
4372                 return 0;
4373
4374         if (arg == NULL) {
4375                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
4376                             filter_op);
4377                 return -EINVAL;
4378         }
4379
4380         switch (filter_op) {
4381         case RTE_ETH_FILTER_ADD:
4382                 ret = igb_add_del_ntuple_filter(dev,
4383                         (struct rte_eth_ntuple_filter *)arg,
4384                         TRUE);
4385                 break;
4386         case RTE_ETH_FILTER_DELETE:
4387                 ret = igb_add_del_ntuple_filter(dev,
4388                         (struct rte_eth_ntuple_filter *)arg,
4389                         FALSE);
4390                 break;
4391         case RTE_ETH_FILTER_GET:
4392                 ret = igb_get_ntuple_filter(dev,
4393                         (struct rte_eth_ntuple_filter *)arg);
4394                 break;
4395         default:
4396                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
4397                 ret = -EINVAL;
4398                 break;
4399         }
4400         return ret;
4401 }
4402
4403 static inline int
4404 igb_ethertype_filter_lookup(struct e1000_filter_info *filter_info,
4405                         uint16_t ethertype)
4406 {
4407         int i;
4408
4409         for (i = 0; i < E1000_MAX_ETQF_FILTERS; i++) {
4410                 if (filter_info->ethertype_filters[i] == ethertype &&
4411                     (filter_info->ethertype_mask & (1 << i)))
4412                         return i;
4413         }
4414         return -1;
4415 }
4416
4417 static inline int
4418 igb_ethertype_filter_insert(struct e1000_filter_info *filter_info,
4419                         uint16_t ethertype)
4420 {
4421         int i;
4422
4423         for (i = 0; i < E1000_MAX_ETQF_FILTERS; i++) {
4424                 if (!(filter_info->ethertype_mask & (1 << i))) {
4425                         filter_info->ethertype_mask |= 1 << i;
4426                         filter_info->ethertype_filters[i] = ethertype;
4427                         return i;
4428                 }
4429         }
4430         return -1;
4431 }
4432
4433 static inline int
4434 igb_ethertype_filter_remove(struct e1000_filter_info *filter_info,
4435                         uint8_t idx)
4436 {
4437         if (idx >= E1000_MAX_ETQF_FILTERS)
4438                 return -1;
4439         filter_info->ethertype_mask &= ~(1 << idx);
4440         filter_info->ethertype_filters[idx] = 0;
4441         return idx;
4442 }
4443
4444
4445 static int
4446 igb_add_del_ethertype_filter(struct rte_eth_dev *dev,
4447                         struct rte_eth_ethertype_filter *filter,
4448                         bool add)
4449 {
4450         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4451         struct e1000_filter_info *filter_info =
4452                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4453         uint32_t etqf = 0;
4454         int ret;
4455
4456         if (filter->ether_type == ETHER_TYPE_IPv4 ||
4457                 filter->ether_type == ETHER_TYPE_IPv6) {
4458                 PMD_DRV_LOG(ERR, "unsupported ether_type(0x%04x) in"
4459                         " ethertype filter.", filter->ether_type);
4460                 return -EINVAL;
4461         }
4462
4463         if (filter->flags & RTE_ETHTYPE_FLAGS_MAC) {
4464                 PMD_DRV_LOG(ERR, "mac compare is unsupported.");
4465                 return -EINVAL;
4466         }
4467         if (filter->flags & RTE_ETHTYPE_FLAGS_DROP) {
4468                 PMD_DRV_LOG(ERR, "drop option is unsupported.");
4469                 return -EINVAL;
4470         }
4471
4472         ret = igb_ethertype_filter_lookup(filter_info, filter->ether_type);
4473         if (ret >= 0 && add) {
4474                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter exists.",
4475                             filter->ether_type);
4476                 return -EEXIST;
4477         }
4478         if (ret < 0 && !add) {
4479                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
4480                             filter->ether_type);
4481                 return -ENOENT;
4482         }
4483
4484         if (add) {
4485                 ret = igb_ethertype_filter_insert(filter_info,
4486                         filter->ether_type);
4487                 if (ret < 0) {
4488                         PMD_DRV_LOG(ERR, "ethertype filters are full.");
4489                         return -ENOSYS;
4490                 }
4491
4492                 etqf |= E1000_ETQF_FILTER_ENABLE | E1000_ETQF_QUEUE_ENABLE;
4493                 etqf |= (uint32_t)(filter->ether_type & E1000_ETQF_ETHERTYPE);
4494                 etqf |= filter->queue << E1000_ETQF_QUEUE_SHIFT;
4495         } else {
4496                 ret = igb_ethertype_filter_remove(filter_info, (uint8_t)ret);
4497                 if (ret < 0)
4498                         return -ENOSYS;
4499         }
4500         E1000_WRITE_REG(hw, E1000_ETQF(ret), etqf);
4501         E1000_WRITE_FLUSH(hw);
4502
4503         return 0;
4504 }
4505
4506 static int
4507 igb_get_ethertype_filter(struct rte_eth_dev *dev,
4508                         struct rte_eth_ethertype_filter *filter)
4509 {
4510         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4511         struct e1000_filter_info *filter_info =
4512                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4513         uint32_t etqf;
4514         int ret;
4515
4516         ret = igb_ethertype_filter_lookup(filter_info, filter->ether_type);
4517         if (ret < 0) {
4518                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
4519                             filter->ether_type);
4520                 return -ENOENT;
4521         }
4522
4523         etqf = E1000_READ_REG(hw, E1000_ETQF(ret));
4524         if (etqf & E1000_ETQF_FILTER_ENABLE) {
4525                 filter->ether_type = etqf & E1000_ETQF_ETHERTYPE;
4526                 filter->flags = 0;
4527                 filter->queue = (etqf & E1000_ETQF_QUEUE) >>
4528                                 E1000_ETQF_QUEUE_SHIFT;
4529                 return 0;
4530         }
4531
4532         return -ENOENT;
4533 }
4534
4535 /*
4536  * igb_ethertype_filter_handle - Handle operations for ethertype filter.
4537  * @dev: pointer to rte_eth_dev structure
4538  * @filter_op:operation will be taken.
4539  * @arg: a pointer to specific structure corresponding to the filter_op
4540  */
4541 static int
4542 igb_ethertype_filter_handle(struct rte_eth_dev *dev,
4543                                 enum rte_filter_op filter_op,
4544                                 void *arg)
4545 {
4546         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4547         int ret;
4548
4549         MAC_TYPE_FILTER_SUP(hw->mac.type);
4550
4551         if (filter_op == RTE_ETH_FILTER_NOP)
4552                 return 0;
4553
4554         if (arg == NULL) {
4555                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
4556                             filter_op);
4557                 return -EINVAL;
4558         }
4559
4560         switch (filter_op) {
4561         case RTE_ETH_FILTER_ADD:
4562                 ret = igb_add_del_ethertype_filter(dev,
4563                         (struct rte_eth_ethertype_filter *)arg,
4564                         TRUE);
4565                 break;
4566         case RTE_ETH_FILTER_DELETE:
4567                 ret = igb_add_del_ethertype_filter(dev,
4568                         (struct rte_eth_ethertype_filter *)arg,
4569                         FALSE);
4570                 break;
4571         case RTE_ETH_FILTER_GET:
4572                 ret = igb_get_ethertype_filter(dev,
4573                         (struct rte_eth_ethertype_filter *)arg);
4574                 break;
4575         default:
4576                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
4577                 ret = -EINVAL;
4578                 break;
4579         }
4580         return ret;
4581 }
4582
4583 static int
4584 eth_igb_filter_ctrl(struct rte_eth_dev *dev,
4585                      enum rte_filter_type filter_type,
4586                      enum rte_filter_op filter_op,
4587                      void *arg)
4588 {
4589         int ret = -EINVAL;
4590
4591         switch (filter_type) {
4592         case RTE_ETH_FILTER_NTUPLE:
4593                 ret = igb_ntuple_filter_handle(dev, filter_op, arg);
4594                 break;
4595         case RTE_ETH_FILTER_ETHERTYPE:
4596                 ret = igb_ethertype_filter_handle(dev, filter_op, arg);
4597                 break;
4598         case RTE_ETH_FILTER_SYN:
4599                 ret = eth_igb_syn_filter_handle(dev, filter_op, arg);
4600                 break;
4601         case RTE_ETH_FILTER_FLEXIBLE:
4602                 ret = eth_igb_flex_filter_handle(dev, filter_op, arg);
4603                 break;
4604         default:
4605                 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
4606                                                         filter_type);
4607                 break;
4608         }
4609
4610         return ret;
4611 }
4612
4613 static int
4614 eth_igb_set_mc_addr_list(struct rte_eth_dev *dev,
4615                          struct ether_addr *mc_addr_set,
4616                          uint32_t nb_mc_addr)
4617 {
4618         struct e1000_hw *hw;
4619
4620         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4621         e1000_update_mc_addr_list(hw, (u8 *)mc_addr_set, nb_mc_addr);
4622         return 0;
4623 }
4624
4625 static uint64_t
4626 igb_read_systime_cyclecounter(struct rte_eth_dev *dev)
4627 {
4628         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4629         uint64_t systime_cycles;
4630
4631         switch (hw->mac.type) {
4632         case e1000_i210:
4633         case e1000_i211:
4634                 /*
4635                  * Need to read System Time Residue Register to be able
4636                  * to read the other two registers.
4637                  */
4638                 E1000_READ_REG(hw, E1000_SYSTIMR);
4639                 /* SYSTIMEL stores ns and SYSTIMEH stores seconds. */
4640                 systime_cycles = (uint64_t)E1000_READ_REG(hw, E1000_SYSTIML);
4641                 systime_cycles += (uint64_t)E1000_READ_REG(hw, E1000_SYSTIMH)
4642                                 * NSEC_PER_SEC;
4643                 break;
4644         case e1000_82580:
4645         case e1000_i350:
4646         case e1000_i354:
4647                 /*
4648                  * Need to read System Time Residue Register to be able
4649                  * to read the other two registers.
4650                  */
4651                 E1000_READ_REG(hw, E1000_SYSTIMR);
4652                 systime_cycles = (uint64_t)E1000_READ_REG(hw, E1000_SYSTIML);
4653                 /* Only the 8 LSB are valid. */
4654                 systime_cycles |= (uint64_t)(E1000_READ_REG(hw, E1000_SYSTIMH)
4655                                 & 0xff) << 32;
4656                 break;
4657         default:
4658                 systime_cycles = (uint64_t)E1000_READ_REG(hw, E1000_SYSTIML);
4659                 systime_cycles |= (uint64_t)E1000_READ_REG(hw, E1000_SYSTIMH)
4660                                 << 32;
4661                 break;
4662         }
4663
4664         return systime_cycles;
4665 }
4666
4667 static uint64_t
4668 igb_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev)
4669 {
4670         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4671         uint64_t rx_tstamp_cycles;
4672
4673         switch (hw->mac.type) {
4674         case e1000_i210:
4675         case e1000_i211:
4676                 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
4677                 rx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_RXSTMPL);
4678                 rx_tstamp_cycles += (uint64_t)E1000_READ_REG(hw, E1000_RXSTMPH)
4679                                 * NSEC_PER_SEC;
4680                 break;
4681         case e1000_82580:
4682         case e1000_i350:
4683         case e1000_i354:
4684                 rx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_RXSTMPL);
4685                 /* Only the 8 LSB are valid. */
4686                 rx_tstamp_cycles |= (uint64_t)(E1000_READ_REG(hw, E1000_RXSTMPH)
4687                                 & 0xff) << 32;
4688                 break;
4689         default:
4690                 rx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_RXSTMPL);
4691                 rx_tstamp_cycles |= (uint64_t)E1000_READ_REG(hw, E1000_RXSTMPH)
4692                                 << 32;
4693                 break;
4694         }
4695
4696         return rx_tstamp_cycles;
4697 }
4698
4699 static uint64_t
4700 igb_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev)
4701 {
4702         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4703         uint64_t tx_tstamp_cycles;
4704
4705         switch (hw->mac.type) {
4706         case e1000_i210:
4707         case e1000_i211:
4708                 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
4709                 tx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_TXSTMPL);
4710                 tx_tstamp_cycles += (uint64_t)E1000_READ_REG(hw, E1000_TXSTMPH)
4711                                 * NSEC_PER_SEC;
4712                 break;
4713         case e1000_82580:
4714         case e1000_i350:
4715         case e1000_i354:
4716                 tx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_TXSTMPL);
4717                 /* Only the 8 LSB are valid. */
4718                 tx_tstamp_cycles |= (uint64_t)(E1000_READ_REG(hw, E1000_TXSTMPH)
4719                                 & 0xff) << 32;
4720                 break;
4721         default:
4722                 tx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_TXSTMPL);
4723                 tx_tstamp_cycles |= (uint64_t)E1000_READ_REG(hw, E1000_TXSTMPH)
4724                                 << 32;
4725                 break;
4726         }
4727
4728         return tx_tstamp_cycles;
4729 }
4730
4731 static void
4732 igb_start_timecounters(struct rte_eth_dev *dev)
4733 {
4734         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4735         struct e1000_adapter *adapter =
4736                 (struct e1000_adapter *)dev->data->dev_private;
4737         uint32_t incval = 1;
4738         uint32_t shift = 0;
4739         uint64_t mask = E1000_CYCLECOUNTER_MASK;
4740
4741         switch (hw->mac.type) {
4742         case e1000_82580:
4743         case e1000_i350:
4744         case e1000_i354:
4745                 /* 32 LSB bits + 8 MSB bits = 40 bits */
4746                 mask = (1ULL << 40) - 1;
4747                 /* fall-through */
4748         case e1000_i210:
4749         case e1000_i211:
4750                 /*
4751                  * Start incrementing the register
4752                  * used to timestamp PTP packets.
4753                  */
4754                 E1000_WRITE_REG(hw, E1000_TIMINCA, incval);
4755                 break;
4756         case e1000_82576:
4757                 incval = E1000_INCVALUE_82576;
4758                 shift = IGB_82576_TSYNC_SHIFT;
4759                 E1000_WRITE_REG(hw, E1000_TIMINCA,
4760                                 E1000_INCPERIOD_82576 | incval);
4761                 break;
4762         default:
4763                 /* Not supported */
4764                 return;
4765         }
4766
4767         memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter));
4768         memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
4769         memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
4770
4771         adapter->systime_tc.cc_mask = mask;
4772         adapter->systime_tc.cc_shift = shift;
4773         adapter->systime_tc.nsec_mask = (1ULL << shift) - 1;
4774
4775         adapter->rx_tstamp_tc.cc_mask = mask;
4776         adapter->rx_tstamp_tc.cc_shift = shift;
4777         adapter->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
4778
4779         adapter->tx_tstamp_tc.cc_mask = mask;
4780         adapter->tx_tstamp_tc.cc_shift = shift;
4781         adapter->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
4782 }
4783
4784 static int
4785 igb_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
4786 {
4787         struct e1000_adapter *adapter =
4788                         (struct e1000_adapter *)dev->data->dev_private;
4789
4790         adapter->systime_tc.nsec += delta;
4791         adapter->rx_tstamp_tc.nsec += delta;
4792         adapter->tx_tstamp_tc.nsec += delta;
4793
4794         return 0;
4795 }
4796
4797 static int
4798 igb_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
4799 {
4800         uint64_t ns;
4801         struct e1000_adapter *adapter =
4802                         (struct e1000_adapter *)dev->data->dev_private;
4803
4804         ns = rte_timespec_to_ns(ts);
4805
4806         /* Set the timecounters to a new value. */
4807         adapter->systime_tc.nsec = ns;
4808         adapter->rx_tstamp_tc.nsec = ns;
4809         adapter->tx_tstamp_tc.nsec = ns;
4810
4811         return 0;
4812 }
4813
4814 static int
4815 igb_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
4816 {
4817         uint64_t ns, systime_cycles;
4818         struct e1000_adapter *adapter =
4819                         (struct e1000_adapter *)dev->data->dev_private;
4820
4821         systime_cycles = igb_read_systime_cyclecounter(dev);
4822         ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles);
4823         *ts = rte_ns_to_timespec(ns);
4824
4825         return 0;
4826 }
4827
4828 static int
4829 igb_timesync_enable(struct rte_eth_dev *dev)
4830 {
4831         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4832         uint32_t tsync_ctl;
4833         uint32_t tsauxc;
4834
4835         /* Stop the timesync system time. */
4836         E1000_WRITE_REG(hw, E1000_TIMINCA, 0x0);
4837         /* Reset the timesync system time value. */
4838         switch (hw->mac.type) {
4839         case e1000_82580:
4840         case e1000_i350:
4841         case e1000_i354:
4842         case e1000_i210:
4843         case e1000_i211:
4844                 E1000_WRITE_REG(hw, E1000_SYSTIMR, 0x0);
4845                 /* fall-through */
4846         case e1000_82576:
4847                 E1000_WRITE_REG(hw, E1000_SYSTIML, 0x0);
4848                 E1000_WRITE_REG(hw, E1000_SYSTIMH, 0x0);
4849                 break;
4850         default:
4851                 /* Not supported. */
4852                 return -ENOTSUP;
4853         }
4854
4855         /* Enable system time for it isn't on by default. */
4856         tsauxc = E1000_READ_REG(hw, E1000_TSAUXC);
4857         tsauxc &= ~E1000_TSAUXC_DISABLE_SYSTIME;
4858         E1000_WRITE_REG(hw, E1000_TSAUXC, tsauxc);
4859
4860         igb_start_timecounters(dev);
4861
4862         /* Enable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
4863         E1000_WRITE_REG(hw, E1000_ETQF(E1000_ETQF_FILTER_1588),
4864                         (ETHER_TYPE_1588 |
4865                          E1000_ETQF_FILTER_ENABLE |
4866                          E1000_ETQF_1588));
4867
4868         /* Enable timestamping of received PTP packets. */
4869         tsync_ctl = E1000_READ_REG(hw, E1000_TSYNCRXCTL);
4870         tsync_ctl |= E1000_TSYNCRXCTL_ENABLED;
4871         E1000_WRITE_REG(hw, E1000_TSYNCRXCTL, tsync_ctl);
4872
4873         /* Enable Timestamping of transmitted PTP packets. */
4874         tsync_ctl = E1000_READ_REG(hw, E1000_TSYNCTXCTL);
4875         tsync_ctl |= E1000_TSYNCTXCTL_ENABLED;
4876         E1000_WRITE_REG(hw, E1000_TSYNCTXCTL, tsync_ctl);
4877
4878         return 0;
4879 }
4880
4881 static int
4882 igb_timesync_disable(struct rte_eth_dev *dev)
4883 {
4884         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4885         uint32_t tsync_ctl;
4886
4887         /* Disable timestamping of transmitted PTP packets. */
4888         tsync_ctl = E1000_READ_REG(hw, E1000_TSYNCTXCTL);
4889         tsync_ctl &= ~E1000_TSYNCTXCTL_ENABLED;
4890         E1000_WRITE_REG(hw, E1000_TSYNCTXCTL, tsync_ctl);
4891
4892         /* Disable timestamping of received PTP packets. */
4893         tsync_ctl = E1000_READ_REG(hw, E1000_TSYNCRXCTL);
4894         tsync_ctl &= ~E1000_TSYNCRXCTL_ENABLED;
4895         E1000_WRITE_REG(hw, E1000_TSYNCRXCTL, tsync_ctl);
4896
4897         /* Disable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
4898         E1000_WRITE_REG(hw, E1000_ETQF(E1000_ETQF_FILTER_1588), 0);
4899
4900         /* Stop incrementating the System Time registers. */
4901         E1000_WRITE_REG(hw, E1000_TIMINCA, 0);
4902
4903         return 0;
4904 }
4905
4906 static int
4907 igb_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
4908                                struct timespec *timestamp,
4909                                uint32_t flags __rte_unused)
4910 {
4911         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4912         struct e1000_adapter *adapter =
4913                         (struct e1000_adapter *)dev->data->dev_private;
4914         uint32_t tsync_rxctl;
4915         uint64_t rx_tstamp_cycles;
4916         uint64_t ns;
4917
4918         tsync_rxctl = E1000_READ_REG(hw, E1000_TSYNCRXCTL);
4919         if ((tsync_rxctl & E1000_TSYNCRXCTL_VALID) == 0)
4920                 return -EINVAL;
4921
4922         rx_tstamp_cycles = igb_read_rx_tstamp_cyclecounter(dev);
4923         ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles);
4924         *timestamp = rte_ns_to_timespec(ns);
4925
4926         return  0;
4927 }
4928
4929 static int
4930 igb_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
4931                                struct timespec *timestamp)
4932 {
4933         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4934         struct e1000_adapter *adapter =
4935                         (struct e1000_adapter *)dev->data->dev_private;
4936         uint32_t tsync_txctl;
4937         uint64_t tx_tstamp_cycles;
4938         uint64_t ns;
4939
4940         tsync_txctl = E1000_READ_REG(hw, E1000_TSYNCTXCTL);
4941         if ((tsync_txctl & E1000_TSYNCTXCTL_VALID) == 0)
4942                 return -EINVAL;
4943
4944         tx_tstamp_cycles = igb_read_tx_tstamp_cyclecounter(dev);
4945         ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles);
4946         *timestamp = rte_ns_to_timespec(ns);
4947
4948         return  0;
4949 }
4950
4951 static int
4952 eth_igb_get_reg_length(struct rte_eth_dev *dev __rte_unused)
4953 {
4954         int count = 0;
4955         int g_ind = 0;
4956         const struct reg_info *reg_group;
4957
4958         while ((reg_group = igb_regs[g_ind++]))
4959                 count += igb_reg_group_count(reg_group);
4960
4961         return count;
4962 }
4963
4964 static int
4965 igbvf_get_reg_length(struct rte_eth_dev *dev __rte_unused)
4966 {
4967         int count = 0;
4968         int g_ind = 0;
4969         const struct reg_info *reg_group;
4970
4971         while ((reg_group = igbvf_regs[g_ind++]))
4972                 count += igb_reg_group_count(reg_group);
4973
4974         return count;
4975 }
4976
4977 static int
4978 eth_igb_get_regs(struct rte_eth_dev *dev,
4979         struct rte_dev_reg_info *regs)
4980 {
4981         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4982         uint32_t *data = regs->data;
4983         int g_ind = 0;
4984         int count = 0;
4985         const struct reg_info *reg_group;
4986
4987         if (data == NULL) {
4988                 regs->length = eth_igb_get_reg_length(dev);
4989                 regs->width = sizeof(uint32_t);
4990                 return 0;
4991         }
4992
4993         /* Support only full register dump */
4994         if ((regs->length == 0) ||
4995             (regs->length == (uint32_t)eth_igb_get_reg_length(dev))) {
4996                 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
4997                         hw->device_id;
4998                 while ((reg_group = igb_regs[g_ind++]))
4999                         count += igb_read_regs_group(dev, &data[count],
5000                                                         reg_group);
5001                 return 0;
5002         }
5003
5004         return -ENOTSUP;
5005 }
5006
5007 static int
5008 igbvf_get_regs(struct rte_eth_dev *dev,
5009         struct rte_dev_reg_info *regs)
5010 {
5011         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5012         uint32_t *data = regs->data;
5013         int g_ind = 0;
5014         int count = 0;
5015         const struct reg_info *reg_group;
5016
5017         if (data == NULL) {
5018                 regs->length = igbvf_get_reg_length(dev);
5019                 regs->width = sizeof(uint32_t);
5020                 return 0;
5021         }
5022
5023         /* Support only full register dump */
5024         if ((regs->length == 0) ||
5025             (regs->length == (uint32_t)igbvf_get_reg_length(dev))) {
5026                 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
5027                         hw->device_id;
5028                 while ((reg_group = igbvf_regs[g_ind++]))
5029                         count += igb_read_regs_group(dev, &data[count],
5030                                                         reg_group);
5031                 return 0;
5032         }
5033
5034         return -ENOTSUP;
5035 }
5036
5037 static int
5038 eth_igb_get_eeprom_length(struct rte_eth_dev *dev)
5039 {
5040         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5041
5042         /* Return unit is byte count */
5043         return hw->nvm.word_size * 2;
5044 }
5045
5046 static int
5047 eth_igb_get_eeprom(struct rte_eth_dev *dev,
5048         struct rte_dev_eeprom_info *in_eeprom)
5049 {
5050         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5051         struct e1000_nvm_info *nvm = &hw->nvm;
5052         uint16_t *data = in_eeprom->data;
5053         int first, length;
5054
5055         first = in_eeprom->offset >> 1;
5056         length = in_eeprom->length >> 1;
5057         if ((first >= hw->nvm.word_size) ||
5058             ((first + length) >= hw->nvm.word_size))
5059                 return -EINVAL;
5060
5061         in_eeprom->magic = hw->vendor_id |
5062                 ((uint32_t)hw->device_id << 16);
5063
5064         if ((nvm->ops.read) == NULL)
5065                 return -ENOTSUP;
5066
5067         return nvm->ops.read(hw, first, length, data);
5068 }
5069
5070 static int
5071 eth_igb_set_eeprom(struct rte_eth_dev *dev,
5072         struct rte_dev_eeprom_info *in_eeprom)
5073 {
5074         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5075         struct e1000_nvm_info *nvm = &hw->nvm;
5076         uint16_t *data = in_eeprom->data;
5077         int first, length;
5078
5079         first = in_eeprom->offset >> 1;
5080         length = in_eeprom->length >> 1;
5081         if ((first >= hw->nvm.word_size) ||
5082             ((first + length) >= hw->nvm.word_size))
5083                 return -EINVAL;
5084
5085         in_eeprom->magic = (uint32_t)hw->vendor_id |
5086                 ((uint32_t)hw->device_id << 16);
5087
5088         if ((nvm->ops.write) == NULL)
5089                 return -ENOTSUP;
5090         return nvm->ops.write(hw,  first, length, data);
5091 }
5092
5093 static int
5094 eth_igb_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
5095 {
5096         struct e1000_hw *hw =
5097                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5098         uint32_t mask = 1 << queue_id;
5099
5100         E1000_WRITE_REG(hw, E1000_EIMC, mask);
5101         E1000_WRITE_FLUSH(hw);
5102
5103         return 0;
5104 }
5105
5106 static int
5107 eth_igb_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
5108 {
5109         struct e1000_hw *hw =
5110                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5111         uint32_t mask = 1 << queue_id;
5112         uint32_t regval;
5113
5114         regval = E1000_READ_REG(hw, E1000_EIMS);
5115         E1000_WRITE_REG(hw, E1000_EIMS, regval | mask);
5116         E1000_WRITE_FLUSH(hw);
5117
5118         rte_intr_enable(&dev->pci_dev->intr_handle);
5119
5120         return 0;
5121 }
5122
5123 static void
5124 eth_igb_write_ivar(struct e1000_hw *hw, uint8_t  msix_vector,
5125                    uint8_t index, uint8_t offset)
5126 {
5127         uint32_t val = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index);
5128
5129         /* clear bits */
5130         val &= ~((uint32_t)0xFF << offset);
5131
5132         /* write vector and valid bit */
5133         val |= (msix_vector | E1000_IVAR_VALID) << offset;
5134
5135         E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, val);
5136 }
5137
5138 static void
5139 eth_igb_assign_msix_vector(struct e1000_hw *hw, int8_t direction,
5140                            uint8_t queue, uint8_t msix_vector)
5141 {
5142         uint32_t tmp = 0;
5143
5144         if (hw->mac.type == e1000_82575) {
5145                 if (direction == 0)
5146                         tmp = E1000_EICR_RX_QUEUE0 << queue;
5147                 else if (direction == 1)
5148                         tmp = E1000_EICR_TX_QUEUE0 << queue;
5149                 E1000_WRITE_REG(hw, E1000_MSIXBM(msix_vector), tmp);
5150         } else if (hw->mac.type == e1000_82576) {
5151                 if ((direction == 0) || (direction == 1))
5152                         eth_igb_write_ivar(hw, msix_vector, queue & 0x7,
5153                                            ((queue & 0x8) << 1) +
5154                                            8 * direction);
5155         } else if ((hw->mac.type == e1000_82580) ||
5156                         (hw->mac.type == e1000_i350) ||
5157                         (hw->mac.type == e1000_i354) ||
5158                         (hw->mac.type == e1000_i210) ||
5159                         (hw->mac.type == e1000_i211)) {
5160                 if ((direction == 0) || (direction == 1))
5161                         eth_igb_write_ivar(hw, msix_vector,
5162                                            queue >> 1,
5163                                            ((queue & 0x1) << 4) +
5164                                            8 * direction);
5165         }
5166 }
5167
5168 /* Sets up the hardware to generate MSI-X interrupts properly
5169  * @hw
5170  *  board private structure
5171  */
5172 static void
5173 eth_igb_configure_msix_intr(struct rte_eth_dev *dev)
5174 {
5175         int queue_id;
5176         uint32_t tmpval, regval, intr_mask;
5177         struct e1000_hw *hw =
5178                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5179         uint32_t vec = E1000_MISC_VEC_ID;
5180         uint32_t base = E1000_MISC_VEC_ID;
5181         uint32_t misc_shift = 0;
5182
5183         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
5184
5185         /* won't configure msix register if no mapping is done
5186          * between intr vector and event fd
5187          */
5188         if (!rte_intr_dp_is_en(intr_handle))
5189                 return;
5190
5191         if (rte_intr_allow_others(intr_handle)) {
5192                 vec = base = E1000_RX_VEC_START;
5193                 misc_shift = 1;
5194         }
5195
5196         /* set interrupt vector for other causes */
5197         if (hw->mac.type == e1000_82575) {
5198                 tmpval = E1000_READ_REG(hw, E1000_CTRL_EXT);
5199                 /* enable MSI-X PBA support */
5200                 tmpval |= E1000_CTRL_EXT_PBA_CLR;
5201
5202                 /* Auto-Mask interrupts upon ICR read */
5203                 tmpval |= E1000_CTRL_EXT_EIAME;
5204                 tmpval |= E1000_CTRL_EXT_IRCA;
5205
5206                 E1000_WRITE_REG(hw, E1000_CTRL_EXT, tmpval);
5207
5208                 /* enable msix_other interrupt */
5209                 E1000_WRITE_REG_ARRAY(hw, E1000_MSIXBM(0), 0, E1000_EIMS_OTHER);
5210                 regval = E1000_READ_REG(hw, E1000_EIAC);
5211                 E1000_WRITE_REG(hw, E1000_EIAC, regval | E1000_EIMS_OTHER);
5212                 regval = E1000_READ_REG(hw, E1000_EIAM);
5213                 E1000_WRITE_REG(hw, E1000_EIMS, regval | E1000_EIMS_OTHER);
5214         } else if ((hw->mac.type == e1000_82576) ||
5215                         (hw->mac.type == e1000_82580) ||
5216                         (hw->mac.type == e1000_i350) ||
5217                         (hw->mac.type == e1000_i354) ||
5218                         (hw->mac.type == e1000_i210) ||
5219                         (hw->mac.type == e1000_i211)) {
5220                 /* turn on MSI-X capability first */
5221                 E1000_WRITE_REG(hw, E1000_GPIE, E1000_GPIE_MSIX_MODE |
5222                                         E1000_GPIE_PBA | E1000_GPIE_EIAME |
5223                                         E1000_GPIE_NSICR);
5224                 intr_mask = RTE_LEN2MASK(intr_handle->nb_efd, uint32_t) <<
5225                         misc_shift;
5226                 regval = E1000_READ_REG(hw, E1000_EIAC);
5227                 E1000_WRITE_REG(hw, E1000_EIAC, regval | intr_mask);
5228
5229                 /* enable msix_other interrupt */
5230                 regval = E1000_READ_REG(hw, E1000_EIMS);
5231                 E1000_WRITE_REG(hw, E1000_EIMS, regval | intr_mask);
5232                 tmpval = (dev->data->nb_rx_queues | E1000_IVAR_VALID) << 8;
5233                 E1000_WRITE_REG(hw, E1000_IVAR_MISC, tmpval);
5234         }
5235
5236         /* use EIAM to auto-mask when MSI-X interrupt
5237          * is asserted, this saves a register write for every interrupt
5238          */
5239         intr_mask = RTE_LEN2MASK(intr_handle->nb_efd, uint32_t) <<
5240                 misc_shift;
5241         regval = E1000_READ_REG(hw, E1000_EIAM);
5242         E1000_WRITE_REG(hw, E1000_EIAM, regval | intr_mask);
5243
5244         for (queue_id = 0; queue_id < dev->data->nb_rx_queues; queue_id++) {
5245                 eth_igb_assign_msix_vector(hw, 0, queue_id, vec);
5246                 intr_handle->intr_vec[queue_id] = vec;
5247                 if (vec < base + intr_handle->nb_efd - 1)
5248                         vec++;
5249         }
5250
5251         E1000_WRITE_FLUSH(hw);
5252 }
5253
5254 RTE_PMD_REGISTER_PCI(net_e1000_igb, rte_igb_pmd.pci_drv);
5255 RTE_PMD_REGISTER_PCI_TABLE(net_e1000_igb, pci_id_igb_map);
5256 RTE_PMD_REGISTER_PCI(net_e1000_igb_vf, rte_igbvf_pmd.pci_drv);
5257 RTE_PMD_REGISTER_PCI_TABLE(net_e1000_igb_vf, pci_id_igbvf_map);