drivers/net/e1000/igb_ethdev.c

   1 /*-
   2  *   BSD LICENSE
   3  *
   4  *   Copyright(c) 2010-2016 Intel Corporation. All rights reserved.
   5  *   All rights reserved.
   6  *
   7  *   Redistribution and use in source and binary forms, with or without
   8  *   modification, are permitted provided that the following conditions
   9  *   are met:
  10  *
  11  *     * Redistributions of source code must retain the above copyright
  12  *       notice, this list of conditions and the following disclaimer.
  13  *     * Redistributions in binary form must reproduce the above copyright
  14  *       notice, this list of conditions and the following disclaimer in
  15  *       the documentation and/or other materials provided with the
  16  *       distribution.
  17  *     * Neither the name of Intel Corporation nor the names of its
  18  *       contributors may be used to endorse or promote products derived
  19  *       from this software without specific prior written permission.
  20  *
  21  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 #include <sys/queue.h>
  35 #include <stdio.h>
  36 #include <errno.h>
  37 #include <stdint.h>
  38 #include <stdarg.h>
  39
  40 #include <rte_common.h>
  41 #include <rte_interrupts.h>
  42 #include <rte_byteorder.h>
  43 #include <rte_log.h>
  44 #include <rte_debug.h>
  45 #include <rte_pci.h>
  46 #include <rte_ether.h>
  47 #include <rte_ethdev.h>
  48 #include <rte_memory.h>
  49 #include <rte_memzone.h>
  50 #include <rte_eal.h>
  51 #include <rte_atomic.h>
  52 #include <rte_malloc.h>
  53 #include <rte_dev.h>
  54
  55 #include "e1000_logs.h"
  56 #include "base/e1000_api.h"
  57 #include "e1000_ethdev.h"
  58 #include "igb_regs.h"
  59
  60 /*
  61  * Default values for port configuration
  62  */
  63 #define IGB_DEFAULT_RX_FREE_THRESH  32
  64
  65 #define IGB_DEFAULT_RX_PTHRESH      ((hw->mac.type == e1000_i354) ? 12 : 8)
  66 #define IGB_DEFAULT_RX_HTHRESH      8
  67 #define IGB_DEFAULT_RX_WTHRESH      ((hw->mac.type == e1000_82576) ? 1 : 4)
  68
  69 #define IGB_DEFAULT_TX_PTHRESH      ((hw->mac.type == e1000_i354) ? 20 : 8)
  70 #define IGB_DEFAULT_TX_HTHRESH      1
  71 #define IGB_DEFAULT_TX_WTHRESH      ((hw->mac.type == e1000_82576) ? 1 : 16)
  72
  73 #define IGB_HKEY_MAX_INDEX 10
  74
  75 /* Bit shift and mask */
  76 #define IGB_4_BIT_WIDTH  (CHAR_BIT / 2)
  77 #define IGB_4_BIT_MASK   RTE_LEN2MASK(IGB_4_BIT_WIDTH, uint8_t)
  78 #define IGB_8_BIT_WIDTH  CHAR_BIT
  79 #define IGB_8_BIT_MASK   UINT8_MAX
  80
  81 /* Additional timesync values. */
  82 #define E1000_CYCLECOUNTER_MASK      0xffffffffffffffffULL
  83 #define E1000_ETQF_FILTER_1588       3
  84 #define IGB_82576_TSYNC_SHIFT        16
  85 #define E1000_INCPERIOD_82576        (1 << E1000_TIMINCA_16NS_SHIFT)
  86 #define E1000_INCVALUE_82576         (16 << IGB_82576_TSYNC_SHIFT)
  87 #define E1000_TSAUXC_DISABLE_SYSTIME 0x80000000
  88
  89 static int  eth_igb_configure(struct rte_eth_dev *dev);
  90 static int  eth_igb_start(struct rte_eth_dev *dev);
  91 static void eth_igb_stop(struct rte_eth_dev *dev);
  92 static void eth_igb_close(struct rte_eth_dev *dev);
  93 static void eth_igb_promiscuous_enable(struct rte_eth_dev *dev);
  94 static void eth_igb_promiscuous_disable(struct rte_eth_dev *dev);
  95 static void eth_igb_allmulticast_enable(struct rte_eth_dev *dev);
  96 static void eth_igb_allmulticast_disable(struct rte_eth_dev *dev);
  97 static int  eth_igb_link_update(struct rte_eth_dev *dev,
  98                                 int wait_to_complete);
  99 static void eth_igb_stats_get(struct rte_eth_dev *dev,
 100                                 struct rte_eth_stats *rte_stats);
 101 static int eth_igb_xstats_get(struct rte_eth_dev *dev,
 102                               struct rte_eth_xstats *xstats, unsigned n);
 103 static void eth_igb_stats_reset(struct rte_eth_dev *dev);
 104 static void eth_igb_xstats_reset(struct rte_eth_dev *dev);
 105 static void eth_igb_infos_get(struct rte_eth_dev *dev,
 106                               struct rte_eth_dev_info *dev_info);
 107 static const uint32_t *eth_igb_supported_ptypes_get(struct rte_eth_dev *dev);
 108 static void eth_igbvf_infos_get(struct rte_eth_dev *dev,
 109                                 struct rte_eth_dev_info *dev_info);
 110 static int  eth_igb_flow_ctrl_get(struct rte_eth_dev *dev,
 111                                 struct rte_eth_fc_conf *fc_conf);
 112 static int  eth_igb_flow_ctrl_set(struct rte_eth_dev *dev,
 113                                 struct rte_eth_fc_conf *fc_conf);
 114 static int eth_igb_lsc_interrupt_setup(struct rte_eth_dev *dev);
 115 static int eth_igb_rxq_interrupt_setup(struct rte_eth_dev *dev);
 116 static int eth_igb_interrupt_get_status(struct rte_eth_dev *dev);
 117 static int eth_igb_interrupt_action(struct rte_eth_dev *dev);
 118 static void eth_igb_interrupt_handler(struct rte_intr_handle *handle,
 119                                                         void *param);
 120 static int  igb_hardware_init(struct e1000_hw *hw);
 121 static void igb_hw_control_acquire(struct e1000_hw *hw);
 122 static void igb_hw_control_release(struct e1000_hw *hw);
 123 static void igb_init_manageability(struct e1000_hw *hw);
 124 static void igb_release_manageability(struct e1000_hw *hw);
 125
 126 static int  eth_igb_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
 127
 128 static int eth_igb_vlan_filter_set(struct rte_eth_dev *dev,
 129                 uint16_t vlan_id, int on);
 130 static int eth_igb_vlan_tpid_set(struct rte_eth_dev *dev,
 131                                  enum rte_vlan_type vlan_type,
 132                                  uint16_t tpid_id);
 133 static void eth_igb_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 134
 135 static void igb_vlan_hw_filter_enable(struct rte_eth_dev *dev);
 136 static void igb_vlan_hw_filter_disable(struct rte_eth_dev *dev);
 137 static void igb_vlan_hw_strip_enable(struct rte_eth_dev *dev);
 138 static void igb_vlan_hw_strip_disable(struct rte_eth_dev *dev);
 139 static void igb_vlan_hw_extend_enable(struct rte_eth_dev *dev);
 140 static void igb_vlan_hw_extend_disable(struct rte_eth_dev *dev);
 141
 142 static int eth_igb_led_on(struct rte_eth_dev *dev);
 143 static int eth_igb_led_off(struct rte_eth_dev *dev);
 144
 145 static void igb_intr_disable(struct e1000_hw *hw);
 146 static int  igb_get_rx_buffer_size(struct e1000_hw *hw);
 147 static void eth_igb_rar_set(struct rte_eth_dev *dev,
 148                 struct ether_addr *mac_addr,
 149                 uint32_t index, uint32_t pool);
 150 static void eth_igb_rar_clear(struct rte_eth_dev *dev, uint32_t index);
 151 static void eth_igb_default_mac_addr_set(struct rte_eth_dev *dev,
 152                 struct ether_addr *addr);
 153
 154 static void igbvf_intr_disable(struct e1000_hw *hw);
 155 static int igbvf_dev_configure(struct rte_eth_dev *dev);
 156 static int igbvf_dev_start(struct rte_eth_dev *dev);
 157 static void igbvf_dev_stop(struct rte_eth_dev *dev);
 158 static void igbvf_dev_close(struct rte_eth_dev *dev);
 159 static void igbvf_promiscuous_enable(struct rte_eth_dev *dev);
 160 static void igbvf_promiscuous_disable(struct rte_eth_dev *dev);
 161 static void igbvf_allmulticast_enable(struct rte_eth_dev *dev);
 162 static void igbvf_allmulticast_disable(struct rte_eth_dev *dev);
 163 static int eth_igbvf_link_update(struct e1000_hw *hw);
 164 static void eth_igbvf_stats_get(struct rte_eth_dev *dev,
 165                                 struct rte_eth_stats *rte_stats);
 166 static int eth_igbvf_xstats_get(struct rte_eth_dev *dev,
 167                                 struct rte_eth_xstats *xstats, unsigned n);
 168 static void eth_igbvf_stats_reset(struct rte_eth_dev *dev);
 169 static int igbvf_vlan_filter_set(struct rte_eth_dev *dev,
 170                 uint16_t vlan_id, int on);
 171 static int igbvf_set_vfta(struct e1000_hw *hw, uint16_t vid, bool on);
 172 static void igbvf_set_vfta_all(struct rte_eth_dev *dev, bool on);
 173 static void igbvf_default_mac_addr_set(struct rte_eth_dev *dev,
 174                 struct ether_addr *addr);
 175 static int igbvf_get_reg_length(struct rte_eth_dev *dev);
 176 static int igbvf_get_regs(struct rte_eth_dev *dev,
 177                 struct rte_dev_reg_info *regs);
 178
 179 static int eth_igb_rss_reta_update(struct rte_eth_dev *dev,
 180                                    struct rte_eth_rss_reta_entry64 *reta_conf,
 181                                    uint16_t reta_size);
 182 static int eth_igb_rss_reta_query(struct rte_eth_dev *dev,
 183                                   struct rte_eth_rss_reta_entry64 *reta_conf,
 184                                   uint16_t reta_size);
 185
 186 static int eth_igb_syn_filter_set(struct rte_eth_dev *dev,
 187                         struct rte_eth_syn_filter *filter,
 188                         bool add);
 189 static int eth_igb_syn_filter_get(struct rte_eth_dev *dev,
 190                         struct rte_eth_syn_filter *filter);
 191 static int eth_igb_syn_filter_handle(struct rte_eth_dev *dev,
 192                         enum rte_filter_op filter_op,
 193                         void *arg);
 194 static int igb_add_2tuple_filter(struct rte_eth_dev *dev,
 195                         struct rte_eth_ntuple_filter *ntuple_filter);
 196 static int igb_remove_2tuple_filter(struct rte_eth_dev *dev,
 197                         struct rte_eth_ntuple_filter *ntuple_filter);
 198 static int eth_igb_add_del_flex_filter(struct rte_eth_dev *dev,
 199                         struct rte_eth_flex_filter *filter,
 200                         bool add);
 201 static int eth_igb_get_flex_filter(struct rte_eth_dev *dev,
 202                         struct rte_eth_flex_filter *filter);
 203 static int eth_igb_flex_filter_handle(struct rte_eth_dev *dev,
 204                         enum rte_filter_op filter_op,
 205                         void *arg);
 206 static int igb_add_5tuple_filter_82576(struct rte_eth_dev *dev,
 207                         struct rte_eth_ntuple_filter *ntuple_filter);
 208 static int igb_remove_5tuple_filter_82576(struct rte_eth_dev *dev,
 209                         struct rte_eth_ntuple_filter *ntuple_filter);
 210 static int igb_add_del_ntuple_filter(struct rte_eth_dev *dev,
 211                         struct rte_eth_ntuple_filter *filter,
 212                         bool add);
 213 static int igb_get_ntuple_filter(struct rte_eth_dev *dev,
 214                         struct rte_eth_ntuple_filter *filter);
 215 static int igb_ntuple_filter_handle(struct rte_eth_dev *dev,
 216                                 enum rte_filter_op filter_op,
 217                                 void *arg);
 218 static int igb_add_del_ethertype_filter(struct rte_eth_dev *dev,
 219                         struct rte_eth_ethertype_filter *filter,
 220                         bool add);
 221 static int igb_ethertype_filter_handle(struct rte_eth_dev *dev,
 222                                 enum rte_filter_op filter_op,
 223                                 void *arg);
 224 static int igb_get_ethertype_filter(struct rte_eth_dev *dev,
 225                         struct rte_eth_ethertype_filter *filter);
 226 static int eth_igb_filter_ctrl(struct rte_eth_dev *dev,
 227                      enum rte_filter_type filter_type,
 228                      enum rte_filter_op filter_op,
 229                      void *arg);
 230 static int eth_igb_get_reg_length(struct rte_eth_dev *dev);
 231 static int eth_igb_get_regs(struct rte_eth_dev *dev,
 232                 struct rte_dev_reg_info *regs);
 233 static int eth_igb_get_eeprom_length(struct rte_eth_dev *dev);
 234 static int eth_igb_get_eeprom(struct rte_eth_dev *dev,
 235                 struct rte_dev_eeprom_info *eeprom);
 236 static int eth_igb_set_eeprom(struct rte_eth_dev *dev,
 237                 struct rte_dev_eeprom_info *eeprom);
 238 static int eth_igb_set_mc_addr_list(struct rte_eth_dev *dev,
 239                                     struct ether_addr *mc_addr_set,
 240                                     uint32_t nb_mc_addr);
 241 static int igb_timesync_enable(struct rte_eth_dev *dev);
 242 static int igb_timesync_disable(struct rte_eth_dev *dev);
 243 static int igb_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
 244                                           struct timespec *timestamp,
 245                                           uint32_t flags);
 246 static int igb_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
 247                                           struct timespec *timestamp);
 248 static int igb_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);
 249 static int igb_timesync_read_time(struct rte_eth_dev *dev,
 250                                   struct timespec *timestamp);
 251 static int igb_timesync_write_time(struct rte_eth_dev *dev,
 252                                    const struct timespec *timestamp);
 253 static int eth_igb_rx_queue_intr_enable(struct rte_eth_dev *dev,
 254                                         uint16_t queue_id);
 255 static int eth_igb_rx_queue_intr_disable(struct rte_eth_dev *dev,
 256                                          uint16_t queue_id);
 257 static void eth_igb_assign_msix_vector(struct e1000_hw *hw, int8_t direction,
 258                                        uint8_t queue, uint8_t msix_vector);
 259 static void eth_igb_write_ivar(struct e1000_hw *hw, uint8_t msix_vector,
 260                                uint8_t index, uint8_t offset);
 261 static void eth_igb_configure_msix_intr(struct rte_eth_dev *dev);
 262
 263 /*
 264  * Define VF Stats MACRO for Non "cleared on read" register
 265  */
 266 #define UPDATE_VF_STAT(reg, last, cur)            \
 267 {                                                 \
 268         u32 latest = E1000_READ_REG(hw, reg);     \
 269         cur += (latest - last) & UINT_MAX;        \
 270         last = latest;                            \
 271 }
 272
 273 #define IGB_FC_PAUSE_TIME 0x0680
 274 #define IGB_LINK_UPDATE_CHECK_TIMEOUT  90  /* 9s */
 275 #define IGB_LINK_UPDATE_CHECK_INTERVAL 100 /* ms */
 276
 277 #define IGBVF_PMD_NAME "rte_igbvf_pmd"     /* PMD name */
 278
 279 static enum e1000_fc_mode igb_fc_setting = e1000_fc_full;
 280
 281 /*
 282  * The set of PCI devices this driver supports
 283  */
 284 static const struct rte_pci_id pci_id_igb_map[] = {
 285
 286 #define RTE_PCI_DEV_ID_DECL_IGB(vend, dev) {RTE_PCI_DEVICE(vend, dev)},
 287 #include "rte_pci_dev_ids.h"
 288
 289 {0},
 290 };
 291
 292 /*
 293  * The set of PCI devices this driver supports (for 82576&I350 VF)
 294  */
 295 static const struct rte_pci_id pci_id_igbvf_map[] = {
 296
 297 #define RTE_PCI_DEV_ID_DECL_IGBVF(vend, dev) {RTE_PCI_DEVICE(vend, dev)},
 298 #include "rte_pci_dev_ids.h"
 299
 300 {0},
 301 };
 302
 303 static const struct rte_eth_desc_lim rx_desc_lim = {
 304         .nb_max = E1000_MAX_RING_DESC,
 305         .nb_min = E1000_MIN_RING_DESC,
 306         .nb_align = IGB_RXD_ALIGN,
 307 };
 308
 309 static const struct rte_eth_desc_lim tx_desc_lim = {
 310         .nb_max = E1000_MAX_RING_DESC,
 311         .nb_min = E1000_MIN_RING_DESC,
 312         .nb_align = IGB_RXD_ALIGN,
 313 };
 314
 315 static const struct eth_dev_ops eth_igb_ops = {
 316         .dev_configure        = eth_igb_configure,
 317         .dev_start            = eth_igb_start,
 318         .dev_stop             = eth_igb_stop,
 319         .dev_close            = eth_igb_close,
 320         .promiscuous_enable   = eth_igb_promiscuous_enable,
 321         .promiscuous_disable  = eth_igb_promiscuous_disable,
 322         .allmulticast_enable  = eth_igb_allmulticast_enable,
 323         .allmulticast_disable = eth_igb_allmulticast_disable,
 324         .link_update          = eth_igb_link_update,
 325         .stats_get            = eth_igb_stats_get,
 326         .xstats_get           = eth_igb_xstats_get,
 327         .stats_reset          = eth_igb_stats_reset,
 328         .xstats_reset         = eth_igb_xstats_reset,
 329         .dev_infos_get        = eth_igb_infos_get,
 330         .dev_supported_ptypes_get = eth_igb_supported_ptypes_get,
 331         .mtu_set              = eth_igb_mtu_set,
 332         .vlan_filter_set      = eth_igb_vlan_filter_set,
 333         .vlan_tpid_set        = eth_igb_vlan_tpid_set,
 334         .vlan_offload_set     = eth_igb_vlan_offload_set,
 335         .rx_queue_setup       = eth_igb_rx_queue_setup,
 336         .rx_queue_intr_enable = eth_igb_rx_queue_intr_enable,
 337         .rx_queue_intr_disable = eth_igb_rx_queue_intr_disable,
 338         .rx_queue_release     = eth_igb_rx_queue_release,
 339         .rx_queue_count       = eth_igb_rx_queue_count,
 340         .rx_descriptor_done   = eth_igb_rx_descriptor_done,
 341         .tx_queue_setup       = eth_igb_tx_queue_setup,
 342         .tx_queue_release     = eth_igb_tx_queue_release,
 343         .dev_led_on           = eth_igb_led_on,
 344         .dev_led_off          = eth_igb_led_off,
 345         .flow_ctrl_get        = eth_igb_flow_ctrl_get,
 346         .flow_ctrl_set        = eth_igb_flow_ctrl_set,
 347         .mac_addr_add         = eth_igb_rar_set,
 348         .mac_addr_remove      = eth_igb_rar_clear,
 349         .mac_addr_set         = eth_igb_default_mac_addr_set,
 350         .reta_update          = eth_igb_rss_reta_update,
 351         .reta_query           = eth_igb_rss_reta_query,
 352         .rss_hash_update      = eth_igb_rss_hash_update,
 353         .rss_hash_conf_get    = eth_igb_rss_hash_conf_get,
 354         .filter_ctrl          = eth_igb_filter_ctrl,
 355         .set_mc_addr_list     = eth_igb_set_mc_addr_list,
 356         .rxq_info_get         = igb_rxq_info_get,
 357         .txq_info_get         = igb_txq_info_get,
 358         .timesync_enable      = igb_timesync_enable,
 359         .timesync_disable     = igb_timesync_disable,
 360         .timesync_read_rx_timestamp = igb_timesync_read_rx_timestamp,
 361         .timesync_read_tx_timestamp = igb_timesync_read_tx_timestamp,
 362         .get_reg_length       = eth_igb_get_reg_length,
 363         .get_reg              = eth_igb_get_regs,
 364         .get_eeprom_length    = eth_igb_get_eeprom_length,
 365         .get_eeprom           = eth_igb_get_eeprom,
 366         .set_eeprom           = eth_igb_set_eeprom,
 367         .timesync_adjust_time = igb_timesync_adjust_time,
 368         .timesync_read_time   = igb_timesync_read_time,
 369         .timesync_write_time  = igb_timesync_write_time,
 370 };
 371
 372 /*
 373  * dev_ops for virtual function, bare necessities for basic vf
 374  * operation have been implemented
 375  */
 376 static const struct eth_dev_ops igbvf_eth_dev_ops = {
 377         .dev_configure        = igbvf_dev_configure,
 378         .dev_start            = igbvf_dev_start,
 379         .dev_stop             = igbvf_dev_stop,
 380         .dev_close            = igbvf_dev_close,
 381         .promiscuous_enable   = igbvf_promiscuous_enable,
 382         .promiscuous_disable  = igbvf_promiscuous_disable,
 383         .allmulticast_enable  = igbvf_allmulticast_enable,
 384         .allmulticast_disable = igbvf_allmulticast_disable,
 385         .link_update          = eth_igb_link_update,
 386         .stats_get            = eth_igbvf_stats_get,
 387         .xstats_get           = eth_igbvf_xstats_get,
 388         .stats_reset          = eth_igbvf_stats_reset,
 389         .xstats_reset         = eth_igbvf_stats_reset,
 390         .vlan_filter_set      = igbvf_vlan_filter_set,
 391         .dev_infos_get        = eth_igbvf_infos_get,
 392         .dev_supported_ptypes_get = eth_igb_supported_ptypes_get,
 393         .rx_queue_setup       = eth_igb_rx_queue_setup,
 394         .rx_queue_release     = eth_igb_rx_queue_release,
 395         .tx_queue_setup       = eth_igb_tx_queue_setup,
 396         .tx_queue_release     = eth_igb_tx_queue_release,
 397         .set_mc_addr_list     = eth_igb_set_mc_addr_list,
 398         .rxq_info_get         = igb_rxq_info_get,
 399         .txq_info_get         = igb_txq_info_get,
 400         .mac_addr_set         = igbvf_default_mac_addr_set,
 401         .get_reg_length       = igbvf_get_reg_length,
 402         .get_reg              = igbvf_get_regs,
 403 };
 404
 405 /* store statistics names and its offset in stats structure */
 406 struct rte_igb_xstats_name_off {
 407         char name[RTE_ETH_XSTATS_NAME_SIZE];
 408         unsigned offset;
 409 };
 410
 411 static const struct rte_igb_xstats_name_off rte_igb_stats_strings[] = {
 412         {"rx_crc_errors", offsetof(struct e1000_hw_stats, crcerrs)},
 413         {"rx_align_errors", offsetof(struct e1000_hw_stats, algnerrc)},
 414         {"rx_symbol_errors", offsetof(struct e1000_hw_stats, symerrs)},
 415         {"rx_missed_packets", offsetof(struct e1000_hw_stats, mpc)},
 416         {"tx_single_collision_packets", offsetof(struct e1000_hw_stats, scc)},
 417         {"tx_multiple_collision_packets", offsetof(struct e1000_hw_stats, mcc)},
 418         {"tx_excessive_collision_packets", offsetof(struct e1000_hw_stats,
 419                 ecol)},
 420         {"tx_late_collisions", offsetof(struct e1000_hw_stats, latecol)},
 421         {"tx_total_collisions", offsetof(struct e1000_hw_stats, colc)},
 422         {"tx_deferred_packets", offsetof(struct e1000_hw_stats, dc)},
 423         {"tx_no_carrier_sense_packets", offsetof(struct e1000_hw_stats, tncrs)},
 424         {"rx_carrier_ext_errors", offsetof(struct e1000_hw_stats, cexterr)},
 425         {"rx_length_errors", offsetof(struct e1000_hw_stats, rlec)},
 426         {"rx_xon_packets", offsetof(struct e1000_hw_stats, xonrxc)},
 427         {"tx_xon_packets", offsetof(struct e1000_hw_stats, xontxc)},
 428         {"rx_xoff_packets", offsetof(struct e1000_hw_stats, xoffrxc)},
 429         {"tx_xoff_packets", offsetof(struct e1000_hw_stats, xofftxc)},
 430         {"rx_flow_control_unsupported_packets", offsetof(struct e1000_hw_stats,
 431                 fcruc)},
 432         {"rx_size_64_packets", offsetof(struct e1000_hw_stats, prc64)},
 433         {"rx_size_65_to_127_packets", offsetof(struct e1000_hw_stats, prc127)},
 434         {"rx_size_128_to_255_packets", offsetof(struct e1000_hw_stats, prc255)},
 435         {"rx_size_256_to_511_packets", offsetof(struct e1000_hw_stats, prc511)},
 436         {"rx_size_512_to_1023_packets", offsetof(struct e1000_hw_stats,
 437                 prc1023)},
 438         {"rx_size_1024_to_max_packets", offsetof(struct e1000_hw_stats,
 439                 prc1522)},
 440         {"rx_broadcast_packets", offsetof(struct e1000_hw_stats, bprc)},
 441         {"rx_multicast_packets", offsetof(struct e1000_hw_stats, mprc)},
 442         {"rx_undersize_errors", offsetof(struct e1000_hw_stats, ruc)},
 443         {"rx_fragment_errors", offsetof(struct e1000_hw_stats, rfc)},
 444         {"rx_oversize_errors", offsetof(struct e1000_hw_stats, roc)},
 445         {"rx_jabber_errors", offsetof(struct e1000_hw_stats, rjc)},
 446         {"rx_management_packets", offsetof(struct e1000_hw_stats, mgprc)},
 447         {"rx_management_dropped", offsetof(struct e1000_hw_stats, mgpdc)},
 448         {"tx_management_packets", offsetof(struct e1000_hw_stats, mgptc)},
 449         {"rx_total_packets", offsetof(struct e1000_hw_stats, tpr)},
 450         {"tx_total_packets", offsetof(struct e1000_hw_stats, tpt)},
 451         {"rx_total_bytes", offsetof(struct e1000_hw_stats, tor)},
 452         {"tx_total_bytes", offsetof(struct e1000_hw_stats, tot)},
 453         {"tx_size_64_packets", offsetof(struct e1000_hw_stats, ptc64)},
 454         {"tx_size_65_to_127_packets", offsetof(struct e1000_hw_stats, ptc127)},
 455         {"tx_size_128_to_255_packets", offsetof(struct e1000_hw_stats, ptc255)},
 456         {"tx_size_256_to_511_packets", offsetof(struct e1000_hw_stats, ptc511)},
 457         {"tx_size_512_to_1023_packets", offsetof(struct e1000_hw_stats,
 458                 ptc1023)},
 459         {"tx_size_1023_to_max_packets", offsetof(struct e1000_hw_stats,
 460                 ptc1522)},
 461         {"tx_multicast_packets", offsetof(struct e1000_hw_stats, mptc)},
 462         {"tx_broadcast_packets", offsetof(struct e1000_hw_stats, bptc)},
 463         {"tx_tso_packets", offsetof(struct e1000_hw_stats, tsctc)},
 464         {"tx_tso_errors", offsetof(struct e1000_hw_stats, tsctfc)},
 465         {"rx_sent_to_host_packets", offsetof(struct e1000_hw_stats, rpthc)},
 466         {"tx_sent_by_host_packets", offsetof(struct e1000_hw_stats, hgptc)},
 467         {"rx_code_violation_packets", offsetof(struct e1000_hw_stats, scvpc)},
 468
 469         {"interrupt_assert_count", offsetof(struct e1000_hw_stats, iac)},
 470 };
 471
 472 #define IGB_NB_XSTATS (sizeof(rte_igb_stats_strings) / \
 473                 sizeof(rte_igb_stats_strings[0]))
 474
 475 static const struct rte_igb_xstats_name_off rte_igbvf_stats_strings[] = {
 476         {"rx_multicast_packets", offsetof(struct e1000_vf_stats, mprc)},
 477         {"rx_good_loopback_packets", offsetof(struct e1000_vf_stats, gprlbc)},
 478         {"tx_good_loopback_packets", offsetof(struct e1000_vf_stats, gptlbc)},
 479         {"rx_good_loopback_bytes", offsetof(struct e1000_vf_stats, gorlbc)},
 480         {"tx_good_loopback_bytes", offsetof(struct e1000_vf_stats, gotlbc)},
 481 };
 482
 483 #define IGBVF_NB_XSTATS (sizeof(rte_igbvf_stats_strings) / \
 484                 sizeof(rte_igbvf_stats_strings[0]))
 485
 486 /**
 487  * Atomically reads the link status information from global
 488  * structure rte_eth_dev.
 489  *
 490  * @param dev
 491  *   - Pointer to the structure rte_eth_dev to read from.
 492  *   - Pointer to the buffer to be saved with the link status.
 493  *
 494  * @return
 495  *   - On success, zero.
 496  *   - On failure, negative value.
 497  */
 498 static inline int
 499 rte_igb_dev_atomic_read_link_status(struct rte_eth_dev *dev,
 500                                 struct rte_eth_link *link)
 501 {
 502         struct rte_eth_link *dst = link;
 503         struct rte_eth_link *src = &(dev->data->dev_link);
 504
 505         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 506                                         *(uint64_t *)src) == 0)
 507                 return -1;
 508
 509         return 0;
 510 }
 511
 512 /**
 513  * Atomically writes the link status information into global
 514  * structure rte_eth_dev.
 515  *
 516  * @param dev
 517  *   - Pointer to the structure rte_eth_dev to read from.
 518  *   - Pointer to the buffer to be saved with the link status.
 519  *
 520  * @return
 521  *   - On success, zero.
 522  *   - On failure, negative value.
 523  */
 524 static inline int
 525 rte_igb_dev_atomic_write_link_status(struct rte_eth_dev *dev,
 526                                 struct rte_eth_link *link)
 527 {
 528         struct rte_eth_link *dst = &(dev->data->dev_link);
 529         struct rte_eth_link *src = link;
 530
 531         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 532                                         *(uint64_t *)src) == 0)
 533                 return -1;
 534
 535         return 0;
 536 }
 537
 538 static inline void
 539 igb_intr_enable(struct rte_eth_dev *dev)
 540 {
 541         struct e1000_interrupt *intr =
 542                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
 543         struct e1000_hw *hw =
 544                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 545
 546         E1000_WRITE_REG(hw, E1000_IMS, intr->mask);
 547         E1000_WRITE_FLUSH(hw);
 548 }
 549
 550 static void
 551 igb_intr_disable(struct e1000_hw *hw)
 552 {
 553         E1000_WRITE_REG(hw, E1000_IMC, ~0);
 554         E1000_WRITE_FLUSH(hw);
 555 }
 556
 557 static inline int32_t
 558 igb_pf_reset_hw(struct e1000_hw *hw)
 559 {
 560         uint32_t ctrl_ext;
 561         int32_t status;
 562
 563         status = e1000_reset_hw(hw);
 564
 565         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
 566         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
 567         ctrl_ext |= E1000_CTRL_EXT_PFRSTD;
 568         E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
 569         E1000_WRITE_FLUSH(hw);
 570
 571         return status;
 572 }
 573
 574 static void
 575 igb_identify_hardware(struct rte_eth_dev *dev)
 576 {
 577         struct e1000_hw *hw =
 578                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 579
 580         hw->vendor_id = dev->pci_dev->id.vendor_id;
 581         hw->device_id = dev->pci_dev->id.device_id;
 582         hw->subsystem_vendor_id = dev->pci_dev->id.subsystem_vendor_id;
 583         hw->subsystem_device_id = dev->pci_dev->id.subsystem_device_id;
 584
 585         e1000_set_mac_type(hw);
 586
 587         /* need to check if it is a vf device below */
 588 }
 589
 590 static int
 591 igb_reset_swfw_lock(struct e1000_hw *hw)
 592 {
 593         int ret_val;
 594
 595         /*
 596          * Do mac ops initialization manually here, since we will need
 597          * some function pointers set by this call.
 598          */
 599         ret_val = e1000_init_mac_params(hw);
 600         if (ret_val)
 601                 return ret_val;
 602
 603         /*
 604          * SMBI lock should not fail in this early stage. If this is the case,
 605          * it is due to an improper exit of the application.
 606          * So force the release of the faulty lock.
 607          */
 608         if (e1000_get_hw_semaphore_generic(hw) < 0) {
 609                 PMD_DRV_LOG(DEBUG, "SMBI lock released");
 610         }
 611         e1000_put_hw_semaphore_generic(hw);
 612
 613         if (hw->mac.ops.acquire_swfw_sync != NULL) {
 614                 uint16_t mask;
 615
 616                 /*
 617                  * Phy lock should not fail in this early stage. If this is the case,
 618                  * it is due to an improper exit of the application.
 619                  * So force the release of the faulty lock.
 620                  */
 621                 mask = E1000_SWFW_PHY0_SM << hw->bus.func;
 622                 if (hw->bus.func > E1000_FUNC_1)
 623                         mask <<= 2;
 624                 if (hw->mac.ops.acquire_swfw_sync(hw, mask) < 0) {
 625                         PMD_DRV_LOG(DEBUG, "SWFW phy%d lock released",
 626                                     hw->bus.func);
 627                 }
 628                 hw->mac.ops.release_swfw_sync(hw, mask);
 629
 630                 /*
 631                  * This one is more tricky since it is common to all ports; but
 632                  * swfw_sync retries last long enough (1s) to be almost sure that if
 633                  * lock can not be taken it is due to an improper lock of the
 634                  * semaphore.
 635                  */
 636                 mask = E1000_SWFW_EEP_SM;
 637                 if (hw->mac.ops.acquire_swfw_sync(hw, mask) < 0) {
 638                         PMD_DRV_LOG(DEBUG, "SWFW common locks released");
 639                 }
 640                 hw->mac.ops.release_swfw_sync(hw, mask);
 641         }
 642
 643         return E1000_SUCCESS;
 644 }
 645
 646 static int
 647 eth_igb_dev_init(struct rte_eth_dev *eth_dev)
 648 {
 649         int error = 0;
 650         struct rte_pci_device *pci_dev;
 651         struct e1000_hw *hw =
 652                 E1000_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 653         struct e1000_vfta * shadow_vfta =
 654                 E1000_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
 655         struct e1000_filter_info *filter_info =
 656                 E1000_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
 657         struct e1000_adapter *adapter =
 658                 E1000_DEV_PRIVATE(eth_dev->data->dev_private);
 659
 660         uint32_t ctrl_ext;
 661
 662         pci_dev = eth_dev->pci_dev;
 663
 664         eth_dev->dev_ops = &eth_igb_ops;
 665         eth_dev->rx_pkt_burst = &eth_igb_recv_pkts;
 666         eth_dev->tx_pkt_burst = &eth_igb_xmit_pkts;
 667
 668         /* for secondary processes, we don't initialise any further as primary
 669          * has already done this work. Only check we don't need a different
 670          * RX function */
 671         if (rte_eal_process_type() != RTE_PROC_PRIMARY){
 672                 if (eth_dev->data->scattered_rx)
 673                         eth_dev->rx_pkt_burst = &eth_igb_recv_scattered_pkts;
 674                 return 0;
 675         }
 676
 677         rte_eth_copy_pci_info(eth_dev, pci_dev);
 678
 679         hw->hw_addr= (void *)pci_dev->mem_resource[0].addr;
 680
 681         igb_identify_hardware(eth_dev);
 682         if (e1000_setup_init_funcs(hw, FALSE) != E1000_SUCCESS) {
 683                 error = -EIO;
 684                 goto err_late;
 685         }
 686
 687         e1000_get_bus_info(hw);
 688
 689         /* Reset any pending lock */
 690         if (igb_reset_swfw_lock(hw) != E1000_SUCCESS) {
 691                 error = -EIO;
 692                 goto err_late;
 693         }
 694
 695         /* Finish initialization */
 696         if (e1000_setup_init_funcs(hw, TRUE) != E1000_SUCCESS) {
 697                 error = -EIO;
 698                 goto err_late;
 699         }
 700
 701         hw->mac.autoneg = 1;
 702         hw->phy.autoneg_wait_to_complete = 0;
 703         hw->phy.autoneg_advertised = E1000_ALL_SPEED_DUPLEX;
 704
 705         /* Copper options */
 706         if (hw->phy.media_type == e1000_media_type_copper) {
 707                 hw->phy.mdix = 0; /* AUTO_ALL_MODES */
 708                 hw->phy.disable_polarity_correction = 0;
 709                 hw->phy.ms_type = e1000_ms_hw_default;
 710         }
 711
 712         /*
 713          * Start from a known state, this is important in reading the nvm
 714          * and mac from that.
 715          */
 716         igb_pf_reset_hw(hw);
 717
 718         /* Make sure we have a good EEPROM before we read from it */
 719         if (e1000_validate_nvm_checksum(hw) < 0) {
 720                 /*
 721                  * Some PCI-E parts fail the first check due to
 722                  * the link being in sleep state, call it again,
 723                  * if it fails a second time its a real issue.
 724                  */
 725                 if (e1000_validate_nvm_checksum(hw) < 0) {
 726                         PMD_INIT_LOG(ERR, "EEPROM checksum invalid");
 727                         error = -EIO;
 728                         goto err_late;
 729                 }
 730         }
 731
 732         /* Read the permanent MAC address out of the EEPROM */
 733         if (e1000_read_mac_addr(hw) != 0) {
 734                 PMD_INIT_LOG(ERR, "EEPROM error while reading MAC address");
 735                 error = -EIO;
 736                 goto err_late;
 737         }
 738
 739         /* Allocate memory for storing MAC addresses */
 740         eth_dev->data->mac_addrs = rte_zmalloc("e1000",
 741                 ETHER_ADDR_LEN * hw->mac.rar_entry_count, 0);
 742         if (eth_dev->data->mac_addrs == NULL) {
 743                 PMD_INIT_LOG(ERR, "Failed to allocate %d bytes needed to "
 744                                                 "store MAC addresses",
 745                                 ETHER_ADDR_LEN * hw->mac.rar_entry_count);
 746                 error = -ENOMEM;
 747                 goto err_late;
 748         }
 749
 750         /* Copy the permanent MAC address */
 751         ether_addr_copy((struct ether_addr *)hw->mac.addr, &eth_dev->data->mac_addrs[0]);
 752
 753         /* initialize the vfta */
 754         memset(shadow_vfta, 0, sizeof(*shadow_vfta));
 755
 756         /* Now initialize the hardware */
 757         if (igb_hardware_init(hw) != 0) {
 758                 PMD_INIT_LOG(ERR, "Hardware initialization failed");
 759                 rte_free(eth_dev->data->mac_addrs);
 760                 eth_dev->data->mac_addrs = NULL;
 761                 error = -ENODEV;
 762                 goto err_late;
 763         }
 764         hw->mac.get_link_status = 1;
 765         adapter->stopped = 0;
 766
 767         /* Indicate SOL/IDER usage */
 768         if (e1000_check_reset_block(hw) < 0) {
 769                 PMD_INIT_LOG(ERR, "PHY reset is blocked due to"
 770                                         "SOL/IDER session");
 771         }
 772
 773         /* initialize PF if max_vfs not zero */
 774         igb_pf_host_init(eth_dev);
 775
 776         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
 777         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
 778         ctrl_ext |= E1000_CTRL_EXT_PFRSTD;
 779         E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
 780         E1000_WRITE_FLUSH(hw);
 781
 782         PMD_INIT_LOG(DEBUG, "port_id %d vendorID=0x%x deviceID=0x%x",
 783                      eth_dev->data->port_id, pci_dev->id.vendor_id,
 784                      pci_dev->id.device_id);
 785
 786         rte_intr_callback_register(&pci_dev->intr_handle,
 787                                    eth_igb_interrupt_handler,
 788                                    (void *)eth_dev);
 789
 790         /* enable uio/vfio intr/eventfd mapping */
 791         rte_intr_enable(&pci_dev->intr_handle);
 792
 793         /* enable support intr */
 794         igb_intr_enable(eth_dev);
 795
 796         TAILQ_INIT(&filter_info->flex_list);
 797         filter_info->flex_mask = 0;
 798         TAILQ_INIT(&filter_info->twotuple_list);
 799         filter_info->twotuple_mask = 0;
 800         TAILQ_INIT(&filter_info->fivetuple_list);
 801         filter_info->fivetuple_mask = 0;
 802
 803         return 0;
 804
 805 err_late:
 806         igb_hw_control_release(hw);
 807
 808         return error;
 809 }
 810
 811 static int
 812 eth_igb_dev_uninit(struct rte_eth_dev *eth_dev)
 813 {
 814         struct rte_pci_device *pci_dev;
 815         struct e1000_hw *hw;
 816         struct e1000_adapter *adapter =
 817                 E1000_DEV_PRIVATE(eth_dev->data->dev_private);
 818
 819         PMD_INIT_FUNC_TRACE();
 820
 821         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
 822                 return -EPERM;
 823
 824         hw = E1000_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 825         pci_dev = eth_dev->pci_dev;
 826
 827         if (adapter->stopped == 0)
 828                 eth_igb_close(eth_dev);
 829
 830         eth_dev->dev_ops = NULL;
 831         eth_dev->rx_pkt_burst = NULL;
 832         eth_dev->tx_pkt_burst = NULL;
 833
 834         /* Reset any pending lock */
 835         igb_reset_swfw_lock(hw);
 836
 837         rte_free(eth_dev->data->mac_addrs);
 838         eth_dev->data->mac_addrs = NULL;
 839
 840         /* uninitialize PF if max_vfs not zero */
 841         igb_pf_host_uninit(eth_dev);
 842
 843         /* disable uio intr before callback unregister */
 844         rte_intr_disable(&(pci_dev->intr_handle));
 845         rte_intr_callback_unregister(&(pci_dev->intr_handle),
 846                 eth_igb_interrupt_handler, (void *)eth_dev);
 847
 848         return 0;
 849 }
 850
 851 /*
 852  * Virtual Function device init
 853  */
 854 static int
 855 eth_igbvf_dev_init(struct rte_eth_dev *eth_dev)
 856 {
 857         struct rte_pci_device *pci_dev;
 858         struct e1000_adapter *adapter =
 859                 E1000_DEV_PRIVATE(eth_dev->data->dev_private);
 860         struct e1000_hw *hw =
 861                 E1000_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 862         int diag;
 863         struct ether_addr *perm_addr = (struct ether_addr *)hw->mac.perm_addr;
 864
 865         PMD_INIT_FUNC_TRACE();
 866
 867         eth_dev->dev_ops = &igbvf_eth_dev_ops;
 868         eth_dev->rx_pkt_burst = &eth_igb_recv_pkts;
 869         eth_dev->tx_pkt_burst = &eth_igb_xmit_pkts;
 870
 871         /* for secondary processes, we don't initialise any further as primary
 872          * has already done this work. Only check we don't need a different
 873          * RX function */
 874         if (rte_eal_process_type() != RTE_PROC_PRIMARY){
 875                 if (eth_dev->data->scattered_rx)
 876                         eth_dev->rx_pkt_burst = &eth_igb_recv_scattered_pkts;
 877                 return 0;
 878         }
 879
 880         pci_dev = eth_dev->pci_dev;
 881
 882         rte_eth_copy_pci_info(eth_dev, pci_dev);
 883
 884         hw->device_id = pci_dev->id.device_id;
 885         hw->vendor_id = pci_dev->id.vendor_id;
 886         hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
 887         adapter->stopped = 0;
 888
 889         /* Initialize the shared code (base driver) */
 890         diag = e1000_setup_init_funcs(hw, TRUE);
 891         if (diag != 0) {
 892                 PMD_INIT_LOG(ERR, "Shared code init failed for igbvf: %d",
 893                         diag);
 894                 return -EIO;
 895         }
 896
 897         /* init_mailbox_params */
 898         hw->mbx.ops.init_params(hw);
 899
 900         /* Disable the interrupts for VF */
 901         igbvf_intr_disable(hw);
 902
 903         diag = hw->mac.ops.reset_hw(hw);
 904
 905         /* Allocate memory for storing MAC addresses */
 906         eth_dev->data->mac_addrs = rte_zmalloc("igbvf", ETHER_ADDR_LEN *
 907                 hw->mac.rar_entry_count, 0);
 908         if (eth_dev->data->mac_addrs == NULL) {
 909                 PMD_INIT_LOG(ERR,
 910                         "Failed to allocate %d bytes needed to store MAC "
 911                         "addresses",
 912                         ETHER_ADDR_LEN * hw->mac.rar_entry_count);
 913                 return -ENOMEM;
 914         }
 915
 916         /* Generate a random MAC address, if none was assigned by PF. */
 917         if (is_zero_ether_addr(perm_addr)) {
 918                 eth_random_addr(perm_addr->addr_bytes);
 919                 diag = e1000_rar_set(hw, perm_addr->addr_bytes, 0);
 920                 if (diag) {
 921                         rte_free(eth_dev->data->mac_addrs);
 922                         eth_dev->data->mac_addrs = NULL;
 923                         return diag;
 924                 }
 925                 PMD_INIT_LOG(INFO, "\tVF MAC address not assigned by Host PF");
 926                 PMD_INIT_LOG(INFO, "\tAssign randomly generated MAC address "
 927                              "%02x:%02x:%02x:%02x:%02x:%02x",
 928                              perm_addr->addr_bytes[0],
 929                              perm_addr->addr_bytes[1],
 930                              perm_addr->addr_bytes[2],
 931                              perm_addr->addr_bytes[3],
 932                              perm_addr->addr_bytes[4],
 933                              perm_addr->addr_bytes[5]);
 934         }
 935
 936         /* Copy the permanent MAC address */
 937         ether_addr_copy((struct ether_addr *) hw->mac.perm_addr,
 938                         &eth_dev->data->mac_addrs[0]);
 939
 940         PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x "
 941                      "mac.type=%s",
 942                      eth_dev->data->port_id, pci_dev->id.vendor_id,
 943                      pci_dev->id.device_id, "igb_mac_82576_vf");
 944
 945         return 0;
 946 }
 947
 948 static int
 949 eth_igbvf_dev_uninit(struct rte_eth_dev *eth_dev)
 950 {
 951         struct e1000_adapter *adapter =
 952                 E1000_DEV_PRIVATE(eth_dev->data->dev_private);
 953
 954         PMD_INIT_FUNC_TRACE();
 955
 956         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
 957                 return -EPERM;
 958
 959         if (adapter->stopped == 0)
 960                 igbvf_dev_close(eth_dev);
 961
 962         eth_dev->dev_ops = NULL;
 963         eth_dev->rx_pkt_burst = NULL;
 964         eth_dev->tx_pkt_burst = NULL;
 965
 966         rte_free(eth_dev->data->mac_addrs);
 967         eth_dev->data->mac_addrs = NULL;
 968
 969         return 0;
 970 }
 971
 972 static struct eth_driver rte_igb_pmd = {
 973         .pci_drv = {
 974                 .name = "rte_igb_pmd",
 975                 .id_table = pci_id_igb_map,
 976                 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC |
 977                         RTE_PCI_DRV_DETACHABLE,
 978         },
 979         .eth_dev_init = eth_igb_dev_init,
 980         .eth_dev_uninit = eth_igb_dev_uninit,
 981         .dev_private_size = sizeof(struct e1000_adapter),
 982 };
 983
 984 /*
 985  * virtual function driver struct
 986  */
 987 static struct eth_driver rte_igbvf_pmd = {
 988         .pci_drv = {
 989                 .name = "rte_igbvf_pmd",
 990                 .id_table = pci_id_igbvf_map,
 991                 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_DETACHABLE,
 992         },
 993         .eth_dev_init = eth_igbvf_dev_init,
 994         .eth_dev_uninit = eth_igbvf_dev_uninit,
 995         .dev_private_size = sizeof(struct e1000_adapter),
 996 };
 997
 998 static int
 999 rte_igb_pmd_init(const char *name __rte_unused, const char *params __rte_unused)
1000 {
1001         rte_eth_driver_register(&rte_igb_pmd);
1002         return 0;
1003 }
1004
1005 static void
1006 igb_vmdq_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1007 {
1008         struct e1000_hw *hw =
1009                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1010         /* RCTL: enable VLAN filter since VMDq always use VLAN filter */
1011         uint32_t rctl = E1000_READ_REG(hw, E1000_RCTL);
1012         rctl |= E1000_RCTL_VFE;
1013         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1014 }
1015
1016 /*
1017  * VF Driver initialization routine.
1018  * Invoked one at EAL init time.
1019  * Register itself as the [Virtual Poll Mode] Driver of PCI IGB devices.
1020  */
1021 static int
1022 rte_igbvf_pmd_init(const char *name __rte_unused, const char *params __rte_unused)
1023 {
1024         PMD_INIT_FUNC_TRACE();
1025
1026         rte_eth_driver_register(&rte_igbvf_pmd);
1027         return 0;
1028 }
1029
1030 static int
1031 igb_check_mq_mode(struct rte_eth_dev *dev)
1032 {
1033         enum rte_eth_rx_mq_mode rx_mq_mode = dev->data->dev_conf.rxmode.mq_mode;
1034         enum rte_eth_tx_mq_mode tx_mq_mode = dev->data->dev_conf.txmode.mq_mode;
1035         uint16_t nb_rx_q = dev->data->nb_rx_queues;
1036         uint16_t nb_tx_q = dev->data->nb_rx_queues;
1037
1038         if ((rx_mq_mode & ETH_MQ_RX_DCB_FLAG) ||
1039             tx_mq_mode == ETH_MQ_TX_DCB ||
1040             tx_mq_mode == ETH_MQ_TX_VMDQ_DCB) {
1041                 PMD_INIT_LOG(ERR, "DCB mode is not supported.");
1042                 return -EINVAL;
1043         }
1044         if (RTE_ETH_DEV_SRIOV(dev).active != 0) {
1045                 /* Check multi-queue mode.
1046                  * To no break software we accept ETH_MQ_RX_NONE as this might
1047                  * be used to turn off VLAN filter.
1048                  */
1049
1050                 if (rx_mq_mode == ETH_MQ_RX_NONE ||
1051                     rx_mq_mode == ETH_MQ_RX_VMDQ_ONLY) {
1052                         dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_ONLY;
1053                         RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool = 1;
1054                 } else {
1055                         /* Only support one queue on VFs.
1056                          * RSS together with SRIOV is not supported.
1057                          */
1058                         PMD_INIT_LOG(ERR, "SRIOV is active,"
1059                                         " wrong mq_mode rx %d.",
1060                                         rx_mq_mode);
1061                         return -EINVAL;
1062                 }
1063                 /* TX mode is not used here, so mode might be ignored.*/
1064                 if (tx_mq_mode != ETH_MQ_TX_VMDQ_ONLY) {
1065                         /* SRIOV only works in VMDq enable mode */
1066                         PMD_INIT_LOG(WARNING, "SRIOV is active,"
1067                                         " TX mode %d is not supported. "
1068                                         " Driver will behave as %d mode.",
1069                                         tx_mq_mode, ETH_MQ_TX_VMDQ_ONLY);
1070                 }
1071
1072                 /* check valid queue number */
1073                 if ((nb_rx_q > 1) || (nb_tx_q > 1)) {
1074                         PMD_INIT_LOG(ERR, "SRIOV is active,"
1075                                         " only support one queue on VFs.");
1076                         return -EINVAL;
1077                 }
1078         } else {
1079                 /* To no break software that set invalid mode, only display
1080                  * warning if invalid mode is used.
1081                  */
1082                 if (rx_mq_mode != ETH_MQ_RX_NONE &&
1083                     rx_mq_mode != ETH_MQ_RX_VMDQ_ONLY &&
1084                     rx_mq_mode != ETH_MQ_RX_RSS) {
1085                         /* RSS together with VMDq not supported*/
1086                         PMD_INIT_LOG(ERR, "RX mode %d is not supported.",
1087                                      rx_mq_mode);
1088                         return -EINVAL;
1089                 }
1090
1091                 if (tx_mq_mode != ETH_MQ_TX_NONE &&
1092                     tx_mq_mode != ETH_MQ_TX_VMDQ_ONLY) {
1093                         PMD_INIT_LOG(WARNING, "TX mode %d is not supported."
1094                                         " Due to txmode is meaningless in this"
1095                                         " driver, just ignore.",
1096                                         tx_mq_mode);
1097                 }
1098         }
1099         return 0;
1100 }
1101
1102 static int
1103 eth_igb_configure(struct rte_eth_dev *dev)
1104 {
1105         struct e1000_interrupt *intr =
1106                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
1107         int ret;
1108
1109         PMD_INIT_FUNC_TRACE();
1110
1111         /* multipe queue mode checking */
1112         ret  = igb_check_mq_mode(dev);
1113         if (ret != 0) {
1114                 PMD_DRV_LOG(ERR, "igb_check_mq_mode fails with %d.",
1115                             ret);
1116                 return ret;
1117         }
1118
1119         intr->flags |= E1000_FLAG_NEED_LINK_UPDATE;
1120         PMD_INIT_FUNC_TRACE();
1121
1122         return 0;
1123 }
1124
1125 static int
1126 eth_igb_start(struct rte_eth_dev *dev)
1127 {
1128         struct e1000_hw *hw =
1129                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1130         struct e1000_adapter *adapter =
1131                 E1000_DEV_PRIVATE(dev->data->dev_private);
1132         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
1133         int ret, mask;
1134         uint32_t intr_vector = 0;
1135         uint32_t ctrl_ext;
1136         uint32_t *speeds;
1137         int num_speeds;
1138         bool autoneg;
1139
1140         PMD_INIT_FUNC_TRACE();
1141
1142         /* disable uio/vfio intr/eventfd mapping */
1143         rte_intr_disable(intr_handle);
1144
1145         /* Power up the phy. Needed to make the link go Up */
1146         e1000_power_up_phy(hw);
1147
1148         /*
1149          * Packet Buffer Allocation (PBA)
1150          * Writing PBA sets the receive portion of the buffer
1151          * the remainder is used for the transmit buffer.
1152          */
1153         if (hw->mac.type == e1000_82575) {
1154                 uint32_t pba;
1155
1156                 pba = E1000_PBA_32K; /* 32K for Rx, 16K for Tx */
1157                 E1000_WRITE_REG(hw, E1000_PBA, pba);
1158         }
1159
1160         /* Put the address into the Receive Address Array */
1161         e1000_rar_set(hw, hw->mac.addr, 0);
1162
1163         /* Initialize the hardware */
1164         if (igb_hardware_init(hw)) {
1165                 PMD_INIT_LOG(ERR, "Unable to initialize the hardware");
1166                 return -EIO;
1167         }
1168         adapter->stopped = 0;
1169
1170         E1000_WRITE_REG(hw, E1000_VET, ETHER_TYPE_VLAN << 16 | ETHER_TYPE_VLAN);
1171
1172         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
1173         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
1174         ctrl_ext |= E1000_CTRL_EXT_PFRSTD;
1175         E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
1176         E1000_WRITE_FLUSH(hw);
1177
1178         /* configure PF module if SRIOV enabled */
1179         igb_pf_host_configure(dev);
1180
1181         /* check and configure queue intr-vector mapping */
1182         if ((rte_intr_cap_multiple(intr_handle) ||
1183              !RTE_ETH_DEV_SRIOV(dev).active) &&
1184             dev->data->dev_conf.intr_conf.rxq != 0) {
1185                 intr_vector = dev->data->nb_rx_queues;
1186                 if (rte_intr_efd_enable(intr_handle, intr_vector))
1187                         return -1;
1188         }
1189
1190         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
1191                 intr_handle->intr_vec =
1192                         rte_zmalloc("intr_vec",
1193                                     dev->data->nb_rx_queues * sizeof(int), 0);
1194                 if (intr_handle->intr_vec == NULL) {
1195                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
1196                                      " intr_vec\n", dev->data->nb_rx_queues);
1197                         return -ENOMEM;
1198                 }
1199         }
1200
1201         /* confiugre msix for rx interrupt */
1202         eth_igb_configure_msix_intr(dev);
1203
1204         /* Configure for OS presence */
1205         igb_init_manageability(hw);
1206
1207         eth_igb_tx_init(dev);
1208
1209         /* This can fail when allocating mbufs for descriptor rings */
1210         ret = eth_igb_rx_init(dev);
1211         if (ret) {
1212                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
1213                 igb_dev_clear_queues(dev);
1214                 return ret;
1215         }
1216
1217         e1000_clear_hw_cntrs_base_generic(hw);
1218
1219         /*
1220          * VLAN Offload Settings
1221          */
1222         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK | \
1223                         ETH_VLAN_EXTEND_MASK;
1224         eth_igb_vlan_offload_set(dev, mask);
1225
1226         if (dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_VMDQ_ONLY) {
1227                 /* Enable VLAN filter since VMDq always use VLAN filter */
1228                 igb_vmdq_vlan_hw_filter_enable(dev);
1229         }
1230
1231         if ((hw->mac.type == e1000_82576) || (hw->mac.type == e1000_82580) ||
1232                 (hw->mac.type == e1000_i350) || (hw->mac.type == e1000_i210) ||
1233                 (hw->mac.type == e1000_i211)) {
1234                 /* Configure EITR with the maximum possible value (0xFFFF) */
1235                 E1000_WRITE_REG(hw, E1000_EITR(0), 0xFFFF);
1236         }
1237
1238         /* Setup link speed and duplex */
1239         speeds = &dev->data->dev_conf.link_speeds;
1240         if (*speeds == ETH_LINK_SPEED_AUTONEG) {
1241                 hw->phy.autoneg_advertised = E1000_ALL_SPEED_DUPLEX;
1242         } else {
1243                 num_speeds = 0;
1244                 autoneg = (*speeds & ETH_LINK_SPEED_FIXED) == 0;
1245
1246                 /* Reset */
1247                 hw->phy.autoneg_advertised = 0;
1248
1249                 if (*speeds & ~(ETH_LINK_SPEED_10M_HD | ETH_LINK_SPEED_10M |
1250                                 ETH_LINK_SPEED_100M_HD | ETH_LINK_SPEED_100M |
1251                                 ETH_LINK_SPEED_1G | ETH_LINK_SPEED_FIXED)) {
1252                         num_speeds = -1;
1253                         goto error_invalid_config;
1254                 }
1255                 if (*speeds & ETH_LINK_SPEED_10M_HD) {
1256                         hw->phy.autoneg_advertised |= ADVERTISE_10_HALF;
1257                         num_speeds++;
1258                 }
1259                 if (*speeds & ETH_LINK_SPEED_10M) {
1260                         hw->phy.autoneg_advertised |= ADVERTISE_10_FULL;
1261                         num_speeds++;
1262                 }
1263                 if (*speeds & ETH_LINK_SPEED_100M_HD) {
1264                         hw->phy.autoneg_advertised |= ADVERTISE_100_HALF;
1265                         num_speeds++;
1266                 }
1267                 if (*speeds & ETH_LINK_SPEED_100M) {
1268                         hw->phy.autoneg_advertised |= ADVERTISE_100_FULL;
1269                         num_speeds++;
1270                 }
1271                 if (*speeds & ETH_LINK_SPEED_1G) {
1272                         hw->phy.autoneg_advertised |= ADVERTISE_1000_FULL;
1273                         num_speeds++;
1274                 }
1275                 if (num_speeds == 0 || (!autoneg && (num_speeds > 1)))
1276                         goto error_invalid_config;
1277         }
1278
1279         e1000_setup_link(hw);
1280
1281         if (rte_intr_allow_others(intr_handle)) {
1282                 /* check if lsc interrupt is enabled */
1283                 if (dev->data->dev_conf.intr_conf.lsc != 0)
1284                         eth_igb_lsc_interrupt_setup(dev);
1285         } else {
1286                 rte_intr_callback_unregister(intr_handle,
1287                                              eth_igb_interrupt_handler,
1288                                              (void *)dev);
1289                 if (dev->data->dev_conf.intr_conf.lsc != 0)
1290                         PMD_INIT_LOG(INFO, "lsc won't enable because of"
1291                                      " no intr multiplex\n");
1292         }
1293
1294         /* check if rxq interrupt is enabled */
1295         if (dev->data->dev_conf.intr_conf.rxq != 0 &&
1296             rte_intr_dp_is_en(intr_handle))
1297                 eth_igb_rxq_interrupt_setup(dev);
1298
1299         /* enable uio/vfio intr/eventfd mapping */
1300         rte_intr_enable(intr_handle);
1301
1302         /* resume enabled intr since hw reset */
1303         igb_intr_enable(dev);
1304
1305         PMD_INIT_LOG(DEBUG, "<<");
1306
1307         return 0;
1308
1309 error_invalid_config:
1310         PMD_INIT_LOG(ERR, "Invalid advertised speeds (%u) for port %u",
1311                      dev->data->dev_conf.link_speeds, dev->data->port_id);
1312         igb_dev_clear_queues(dev);
1313         return -EINVAL;
1314 }
1315
1316 /*********************************************************************
1317  *
1318  *  This routine disables all traffic on the adapter by issuing a
1319  *  global reset on the MAC.
1320  *
1321  **********************************************************************/
1322 static void
1323 eth_igb_stop(struct rte_eth_dev *dev)
1324 {
1325         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1326         struct e1000_filter_info *filter_info =
1327                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
1328         struct rte_eth_link link;
1329         struct e1000_flex_filter *p_flex;
1330         struct e1000_5tuple_filter *p_5tuple, *p_5tuple_next;
1331         struct e1000_2tuple_filter *p_2tuple, *p_2tuple_next;
1332         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
1333
1334         igb_intr_disable(hw);
1335
1336         /* disable intr eventfd mapping */
1337         rte_intr_disable(intr_handle);
1338
1339         igb_pf_reset_hw(hw);
1340         E1000_WRITE_REG(hw, E1000_WUC, 0);
1341
1342         /* Set bit for Go Link disconnect */
1343         if (hw->mac.type >= e1000_82580) {
1344                 uint32_t phpm_reg;
1345
1346                 phpm_reg = E1000_READ_REG(hw, E1000_82580_PHY_POWER_MGMT);
1347                 phpm_reg |= E1000_82580_PM_GO_LINKD;
1348                 E1000_WRITE_REG(hw, E1000_82580_PHY_POWER_MGMT, phpm_reg);
1349         }
1350
1351         /* Power down the phy. Needed to make the link go Down */
1352         if (hw->phy.media_type == e1000_media_type_copper)
1353                 e1000_power_down_phy(hw);
1354         else
1355                 e1000_shutdown_fiber_serdes_link(hw);
1356
1357         igb_dev_clear_queues(dev);
1358
1359         /* clear the recorded link status */
1360         memset(&link, 0, sizeof(link));
1361         rte_igb_dev_atomic_write_link_status(dev, &link);
1362
1363         /* Remove all flex filters of the device */
1364         while ((p_flex = TAILQ_FIRST(&filter_info->flex_list))) {
1365                 TAILQ_REMOVE(&filter_info->flex_list, p_flex, entries);
1366                 rte_free(p_flex);
1367         }
1368         filter_info->flex_mask = 0;
1369
1370         /* Remove all ntuple filters of the device */
1371         for (p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list);
1372              p_5tuple != NULL; p_5tuple = p_5tuple_next) {
1373                 p_5tuple_next = TAILQ_NEXT(p_5tuple, entries);
1374                 TAILQ_REMOVE(&filter_info->fivetuple_list,
1375                              p_5tuple, entries);
1376                 rte_free(p_5tuple);
1377         }
1378         filter_info->fivetuple_mask = 0;
1379         for (p_2tuple = TAILQ_FIRST(&filter_info->twotuple_list);
1380              p_2tuple != NULL; p_2tuple = p_2tuple_next) {
1381                 p_2tuple_next = TAILQ_NEXT(p_2tuple, entries);
1382                 TAILQ_REMOVE(&filter_info->twotuple_list,
1383                              p_2tuple, entries);
1384                 rte_free(p_2tuple);
1385         }
1386         filter_info->twotuple_mask = 0;
1387
1388         if (!rte_intr_allow_others(intr_handle))
1389                 /* resume to the default handler */
1390                 rte_intr_callback_register(intr_handle,
1391                                            eth_igb_interrupt_handler,
1392                                            (void *)dev);
1393
1394         /* Clean datapath event and queue/vec mapping */
1395         rte_intr_efd_disable(intr_handle);
1396         if (intr_handle->intr_vec != NULL) {
1397                 rte_free(intr_handle->intr_vec);
1398                 intr_handle->intr_vec = NULL;
1399         }
1400 }
1401
1402 static void
1403 eth_igb_close(struct rte_eth_dev *dev)
1404 {
1405         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1406         struct e1000_adapter *adapter =
1407                 E1000_DEV_PRIVATE(dev->data->dev_private);
1408         struct rte_eth_link link;
1409         struct rte_pci_device *pci_dev;
1410
1411         eth_igb_stop(dev);
1412         adapter->stopped = 1;
1413
1414         e1000_phy_hw_reset(hw);
1415         igb_release_manageability(hw);
1416         igb_hw_control_release(hw);
1417
1418         /* Clear bit for Go Link disconnect */
1419         if (hw->mac.type >= e1000_82580) {
1420                 uint32_t phpm_reg;
1421
1422                 phpm_reg = E1000_READ_REG(hw, E1000_82580_PHY_POWER_MGMT);
1423                 phpm_reg &= ~E1000_82580_PM_GO_LINKD;
1424                 E1000_WRITE_REG(hw, E1000_82580_PHY_POWER_MGMT, phpm_reg);
1425         }
1426
1427         igb_dev_free_queues(dev);
1428
1429         pci_dev = dev->pci_dev;
1430         if (pci_dev->intr_handle.intr_vec) {
1431                 rte_free(pci_dev->intr_handle.intr_vec);
1432                 pci_dev->intr_handle.intr_vec = NULL;
1433         }
1434
1435         memset(&link, 0, sizeof(link));
1436         rte_igb_dev_atomic_write_link_status(dev, &link);
1437 }
1438
1439 static int
1440 igb_get_rx_buffer_size(struct e1000_hw *hw)
1441 {
1442         uint32_t rx_buf_size;
1443         if (hw->mac.type == e1000_82576) {
1444                 rx_buf_size = (E1000_READ_REG(hw, E1000_RXPBS) & 0xffff) << 10;
1445         } else if (hw->mac.type == e1000_82580 || hw->mac.type == e1000_i350) {
1446                 /* PBS needs to be translated according to a lookup table */
1447                 rx_buf_size = (E1000_READ_REG(hw, E1000_RXPBS) & 0xf);
1448                 rx_buf_size = (uint32_t) e1000_rxpbs_adjust_82580(rx_buf_size);
1449                 rx_buf_size = (rx_buf_size << 10);
1450         } else if (hw->mac.type == e1000_i210 || hw->mac.type == e1000_i211) {
1451                 rx_buf_size = (E1000_READ_REG(hw, E1000_RXPBS) & 0x3f) << 10;
1452         } else {
1453                 rx_buf_size = (E1000_READ_REG(hw, E1000_PBA) & 0xffff) << 10;
1454         }
1455
1456         return rx_buf_size;
1457 }
1458
1459 /*********************************************************************
1460  *
1461  *  Initialize the hardware
1462  *
1463  **********************************************************************/
1464 static int
1465 igb_hardware_init(struct e1000_hw *hw)
1466 {
1467         uint32_t rx_buf_size;
1468         int diag;
1469
1470         /* Let the firmware know the OS is in control */
1471         igb_hw_control_acquire(hw);
1472
1473         /*
1474          * These parameters control the automatic generation (Tx) and
1475          * response (Rx) to Ethernet PAUSE frames.
1476          * - High water mark should allow for at least two standard size (1518)
1477          *   frames to be received after sending an XOFF.
1478          * - Low water mark works best when it is very near the high water mark.
1479          *   This allows the receiver to restart by sending XON when it has
1480          *   drained a bit. Here we use an arbitrary value of 1500 which will
1481          *   restart after one full frame is pulled from the buffer. There
1482          *   could be several smaller frames in the buffer and if so they will
1483          *   not trigger the XON until their total number reduces the buffer
1484          *   by 1500.
1485          * - The pause time is fairly large at 1000 x 512ns = 512 usec.
1486          */
1487         rx_buf_size = igb_get_rx_buffer_size(hw);
1488
1489         hw->fc.high_water = rx_buf_size - (ETHER_MAX_LEN * 2);
1490         hw->fc.low_water = hw->fc.high_water - 1500;
1491         hw->fc.pause_time = IGB_FC_PAUSE_TIME;
1492         hw->fc.send_xon = 1;
1493
1494         /* Set Flow control, use the tunable location if sane */
1495         if ((igb_fc_setting != e1000_fc_none) && (igb_fc_setting < 4))
1496                 hw->fc.requested_mode = igb_fc_setting;
1497         else
1498                 hw->fc.requested_mode = e1000_fc_none;
1499
1500         /* Issue a global reset */
1501         igb_pf_reset_hw(hw);
1502         E1000_WRITE_REG(hw, E1000_WUC, 0);
1503
1504         diag = e1000_init_hw(hw);
1505         if (diag < 0)
1506                 return diag;
1507
1508         E1000_WRITE_REG(hw, E1000_VET, ETHER_TYPE_VLAN << 16 | ETHER_TYPE_VLAN);
1509         e1000_get_phy_info(hw);
1510         e1000_check_for_link(hw);
1511
1512         return 0;
1513 }
1514
1515 /* This function is based on igb_update_stats_counters() in igb/if_igb.c */
1516 static void
1517 igb_read_stats_registers(struct e1000_hw *hw, struct e1000_hw_stats *stats)
1518 {
1519         int pause_frames;
1520
1521         uint64_t old_gprc  = stats->gprc;
1522         uint64_t old_gptc  = stats->gptc;
1523         uint64_t old_tpr   = stats->tpr;
1524         uint64_t old_tpt   = stats->tpt;
1525         uint64_t old_rpthc = stats->rpthc;
1526         uint64_t old_hgptc = stats->hgptc;
1527
1528         if(hw->phy.media_type == e1000_media_type_copper ||
1529             (E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU)) {
1530                 stats->symerrs +=
1531                     E1000_READ_REG(hw,E1000_SYMERRS);
1532                 stats->sec += E1000_READ_REG(hw, E1000_SEC);
1533         }
1534
1535         stats->crcerrs += E1000_READ_REG(hw, E1000_CRCERRS);
1536         stats->mpc += E1000_READ_REG(hw, E1000_MPC);
1537         stats->scc += E1000_READ_REG(hw, E1000_SCC);
1538         stats->ecol += E1000_READ_REG(hw, E1000_ECOL);
1539
1540         stats->mcc += E1000_READ_REG(hw, E1000_MCC);
1541         stats->latecol += E1000_READ_REG(hw, E1000_LATECOL);
1542         stats->colc += E1000_READ_REG(hw, E1000_COLC);
1543         stats->dc += E1000_READ_REG(hw, E1000_DC);
1544         stats->rlec += E1000_READ_REG(hw, E1000_RLEC);
1545         stats->xonrxc += E1000_READ_REG(hw, E1000_XONRXC);
1546         stats->xontxc += E1000_READ_REG(hw, E1000_XONTXC);
1547         /*
1548         ** For watchdog management we need to know if we have been
1549         ** paused during the last interval, so capture that here.
1550         */
1551         pause_frames = E1000_READ_REG(hw, E1000_XOFFRXC);
1552         stats->xoffrxc += pause_frames;
1553         stats->xofftxc += E1000_READ_REG(hw, E1000_XOFFTXC);
1554         stats->fcruc += E1000_READ_REG(hw, E1000_FCRUC);
1555         stats->prc64 += E1000_READ_REG(hw, E1000_PRC64);
1556         stats->prc127 += E1000_READ_REG(hw, E1000_PRC127);
1557         stats->prc255 += E1000_READ_REG(hw, E1000_PRC255);
1558         stats->prc511 += E1000_READ_REG(hw, E1000_PRC511);
1559         stats->prc1023 += E1000_READ_REG(hw, E1000_PRC1023);
1560         stats->prc1522 += E1000_READ_REG(hw, E1000_PRC1522);
1561         stats->gprc += E1000_READ_REG(hw, E1000_GPRC);
1562         stats->bprc += E1000_READ_REG(hw, E1000_BPRC);
1563         stats->mprc += E1000_READ_REG(hw, E1000_MPRC);
1564         stats->gptc += E1000_READ_REG(hw, E1000_GPTC);
1565
1566         /* For the 64-bit byte counters the low dword must be read first. */
1567         /* Both registers clear on the read of the high dword */
1568
1569         /* Workaround CRC bytes included in size, take away 4 bytes/packet */
1570         stats->gorc += E1000_READ_REG(hw, E1000_GORCL);
1571         stats->gorc += ((uint64_t)E1000_READ_REG(hw, E1000_GORCH) << 32);
1572         stats->gorc -= (stats->gprc - old_gprc) * ETHER_CRC_LEN;
1573         stats->gotc += E1000_READ_REG(hw, E1000_GOTCL);
1574         stats->gotc += ((uint64_t)E1000_READ_REG(hw, E1000_GOTCH) << 32);
1575         stats->gotc -= (stats->gptc - old_gptc) * ETHER_CRC_LEN;
1576
1577         stats->rnbc += E1000_READ_REG(hw, E1000_RNBC);
1578         stats->ruc += E1000_READ_REG(hw, E1000_RUC);
1579         stats->rfc += E1000_READ_REG(hw, E1000_RFC);
1580         stats->roc += E1000_READ_REG(hw, E1000_ROC);
1581         stats->rjc += E1000_READ_REG(hw, E1000_RJC);
1582
1583         stats->tpr += E1000_READ_REG(hw, E1000_TPR);
1584         stats->tpt += E1000_READ_REG(hw, E1000_TPT);
1585
1586         stats->tor += E1000_READ_REG(hw, E1000_TORL);
1587         stats->tor += ((uint64_t)E1000_READ_REG(hw, E1000_TORH) << 32);
1588         stats->tor -= (stats->tpr - old_tpr) * ETHER_CRC_LEN;
1589         stats->tot += E1000_READ_REG(hw, E1000_TOTL);
1590         stats->tot += ((uint64_t)E1000_READ_REG(hw, E1000_TOTH) << 32);
1591         stats->tot -= (stats->tpt - old_tpt) * ETHER_CRC_LEN;
1592
1593         stats->ptc64 += E1000_READ_REG(hw, E1000_PTC64);
1594         stats->ptc127 += E1000_READ_REG(hw, E1000_PTC127);
1595         stats->ptc255 += E1000_READ_REG(hw, E1000_PTC255);
1596         stats->ptc511 += E1000_READ_REG(hw, E1000_PTC511);
1597         stats->ptc1023 += E1000_READ_REG(hw, E1000_PTC1023);
1598         stats->ptc1522 += E1000_READ_REG(hw, E1000_PTC1522);
1599         stats->mptc += E1000_READ_REG(hw, E1000_MPTC);
1600         stats->bptc += E1000_READ_REG(hw, E1000_BPTC);
1601
1602         /* Interrupt Counts */
1603
1604         stats->iac += E1000_READ_REG(hw, E1000_IAC);
1605         stats->icrxptc += E1000_READ_REG(hw, E1000_ICRXPTC);
1606         stats->icrxatc += E1000_READ_REG(hw, E1000_ICRXATC);
1607         stats->ictxptc += E1000_READ_REG(hw, E1000_ICTXPTC);
1608         stats->ictxatc += E1000_READ_REG(hw, E1000_ICTXATC);
1609         stats->ictxqec += E1000_READ_REG(hw, E1000_ICTXQEC);
1610         stats->ictxqmtc += E1000_READ_REG(hw, E1000_ICTXQMTC);
1611         stats->icrxdmtc += E1000_READ_REG(hw, E1000_ICRXDMTC);
1612         stats->icrxoc += E1000_READ_REG(hw, E1000_ICRXOC);
1613
1614         /* Host to Card Statistics */
1615
1616         stats->cbtmpc += E1000_READ_REG(hw, E1000_CBTMPC);
1617         stats->htdpmc += E1000_READ_REG(hw, E1000_HTDPMC);
1618         stats->cbrdpc += E1000_READ_REG(hw, E1000_CBRDPC);
1619         stats->cbrmpc += E1000_READ_REG(hw, E1000_CBRMPC);
1620         stats->rpthc += E1000_READ_REG(hw, E1000_RPTHC);
1621         stats->hgptc += E1000_READ_REG(hw, E1000_HGPTC);
1622         stats->htcbdpc += E1000_READ_REG(hw, E1000_HTCBDPC);
1623         stats->hgorc += E1000_READ_REG(hw, E1000_HGORCL);
1624         stats->hgorc += ((uint64_t)E1000_READ_REG(hw, E1000_HGORCH) << 32);
1625         stats->hgorc -= (stats->rpthc - old_rpthc) * ETHER_CRC_LEN;
1626         stats->hgotc += E1000_READ_REG(hw, E1000_HGOTCL);
1627         stats->hgotc += ((uint64_t)E1000_READ_REG(hw, E1000_HGOTCH) << 32);
1628         stats->hgotc -= (stats->hgptc - old_hgptc) * ETHER_CRC_LEN;
1629         stats->lenerrs += E1000_READ_REG(hw, E1000_LENERRS);
1630         stats->scvpc += E1000_READ_REG(hw, E1000_SCVPC);
1631         stats->hrmpc += E1000_READ_REG(hw, E1000_HRMPC);
1632
1633         stats->algnerrc += E1000_READ_REG(hw, E1000_ALGNERRC);
1634         stats->rxerrc += E1000_READ_REG(hw, E1000_RXERRC);
1635         stats->tncrs += E1000_READ_REG(hw, E1000_TNCRS);
1636         stats->cexterr += E1000_READ_REG(hw, E1000_CEXTERR);
1637         stats->tsctc += E1000_READ_REG(hw, E1000_TSCTC);
1638         stats->tsctfc += E1000_READ_REG(hw, E1000_TSCTFC);
1639 }
1640
1641 static void
1642 eth_igb_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *rte_stats)
1643 {
1644         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1645         struct e1000_hw_stats *stats =
1646                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1647
1648         igb_read_stats_registers(hw, stats);
1649
1650         if (rte_stats == NULL)
1651                 return;
1652
1653         /* Rx Errors */
1654         rte_stats->imissed = stats->mpc;
1655         rte_stats->ierrors = stats->crcerrs +
1656                              stats->rlec + stats->ruc + stats->roc +
1657                              stats->rxerrc + stats->algnerrc + stats->cexterr;
1658
1659         /* Tx Errors */
1660         rte_stats->oerrors = stats->ecol + stats->latecol;
1661
1662         rte_stats->ipackets = stats->gprc;
1663         rte_stats->opackets = stats->gptc;
1664         rte_stats->ibytes   = stats->gorc;
1665         rte_stats->obytes   = stats->gotc;
1666 }
1667
1668 static void
1669 eth_igb_stats_reset(struct rte_eth_dev *dev)
1670 {
1671         struct e1000_hw_stats *hw_stats =
1672                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1673
1674         /* HW registers are cleared on read */
1675         eth_igb_stats_get(dev, NULL);
1676
1677         /* Reset software totals */
1678         memset(hw_stats, 0, sizeof(*hw_stats));
1679 }
1680
1681 static void
1682 eth_igb_xstats_reset(struct rte_eth_dev *dev)
1683 {
1684         struct e1000_hw_stats *stats =
1685                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1686
1687         /* HW registers are cleared on read */
1688         eth_igb_xstats_get(dev, NULL, IGB_NB_XSTATS);
1689
1690         /* Reset software totals */
1691         memset(stats, 0, sizeof(*stats));
1692 }
1693
1694 static int
1695 eth_igb_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstats *xstats,
1696                    unsigned n)
1697 {
1698         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1699         struct e1000_hw_stats *hw_stats =
1700                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1701         unsigned i;
1702
1703         if (n < IGB_NB_XSTATS)
1704                 return IGB_NB_XSTATS;
1705
1706         igb_read_stats_registers(hw, hw_stats);
1707
1708         /* If this is a reset xstats is NULL, and we have cleared the
1709          * registers by reading them.
1710          */
1711         if (!xstats)
1712                 return 0;
1713
1714         /* Extended stats */
1715         for (i = 0; i < IGB_NB_XSTATS; i++) {
1716                 snprintf(xstats[i].name, sizeof(xstats[i].name),
1717                          "%s", rte_igb_stats_strings[i].name);
1718                 xstats[i].value = *(uint64_t *)(((char *)hw_stats) +
1719                         rte_igb_stats_strings[i].offset);
1720         }
1721
1722         return IGB_NB_XSTATS;
1723 }
1724
1725 static void
1726 igbvf_read_stats_registers(struct e1000_hw *hw, struct e1000_vf_stats *hw_stats)
1727 {
1728         /* Good Rx packets, include VF loopback */
1729         UPDATE_VF_STAT(E1000_VFGPRC,
1730             hw_stats->last_gprc, hw_stats->gprc);
1731
1732         /* Good Rx octets, include VF loopback */
1733         UPDATE_VF_STAT(E1000_VFGORC,
1734             hw_stats->last_gorc, hw_stats->gorc);
1735
1736         /* Good Tx packets, include VF loopback */
1737         UPDATE_VF_STAT(E1000_VFGPTC,
1738             hw_stats->last_gptc, hw_stats->gptc);
1739
1740         /* Good Tx octets, include VF loopback */
1741         UPDATE_VF_STAT(E1000_VFGOTC,
1742             hw_stats->last_gotc, hw_stats->gotc);
1743
1744         /* Rx Multicst packets */
1745         UPDATE_VF_STAT(E1000_VFMPRC,
1746             hw_stats->last_mprc, hw_stats->mprc);
1747
1748         /* Good Rx loopback packets */
1749         UPDATE_VF_STAT(E1000_VFGPRLBC,
1750             hw_stats->last_gprlbc, hw_stats->gprlbc);
1751
1752         /* Good Rx loopback octets */
1753         UPDATE_VF_STAT(E1000_VFGORLBC,
1754             hw_stats->last_gorlbc, hw_stats->gorlbc);
1755
1756         /* Good Tx loopback packets */
1757         UPDATE_VF_STAT(E1000_VFGPTLBC,
1758             hw_stats->last_gptlbc, hw_stats->gptlbc);
1759
1760         /* Good Tx loopback octets */
1761         UPDATE_VF_STAT(E1000_VFGOTLBC,
1762             hw_stats->last_gotlbc, hw_stats->gotlbc);
1763 }
1764
1765 static int
1766 eth_igbvf_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstats *xstats,
1767                      unsigned n)
1768 {
1769         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1770         struct e1000_vf_stats *hw_stats = (struct e1000_vf_stats *)
1771                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1772         unsigned i;
1773
1774         if (n < IGBVF_NB_XSTATS)
1775                 return IGBVF_NB_XSTATS;
1776
1777         igbvf_read_stats_registers(hw, hw_stats);
1778
1779         if (!xstats)
1780                 return 0;
1781
1782         for (i = 0; i < IGBVF_NB_XSTATS; i++) {
1783                 snprintf(xstats[i].name, sizeof(xstats[i].name), "%s",
1784                          rte_igbvf_stats_strings[i].name);
1785                 xstats[i].value = *(uint64_t *)(((char *)hw_stats) +
1786                         rte_igbvf_stats_strings[i].offset);
1787         }
1788
1789         return IGBVF_NB_XSTATS;
1790 }
1791
1792 static void
1793 eth_igbvf_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *rte_stats)
1794 {
1795         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1796         struct e1000_vf_stats *hw_stats = (struct e1000_vf_stats *)
1797                           E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1798
1799         igbvf_read_stats_registers(hw, hw_stats);
1800
1801         if (rte_stats == NULL)
1802                 return;
1803
1804         rte_stats->ipackets = hw_stats->gprc;
1805         rte_stats->ibytes = hw_stats->gorc;
1806         rte_stats->opackets = hw_stats->gptc;
1807         rte_stats->obytes = hw_stats->gotc;
1808         rte_stats->imcasts = hw_stats->mprc;
1809         rte_stats->ilbpackets = hw_stats->gprlbc;
1810         rte_stats->ilbbytes = hw_stats->gorlbc;
1811         rte_stats->olbpackets = hw_stats->gptlbc;
1812         rte_stats->olbbytes = hw_stats->gotlbc;
1813 }
1814
1815 static void
1816 eth_igbvf_stats_reset(struct rte_eth_dev *dev)
1817 {
1818         struct e1000_vf_stats *hw_stats = (struct e1000_vf_stats*)
1819                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1820
1821         /* Sync HW register to the last stats */
1822         eth_igbvf_stats_get(dev, NULL);
1823
1824         /* reset HW current stats*/
1825         memset(&hw_stats->gprc, 0, sizeof(*hw_stats) -
1826                offsetof(struct e1000_vf_stats, gprc));
1827 }
1828
1829 static void
1830 eth_igb_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
1831 {
1832         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1833
1834         dev_info->min_rx_bufsize = 256; /* See BSIZE field of RCTL register. */
1835         dev_info->max_rx_pktlen  = 0x3FFF; /* See RLPML register. */
1836         dev_info->max_mac_addrs = hw->mac.rar_entry_count;
1837         dev_info->rx_offload_capa =
1838                 DEV_RX_OFFLOAD_VLAN_STRIP |
1839                 DEV_RX_OFFLOAD_IPV4_CKSUM |
1840                 DEV_RX_OFFLOAD_UDP_CKSUM  |
1841                 DEV_RX_OFFLOAD_TCP_CKSUM;
1842         dev_info->tx_offload_capa =
1843                 DEV_TX_OFFLOAD_VLAN_INSERT |
1844                 DEV_TX_OFFLOAD_IPV4_CKSUM  |
1845                 DEV_TX_OFFLOAD_UDP_CKSUM   |
1846                 DEV_TX_OFFLOAD_TCP_CKSUM   |
1847                 DEV_TX_OFFLOAD_SCTP_CKSUM  |
1848                 DEV_TX_OFFLOAD_TCP_TSO;
1849
1850         switch (hw->mac.type) {
1851         case e1000_82575:
1852                 dev_info->max_rx_queues = 4;
1853                 dev_info->max_tx_queues = 4;
1854                 dev_info->max_vmdq_pools = 0;
1855                 break;
1856
1857         case e1000_82576:
1858                 dev_info->max_rx_queues = 16;
1859                 dev_info->max_tx_queues = 16;
1860                 dev_info->max_vmdq_pools = ETH_8_POOLS;
1861                 dev_info->vmdq_queue_num = 16;
1862                 break;
1863
1864         case e1000_82580:
1865                 dev_info->max_rx_queues = 8;
1866                 dev_info->max_tx_queues = 8;
1867                 dev_info->max_vmdq_pools = ETH_8_POOLS;
1868                 dev_info->vmdq_queue_num = 8;
1869                 break;
1870
1871         case e1000_i350:
1872                 dev_info->max_rx_queues = 8;
1873                 dev_info->max_tx_queues = 8;
1874                 dev_info->max_vmdq_pools = ETH_8_POOLS;
1875                 dev_info->vmdq_queue_num = 8;
1876                 break;
1877
1878         case e1000_i354:
1879                 dev_info->max_rx_queues = 8;
1880                 dev_info->max_tx_queues = 8;
1881                 break;
1882
1883         case e1000_i210:
1884                 dev_info->max_rx_queues = 4;
1885                 dev_info->max_tx_queues = 4;
1886                 dev_info->max_vmdq_pools = 0;
1887                 break;
1888
1889         case e1000_i211:
1890                 dev_info->max_rx_queues = 2;
1891                 dev_info->max_tx_queues = 2;
1892                 dev_info->max_vmdq_pools = 0;
1893                 break;
1894
1895         default:
1896                 /* Should not happen */
1897                 break;
1898         }
1899         dev_info->hash_key_size = IGB_HKEY_MAX_INDEX * sizeof(uint32_t);
1900         dev_info->reta_size = ETH_RSS_RETA_SIZE_128;
1901         dev_info->flow_type_rss_offloads = IGB_RSS_OFFLOAD_ALL;
1902
1903         dev_info->default_rxconf = (struct rte_eth_rxconf) {
1904                 .rx_thresh = {
1905                         .pthresh = IGB_DEFAULT_RX_PTHRESH,
1906                         .hthresh = IGB_DEFAULT_RX_HTHRESH,
1907                         .wthresh = IGB_DEFAULT_RX_WTHRESH,
1908                 },
1909                 .rx_free_thresh = IGB_DEFAULT_RX_FREE_THRESH,
1910                 .rx_drop_en = 0,
1911         };
1912
1913         dev_info->default_txconf = (struct rte_eth_txconf) {
1914                 .tx_thresh = {
1915                         .pthresh = IGB_DEFAULT_TX_PTHRESH,
1916                         .hthresh = IGB_DEFAULT_TX_HTHRESH,
1917                         .wthresh = IGB_DEFAULT_TX_WTHRESH,
1918                 },
1919                 .txq_flags = 0,
1920         };
1921
1922         dev_info->rx_desc_lim = rx_desc_lim;
1923         dev_info->tx_desc_lim = tx_desc_lim;
1924
1925         dev_info->speed_capa = ETH_LINK_SPEED_10M_HD | ETH_LINK_SPEED_10M |
1926                         ETH_LINK_SPEED_100M_HD | ETH_LINK_SPEED_100M |
1927                         ETH_LINK_SPEED_1G;
1928 }
1929
1930 static const uint32_t *
1931 eth_igb_supported_ptypes_get(struct rte_eth_dev *dev)
1932 {
1933         static const uint32_t ptypes[] = {
1934                 /* refers to igb_rxd_pkt_info_to_pkt_type() */
1935                 RTE_PTYPE_L2_ETHER,
1936                 RTE_PTYPE_L3_IPV4,
1937                 RTE_PTYPE_L3_IPV4_EXT,
1938                 RTE_PTYPE_L3_IPV6,
1939                 RTE_PTYPE_L3_IPV6_EXT,
1940                 RTE_PTYPE_L4_TCP,
1941                 RTE_PTYPE_L4_UDP,
1942                 RTE_PTYPE_L4_SCTP,
1943                 RTE_PTYPE_TUNNEL_IP,
1944                 RTE_PTYPE_INNER_L3_IPV6,
1945                 RTE_PTYPE_INNER_L3_IPV6_EXT,
1946                 RTE_PTYPE_INNER_L4_TCP,
1947                 RTE_PTYPE_INNER_L4_UDP,
1948                 RTE_PTYPE_UNKNOWN
1949         };
1950
1951         if (dev->rx_pkt_burst == eth_igb_recv_pkts ||
1952             dev->rx_pkt_burst == eth_igb_recv_scattered_pkts)
1953                 return ptypes;
1954         return NULL;
1955 }
1956
1957 static void
1958 eth_igbvf_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
1959 {
1960         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1961
1962         dev_info->min_rx_bufsize = 256; /* See BSIZE field of RCTL register. */
1963         dev_info->max_rx_pktlen  = 0x3FFF; /* See RLPML register. */
1964         dev_info->max_mac_addrs = hw->mac.rar_entry_count;
1965         dev_info->rx_offload_capa = DEV_RX_OFFLOAD_VLAN_STRIP |
1966                                 DEV_RX_OFFLOAD_IPV4_CKSUM |
1967                                 DEV_RX_OFFLOAD_UDP_CKSUM  |
1968                                 DEV_RX_OFFLOAD_TCP_CKSUM;
1969         dev_info->tx_offload_capa = DEV_TX_OFFLOAD_VLAN_INSERT |
1970                                 DEV_TX_OFFLOAD_IPV4_CKSUM  |
1971                                 DEV_TX_OFFLOAD_UDP_CKSUM   |
1972                                 DEV_TX_OFFLOAD_TCP_CKSUM   |
1973                                 DEV_TX_OFFLOAD_SCTP_CKSUM  |
1974                                 DEV_TX_OFFLOAD_TCP_TSO;
1975         switch (hw->mac.type) {
1976         case e1000_vfadapt:
1977                 dev_info->max_rx_queues = 2;
1978                 dev_info->max_tx_queues = 2;
1979                 break;
1980         case e1000_vfadapt_i350:
1981                 dev_info->max_rx_queues = 1;
1982                 dev_info->max_tx_queues = 1;
1983                 break;
1984         default:
1985                 /* Should not happen */
1986                 break;
1987         }
1988
1989         dev_info->default_rxconf = (struct rte_eth_rxconf) {
1990                 .rx_thresh = {
1991                         .pthresh = IGB_DEFAULT_RX_PTHRESH,
1992                         .hthresh = IGB_DEFAULT_RX_HTHRESH,
1993                         .wthresh = IGB_DEFAULT_RX_WTHRESH,
1994                 },
1995                 .rx_free_thresh = IGB_DEFAULT_RX_FREE_THRESH,
1996                 .rx_drop_en = 0,
1997         };
1998
1999         dev_info->default_txconf = (struct rte_eth_txconf) {
2000                 .tx_thresh = {
2001                         .pthresh = IGB_DEFAULT_TX_PTHRESH,
2002                         .hthresh = IGB_DEFAULT_TX_HTHRESH,
2003                         .wthresh = IGB_DEFAULT_TX_WTHRESH,
2004                 },
2005                 .txq_flags = 0,
2006         };
2007
2008         dev_info->rx_desc_lim = rx_desc_lim;
2009         dev_info->tx_desc_lim = tx_desc_lim;
2010 }
2011
2012 /* return 0 means link status changed, -1 means not changed */
2013 static int
2014 eth_igb_link_update(struct rte_eth_dev *dev, int wait_to_complete)
2015 {
2016         struct e1000_hw *hw =
2017                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2018         struct rte_eth_link link, old;
2019         int link_check, count;
2020
2021         link_check = 0;
2022         hw->mac.get_link_status = 1;
2023
2024         /* possible wait-to-complete in up to 9 seconds */
2025         for (count = 0; count < IGB_LINK_UPDATE_CHECK_TIMEOUT; count ++) {
2026                 /* Read the real link status */
2027                 switch (hw->phy.media_type) {
2028                 case e1000_media_type_copper:
2029                         /* Do the work to read phy */
2030                         e1000_check_for_link(hw);
2031                         link_check = !hw->mac.get_link_status;
2032                         break;
2033
2034                 case e1000_media_type_fiber:
2035                         e1000_check_for_link(hw);
2036                         link_check = (E1000_READ_REG(hw, E1000_STATUS) &
2037                                       E1000_STATUS_LU);
2038                         break;
2039
2040                 case e1000_media_type_internal_serdes:
2041                         e1000_check_for_link(hw);
2042                         link_check = hw->mac.serdes_has_link;
2043                         break;
2044
2045                 /* VF device is type_unknown */
2046                 case e1000_media_type_unknown:
2047                         eth_igbvf_link_update(hw);
2048                         link_check = !hw->mac.get_link_status;
2049                         break;
2050
2051                 default:
2052                         break;
2053                 }
2054                 if (link_check || wait_to_complete == 0)
2055                         break;
2056                 rte_delay_ms(IGB_LINK_UPDATE_CHECK_INTERVAL);
2057         }
2058         memset(&link, 0, sizeof(link));
2059         rte_igb_dev_atomic_read_link_status(dev, &link);
2060         old = link;
2061
2062         /* Now we check if a transition has happened */
2063         if (link_check) {
2064                 uint16_t duplex, speed;
2065                 hw->mac.ops.get_link_up_info(hw, &speed, &duplex);
2066                 link.link_duplex = (duplex == FULL_DUPLEX) ?
2067                                 ETH_LINK_FULL_DUPLEX :
2068                                 ETH_LINK_HALF_DUPLEX;
2069                 link.link_speed = speed;
2070                 link.link_status = ETH_LINK_UP;
2071                 link.link_autoneg = !(dev->data->dev_conf.link_speeds &
2072                                 ETH_LINK_SPEED_FIXED);
2073         } else if (!link_check) {
2074                 link.link_speed = 0;
2075                 link.link_duplex = ETH_LINK_HALF_DUPLEX;
2076                 link.link_status = ETH_LINK_DOWN;
2077                 link.link_autoneg = ETH_LINK_SPEED_FIXED;
2078         }
2079         rte_igb_dev_atomic_write_link_status(dev, &link);
2080
2081         /* not changed */
2082         if (old.link_status == link.link_status)
2083                 return -1;
2084
2085         /* changed */
2086         return 0;
2087 }
2088
2089 /*
2090  * igb_hw_control_acquire sets CTRL_EXT:DRV_LOAD bit.
2091  * For ASF and Pass Through versions of f/w this means
2092  * that the driver is loaded.
2093  */
2094 static void
2095 igb_hw_control_acquire(struct e1000_hw *hw)
2096 {
2097         uint32_t ctrl_ext;
2098
2099         /* Let firmware know the driver has taken over */
2100         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
2101         E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
2102 }
2103
2104 /*
2105  * igb_hw_control_release resets CTRL_EXT:DRV_LOAD bit.
2106  * For ASF and Pass Through versions of f/w this means that the
2107  * driver is no longer loaded.
2108  */
2109 static void
2110 igb_hw_control_release(struct e1000_hw *hw)
2111 {
2112         uint32_t ctrl_ext;
2113
2114         /* Let firmware taken over control of h/w */
2115         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
2116         E1000_WRITE_REG(hw, E1000_CTRL_EXT,
2117                         ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
2118 }
2119
2120 /*
2121  * Bit of a misnomer, what this really means is
2122  * to enable OS management of the system... aka
2123  * to disable special hardware management features.
2124  */
2125 static void
2126 igb_init_manageability(struct e1000_hw *hw)
2127 {
2128         if (e1000_enable_mng_pass_thru(hw)) {
2129                 uint32_t manc2h = E1000_READ_REG(hw, E1000_MANC2H);
2130                 uint32_t manc = E1000_READ_REG(hw, E1000_MANC);
2131
2132                 /* disable hardware interception of ARP */
2133                 manc &= ~(E1000_MANC_ARP_EN);
2134
2135                 /* enable receiving management packets to the host */
2136                 manc |= E1000_MANC_EN_MNG2HOST;
2137                 manc2h |= 1 << 5;  /* Mng Port 623 */
2138                 manc2h |= 1 << 6;  /* Mng Port 664 */
2139                 E1000_WRITE_REG(hw, E1000_MANC2H, manc2h);
2140                 E1000_WRITE_REG(hw, E1000_MANC, manc);
2141         }
2142 }
2143
2144 static void
2145 igb_release_manageability(struct e1000_hw *hw)
2146 {
2147         if (e1000_enable_mng_pass_thru(hw)) {
2148                 uint32_t manc = E1000_READ_REG(hw, E1000_MANC);
2149
2150                 manc |= E1000_MANC_ARP_EN;
2151                 manc &= ~E1000_MANC_EN_MNG2HOST;
2152
2153                 E1000_WRITE_REG(hw, E1000_MANC, manc);
2154         }
2155 }
2156
2157 static void
2158 eth_igb_promiscuous_enable(struct rte_eth_dev *dev)
2159 {
2160         struct e1000_hw *hw =
2161                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2162         uint32_t rctl;
2163
2164         rctl = E1000_READ_REG(hw, E1000_RCTL);
2165         rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
2166         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2167 }
2168
2169 static void
2170 eth_igb_promiscuous_disable(struct rte_eth_dev *dev)
2171 {
2172         struct e1000_hw *hw =
2173                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2174         uint32_t rctl;
2175
2176         rctl = E1000_READ_REG(hw, E1000_RCTL);
2177         rctl &= (~E1000_RCTL_UPE);
2178         if (dev->data->all_multicast == 1)
2179                 rctl |= E1000_RCTL_MPE;
2180         else
2181                 rctl &= (~E1000_RCTL_MPE);
2182         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2183 }
2184
2185 static void
2186 eth_igb_allmulticast_enable(struct rte_eth_dev *dev)
2187 {
2188         struct e1000_hw *hw =
2189                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2190         uint32_t rctl;
2191
2192         rctl = E1000_READ_REG(hw, E1000_RCTL);
2193         rctl |= E1000_RCTL_MPE;
2194         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2195 }
2196
2197 static void
2198 eth_igb_allmulticast_disable(struct rte_eth_dev *dev)
2199 {
2200         struct e1000_hw *hw =
2201                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2202         uint32_t rctl;
2203
2204         if (dev->data->promiscuous == 1)
2205                 return; /* must remain in all_multicast mode */
2206         rctl = E1000_READ_REG(hw, E1000_RCTL);
2207         rctl &= (~E1000_RCTL_MPE);
2208         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2209 }
2210
2211 static int
2212 eth_igb_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
2213 {
2214         struct e1000_hw *hw =
2215                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2216         struct e1000_vfta * shadow_vfta =
2217                 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
2218         uint32_t vfta;
2219         uint32_t vid_idx;
2220         uint32_t vid_bit;
2221
2222         vid_idx = (uint32_t) ((vlan_id >> E1000_VFTA_ENTRY_SHIFT) &
2223                               E1000_VFTA_ENTRY_MASK);
2224         vid_bit = (uint32_t) (1 << (vlan_id & E1000_VFTA_ENTRY_BIT_SHIFT_MASK));
2225         vfta = E1000_READ_REG_ARRAY(hw, E1000_VFTA, vid_idx);
2226         if (on)
2227                 vfta |= vid_bit;
2228         else
2229                 vfta &= ~vid_bit;
2230         E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, vid_idx, vfta);
2231
2232         /* update local VFTA copy */
2233         shadow_vfta->vfta[vid_idx] = vfta;
2234
2235         return 0;
2236 }
2237
2238 static int
2239 eth_igb_vlan_tpid_set(struct rte_eth_dev *dev,
2240                       enum rte_vlan_type vlan_type,
2241                       uint16_t tpid)
2242 {
2243         struct e1000_hw *hw =
2244                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2245         uint32_t reg = ETHER_TYPE_VLAN;
2246         int ret = 0;
2247
2248         switch (vlan_type) {
2249         case ETH_VLAN_TYPE_INNER:
2250                 reg |= (tpid << 16);
2251                 E1000_WRITE_REG(hw, E1000_VET, reg);
2252                 break;
2253         default:
2254                 ret = -EINVAL;
2255                 PMD_DRV_LOG(ERR, "Unsupported vlan type %d\n", vlan_type);
2256                 break;
2257         }
2258
2259         return ret;
2260 }
2261
2262 static void
2263 igb_vlan_hw_filter_disable(struct rte_eth_dev *dev)
2264 {
2265         struct e1000_hw *hw =
2266                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2267         uint32_t reg;
2268
2269         /* Filter Table Disable */
2270         reg = E1000_READ_REG(hw, E1000_RCTL);
2271         reg &= ~E1000_RCTL_CFIEN;
2272         reg &= ~E1000_RCTL_VFE;
2273         E1000_WRITE_REG(hw, E1000_RCTL, reg);
2274 }
2275
2276 static void
2277 igb_vlan_hw_filter_enable(struct rte_eth_dev *dev)
2278 {
2279         struct e1000_hw *hw =
2280                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2281         struct e1000_vfta * shadow_vfta =
2282                 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
2283         uint32_t reg;
2284         int i;
2285
2286         /* Filter Table Enable, CFI not used for packet acceptance */
2287         reg = E1000_READ_REG(hw, E1000_RCTL);
2288         reg &= ~E1000_RCTL_CFIEN;
2289         reg |= E1000_RCTL_VFE;
2290         E1000_WRITE_REG(hw, E1000_RCTL, reg);
2291
2292         /* restore VFTA table */
2293         for (i = 0; i < IGB_VFTA_SIZE; i++)
2294                 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, i, shadow_vfta->vfta[i]);
2295 }
2296
2297 static void
2298 igb_vlan_hw_strip_disable(struct rte_eth_dev *dev)
2299 {
2300         struct e1000_hw *hw =
2301                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2302         uint32_t reg;
2303
2304         /* VLAN Mode Disable */
2305         reg = E1000_READ_REG(hw, E1000_CTRL);
2306         reg &= ~E1000_CTRL_VME;
2307         E1000_WRITE_REG(hw, E1000_CTRL, reg);
2308 }
2309
2310 static void
2311 igb_vlan_hw_strip_enable(struct rte_eth_dev *dev)
2312 {
2313         struct e1000_hw *hw =
2314                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2315         uint32_t reg;
2316
2317         /* VLAN Mode Enable */
2318         reg = E1000_READ_REG(hw, E1000_CTRL);
2319         reg |= E1000_CTRL_VME;
2320         E1000_WRITE_REG(hw, E1000_CTRL, reg);
2321 }
2322
2323 static void
2324 igb_vlan_hw_extend_disable(struct rte_eth_dev *dev)
2325 {
2326         struct e1000_hw *hw =
2327                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2328         uint32_t reg;
2329
2330         /* CTRL_EXT: Extended VLAN */
2331         reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
2332         reg &= ~E1000_CTRL_EXT_EXTEND_VLAN;
2333         E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg);
2334
2335         /* Update maximum packet length */
2336         if (dev->data->dev_conf.rxmode.jumbo_frame == 1)
2337                 E1000_WRITE_REG(hw, E1000_RLPML,
2338                         dev->data->dev_conf.rxmode.max_rx_pkt_len +
2339                                                 VLAN_TAG_SIZE);
2340 }
2341
2342 static void
2343 igb_vlan_hw_extend_enable(struct rte_eth_dev *dev)
2344 {
2345         struct e1000_hw *hw =
2346                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2347         uint32_t reg;
2348
2349         /* CTRL_EXT: Extended VLAN */
2350         reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
2351         reg |= E1000_CTRL_EXT_EXTEND_VLAN;
2352         E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg);
2353
2354         /* Update maximum packet length */
2355         if (dev->data->dev_conf.rxmode.jumbo_frame == 1)
2356                 E1000_WRITE_REG(hw, E1000_RLPML,
2357                         dev->data->dev_conf.rxmode.max_rx_pkt_len +
2358                                                 2 * VLAN_TAG_SIZE);
2359 }
2360
2361 static void
2362 eth_igb_vlan_offload_set(struct rte_eth_dev *dev, int mask)
2363 {
2364         if(mask & ETH_VLAN_STRIP_MASK){
2365                 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
2366                         igb_vlan_hw_strip_enable(dev);
2367                 else
2368                         igb_vlan_hw_strip_disable(dev);
2369         }
2370
2371         if(mask & ETH_VLAN_FILTER_MASK){
2372                 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
2373                         igb_vlan_hw_filter_enable(dev);
2374                 else
2375                         igb_vlan_hw_filter_disable(dev);
2376         }
2377
2378         if(mask & ETH_VLAN_EXTEND_MASK){
2379                 if (dev->data->dev_conf.rxmode.hw_vlan_extend)
2380                         igb_vlan_hw_extend_enable(dev);
2381                 else
2382                         igb_vlan_hw_extend_disable(dev);
2383         }
2384 }
2385
2386
2387 /**
2388  * It enables the interrupt mask and then enable the interrupt.
2389  *
2390  * @param dev
2391  *  Pointer to struct rte_eth_dev.
2392  *
2393  * @return
2394  *  - On success, zero.
2395  *  - On failure, a negative value.
2396  */
2397 static int
2398 eth_igb_lsc_interrupt_setup(struct rte_eth_dev *dev)
2399 {
2400         struct e1000_interrupt *intr =
2401                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2402
2403         intr->mask |= E1000_ICR_LSC;
2404
2405         return 0;
2406 }
2407
2408 /* It clears the interrupt causes and enables the interrupt.
2409  * It will be called once only during nic initialized.
2410  *
2411  * @param dev
2412  *  Pointer to struct rte_eth_dev.
2413  *
2414  * @return
2415  *  - On success, zero.
2416  *  - On failure, a negative value.
2417  */
2418 static int eth_igb_rxq_interrupt_setup(struct rte_eth_dev *dev)
2419 {
2420         uint32_t mask, regval;
2421         struct e1000_hw *hw =
2422                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2423         struct rte_eth_dev_info dev_info;
2424
2425         memset(&dev_info, 0, sizeof(dev_info));
2426         eth_igb_infos_get(dev, &dev_info);
2427
2428         mask = 0xFFFFFFFF >> (32 - dev_info.max_rx_queues);
2429         regval = E1000_READ_REG(hw, E1000_EIMS);
2430         E1000_WRITE_REG(hw, E1000_EIMS, regval | mask);
2431
2432         return 0;
2433 }
2434
2435 /*
2436  * It reads ICR and gets interrupt causes, check it and set a bit flag
2437  * to update link status.
2438  *
2439  * @param dev
2440  *  Pointer to struct rte_eth_dev.
2441  *
2442  * @return
2443  *  - On success, zero.
2444  *  - On failure, a negative value.
2445  */
2446 static int
2447 eth_igb_interrupt_get_status(struct rte_eth_dev *dev)
2448 {
2449         uint32_t icr;
2450         struct e1000_hw *hw =
2451                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2452         struct e1000_interrupt *intr =
2453                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2454
2455         igb_intr_disable(hw);
2456
2457         /* read-on-clear nic registers here */
2458         icr = E1000_READ_REG(hw, E1000_ICR);
2459
2460         intr->flags = 0;
2461         if (icr & E1000_ICR_LSC) {
2462                 intr->flags |= E1000_FLAG_NEED_LINK_UPDATE;
2463         }
2464
2465         if (icr & E1000_ICR_VMMB)
2466                 intr->flags |= E1000_FLAG_MAILBOX;
2467
2468         return 0;
2469 }
2470
2471 /*
2472  * It executes link_update after knowing an interrupt is prsent.
2473  *
2474  * @param dev
2475  *  Pointer to struct rte_eth_dev.
2476  *
2477  * @return
2478  *  - On success, zero.
2479  *  - On failure, a negative value.
2480  */
2481 static int
2482 eth_igb_interrupt_action(struct rte_eth_dev *dev)
2483 {
2484         struct e1000_hw *hw =
2485                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2486         struct e1000_interrupt *intr =
2487                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2488         uint32_t tctl, rctl;
2489         struct rte_eth_link link;
2490         int ret;
2491
2492         if (intr->flags & E1000_FLAG_MAILBOX) {
2493                 igb_pf_mbx_process(dev);
2494                 intr->flags &= ~E1000_FLAG_MAILBOX;
2495         }
2496
2497         igb_intr_enable(dev);
2498         rte_intr_enable(&(dev->pci_dev->intr_handle));
2499
2500         if (intr->flags & E1000_FLAG_NEED_LINK_UPDATE) {
2501                 intr->flags &= ~E1000_FLAG_NEED_LINK_UPDATE;
2502
2503                 /* set get_link_status to check register later */
2504                 hw->mac.get_link_status = 1;
2505                 ret = eth_igb_link_update(dev, 0);
2506
2507                 /* check if link has changed */
2508                 if (ret < 0)
2509                         return 0;
2510
2511                 memset(&link, 0, sizeof(link));
2512                 rte_igb_dev_atomic_read_link_status(dev, &link);
2513                 if (link.link_status) {
2514                         PMD_INIT_LOG(INFO,
2515                                      " Port %d: Link Up - speed %u Mbps - %s",
2516                                      dev->data->port_id,
2517                                      (unsigned)link.link_speed,
2518                                      link.link_duplex == ETH_LINK_FULL_DUPLEX ?
2519                                      "full-duplex" : "half-duplex");
2520                 } else {
2521                         PMD_INIT_LOG(INFO, " Port %d: Link Down",
2522                                      dev->data->port_id);
2523                 }
2524
2525                 PMD_INIT_LOG(DEBUG, "PCI Address: %04d:%02d:%02d:%d",
2526                              dev->pci_dev->addr.domain,
2527                              dev->pci_dev->addr.bus,
2528                              dev->pci_dev->addr.devid,
2529                              dev->pci_dev->addr.function);
2530                 tctl = E1000_READ_REG(hw, E1000_TCTL);
2531                 rctl = E1000_READ_REG(hw, E1000_RCTL);
2532                 if (link.link_status) {
2533                         /* enable Tx/Rx */
2534                         tctl |= E1000_TCTL_EN;
2535                         rctl |= E1000_RCTL_EN;
2536                 } else {
2537                         /* disable Tx/Rx */
2538                         tctl &= ~E1000_TCTL_EN;
2539                         rctl &= ~E1000_RCTL_EN;
2540                 }
2541                 E1000_WRITE_REG(hw, E1000_TCTL, tctl);
2542                 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2543                 E1000_WRITE_FLUSH(hw);
2544                 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC);
2545         }
2546
2547         return 0;
2548 }
2549
2550 /**
2551  * Interrupt handler which shall be registered at first.
2552  *
2553  * @param handle
2554  *  Pointer to interrupt handle.
2555  * @param param
2556  *  The address of parameter (struct rte_eth_dev *) regsitered before.
2557  *
2558  * @return
2559  *  void
2560  */
2561 static void
2562 eth_igb_interrupt_handler(__rte_unused struct rte_intr_handle *handle,
2563                                                         void *param)
2564 {
2565         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
2566
2567         eth_igb_interrupt_get_status(dev);
2568         eth_igb_interrupt_action(dev);
2569 }
2570
2571 static int
2572 eth_igb_led_on(struct rte_eth_dev *dev)
2573 {
2574         struct e1000_hw *hw;
2575
2576         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2577         return e1000_led_on(hw) == E1000_SUCCESS ? 0 : -ENOTSUP;
2578 }
2579
2580 static int
2581 eth_igb_led_off(struct rte_eth_dev *dev)
2582 {
2583         struct e1000_hw *hw;
2584
2585         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2586         return e1000_led_off(hw) == E1000_SUCCESS ? 0 : -ENOTSUP;
2587 }
2588
2589 static int
2590 eth_igb_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
2591 {
2592         struct e1000_hw *hw;
2593         uint32_t ctrl;
2594         int tx_pause;
2595         int rx_pause;
2596
2597         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2598         fc_conf->pause_time = hw->fc.pause_time;
2599         fc_conf->high_water = hw->fc.high_water;
2600         fc_conf->low_water = hw->fc.low_water;
2601         fc_conf->send_xon = hw->fc.send_xon;
2602         fc_conf->autoneg = hw->mac.autoneg;
2603
2604         /*
2605          * Return rx_pause and tx_pause status according to actual setting of
2606          * the TFCE and RFCE bits in the CTRL register.
2607          */
2608         ctrl = E1000_READ_REG(hw, E1000_CTRL);
2609         if (ctrl & E1000_CTRL_TFCE)
2610                 tx_pause = 1;
2611         else
2612                 tx_pause = 0;
2613
2614         if (ctrl & E1000_CTRL_RFCE)
2615                 rx_pause = 1;
2616         else
2617                 rx_pause = 0;
2618
2619         if (rx_pause && tx_pause)
2620                 fc_conf->mode = RTE_FC_FULL;
2621         else if (rx_pause)
2622                 fc_conf->mode = RTE_FC_RX_PAUSE;
2623         else if (tx_pause)
2624                 fc_conf->mode = RTE_FC_TX_PAUSE;
2625         else
2626                 fc_conf->mode = RTE_FC_NONE;
2627
2628         return 0;
2629 }
2630
2631 static int
2632 eth_igb_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
2633 {
2634         struct e1000_hw *hw;
2635         int err;
2636         enum e1000_fc_mode rte_fcmode_2_e1000_fcmode[] = {
2637                 e1000_fc_none,
2638                 e1000_fc_rx_pause,
2639                 e1000_fc_tx_pause,
2640                 e1000_fc_full
2641         };
2642         uint32_t rx_buf_size;
2643         uint32_t max_high_water;
2644         uint32_t rctl;
2645
2646         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2647         if (fc_conf->autoneg != hw->mac.autoneg)
2648                 return -ENOTSUP;
2649         rx_buf_size = igb_get_rx_buffer_size(hw);
2650         PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
2651
2652         /* At least reserve one Ethernet frame for watermark */
2653         max_high_water = rx_buf_size - ETHER_MAX_LEN;
2654         if ((fc_conf->high_water > max_high_water) ||
2655             (fc_conf->high_water < fc_conf->low_water)) {
2656                 PMD_INIT_LOG(ERR, "e1000 incorrect high/low water value");
2657                 PMD_INIT_LOG(ERR, "high water must <=  0x%x", max_high_water);
2658                 return -EINVAL;
2659         }
2660
2661         hw->fc.requested_mode = rte_fcmode_2_e1000_fcmode[fc_conf->mode];
2662         hw->fc.pause_time     = fc_conf->pause_time;
2663         hw->fc.high_water     = fc_conf->high_water;
2664         hw->fc.low_water      = fc_conf->low_water;
2665         hw->fc.send_xon       = fc_conf->send_xon;
2666
2667         err = e1000_setup_link_generic(hw);
2668         if (err == E1000_SUCCESS) {
2669
2670                 /* check if we want to forward MAC frames - driver doesn't have native
2671                  * capability to do that, so we'll write the registers ourselves */
2672
2673                 rctl = E1000_READ_REG(hw, E1000_RCTL);
2674
2675                 /* set or clear MFLCN.PMCF bit depending on configuration */
2676                 if (fc_conf->mac_ctrl_frame_fwd != 0)
2677                         rctl |= E1000_RCTL_PMCF;
2678                 else
2679                         rctl &= ~E1000_RCTL_PMCF;
2680
2681                 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2682                 E1000_WRITE_FLUSH(hw);
2683
2684                 return 0;
2685         }
2686
2687         PMD_INIT_LOG(ERR, "e1000_setup_link_generic = 0x%x", err);
2688         return -EIO;
2689 }
2690
2691 #define E1000_RAH_POOLSEL_SHIFT      (18)
2692 static void
2693 eth_igb_rar_set(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
2694                 uint32_t index, __rte_unused uint32_t pool)
2695 {
2696         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2697         uint32_t rah;
2698
2699         e1000_rar_set(hw, mac_addr->addr_bytes, index);
2700         rah = E1000_READ_REG(hw, E1000_RAH(index));
2701         rah |= (0x1 << (E1000_RAH_POOLSEL_SHIFT + pool));
2702         E1000_WRITE_REG(hw, E1000_RAH(index), rah);
2703 }
2704
2705 static void
2706 eth_igb_rar_clear(struct rte_eth_dev *dev, uint32_t index)
2707 {
2708         uint8_t addr[ETHER_ADDR_LEN];
2709         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2710
2711         memset(addr, 0, sizeof(addr));
2712
2713         e1000_rar_set(hw, addr, index);
2714 }
2715
2716 static void
2717 eth_igb_default_mac_addr_set(struct rte_eth_dev *dev,
2718                                 struct ether_addr *addr)
2719 {
2720         eth_igb_rar_clear(dev, 0);
2721
2722         eth_igb_rar_set(dev, (void *)addr, 0, 0);
2723 }
2724 /*
2725  * Virtual Function operations
2726  */
2727 static void
2728 igbvf_intr_disable(struct e1000_hw *hw)
2729 {
2730         PMD_INIT_FUNC_TRACE();
2731
2732         /* Clear interrupt mask to stop from interrupts being generated */
2733         E1000_WRITE_REG(hw, E1000_EIMC, 0xFFFF);
2734
2735         E1000_WRITE_FLUSH(hw);
2736 }
2737
2738 static void
2739 igbvf_stop_adapter(struct rte_eth_dev *dev)
2740 {
2741         u32 reg_val;
2742         u16 i;
2743         struct rte_eth_dev_info dev_info;
2744         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2745
2746         memset(&dev_info, 0, sizeof(dev_info));
2747         eth_igbvf_infos_get(dev, &dev_info);
2748
2749         /* Clear interrupt mask to stop from interrupts being generated */
2750         igbvf_intr_disable(hw);
2751
2752         /* Clear any pending interrupts, flush previous writes */
2753         E1000_READ_REG(hw, E1000_EICR);
2754
2755         /* Disable the transmit unit.  Each queue must be disabled. */
2756         for (i = 0; i < dev_info.max_tx_queues; i++)
2757                 E1000_WRITE_REG(hw, E1000_TXDCTL(i), E1000_TXDCTL_SWFLSH);
2758
2759         /* Disable the receive unit by stopping each queue */
2760         for (i = 0; i < dev_info.max_rx_queues; i++) {
2761                 reg_val = E1000_READ_REG(hw, E1000_RXDCTL(i));
2762                 reg_val &= ~E1000_RXDCTL_QUEUE_ENABLE;
2763                 E1000_WRITE_REG(hw, E1000_RXDCTL(i), reg_val);
2764                 while (E1000_READ_REG(hw, E1000_RXDCTL(i)) & E1000_RXDCTL_QUEUE_ENABLE)
2765                         ;
2766         }
2767
2768         /* flush all queues disables */
2769         E1000_WRITE_FLUSH(hw);
2770         msec_delay(2);
2771 }
2772
2773 static int eth_igbvf_link_update(struct e1000_hw *hw)
2774 {
2775         struct e1000_mbx_info *mbx = &hw->mbx;
2776         struct e1000_mac_info *mac = &hw->mac;
2777         int ret_val = E1000_SUCCESS;
2778
2779         PMD_INIT_LOG(DEBUG, "e1000_check_for_link_vf");
2780
2781         /*
2782          * We only want to run this if there has been a rst asserted.
2783          * in this case that could mean a link change, device reset,
2784          * or a virtual function reset
2785          */
2786
2787         /* If we were hit with a reset or timeout drop the link */
2788         if (!e1000_check_for_rst(hw, 0) || !mbx->timeout)
2789                 mac->get_link_status = TRUE;
2790
2791         if (!mac->get_link_status)
2792                 goto out;
2793
2794         /* if link status is down no point in checking to see if pf is up */
2795         if (!(E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU))
2796                 goto out;
2797
2798         /* if we passed all the tests above then the link is up and we no
2799          * longer need to check for link */
2800         mac->get_link_status = FALSE;
2801
2802 out:
2803         return ret_val;
2804 }
2805
2806
2807 static int
2808 igbvf_dev_configure(struct rte_eth_dev *dev)
2809 {
2810         struct rte_eth_conf* conf = &dev->data->dev_conf;
2811
2812         PMD_INIT_LOG(DEBUG, "Configured Virtual Function port id: %d",
2813                      dev->data->port_id);
2814
2815         /*
2816          * VF has no ability to enable/disable HW CRC
2817          * Keep the persistent behavior the same as Host PF
2818          */
2819 #ifndef RTE_LIBRTE_E1000_PF_DISABLE_STRIP_CRC
2820         if (!conf->rxmode.hw_strip_crc) {
2821                 PMD_INIT_LOG(NOTICE, "VF can't disable HW CRC Strip");
2822                 conf->rxmode.hw_strip_crc = 1;
2823         }
2824 #else
2825         if (conf->rxmode.hw_strip_crc) {
2826                 PMD_INIT_LOG(NOTICE, "VF can't enable HW CRC Strip");
2827                 conf->rxmode.hw_strip_crc = 0;
2828         }
2829 #endif
2830
2831         return 0;
2832 }
2833
2834 static int
2835 igbvf_dev_start(struct rte_eth_dev *dev)
2836 {
2837         struct e1000_hw *hw =
2838                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2839         struct e1000_adapter *adapter =
2840                 E1000_DEV_PRIVATE(dev->data->dev_private);
2841         int ret;
2842
2843         PMD_INIT_FUNC_TRACE();
2844
2845         hw->mac.ops.reset_hw(hw);
2846         adapter->stopped = 0;
2847
2848         /* Set all vfta */
2849         igbvf_set_vfta_all(dev,1);
2850
2851         eth_igbvf_tx_init(dev);
2852
2853         /* This can fail when allocating mbufs for descriptor rings */
2854         ret = eth_igbvf_rx_init(dev);
2855         if (ret) {
2856                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
2857                 igb_dev_clear_queues(dev);
2858                 return ret;
2859         }
2860
2861         return 0;
2862 }
2863
2864 static void
2865 igbvf_dev_stop(struct rte_eth_dev *dev)
2866 {
2867         PMD_INIT_FUNC_TRACE();
2868
2869         igbvf_stop_adapter(dev);
2870
2871         /*
2872           * Clear what we set, but we still keep shadow_vfta to
2873           * restore after device starts
2874           */
2875         igbvf_set_vfta_all(dev,0);
2876
2877         igb_dev_clear_queues(dev);
2878 }
2879
2880 static void
2881 igbvf_dev_close(struct rte_eth_dev *dev)
2882 {
2883         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2884         struct e1000_adapter *adapter =
2885                 E1000_DEV_PRIVATE(dev->data->dev_private);
2886         struct ether_addr addr;
2887
2888         PMD_INIT_FUNC_TRACE();
2889
2890         e1000_reset_hw(hw);
2891
2892         igbvf_dev_stop(dev);
2893         adapter->stopped = 1;
2894         igb_dev_free_queues(dev);
2895
2896         /**
2897          * reprogram the RAR with a zero mac address,
2898          * to ensure that the VF traffic goes to the PF
2899          * after stop, close and detach of the VF.
2900          **/
2901
2902         memset(&addr, 0, sizeof(addr));
2903         igbvf_default_mac_addr_set(dev, &addr);
2904 }
2905
2906 static void
2907 igbvf_promiscuous_enable(struct rte_eth_dev *dev)
2908 {
2909         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2910
2911         /* Set both unicast and multicast promisc */
2912         e1000_promisc_set_vf(hw, e1000_promisc_enabled);
2913 }
2914
2915 static void
2916 igbvf_promiscuous_disable(struct rte_eth_dev *dev)
2917 {
2918         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2919
2920         /* If in allmulticast mode leave multicast promisc */
2921         if (dev->data->all_multicast == 1)
2922                 e1000_promisc_set_vf(hw, e1000_promisc_multicast);
2923         else
2924                 e1000_promisc_set_vf(hw, e1000_promisc_disabled);
2925 }
2926
2927 static void
2928 igbvf_allmulticast_enable(struct rte_eth_dev *dev)
2929 {
2930         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2931
2932         /* In promiscuous mode multicast promisc already set */
2933         if (dev->data->promiscuous == 0)
2934                 e1000_promisc_set_vf(hw, e1000_promisc_multicast);
2935 }
2936
2937 static void
2938 igbvf_allmulticast_disable(struct rte_eth_dev *dev)
2939 {
2940         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2941
2942         /* In promiscuous mode leave multicast promisc enabled */
2943         if (dev->data->promiscuous == 0)
2944                 e1000_promisc_set_vf(hw, e1000_promisc_disabled);
2945 }
2946
2947 static int igbvf_set_vfta(struct e1000_hw *hw, uint16_t vid, bool on)
2948 {
2949         struct e1000_mbx_info *mbx = &hw->mbx;
2950         uint32_t msgbuf[2];
2951         s32 err;
2952
2953         /* After set vlan, vlan strip will also be enabled in igb driver*/
2954         msgbuf[0] = E1000_VF_SET_VLAN;
2955         msgbuf[1] = vid;
2956         /* Setting the 8 bit field MSG INFO to TRUE indicates "add" */
2957         if (on)
2958                 msgbuf[0] |= E1000_VF_SET_VLAN_ADD;
2959
2960         err = mbx->ops.write_posted(hw, msgbuf, 2, 0);
2961         if (err)
2962                 goto mbx_err;
2963
2964         err = mbx->ops.read_posted(hw, msgbuf, 2, 0);
2965         if (err)
2966                 goto mbx_err;
2967
2968         msgbuf[0] &= ~E1000_VT_MSGTYPE_CTS;
2969         if (msgbuf[0] == (E1000_VF_SET_VLAN | E1000_VT_MSGTYPE_NACK))
2970                 err = -EINVAL;
2971
2972 mbx_err:
2973         return err;
2974 }
2975
2976 static void igbvf_set_vfta_all(struct rte_eth_dev *dev, bool on)
2977 {
2978         struct e1000_hw *hw =
2979                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2980         struct e1000_vfta * shadow_vfta =
2981                 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
2982         int i = 0, j = 0, vfta = 0, mask = 1;
2983
2984         for (i = 0; i < IGB_VFTA_SIZE; i++){
2985                 vfta = shadow_vfta->vfta[i];
2986                 if(vfta){
2987                         mask = 1;
2988                         for (j = 0; j < 32; j++){
2989                                 if(vfta & mask)
2990                                         igbvf_set_vfta(hw,
2991                                                 (uint16_t)((i<<5)+j), on);
2992                                 mask<<=1;
2993                         }
2994                 }
2995         }
2996
2997 }
2998
2999 static int
3000 igbvf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
3001 {
3002         struct e1000_hw *hw =
3003                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3004         struct e1000_vfta * shadow_vfta =
3005                 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
3006         uint32_t vid_idx = 0;
3007         uint32_t vid_bit = 0;
3008         int ret = 0;
3009
3010         PMD_INIT_FUNC_TRACE();
3011
3012         /*vind is not used in VF driver, set to 0, check ixgbe_set_vfta_vf*/
3013         ret = igbvf_set_vfta(hw, vlan_id, !!on);
3014         if(ret){
3015                 PMD_INIT_LOG(ERR, "Unable to set VF vlan");
3016                 return ret;
3017         }
3018         vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
3019         vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
3020
3021         /*Save what we set and retore it after device reset*/
3022         if (on)
3023                 shadow_vfta->vfta[vid_idx] |= vid_bit;
3024         else
3025                 shadow_vfta->vfta[vid_idx] &= ~vid_bit;
3026
3027         return 0;
3028 }
3029
3030 static void
3031 igbvf_default_mac_addr_set(struct rte_eth_dev *dev, struct ether_addr *addr)
3032 {
3033         struct e1000_hw *hw =
3034                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3035
3036         /* index is not used by rar_set() */
3037         hw->mac.ops.rar_set(hw, (void *)addr, 0);
3038 }
3039
3040
3041 static int
3042 eth_igb_rss_reta_update(struct rte_eth_dev *dev,
3043                         struct rte_eth_rss_reta_entry64 *reta_conf,
3044                         uint16_t reta_size)
3045 {
3046         uint8_t i, j, mask;
3047         uint32_t reta, r;
3048         uint16_t idx, shift;
3049         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3050
3051         if (reta_size != ETH_RSS_RETA_SIZE_128) {
3052                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
3053                         "(%d) doesn't match the number hardware can supported "
3054                         "(%d)\n", reta_size, ETH_RSS_RETA_SIZE_128);
3055                 return -EINVAL;
3056         }
3057
3058         for (i = 0; i < reta_size; i += IGB_4_BIT_WIDTH) {
3059                 idx = i / RTE_RETA_GROUP_SIZE;
3060                 shift = i % RTE_RETA_GROUP_SIZE;
3061                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
3062                                                 IGB_4_BIT_MASK);
3063                 if (!mask)
3064                         continue;
3065                 if (mask == IGB_4_BIT_MASK)
3066                         r = 0;
3067                 else
3068                         r = E1000_READ_REG(hw, E1000_RETA(i >> 2));
3069                 for (j = 0, reta = 0; j < IGB_4_BIT_WIDTH; j++) {
3070                         if (mask & (0x1 << j))
3071                                 reta |= reta_conf[idx].reta[shift + j] <<
3072                                                         (CHAR_BIT * j);
3073                         else
3074                                 reta |= r & (IGB_8_BIT_MASK << (CHAR_BIT * j));
3075                 }
3076                 E1000_WRITE_REG(hw, E1000_RETA(i >> 2), reta);
3077         }
3078
3079         return 0;
3080 }
3081
3082 static int
3083 eth_igb_rss_reta_query(struct rte_eth_dev *dev,
3084                        struct rte_eth_rss_reta_entry64 *reta_conf,
3085                        uint16_t reta_size)
3086 {
3087         uint8_t i, j, mask;
3088         uint32_t reta;
3089         uint16_t idx, shift;
3090         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3091
3092         if (reta_size != ETH_RSS_RETA_SIZE_128) {
3093                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
3094                         "(%d) doesn't match the number hardware can supported "
3095                         "(%d)\n", reta_size, ETH_RSS_RETA_SIZE_128);
3096                 return -EINVAL;
3097         }
3098
3099         for (i = 0; i < reta_size; i += IGB_4_BIT_WIDTH) {
3100                 idx = i / RTE_RETA_GROUP_SIZE;
3101                 shift = i % RTE_RETA_GROUP_SIZE;
3102                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
3103                                                 IGB_4_BIT_MASK);
3104                 if (!mask)
3105                         continue;
3106                 reta = E1000_READ_REG(hw, E1000_RETA(i >> 2));
3107                 for (j = 0; j < IGB_4_BIT_WIDTH; j++) {
3108                         if (mask & (0x1 << j))
3109                                 reta_conf[idx].reta[shift + j] =
3110                                         ((reta >> (CHAR_BIT * j)) &
3111                                                 IGB_8_BIT_MASK);
3112                 }
3113         }
3114
3115         return 0;
3116 }
3117
3118 #define MAC_TYPE_FILTER_SUP(type)    do {\
3119         if ((type) != e1000_82580 && (type) != e1000_i350 &&\
3120                 (type) != e1000_82576)\
3121                 return -ENOTSUP;\
3122 } while (0)
3123
3124 static int
3125 eth_igb_syn_filter_set(struct rte_eth_dev *dev,
3126                         struct rte_eth_syn_filter *filter,
3127                         bool add)
3128 {
3129         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3130         uint32_t synqf, rfctl;
3131
3132         if (filter->queue >= IGB_MAX_RX_QUEUE_NUM)
3133                 return -EINVAL;
3134
3135         synqf = E1000_READ_REG(hw, E1000_SYNQF(0));
3136
3137         if (add) {
3138                 if (synqf & E1000_SYN_FILTER_ENABLE)
3139                         return -EINVAL;
3140
3141                 synqf = (uint32_t)(((filter->queue << E1000_SYN_FILTER_QUEUE_SHIFT) &
3142                         E1000_SYN_FILTER_QUEUE) | E1000_SYN_FILTER_ENABLE);
3143
3144                 rfctl = E1000_READ_REG(hw, E1000_RFCTL);
3145                 if (filter->hig_pri)
3146                         rfctl |= E1000_RFCTL_SYNQFP;
3147                 else
3148                         rfctl &= ~E1000_RFCTL_SYNQFP;
3149
3150                 E1000_WRITE_REG(hw, E1000_RFCTL, rfctl);
3151         } else {
3152                 if (!(synqf & E1000_SYN_FILTER_ENABLE))
3153                         return -ENOENT;
3154                 synqf = 0;
3155         }
3156
3157         E1000_WRITE_REG(hw, E1000_SYNQF(0), synqf);
3158         E1000_WRITE_FLUSH(hw);
3159         return 0;
3160 }
3161
3162 static int
3163 eth_igb_syn_filter_get(struct rte_eth_dev *dev,
3164                         struct rte_eth_syn_filter *filter)
3165 {
3166         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3167         uint32_t synqf, rfctl;
3168
3169         synqf = E1000_READ_REG(hw, E1000_SYNQF(0));
3170         if (synqf & E1000_SYN_FILTER_ENABLE) {
3171                 rfctl = E1000_READ_REG(hw, E1000_RFCTL);
3172                 filter->hig_pri = (rfctl & E1000_RFCTL_SYNQFP) ? 1 : 0;
3173                 filter->queue = (uint8_t)((synqf & E1000_SYN_FILTER_QUEUE) >>
3174                                 E1000_SYN_FILTER_QUEUE_SHIFT);
3175                 return 0;
3176         }
3177
3178         return -ENOENT;
3179 }
3180
3181 static int
3182 eth_igb_syn_filter_handle(struct rte_eth_dev *dev,
3183                         enum rte_filter_op filter_op,
3184                         void *arg)
3185 {
3186         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3187         int ret;
3188
3189         MAC_TYPE_FILTER_SUP(hw->mac.type);
3190
3191         if (filter_op == RTE_ETH_FILTER_NOP)
3192                 return 0;
3193
3194         if (arg == NULL) {
3195                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
3196                             filter_op);
3197                 return -EINVAL;
3198         }
3199
3200         switch (filter_op) {
3201         case RTE_ETH_FILTER_ADD:
3202                 ret = eth_igb_syn_filter_set(dev,
3203                                 (struct rte_eth_syn_filter *)arg,
3204                                 TRUE);
3205                 break;
3206         case RTE_ETH_FILTER_DELETE:
3207                 ret = eth_igb_syn_filter_set(dev,
3208                                 (struct rte_eth_syn_filter *)arg,
3209                                 FALSE);
3210                 break;
3211         case RTE_ETH_FILTER_GET:
3212                 ret = eth_igb_syn_filter_get(dev,
3213                                 (struct rte_eth_syn_filter *)arg);
3214                 break;
3215         default:
3216                 PMD_DRV_LOG(ERR, "unsupported operation %u\n", filter_op);
3217                 ret = -EINVAL;
3218                 break;
3219         }
3220
3221         return ret;
3222 }
3223
3224 #define MAC_TYPE_FILTER_SUP_EXT(type)    do {\
3225         if ((type) != e1000_82580 && (type) != e1000_i350)\
3226                 return -ENOSYS; \
3227 } while (0)
3228
3229 /* translate elements in struct rte_eth_ntuple_filter to struct e1000_2tuple_filter_info*/
3230 static inline int
3231 ntuple_filter_to_2tuple(struct rte_eth_ntuple_filter *filter,
3232                         struct e1000_2tuple_filter_info *filter_info)
3233 {
3234         if (filter->queue >= IGB_MAX_RX_QUEUE_NUM)
3235                 return -EINVAL;
3236         if (filter->priority > E1000_2TUPLE_MAX_PRI)
3237                 return -EINVAL;  /* filter index is out of range. */
3238         if (filter->tcp_flags > TCP_FLAG_ALL)
3239                 return -EINVAL;  /* flags is invalid. */
3240
3241         switch (filter->dst_port_mask) {
3242         case UINT16_MAX:
3243                 filter_info->dst_port_mask = 0;
3244                 filter_info->dst_port = filter->dst_port;
3245                 break;
3246         case 0:
3247                 filter_info->dst_port_mask = 1;
3248                 break;
3249         default:
3250                 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
3251                 return -EINVAL;
3252         }
3253
3254         switch (filter->proto_mask) {
3255         case UINT8_MAX:
3256                 filter_info->proto_mask = 0;
3257                 filter_info->proto = filter->proto;
3258                 break;
3259         case 0:
3260                 filter_info->proto_mask = 1;
3261                 break;
3262         default:
3263                 PMD_DRV_LOG(ERR, "invalid protocol mask.");
3264                 return -EINVAL;
3265         }
3266
3267         filter_info->priority = (uint8_t)filter->priority;
3268         if (filter->flags & RTE_NTUPLE_FLAGS_TCP_FLAG)
3269                 filter_info->tcp_flags = filter->tcp_flags;
3270         else
3271                 filter_info->tcp_flags = 0;
3272
3273         return 0;
3274 }
3275
3276 static inline struct e1000_2tuple_filter *
3277 igb_2tuple_filter_lookup(struct e1000_2tuple_filter_list *filter_list,
3278                         struct e1000_2tuple_filter_info *key)
3279 {
3280         struct e1000_2tuple_filter *it;
3281
3282         TAILQ_FOREACH(it, filter_list, entries) {
3283                 if (memcmp(key, &it->filter_info,
3284                         sizeof(struct e1000_2tuple_filter_info)) == 0) {
3285                         return it;
3286                 }
3287         }
3288         return NULL;
3289 }
3290
3291 /*
3292  * igb_add_2tuple_filter - add a 2tuple filter
3293  *
3294  * @param
3295  * dev: Pointer to struct rte_eth_dev.
3296  * ntuple_filter: ponter to the filter that will be added.
3297  *
3298  * @return
3299  *    - On success, zero.
3300  *    - On failure, a negative value.
3301  */
3302 static int
3303 igb_add_2tuple_filter(struct rte_eth_dev *dev,
3304                         struct rte_eth_ntuple_filter *ntuple_filter)
3305 {
3306         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3307         struct e1000_filter_info *filter_info =
3308                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3309         struct e1000_2tuple_filter *filter;
3310         uint32_t ttqf = E1000_TTQF_DISABLE_MASK;
3311         uint32_t imir, imir_ext = E1000_IMIREXT_SIZE_BP;
3312         int i, ret;
3313
3314         filter = rte_zmalloc("e1000_2tuple_filter",
3315                         sizeof(struct e1000_2tuple_filter), 0);
3316         if (filter == NULL)
3317                 return -ENOMEM;
3318
3319         ret = ntuple_filter_to_2tuple(ntuple_filter,
3320                                       &filter->filter_info);
3321         if (ret < 0) {
3322                 rte_free(filter);
3323                 return ret;
3324         }
3325         if (igb_2tuple_filter_lookup(&filter_info->twotuple_list,
3326                                          &filter->filter_info) != NULL) {
3327                 PMD_DRV_LOG(ERR, "filter exists.");
3328                 rte_free(filter);
3329                 return -EEXIST;
3330         }
3331         filter->queue = ntuple_filter->queue;
3332
3333         /*
3334          * look for an unused 2tuple filter index,
3335          * and insert the filter to list.
3336          */
3337         for (i = 0; i < E1000_MAX_TTQF_FILTERS; i++) {
3338                 if (!(filter_info->twotuple_mask & (1 << i))) {
3339                         filter_info->twotuple_mask |= 1 << i;
3340                         filter->index = i;
3341                         TAILQ_INSERT_TAIL(&filter_info->twotuple_list,
3342                                           filter,
3343                                           entries);
3344                         break;
3345                 }
3346         }
3347         if (i >= E1000_MAX_TTQF_FILTERS) {
3348                 PMD_DRV_LOG(ERR, "2tuple filters are full.");
3349                 rte_free(filter);
3350                 return -ENOSYS;
3351         }
3352
3353         imir = (uint32_t)(filter->filter_info.dst_port & E1000_IMIR_DSTPORT);
3354         if (filter->filter_info.dst_port_mask == 1) /* 1b means not compare. */
3355                 imir |= E1000_IMIR_PORT_BP;
3356         else
3357                 imir &= ~E1000_IMIR_PORT_BP;
3358
3359         imir |= filter->filter_info.priority << E1000_IMIR_PRIORITY_SHIFT;
3360
3361         ttqf |= E1000_TTQF_QUEUE_ENABLE;
3362         ttqf |= (uint32_t)(filter->queue << E1000_TTQF_QUEUE_SHIFT);
3363         ttqf |= (uint32_t)(filter->filter_info.proto & E1000_TTQF_PROTOCOL_MASK);
3364         if (filter->filter_info.proto_mask == 0)
3365                 ttqf &= ~E1000_TTQF_MASK_ENABLE;
3366
3367         /* tcp flags bits setting. */
3368         if (filter->filter_info.tcp_flags & TCP_FLAG_ALL) {
3369                 if (filter->filter_info.tcp_flags & TCP_URG_FLAG)
3370                         imir_ext |= E1000_IMIREXT_CTRL_URG;
3371                 if (filter->filter_info.tcp_flags & TCP_ACK_FLAG)
3372                         imir_ext |= E1000_IMIREXT_CTRL_ACK;
3373                 if (filter->filter_info.tcp_flags & TCP_PSH_FLAG)
3374                         imir_ext |= E1000_IMIREXT_CTRL_PSH;
3375                 if (filter->filter_info.tcp_flags & TCP_RST_FLAG)
3376                         imir_ext |= E1000_IMIREXT_CTRL_RST;
3377                 if (filter->filter_info.tcp_flags & TCP_SYN_FLAG)
3378                         imir_ext |= E1000_IMIREXT_CTRL_SYN;
3379                 if (filter->filter_info.tcp_flags & TCP_FIN_FLAG)
3380                         imir_ext |= E1000_IMIREXT_CTRL_FIN;
3381         } else
3382                 imir_ext |= E1000_IMIREXT_CTRL_BP;
3383         E1000_WRITE_REG(hw, E1000_IMIR(i), imir);
3384         E1000_WRITE_REG(hw, E1000_TTQF(i), ttqf);
3385         E1000_WRITE_REG(hw, E1000_IMIREXT(i), imir_ext);
3386         return 0;
3387 }
3388
3389 /*
3390  * igb_remove_2tuple_filter - remove a 2tuple filter
3391  *
3392  * @param
3393  * dev: Pointer to struct rte_eth_dev.
3394  * ntuple_filter: ponter to the filter that will be removed.
3395  *
3396  * @return
3397  *    - On success, zero.
3398  *    - On failure, a negative value.
3399  */
3400 static int
3401 igb_remove_2tuple_filter(struct rte_eth_dev *dev,
3402                         struct rte_eth_ntuple_filter *ntuple_filter)
3403 {
3404         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3405         struct e1000_filter_info *filter_info =
3406                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3407         struct e1000_2tuple_filter_info filter_2tuple;
3408         struct e1000_2tuple_filter *filter;
3409         int ret;
3410
3411         memset(&filter_2tuple, 0, sizeof(struct e1000_2tuple_filter_info));
3412         ret = ntuple_filter_to_2tuple(ntuple_filter,
3413                                       &filter_2tuple);
3414         if (ret < 0)
3415                 return ret;
3416
3417         filter = igb_2tuple_filter_lookup(&filter_info->twotuple_list,
3418                                          &filter_2tuple);
3419         if (filter == NULL) {
3420                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
3421                 return -ENOENT;
3422         }
3423
3424         filter_info->twotuple_mask &= ~(1 << filter->index);
3425         TAILQ_REMOVE(&filter_info->twotuple_list, filter, entries);
3426         rte_free(filter);
3427
3428         E1000_WRITE_REG(hw, E1000_TTQF(filter->index), E1000_TTQF_DISABLE_MASK);
3429         E1000_WRITE_REG(hw, E1000_IMIR(filter->index), 0);
3430         E1000_WRITE_REG(hw, E1000_IMIREXT(filter->index), 0);
3431         return 0;
3432 }
3433
3434 static inline struct e1000_flex_filter *
3435 eth_igb_flex_filter_lookup(struct e1000_flex_filter_list *filter_list,
3436                         struct e1000_flex_filter_info *key)
3437 {
3438         struct e1000_flex_filter *it;
3439
3440         TAILQ_FOREACH(it, filter_list, entries) {
3441                 if (memcmp(key, &it->filter_info,
3442                         sizeof(struct e1000_flex_filter_info)) == 0)
3443                         return it;
3444         }
3445
3446         return NULL;
3447 }
3448
3449 static int
3450 eth_igb_add_del_flex_filter(struct rte_eth_dev *dev,
3451                         struct rte_eth_flex_filter *filter,
3452                         bool add)
3453 {
3454         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3455         struct e1000_filter_info *filter_info =
3456                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3457         struct e1000_flex_filter *flex_filter, *it;
3458         uint32_t wufc, queueing, mask;
3459         uint32_t reg_off;
3460         uint8_t shift, i, j = 0;
3461
3462         flex_filter = rte_zmalloc("e1000_flex_filter",
3463                         sizeof(struct e1000_flex_filter), 0);
3464         if (flex_filter == NULL)
3465                 return -ENOMEM;
3466
3467         flex_filter->filter_info.len = filter->len;
3468         flex_filter->filter_info.priority = filter->priority;
3469         memcpy(flex_filter->filter_info.dwords, filter->bytes, filter->len);
3470         for (i = 0; i < RTE_ALIGN(filter->len, CHAR_BIT) / CHAR_BIT; i++) {
3471                 mask = 0;
3472                 /* reverse bits in flex filter's mask*/
3473                 for (shift = 0; shift < CHAR_BIT; shift++) {
3474                         if (filter->mask[i] & (0x01 << shift))
3475                                 mask |= (0x80 >> shift);
3476                 }
3477                 flex_filter->filter_info.mask[i] = mask;
3478         }
3479
3480         wufc = E1000_READ_REG(hw, E1000_WUFC);
3481         if (flex_filter->index < E1000_MAX_FHFT)
3482                 reg_off = E1000_FHFT(flex_filter->index);
3483         else
3484                 reg_off = E1000_FHFT_EXT(flex_filter->index - E1000_MAX_FHFT);
3485
3486         if (add) {
3487                 if (eth_igb_flex_filter_lookup(&filter_info->flex_list,
3488                                 &flex_filter->filter_info) != NULL) {
3489                         PMD_DRV_LOG(ERR, "filter exists.");
3490                         rte_free(flex_filter);
3491                         return -EEXIST;
3492                 }
3493                 flex_filter->queue = filter->queue;
3494                 /*
3495                  * look for an unused flex filter index
3496                  * and insert the filter into the list.
3497                  */
3498                 for (i = 0; i < E1000_MAX_FLEX_FILTERS; i++) {
3499                         if (!(filter_info->flex_mask & (1 << i))) {
3500                                 filter_info->flex_mask |= 1 << i;
3501                                 flex_filter->index = i;
3502                                 TAILQ_INSERT_TAIL(&filter_info->flex_list,
3503                                         flex_filter,
3504                                         entries);
3505                                 break;
3506                         }
3507                 }
3508                 if (i >= E1000_MAX_FLEX_FILTERS) {
3509                         PMD_DRV_LOG(ERR, "flex filters are full.");
3510                         rte_free(flex_filter);
3511                         return -ENOSYS;
3512                 }
3513
3514                 E1000_WRITE_REG(hw, E1000_WUFC, wufc | E1000_WUFC_FLEX_HQ |
3515                                 (E1000_WUFC_FLX0 << flex_filter->index));
3516                 queueing = filter->len |
3517                         (filter->queue << E1000_FHFT_QUEUEING_QUEUE_SHIFT) |
3518                         (filter->priority << E1000_FHFT_QUEUEING_PRIO_SHIFT);
3519                 E1000_WRITE_REG(hw, reg_off + E1000_FHFT_QUEUEING_OFFSET,
3520                                 queueing);
3521                 for (i = 0; i < E1000_FLEX_FILTERS_MASK_SIZE; i++) {
3522                         E1000_WRITE_REG(hw, reg_off,
3523                                         flex_filter->filter_info.dwords[j]);
3524                         reg_off += sizeof(uint32_t);
3525                         E1000_WRITE_REG(hw, reg_off,
3526                                         flex_filter->filter_info.dwords[++j]);
3527                         reg_off += sizeof(uint32_t);
3528                         E1000_WRITE_REG(hw, reg_off,
3529                                 (uint32_t)flex_filter->filter_info.mask[i]);
3530                         reg_off += sizeof(uint32_t) * 2;
3531                         ++j;
3532                 }
3533         } else {
3534                 it = eth_igb_flex_filter_lookup(&filter_info->flex_list,
3535                                 &flex_filter->filter_info);
3536                 if (it == NULL) {
3537                         PMD_DRV_LOG(ERR, "filter doesn't exist.");
3538                         rte_free(flex_filter);
3539                         return -ENOENT;
3540                 }
3541
3542                 for (i = 0; i < E1000_FHFT_SIZE_IN_DWD; i++)
3543                         E1000_WRITE_REG(hw, reg_off + i * sizeof(uint32_t), 0);
3544                 E1000_WRITE_REG(hw, E1000_WUFC, wufc &
3545                         (~(E1000_WUFC_FLX0 << it->index)));
3546
3547                 filter_info->flex_mask &= ~(1 << it->index);
3548                 TAILQ_REMOVE(&filter_info->flex_list, it, entries);
3549                 rte_free(it);
3550                 rte_free(flex_filter);
3551         }
3552
3553         return 0;
3554 }
3555
3556 static int
3557 eth_igb_get_flex_filter(struct rte_eth_dev *dev,
3558                         struct rte_eth_flex_filter *filter)
3559 {
3560         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3561         struct e1000_filter_info *filter_info =
3562                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3563         struct e1000_flex_filter flex_filter, *it;
3564         uint32_t wufc, queueing, wufc_en = 0;
3565
3566         memset(&flex_filter, 0, sizeof(struct e1000_flex_filter));
3567         flex_filter.filter_info.len = filter->len;
3568         flex_filter.filter_info.priority = filter->priority;
3569         memcpy(flex_filter.filter_info.dwords, filter->bytes, filter->len);
3570         memcpy(flex_filter.filter_info.mask, filter->mask,
3571                         RTE_ALIGN(filter->len, sizeof(char)) / sizeof(char));
3572
3573         it = eth_igb_flex_filter_lookup(&filter_info->flex_list,
3574                                 &flex_filter.filter_info);
3575         if (it == NULL) {
3576                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
3577                 return -ENOENT;
3578         }
3579
3580         wufc = E1000_READ_REG(hw, E1000_WUFC);
3581         wufc_en = E1000_WUFC_FLEX_HQ | (E1000_WUFC_FLX0 << it->index);
3582
3583         if ((wufc & wufc_en) == wufc_en) {
3584                 uint32_t reg_off = 0;
3585                 if (it->index < E1000_MAX_FHFT)
3586                         reg_off = E1000_FHFT(it->index);
3587                 else
3588                         reg_off = E1000_FHFT_EXT(it->index - E1000_MAX_FHFT);
3589
3590                 queueing = E1000_READ_REG(hw,
3591                                 reg_off + E1000_FHFT_QUEUEING_OFFSET);
3592                 filter->len = queueing & E1000_FHFT_QUEUEING_LEN;
3593                 filter->priority = (queueing & E1000_FHFT_QUEUEING_PRIO) >>
3594                         E1000_FHFT_QUEUEING_PRIO_SHIFT;
3595                 filter->queue = (queueing & E1000_FHFT_QUEUEING_QUEUE) >>
3596                         E1000_FHFT_QUEUEING_QUEUE_SHIFT;
3597                 return 0;
3598         }
3599         return -ENOENT;
3600 }
3601
3602 static int
3603 eth_igb_flex_filter_handle(struct rte_eth_dev *dev,
3604                         enum rte_filter_op filter_op,
3605                         void *arg)
3606 {
3607         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3608         struct rte_eth_flex_filter *filter;
3609         int ret = 0;
3610
3611         MAC_TYPE_FILTER_SUP_EXT(hw->mac.type);
3612
3613         if (filter_op == RTE_ETH_FILTER_NOP)
3614                 return ret;
3615
3616         if (arg == NULL) {
3617                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
3618                             filter_op);
3619                 return -EINVAL;
3620         }
3621
3622         filter = (struct rte_eth_flex_filter *)arg;
3623         if (filter->len == 0 || filter->len > E1000_MAX_FLEX_FILTER_LEN
3624             || filter->len % sizeof(uint64_t) != 0) {
3625                 PMD_DRV_LOG(ERR, "filter's length is out of range");
3626                 return -EINVAL;
3627         }
3628         if (filter->priority > E1000_MAX_FLEX_FILTER_PRI) {
3629                 PMD_DRV_LOG(ERR, "filter's priority is out of range");
3630                 return -EINVAL;
3631         }
3632
3633         switch (filter_op) {
3634         case RTE_ETH_FILTER_ADD:
3635                 ret = eth_igb_add_del_flex_filter(dev, filter, TRUE);
3636                 break;
3637         case RTE_ETH_FILTER_DELETE:
3638                 ret = eth_igb_add_del_flex_filter(dev, filter, FALSE);
3639                 break;
3640         case RTE_ETH_FILTER_GET:
3641                 ret = eth_igb_get_flex_filter(dev, filter);
3642                 break;
3643         default:
3644                 PMD_DRV_LOG(ERR, "unsupported operation %u", filter_op);
3645                 ret = -EINVAL;
3646                 break;
3647         }
3648
3649         return ret;
3650 }
3651
3652 /* translate elements in struct rte_eth_ntuple_filter to struct e1000_5tuple_filter_info*/
3653 static inline int
3654 ntuple_filter_to_5tuple_82576(struct rte_eth_ntuple_filter *filter,
3655                         struct e1000_5tuple_filter_info *filter_info)
3656 {
3657         if (filter->queue >= IGB_MAX_RX_QUEUE_NUM_82576)
3658                 return -EINVAL;
3659         if (filter->priority > E1000_2TUPLE_MAX_PRI)
3660                 return -EINVAL;  /* filter index is out of range. */
3661         if (filter->tcp_flags > TCP_FLAG_ALL)
3662                 return -EINVAL;  /* flags is invalid. */
3663
3664         switch (filter->dst_ip_mask) {
3665         case UINT32_MAX:
3666                 filter_info->dst_ip_mask = 0;
3667                 filter_info->dst_ip = filter->dst_ip;
3668                 break;
3669         case 0:
3670                 filter_info->dst_ip_mask = 1;
3671                 break;
3672         default:
3673                 PMD_DRV_LOG(ERR, "invalid dst_ip mask.");
3674                 return -EINVAL;
3675         }
3676
3677         switch (filter->src_ip_mask) {
3678         case UINT32_MAX:
3679                 filter_info->src_ip_mask = 0;
3680                 filter_info->src_ip = filter->src_ip;
3681                 break;
3682         case 0:
3683                 filter_info->src_ip_mask = 1;
3684                 break;
3685         default:
3686                 PMD_DRV_LOG(ERR, "invalid src_ip mask.");
3687                 return -EINVAL;
3688         }
3689
3690         switch (filter->dst_port_mask) {
3691         case UINT16_MAX:
3692                 filter_info->dst_port_mask = 0;
3693                 filter_info->dst_port = filter->dst_port;
3694                 break;
3695         case 0:
3696                 filter_info->dst_port_mask = 1;
3697                 break;
3698         default:
3699                 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
3700                 return -EINVAL;
3701         }
3702
3703         switch (filter->src_port_mask) {
3704         case UINT16_MAX:
3705                 filter_info->src_port_mask = 0;
3706                 filter_info->src_port = filter->src_port;
3707                 break;
3708         case 0:
3709                 filter_info->src_port_mask = 1;
3710                 break;
3711         default:
3712                 PMD_DRV_LOG(ERR, "invalid src_port mask.");
3713                 return -EINVAL;
3714         }
3715
3716         switch (filter->proto_mask) {
3717         case UINT8_MAX:
3718                 filter_info->proto_mask = 0;
3719                 filter_info->proto = filter->proto;
3720                 break;
3721         case 0:
3722                 filter_info->proto_mask = 1;
3723                 break;
3724         default:
3725                 PMD_DRV_LOG(ERR, "invalid protocol mask.");
3726                 return -EINVAL;
3727         }
3728
3729         filter_info->priority = (uint8_t)filter->priority;
3730         if (filter->flags & RTE_NTUPLE_FLAGS_TCP_FLAG)
3731                 filter_info->tcp_flags = filter->tcp_flags;
3732         else
3733                 filter_info->tcp_flags = 0;
3734
3735         return 0;
3736 }
3737
3738 static inline struct e1000_5tuple_filter *
3739 igb_5tuple_filter_lookup_82576(struct e1000_5tuple_filter_list *filter_list,
3740                         struct e1000_5tuple_filter_info *key)
3741 {
3742         struct e1000_5tuple_filter *it;
3743
3744         TAILQ_FOREACH(it, filter_list, entries) {
3745                 if (memcmp(key, &it->filter_info,
3746                         sizeof(struct e1000_5tuple_filter_info)) == 0) {
3747                         return it;
3748                 }
3749         }
3750         return NULL;
3751 }
3752
3753 /*
3754  * igb_add_5tuple_filter_82576 - add a 5tuple filter
3755  *
3756  * @param
3757  * dev: Pointer to struct rte_eth_dev.
3758  * ntuple_filter: ponter to the filter that will be added.
3759  *
3760  * @return
3761  *    - On success, zero.
3762  *    - On failure, a negative value.
3763  */
3764 static int
3765 igb_add_5tuple_filter_82576(struct rte_eth_dev *dev,
3766                         struct rte_eth_ntuple_filter *ntuple_filter)
3767 {
3768         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3769         struct e1000_filter_info *filter_info =
3770                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3771         struct e1000_5tuple_filter *filter;
3772         uint32_t ftqf = E1000_FTQF_VF_BP | E1000_FTQF_MASK;
3773         uint32_t spqf, imir, imir_ext = E1000_IMIREXT_SIZE_BP;
3774         uint8_t i;
3775         int ret;
3776
3777         filter = rte_zmalloc("e1000_5tuple_filter",
3778                         sizeof(struct e1000_5tuple_filter), 0);
3779         if (filter == NULL)
3780                 return -ENOMEM;
3781
3782         ret = ntuple_filter_to_5tuple_82576(ntuple_filter,
3783                                             &filter->filter_info);
3784         if (ret < 0) {
3785                 rte_free(filter);
3786                 return ret;
3787         }
3788
3789         if (igb_5tuple_filter_lookup_82576(&filter_info->fivetuple_list,
3790                                          &filter->filter_info) != NULL) {
3791                 PMD_DRV_LOG(ERR, "filter exists.");
3792                 rte_free(filter);
3793                 return -EEXIST;
3794         }
3795         filter->queue = ntuple_filter->queue;
3796
3797         /*
3798          * look for an unused 5tuple filter index,
3799          * and insert the filter to list.
3800          */
3801         for (i = 0; i < E1000_MAX_FTQF_FILTERS; i++) {
3802                 if (!(filter_info->fivetuple_mask & (1 << i))) {
3803                         filter_info->fivetuple_mask |= 1 << i;
3804                         filter->index = i;
3805                         TAILQ_INSERT_TAIL(&filter_info->fivetuple_list,
3806                                           filter,
3807                                           entries);
3808                         break;
3809                 }
3810         }
3811         if (i >= E1000_MAX_FTQF_FILTERS) {
3812                 PMD_DRV_LOG(ERR, "5tuple filters are full.");
3813                 rte_free(filter);
3814                 return -ENOSYS;
3815         }
3816
3817         ftqf |= filter->filter_info.proto & E1000_FTQF_PROTOCOL_MASK;
3818         if (filter->filter_info.src_ip_mask == 0) /* 0b means compare. */
3819                 ftqf &= ~E1000_FTQF_MASK_SOURCE_ADDR_BP;
3820         if (filter->filter_info.dst_ip_mask == 0)
3821                 ftqf &= ~E1000_FTQF_MASK_DEST_ADDR_BP;
3822         if (filter->filter_info.src_port_mask == 0)
3823                 ftqf &= ~E1000_FTQF_MASK_SOURCE_PORT_BP;
3824         if (filter->filter_info.proto_mask == 0)
3825                 ftqf &= ~E1000_FTQF_MASK_PROTO_BP;
3826         ftqf |= (filter->queue << E1000_FTQF_QUEUE_SHIFT) &
3827                 E1000_FTQF_QUEUE_MASK;
3828         ftqf |= E1000_FTQF_QUEUE_ENABLE;
3829         E1000_WRITE_REG(hw, E1000_FTQF(i), ftqf);
3830         E1000_WRITE_REG(hw, E1000_DAQF(i), filter->filter_info.dst_ip);
3831         E1000_WRITE_REG(hw, E1000_SAQF(i), filter->filter_info.src_ip);
3832
3833         spqf = filter->filter_info.src_port & E1000_SPQF_SRCPORT;
3834         E1000_WRITE_REG(hw, E1000_SPQF(i), spqf);
3835
3836         imir = (uint32_t)(filter->filter_info.dst_port & E1000_IMIR_DSTPORT);
3837         if (filter->filter_info.dst_port_mask == 1) /* 1b means not compare. */
3838                 imir |= E1000_IMIR_PORT_BP;
3839         else
3840                 imir &= ~E1000_IMIR_PORT_BP;
3841         imir |= filter->filter_info.priority << E1000_IMIR_PRIORITY_SHIFT;
3842
3843         /* tcp flags bits setting. */
3844         if (filter->filter_info.tcp_flags & TCP_FLAG_ALL) {
3845                 if (filter->filter_info.tcp_flags & TCP_URG_FLAG)
3846                         imir_ext |= E1000_IMIREXT_CTRL_URG;
3847                 if (filter->filter_info.tcp_flags & TCP_ACK_FLAG)
3848                         imir_ext |= E1000_IMIREXT_CTRL_ACK;
3849                 if (filter->filter_info.tcp_flags & TCP_PSH_FLAG)
3850                         imir_ext |= E1000_IMIREXT_CTRL_PSH;
3851                 if (filter->filter_info.tcp_flags & TCP_RST_FLAG)
3852                         imir_ext |= E1000_IMIREXT_CTRL_RST;
3853                 if (filter->filter_info.tcp_flags & TCP_SYN_FLAG)
3854                         imir_ext |= E1000_IMIREXT_CTRL_SYN;
3855                 if (filter->filter_info.tcp_flags & TCP_FIN_FLAG)
3856                         imir_ext |= E1000_IMIREXT_CTRL_FIN;
3857         } else
3858                 imir_ext |= E1000_IMIREXT_CTRL_BP;
3859         E1000_WRITE_REG(hw, E1000_IMIR(i), imir);
3860         E1000_WRITE_REG(hw, E1000_IMIREXT(i), imir_ext);
3861         return 0;
3862 }
3863
3864 /*
3865  * igb_remove_5tuple_filter_82576 - remove a 5tuple filter
3866  *
3867  * @param
3868  * dev: Pointer to struct rte_eth_dev.
3869  * ntuple_filter: ponter to the filter that will be removed.
3870  *
3871  * @return
3872  *    - On success, zero.
3873  *    - On failure, a negative value.
3874  */
3875 static int
3876 igb_remove_5tuple_filter_82576(struct rte_eth_dev *dev,
3877                                 struct rte_eth_ntuple_filter *ntuple_filter)
3878 {
3879         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3880         struct e1000_filter_info *filter_info =
3881                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3882         struct e1000_5tuple_filter_info filter_5tuple;
3883         struct e1000_5tuple_filter *filter;
3884         int ret;
3885
3886         memset(&filter_5tuple, 0, sizeof(struct e1000_5tuple_filter_info));
3887         ret = ntuple_filter_to_5tuple_82576(ntuple_filter,
3888                                             &filter_5tuple);
3889         if (ret < 0)
3890                 return ret;
3891
3892         filter = igb_5tuple_filter_lookup_82576(&filter_info->fivetuple_list,
3893                                          &filter_5tuple);
3894         if (filter == NULL) {
3895                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
3896                 return -ENOENT;
3897         }
3898
3899         filter_info->fivetuple_mask &= ~(1 << filter->index);
3900         TAILQ_REMOVE(&filter_info->fivetuple_list, filter, entries);
3901         rte_free(filter);
3902
3903         E1000_WRITE_REG(hw, E1000_FTQF(filter->index),
3904                         E1000_FTQF_VF_BP | E1000_FTQF_MASK);
3905         E1000_WRITE_REG(hw, E1000_DAQF(filter->index), 0);
3906         E1000_WRITE_REG(hw, E1000_SAQF(filter->index), 0);
3907         E1000_WRITE_REG(hw, E1000_SPQF(filter->index), 0);
3908         E1000_WRITE_REG(hw, E1000_IMIR(filter->index), 0);
3909         E1000_WRITE_REG(hw, E1000_IMIREXT(filter->index), 0);
3910         return 0;
3911 }
3912
3913 static int
3914 eth_igb_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
3915 {
3916         uint32_t rctl;
3917         struct e1000_hw *hw;
3918         struct rte_eth_dev_info dev_info;
3919         uint32_t frame_size = mtu + (ETHER_HDR_LEN + ETHER_CRC_LEN +
3920                                      VLAN_TAG_SIZE);
3921
3922         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3923
3924 #ifdef RTE_LIBRTE_82571_SUPPORT
3925         /* XXX: not bigger than max_rx_pktlen */
3926         if (hw->mac.type == e1000_82571)
3927                 return -ENOTSUP;
3928 #endif
3929         eth_igb_infos_get(dev, &dev_info);
3930
3931         /* check that mtu is within the allowed range */
3932         if ((mtu < ETHER_MIN_MTU) ||
3933             (frame_size > dev_info.max_rx_pktlen))
3934                 return -EINVAL;
3935
3936         /* refuse mtu that requires the support of scattered packets when this
3937          * feature has not been enabled before. */
3938         if (!dev->data->scattered_rx &&
3939             frame_size > dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)
3940                 return -EINVAL;
3941
3942         rctl = E1000_READ_REG(hw, E1000_RCTL);
3943
3944         /* switch to jumbo mode if needed */
3945         if (frame_size > ETHER_MAX_LEN) {
3946                 dev->data->dev_conf.rxmode.jumbo_frame = 1;
3947                 rctl |= E1000_RCTL_LPE;
3948         } else {
3949                 dev->data->dev_conf.rxmode.jumbo_frame = 0;
3950                 rctl &= ~E1000_RCTL_LPE;
3951         }
3952         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
3953
3954         /* update max frame size */
3955         dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
3956
3957         E1000_WRITE_REG(hw, E1000_RLPML,
3958                         dev->data->dev_conf.rxmode.max_rx_pkt_len);
3959
3960         return 0;
3961 }
3962
3963 /*
3964  * igb_add_del_ntuple_filter - add or delete a ntuple filter
3965  *
3966  * @param
3967  * dev: Pointer to struct rte_eth_dev.
3968  * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
3969  * add: if true, add filter, if false, remove filter
3970  *
3971  * @return
3972  *    - On success, zero.
3973  *    - On failure, a negative value.
3974  */
3975 static int
3976 igb_add_del_ntuple_filter(struct rte_eth_dev *dev,
3977                         struct rte_eth_ntuple_filter *ntuple_filter,
3978                         bool add)
3979 {
3980         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3981         int ret;
3982
3983         switch (ntuple_filter->flags) {
3984         case RTE_5TUPLE_FLAGS:
3985         case (RTE_5TUPLE_FLAGS | RTE_NTUPLE_FLAGS_TCP_FLAG):
3986                 if (hw->mac.type != e1000_82576)
3987                         return -ENOTSUP;
3988                 if (add)
3989                         ret = igb_add_5tuple_filter_82576(dev,
3990                                                           ntuple_filter);
3991                 else
3992                         ret = igb_remove_5tuple_filter_82576(dev,
3993                                                              ntuple_filter);
3994                 break;
3995         case RTE_2TUPLE_FLAGS:
3996         case (RTE_2TUPLE_FLAGS | RTE_NTUPLE_FLAGS_TCP_FLAG):
3997                 if (hw->mac.type != e1000_82580 && hw->mac.type != e1000_i350)
3998                         return -ENOTSUP;
3999                 if (add)
4000                         ret = igb_add_2tuple_filter(dev, ntuple_filter);
4001                 else
4002                         ret = igb_remove_2tuple_filter(dev, ntuple_filter);
4003                 break;
4004         default:
4005                 ret = -EINVAL;
4006                 break;
4007         }
4008
4009         return ret;
4010 }
4011
4012 /*
4013  * igb_get_ntuple_filter - get a ntuple filter
4014  *
4015  * @param
4016  * dev: Pointer to struct rte_eth_dev.
4017  * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
4018  *
4019  * @return
4020  *    - On success, zero.
4021  *    - On failure, a negative value.
4022  */
4023 static int
4024 igb_get_ntuple_filter(struct rte_eth_dev *dev,
4025                         struct rte_eth_ntuple_filter *ntuple_filter)
4026 {
4027         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4028         struct e1000_filter_info *filter_info =
4029                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4030         struct e1000_5tuple_filter_info filter_5tuple;
4031         struct e1000_2tuple_filter_info filter_2tuple;
4032         struct e1000_5tuple_filter *p_5tuple_filter;
4033         struct e1000_2tuple_filter *p_2tuple_filter;
4034         int ret;
4035
4036         switch (ntuple_filter->flags) {
4037         case RTE_5TUPLE_FLAGS:
4038         case (RTE_5TUPLE_FLAGS | RTE_NTUPLE_FLAGS_TCP_FLAG):
4039                 if (hw->mac.type != e1000_82576)
4040                         return -ENOTSUP;
4041                 memset(&filter_5tuple,
4042                         0,
4043                         sizeof(struct e1000_5tuple_filter_info));
4044                 ret = ntuple_filter_to_5tuple_82576(ntuple_filter,
4045                                                     &filter_5tuple);
4046                 if (ret < 0)
4047                         return ret;
4048                 p_5tuple_filter = igb_5tuple_filter_lookup_82576(
4049                                         &filter_info->fivetuple_list,
4050                                         &filter_5tuple);
4051                 if (p_5tuple_filter == NULL) {
4052                         PMD_DRV_LOG(ERR, "filter doesn't exist.");
4053                         return -ENOENT;
4054                 }
4055                 ntuple_filter->queue = p_5tuple_filter->queue;
4056                 break;
4057         case RTE_2TUPLE_FLAGS:
4058         case (RTE_2TUPLE_FLAGS | RTE_NTUPLE_FLAGS_TCP_FLAG):
4059                 if (hw->mac.type != e1000_82580 && hw->mac.type != e1000_i350)
4060                         return -ENOTSUP;
4061                 memset(&filter_2tuple,
4062                         0,
4063                         sizeof(struct e1000_2tuple_filter_info));
4064                 ret = ntuple_filter_to_2tuple(ntuple_filter, &filter_2tuple);
4065                 if (ret < 0)
4066                         return ret;
4067                 p_2tuple_filter = igb_2tuple_filter_lookup(
4068                                         &filter_info->twotuple_list,
4069                                         &filter_2tuple);
4070                 if (p_2tuple_filter == NULL) {
4071                         PMD_DRV_LOG(ERR, "filter doesn't exist.");
4072                         return -ENOENT;
4073                 }
4074                 ntuple_filter->queue = p_2tuple_filter->queue;
4075                 break;
4076         default:
4077                 ret = -EINVAL;
4078                 break;
4079         }
4080
4081         return 0;
4082 }
4083
4084 /*
4085  * igb_ntuple_filter_handle - Handle operations for ntuple filter.
4086  * @dev: pointer to rte_eth_dev structure
4087  * @filter_op:operation will be taken.
4088  * @arg: a pointer to specific structure corresponding to the filter_op
4089  */
4090 static int
4091 igb_ntuple_filter_handle(struct rte_eth_dev *dev,
4092                                 enum rte_filter_op filter_op,
4093                                 void *arg)
4094 {
4095         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4096         int ret;
4097
4098         MAC_TYPE_FILTER_SUP(hw->mac.type);
4099
4100         if (filter_op == RTE_ETH_FILTER_NOP)
4101                 return 0;
4102
4103         if (arg == NULL) {
4104                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
4105                             filter_op);
4106                 return -EINVAL;
4107         }
4108
4109         switch (filter_op) {
4110         case RTE_ETH_FILTER_ADD:
4111                 ret = igb_add_del_ntuple_filter(dev,
4112                         (struct rte_eth_ntuple_filter *)arg,
4113                         TRUE);
4114                 break;
4115         case RTE_ETH_FILTER_DELETE:
4116                 ret = igb_add_del_ntuple_filter(dev,
4117                         (struct rte_eth_ntuple_filter *)arg,
4118                         FALSE);
4119                 break;
4120         case RTE_ETH_FILTER_GET:
4121                 ret = igb_get_ntuple_filter(dev,
4122                         (struct rte_eth_ntuple_filter *)arg);
4123                 break;
4124         default:
4125                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
4126                 ret = -EINVAL;
4127                 break;
4128         }
4129         return ret;
4130 }
4131
4132 static inline int
4133 igb_ethertype_filter_lookup(struct e1000_filter_info *filter_info,
4134                         uint16_t ethertype)
4135 {
4136         int i;
4137
4138         for (i = 0; i < E1000_MAX_ETQF_FILTERS; i++) {
4139                 if (filter_info->ethertype_filters[i] == ethertype &&
4140                     (filter_info->ethertype_mask & (1 << i)))
4141                         return i;
4142         }
4143         return -1;
4144 }
4145
4146 static inline int
4147 igb_ethertype_filter_insert(struct e1000_filter_info *filter_info,
4148                         uint16_t ethertype)
4149 {
4150         int i;
4151
4152         for (i = 0; i < E1000_MAX_ETQF_FILTERS; i++) {
4153                 if (!(filter_info->ethertype_mask & (1 << i))) {
4154                         filter_info->ethertype_mask |= 1 << i;
4155                         filter_info->ethertype_filters[i] = ethertype;
4156                         return i;
4157                 }
4158         }
4159         return -1;
4160 }
4161
4162 static inline int
4163 igb_ethertype_filter_remove(struct e1000_filter_info *filter_info,
4164                         uint8_t idx)
4165 {
4166         if (idx >= E1000_MAX_ETQF_FILTERS)
4167                 return -1;
4168         filter_info->ethertype_mask &= ~(1 << idx);
4169         filter_info->ethertype_filters[idx] = 0;
4170         return idx;
4171 }
4172
4173
4174 static int
4175 igb_add_del_ethertype_filter(struct rte_eth_dev *dev,
4176                         struct rte_eth_ethertype_filter *filter,
4177                         bool add)
4178 {
4179         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4180         struct e1000_filter_info *filter_info =
4181                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4182         uint32_t etqf = 0;
4183         int ret;
4184
4185         if (filter->ether_type == ETHER_TYPE_IPv4 ||
4186                 filter->ether_type == ETHER_TYPE_IPv6) {
4187                 PMD_DRV_LOG(ERR, "unsupported ether_type(0x%04x) in"
4188                         " ethertype filter.", filter->ether_type);
4189                 return -EINVAL;
4190         }
4191
4192         if (filter->flags & RTE_ETHTYPE_FLAGS_MAC) {
4193                 PMD_DRV_LOG(ERR, "mac compare is unsupported.");
4194                 return -EINVAL;
4195         }
4196         if (filter->flags & RTE_ETHTYPE_FLAGS_DROP) {
4197                 PMD_DRV_LOG(ERR, "drop option is unsupported.");
4198                 return -EINVAL;
4199         }
4200
4201         ret = igb_ethertype_filter_lookup(filter_info, filter->ether_type);
4202         if (ret >= 0 && add) {
4203                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter exists.",
4204                             filter->ether_type);
4205                 return -EEXIST;
4206         }
4207         if (ret < 0 && !add) {
4208                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
4209                             filter->ether_type);
4210                 return -ENOENT;
4211         }
4212
4213         if (add) {
4214                 ret = igb_ethertype_filter_insert(filter_info,
4215                         filter->ether_type);
4216                 if (ret < 0) {
4217                         PMD_DRV_LOG(ERR, "ethertype filters are full.");
4218                         return -ENOSYS;
4219                 }
4220
4221                 etqf |= E1000_ETQF_FILTER_ENABLE | E1000_ETQF_QUEUE_ENABLE;
4222                 etqf |= (uint32_t)(filter->ether_type & E1000_ETQF_ETHERTYPE);
4223                 etqf |= filter->queue << E1000_ETQF_QUEUE_SHIFT;
4224         } else {
4225                 ret = igb_ethertype_filter_remove(filter_info, (uint8_t)ret);
4226                 if (ret < 0)
4227                         return -ENOSYS;
4228         }
4229         E1000_WRITE_REG(hw, E1000_ETQF(ret), etqf);
4230         E1000_WRITE_FLUSH(hw);
4231
4232         return 0;
4233 }
4234
4235 static int
4236 igb_get_ethertype_filter(struct rte_eth_dev *dev,
4237                         struct rte_eth_ethertype_filter *filter)
4238 {
4239         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4240         struct e1000_filter_info *filter_info =
4241                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4242         uint32_t etqf;
4243         int ret;
4244
4245         ret = igb_ethertype_filter_lookup(filter_info, filter->ether_type);
4246         if (ret < 0) {
4247                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
4248                             filter->ether_type);
4249                 return -ENOENT;
4250         }
4251
4252         etqf = E1000_READ_REG(hw, E1000_ETQF(ret));
4253         if (etqf & E1000_ETQF_FILTER_ENABLE) {
4254                 filter->ether_type = etqf & E1000_ETQF_ETHERTYPE;
4255                 filter->flags = 0;
4256                 filter->queue = (etqf & E1000_ETQF_QUEUE) >>
4257                                 E1000_ETQF_QUEUE_SHIFT;
4258                 return 0;
4259         }
4260
4261         return -ENOENT;
4262 }
4263
4264 /*
4265  * igb_ethertype_filter_handle - Handle operations for ethertype filter.
4266  * @dev: pointer to rte_eth_dev structure
4267  * @filter_op:operation will be taken.
4268  * @arg: a pointer to specific structure corresponding to the filter_op
4269  */
4270 static int
4271 igb_ethertype_filter_handle(struct rte_eth_dev *dev,
4272                                 enum rte_filter_op filter_op,
4273                                 void *arg)
4274 {
4275         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4276         int ret;
4277
4278         MAC_TYPE_FILTER_SUP(hw->mac.type);
4279
4280         if (filter_op == RTE_ETH_FILTER_NOP)
4281                 return 0;
4282
4283         if (arg == NULL) {
4284                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
4285                             filter_op);
4286                 return -EINVAL;
4287         }
4288
4289         switch (filter_op) {
4290         case RTE_ETH_FILTER_ADD:
4291                 ret = igb_add_del_ethertype_filter(dev,
4292                         (struct rte_eth_ethertype_filter *)arg,
4293                         TRUE);
4294                 break;
4295         case RTE_ETH_FILTER_DELETE:
4296                 ret = igb_add_del_ethertype_filter(dev,
4297                         (struct rte_eth_ethertype_filter *)arg,
4298                         FALSE);
4299                 break;
4300         case RTE_ETH_FILTER_GET:
4301                 ret = igb_get_ethertype_filter(dev,
4302                         (struct rte_eth_ethertype_filter *)arg);
4303                 break;
4304         default:
4305                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
4306                 ret = -EINVAL;
4307                 break;
4308         }
4309         return ret;
4310 }
4311
4312 static int
4313 eth_igb_filter_ctrl(struct rte_eth_dev *dev,
4314                      enum rte_filter_type filter_type,
4315                      enum rte_filter_op filter_op,
4316                      void *arg)
4317 {
4318         int ret = -EINVAL;
4319
4320         switch (filter_type) {
4321         case RTE_ETH_FILTER_NTUPLE:
4322                 ret = igb_ntuple_filter_handle(dev, filter_op, arg);
4323                 break;
4324         case RTE_ETH_FILTER_ETHERTYPE:
4325                 ret = igb_ethertype_filter_handle(dev, filter_op, arg);
4326                 break;
4327         case RTE_ETH_FILTER_SYN:
4328                 ret = eth_igb_syn_filter_handle(dev, filter_op, arg);
4329                 break;
4330         case RTE_ETH_FILTER_FLEXIBLE:
4331                 ret = eth_igb_flex_filter_handle(dev, filter_op, arg);
4332                 break;
4333         default:
4334                 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
4335                                                         filter_type);
4336                 break;
4337         }
4338
4339         return ret;
4340 }
4341
4342 static int
4343 eth_igb_set_mc_addr_list(struct rte_eth_dev *dev,
4344                          struct ether_addr *mc_addr_set,
4345                          uint32_t nb_mc_addr)
4346 {
4347         struct e1000_hw *hw;
4348
4349         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4350         e1000_update_mc_addr_list(hw, (u8 *)mc_addr_set, nb_mc_addr);
4351         return 0;
4352 }
4353
4354 static uint64_t
4355 igb_read_systime_cyclecounter(struct rte_eth_dev *dev)
4356 {
4357         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4358         uint64_t systime_cycles;
4359
4360         switch (hw->mac.type) {
4361         case e1000_i210:
4362         case e1000_i211:
4363                 /*
4364                  * Need to read System Time Residue Register to be able
4365                  * to read the other two registers.
4366                  */
4367                 E1000_READ_REG(hw, E1000_SYSTIMR);
4368                 /* SYSTIMEL stores ns and SYSTIMEH stores seconds. */
4369                 systime_cycles = (uint64_t)E1000_READ_REG(hw, E1000_SYSTIML);
4370                 systime_cycles += (uint64_t)E1000_READ_REG(hw, E1000_SYSTIMH)
4371                                 * NSEC_PER_SEC;
4372                 break;
4373         case e1000_82580:
4374         case e1000_i350:
4375         case e1000_i354:
4376                 /*
4377                  * Need to read System Time Residue Register to be able
4378                  * to read the other two registers.
4379                  */
4380                 E1000_READ_REG(hw, E1000_SYSTIMR);
4381                 systime_cycles = (uint64_t)E1000_READ_REG(hw, E1000_SYSTIML);
4382                 /* Only the 8 LSB are valid. */
4383                 systime_cycles |= (uint64_t)(E1000_READ_REG(hw, E1000_SYSTIMH)
4384                                 & 0xff) << 32;
4385                 break;
4386         default:
4387                 systime_cycles = (uint64_t)E1000_READ_REG(hw, E1000_SYSTIML);
4388                 systime_cycles |= (uint64_t)E1000_READ_REG(hw, E1000_SYSTIMH)
4389                                 << 32;
4390                 break;
4391         }
4392
4393         return systime_cycles;
4394 }
4395
4396 static uint64_t
4397 igb_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev)
4398 {
4399         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4400         uint64_t rx_tstamp_cycles;
4401
4402         switch (hw->mac.type) {
4403         case e1000_i210:
4404         case e1000_i211:
4405                 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
4406                 rx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_RXSTMPL);
4407                 rx_tstamp_cycles += (uint64_t)E1000_READ_REG(hw, E1000_RXSTMPH)
4408                                 * NSEC_PER_SEC;
4409                 break;
4410         case e1000_82580:
4411         case e1000_i350:
4412         case e1000_i354:
4413                 rx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_RXSTMPL);
4414                 /* Only the 8 LSB are valid. */
4415                 rx_tstamp_cycles |= (uint64_t)(E1000_READ_REG(hw, E1000_RXSTMPH)
4416                                 & 0xff) << 32;
4417                 break;
4418         default:
4419                 rx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_RXSTMPL);
4420                 rx_tstamp_cycles |= (uint64_t)E1000_READ_REG(hw, E1000_RXSTMPH)
4421                                 << 32;
4422                 break;
4423         }
4424
4425         return rx_tstamp_cycles;
4426 }
4427
4428 static uint64_t
4429 igb_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev)
4430 {
4431         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4432         uint64_t tx_tstamp_cycles;
4433
4434         switch (hw->mac.type) {
4435         case e1000_i210:
4436         case e1000_i211:
4437                 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
4438                 tx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_TXSTMPL);
4439                 tx_tstamp_cycles += (uint64_t)E1000_READ_REG(hw, E1000_TXSTMPH)
4440                                 * NSEC_PER_SEC;
4441                 break;
4442         case e1000_82580:
4443         case e1000_i350:
4444         case e1000_i354:
4445                 tx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_TXSTMPL);
4446                 /* Only the 8 LSB are valid. */
4447                 tx_tstamp_cycles |= (uint64_t)(E1000_READ_REG(hw, E1000_TXSTMPH)
4448                                 & 0xff) << 32;
4449                 break;
4450         default:
4451                 tx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_TXSTMPL);
4452                 tx_tstamp_cycles |= (uint64_t)E1000_READ_REG(hw, E1000_TXSTMPH)
4453                                 << 32;
4454                 break;
4455         }
4456
4457         return tx_tstamp_cycles;
4458 }
4459
4460 static void
4461 igb_start_timecounters(struct rte_eth_dev *dev)
4462 {
4463         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4464         struct e1000_adapter *adapter =
4465                 (struct e1000_adapter *)dev->data->dev_private;
4466         uint32_t incval = 1;
4467         uint32_t shift = 0;
4468         uint64_t mask = E1000_CYCLECOUNTER_MASK;
4469
4470         switch (hw->mac.type) {
4471         case e1000_82580:
4472         case e1000_i350:
4473         case e1000_i354:
4474                 /* 32 LSB bits + 8 MSB bits = 40 bits */
4475                 mask = (1ULL << 40) - 1;
4476                 /* fall-through */
4477         case e1000_i210:
4478         case e1000_i211:
4479                 /*
4480                  * Start incrementing the register
4481                  * used to timestamp PTP packets.
4482                  */
4483                 E1000_WRITE_REG(hw, E1000_TIMINCA, incval);
4484                 break;
4485         case e1000_82576:
4486                 incval = E1000_INCVALUE_82576;
4487                 shift = IGB_82576_TSYNC_SHIFT;
4488                 E1000_WRITE_REG(hw, E1000_TIMINCA,
4489                                 E1000_INCPERIOD_82576 | incval);
4490                 break;
4491         default:
4492                 /* Not supported */
4493                 return;
4494         }
4495
4496         memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter));
4497         memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
4498         memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
4499
4500         adapter->systime_tc.cc_mask = mask;
4501         adapter->systime_tc.cc_shift = shift;
4502         adapter->systime_tc.nsec_mask = (1ULL << shift) - 1;
4503
4504         adapter->rx_tstamp_tc.cc_mask = mask;
4505         adapter->rx_tstamp_tc.cc_shift = shift;
4506         adapter->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
4507
4508         adapter->tx_tstamp_tc.cc_mask = mask;
4509         adapter->tx_tstamp_tc.cc_shift = shift;
4510         adapter->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
4511 }
4512
4513 static int
4514 igb_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
4515 {
4516         struct e1000_adapter *adapter =
4517                         (struct e1000_adapter *)dev->data->dev_private;
4518
4519         adapter->systime_tc.nsec += delta;
4520         adapter->rx_tstamp_tc.nsec += delta;
4521         adapter->tx_tstamp_tc.nsec += delta;
4522
4523         return 0;
4524 }
4525
4526 static int
4527 igb_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
4528 {
4529         uint64_t ns;
4530         struct e1000_adapter *adapter =
4531                         (struct e1000_adapter *)dev->data->dev_private;
4532
4533         ns = rte_timespec_to_ns(ts);
4534
4535         /* Set the timecounters to a new value. */
4536         adapter->systime_tc.nsec = ns;
4537         adapter->rx_tstamp_tc.nsec = ns;
4538         adapter->tx_tstamp_tc.nsec = ns;
4539
4540         return 0;
4541 }
4542
4543 static int
4544 igb_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
4545 {
4546         uint64_t ns, systime_cycles;
4547         struct e1000_adapter *adapter =
4548                         (struct e1000_adapter *)dev->data->dev_private;
4549
4550         systime_cycles = igb_read_systime_cyclecounter(dev);
4551         ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles);
4552         *ts = rte_ns_to_timespec(ns);
4553
4554         return 0;
4555 }
4556
4557 static int
4558 igb_timesync_enable(struct rte_eth_dev *dev)
4559 {
4560         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4561         uint32_t tsync_ctl;
4562         uint32_t tsauxc;
4563
4564         /* Stop the timesync system time. */
4565         E1000_WRITE_REG(hw, E1000_TIMINCA, 0x0);
4566         /* Reset the timesync system time value. */
4567         switch (hw->mac.type) {
4568         case e1000_82580:
4569         case e1000_i350:
4570         case e1000_i354:
4571         case e1000_i210:
4572         case e1000_i211:
4573                 E1000_WRITE_REG(hw, E1000_SYSTIMR, 0x0);
4574                 /* fall-through */
4575         case e1000_82576:
4576                 E1000_WRITE_REG(hw, E1000_SYSTIML, 0x0);
4577                 E1000_WRITE_REG(hw, E1000_SYSTIMH, 0x0);
4578                 break;
4579         default:
4580                 /* Not supported. */
4581                 return -ENOTSUP;
4582         }
4583
4584         /* Enable system time for it isn't on by default. */
4585         tsauxc = E1000_READ_REG(hw, E1000_TSAUXC);
4586         tsauxc &= ~E1000_TSAUXC_DISABLE_SYSTIME;
4587         E1000_WRITE_REG(hw, E1000_TSAUXC, tsauxc);
4588
4589         igb_start_timecounters(dev);
4590
4591         /* Enable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
4592         E1000_WRITE_REG(hw, E1000_ETQF(E1000_ETQF_FILTER_1588),
4593                         (ETHER_TYPE_1588 |
4594                          E1000_ETQF_FILTER_ENABLE |
4595                          E1000_ETQF_1588));
4596
4597         /* Enable timestamping of received PTP packets. */
4598         tsync_ctl = E1000_READ_REG(hw, E1000_TSYNCRXCTL);
4599         tsync_ctl |= E1000_TSYNCRXCTL_ENABLED;
4600         E1000_WRITE_REG(hw, E1000_TSYNCRXCTL, tsync_ctl);
4601
4602         /* Enable Timestamping of transmitted PTP packets. */
4603         tsync_ctl = E1000_READ_REG(hw, E1000_TSYNCTXCTL);
4604         tsync_ctl |= E1000_TSYNCTXCTL_ENABLED;
4605         E1000_WRITE_REG(hw, E1000_TSYNCTXCTL, tsync_ctl);
4606
4607         return 0;
4608 }
4609
4610 static int
4611 igb_timesync_disable(struct rte_eth_dev *dev)
4612 {
4613         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4614         uint32_t tsync_ctl;
4615
4616         /* Disable timestamping of transmitted PTP packets. */
4617         tsync_ctl = E1000_READ_REG(hw, E1000_TSYNCTXCTL);
4618         tsync_ctl &= ~E1000_TSYNCTXCTL_ENABLED;
4619         E1000_WRITE_REG(hw, E1000_TSYNCTXCTL, tsync_ctl);
4620
4621         /* Disable timestamping of received PTP packets. */
4622         tsync_ctl = E1000_READ_REG(hw, E1000_TSYNCRXCTL);
4623         tsync_ctl &= ~E1000_TSYNCRXCTL_ENABLED;
4624         E1000_WRITE_REG(hw, E1000_TSYNCRXCTL, tsync_ctl);
4625
4626         /* Disable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
4627         E1000_WRITE_REG(hw, E1000_ETQF(E1000_ETQF_FILTER_1588), 0);
4628
4629         /* Stop incrementating the System Time registers. */
4630         E1000_WRITE_REG(hw, E1000_TIMINCA, 0);
4631
4632         return 0;
4633 }
4634
4635 static int
4636 igb_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
4637                                struct timespec *timestamp,
4638                                uint32_t flags __rte_unused)
4639 {
4640         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4641         struct e1000_adapter *adapter =
4642                         (struct e1000_adapter *)dev->data->dev_private;
4643         uint32_t tsync_rxctl;
4644         uint64_t rx_tstamp_cycles;
4645         uint64_t ns;
4646
4647         tsync_rxctl = E1000_READ_REG(hw, E1000_TSYNCRXCTL);
4648         if ((tsync_rxctl & E1000_TSYNCRXCTL_VALID) == 0)
4649                 return -EINVAL;
4650
4651         rx_tstamp_cycles = igb_read_rx_tstamp_cyclecounter(dev);
4652         ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles);
4653         *timestamp = rte_ns_to_timespec(ns);
4654
4655         return  0;
4656 }
4657
4658 static int
4659 igb_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
4660                                struct timespec *timestamp)
4661 {
4662         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4663         struct e1000_adapter *adapter =
4664                         (struct e1000_adapter *)dev->data->dev_private;
4665         uint32_t tsync_txctl;
4666         uint64_t tx_tstamp_cycles;
4667         uint64_t ns;
4668
4669         tsync_txctl = E1000_READ_REG(hw, E1000_TSYNCTXCTL);
4670         if ((tsync_txctl & E1000_TSYNCTXCTL_VALID) == 0)
4671                 return -EINVAL;
4672
4673         tx_tstamp_cycles = igb_read_tx_tstamp_cyclecounter(dev);
4674         ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles);
4675         *timestamp = rte_ns_to_timespec(ns);
4676
4677         return  0;
4678 }
4679
4680 static int
4681 eth_igb_get_reg_length(struct rte_eth_dev *dev __rte_unused)
4682 {
4683         int count = 0;
4684         int g_ind = 0;
4685         const struct reg_info *reg_group;
4686
4687         while ((reg_group = igb_regs[g_ind++]))
4688                 count += igb_reg_group_count(reg_group);
4689
4690         return count;
4691 }
4692
4693 static int
4694 igbvf_get_reg_length(struct rte_eth_dev *dev __rte_unused)
4695 {
4696         int count = 0;
4697         int g_ind = 0;
4698         const struct reg_info *reg_group;
4699
4700         while ((reg_group = igbvf_regs[g_ind++]))
4701                 count += igb_reg_group_count(reg_group);
4702
4703         return count;
4704 }
4705
4706 static int
4707 eth_igb_get_regs(struct rte_eth_dev *dev,
4708         struct rte_dev_reg_info *regs)
4709 {
4710         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4711         uint32_t *data = regs->data;
4712         int g_ind = 0;
4713         int count = 0;
4714         const struct reg_info *reg_group;
4715
4716         /* Support only full register dump */
4717         if ((regs->length == 0) ||
4718             (regs->length == (uint32_t)eth_igb_get_reg_length(dev))) {
4719                 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
4720                         hw->device_id;
4721                 while ((reg_group = igb_regs[g_ind++]))
4722                         count += igb_read_regs_group(dev, &data[count],
4723                                                         reg_group);
4724                 return 0;
4725         }
4726
4727         return -ENOTSUP;
4728 }
4729
4730 static int
4731 igbvf_get_regs(struct rte_eth_dev *dev,
4732         struct rte_dev_reg_info *regs)
4733 {
4734         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4735         uint32_t *data = regs->data;
4736         int g_ind = 0;
4737         int count = 0;
4738         const struct reg_info *reg_group;
4739
4740         /* Support only full register dump */
4741         if ((regs->length == 0) ||
4742             (regs->length == (uint32_t)igbvf_get_reg_length(dev))) {
4743                 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
4744                         hw->device_id;
4745                 while ((reg_group = igbvf_regs[g_ind++]))
4746                         count += igb_read_regs_group(dev, &data[count],
4747                                                         reg_group);
4748                 return 0;
4749         }
4750
4751         return -ENOTSUP;
4752 }
4753
4754 static int
4755 eth_igb_get_eeprom_length(struct rte_eth_dev *dev)
4756 {
4757         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4758
4759         /* Return unit is byte count */
4760         return hw->nvm.word_size * 2;
4761 }
4762
4763 static int
4764 eth_igb_get_eeprom(struct rte_eth_dev *dev,
4765         struct rte_dev_eeprom_info *in_eeprom)
4766 {
4767         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4768         struct e1000_nvm_info *nvm = &hw->nvm;
4769         uint16_t *data = in_eeprom->data;
4770         int first, length;
4771
4772         first = in_eeprom->offset >> 1;
4773         length = in_eeprom->length >> 1;
4774         if ((first >= hw->nvm.word_size) ||
4775             ((first + length) >= hw->nvm.word_size))
4776                 return -EINVAL;
4777
4778         in_eeprom->magic = hw->vendor_id |
4779                 ((uint32_t)hw->device_id << 16);
4780
4781         if ((nvm->ops.read) == NULL)
4782                 return -ENOTSUP;
4783
4784         return nvm->ops.read(hw, first, length, data);
4785 }
4786
4787 static int
4788 eth_igb_set_eeprom(struct rte_eth_dev *dev,
4789         struct rte_dev_eeprom_info *in_eeprom)
4790 {
4791         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4792         struct e1000_nvm_info *nvm = &hw->nvm;
4793         uint16_t *data = in_eeprom->data;
4794         int first, length;
4795
4796         first = in_eeprom->offset >> 1;
4797         length = in_eeprom->length >> 1;
4798         if ((first >= hw->nvm.word_size) ||
4799             ((first + length) >= hw->nvm.word_size))
4800                 return -EINVAL;
4801
4802         in_eeprom->magic = (uint32_t)hw->vendor_id |
4803                 ((uint32_t)hw->device_id << 16);
4804
4805         if ((nvm->ops.write) == NULL)
4806                 return -ENOTSUP;
4807         return nvm->ops.write(hw,  first, length, data);
4808 }
4809
4810 static struct rte_driver pmd_igb_drv = {
4811         .type = PMD_PDEV,
4812         .init = rte_igb_pmd_init,
4813 };
4814
4815 static struct rte_driver pmd_igbvf_drv = {
4816         .type = PMD_PDEV,
4817         .init = rte_igbvf_pmd_init,
4818 };
4819
4820 static int
4821 eth_igb_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
4822 {
4823         struct e1000_hw *hw =
4824                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4825         uint32_t mask = 1 << queue_id;
4826
4827         E1000_WRITE_REG(hw, E1000_EIMC, mask);
4828         E1000_WRITE_FLUSH(hw);
4829
4830         return 0;
4831 }
4832
4833 static int
4834 eth_igb_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
4835 {
4836         struct e1000_hw *hw =
4837                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4838         uint32_t mask = 1 << queue_id;
4839         uint32_t regval;
4840
4841         regval = E1000_READ_REG(hw, E1000_EIMS);
4842         E1000_WRITE_REG(hw, E1000_EIMS, regval | mask);
4843         E1000_WRITE_FLUSH(hw);
4844
4845         rte_intr_enable(&dev->pci_dev->intr_handle);
4846
4847         return 0;
4848 }
4849
4850 static void
4851 eth_igb_write_ivar(struct e1000_hw *hw, uint8_t  msix_vector,
4852                    uint8_t index, uint8_t offset)
4853 {
4854         uint32_t val = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index);
4855
4856         /* clear bits */
4857         val &= ~((uint32_t)0xFF << offset);
4858
4859         /* write vector and valid bit */
4860         val |= (msix_vector | E1000_IVAR_VALID) << offset;
4861
4862         E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, val);
4863 }
4864
4865 static void
4866 eth_igb_assign_msix_vector(struct e1000_hw *hw, int8_t direction,
4867                            uint8_t queue, uint8_t msix_vector)
4868 {
4869         uint32_t tmp = 0;
4870
4871         if (hw->mac.type == e1000_82575) {
4872                 if (direction == 0)
4873                         tmp = E1000_EICR_RX_QUEUE0 << queue;
4874                 else if (direction == 1)
4875                         tmp = E1000_EICR_TX_QUEUE0 << queue;
4876                 E1000_WRITE_REG(hw, E1000_MSIXBM(msix_vector), tmp);
4877         } else if (hw->mac.type == e1000_82576) {
4878                 if ((direction == 0) || (direction == 1))
4879                         eth_igb_write_ivar(hw, msix_vector, queue & 0x7,
4880                                            ((queue & 0x8) << 1) +
4881                                            8 * direction);
4882         } else if ((hw->mac.type == e1000_82580) ||
4883                         (hw->mac.type == e1000_i350) ||
4884                         (hw->mac.type == e1000_i354) ||
4885                         (hw->mac.type == e1000_i210) ||
4886                         (hw->mac.type == e1000_i211)) {
4887                 if ((direction == 0) || (direction == 1))
4888                         eth_igb_write_ivar(hw, msix_vector,
4889                                            queue >> 1,
4890                                            ((queue & 0x1) << 4) +
4891                                            8 * direction);
4892         }
4893 }
4894
4895 /* Sets up the hardware to generate MSI-X interrupts properly
4896  * @hw
4897  *  board private structure
4898  */
4899 static void
4900 eth_igb_configure_msix_intr(struct rte_eth_dev *dev)
4901 {
4902         int queue_id;
4903         uint32_t tmpval, regval, intr_mask;
4904         struct e1000_hw *hw =
4905                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4906         uint32_t vec = E1000_MISC_VEC_ID;
4907         uint32_t base = E1000_MISC_VEC_ID;
4908         uint32_t misc_shift = 0;
4909
4910         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
4911
4912         /* won't configure msix register if no mapping is done
4913          * between intr vector and event fd
4914          */
4915         if (!rte_intr_dp_is_en(intr_handle))
4916                 return;
4917
4918         if (rte_intr_allow_others(intr_handle)) {
4919                 vec = base = E1000_RX_VEC_START;
4920                 misc_shift = 1;
4921         }
4922
4923         /* set interrupt vector for other causes */
4924         if (hw->mac.type == e1000_82575) {
4925                 tmpval = E1000_READ_REG(hw, E1000_CTRL_EXT);
4926                 /* enable MSI-X PBA support */
4927                 tmpval |= E1000_CTRL_EXT_PBA_CLR;
4928
4929                 /* Auto-Mask interrupts upon ICR read */
4930                 tmpval |= E1000_CTRL_EXT_EIAME;
4931                 tmpval |= E1000_CTRL_EXT_IRCA;
4932
4933                 E1000_WRITE_REG(hw, E1000_CTRL_EXT, tmpval);
4934
4935                 /* enable msix_other interrupt */
4936                 E1000_WRITE_REG_ARRAY(hw, E1000_MSIXBM(0), 0, E1000_EIMS_OTHER);
4937                 regval = E1000_READ_REG(hw, E1000_EIAC);
4938                 E1000_WRITE_REG(hw, E1000_EIAC, regval | E1000_EIMS_OTHER);
4939                 regval = E1000_READ_REG(hw, E1000_EIAM);
4940                 E1000_WRITE_REG(hw, E1000_EIMS, regval | E1000_EIMS_OTHER);
4941         } else if ((hw->mac.type == e1000_82576) ||
4942                         (hw->mac.type == e1000_82580) ||
4943                         (hw->mac.type == e1000_i350) ||
4944                         (hw->mac.type == e1000_i354) ||
4945                         (hw->mac.type == e1000_i210) ||
4946                         (hw->mac.type == e1000_i211)) {
4947                 /* turn on MSI-X capability first */
4948                 E1000_WRITE_REG(hw, E1000_GPIE, E1000_GPIE_MSIX_MODE |
4949                                         E1000_GPIE_PBA | E1000_GPIE_EIAME |
4950                                         E1000_GPIE_NSICR);
4951                 intr_mask = RTE_LEN2MASK(intr_handle->nb_efd, uint32_t) <<
4952                         misc_shift;
4953                 regval = E1000_READ_REG(hw, E1000_EIAC);
4954                 E1000_WRITE_REG(hw, E1000_EIAC, regval | intr_mask);
4955
4956                 /* enable msix_other interrupt */
4957                 regval = E1000_READ_REG(hw, E1000_EIMS);
4958                 E1000_WRITE_REG(hw, E1000_EIMS, regval | intr_mask);
4959                 tmpval = (dev->data->nb_rx_queues | E1000_IVAR_VALID) << 8;
4960                 E1000_WRITE_REG(hw, E1000_IVAR_MISC, tmpval);
4961         }
4962
4963         /* use EIAM to auto-mask when MSI-X interrupt
4964          * is asserted, this saves a register write for every interrupt
4965          */
4966         intr_mask = RTE_LEN2MASK(intr_handle->nb_efd, uint32_t) <<
4967                 misc_shift;
4968         regval = E1000_READ_REG(hw, E1000_EIAM);
4969         E1000_WRITE_REG(hw, E1000_EIAM, regval | intr_mask);
4970
4971         for (queue_id = 0; queue_id < dev->data->nb_rx_queues; queue_id++) {
4972                 eth_igb_assign_msix_vector(hw, 0, queue_id, vec);
4973                 intr_handle->intr_vec[queue_id] = vec;
4974                 if (vec < base + intr_handle->nb_efd - 1)
4975                         vec++;
4976         }
4977
4978         E1000_WRITE_FLUSH(hw);
4979 }
4980
4981 PMD_REGISTER_DRIVER(pmd_igb_drv);
4982 PMD_REGISTER_DRIVER(pmd_igbvf_drv);