drivers/net/e1000/igb_ethdev.c

   1 /*-
   2  *   BSD LICENSE
   3  *
   4  *   Copyright(c) 2010-2016 Intel Corporation. All rights reserved.
   5  *   All rights reserved.
   6  *
   7  *   Redistribution and use in source and binary forms, with or without
   8  *   modification, are permitted provided that the following conditions
   9  *   are met:
  10  *
  11  *     * Redistributions of source code must retain the above copyright
  12  *       notice, this list of conditions and the following disclaimer.
  13  *     * Redistributions in binary form must reproduce the above copyright
  14  *       notice, this list of conditions and the following disclaimer in
  15  *       the documentation and/or other materials provided with the
  16  *       distribution.
  17  *     * Neither the name of Intel Corporation nor the names of its
  18  *       contributors may be used to endorse or promote products derived
  19  *       from this software without specific prior written permission.
  20  *
  21  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 #include <sys/queue.h>
  35 #include <stdio.h>
  36 #include <errno.h>
  37 #include <stdint.h>
  38 #include <stdarg.h>
  39
  40 #include <rte_common.h>
  41 #include <rte_interrupts.h>
  42 #include <rte_byteorder.h>
  43 #include <rte_log.h>
  44 #include <rte_debug.h>
  45 #include <rte_pci.h>
  46 #include <rte_ether.h>
  47 #include <rte_ethdev.h>
  48 #include <rte_ethdev_pci.h>
  49 #include <rte_memory.h>
  50 #include <rte_memzone.h>
  51 #include <rte_eal.h>
  52 #include <rte_atomic.h>
  53 #include <rte_malloc.h>
  54 #include <rte_dev.h>
  55
  56 #include "e1000_logs.h"
  57 #include "base/e1000_api.h"
  58 #include "e1000_ethdev.h"
  59 #include "igb_regs.h"
  60
  61 /*
  62  * Default values for port configuration
  63  */
  64 #define IGB_DEFAULT_RX_FREE_THRESH  32
  65
  66 #define IGB_DEFAULT_RX_PTHRESH      ((hw->mac.type == e1000_i354) ? 12 : 8)
  67 #define IGB_DEFAULT_RX_HTHRESH      8
  68 #define IGB_DEFAULT_RX_WTHRESH      ((hw->mac.type == e1000_82576) ? 1 : 4)
  69
  70 #define IGB_DEFAULT_TX_PTHRESH      ((hw->mac.type == e1000_i354) ? 20 : 8)
  71 #define IGB_DEFAULT_TX_HTHRESH      1
  72 #define IGB_DEFAULT_TX_WTHRESH      ((hw->mac.type == e1000_82576) ? 1 : 16)
  73
  74 #define IGB_HKEY_MAX_INDEX 10
  75
  76 /* Bit shift and mask */
  77 #define IGB_4_BIT_WIDTH  (CHAR_BIT / 2)
  78 #define IGB_4_BIT_MASK   RTE_LEN2MASK(IGB_4_BIT_WIDTH, uint8_t)
  79 #define IGB_8_BIT_WIDTH  CHAR_BIT
  80 #define IGB_8_BIT_MASK   UINT8_MAX
  81
  82 /* Additional timesync values. */
  83 #define E1000_CYCLECOUNTER_MASK      0xffffffffffffffffULL
  84 #define E1000_ETQF_FILTER_1588       3
  85 #define IGB_82576_TSYNC_SHIFT        16
  86 #define E1000_INCPERIOD_82576        (1 << E1000_TIMINCA_16NS_SHIFT)
  87 #define E1000_INCVALUE_82576         (16 << IGB_82576_TSYNC_SHIFT)
  88 #define E1000_TSAUXC_DISABLE_SYSTIME 0x80000000
  89
  90 #define E1000_VTIVAR_MISC                0x01740
  91 #define E1000_VTIVAR_MISC_MASK           0xFF
  92 #define E1000_VTIVAR_VALID               0x80
  93 #define E1000_VTIVAR_MISC_MAILBOX        0
  94 #define E1000_VTIVAR_MISC_INTR_MASK      0x3
  95
  96 /* External VLAN Enable bit mask */
  97 #define E1000_CTRL_EXT_EXT_VLAN      (1 << 26)
  98
  99 /* External VLAN Ether Type bit mask and shift */
 100 #define E1000_VET_VET_EXT            0xFFFF0000
 101 #define E1000_VET_VET_EXT_SHIFT      16
 102
 103 static int  eth_igb_configure(struct rte_eth_dev *dev);
 104 static int  eth_igb_start(struct rte_eth_dev *dev);
 105 static void eth_igb_stop(struct rte_eth_dev *dev);
 106 static int  eth_igb_dev_set_link_up(struct rte_eth_dev *dev);
 107 static int  eth_igb_dev_set_link_down(struct rte_eth_dev *dev);
 108 static void eth_igb_close(struct rte_eth_dev *dev);
 109 static void eth_igb_promiscuous_enable(struct rte_eth_dev *dev);
 110 static void eth_igb_promiscuous_disable(struct rte_eth_dev *dev);
 111 static void eth_igb_allmulticast_enable(struct rte_eth_dev *dev);
 112 static void eth_igb_allmulticast_disable(struct rte_eth_dev *dev);
 113 static int  eth_igb_link_update(struct rte_eth_dev *dev,
 114                                 int wait_to_complete);
 115 static void eth_igb_stats_get(struct rte_eth_dev *dev,
 116                                 struct rte_eth_stats *rte_stats);
 117 static int eth_igb_xstats_get(struct rte_eth_dev *dev,
 118                               struct rte_eth_xstat *xstats, unsigned n);
 119 static int eth_igb_xstats_get_by_id(struct rte_eth_dev *dev,
 120                 const uint64_t *ids,
 121                 uint64_t *values, unsigned int n);
 122 static int eth_igb_xstats_get_names(struct rte_eth_dev *dev,
 123                                     struct rte_eth_xstat_name *xstats_names,
 124                                     unsigned int size);
 125 static int eth_igb_xstats_get_names_by_id(struct rte_eth_dev *dev,
 126                 struct rte_eth_xstat_name *xstats_names, const uint64_t *ids,
 127                 unsigned int limit);
 128 static void eth_igb_stats_reset(struct rte_eth_dev *dev);
 129 static void eth_igb_xstats_reset(struct rte_eth_dev *dev);
 130 static int eth_igb_fw_version_get(struct rte_eth_dev *dev,
 131                                    char *fw_version, size_t fw_size);
 132 static void eth_igb_infos_get(struct rte_eth_dev *dev,
 133                               struct rte_eth_dev_info *dev_info);
 134 static const uint32_t *eth_igb_supported_ptypes_get(struct rte_eth_dev *dev);
 135 static void eth_igbvf_infos_get(struct rte_eth_dev *dev,
 136                                 struct rte_eth_dev_info *dev_info);
 137 static int  eth_igb_flow_ctrl_get(struct rte_eth_dev *dev,
 138                                 struct rte_eth_fc_conf *fc_conf);
 139 static int  eth_igb_flow_ctrl_set(struct rte_eth_dev *dev,
 140                                 struct rte_eth_fc_conf *fc_conf);
 141 static int eth_igb_lsc_interrupt_setup(struct rte_eth_dev *dev, uint8_t on);
 142 static int eth_igb_rxq_interrupt_setup(struct rte_eth_dev *dev);
 143 static int eth_igb_interrupt_get_status(struct rte_eth_dev *dev);
 144 static int eth_igb_interrupt_action(struct rte_eth_dev *dev,
 145                                     struct rte_intr_handle *handle);
 146 static void eth_igb_interrupt_handler(void *param);
 147 static int  igb_hardware_init(struct e1000_hw *hw);
 148 static void igb_hw_control_acquire(struct e1000_hw *hw);
 149 static void igb_hw_control_release(struct e1000_hw *hw);
 150 static void igb_init_manageability(struct e1000_hw *hw);
 151 static void igb_release_manageability(struct e1000_hw *hw);
 152
 153 static int  eth_igb_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
 154
 155 static int eth_igb_vlan_filter_set(struct rte_eth_dev *dev,
 156                 uint16_t vlan_id, int on);
 157 static int eth_igb_vlan_tpid_set(struct rte_eth_dev *dev,
 158                                  enum rte_vlan_type vlan_type,
 159                                  uint16_t tpid_id);
 160 static void eth_igb_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 161
 162 static void igb_vlan_hw_filter_enable(struct rte_eth_dev *dev);
 163 static void igb_vlan_hw_filter_disable(struct rte_eth_dev *dev);
 164 static void igb_vlan_hw_strip_enable(struct rte_eth_dev *dev);
 165 static void igb_vlan_hw_strip_disable(struct rte_eth_dev *dev);
 166 static void igb_vlan_hw_extend_enable(struct rte_eth_dev *dev);
 167 static void igb_vlan_hw_extend_disable(struct rte_eth_dev *dev);
 168
 169 static int eth_igb_led_on(struct rte_eth_dev *dev);
 170 static int eth_igb_led_off(struct rte_eth_dev *dev);
 171
 172 static void igb_intr_disable(struct e1000_hw *hw);
 173 static int  igb_get_rx_buffer_size(struct e1000_hw *hw);
 174 static int eth_igb_rar_set(struct rte_eth_dev *dev,
 175                            struct ether_addr *mac_addr,
 176                            uint32_t index, uint32_t pool);
 177 static void eth_igb_rar_clear(struct rte_eth_dev *dev, uint32_t index);
 178 static void eth_igb_default_mac_addr_set(struct rte_eth_dev *dev,
 179                 struct ether_addr *addr);
 180
 181 static void igbvf_intr_disable(struct e1000_hw *hw);
 182 static int igbvf_dev_configure(struct rte_eth_dev *dev);
 183 static int igbvf_dev_start(struct rte_eth_dev *dev);
 184 static void igbvf_dev_stop(struct rte_eth_dev *dev);
 185 static void igbvf_dev_close(struct rte_eth_dev *dev);
 186 static void igbvf_promiscuous_enable(struct rte_eth_dev *dev);
 187 static void igbvf_promiscuous_disable(struct rte_eth_dev *dev);
 188 static void igbvf_allmulticast_enable(struct rte_eth_dev *dev);
 189 static void igbvf_allmulticast_disable(struct rte_eth_dev *dev);
 190 static int eth_igbvf_link_update(struct e1000_hw *hw);
 191 static void eth_igbvf_stats_get(struct rte_eth_dev *dev,
 192                                 struct rte_eth_stats *rte_stats);
 193 static int eth_igbvf_xstats_get(struct rte_eth_dev *dev,
 194                                 struct rte_eth_xstat *xstats, unsigned n);
 195 static int eth_igbvf_xstats_get_names(struct rte_eth_dev *dev,
 196                                       struct rte_eth_xstat_name *xstats_names,
 197                                       unsigned limit);
 198 static void eth_igbvf_stats_reset(struct rte_eth_dev *dev);
 199 static int igbvf_vlan_filter_set(struct rte_eth_dev *dev,
 200                 uint16_t vlan_id, int on);
 201 static int igbvf_set_vfta(struct e1000_hw *hw, uint16_t vid, bool on);
 202 static void igbvf_set_vfta_all(struct rte_eth_dev *dev, bool on);
 203 static void igbvf_default_mac_addr_set(struct rte_eth_dev *dev,
 204                 struct ether_addr *addr);
 205 static int igbvf_get_reg_length(struct rte_eth_dev *dev);
 206 static int igbvf_get_regs(struct rte_eth_dev *dev,
 207                 struct rte_dev_reg_info *regs);
 208
 209 static int eth_igb_rss_reta_update(struct rte_eth_dev *dev,
 210                                    struct rte_eth_rss_reta_entry64 *reta_conf,
 211                                    uint16_t reta_size);
 212 static int eth_igb_rss_reta_query(struct rte_eth_dev *dev,
 213                                   struct rte_eth_rss_reta_entry64 *reta_conf,
 214                                   uint16_t reta_size);
 215
 216 static int eth_igb_syn_filter_get(struct rte_eth_dev *dev,
 217                         struct rte_eth_syn_filter *filter);
 218 static int eth_igb_syn_filter_handle(struct rte_eth_dev *dev,
 219                         enum rte_filter_op filter_op,
 220                         void *arg);
 221 static int igb_add_2tuple_filter(struct rte_eth_dev *dev,
 222                         struct rte_eth_ntuple_filter *ntuple_filter);
 223 static int igb_remove_2tuple_filter(struct rte_eth_dev *dev,
 224                         struct rte_eth_ntuple_filter *ntuple_filter);
 225 static int eth_igb_get_flex_filter(struct rte_eth_dev *dev,
 226                         struct rte_eth_flex_filter *filter);
 227 static int eth_igb_flex_filter_handle(struct rte_eth_dev *dev,
 228                         enum rte_filter_op filter_op,
 229                         void *arg);
 230 static int igb_add_5tuple_filter_82576(struct rte_eth_dev *dev,
 231                         struct rte_eth_ntuple_filter *ntuple_filter);
 232 static int igb_remove_5tuple_filter_82576(struct rte_eth_dev *dev,
 233                         struct rte_eth_ntuple_filter *ntuple_filter);
 234 static int igb_get_ntuple_filter(struct rte_eth_dev *dev,
 235                         struct rte_eth_ntuple_filter *filter);
 236 static int igb_ntuple_filter_handle(struct rte_eth_dev *dev,
 237                                 enum rte_filter_op filter_op,
 238                                 void *arg);
 239 static int igb_ethertype_filter_handle(struct rte_eth_dev *dev,
 240                                 enum rte_filter_op filter_op,
 241                                 void *arg);
 242 static int igb_get_ethertype_filter(struct rte_eth_dev *dev,
 243                         struct rte_eth_ethertype_filter *filter);
 244 static int eth_igb_filter_ctrl(struct rte_eth_dev *dev,
 245                      enum rte_filter_type filter_type,
 246                      enum rte_filter_op filter_op,
 247                      void *arg);
 248 static int eth_igb_get_reg_length(struct rte_eth_dev *dev);
 249 static int eth_igb_get_regs(struct rte_eth_dev *dev,
 250                 struct rte_dev_reg_info *regs);
 251 static int eth_igb_get_eeprom_length(struct rte_eth_dev *dev);
 252 static int eth_igb_get_eeprom(struct rte_eth_dev *dev,
 253                 struct rte_dev_eeprom_info *eeprom);
 254 static int eth_igb_set_eeprom(struct rte_eth_dev *dev,
 255                 struct rte_dev_eeprom_info *eeprom);
 256 static int eth_igb_set_mc_addr_list(struct rte_eth_dev *dev,
 257                                     struct ether_addr *mc_addr_set,
 258                                     uint32_t nb_mc_addr);
 259 static int igb_timesync_enable(struct rte_eth_dev *dev);
 260 static int igb_timesync_disable(struct rte_eth_dev *dev);
 261 static int igb_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
 262                                           struct timespec *timestamp,
 263                                           uint32_t flags);
 264 static int igb_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
 265                                           struct timespec *timestamp);
 266 static int igb_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);
 267 static int igb_timesync_read_time(struct rte_eth_dev *dev,
 268                                   struct timespec *timestamp);
 269 static int igb_timesync_write_time(struct rte_eth_dev *dev,
 270                                    const struct timespec *timestamp);
 271 static int eth_igb_rx_queue_intr_enable(struct rte_eth_dev *dev,
 272                                         uint16_t queue_id);
 273 static int eth_igb_rx_queue_intr_disable(struct rte_eth_dev *dev,
 274                                          uint16_t queue_id);
 275 static void eth_igb_assign_msix_vector(struct e1000_hw *hw, int8_t direction,
 276                                        uint8_t queue, uint8_t msix_vector);
 277 static void eth_igb_write_ivar(struct e1000_hw *hw, uint8_t msix_vector,
 278                                uint8_t index, uint8_t offset);
 279 static void eth_igb_configure_msix_intr(struct rte_eth_dev *dev);
 280 static void eth_igbvf_interrupt_handler(void *param);
 281 static void igbvf_mbx_process(struct rte_eth_dev *dev);
 282 static int igb_filter_restore(struct rte_eth_dev *dev);
 283
 284 /*
 285  * Define VF Stats MACRO for Non "cleared on read" register
 286  */
 287 #define UPDATE_VF_STAT(reg, last, cur)            \
 288 {                                                 \
 289         u32 latest = E1000_READ_REG(hw, reg);     \
 290         cur += (latest - last) & UINT_MAX;        \
 291         last = latest;                            \
 292 }
 293
 294 #define IGB_FC_PAUSE_TIME 0x0680
 295 #define IGB_LINK_UPDATE_CHECK_TIMEOUT  90  /* 9s */
 296 #define IGB_LINK_UPDATE_CHECK_INTERVAL 100 /* ms */
 297
 298 #define IGBVF_PMD_NAME "rte_igbvf_pmd"     /* PMD name */
 299
 300 static enum e1000_fc_mode igb_fc_setting = e1000_fc_full;
 301
 302 /*
 303  * The set of PCI devices this driver supports
 304  */
 305 static const struct rte_pci_id pci_id_igb_map[] = {
 306         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576) },
 307         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_FIBER) },
 308         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_SERDES) },
 309         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_QUAD_COPPER) },
 310         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_QUAD_COPPER_ET2) },
 311         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_NS) },
 312         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_NS_SERDES) },
 313         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_SERDES_QUAD) },
 314
 315         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82575EB_COPPER) },
 316         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82575EB_FIBER_SERDES) },
 317         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82575GB_QUAD_COPPER) },
 318
 319         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82580_COPPER) },
 320         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82580_FIBER) },
 321         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82580_SERDES) },
 322         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82580_SGMII) },
 323         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82580_COPPER_DUAL) },
 324         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82580_QUAD_FIBER) },
 325
 326         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_COPPER) },
 327         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_FIBER) },
 328         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_SERDES) },
 329         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_SGMII) },
 330         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_DA4) },
 331         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_COPPER) },
 332         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_COPPER_OEM1) },
 333         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_COPPER_IT) },
 334         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_FIBER) },
 335         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_SERDES) },
 336         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_SGMII) },
 337         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I211_COPPER) },
 338         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I354_BACKPLANE_1GBPS) },
 339         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I354_SGMII) },
 340         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I354_BACKPLANE_2_5GBPS) },
 341         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_DH89XXCC_SGMII) },
 342         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_DH89XXCC_SERDES) },
 343         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_DH89XXCC_BACKPLANE) },
 344         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_DH89XXCC_SFP) },
 345         { .vendor_id = 0, /* sentinel */ },
 346 };
 347
 348 /*
 349  * The set of PCI devices this driver supports (for 82576&I350 VF)
 350  */
 351 static const struct rte_pci_id pci_id_igbvf_map[] = {
 352         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_VF) },
 353         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_VF_HV) },
 354         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_VF) },
 355         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_VF_HV) },
 356         { .vendor_id = 0, /* sentinel */ },
 357 };
 358
 359 static const struct rte_eth_desc_lim rx_desc_lim = {
 360         .nb_max = E1000_MAX_RING_DESC,
 361         .nb_min = E1000_MIN_RING_DESC,
 362         .nb_align = IGB_RXD_ALIGN,
 363 };
 364
 365 static const struct rte_eth_desc_lim tx_desc_lim = {
 366         .nb_max = E1000_MAX_RING_DESC,
 367         .nb_min = E1000_MIN_RING_DESC,
 368         .nb_align = IGB_RXD_ALIGN,
 369         .nb_seg_max = IGB_TX_MAX_SEG,
 370         .nb_mtu_seg_max = IGB_TX_MAX_MTU_SEG,
 371 };
 372
 373 static const struct eth_dev_ops eth_igb_ops = {
 374         .dev_configure        = eth_igb_configure,
 375         .dev_start            = eth_igb_start,
 376         .dev_stop             = eth_igb_stop,
 377         .dev_set_link_up      = eth_igb_dev_set_link_up,
 378         .dev_set_link_down    = eth_igb_dev_set_link_down,
 379         .dev_close            = eth_igb_close,
 380         .promiscuous_enable   = eth_igb_promiscuous_enable,
 381         .promiscuous_disable  = eth_igb_promiscuous_disable,
 382         .allmulticast_enable  = eth_igb_allmulticast_enable,
 383         .allmulticast_disable = eth_igb_allmulticast_disable,
 384         .link_update          = eth_igb_link_update,
 385         .stats_get            = eth_igb_stats_get,
 386         .xstats_get           = eth_igb_xstats_get,
 387         .xstats_get_by_id     = eth_igb_xstats_get_by_id,
 388         .xstats_get_names_by_id = eth_igb_xstats_get_names_by_id,
 389         .xstats_get_names     = eth_igb_xstats_get_names,
 390         .stats_reset          = eth_igb_stats_reset,
 391         .xstats_reset         = eth_igb_xstats_reset,
 392         .fw_version_get       = eth_igb_fw_version_get,
 393         .dev_infos_get        = eth_igb_infos_get,
 394         .dev_supported_ptypes_get = eth_igb_supported_ptypes_get,
 395         .mtu_set              = eth_igb_mtu_set,
 396         .vlan_filter_set      = eth_igb_vlan_filter_set,
 397         .vlan_tpid_set        = eth_igb_vlan_tpid_set,
 398         .vlan_offload_set     = eth_igb_vlan_offload_set,
 399         .rx_queue_setup       = eth_igb_rx_queue_setup,
 400         .rx_queue_intr_enable = eth_igb_rx_queue_intr_enable,
 401         .rx_queue_intr_disable = eth_igb_rx_queue_intr_disable,
 402         .rx_queue_release     = eth_igb_rx_queue_release,
 403         .rx_queue_count       = eth_igb_rx_queue_count,
 404         .rx_descriptor_done   = eth_igb_rx_descriptor_done,
 405         .rx_descriptor_status = eth_igb_rx_descriptor_status,
 406         .tx_descriptor_status = eth_igb_tx_descriptor_status,
 407         .tx_queue_setup       = eth_igb_tx_queue_setup,
 408         .tx_queue_release     = eth_igb_tx_queue_release,
 409         .tx_done_cleanup      = eth_igb_tx_done_cleanup,
 410         .dev_led_on           = eth_igb_led_on,
 411         .dev_led_off          = eth_igb_led_off,
 412         .flow_ctrl_get        = eth_igb_flow_ctrl_get,
 413         .flow_ctrl_set        = eth_igb_flow_ctrl_set,
 414         .mac_addr_add         = eth_igb_rar_set,
 415         .mac_addr_remove      = eth_igb_rar_clear,
 416         .mac_addr_set         = eth_igb_default_mac_addr_set,
 417         .reta_update          = eth_igb_rss_reta_update,
 418         .reta_query           = eth_igb_rss_reta_query,
 419         .rss_hash_update      = eth_igb_rss_hash_update,
 420         .rss_hash_conf_get    = eth_igb_rss_hash_conf_get,
 421         .filter_ctrl          = eth_igb_filter_ctrl,
 422         .set_mc_addr_list     = eth_igb_set_mc_addr_list,
 423         .rxq_info_get         = igb_rxq_info_get,
 424         .txq_info_get         = igb_txq_info_get,
 425         .timesync_enable      = igb_timesync_enable,
 426         .timesync_disable     = igb_timesync_disable,
 427         .timesync_read_rx_timestamp = igb_timesync_read_rx_timestamp,
 428         .timesync_read_tx_timestamp = igb_timesync_read_tx_timestamp,
 429         .get_reg              = eth_igb_get_regs,
 430         .get_eeprom_length    = eth_igb_get_eeprom_length,
 431         .get_eeprom           = eth_igb_get_eeprom,
 432         .set_eeprom           = eth_igb_set_eeprom,
 433         .timesync_adjust_time = igb_timesync_adjust_time,
 434         .timesync_read_time   = igb_timesync_read_time,
 435         .timesync_write_time  = igb_timesync_write_time,
 436 };
 437
 438 /*
 439  * dev_ops for virtual function, bare necessities for basic vf
 440  * operation have been implemented
 441  */
 442 static const struct eth_dev_ops igbvf_eth_dev_ops = {
 443         .dev_configure        = igbvf_dev_configure,
 444         .dev_start            = igbvf_dev_start,
 445         .dev_stop             = igbvf_dev_stop,
 446         .dev_close            = igbvf_dev_close,
 447         .promiscuous_enable   = igbvf_promiscuous_enable,
 448         .promiscuous_disable  = igbvf_promiscuous_disable,
 449         .allmulticast_enable  = igbvf_allmulticast_enable,
 450         .allmulticast_disable = igbvf_allmulticast_disable,
 451         .link_update          = eth_igb_link_update,
 452         .stats_get            = eth_igbvf_stats_get,
 453         .xstats_get           = eth_igbvf_xstats_get,
 454         .xstats_get_names     = eth_igbvf_xstats_get_names,
 455         .stats_reset          = eth_igbvf_stats_reset,
 456         .xstats_reset         = eth_igbvf_stats_reset,
 457         .vlan_filter_set      = igbvf_vlan_filter_set,
 458         .dev_infos_get        = eth_igbvf_infos_get,
 459         .dev_supported_ptypes_get = eth_igb_supported_ptypes_get,
 460         .rx_queue_setup       = eth_igb_rx_queue_setup,
 461         .rx_queue_release     = eth_igb_rx_queue_release,
 462         .tx_queue_setup       = eth_igb_tx_queue_setup,
 463         .tx_queue_release     = eth_igb_tx_queue_release,
 464         .set_mc_addr_list     = eth_igb_set_mc_addr_list,
 465         .rxq_info_get         = igb_rxq_info_get,
 466         .txq_info_get         = igb_txq_info_get,
 467         .mac_addr_set         = igbvf_default_mac_addr_set,
 468         .get_reg              = igbvf_get_regs,
 469 };
 470
 471 /* store statistics names and its offset in stats structure */
 472 struct rte_igb_xstats_name_off {
 473         char name[RTE_ETH_XSTATS_NAME_SIZE];
 474         unsigned offset;
 475 };
 476
 477 static const struct rte_igb_xstats_name_off rte_igb_stats_strings[] = {
 478         {"rx_crc_errors", offsetof(struct e1000_hw_stats, crcerrs)},
 479         {"rx_align_errors", offsetof(struct e1000_hw_stats, algnerrc)},
 480         {"rx_symbol_errors", offsetof(struct e1000_hw_stats, symerrs)},
 481         {"rx_missed_packets", offsetof(struct e1000_hw_stats, mpc)},
 482         {"tx_single_collision_packets", offsetof(struct e1000_hw_stats, scc)},
 483         {"tx_multiple_collision_packets", offsetof(struct e1000_hw_stats, mcc)},
 484         {"tx_excessive_collision_packets", offsetof(struct e1000_hw_stats,
 485                 ecol)},
 486         {"tx_late_collisions", offsetof(struct e1000_hw_stats, latecol)},
 487         {"tx_total_collisions", offsetof(struct e1000_hw_stats, colc)},
 488         {"tx_deferred_packets", offsetof(struct e1000_hw_stats, dc)},
 489         {"tx_no_carrier_sense_packets", offsetof(struct e1000_hw_stats, tncrs)},
 490         {"rx_carrier_ext_errors", offsetof(struct e1000_hw_stats, cexterr)},
 491         {"rx_length_errors", offsetof(struct e1000_hw_stats, rlec)},
 492         {"rx_xon_packets", offsetof(struct e1000_hw_stats, xonrxc)},
 493         {"tx_xon_packets", offsetof(struct e1000_hw_stats, xontxc)},
 494         {"rx_xoff_packets", offsetof(struct e1000_hw_stats, xoffrxc)},
 495         {"tx_xoff_packets", offsetof(struct e1000_hw_stats, xofftxc)},
 496         {"rx_flow_control_unsupported_packets", offsetof(struct e1000_hw_stats,
 497                 fcruc)},
 498         {"rx_size_64_packets", offsetof(struct e1000_hw_stats, prc64)},
 499         {"rx_size_65_to_127_packets", offsetof(struct e1000_hw_stats, prc127)},
 500         {"rx_size_128_to_255_packets", offsetof(struct e1000_hw_stats, prc255)},
 501         {"rx_size_256_to_511_packets", offsetof(struct e1000_hw_stats, prc511)},
 502         {"rx_size_512_to_1023_packets", offsetof(struct e1000_hw_stats,
 503                 prc1023)},
 504         {"rx_size_1024_to_max_packets", offsetof(struct e1000_hw_stats,
 505                 prc1522)},
 506         {"rx_broadcast_packets", offsetof(struct e1000_hw_stats, bprc)},
 507         {"rx_multicast_packets", offsetof(struct e1000_hw_stats, mprc)},
 508         {"rx_undersize_errors", offsetof(struct e1000_hw_stats, ruc)},
 509         {"rx_fragment_errors", offsetof(struct e1000_hw_stats, rfc)},
 510         {"rx_oversize_errors", offsetof(struct e1000_hw_stats, roc)},
 511         {"rx_jabber_errors", offsetof(struct e1000_hw_stats, rjc)},
 512         {"rx_management_packets", offsetof(struct e1000_hw_stats, mgprc)},
 513         {"rx_management_dropped", offsetof(struct e1000_hw_stats, mgpdc)},
 514         {"tx_management_packets", offsetof(struct e1000_hw_stats, mgptc)},
 515         {"rx_total_packets", offsetof(struct e1000_hw_stats, tpr)},
 516         {"tx_total_packets", offsetof(struct e1000_hw_stats, tpt)},
 517         {"rx_total_bytes", offsetof(struct e1000_hw_stats, tor)},
 518         {"tx_total_bytes", offsetof(struct e1000_hw_stats, tot)},
 519         {"tx_size_64_packets", offsetof(struct e1000_hw_stats, ptc64)},
 520         {"tx_size_65_to_127_packets", offsetof(struct e1000_hw_stats, ptc127)},
 521         {"tx_size_128_to_255_packets", offsetof(struct e1000_hw_stats, ptc255)},
 522         {"tx_size_256_to_511_packets", offsetof(struct e1000_hw_stats, ptc511)},
 523         {"tx_size_512_to_1023_packets", offsetof(struct e1000_hw_stats,
 524                 ptc1023)},
 525         {"tx_size_1023_to_max_packets", offsetof(struct e1000_hw_stats,
 526                 ptc1522)},
 527         {"tx_multicast_packets", offsetof(struct e1000_hw_stats, mptc)},
 528         {"tx_broadcast_packets", offsetof(struct e1000_hw_stats, bptc)},
 529         {"tx_tso_packets", offsetof(struct e1000_hw_stats, tsctc)},
 530         {"tx_tso_errors", offsetof(struct e1000_hw_stats, tsctfc)},
 531         {"rx_sent_to_host_packets", offsetof(struct e1000_hw_stats, rpthc)},
 532         {"tx_sent_by_host_packets", offsetof(struct e1000_hw_stats, hgptc)},
 533         {"rx_code_violation_packets", offsetof(struct e1000_hw_stats, scvpc)},
 534
 535         {"interrupt_assert_count", offsetof(struct e1000_hw_stats, iac)},
 536 };
 537
 538 #define IGB_NB_XSTATS (sizeof(rte_igb_stats_strings) / \
 539                 sizeof(rte_igb_stats_strings[0]))
 540
 541 static const struct rte_igb_xstats_name_off rte_igbvf_stats_strings[] = {
 542         {"rx_multicast_packets", offsetof(struct e1000_vf_stats, mprc)},
 543         {"rx_good_loopback_packets", offsetof(struct e1000_vf_stats, gprlbc)},
 544         {"tx_good_loopback_packets", offsetof(struct e1000_vf_stats, gptlbc)},
 545         {"rx_good_loopback_bytes", offsetof(struct e1000_vf_stats, gorlbc)},
 546         {"tx_good_loopback_bytes", offsetof(struct e1000_vf_stats, gotlbc)},
 547 };
 548
 549 #define IGBVF_NB_XSTATS (sizeof(rte_igbvf_stats_strings) / \
 550                 sizeof(rte_igbvf_stats_strings[0]))
 551
 552 /**
 553  * Atomically reads the link status information from global
 554  * structure rte_eth_dev.
 555  *
 556  * @param dev
 557  *   - Pointer to the structure rte_eth_dev to read from.
 558  *   - Pointer to the buffer to be saved with the link status.
 559  *
 560  * @return
 561  *   - On success, zero.
 562  *   - On failure, negative value.
 563  */
 564 static inline int
 565 rte_igb_dev_atomic_read_link_status(struct rte_eth_dev *dev,
 566                                 struct rte_eth_link *link)
 567 {
 568         struct rte_eth_link *dst = link;
 569         struct rte_eth_link *src = &(dev->data->dev_link);
 570
 571         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 572                                         *(uint64_t *)src) == 0)
 573                 return -1;
 574
 575         return 0;
 576 }
 577
 578 /**
 579  * Atomically writes the link status information into global
 580  * structure rte_eth_dev.
 581  *
 582  * @param dev
 583  *   - Pointer to the structure rte_eth_dev to read from.
 584  *   - Pointer to the buffer to be saved with the link status.
 585  *
 586  * @return
 587  *   - On success, zero.
 588  *   - On failure, negative value.
 589  */
 590 static inline int
 591 rte_igb_dev_atomic_write_link_status(struct rte_eth_dev *dev,
 592                                 struct rte_eth_link *link)
 593 {
 594         struct rte_eth_link *dst = &(dev->data->dev_link);
 595         struct rte_eth_link *src = link;
 596
 597         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 598                                         *(uint64_t *)src) == 0)
 599                 return -1;
 600
 601         return 0;
 602 }
 603
 604 static inline void
 605 igb_intr_enable(struct rte_eth_dev *dev)
 606 {
 607         struct e1000_interrupt *intr =
 608                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
 609         struct e1000_hw *hw =
 610                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 611
 612         E1000_WRITE_REG(hw, E1000_IMS, intr->mask);
 613         E1000_WRITE_FLUSH(hw);
 614 }
 615
 616 static void
 617 igb_intr_disable(struct e1000_hw *hw)
 618 {
 619         E1000_WRITE_REG(hw, E1000_IMC, ~0);
 620         E1000_WRITE_FLUSH(hw);
 621 }
 622
 623 static inline void
 624 igbvf_intr_enable(struct rte_eth_dev *dev)
 625 {
 626         struct e1000_hw *hw =
 627                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 628
 629         /* only for mailbox */
 630         E1000_WRITE_REG(hw, E1000_EIAM, 1 << E1000_VTIVAR_MISC_MAILBOX);
 631         E1000_WRITE_REG(hw, E1000_EIAC, 1 << E1000_VTIVAR_MISC_MAILBOX);
 632         E1000_WRITE_REG(hw, E1000_EIMS, 1 << E1000_VTIVAR_MISC_MAILBOX);
 633         E1000_WRITE_FLUSH(hw);
 634 }
 635
 636 /* only for mailbox now. If RX/TX needed, should extend this function.  */
 637 static void
 638 igbvf_set_ivar_map(struct e1000_hw *hw, uint8_t msix_vector)
 639 {
 640         uint32_t tmp = 0;
 641
 642         /* mailbox */
 643         tmp |= (msix_vector & E1000_VTIVAR_MISC_INTR_MASK);
 644         tmp |= E1000_VTIVAR_VALID;
 645         E1000_WRITE_REG(hw, E1000_VTIVAR_MISC, tmp);
 646 }
 647
 648 static void
 649 eth_igbvf_configure_msix_intr(struct rte_eth_dev *dev)
 650 {
 651         struct e1000_hw *hw =
 652                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 653
 654         /* Configure VF other cause ivar */
 655         igbvf_set_ivar_map(hw, E1000_VTIVAR_MISC_MAILBOX);
 656 }
 657
 658 static inline int32_t
 659 igb_pf_reset_hw(struct e1000_hw *hw)
 660 {
 661         uint32_t ctrl_ext;
 662         int32_t status;
 663
 664         status = e1000_reset_hw(hw);
 665
 666         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
 667         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
 668         ctrl_ext |= E1000_CTRL_EXT_PFRSTD;
 669         E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
 670         E1000_WRITE_FLUSH(hw);
 671
 672         return status;
 673 }
 674
 675 static void
 676 igb_identify_hardware(struct rte_eth_dev *dev, struct rte_pci_device *pci_dev)
 677 {
 678         struct e1000_hw *hw =
 679                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 680
 681
 682         hw->vendor_id = pci_dev->id.vendor_id;
 683         hw->device_id = pci_dev->id.device_id;
 684         hw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
 685         hw->subsystem_device_id = pci_dev->id.subsystem_device_id;
 686
 687         e1000_set_mac_type(hw);
 688
 689         /* need to check if it is a vf device below */
 690 }
 691
 692 static int
 693 igb_reset_swfw_lock(struct e1000_hw *hw)
 694 {
 695         int ret_val;
 696
 697         /*
 698          * Do mac ops initialization manually here, since we will need
 699          * some function pointers set by this call.
 700          */
 701         ret_val = e1000_init_mac_params(hw);
 702         if (ret_val)
 703                 return ret_val;
 704
 705         /*
 706          * SMBI lock should not fail in this early stage. If this is the case,
 707          * it is due to an improper exit of the application.
 708          * So force the release of the faulty lock.
 709          */
 710         if (e1000_get_hw_semaphore_generic(hw) < 0) {
 711                 PMD_DRV_LOG(DEBUG, "SMBI lock released");
 712         }
 713         e1000_put_hw_semaphore_generic(hw);
 714
 715         if (hw->mac.ops.acquire_swfw_sync != NULL) {
 716                 uint16_t mask;
 717
 718                 /*
 719                  * Phy lock should not fail in this early stage. If this is the case,
 720                  * it is due to an improper exit of the application.
 721                  * So force the release of the faulty lock.
 722                  */
 723                 mask = E1000_SWFW_PHY0_SM << hw->bus.func;
 724                 if (hw->bus.func > E1000_FUNC_1)
 725                         mask <<= 2;
 726                 if (hw->mac.ops.acquire_swfw_sync(hw, mask) < 0) {
 727                         PMD_DRV_LOG(DEBUG, "SWFW phy%d lock released",
 728                                     hw->bus.func);
 729                 }
 730                 hw->mac.ops.release_swfw_sync(hw, mask);
 731
 732                 /*
 733                  * This one is more tricky since it is common to all ports; but
 734                  * swfw_sync retries last long enough (1s) to be almost sure that if
 735                  * lock can not be taken it is due to an improper lock of the
 736                  * semaphore.
 737                  */
 738                 mask = E1000_SWFW_EEP_SM;
 739                 if (hw->mac.ops.acquire_swfw_sync(hw, mask) < 0) {
 740                         PMD_DRV_LOG(DEBUG, "SWFW common locks released");
 741                 }
 742                 hw->mac.ops.release_swfw_sync(hw, mask);
 743         }
 744
 745         return E1000_SUCCESS;
 746 }
 747
 748 /* Remove all ntuple filters of the device */
 749 static int igb_ntuple_filter_uninit(struct rte_eth_dev *eth_dev)
 750 {
 751         struct e1000_filter_info *filter_info =
 752                 E1000_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
 753         struct e1000_5tuple_filter *p_5tuple;
 754         struct e1000_2tuple_filter *p_2tuple;
 755
 756         while ((p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list))) {
 757                 TAILQ_REMOVE(&filter_info->fivetuple_list,
 758                         p_5tuple, entries);
 759                         rte_free(p_5tuple);
 760         }
 761         filter_info->fivetuple_mask = 0;
 762         while ((p_2tuple = TAILQ_FIRST(&filter_info->twotuple_list))) {
 763                 TAILQ_REMOVE(&filter_info->twotuple_list,
 764                         p_2tuple, entries);
 765                         rte_free(p_2tuple);
 766         }
 767         filter_info->twotuple_mask = 0;
 768
 769         return 0;
 770 }
 771
 772 /* Remove all flex filters of the device */
 773 static int igb_flex_filter_uninit(struct rte_eth_dev *eth_dev)
 774 {
 775         struct e1000_filter_info *filter_info =
 776                 E1000_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
 777         struct e1000_flex_filter *p_flex;
 778
 779         while ((p_flex = TAILQ_FIRST(&filter_info->flex_list))) {
 780                 TAILQ_REMOVE(&filter_info->flex_list, p_flex, entries);
 781                 rte_free(p_flex);
 782         }
 783         filter_info->flex_mask = 0;
 784
 785         return 0;
 786 }
 787
 788 static int
 789 eth_igb_dev_init(struct rte_eth_dev *eth_dev)
 790 {
 791         int error = 0;
 792         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
 793         struct e1000_hw *hw =
 794                 E1000_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 795         struct e1000_vfta * shadow_vfta =
 796                 E1000_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
 797         struct e1000_filter_info *filter_info =
 798                 E1000_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
 799         struct e1000_adapter *adapter =
 800                 E1000_DEV_PRIVATE(eth_dev->data->dev_private);
 801
 802         uint32_t ctrl_ext;
 803
 804         eth_dev->dev_ops = &eth_igb_ops;
 805         eth_dev->rx_pkt_burst = &eth_igb_recv_pkts;
 806         eth_dev->tx_pkt_burst = &eth_igb_xmit_pkts;
 807         eth_dev->tx_pkt_prepare = &eth_igb_prep_pkts;
 808
 809         /* for secondary processes, we don't initialise any further as primary
 810          * has already done this work. Only check we don't need a different
 811          * RX function */
 812         if (rte_eal_process_type() != RTE_PROC_PRIMARY){
 813                 if (eth_dev->data->scattered_rx)
 814                         eth_dev->rx_pkt_burst = &eth_igb_recv_scattered_pkts;
 815                 return 0;
 816         }
 817
 818         rte_eth_copy_pci_info(eth_dev, pci_dev);
 819         eth_dev->data->dev_flags |= RTE_ETH_DEV_DETACHABLE;
 820
 821         hw->hw_addr= (void *)pci_dev->mem_resource[0].addr;
 822
 823         igb_identify_hardware(eth_dev, pci_dev);
 824         if (e1000_setup_init_funcs(hw, FALSE) != E1000_SUCCESS) {
 825                 error = -EIO;
 826                 goto err_late;
 827         }
 828
 829         e1000_get_bus_info(hw);
 830
 831         /* Reset any pending lock */
 832         if (igb_reset_swfw_lock(hw) != E1000_SUCCESS) {
 833                 error = -EIO;
 834                 goto err_late;
 835         }
 836
 837         /* Finish initialization */
 838         if (e1000_setup_init_funcs(hw, TRUE) != E1000_SUCCESS) {
 839                 error = -EIO;
 840                 goto err_late;
 841         }
 842
 843         hw->mac.autoneg = 1;
 844         hw->phy.autoneg_wait_to_complete = 0;
 845         hw->phy.autoneg_advertised = E1000_ALL_SPEED_DUPLEX;
 846
 847         /* Copper options */
 848         if (hw->phy.media_type == e1000_media_type_copper) {
 849                 hw->phy.mdix = 0; /* AUTO_ALL_MODES */
 850                 hw->phy.disable_polarity_correction = 0;
 851                 hw->phy.ms_type = e1000_ms_hw_default;
 852         }
 853
 854         /*
 855          * Start from a known state, this is important in reading the nvm
 856          * and mac from that.
 857          */
 858         igb_pf_reset_hw(hw);
 859
 860         /* Make sure we have a good EEPROM before we read from it */
 861         if (e1000_validate_nvm_checksum(hw) < 0) {
 862                 /*
 863                  * Some PCI-E parts fail the first check due to
 864                  * the link being in sleep state, call it again,
 865                  * if it fails a second time its a real issue.
 866                  */
 867                 if (e1000_validate_nvm_checksum(hw) < 0) {
 868                         PMD_INIT_LOG(ERR, "EEPROM checksum invalid");
 869                         error = -EIO;
 870                         goto err_late;
 871                 }
 872         }
 873
 874         /* Read the permanent MAC address out of the EEPROM */
 875         if (e1000_read_mac_addr(hw) != 0) {
 876                 PMD_INIT_LOG(ERR, "EEPROM error while reading MAC address");
 877                 error = -EIO;
 878                 goto err_late;
 879         }
 880
 881         /* Allocate memory for storing MAC addresses */
 882         eth_dev->data->mac_addrs = rte_zmalloc("e1000",
 883                 ETHER_ADDR_LEN * hw->mac.rar_entry_count, 0);
 884         if (eth_dev->data->mac_addrs == NULL) {
 885                 PMD_INIT_LOG(ERR, "Failed to allocate %d bytes needed to "
 886                                                 "store MAC addresses",
 887                                 ETHER_ADDR_LEN * hw->mac.rar_entry_count);
 888                 error = -ENOMEM;
 889                 goto err_late;
 890         }
 891
 892         /* Copy the permanent MAC address */
 893         ether_addr_copy((struct ether_addr *)hw->mac.addr, &eth_dev->data->mac_addrs[0]);
 894
 895         /* initialize the vfta */
 896         memset(shadow_vfta, 0, sizeof(*shadow_vfta));
 897
 898         /* Now initialize the hardware */
 899         if (igb_hardware_init(hw) != 0) {
 900                 PMD_INIT_LOG(ERR, "Hardware initialization failed");
 901                 rte_free(eth_dev->data->mac_addrs);
 902                 eth_dev->data->mac_addrs = NULL;
 903                 error = -ENODEV;
 904                 goto err_late;
 905         }
 906         hw->mac.get_link_status = 1;
 907         adapter->stopped = 0;
 908
 909         /* Indicate SOL/IDER usage */
 910         if (e1000_check_reset_block(hw) < 0) {
 911                 PMD_INIT_LOG(ERR, "PHY reset is blocked due to"
 912                                         "SOL/IDER session");
 913         }
 914
 915         /* initialize PF if max_vfs not zero */
 916         igb_pf_host_init(eth_dev);
 917
 918         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
 919         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
 920         ctrl_ext |= E1000_CTRL_EXT_PFRSTD;
 921         E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
 922         E1000_WRITE_FLUSH(hw);
 923
 924         PMD_INIT_LOG(DEBUG, "port_id %d vendorID=0x%x deviceID=0x%x",
 925                      eth_dev->data->port_id, pci_dev->id.vendor_id,
 926                      pci_dev->id.device_id);
 927
 928         rte_intr_callback_register(&pci_dev->intr_handle,
 929                                    eth_igb_interrupt_handler,
 930                                    (void *)eth_dev);
 931
 932         /* enable uio/vfio intr/eventfd mapping */
 933         rte_intr_enable(&pci_dev->intr_handle);
 934
 935         /* enable support intr */
 936         igb_intr_enable(eth_dev);
 937
 938         /* initialize filter info */
 939         memset(filter_info, 0,
 940                sizeof(struct e1000_filter_info));
 941
 942         TAILQ_INIT(&filter_info->flex_list);
 943         TAILQ_INIT(&filter_info->twotuple_list);
 944         TAILQ_INIT(&filter_info->fivetuple_list);
 945
 946         TAILQ_INIT(&igb_filter_ntuple_list);
 947         TAILQ_INIT(&igb_filter_ethertype_list);
 948         TAILQ_INIT(&igb_filter_syn_list);
 949         TAILQ_INIT(&igb_filter_flex_list);
 950         TAILQ_INIT(&igb_flow_list);
 951
 952         return 0;
 953
 954 err_late:
 955         igb_hw_control_release(hw);
 956
 957         return error;
 958 }
 959
 960 static int
 961 eth_igb_dev_uninit(struct rte_eth_dev *eth_dev)
 962 {
 963         struct rte_pci_device *pci_dev;
 964         struct rte_intr_handle *intr_handle;
 965         struct e1000_hw *hw;
 966         struct e1000_adapter *adapter =
 967                 E1000_DEV_PRIVATE(eth_dev->data->dev_private);
 968         struct e1000_filter_info *filter_info =
 969                 E1000_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
 970
 971         PMD_INIT_FUNC_TRACE();
 972
 973         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
 974                 return -EPERM;
 975
 976         hw = E1000_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 977         pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
 978         intr_handle = &pci_dev->intr_handle;
 979
 980         if (adapter->stopped == 0)
 981                 eth_igb_close(eth_dev);
 982
 983         eth_dev->dev_ops = NULL;
 984         eth_dev->rx_pkt_burst = NULL;
 985         eth_dev->tx_pkt_burst = NULL;
 986
 987         /* Reset any pending lock */
 988         igb_reset_swfw_lock(hw);
 989
 990         rte_free(eth_dev->data->mac_addrs);
 991         eth_dev->data->mac_addrs = NULL;
 992
 993         /* uninitialize PF if max_vfs not zero */
 994         igb_pf_host_uninit(eth_dev);
 995
 996         /* disable uio intr before callback unregister */
 997         rte_intr_disable(intr_handle);
 998         rte_intr_callback_unregister(intr_handle,
 999                                      eth_igb_interrupt_handler, eth_dev);
1000
1001         /* clear the SYN filter info */
1002         filter_info->syn_info = 0;
1003
1004         /* clear the ethertype filters info */
1005         filter_info->ethertype_mask = 0;
1006         memset(filter_info->ethertype_filters, 0,
1007                 E1000_MAX_ETQF_FILTERS * sizeof(struct igb_ethertype_filter));
1008
1009         /* remove all ntuple filters of the device */
1010         igb_ntuple_filter_uninit(eth_dev);
1011
1012         /* remove all flex filters of the device */
1013         igb_flex_filter_uninit(eth_dev);
1014
1015         /* clear all the filters list */
1016         igb_filterlist_flush(eth_dev);
1017
1018         return 0;
1019 }
1020
1021 /*
1022  * Virtual Function device init
1023  */
1024 static int
1025 eth_igbvf_dev_init(struct rte_eth_dev *eth_dev)
1026 {
1027         struct rte_pci_device *pci_dev;
1028         struct rte_intr_handle *intr_handle;
1029         struct e1000_adapter *adapter =
1030                 E1000_DEV_PRIVATE(eth_dev->data->dev_private);
1031         struct e1000_hw *hw =
1032                 E1000_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1033         int diag;
1034         struct ether_addr *perm_addr = (struct ether_addr *)hw->mac.perm_addr;
1035
1036         PMD_INIT_FUNC_TRACE();
1037
1038         eth_dev->dev_ops = &igbvf_eth_dev_ops;
1039         eth_dev->rx_pkt_burst = &eth_igb_recv_pkts;
1040         eth_dev->tx_pkt_burst = &eth_igb_xmit_pkts;
1041         eth_dev->tx_pkt_prepare = &eth_igb_prep_pkts;
1042
1043         /* for secondary processes, we don't initialise any further as primary
1044          * has already done this work. Only check we don't need a different
1045          * RX function */
1046         if (rte_eal_process_type() != RTE_PROC_PRIMARY){
1047                 if (eth_dev->data->scattered_rx)
1048                         eth_dev->rx_pkt_burst = &eth_igb_recv_scattered_pkts;
1049                 return 0;
1050         }
1051
1052         pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1053         rte_eth_copy_pci_info(eth_dev, pci_dev);
1054         eth_dev->data->dev_flags |= RTE_ETH_DEV_DETACHABLE;
1055
1056         hw->device_id = pci_dev->id.device_id;
1057         hw->vendor_id = pci_dev->id.vendor_id;
1058         hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
1059         adapter->stopped = 0;
1060
1061         /* Initialize the shared code (base driver) */
1062         diag = e1000_setup_init_funcs(hw, TRUE);
1063         if (diag != 0) {
1064                 PMD_INIT_LOG(ERR, "Shared code init failed for igbvf: %d",
1065                         diag);
1066                 return -EIO;
1067         }
1068
1069         /* init_mailbox_params */
1070         hw->mbx.ops.init_params(hw);
1071
1072         /* Disable the interrupts for VF */
1073         igbvf_intr_disable(hw);
1074
1075         diag = hw->mac.ops.reset_hw(hw);
1076
1077         /* Allocate memory for storing MAC addresses */
1078         eth_dev->data->mac_addrs = rte_zmalloc("igbvf", ETHER_ADDR_LEN *
1079                 hw->mac.rar_entry_count, 0);
1080         if (eth_dev->data->mac_addrs == NULL) {
1081                 PMD_INIT_LOG(ERR,
1082                         "Failed to allocate %d bytes needed to store MAC "
1083                         "addresses",
1084                         ETHER_ADDR_LEN * hw->mac.rar_entry_count);
1085                 return -ENOMEM;
1086         }
1087
1088         /* Generate a random MAC address, if none was assigned by PF. */
1089         if (is_zero_ether_addr(perm_addr)) {
1090                 eth_random_addr(perm_addr->addr_bytes);
1091                 PMD_INIT_LOG(INFO, "\tVF MAC address not assigned by Host PF");
1092                 PMD_INIT_LOG(INFO, "\tAssign randomly generated MAC address "
1093                              "%02x:%02x:%02x:%02x:%02x:%02x",
1094                              perm_addr->addr_bytes[0],
1095                              perm_addr->addr_bytes[1],
1096                              perm_addr->addr_bytes[2],
1097                              perm_addr->addr_bytes[3],
1098                              perm_addr->addr_bytes[4],
1099                              perm_addr->addr_bytes[5]);
1100         }
1101
1102         diag = e1000_rar_set(hw, perm_addr->addr_bytes, 0);
1103         if (diag) {
1104                 rte_free(eth_dev->data->mac_addrs);
1105                 eth_dev->data->mac_addrs = NULL;
1106                 return diag;
1107         }
1108         /* Copy the permanent MAC address */
1109         ether_addr_copy((struct ether_addr *) hw->mac.perm_addr,
1110                         &eth_dev->data->mac_addrs[0]);
1111
1112         PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x "
1113                      "mac.type=%s",
1114                      eth_dev->data->port_id, pci_dev->id.vendor_id,
1115                      pci_dev->id.device_id, "igb_mac_82576_vf");
1116
1117         intr_handle = &pci_dev->intr_handle;
1118         rte_intr_callback_register(intr_handle,
1119                                    eth_igbvf_interrupt_handler, eth_dev);
1120
1121         return 0;
1122 }
1123
1124 static int
1125 eth_igbvf_dev_uninit(struct rte_eth_dev *eth_dev)
1126 {
1127         struct e1000_adapter *adapter =
1128                 E1000_DEV_PRIVATE(eth_dev->data->dev_private);
1129         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1130
1131         PMD_INIT_FUNC_TRACE();
1132
1133         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1134                 return -EPERM;
1135
1136         if (adapter->stopped == 0)
1137                 igbvf_dev_close(eth_dev);
1138
1139         eth_dev->dev_ops = NULL;
1140         eth_dev->rx_pkt_burst = NULL;
1141         eth_dev->tx_pkt_burst = NULL;
1142
1143         rte_free(eth_dev->data->mac_addrs);
1144         eth_dev->data->mac_addrs = NULL;
1145
1146         /* disable uio intr before callback unregister */
1147         rte_intr_disable(&pci_dev->intr_handle);
1148         rte_intr_callback_unregister(&pci_dev->intr_handle,
1149                                      eth_igbvf_interrupt_handler,
1150                                      (void *)eth_dev);
1151
1152         return 0;
1153 }
1154
1155 static int eth_igb_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
1156         struct rte_pci_device *pci_dev)
1157 {
1158         return rte_eth_dev_pci_generic_probe(pci_dev,
1159                 sizeof(struct e1000_adapter), eth_igb_dev_init);
1160 }
1161
1162 static int eth_igb_pci_remove(struct rte_pci_device *pci_dev)
1163 {
1164         return rte_eth_dev_pci_generic_remove(pci_dev, eth_igb_dev_uninit);
1165 }
1166
1167 static struct rte_pci_driver rte_igb_pmd = {
1168         .id_table = pci_id_igb_map,
1169         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
1170         .probe = eth_igb_pci_probe,
1171         .remove = eth_igb_pci_remove,
1172 };
1173
1174
1175 static int eth_igbvf_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
1176         struct rte_pci_device *pci_dev)
1177 {
1178         return rte_eth_dev_pci_generic_probe(pci_dev,
1179                 sizeof(struct e1000_adapter), eth_igbvf_dev_init);
1180 }
1181
1182 static int eth_igbvf_pci_remove(struct rte_pci_device *pci_dev)
1183 {
1184         return rte_eth_dev_pci_generic_remove(pci_dev, eth_igbvf_dev_uninit);
1185 }
1186
1187 /*
1188  * virtual function driver struct
1189  */
1190 static struct rte_pci_driver rte_igbvf_pmd = {
1191         .id_table = pci_id_igbvf_map,
1192         .drv_flags = RTE_PCI_DRV_NEED_MAPPING,
1193         .probe = eth_igbvf_pci_probe,
1194         .remove = eth_igbvf_pci_remove,
1195 };
1196
1197 static void
1198 igb_vmdq_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1199 {
1200         struct e1000_hw *hw =
1201                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1202         /* RCTL: enable VLAN filter since VMDq always use VLAN filter */
1203         uint32_t rctl = E1000_READ_REG(hw, E1000_RCTL);
1204         rctl |= E1000_RCTL_VFE;
1205         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1206 }
1207
1208 static int
1209 igb_check_mq_mode(struct rte_eth_dev *dev)
1210 {
1211         enum rte_eth_rx_mq_mode rx_mq_mode = dev->data->dev_conf.rxmode.mq_mode;
1212         enum rte_eth_tx_mq_mode tx_mq_mode = dev->data->dev_conf.txmode.mq_mode;
1213         uint16_t nb_rx_q = dev->data->nb_rx_queues;
1214         uint16_t nb_tx_q = dev->data->nb_rx_queues;
1215
1216         if ((rx_mq_mode & ETH_MQ_RX_DCB_FLAG) ||
1217             tx_mq_mode == ETH_MQ_TX_DCB ||
1218             tx_mq_mode == ETH_MQ_TX_VMDQ_DCB) {
1219                 PMD_INIT_LOG(ERR, "DCB mode is not supported.");
1220                 return -EINVAL;
1221         }
1222         if (RTE_ETH_DEV_SRIOV(dev).active != 0) {
1223                 /* Check multi-queue mode.
1224                  * To no break software we accept ETH_MQ_RX_NONE as this might
1225                  * be used to turn off VLAN filter.
1226                  */
1227
1228                 if (rx_mq_mode == ETH_MQ_RX_NONE ||
1229                     rx_mq_mode == ETH_MQ_RX_VMDQ_ONLY) {
1230                         dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_ONLY;
1231                         RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool = 1;
1232                 } else {
1233                         /* Only support one queue on VFs.
1234                          * RSS together with SRIOV is not supported.
1235                          */
1236                         PMD_INIT_LOG(ERR, "SRIOV is active,"
1237                                         " wrong mq_mode rx %d.",
1238                                         rx_mq_mode);
1239                         return -EINVAL;
1240                 }
1241                 /* TX mode is not used here, so mode might be ignored.*/
1242                 if (tx_mq_mode != ETH_MQ_TX_VMDQ_ONLY) {
1243                         /* SRIOV only works in VMDq enable mode */
1244                         PMD_INIT_LOG(WARNING, "SRIOV is active,"
1245                                         " TX mode %d is not supported. "
1246                                         " Driver will behave as %d mode.",
1247                                         tx_mq_mode, ETH_MQ_TX_VMDQ_ONLY);
1248                 }
1249
1250                 /* check valid queue number */
1251                 if ((nb_rx_q > 1) || (nb_tx_q > 1)) {
1252                         PMD_INIT_LOG(ERR, "SRIOV is active,"
1253                                         " only support one queue on VFs.");
1254                         return -EINVAL;
1255                 }
1256         } else {
1257                 /* To no break software that set invalid mode, only display
1258                  * warning if invalid mode is used.
1259                  */
1260                 if (rx_mq_mode != ETH_MQ_RX_NONE &&
1261                     rx_mq_mode != ETH_MQ_RX_VMDQ_ONLY &&
1262                     rx_mq_mode != ETH_MQ_RX_RSS) {
1263                         /* RSS together with VMDq not supported*/
1264                         PMD_INIT_LOG(ERR, "RX mode %d is not supported.",
1265                                      rx_mq_mode);
1266                         return -EINVAL;
1267                 }
1268
1269                 if (tx_mq_mode != ETH_MQ_TX_NONE &&
1270                     tx_mq_mode != ETH_MQ_TX_VMDQ_ONLY) {
1271                         PMD_INIT_LOG(WARNING, "TX mode %d is not supported."
1272                                         " Due to txmode is meaningless in this"
1273                                         " driver, just ignore.",
1274                                         tx_mq_mode);
1275                 }
1276         }
1277         return 0;
1278 }
1279
1280 static int
1281 eth_igb_configure(struct rte_eth_dev *dev)
1282 {
1283         struct e1000_interrupt *intr =
1284                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
1285         int ret;
1286
1287         PMD_INIT_FUNC_TRACE();
1288
1289         /* multipe queue mode checking */
1290         ret  = igb_check_mq_mode(dev);
1291         if (ret != 0) {
1292                 PMD_DRV_LOG(ERR, "igb_check_mq_mode fails with %d.",
1293                             ret);
1294                 return ret;
1295         }
1296
1297         intr->flags |= E1000_FLAG_NEED_LINK_UPDATE;
1298         PMD_INIT_FUNC_TRACE();
1299
1300         return 0;
1301 }
1302
1303 static int
1304 eth_igb_start(struct rte_eth_dev *dev)
1305 {
1306         struct e1000_hw *hw =
1307                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1308         struct e1000_adapter *adapter =
1309                 E1000_DEV_PRIVATE(dev->data->dev_private);
1310         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1311         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1312         int ret, mask;
1313         uint32_t intr_vector = 0;
1314         uint32_t ctrl_ext;
1315         uint32_t *speeds;
1316         int num_speeds;
1317         bool autoneg;
1318
1319         PMD_INIT_FUNC_TRACE();
1320
1321         /* disable uio/vfio intr/eventfd mapping */
1322         rte_intr_disable(intr_handle);
1323
1324         /* Power up the phy. Needed to make the link go Up */
1325         eth_igb_dev_set_link_up(dev);
1326
1327         /*
1328          * Packet Buffer Allocation (PBA)
1329          * Writing PBA sets the receive portion of the buffer
1330          * the remainder is used for the transmit buffer.
1331          */
1332         if (hw->mac.type == e1000_82575) {
1333                 uint32_t pba;
1334
1335                 pba = E1000_PBA_32K; /* 32K for Rx, 16K for Tx */
1336                 E1000_WRITE_REG(hw, E1000_PBA, pba);
1337         }
1338
1339         /* Put the address into the Receive Address Array */
1340         e1000_rar_set(hw, hw->mac.addr, 0);
1341
1342         /* Initialize the hardware */
1343         if (igb_hardware_init(hw)) {
1344                 PMD_INIT_LOG(ERR, "Unable to initialize the hardware");
1345                 return -EIO;
1346         }
1347         adapter->stopped = 0;
1348
1349         E1000_WRITE_REG(hw, E1000_VET, ETHER_TYPE_VLAN << 16 | ETHER_TYPE_VLAN);
1350
1351         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
1352         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
1353         ctrl_ext |= E1000_CTRL_EXT_PFRSTD;
1354         E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
1355         E1000_WRITE_FLUSH(hw);
1356
1357         /* configure PF module if SRIOV enabled */
1358         igb_pf_host_configure(dev);
1359
1360         /* check and configure queue intr-vector mapping */
1361         if ((rte_intr_cap_multiple(intr_handle) ||
1362              !RTE_ETH_DEV_SRIOV(dev).active) &&
1363             dev->data->dev_conf.intr_conf.rxq != 0) {
1364                 intr_vector = dev->data->nb_rx_queues;
1365                 if (rte_intr_efd_enable(intr_handle, intr_vector))
1366                         return -1;
1367         }
1368
1369         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
1370                 intr_handle->intr_vec =
1371                         rte_zmalloc("intr_vec",
1372                                     dev->data->nb_rx_queues * sizeof(int), 0);
1373                 if (intr_handle->intr_vec == NULL) {
1374                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
1375                                      " intr_vec", dev->data->nb_rx_queues);
1376                         return -ENOMEM;
1377                 }
1378         }
1379
1380         /* confiugre msix for rx interrupt */
1381         eth_igb_configure_msix_intr(dev);
1382
1383         /* Configure for OS presence */
1384         igb_init_manageability(hw);
1385
1386         eth_igb_tx_init(dev);
1387
1388         /* This can fail when allocating mbufs for descriptor rings */
1389         ret = eth_igb_rx_init(dev);
1390         if (ret) {
1391                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
1392                 igb_dev_clear_queues(dev);
1393                 return ret;
1394         }
1395
1396         e1000_clear_hw_cntrs_base_generic(hw);
1397
1398         /*
1399          * VLAN Offload Settings
1400          */
1401         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK | \
1402                         ETH_VLAN_EXTEND_MASK;
1403         eth_igb_vlan_offload_set(dev, mask);
1404
1405         if (dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_VMDQ_ONLY) {
1406                 /* Enable VLAN filter since VMDq always use VLAN filter */
1407                 igb_vmdq_vlan_hw_filter_enable(dev);
1408         }
1409
1410         if ((hw->mac.type == e1000_82576) || (hw->mac.type == e1000_82580) ||
1411                 (hw->mac.type == e1000_i350) || (hw->mac.type == e1000_i210) ||
1412                 (hw->mac.type == e1000_i211)) {
1413                 /* Configure EITR with the maximum possible value (0xFFFF) */
1414                 E1000_WRITE_REG(hw, E1000_EITR(0), 0xFFFF);
1415         }
1416
1417         /* Setup link speed and duplex */
1418         speeds = &dev->data->dev_conf.link_speeds;
1419         if (*speeds == ETH_LINK_SPEED_AUTONEG) {
1420                 hw->phy.autoneg_advertised = E1000_ALL_SPEED_DUPLEX;
1421                 hw->mac.autoneg = 1;
1422         } else {
1423                 num_speeds = 0;
1424                 autoneg = (*speeds & ETH_LINK_SPEED_FIXED) == 0;
1425
1426                 /* Reset */
1427                 hw->phy.autoneg_advertised = 0;
1428
1429                 if (*speeds & ~(ETH_LINK_SPEED_10M_HD | ETH_LINK_SPEED_10M |
1430                                 ETH_LINK_SPEED_100M_HD | ETH_LINK_SPEED_100M |
1431                                 ETH_LINK_SPEED_1G | ETH_LINK_SPEED_FIXED)) {
1432                         num_speeds = -1;
1433                         goto error_invalid_config;
1434                 }
1435                 if (*speeds & ETH_LINK_SPEED_10M_HD) {
1436                         hw->phy.autoneg_advertised |= ADVERTISE_10_HALF;
1437                         num_speeds++;
1438                 }
1439                 if (*speeds & ETH_LINK_SPEED_10M) {
1440                         hw->phy.autoneg_advertised |= ADVERTISE_10_FULL;
1441                         num_speeds++;
1442                 }
1443                 if (*speeds & ETH_LINK_SPEED_100M_HD) {
1444                         hw->phy.autoneg_advertised |= ADVERTISE_100_HALF;
1445                         num_speeds++;
1446                 }
1447                 if (*speeds & ETH_LINK_SPEED_100M) {
1448                         hw->phy.autoneg_advertised |= ADVERTISE_100_FULL;
1449                         num_speeds++;
1450                 }
1451                 if (*speeds & ETH_LINK_SPEED_1G) {
1452                         hw->phy.autoneg_advertised |= ADVERTISE_1000_FULL;
1453                         num_speeds++;
1454                 }
1455                 if (num_speeds == 0 || (!autoneg && (num_speeds > 1)))
1456                         goto error_invalid_config;
1457
1458                 /* Set/reset the mac.autoneg based on the link speed,
1459                  * fixed or not
1460                  */
1461                 if (!autoneg) {
1462                         hw->mac.autoneg = 0;
1463                         hw->mac.forced_speed_duplex =
1464                                         hw->phy.autoneg_advertised;
1465                 } else {
1466                         hw->mac.autoneg = 1;
1467                 }
1468         }
1469
1470         e1000_setup_link(hw);
1471
1472         if (rte_intr_allow_others(intr_handle)) {
1473                 /* check if lsc interrupt is enabled */
1474                 if (dev->data->dev_conf.intr_conf.lsc != 0)
1475                         eth_igb_lsc_interrupt_setup(dev, TRUE);
1476                 else
1477                         eth_igb_lsc_interrupt_setup(dev, FALSE);
1478         } else {
1479                 rte_intr_callback_unregister(intr_handle,
1480                                              eth_igb_interrupt_handler,
1481                                              (void *)dev);
1482                 if (dev->data->dev_conf.intr_conf.lsc != 0)
1483                         PMD_INIT_LOG(INFO, "lsc won't enable because of"
1484                                      " no intr multiplex");
1485         }
1486
1487         /* check if rxq interrupt is enabled */
1488         if (dev->data->dev_conf.intr_conf.rxq != 0 &&
1489             rte_intr_dp_is_en(intr_handle))
1490                 eth_igb_rxq_interrupt_setup(dev);
1491
1492         /* enable uio/vfio intr/eventfd mapping */
1493         rte_intr_enable(intr_handle);
1494
1495         /* resume enabled intr since hw reset */
1496         igb_intr_enable(dev);
1497
1498         /* restore all types filter */
1499         igb_filter_restore(dev);
1500
1501         PMD_INIT_LOG(DEBUG, "<<");
1502
1503         return 0;
1504
1505 error_invalid_config:
1506         PMD_INIT_LOG(ERR, "Invalid advertised speeds (%u) for port %u",
1507                      dev->data->dev_conf.link_speeds, dev->data->port_id);
1508         igb_dev_clear_queues(dev);
1509         return -EINVAL;
1510 }
1511
1512 /*********************************************************************
1513  *
1514  *  This routine disables all traffic on the adapter by issuing a
1515  *  global reset on the MAC.
1516  *
1517  **********************************************************************/
1518 static void
1519 eth_igb_stop(struct rte_eth_dev *dev)
1520 {
1521         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1522         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1523         struct rte_eth_link link;
1524         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1525
1526         igb_intr_disable(hw);
1527
1528         /* disable intr eventfd mapping */
1529         rte_intr_disable(intr_handle);
1530
1531         igb_pf_reset_hw(hw);
1532         E1000_WRITE_REG(hw, E1000_WUC, 0);
1533
1534         /* Set bit for Go Link disconnect */
1535         if (hw->mac.type >= e1000_82580) {
1536                 uint32_t phpm_reg;
1537
1538                 phpm_reg = E1000_READ_REG(hw, E1000_82580_PHY_POWER_MGMT);
1539                 phpm_reg |= E1000_82580_PM_GO_LINKD;
1540                 E1000_WRITE_REG(hw, E1000_82580_PHY_POWER_MGMT, phpm_reg);
1541         }
1542
1543         /* Power down the phy. Needed to make the link go Down */
1544         eth_igb_dev_set_link_down(dev);
1545
1546         igb_dev_clear_queues(dev);
1547
1548         /* clear the recorded link status */
1549         memset(&link, 0, sizeof(link));
1550         rte_igb_dev_atomic_write_link_status(dev, &link);
1551
1552         if (!rte_intr_allow_others(intr_handle))
1553                 /* resume to the default handler */
1554                 rte_intr_callback_register(intr_handle,
1555                                            eth_igb_interrupt_handler,
1556                                            (void *)dev);
1557
1558         /* Clean datapath event and queue/vec mapping */
1559         rte_intr_efd_disable(intr_handle);
1560         if (intr_handle->intr_vec != NULL) {
1561                 rte_free(intr_handle->intr_vec);
1562                 intr_handle->intr_vec = NULL;
1563         }
1564 }
1565
1566 static int
1567 eth_igb_dev_set_link_up(struct rte_eth_dev *dev)
1568 {
1569         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1570
1571         if (hw->phy.media_type == e1000_media_type_copper)
1572                 e1000_power_up_phy(hw);
1573         else
1574                 e1000_power_up_fiber_serdes_link(hw);
1575
1576         return 0;
1577 }
1578
1579 static int
1580 eth_igb_dev_set_link_down(struct rte_eth_dev *dev)
1581 {
1582         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1583
1584         if (hw->phy.media_type == e1000_media_type_copper)
1585                 e1000_power_down_phy(hw);
1586         else
1587                 e1000_shutdown_fiber_serdes_link(hw);
1588
1589         return 0;
1590 }
1591
1592 static void
1593 eth_igb_close(struct rte_eth_dev *dev)
1594 {
1595         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1596         struct e1000_adapter *adapter =
1597                 E1000_DEV_PRIVATE(dev->data->dev_private);
1598         struct rte_eth_link link;
1599         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1600         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1601
1602         eth_igb_stop(dev);
1603         adapter->stopped = 1;
1604
1605         e1000_phy_hw_reset(hw);
1606         igb_release_manageability(hw);
1607         igb_hw_control_release(hw);
1608
1609         /* Clear bit for Go Link disconnect */
1610         if (hw->mac.type >= e1000_82580) {
1611                 uint32_t phpm_reg;
1612
1613                 phpm_reg = E1000_READ_REG(hw, E1000_82580_PHY_POWER_MGMT);
1614                 phpm_reg &= ~E1000_82580_PM_GO_LINKD;
1615                 E1000_WRITE_REG(hw, E1000_82580_PHY_POWER_MGMT, phpm_reg);
1616         }
1617
1618         igb_dev_free_queues(dev);
1619
1620         if (intr_handle->intr_vec) {
1621                 rte_free(intr_handle->intr_vec);
1622                 intr_handle->intr_vec = NULL;
1623         }
1624
1625         memset(&link, 0, sizeof(link));
1626         rte_igb_dev_atomic_write_link_status(dev, &link);
1627 }
1628
1629 static int
1630 igb_get_rx_buffer_size(struct e1000_hw *hw)
1631 {
1632         uint32_t rx_buf_size;
1633         if (hw->mac.type == e1000_82576) {
1634                 rx_buf_size = (E1000_READ_REG(hw, E1000_RXPBS) & 0xffff) << 10;
1635         } else if (hw->mac.type == e1000_82580 || hw->mac.type == e1000_i350) {
1636                 /* PBS needs to be translated according to a lookup table */
1637                 rx_buf_size = (E1000_READ_REG(hw, E1000_RXPBS) & 0xf);
1638                 rx_buf_size = (uint32_t) e1000_rxpbs_adjust_82580(rx_buf_size);
1639                 rx_buf_size = (rx_buf_size << 10);
1640         } else if (hw->mac.type == e1000_i210 || hw->mac.type == e1000_i211) {
1641                 rx_buf_size = (E1000_READ_REG(hw, E1000_RXPBS) & 0x3f) << 10;
1642         } else {
1643                 rx_buf_size = (E1000_READ_REG(hw, E1000_PBA) & 0xffff) << 10;
1644         }
1645
1646         return rx_buf_size;
1647 }
1648
1649 /*********************************************************************
1650  *
1651  *  Initialize the hardware
1652  *
1653  **********************************************************************/
1654 static int
1655 igb_hardware_init(struct e1000_hw *hw)
1656 {
1657         uint32_t rx_buf_size;
1658         int diag;
1659
1660         /* Let the firmware know the OS is in control */
1661         igb_hw_control_acquire(hw);
1662
1663         /*
1664          * These parameters control the automatic generation (Tx) and
1665          * response (Rx) to Ethernet PAUSE frames.
1666          * - High water mark should allow for at least two standard size (1518)
1667          *   frames to be received after sending an XOFF.
1668          * - Low water mark works best when it is very near the high water mark.
1669          *   This allows the receiver to restart by sending XON when it has
1670          *   drained a bit. Here we use an arbitrary value of 1500 which will
1671          *   restart after one full frame is pulled from the buffer. There
1672          *   could be several smaller frames in the buffer and if so they will
1673          *   not trigger the XON until their total number reduces the buffer
1674          *   by 1500.
1675          * - The pause time is fairly large at 1000 x 512ns = 512 usec.
1676          */
1677         rx_buf_size = igb_get_rx_buffer_size(hw);
1678
1679         hw->fc.high_water = rx_buf_size - (ETHER_MAX_LEN * 2);
1680         hw->fc.low_water = hw->fc.high_water - 1500;
1681         hw->fc.pause_time = IGB_FC_PAUSE_TIME;
1682         hw->fc.send_xon = 1;
1683
1684         /* Set Flow control, use the tunable location if sane */
1685         if ((igb_fc_setting != e1000_fc_none) && (igb_fc_setting < 4))
1686                 hw->fc.requested_mode = igb_fc_setting;
1687         else
1688                 hw->fc.requested_mode = e1000_fc_none;
1689
1690         /* Issue a global reset */
1691         igb_pf_reset_hw(hw);
1692         E1000_WRITE_REG(hw, E1000_WUC, 0);
1693
1694         diag = e1000_init_hw(hw);
1695         if (diag < 0)
1696                 return diag;
1697
1698         E1000_WRITE_REG(hw, E1000_VET, ETHER_TYPE_VLAN << 16 | ETHER_TYPE_VLAN);
1699         e1000_get_phy_info(hw);
1700         e1000_check_for_link(hw);
1701
1702         return 0;
1703 }
1704
1705 /* This function is based on igb_update_stats_counters() in igb/if_igb.c */
1706 static void
1707 igb_read_stats_registers(struct e1000_hw *hw, struct e1000_hw_stats *stats)
1708 {
1709         int pause_frames;
1710
1711         uint64_t old_gprc  = stats->gprc;
1712         uint64_t old_gptc  = stats->gptc;
1713         uint64_t old_tpr   = stats->tpr;
1714         uint64_t old_tpt   = stats->tpt;
1715         uint64_t old_rpthc = stats->rpthc;
1716         uint64_t old_hgptc = stats->hgptc;
1717
1718         if(hw->phy.media_type == e1000_media_type_copper ||
1719             (E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU)) {
1720                 stats->symerrs +=
1721                     E1000_READ_REG(hw,E1000_SYMERRS);
1722                 stats->sec += E1000_READ_REG(hw, E1000_SEC);
1723         }
1724
1725         stats->crcerrs += E1000_READ_REG(hw, E1000_CRCERRS);
1726         stats->mpc += E1000_READ_REG(hw, E1000_MPC);
1727         stats->scc += E1000_READ_REG(hw, E1000_SCC);
1728         stats->ecol += E1000_READ_REG(hw, E1000_ECOL);
1729
1730         stats->mcc += E1000_READ_REG(hw, E1000_MCC);
1731         stats->latecol += E1000_READ_REG(hw, E1000_LATECOL);
1732         stats->colc += E1000_READ_REG(hw, E1000_COLC);
1733         stats->dc += E1000_READ_REG(hw, E1000_DC);
1734         stats->rlec += E1000_READ_REG(hw, E1000_RLEC);
1735         stats->xonrxc += E1000_READ_REG(hw, E1000_XONRXC);
1736         stats->xontxc += E1000_READ_REG(hw, E1000_XONTXC);
1737         /*
1738         ** For watchdog management we need to know if we have been
1739         ** paused during the last interval, so capture that here.
1740         */
1741         pause_frames = E1000_READ_REG(hw, E1000_XOFFRXC);
1742         stats->xoffrxc += pause_frames;
1743         stats->xofftxc += E1000_READ_REG(hw, E1000_XOFFTXC);
1744         stats->fcruc += E1000_READ_REG(hw, E1000_FCRUC);
1745         stats->prc64 += E1000_READ_REG(hw, E1000_PRC64);
1746         stats->prc127 += E1000_READ_REG(hw, E1000_PRC127);
1747         stats->prc255 += E1000_READ_REG(hw, E1000_PRC255);
1748         stats->prc511 += E1000_READ_REG(hw, E1000_PRC511);
1749         stats->prc1023 += E1000_READ_REG(hw, E1000_PRC1023);
1750         stats->prc1522 += E1000_READ_REG(hw, E1000_PRC1522);
1751         stats->gprc += E1000_READ_REG(hw, E1000_GPRC);
1752         stats->bprc += E1000_READ_REG(hw, E1000_BPRC);
1753         stats->mprc += E1000_READ_REG(hw, E1000_MPRC);
1754         stats->gptc += E1000_READ_REG(hw, E1000_GPTC);
1755
1756         /* For the 64-bit byte counters the low dword must be read first. */
1757         /* Both registers clear on the read of the high dword */
1758
1759         /* Workaround CRC bytes included in size, take away 4 bytes/packet */
1760         stats->gorc += E1000_READ_REG(hw, E1000_GORCL);
1761         stats->gorc += ((uint64_t)E1000_READ_REG(hw, E1000_GORCH) << 32);
1762         stats->gorc -= (stats->gprc - old_gprc) * ETHER_CRC_LEN;
1763         stats->gotc += E1000_READ_REG(hw, E1000_GOTCL);
1764         stats->gotc += ((uint64_t)E1000_READ_REG(hw, E1000_GOTCH) << 32);
1765         stats->gotc -= (stats->gptc - old_gptc) * ETHER_CRC_LEN;
1766
1767         stats->rnbc += E1000_READ_REG(hw, E1000_RNBC);
1768         stats->ruc += E1000_READ_REG(hw, E1000_RUC);
1769         stats->rfc += E1000_READ_REG(hw, E1000_RFC);
1770         stats->roc += E1000_READ_REG(hw, E1000_ROC);
1771         stats->rjc += E1000_READ_REG(hw, E1000_RJC);
1772
1773         stats->tpr += E1000_READ_REG(hw, E1000_TPR);
1774         stats->tpt += E1000_READ_REG(hw, E1000_TPT);
1775
1776         stats->tor += E1000_READ_REG(hw, E1000_TORL);
1777         stats->tor += ((uint64_t)E1000_READ_REG(hw, E1000_TORH) << 32);
1778         stats->tor -= (stats->tpr - old_tpr) * ETHER_CRC_LEN;
1779         stats->tot += E1000_READ_REG(hw, E1000_TOTL);
1780         stats->tot += ((uint64_t)E1000_READ_REG(hw, E1000_TOTH) << 32);
1781         stats->tot -= (stats->tpt - old_tpt) * ETHER_CRC_LEN;
1782
1783         stats->ptc64 += E1000_READ_REG(hw, E1000_PTC64);
1784         stats->ptc127 += E1000_READ_REG(hw, E1000_PTC127);
1785         stats->ptc255 += E1000_READ_REG(hw, E1000_PTC255);
1786         stats->ptc511 += E1000_READ_REG(hw, E1000_PTC511);
1787         stats->ptc1023 += E1000_READ_REG(hw, E1000_PTC1023);
1788         stats->ptc1522 += E1000_READ_REG(hw, E1000_PTC1522);
1789         stats->mptc += E1000_READ_REG(hw, E1000_MPTC);
1790         stats->bptc += E1000_READ_REG(hw, E1000_BPTC);
1791
1792         /* Interrupt Counts */
1793
1794         stats->iac += E1000_READ_REG(hw, E1000_IAC);
1795         stats->icrxptc += E1000_READ_REG(hw, E1000_ICRXPTC);
1796         stats->icrxatc += E1000_READ_REG(hw, E1000_ICRXATC);
1797         stats->ictxptc += E1000_READ_REG(hw, E1000_ICTXPTC);
1798         stats->ictxatc += E1000_READ_REG(hw, E1000_ICTXATC);
1799         stats->ictxqec += E1000_READ_REG(hw, E1000_ICTXQEC);
1800         stats->ictxqmtc += E1000_READ_REG(hw, E1000_ICTXQMTC);
1801         stats->icrxdmtc += E1000_READ_REG(hw, E1000_ICRXDMTC);
1802         stats->icrxoc += E1000_READ_REG(hw, E1000_ICRXOC);
1803
1804         /* Host to Card Statistics */
1805
1806         stats->cbtmpc += E1000_READ_REG(hw, E1000_CBTMPC);
1807         stats->htdpmc += E1000_READ_REG(hw, E1000_HTDPMC);
1808         stats->cbrdpc += E1000_READ_REG(hw, E1000_CBRDPC);
1809         stats->cbrmpc += E1000_READ_REG(hw, E1000_CBRMPC);
1810         stats->rpthc += E1000_READ_REG(hw, E1000_RPTHC);
1811         stats->hgptc += E1000_READ_REG(hw, E1000_HGPTC);
1812         stats->htcbdpc += E1000_READ_REG(hw, E1000_HTCBDPC);
1813         stats->hgorc += E1000_READ_REG(hw, E1000_HGORCL);
1814         stats->hgorc += ((uint64_t)E1000_READ_REG(hw, E1000_HGORCH) << 32);
1815         stats->hgorc -= (stats->rpthc - old_rpthc) * ETHER_CRC_LEN;
1816         stats->hgotc += E1000_READ_REG(hw, E1000_HGOTCL);
1817         stats->hgotc += ((uint64_t)E1000_READ_REG(hw, E1000_HGOTCH) << 32);
1818         stats->hgotc -= (stats->hgptc - old_hgptc) * ETHER_CRC_LEN;
1819         stats->lenerrs += E1000_READ_REG(hw, E1000_LENERRS);
1820         stats->scvpc += E1000_READ_REG(hw, E1000_SCVPC);
1821         stats->hrmpc += E1000_READ_REG(hw, E1000_HRMPC);
1822
1823         stats->algnerrc += E1000_READ_REG(hw, E1000_ALGNERRC);
1824         stats->rxerrc += E1000_READ_REG(hw, E1000_RXERRC);
1825         stats->tncrs += E1000_READ_REG(hw, E1000_TNCRS);
1826         stats->cexterr += E1000_READ_REG(hw, E1000_CEXTERR);
1827         stats->tsctc += E1000_READ_REG(hw, E1000_TSCTC);
1828         stats->tsctfc += E1000_READ_REG(hw, E1000_TSCTFC);
1829 }
1830
1831 static void
1832 eth_igb_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *rte_stats)
1833 {
1834         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1835         struct e1000_hw_stats *stats =
1836                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1837
1838         igb_read_stats_registers(hw, stats);
1839
1840         if (rte_stats == NULL)
1841                 return;
1842
1843         /* Rx Errors */
1844         rte_stats->imissed = stats->mpc;
1845         rte_stats->ierrors = stats->crcerrs +
1846                              stats->rlec + stats->ruc + stats->roc +
1847                              stats->rxerrc + stats->algnerrc + stats->cexterr;
1848
1849         /* Tx Errors */
1850         rte_stats->oerrors = stats->ecol + stats->latecol;
1851
1852         rte_stats->ipackets = stats->gprc;
1853         rte_stats->opackets = stats->gptc;
1854         rte_stats->ibytes   = stats->gorc;
1855         rte_stats->obytes   = stats->gotc;
1856 }
1857
1858 static void
1859 eth_igb_stats_reset(struct rte_eth_dev *dev)
1860 {
1861         struct e1000_hw_stats *hw_stats =
1862                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1863
1864         /* HW registers are cleared on read */
1865         eth_igb_stats_get(dev, NULL);
1866
1867         /* Reset software totals */
1868         memset(hw_stats, 0, sizeof(*hw_stats));
1869 }
1870
1871 static void
1872 eth_igb_xstats_reset(struct rte_eth_dev *dev)
1873 {
1874         struct e1000_hw_stats *stats =
1875                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1876
1877         /* HW registers are cleared on read */
1878         eth_igb_xstats_get(dev, NULL, IGB_NB_XSTATS);
1879
1880         /* Reset software totals */
1881         memset(stats, 0, sizeof(*stats));
1882 }
1883
1884 static int eth_igb_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
1885         struct rte_eth_xstat_name *xstats_names,
1886         __rte_unused unsigned int size)
1887 {
1888         unsigned i;
1889
1890         if (xstats_names == NULL)
1891                 return IGB_NB_XSTATS;
1892
1893         /* Note: limit checked in rte_eth_xstats_names() */
1894
1895         for (i = 0; i < IGB_NB_XSTATS; i++) {
1896                 snprintf(xstats_names[i].name, sizeof(xstats_names[i].name),
1897                          "%s", rte_igb_stats_strings[i].name);
1898         }
1899
1900         return IGB_NB_XSTATS;
1901 }
1902
1903 static int eth_igb_xstats_get_names_by_id(struct rte_eth_dev *dev,
1904                 struct rte_eth_xstat_name *xstats_names, const uint64_t *ids,
1905                 unsigned int limit)
1906 {
1907         unsigned int i;
1908
1909         if (!ids) {
1910                 if (xstats_names == NULL)
1911                         return IGB_NB_XSTATS;
1912
1913                 for (i = 0; i < IGB_NB_XSTATS; i++)
1914                         snprintf(xstats_names[i].name,
1915                                         sizeof(xstats_names[i].name),
1916                                         "%s", rte_igb_stats_strings[i].name);
1917
1918                 return IGB_NB_XSTATS;
1919
1920         } else {
1921                 struct rte_eth_xstat_name xstats_names_copy[IGB_NB_XSTATS];
1922
1923                 eth_igb_xstats_get_names_by_id(dev, xstats_names_copy, NULL,
1924                                 IGB_NB_XSTATS);
1925
1926                 for (i = 0; i < limit; i++) {
1927                         if (ids[i] >= IGB_NB_XSTATS) {
1928                                 PMD_INIT_LOG(ERR, "id value isn't valid");
1929                                 return -1;
1930                         }
1931                         strcpy(xstats_names[i].name,
1932                                         xstats_names_copy[ids[i]].name);
1933                 }
1934                 return limit;
1935         }
1936 }
1937
1938 static int
1939 eth_igb_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
1940                    unsigned n)
1941 {
1942         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1943         struct e1000_hw_stats *hw_stats =
1944                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1945         unsigned i;
1946
1947         if (n < IGB_NB_XSTATS)
1948                 return IGB_NB_XSTATS;
1949
1950         igb_read_stats_registers(hw, hw_stats);
1951
1952         /* If this is a reset xstats is NULL, and we have cleared the
1953          * registers by reading them.
1954          */
1955         if (!xstats)
1956                 return 0;
1957
1958         /* Extended stats */
1959         for (i = 0; i < IGB_NB_XSTATS; i++) {
1960                 xstats[i].id = i;
1961                 xstats[i].value = *(uint64_t *)(((char *)hw_stats) +
1962                         rte_igb_stats_strings[i].offset);
1963         }
1964
1965         return IGB_NB_XSTATS;
1966 }
1967
1968 static int
1969 eth_igb_xstats_get_by_id(struct rte_eth_dev *dev, const uint64_t *ids,
1970                 uint64_t *values, unsigned int n)
1971 {
1972         unsigned int i;
1973
1974         if (!ids) {
1975                 struct e1000_hw *hw =
1976                         E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1977                 struct e1000_hw_stats *hw_stats =
1978                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1979
1980                 if (n < IGB_NB_XSTATS)
1981                         return IGB_NB_XSTATS;
1982
1983                 igb_read_stats_registers(hw, hw_stats);
1984
1985                 /* If this is a reset xstats is NULL, and we have cleared the
1986                  * registers by reading them.
1987                  */
1988                 if (!values)
1989                         return 0;
1990
1991                 /* Extended stats */
1992                 for (i = 0; i < IGB_NB_XSTATS; i++)
1993                         values[i] = *(uint64_t *)(((char *)hw_stats) +
1994                                         rte_igb_stats_strings[i].offset);
1995
1996                 return IGB_NB_XSTATS;
1997
1998         } else {
1999                 uint64_t values_copy[IGB_NB_XSTATS];
2000
2001                 eth_igb_xstats_get_by_id(dev, NULL, values_copy,
2002                                 IGB_NB_XSTATS);
2003
2004                 for (i = 0; i < n; i++) {
2005                         if (ids[i] >= IGB_NB_XSTATS) {
2006                                 PMD_INIT_LOG(ERR, "id value isn't valid");
2007                                 return -1;
2008                         }
2009                         values[i] = values_copy[ids[i]];
2010                 }
2011                 return n;
2012         }
2013 }
2014
2015 static void
2016 igbvf_read_stats_registers(struct e1000_hw *hw, struct e1000_vf_stats *hw_stats)
2017 {
2018         /* Good Rx packets, include VF loopback */
2019         UPDATE_VF_STAT(E1000_VFGPRC,
2020             hw_stats->last_gprc, hw_stats->gprc);
2021
2022         /* Good Rx octets, include VF loopback */
2023         UPDATE_VF_STAT(E1000_VFGORC,
2024             hw_stats->last_gorc, hw_stats->gorc);
2025
2026         /* Good Tx packets, include VF loopback */
2027         UPDATE_VF_STAT(E1000_VFGPTC,
2028             hw_stats->last_gptc, hw_stats->gptc);
2029
2030         /* Good Tx octets, include VF loopback */
2031         UPDATE_VF_STAT(E1000_VFGOTC,
2032             hw_stats->last_gotc, hw_stats->gotc);
2033
2034         /* Rx Multicst packets */
2035         UPDATE_VF_STAT(E1000_VFMPRC,
2036             hw_stats->last_mprc, hw_stats->mprc);
2037
2038         /* Good Rx loopback packets */
2039         UPDATE_VF_STAT(E1000_VFGPRLBC,
2040             hw_stats->last_gprlbc, hw_stats->gprlbc);
2041
2042         /* Good Rx loopback octets */
2043         UPDATE_VF_STAT(E1000_VFGORLBC,
2044             hw_stats->last_gorlbc, hw_stats->gorlbc);
2045
2046         /* Good Tx loopback packets */
2047         UPDATE_VF_STAT(E1000_VFGPTLBC,
2048             hw_stats->last_gptlbc, hw_stats->gptlbc);
2049
2050         /* Good Tx loopback octets */
2051         UPDATE_VF_STAT(E1000_VFGOTLBC,
2052             hw_stats->last_gotlbc, hw_stats->gotlbc);
2053 }
2054
2055 static int eth_igbvf_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
2056                                      struct rte_eth_xstat_name *xstats_names,
2057                                      __rte_unused unsigned limit)
2058 {
2059         unsigned i;
2060
2061         if (xstats_names != NULL)
2062                 for (i = 0; i < IGBVF_NB_XSTATS; i++) {
2063                         snprintf(xstats_names[i].name,
2064                                 sizeof(xstats_names[i].name), "%s",
2065                                 rte_igbvf_stats_strings[i].name);
2066                 }
2067         return IGBVF_NB_XSTATS;
2068 }
2069
2070 static int
2071 eth_igbvf_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
2072                      unsigned n)
2073 {
2074         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2075         struct e1000_vf_stats *hw_stats = (struct e1000_vf_stats *)
2076                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2077         unsigned i;
2078
2079         if (n < IGBVF_NB_XSTATS)
2080                 return IGBVF_NB_XSTATS;
2081
2082         igbvf_read_stats_registers(hw, hw_stats);
2083
2084         if (!xstats)
2085                 return 0;
2086
2087         for (i = 0; i < IGBVF_NB_XSTATS; i++) {
2088                 xstats[i].id = i;
2089                 xstats[i].value = *(uint64_t *)(((char *)hw_stats) +
2090                         rte_igbvf_stats_strings[i].offset);
2091         }
2092
2093         return IGBVF_NB_XSTATS;
2094 }
2095
2096 static void
2097 eth_igbvf_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *rte_stats)
2098 {
2099         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2100         struct e1000_vf_stats *hw_stats = (struct e1000_vf_stats *)
2101                           E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2102
2103         igbvf_read_stats_registers(hw, hw_stats);
2104
2105         if (rte_stats == NULL)
2106                 return;
2107
2108         rte_stats->ipackets = hw_stats->gprc;
2109         rte_stats->ibytes = hw_stats->gorc;
2110         rte_stats->opackets = hw_stats->gptc;
2111         rte_stats->obytes = hw_stats->gotc;
2112 }
2113
2114 static void
2115 eth_igbvf_stats_reset(struct rte_eth_dev *dev)
2116 {
2117         struct e1000_vf_stats *hw_stats = (struct e1000_vf_stats*)
2118                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2119
2120         /* Sync HW register to the last stats */
2121         eth_igbvf_stats_get(dev, NULL);
2122
2123         /* reset HW current stats*/
2124         memset(&hw_stats->gprc, 0, sizeof(*hw_stats) -
2125                offsetof(struct e1000_vf_stats, gprc));
2126 }
2127
2128 static int
2129 eth_igb_fw_version_get(struct rte_eth_dev *dev, char *fw_version,
2130                        size_t fw_size)
2131 {
2132         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2133         struct e1000_fw_version fw;
2134         int ret;
2135
2136         e1000_get_fw_version(hw, &fw);
2137
2138         switch (hw->mac.type) {
2139         case e1000_i210:
2140         case e1000_i211:
2141                 if (!(e1000_get_flash_presence_i210(hw))) {
2142                         ret = snprintf(fw_version, fw_size,
2143                                  "%2d.%2d-%d",
2144                                  fw.invm_major, fw.invm_minor,
2145                                  fw.invm_img_type);
2146                         break;
2147                 }
2148                 /* fall through */
2149         default:
2150                 /* if option rom is valid, display its version too */
2151                 if (fw.or_valid) {
2152                         ret = snprintf(fw_version, fw_size,
2153                                  "%d.%d, 0x%08x, %d.%d.%d",
2154                                  fw.eep_major, fw.eep_minor, fw.etrack_id,
2155                                  fw.or_major, fw.or_build, fw.or_patch);
2156                 /* no option rom */
2157                 } else {
2158                         if (fw.etrack_id != 0X0000) {
2159                                 ret = snprintf(fw_version, fw_size,
2160                                          "%d.%d, 0x%08x",
2161                                          fw.eep_major, fw.eep_minor,
2162                                          fw.etrack_id);
2163                         } else {
2164                                 ret = snprintf(fw_version, fw_size,
2165                                          "%d.%d.%d",
2166                                          fw.eep_major, fw.eep_minor,
2167                                          fw.eep_build);
2168                         }
2169                 }
2170                 break;
2171         }
2172
2173         ret += 1; /* add the size of '\0' */
2174         if (fw_size < (u32)ret)
2175                 return ret;
2176         else
2177                 return 0;
2178 }
2179
2180 static void
2181 eth_igb_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
2182 {
2183         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2184
2185         dev_info->pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2186         dev_info->min_rx_bufsize = 256; /* See BSIZE field of RCTL register. */
2187         dev_info->max_rx_pktlen  = 0x3FFF; /* See RLPML register. */
2188         dev_info->max_mac_addrs = hw->mac.rar_entry_count;
2189         dev_info->rx_offload_capa =
2190                 DEV_RX_OFFLOAD_VLAN_STRIP |
2191                 DEV_RX_OFFLOAD_IPV4_CKSUM |
2192                 DEV_RX_OFFLOAD_UDP_CKSUM  |
2193                 DEV_RX_OFFLOAD_TCP_CKSUM;
2194         dev_info->tx_offload_capa =
2195                 DEV_TX_OFFLOAD_VLAN_INSERT |
2196                 DEV_TX_OFFLOAD_IPV4_CKSUM  |
2197                 DEV_TX_OFFLOAD_UDP_CKSUM   |
2198                 DEV_TX_OFFLOAD_TCP_CKSUM   |
2199                 DEV_TX_OFFLOAD_SCTP_CKSUM  |
2200                 DEV_TX_OFFLOAD_TCP_TSO;
2201
2202         switch (hw->mac.type) {
2203         case e1000_82575:
2204                 dev_info->max_rx_queues = 4;
2205                 dev_info->max_tx_queues = 4;
2206                 dev_info->max_vmdq_pools = 0;
2207                 break;
2208
2209         case e1000_82576:
2210                 dev_info->max_rx_queues = 16;
2211                 dev_info->max_tx_queues = 16;
2212                 dev_info->max_vmdq_pools = ETH_8_POOLS;
2213                 dev_info->vmdq_queue_num = 16;
2214                 break;
2215
2216         case e1000_82580:
2217                 dev_info->max_rx_queues = 8;
2218                 dev_info->max_tx_queues = 8;
2219                 dev_info->max_vmdq_pools = ETH_8_POOLS;
2220                 dev_info->vmdq_queue_num = 8;
2221                 break;
2222
2223         case e1000_i350:
2224                 dev_info->max_rx_queues = 8;
2225                 dev_info->max_tx_queues = 8;
2226                 dev_info->max_vmdq_pools = ETH_8_POOLS;
2227                 dev_info->vmdq_queue_num = 8;
2228                 break;
2229
2230         case e1000_i354:
2231                 dev_info->max_rx_queues = 8;
2232                 dev_info->max_tx_queues = 8;
2233                 break;
2234
2235         case e1000_i210:
2236                 dev_info->max_rx_queues = 4;
2237                 dev_info->max_tx_queues = 4;
2238                 dev_info->max_vmdq_pools = 0;
2239                 break;
2240
2241         case e1000_i211:
2242                 dev_info->max_rx_queues = 2;
2243                 dev_info->max_tx_queues = 2;
2244                 dev_info->max_vmdq_pools = 0;
2245                 break;
2246
2247         default:
2248                 /* Should not happen */
2249                 break;
2250         }
2251         dev_info->hash_key_size = IGB_HKEY_MAX_INDEX * sizeof(uint32_t);
2252         dev_info->reta_size = ETH_RSS_RETA_SIZE_128;
2253         dev_info->flow_type_rss_offloads = IGB_RSS_OFFLOAD_ALL;
2254
2255         dev_info->default_rxconf = (struct rte_eth_rxconf) {
2256                 .rx_thresh = {
2257                         .pthresh = IGB_DEFAULT_RX_PTHRESH,
2258                         .hthresh = IGB_DEFAULT_RX_HTHRESH,
2259                         .wthresh = IGB_DEFAULT_RX_WTHRESH,
2260                 },
2261                 .rx_free_thresh = IGB_DEFAULT_RX_FREE_THRESH,
2262                 .rx_drop_en = 0,
2263         };
2264
2265         dev_info->default_txconf = (struct rte_eth_txconf) {
2266                 .tx_thresh = {
2267                         .pthresh = IGB_DEFAULT_TX_PTHRESH,
2268                         .hthresh = IGB_DEFAULT_TX_HTHRESH,
2269                         .wthresh = IGB_DEFAULT_TX_WTHRESH,
2270                 },
2271                 .txq_flags = 0,
2272         };
2273
2274         dev_info->rx_desc_lim = rx_desc_lim;
2275         dev_info->tx_desc_lim = tx_desc_lim;
2276
2277         dev_info->speed_capa = ETH_LINK_SPEED_10M_HD | ETH_LINK_SPEED_10M |
2278                         ETH_LINK_SPEED_100M_HD | ETH_LINK_SPEED_100M |
2279                         ETH_LINK_SPEED_1G;
2280 }
2281
2282 static const uint32_t *
2283 eth_igb_supported_ptypes_get(struct rte_eth_dev *dev)
2284 {
2285         static const uint32_t ptypes[] = {
2286                 /* refers to igb_rxd_pkt_info_to_pkt_type() */
2287                 RTE_PTYPE_L2_ETHER,
2288                 RTE_PTYPE_L3_IPV4,
2289                 RTE_PTYPE_L3_IPV4_EXT,
2290                 RTE_PTYPE_L3_IPV6,
2291                 RTE_PTYPE_L3_IPV6_EXT,
2292                 RTE_PTYPE_L4_TCP,
2293                 RTE_PTYPE_L4_UDP,
2294                 RTE_PTYPE_L4_SCTP,
2295                 RTE_PTYPE_TUNNEL_IP,
2296                 RTE_PTYPE_INNER_L3_IPV6,
2297                 RTE_PTYPE_INNER_L3_IPV6_EXT,
2298                 RTE_PTYPE_INNER_L4_TCP,
2299                 RTE_PTYPE_INNER_L4_UDP,
2300                 RTE_PTYPE_UNKNOWN
2301         };
2302
2303         if (dev->rx_pkt_burst == eth_igb_recv_pkts ||
2304             dev->rx_pkt_burst == eth_igb_recv_scattered_pkts)
2305                 return ptypes;
2306         return NULL;
2307 }
2308
2309 static void
2310 eth_igbvf_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
2311 {
2312         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2313
2314         dev_info->pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2315         dev_info->min_rx_bufsize = 256; /* See BSIZE field of RCTL register. */
2316         dev_info->max_rx_pktlen  = 0x3FFF; /* See RLPML register. */
2317         dev_info->max_mac_addrs = hw->mac.rar_entry_count;
2318         dev_info->rx_offload_capa = DEV_RX_OFFLOAD_VLAN_STRIP |
2319                                 DEV_RX_OFFLOAD_IPV4_CKSUM |
2320                                 DEV_RX_OFFLOAD_UDP_CKSUM  |
2321                                 DEV_RX_OFFLOAD_TCP_CKSUM;
2322         dev_info->tx_offload_capa = DEV_TX_OFFLOAD_VLAN_INSERT |
2323                                 DEV_TX_OFFLOAD_IPV4_CKSUM  |
2324                                 DEV_TX_OFFLOAD_UDP_CKSUM   |
2325                                 DEV_TX_OFFLOAD_TCP_CKSUM   |
2326                                 DEV_TX_OFFLOAD_SCTP_CKSUM  |
2327                                 DEV_TX_OFFLOAD_TCP_TSO;
2328         switch (hw->mac.type) {
2329         case e1000_vfadapt:
2330                 dev_info->max_rx_queues = 2;
2331                 dev_info->max_tx_queues = 2;
2332                 break;
2333         case e1000_vfadapt_i350:
2334                 dev_info->max_rx_queues = 1;
2335                 dev_info->max_tx_queues = 1;
2336                 break;
2337         default:
2338                 /* Should not happen */
2339                 break;
2340         }
2341
2342         dev_info->default_rxconf = (struct rte_eth_rxconf) {
2343                 .rx_thresh = {
2344                         .pthresh = IGB_DEFAULT_RX_PTHRESH,
2345                         .hthresh = IGB_DEFAULT_RX_HTHRESH,
2346                         .wthresh = IGB_DEFAULT_RX_WTHRESH,
2347                 },
2348                 .rx_free_thresh = IGB_DEFAULT_RX_FREE_THRESH,
2349                 .rx_drop_en = 0,
2350         };
2351
2352         dev_info->default_txconf = (struct rte_eth_txconf) {
2353                 .tx_thresh = {
2354                         .pthresh = IGB_DEFAULT_TX_PTHRESH,
2355                         .hthresh = IGB_DEFAULT_TX_HTHRESH,
2356                         .wthresh = IGB_DEFAULT_TX_WTHRESH,
2357                 },
2358                 .txq_flags = 0,
2359         };
2360
2361         dev_info->rx_desc_lim = rx_desc_lim;
2362         dev_info->tx_desc_lim = tx_desc_lim;
2363 }
2364
2365 /* return 0 means link status changed, -1 means not changed */
2366 static int
2367 eth_igb_link_update(struct rte_eth_dev *dev, int wait_to_complete)
2368 {
2369         struct e1000_hw *hw =
2370                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2371         struct rte_eth_link link, old;
2372         int link_check, count;
2373
2374         link_check = 0;
2375         hw->mac.get_link_status = 1;
2376
2377         /* possible wait-to-complete in up to 9 seconds */
2378         for (count = 0; count < IGB_LINK_UPDATE_CHECK_TIMEOUT; count ++) {
2379                 /* Read the real link status */
2380                 switch (hw->phy.media_type) {
2381                 case e1000_media_type_copper:
2382                         /* Do the work to read phy */
2383                         e1000_check_for_link(hw);
2384                         link_check = !hw->mac.get_link_status;
2385                         break;
2386
2387                 case e1000_media_type_fiber:
2388                         e1000_check_for_link(hw);
2389                         link_check = (E1000_READ_REG(hw, E1000_STATUS) &
2390                                       E1000_STATUS_LU);
2391                         break;
2392
2393                 case e1000_media_type_internal_serdes:
2394                         e1000_check_for_link(hw);
2395                         link_check = hw->mac.serdes_has_link;
2396                         break;
2397
2398                 /* VF device is type_unknown */
2399                 case e1000_media_type_unknown:
2400                         eth_igbvf_link_update(hw);
2401                         link_check = !hw->mac.get_link_status;
2402                         break;
2403
2404                 default:
2405                         break;
2406                 }
2407                 if (link_check || wait_to_complete == 0)
2408                         break;
2409                 rte_delay_ms(IGB_LINK_UPDATE_CHECK_INTERVAL);
2410         }
2411         memset(&link, 0, sizeof(link));
2412         rte_igb_dev_atomic_read_link_status(dev, &link);
2413         old = link;
2414
2415         /* Now we check if a transition has happened */
2416         if (link_check) {
2417                 uint16_t duplex, speed;
2418                 hw->mac.ops.get_link_up_info(hw, &speed, &duplex);
2419                 link.link_duplex = (duplex == FULL_DUPLEX) ?
2420                                 ETH_LINK_FULL_DUPLEX :
2421                                 ETH_LINK_HALF_DUPLEX;
2422                 link.link_speed = speed;
2423                 link.link_status = ETH_LINK_UP;
2424                 link.link_autoneg = !(dev->data->dev_conf.link_speeds &
2425                                 ETH_LINK_SPEED_FIXED);
2426         } else if (!link_check) {
2427                 link.link_speed = 0;
2428                 link.link_duplex = ETH_LINK_HALF_DUPLEX;
2429                 link.link_status = ETH_LINK_DOWN;
2430                 link.link_autoneg = ETH_LINK_SPEED_FIXED;
2431         }
2432         rte_igb_dev_atomic_write_link_status(dev, &link);
2433
2434         /* not changed */
2435         if (old.link_status == link.link_status)
2436                 return -1;
2437
2438         /* changed */
2439         return 0;
2440 }
2441
2442 /*
2443  * igb_hw_control_acquire sets CTRL_EXT:DRV_LOAD bit.
2444  * For ASF and Pass Through versions of f/w this means
2445  * that the driver is loaded.
2446  */
2447 static void
2448 igb_hw_control_acquire(struct e1000_hw *hw)
2449 {
2450         uint32_t ctrl_ext;
2451
2452         /* Let firmware know the driver has taken over */
2453         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
2454         E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
2455 }
2456
2457 /*
2458  * igb_hw_control_release resets CTRL_EXT:DRV_LOAD bit.
2459  * For ASF and Pass Through versions of f/w this means that the
2460  * driver is no longer loaded.
2461  */
2462 static void
2463 igb_hw_control_release(struct e1000_hw *hw)
2464 {
2465         uint32_t ctrl_ext;
2466
2467         /* Let firmware taken over control of h/w */
2468         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
2469         E1000_WRITE_REG(hw, E1000_CTRL_EXT,
2470                         ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
2471 }
2472
2473 /*
2474  * Bit of a misnomer, what this really means is
2475  * to enable OS management of the system... aka
2476  * to disable special hardware management features.
2477  */
2478 static void
2479 igb_init_manageability(struct e1000_hw *hw)
2480 {
2481         if (e1000_enable_mng_pass_thru(hw)) {
2482                 uint32_t manc2h = E1000_READ_REG(hw, E1000_MANC2H);
2483                 uint32_t manc = E1000_READ_REG(hw, E1000_MANC);
2484
2485                 /* disable hardware interception of ARP */
2486                 manc &= ~(E1000_MANC_ARP_EN);
2487
2488                 /* enable receiving management packets to the host */
2489                 manc |= E1000_MANC_EN_MNG2HOST;
2490                 manc2h |= 1 << 5;  /* Mng Port 623 */
2491                 manc2h |= 1 << 6;  /* Mng Port 664 */
2492                 E1000_WRITE_REG(hw, E1000_MANC2H, manc2h);
2493                 E1000_WRITE_REG(hw, E1000_MANC, manc);
2494         }
2495 }
2496
2497 static void
2498 igb_release_manageability(struct e1000_hw *hw)
2499 {
2500         if (e1000_enable_mng_pass_thru(hw)) {
2501                 uint32_t manc = E1000_READ_REG(hw, E1000_MANC);
2502
2503                 manc |= E1000_MANC_ARP_EN;
2504                 manc &= ~E1000_MANC_EN_MNG2HOST;
2505
2506                 E1000_WRITE_REG(hw, E1000_MANC, manc);
2507         }
2508 }
2509
2510 static void
2511 eth_igb_promiscuous_enable(struct rte_eth_dev *dev)
2512 {
2513         struct e1000_hw *hw =
2514                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2515         uint32_t rctl;
2516
2517         rctl = E1000_READ_REG(hw, E1000_RCTL);
2518         rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
2519         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2520 }
2521
2522 static void
2523 eth_igb_promiscuous_disable(struct rte_eth_dev *dev)
2524 {
2525         struct e1000_hw *hw =
2526                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2527         uint32_t rctl;
2528
2529         rctl = E1000_READ_REG(hw, E1000_RCTL);
2530         rctl &= (~E1000_RCTL_UPE);
2531         if (dev->data->all_multicast == 1)
2532                 rctl |= E1000_RCTL_MPE;
2533         else
2534                 rctl &= (~E1000_RCTL_MPE);
2535         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2536 }
2537
2538 static void
2539 eth_igb_allmulticast_enable(struct rte_eth_dev *dev)
2540 {
2541         struct e1000_hw *hw =
2542                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2543         uint32_t rctl;
2544
2545         rctl = E1000_READ_REG(hw, E1000_RCTL);
2546         rctl |= E1000_RCTL_MPE;
2547         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2548 }
2549
2550 static void
2551 eth_igb_allmulticast_disable(struct rte_eth_dev *dev)
2552 {
2553         struct e1000_hw *hw =
2554                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2555         uint32_t rctl;
2556
2557         if (dev->data->promiscuous == 1)
2558                 return; /* must remain in all_multicast mode */
2559         rctl = E1000_READ_REG(hw, E1000_RCTL);
2560         rctl &= (~E1000_RCTL_MPE);
2561         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2562 }
2563
2564 static int
2565 eth_igb_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
2566 {
2567         struct e1000_hw *hw =
2568                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2569         struct e1000_vfta * shadow_vfta =
2570                 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
2571         uint32_t vfta;
2572         uint32_t vid_idx;
2573         uint32_t vid_bit;
2574
2575         vid_idx = (uint32_t) ((vlan_id >> E1000_VFTA_ENTRY_SHIFT) &
2576                               E1000_VFTA_ENTRY_MASK);
2577         vid_bit = (uint32_t) (1 << (vlan_id & E1000_VFTA_ENTRY_BIT_SHIFT_MASK));
2578         vfta = E1000_READ_REG_ARRAY(hw, E1000_VFTA, vid_idx);
2579         if (on)
2580                 vfta |= vid_bit;
2581         else
2582                 vfta &= ~vid_bit;
2583         E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, vid_idx, vfta);
2584
2585         /* update local VFTA copy */
2586         shadow_vfta->vfta[vid_idx] = vfta;
2587
2588         return 0;
2589 }
2590
2591 static int
2592 eth_igb_vlan_tpid_set(struct rte_eth_dev *dev,
2593                       enum rte_vlan_type vlan_type,
2594                       uint16_t tpid)
2595 {
2596         struct e1000_hw *hw =
2597                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2598         uint32_t reg, qinq;
2599
2600         qinq = E1000_READ_REG(hw, E1000_CTRL_EXT);
2601         qinq &= E1000_CTRL_EXT_EXT_VLAN;
2602
2603         /* only outer TPID of double VLAN can be configured*/
2604         if (qinq && vlan_type == ETH_VLAN_TYPE_OUTER) {
2605                 reg = E1000_READ_REG(hw, E1000_VET);
2606                 reg = (reg & (~E1000_VET_VET_EXT)) |
2607                         ((uint32_t)tpid << E1000_VET_VET_EXT_SHIFT);
2608                 E1000_WRITE_REG(hw, E1000_VET, reg);
2609
2610                 return 0;
2611         }
2612
2613         /* all other TPID values are read-only*/
2614         PMD_DRV_LOG(ERR, "Not supported");
2615
2616         return -ENOTSUP;
2617 }
2618
2619 static void
2620 igb_vlan_hw_filter_disable(struct rte_eth_dev *dev)
2621 {
2622         struct e1000_hw *hw =
2623                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2624         uint32_t reg;
2625
2626         /* Filter Table Disable */
2627         reg = E1000_READ_REG(hw, E1000_RCTL);
2628         reg &= ~E1000_RCTL_CFIEN;
2629         reg &= ~E1000_RCTL_VFE;
2630         E1000_WRITE_REG(hw, E1000_RCTL, reg);
2631 }
2632
2633 static void
2634 igb_vlan_hw_filter_enable(struct rte_eth_dev *dev)
2635 {
2636         struct e1000_hw *hw =
2637                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2638         struct e1000_vfta * shadow_vfta =
2639                 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
2640         uint32_t reg;
2641         int i;
2642
2643         /* Filter Table Enable, CFI not used for packet acceptance */
2644         reg = E1000_READ_REG(hw, E1000_RCTL);
2645         reg &= ~E1000_RCTL_CFIEN;
2646         reg |= E1000_RCTL_VFE;
2647         E1000_WRITE_REG(hw, E1000_RCTL, reg);
2648
2649         /* restore VFTA table */
2650         for (i = 0; i < IGB_VFTA_SIZE; i++)
2651                 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, i, shadow_vfta->vfta[i]);
2652 }
2653
2654 static void
2655 igb_vlan_hw_strip_disable(struct rte_eth_dev *dev)
2656 {
2657         struct e1000_hw *hw =
2658                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2659         uint32_t reg;
2660
2661         /* VLAN Mode Disable */
2662         reg = E1000_READ_REG(hw, E1000_CTRL);
2663         reg &= ~E1000_CTRL_VME;
2664         E1000_WRITE_REG(hw, E1000_CTRL, reg);
2665 }
2666
2667 static void
2668 igb_vlan_hw_strip_enable(struct rte_eth_dev *dev)
2669 {
2670         struct e1000_hw *hw =
2671                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2672         uint32_t reg;
2673
2674         /* VLAN Mode Enable */
2675         reg = E1000_READ_REG(hw, E1000_CTRL);
2676         reg |= E1000_CTRL_VME;
2677         E1000_WRITE_REG(hw, E1000_CTRL, reg);
2678 }
2679
2680 static void
2681 igb_vlan_hw_extend_disable(struct rte_eth_dev *dev)
2682 {
2683         struct e1000_hw *hw =
2684                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2685         uint32_t reg;
2686
2687         /* CTRL_EXT: Extended VLAN */
2688         reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
2689         reg &= ~E1000_CTRL_EXT_EXTEND_VLAN;
2690         E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg);
2691
2692         /* Update maximum packet length */
2693         if (dev->data->dev_conf.rxmode.jumbo_frame == 1)
2694                 E1000_WRITE_REG(hw, E1000_RLPML,
2695                         dev->data->dev_conf.rxmode.max_rx_pkt_len +
2696                                                 VLAN_TAG_SIZE);
2697 }
2698
2699 static void
2700 igb_vlan_hw_extend_enable(struct rte_eth_dev *dev)
2701 {
2702         struct e1000_hw *hw =
2703                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2704         uint32_t reg;
2705
2706         /* CTRL_EXT: Extended VLAN */
2707         reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
2708         reg |= E1000_CTRL_EXT_EXTEND_VLAN;
2709         E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg);
2710
2711         /* Update maximum packet length */
2712         if (dev->data->dev_conf.rxmode.jumbo_frame == 1)
2713                 E1000_WRITE_REG(hw, E1000_RLPML,
2714                         dev->data->dev_conf.rxmode.max_rx_pkt_len +
2715                                                 2 * VLAN_TAG_SIZE);
2716 }
2717
2718 static void
2719 eth_igb_vlan_offload_set(struct rte_eth_dev *dev, int mask)
2720 {
2721         if(mask & ETH_VLAN_STRIP_MASK){
2722                 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
2723                         igb_vlan_hw_strip_enable(dev);
2724                 else
2725                         igb_vlan_hw_strip_disable(dev);
2726         }
2727
2728         if(mask & ETH_VLAN_FILTER_MASK){
2729                 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
2730                         igb_vlan_hw_filter_enable(dev);
2731                 else
2732                         igb_vlan_hw_filter_disable(dev);
2733         }
2734
2735         if(mask & ETH_VLAN_EXTEND_MASK){
2736                 if (dev->data->dev_conf.rxmode.hw_vlan_extend)
2737                         igb_vlan_hw_extend_enable(dev);
2738                 else
2739                         igb_vlan_hw_extend_disable(dev);
2740         }
2741 }
2742
2743
2744 /**
2745  * It enables the interrupt mask and then enable the interrupt.
2746  *
2747  * @param dev
2748  *  Pointer to struct rte_eth_dev.
2749  * @param on
2750  *  Enable or Disable
2751  *
2752  * @return
2753  *  - On success, zero.
2754  *  - On failure, a negative value.
2755  */
2756 static int
2757 eth_igb_lsc_interrupt_setup(struct rte_eth_dev *dev, uint8_t on)
2758 {
2759         struct e1000_interrupt *intr =
2760                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2761
2762         if (on)
2763                 intr->mask |= E1000_ICR_LSC;
2764         else
2765                 intr->mask &= ~E1000_ICR_LSC;
2766
2767         return 0;
2768 }
2769
2770 /* It clears the interrupt causes and enables the interrupt.
2771  * It will be called once only during nic initialized.
2772  *
2773  * @param dev
2774  *  Pointer to struct rte_eth_dev.
2775  *
2776  * @return
2777  *  - On success, zero.
2778  *  - On failure, a negative value.
2779  */
2780 static int eth_igb_rxq_interrupt_setup(struct rte_eth_dev *dev)
2781 {
2782         uint32_t mask, regval;
2783         struct e1000_hw *hw =
2784                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2785         struct rte_eth_dev_info dev_info;
2786
2787         memset(&dev_info, 0, sizeof(dev_info));
2788         eth_igb_infos_get(dev, &dev_info);
2789
2790         mask = 0xFFFFFFFF >> (32 - dev_info.max_rx_queues);
2791         regval = E1000_READ_REG(hw, E1000_EIMS);
2792         E1000_WRITE_REG(hw, E1000_EIMS, regval | mask);
2793
2794         return 0;
2795 }
2796
2797 /*
2798  * It reads ICR and gets interrupt causes, check it and set a bit flag
2799  * to update link status.
2800  *
2801  * @param dev
2802  *  Pointer to struct rte_eth_dev.
2803  *
2804  * @return
2805  *  - On success, zero.
2806  *  - On failure, a negative value.
2807  */
2808 static int
2809 eth_igb_interrupt_get_status(struct rte_eth_dev *dev)
2810 {
2811         uint32_t icr;
2812         struct e1000_hw *hw =
2813                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2814         struct e1000_interrupt *intr =
2815                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2816
2817         igb_intr_disable(hw);
2818
2819         /* read-on-clear nic registers here */
2820         icr = E1000_READ_REG(hw, E1000_ICR);
2821
2822         intr->flags = 0;
2823         if (icr & E1000_ICR_LSC) {
2824                 intr->flags |= E1000_FLAG_NEED_LINK_UPDATE;
2825         }
2826
2827         if (icr & E1000_ICR_VMMB)
2828                 intr->flags |= E1000_FLAG_MAILBOX;
2829
2830         return 0;
2831 }
2832
2833 /*
2834  * It executes link_update after knowing an interrupt is prsent.
2835  *
2836  * @param dev
2837  *  Pointer to struct rte_eth_dev.
2838  *
2839  * @return
2840  *  - On success, zero.
2841  *  - On failure, a negative value.
2842  */
2843 static int
2844 eth_igb_interrupt_action(struct rte_eth_dev *dev,
2845                          struct rte_intr_handle *intr_handle)
2846 {
2847         struct e1000_hw *hw =
2848                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2849         struct e1000_interrupt *intr =
2850                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2851         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2852         uint32_t tctl, rctl;
2853         struct rte_eth_link link;
2854         int ret;
2855
2856         if (intr->flags & E1000_FLAG_MAILBOX) {
2857                 igb_pf_mbx_process(dev);
2858                 intr->flags &= ~E1000_FLAG_MAILBOX;
2859         }
2860
2861         igb_intr_enable(dev);
2862         rte_intr_enable(intr_handle);
2863
2864         if (intr->flags & E1000_FLAG_NEED_LINK_UPDATE) {
2865                 intr->flags &= ~E1000_FLAG_NEED_LINK_UPDATE;
2866
2867                 /* set get_link_status to check register later */
2868                 hw->mac.get_link_status = 1;
2869                 ret = eth_igb_link_update(dev, 0);
2870
2871                 /* check if link has changed */
2872                 if (ret < 0)
2873                         return 0;
2874
2875                 memset(&link, 0, sizeof(link));
2876                 rte_igb_dev_atomic_read_link_status(dev, &link);
2877                 if (link.link_status) {
2878                         PMD_INIT_LOG(INFO,
2879                                      " Port %d: Link Up - speed %u Mbps - %s",
2880                                      dev->data->port_id,
2881                                      (unsigned)link.link_speed,
2882                                      link.link_duplex == ETH_LINK_FULL_DUPLEX ?
2883                                      "full-duplex" : "half-duplex");
2884                 } else {
2885                         PMD_INIT_LOG(INFO, " Port %d: Link Down",
2886                                      dev->data->port_id);
2887                 }
2888
2889                 PMD_INIT_LOG(DEBUG, "PCI Address: %04d:%02d:%02d:%d",
2890                              pci_dev->addr.domain,
2891                              pci_dev->addr.bus,
2892                              pci_dev->addr.devid,
2893                              pci_dev->addr.function);
2894                 tctl = E1000_READ_REG(hw, E1000_TCTL);
2895                 rctl = E1000_READ_REG(hw, E1000_RCTL);
2896                 if (link.link_status) {
2897                         /* enable Tx/Rx */
2898                         tctl |= E1000_TCTL_EN;
2899                         rctl |= E1000_RCTL_EN;
2900                 } else {
2901                         /* disable Tx/Rx */
2902                         tctl &= ~E1000_TCTL_EN;
2903                         rctl &= ~E1000_RCTL_EN;
2904                 }
2905                 E1000_WRITE_REG(hw, E1000_TCTL, tctl);
2906                 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2907                 E1000_WRITE_FLUSH(hw);
2908                 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC,
2909                                               NULL, NULL);
2910         }
2911
2912         return 0;
2913 }
2914
2915 /**
2916  * Interrupt handler which shall be registered at first.
2917  *
2918  * @param handle
2919  *  Pointer to interrupt handle.
2920  * @param param
2921  *  The address of parameter (struct rte_eth_dev *) regsitered before.
2922  *
2923  * @return
2924  *  void
2925  */
2926 static void
2927 eth_igb_interrupt_handler(void *param)
2928 {
2929         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
2930
2931         eth_igb_interrupt_get_status(dev);
2932         eth_igb_interrupt_action(dev, dev->intr_handle);
2933 }
2934
2935 static int
2936 eth_igbvf_interrupt_get_status(struct rte_eth_dev *dev)
2937 {
2938         uint32_t eicr;
2939         struct e1000_hw *hw =
2940                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2941         struct e1000_interrupt *intr =
2942                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2943
2944         igbvf_intr_disable(hw);
2945
2946         /* read-on-clear nic registers here */
2947         eicr = E1000_READ_REG(hw, E1000_EICR);
2948         intr->flags = 0;
2949
2950         if (eicr == E1000_VTIVAR_MISC_MAILBOX)
2951                 intr->flags |= E1000_FLAG_MAILBOX;
2952
2953         return 0;
2954 }
2955
2956 void igbvf_mbx_process(struct rte_eth_dev *dev)
2957 {
2958         struct e1000_hw *hw =
2959                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2960         struct e1000_mbx_info *mbx = &hw->mbx;
2961         u32 in_msg = 0;
2962
2963         if (mbx->ops.read(hw, &in_msg, 1, 0))
2964                 return;
2965
2966         /* PF reset VF event */
2967         if (in_msg == E1000_PF_CONTROL_MSG)
2968                 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_RESET,
2969                                               NULL, NULL);
2970 }
2971
2972 static int
2973 eth_igbvf_interrupt_action(struct rte_eth_dev *dev, struct rte_intr_handle *intr_handle)
2974 {
2975         struct e1000_interrupt *intr =
2976                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2977
2978         if (intr->flags & E1000_FLAG_MAILBOX) {
2979                 igbvf_mbx_process(dev);
2980                 intr->flags &= ~E1000_FLAG_MAILBOX;
2981         }
2982
2983         igbvf_intr_enable(dev);
2984         rte_intr_enable(intr_handle);
2985
2986         return 0;
2987 }
2988
2989 static void
2990 eth_igbvf_interrupt_handler(void *param)
2991 {
2992         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
2993
2994         eth_igbvf_interrupt_get_status(dev);
2995         eth_igbvf_interrupt_action(dev, dev->intr_handle);
2996 }
2997
2998 static int
2999 eth_igb_led_on(struct rte_eth_dev *dev)
3000 {
3001         struct e1000_hw *hw;
3002
3003         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3004         return e1000_led_on(hw) == E1000_SUCCESS ? 0 : -ENOTSUP;
3005 }
3006
3007 static int
3008 eth_igb_led_off(struct rte_eth_dev *dev)
3009 {
3010         struct e1000_hw *hw;
3011
3012         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3013         return e1000_led_off(hw) == E1000_SUCCESS ? 0 : -ENOTSUP;
3014 }
3015
3016 static int
3017 eth_igb_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3018 {
3019         struct e1000_hw *hw;
3020         uint32_t ctrl;
3021         int tx_pause;
3022         int rx_pause;
3023
3024         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3025         fc_conf->pause_time = hw->fc.pause_time;
3026         fc_conf->high_water = hw->fc.high_water;
3027         fc_conf->low_water = hw->fc.low_water;
3028         fc_conf->send_xon = hw->fc.send_xon;
3029         fc_conf->autoneg = hw->mac.autoneg;
3030
3031         /*
3032          * Return rx_pause and tx_pause status according to actual setting of
3033          * the TFCE and RFCE bits in the CTRL register.
3034          */
3035         ctrl = E1000_READ_REG(hw, E1000_CTRL);
3036         if (ctrl & E1000_CTRL_TFCE)
3037                 tx_pause = 1;
3038         else
3039                 tx_pause = 0;
3040
3041         if (ctrl & E1000_CTRL_RFCE)
3042                 rx_pause = 1;
3043         else
3044                 rx_pause = 0;
3045
3046         if (rx_pause && tx_pause)
3047                 fc_conf->mode = RTE_FC_FULL;
3048         else if (rx_pause)
3049                 fc_conf->mode = RTE_FC_RX_PAUSE;
3050         else if (tx_pause)
3051                 fc_conf->mode = RTE_FC_TX_PAUSE;
3052         else
3053                 fc_conf->mode = RTE_FC_NONE;
3054
3055         return 0;
3056 }
3057
3058 static int
3059 eth_igb_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3060 {
3061         struct e1000_hw *hw;
3062         int err;
3063         enum e1000_fc_mode rte_fcmode_2_e1000_fcmode[] = {
3064                 e1000_fc_none,
3065                 e1000_fc_rx_pause,
3066                 e1000_fc_tx_pause,
3067                 e1000_fc_full
3068         };
3069         uint32_t rx_buf_size;
3070         uint32_t max_high_water;
3071         uint32_t rctl;
3072
3073         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3074         if (fc_conf->autoneg != hw->mac.autoneg)
3075                 return -ENOTSUP;
3076         rx_buf_size = igb_get_rx_buffer_size(hw);
3077         PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
3078
3079         /* At least reserve one Ethernet frame for watermark */
3080         max_high_water = rx_buf_size - ETHER_MAX_LEN;
3081         if ((fc_conf->high_water > max_high_water) ||
3082             (fc_conf->high_water < fc_conf->low_water)) {
3083                 PMD_INIT_LOG(ERR, "e1000 incorrect high/low water value");
3084                 PMD_INIT_LOG(ERR, "high water must <=  0x%x", max_high_water);
3085                 return -EINVAL;
3086         }
3087
3088         hw->fc.requested_mode = rte_fcmode_2_e1000_fcmode[fc_conf->mode];
3089         hw->fc.pause_time     = fc_conf->pause_time;
3090         hw->fc.high_water     = fc_conf->high_water;
3091         hw->fc.low_water      = fc_conf->low_water;
3092         hw->fc.send_xon       = fc_conf->send_xon;
3093
3094         err = e1000_setup_link_generic(hw);
3095         if (err == E1000_SUCCESS) {
3096
3097                 /* check if we want to forward MAC frames - driver doesn't have native
3098                  * capability to do that, so we'll write the registers ourselves */
3099
3100                 rctl = E1000_READ_REG(hw, E1000_RCTL);
3101
3102                 /* set or clear MFLCN.PMCF bit depending on configuration */
3103                 if (fc_conf->mac_ctrl_frame_fwd != 0)
3104                         rctl |= E1000_RCTL_PMCF;
3105                 else
3106                         rctl &= ~E1000_RCTL_PMCF;
3107
3108                 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
3109                 E1000_WRITE_FLUSH(hw);
3110
3111                 return 0;
3112         }
3113
3114         PMD_INIT_LOG(ERR, "e1000_setup_link_generic = 0x%x", err);
3115         return -EIO;
3116 }
3117
3118 #define E1000_RAH_POOLSEL_SHIFT      (18)
3119 static int
3120 eth_igb_rar_set(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
3121                 uint32_t index, uint32_t pool)
3122 {
3123         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3124         uint32_t rah;
3125
3126         e1000_rar_set(hw, mac_addr->addr_bytes, index);
3127         rah = E1000_READ_REG(hw, E1000_RAH(index));
3128         rah |= (0x1 << (E1000_RAH_POOLSEL_SHIFT + pool));
3129         E1000_WRITE_REG(hw, E1000_RAH(index), rah);
3130         return 0;
3131 }
3132
3133 static void
3134 eth_igb_rar_clear(struct rte_eth_dev *dev, uint32_t index)
3135 {
3136         uint8_t addr[ETHER_ADDR_LEN];
3137         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3138
3139         memset(addr, 0, sizeof(addr));
3140
3141         e1000_rar_set(hw, addr, index);
3142 }
3143
3144 static void
3145 eth_igb_default_mac_addr_set(struct rte_eth_dev *dev,
3146                                 struct ether_addr *addr)
3147 {
3148         eth_igb_rar_clear(dev, 0);
3149
3150         eth_igb_rar_set(dev, (void *)addr, 0, 0);
3151 }
3152 /*
3153  * Virtual Function operations
3154  */
3155 static void
3156 igbvf_intr_disable(struct e1000_hw *hw)
3157 {
3158         PMD_INIT_FUNC_TRACE();
3159
3160         /* Clear interrupt mask to stop from interrupts being generated */
3161         E1000_WRITE_REG(hw, E1000_EIMC, 0xFFFF);
3162
3163         E1000_WRITE_FLUSH(hw);
3164 }
3165
3166 static void
3167 igbvf_stop_adapter(struct rte_eth_dev *dev)
3168 {
3169         u32 reg_val;
3170         u16 i;
3171         struct rte_eth_dev_info dev_info;
3172         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3173
3174         memset(&dev_info, 0, sizeof(dev_info));
3175         eth_igbvf_infos_get(dev, &dev_info);
3176
3177         /* Clear interrupt mask to stop from interrupts being generated */
3178         igbvf_intr_disable(hw);
3179
3180         /* Clear any pending interrupts, flush previous writes */
3181         E1000_READ_REG(hw, E1000_EICR);
3182
3183         /* Disable the transmit unit.  Each queue must be disabled. */
3184         for (i = 0; i < dev_info.max_tx_queues; i++)
3185                 E1000_WRITE_REG(hw, E1000_TXDCTL(i), E1000_TXDCTL_SWFLSH);
3186
3187         /* Disable the receive unit by stopping each queue */
3188         for (i = 0; i < dev_info.max_rx_queues; i++) {
3189                 reg_val = E1000_READ_REG(hw, E1000_RXDCTL(i));
3190                 reg_val &= ~E1000_RXDCTL_QUEUE_ENABLE;
3191                 E1000_WRITE_REG(hw, E1000_RXDCTL(i), reg_val);
3192                 while (E1000_READ_REG(hw, E1000_RXDCTL(i)) & E1000_RXDCTL_QUEUE_ENABLE)
3193                         ;
3194         }
3195
3196         /* flush all queues disables */
3197         E1000_WRITE_FLUSH(hw);
3198         msec_delay(2);
3199 }
3200
3201 static int eth_igbvf_link_update(struct e1000_hw *hw)
3202 {
3203         struct e1000_mbx_info *mbx = &hw->mbx;
3204         struct e1000_mac_info *mac = &hw->mac;
3205         int ret_val = E1000_SUCCESS;
3206
3207         PMD_INIT_LOG(DEBUG, "e1000_check_for_link_vf");
3208
3209         /*
3210          * We only want to run this if there has been a rst asserted.
3211          * in this case that could mean a link change, device reset,
3212          * or a virtual function reset
3213          */
3214
3215         /* If we were hit with a reset or timeout drop the link */
3216         if (!e1000_check_for_rst(hw, 0) || !mbx->timeout)
3217                 mac->get_link_status = TRUE;
3218
3219         if (!mac->get_link_status)
3220                 goto out;
3221
3222         /* if link status is down no point in checking to see if pf is up */
3223         if (!(E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU))
3224                 goto out;
3225
3226         /* if we passed all the tests above then the link is up and we no
3227          * longer need to check for link */
3228         mac->get_link_status = FALSE;
3229
3230 out:
3231         return ret_val;
3232 }
3233
3234
3235 static int
3236 igbvf_dev_configure(struct rte_eth_dev *dev)
3237 {
3238         struct rte_eth_conf* conf = &dev->data->dev_conf;
3239
3240         PMD_INIT_LOG(DEBUG, "Configured Virtual Function port id: %d",
3241                      dev->data->port_id);
3242
3243         /*
3244          * VF has no ability to enable/disable HW CRC
3245          * Keep the persistent behavior the same as Host PF
3246          */
3247 #ifndef RTE_LIBRTE_E1000_PF_DISABLE_STRIP_CRC
3248         if (!conf->rxmode.hw_strip_crc) {
3249                 PMD_INIT_LOG(NOTICE, "VF can't disable HW CRC Strip");
3250                 conf->rxmode.hw_strip_crc = 1;
3251         }
3252 #else
3253         if (conf->rxmode.hw_strip_crc) {
3254                 PMD_INIT_LOG(NOTICE, "VF can't enable HW CRC Strip");
3255                 conf->rxmode.hw_strip_crc = 0;
3256         }
3257 #endif
3258
3259         return 0;
3260 }
3261
3262 static int
3263 igbvf_dev_start(struct rte_eth_dev *dev)
3264 {
3265         struct e1000_hw *hw =
3266                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3267         struct e1000_adapter *adapter =
3268                 E1000_DEV_PRIVATE(dev->data->dev_private);
3269         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3270         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
3271         int ret;
3272         uint32_t intr_vector = 0;
3273
3274         PMD_INIT_FUNC_TRACE();
3275
3276         hw->mac.ops.reset_hw(hw);
3277         adapter->stopped = 0;
3278
3279         /* Set all vfta */
3280         igbvf_set_vfta_all(dev,1);
3281
3282         eth_igbvf_tx_init(dev);
3283
3284         /* This can fail when allocating mbufs for descriptor rings */
3285         ret = eth_igbvf_rx_init(dev);
3286         if (ret) {
3287                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
3288                 igb_dev_clear_queues(dev);
3289                 return ret;
3290         }
3291
3292         /* check and configure queue intr-vector mapping */
3293         if (dev->data->dev_conf.intr_conf.rxq != 0) {
3294                 intr_vector = dev->data->nb_rx_queues;
3295                 ret = rte_intr_efd_enable(intr_handle, intr_vector);
3296                 if (ret)
3297                         return ret;
3298         }
3299
3300         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
3301                 intr_handle->intr_vec =
3302                         rte_zmalloc("intr_vec",
3303                                     dev->data->nb_rx_queues * sizeof(int), 0);
3304                 if (!intr_handle->intr_vec) {
3305                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
3306                                      " intr_vec", dev->data->nb_rx_queues);
3307                         return -ENOMEM;
3308                 }
3309         }
3310
3311         eth_igbvf_configure_msix_intr(dev);
3312
3313         /* enable uio/vfio intr/eventfd mapping */
3314         rte_intr_enable(intr_handle);
3315
3316         /* resume enabled intr since hw reset */
3317         igbvf_intr_enable(dev);
3318
3319         return 0;
3320 }
3321
3322 static void
3323 igbvf_dev_stop(struct rte_eth_dev *dev)
3324 {
3325         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3326         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
3327
3328         PMD_INIT_FUNC_TRACE();
3329
3330         igbvf_stop_adapter(dev);
3331
3332         /*
3333           * Clear what we set, but we still keep shadow_vfta to
3334           * restore after device starts
3335           */
3336         igbvf_set_vfta_all(dev,0);
3337
3338         igb_dev_clear_queues(dev);
3339
3340         /* disable intr eventfd mapping */
3341         rte_intr_disable(intr_handle);
3342
3343         /* Clean datapath event and queue/vec mapping */
3344         rte_intr_efd_disable(intr_handle);
3345         if (intr_handle->intr_vec) {
3346                 rte_free(intr_handle->intr_vec);
3347                 intr_handle->intr_vec = NULL;
3348         }
3349 }
3350
3351 static void
3352 igbvf_dev_close(struct rte_eth_dev *dev)
3353 {
3354         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3355         struct e1000_adapter *adapter =
3356                 E1000_DEV_PRIVATE(dev->data->dev_private);
3357         struct ether_addr addr;
3358
3359         PMD_INIT_FUNC_TRACE();
3360
3361         e1000_reset_hw(hw);
3362
3363         igbvf_dev_stop(dev);
3364         adapter->stopped = 1;
3365         igb_dev_free_queues(dev);
3366
3367         /**
3368          * reprogram the RAR with a zero mac address,
3369          * to ensure that the VF traffic goes to the PF
3370          * after stop, close and detach of the VF.
3371          **/
3372
3373         memset(&addr, 0, sizeof(addr));
3374         igbvf_default_mac_addr_set(dev, &addr);
3375 }
3376
3377 static void
3378 igbvf_promiscuous_enable(struct rte_eth_dev *dev)
3379 {
3380         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3381
3382         /* Set both unicast and multicast promisc */
3383         e1000_promisc_set_vf(hw, e1000_promisc_enabled);
3384 }
3385
3386 static void
3387 igbvf_promiscuous_disable(struct rte_eth_dev *dev)
3388 {
3389         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3390
3391         /* If in allmulticast mode leave multicast promisc */
3392         if (dev->data->all_multicast == 1)
3393                 e1000_promisc_set_vf(hw, e1000_promisc_multicast);
3394         else
3395                 e1000_promisc_set_vf(hw, e1000_promisc_disabled);
3396 }
3397
3398 static void
3399 igbvf_allmulticast_enable(struct rte_eth_dev *dev)
3400 {
3401         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3402
3403         /* In promiscuous mode multicast promisc already set */
3404         if (dev->data->promiscuous == 0)
3405                 e1000_promisc_set_vf(hw, e1000_promisc_multicast);
3406 }
3407
3408 static void
3409 igbvf_allmulticast_disable(struct rte_eth_dev *dev)
3410 {
3411         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3412
3413         /* In promiscuous mode leave multicast promisc enabled */
3414         if (dev->data->promiscuous == 0)
3415                 e1000_promisc_set_vf(hw, e1000_promisc_disabled);
3416 }
3417
3418 static int igbvf_set_vfta(struct e1000_hw *hw, uint16_t vid, bool on)
3419 {
3420         struct e1000_mbx_info *mbx = &hw->mbx;
3421         uint32_t msgbuf[2];
3422         s32 err;
3423
3424         /* After set vlan, vlan strip will also be enabled in igb driver*/
3425         msgbuf[0] = E1000_VF_SET_VLAN;
3426         msgbuf[1] = vid;
3427         /* Setting the 8 bit field MSG INFO to TRUE indicates "add" */
3428         if (on)
3429                 msgbuf[0] |= E1000_VF_SET_VLAN_ADD;
3430
3431         err = mbx->ops.write_posted(hw, msgbuf, 2, 0);
3432         if (err)
3433                 goto mbx_err;
3434
3435         err = mbx->ops.read_posted(hw, msgbuf, 2, 0);
3436         if (err)
3437                 goto mbx_err;
3438
3439         msgbuf[0] &= ~E1000_VT_MSGTYPE_CTS;
3440         if (msgbuf[0] == (E1000_VF_SET_VLAN | E1000_VT_MSGTYPE_NACK))
3441                 err = -EINVAL;
3442
3443 mbx_err:
3444         return err;
3445 }
3446
3447 static void igbvf_set_vfta_all(struct rte_eth_dev *dev, bool on)
3448 {
3449         struct e1000_hw *hw =
3450                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3451         struct e1000_vfta * shadow_vfta =
3452                 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
3453         int i = 0, j = 0, vfta = 0, mask = 1;
3454
3455         for (i = 0; i < IGB_VFTA_SIZE; i++){
3456                 vfta = shadow_vfta->vfta[i];
3457                 if(vfta){
3458                         mask = 1;
3459                         for (j = 0; j < 32; j++){
3460                                 if(vfta & mask)
3461                                         igbvf_set_vfta(hw,
3462                                                 (uint16_t)((i<<5)+j), on);
3463                                 mask<<=1;
3464                         }
3465                 }
3466         }
3467
3468 }
3469
3470 static int
3471 igbvf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
3472 {
3473         struct e1000_hw *hw =
3474                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3475         struct e1000_vfta * shadow_vfta =
3476                 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
3477         uint32_t vid_idx = 0;
3478         uint32_t vid_bit = 0;
3479         int ret = 0;
3480
3481         PMD_INIT_FUNC_TRACE();
3482
3483         /*vind is not used in VF driver, set to 0, check ixgbe_set_vfta_vf*/
3484         ret = igbvf_set_vfta(hw, vlan_id, !!on);
3485         if(ret){
3486                 PMD_INIT_LOG(ERR, "Unable to set VF vlan");
3487                 return ret;
3488         }
3489         vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
3490         vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
3491
3492         /*Save what we set and retore it after device reset*/
3493         if (on)
3494                 shadow_vfta->vfta[vid_idx] |= vid_bit;
3495         else
3496                 shadow_vfta->vfta[vid_idx] &= ~vid_bit;
3497
3498         return 0;
3499 }
3500
3501 static void
3502 igbvf_default_mac_addr_set(struct rte_eth_dev *dev, struct ether_addr *addr)
3503 {
3504         struct e1000_hw *hw =
3505                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3506
3507         /* index is not used by rar_set() */
3508         hw->mac.ops.rar_set(hw, (void *)addr, 0);
3509 }
3510
3511
3512 static int
3513 eth_igb_rss_reta_update(struct rte_eth_dev *dev,
3514                         struct rte_eth_rss_reta_entry64 *reta_conf,
3515                         uint16_t reta_size)
3516 {
3517         uint8_t i, j, mask;
3518         uint32_t reta, r;
3519         uint16_t idx, shift;
3520         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3521
3522         if (reta_size != ETH_RSS_RETA_SIZE_128) {
3523                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
3524                         "(%d) doesn't match the number hardware can supported "
3525                         "(%d)", reta_size, ETH_RSS_RETA_SIZE_128);
3526                 return -EINVAL;
3527         }
3528
3529         for (i = 0; i < reta_size; i += IGB_4_BIT_WIDTH) {
3530                 idx = i / RTE_RETA_GROUP_SIZE;
3531                 shift = i % RTE_RETA_GROUP_SIZE;
3532                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
3533                                                 IGB_4_BIT_MASK);
3534                 if (!mask)
3535                         continue;
3536                 if (mask == IGB_4_BIT_MASK)
3537                         r = 0;
3538                 else
3539                         r = E1000_READ_REG(hw, E1000_RETA(i >> 2));
3540                 for (j = 0, reta = 0; j < IGB_4_BIT_WIDTH; j++) {
3541                         if (mask & (0x1 << j))
3542                                 reta |= reta_conf[idx].reta[shift + j] <<
3543                                                         (CHAR_BIT * j);
3544                         else
3545                                 reta |= r & (IGB_8_BIT_MASK << (CHAR_BIT * j));
3546                 }
3547                 E1000_WRITE_REG(hw, E1000_RETA(i >> 2), reta);
3548         }
3549
3550         return 0;
3551 }
3552
3553 static int
3554 eth_igb_rss_reta_query(struct rte_eth_dev *dev,
3555                        struct rte_eth_rss_reta_entry64 *reta_conf,
3556                        uint16_t reta_size)
3557 {
3558         uint8_t i, j, mask;
3559         uint32_t reta;
3560         uint16_t idx, shift;
3561         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3562
3563         if (reta_size != ETH_RSS_RETA_SIZE_128) {
3564                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
3565                         "(%d) doesn't match the number hardware can supported "
3566                         "(%d)", reta_size, ETH_RSS_RETA_SIZE_128);
3567                 return -EINVAL;
3568         }
3569
3570         for (i = 0; i < reta_size; i += IGB_4_BIT_WIDTH) {
3571                 idx = i / RTE_RETA_GROUP_SIZE;
3572                 shift = i % RTE_RETA_GROUP_SIZE;
3573                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
3574                                                 IGB_4_BIT_MASK);
3575                 if (!mask)
3576                         continue;
3577                 reta = E1000_READ_REG(hw, E1000_RETA(i >> 2));
3578                 for (j = 0; j < IGB_4_BIT_WIDTH; j++) {
3579                         if (mask & (0x1 << j))
3580                                 reta_conf[idx].reta[shift + j] =
3581                                         ((reta >> (CHAR_BIT * j)) &
3582                                                 IGB_8_BIT_MASK);
3583                 }
3584         }
3585
3586         return 0;
3587 }
3588
3589 int
3590 eth_igb_syn_filter_set(struct rte_eth_dev *dev,
3591                         struct rte_eth_syn_filter *filter,
3592                         bool add)
3593 {
3594         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3595         struct e1000_filter_info *filter_info =
3596                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3597         uint32_t synqf, rfctl;
3598
3599         if (filter->queue >= IGB_MAX_RX_QUEUE_NUM)
3600                 return -EINVAL;
3601
3602         synqf = E1000_READ_REG(hw, E1000_SYNQF(0));
3603
3604         if (add) {
3605                 if (synqf & E1000_SYN_FILTER_ENABLE)
3606                         return -EINVAL;
3607
3608                 synqf = (uint32_t)(((filter->queue << E1000_SYN_FILTER_QUEUE_SHIFT) &
3609                         E1000_SYN_FILTER_QUEUE) | E1000_SYN_FILTER_ENABLE);
3610
3611                 rfctl = E1000_READ_REG(hw, E1000_RFCTL);
3612                 if (filter->hig_pri)
3613                         rfctl |= E1000_RFCTL_SYNQFP;
3614                 else
3615                         rfctl &= ~E1000_RFCTL_SYNQFP;
3616
3617                 E1000_WRITE_REG(hw, E1000_RFCTL, rfctl);
3618         } else {
3619                 if (!(synqf & E1000_SYN_FILTER_ENABLE))
3620                         return -ENOENT;
3621                 synqf = 0;
3622         }
3623
3624         filter_info->syn_info = synqf;
3625         E1000_WRITE_REG(hw, E1000_SYNQF(0), synqf);
3626         E1000_WRITE_FLUSH(hw);
3627         return 0;
3628 }
3629
3630 static int
3631 eth_igb_syn_filter_get(struct rte_eth_dev *dev,
3632                         struct rte_eth_syn_filter *filter)
3633 {
3634         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3635         uint32_t synqf, rfctl;
3636
3637         synqf = E1000_READ_REG(hw, E1000_SYNQF(0));
3638         if (synqf & E1000_SYN_FILTER_ENABLE) {
3639                 rfctl = E1000_READ_REG(hw, E1000_RFCTL);
3640                 filter->hig_pri = (rfctl & E1000_RFCTL_SYNQFP) ? 1 : 0;
3641                 filter->queue = (uint8_t)((synqf & E1000_SYN_FILTER_QUEUE) >>
3642                                 E1000_SYN_FILTER_QUEUE_SHIFT);
3643                 return 0;
3644         }
3645
3646         return -ENOENT;
3647 }
3648
3649 static int
3650 eth_igb_syn_filter_handle(struct rte_eth_dev *dev,
3651                         enum rte_filter_op filter_op,
3652                         void *arg)
3653 {
3654         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3655         int ret;
3656
3657         MAC_TYPE_FILTER_SUP(hw->mac.type);
3658
3659         if (filter_op == RTE_ETH_FILTER_NOP)
3660                 return 0;
3661
3662         if (arg == NULL) {
3663                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
3664                             filter_op);
3665                 return -EINVAL;
3666         }
3667
3668         switch (filter_op) {
3669         case RTE_ETH_FILTER_ADD:
3670                 ret = eth_igb_syn_filter_set(dev,
3671                                 (struct rte_eth_syn_filter *)arg,
3672                                 TRUE);
3673                 break;
3674         case RTE_ETH_FILTER_DELETE:
3675                 ret = eth_igb_syn_filter_set(dev,
3676                                 (struct rte_eth_syn_filter *)arg,
3677                                 FALSE);
3678                 break;
3679         case RTE_ETH_FILTER_GET:
3680                 ret = eth_igb_syn_filter_get(dev,
3681                                 (struct rte_eth_syn_filter *)arg);
3682                 break;
3683         default:
3684                 PMD_DRV_LOG(ERR, "unsupported operation %u", filter_op);
3685                 ret = -EINVAL;
3686                 break;
3687         }
3688
3689         return ret;
3690 }
3691
3692 /* translate elements in struct rte_eth_ntuple_filter to struct e1000_2tuple_filter_info*/
3693 static inline int
3694 ntuple_filter_to_2tuple(struct rte_eth_ntuple_filter *filter,
3695                         struct e1000_2tuple_filter_info *filter_info)
3696 {
3697         if (filter->queue >= IGB_MAX_RX_QUEUE_NUM)
3698                 return -EINVAL;
3699         if (filter->priority > E1000_2TUPLE_MAX_PRI)
3700                 return -EINVAL;  /* filter index is out of range. */
3701         if (filter->tcp_flags > TCP_FLAG_ALL)
3702                 return -EINVAL;  /* flags is invalid. */
3703
3704         switch (filter->dst_port_mask) {
3705         case UINT16_MAX:
3706                 filter_info->dst_port_mask = 0;
3707                 filter_info->dst_port = filter->dst_port;
3708                 break;
3709         case 0:
3710                 filter_info->dst_port_mask = 1;
3711                 break;
3712         default:
3713                 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
3714                 return -EINVAL;
3715         }
3716
3717         switch (filter->proto_mask) {
3718         case UINT8_MAX:
3719                 filter_info->proto_mask = 0;
3720                 filter_info->proto = filter->proto;
3721                 break;
3722         case 0:
3723                 filter_info->proto_mask = 1;
3724                 break;
3725         default:
3726                 PMD_DRV_LOG(ERR, "invalid protocol mask.");
3727                 return -EINVAL;
3728         }
3729
3730         filter_info->priority = (uint8_t)filter->priority;
3731         if (filter->flags & RTE_NTUPLE_FLAGS_TCP_FLAG)
3732                 filter_info->tcp_flags = filter->tcp_flags;
3733         else
3734                 filter_info->tcp_flags = 0;
3735
3736         return 0;
3737 }
3738
3739 static inline struct e1000_2tuple_filter *
3740 igb_2tuple_filter_lookup(struct e1000_2tuple_filter_list *filter_list,
3741                         struct e1000_2tuple_filter_info *key)
3742 {
3743         struct e1000_2tuple_filter *it;
3744
3745         TAILQ_FOREACH(it, filter_list, entries) {
3746                 if (memcmp(key, &it->filter_info,
3747                         sizeof(struct e1000_2tuple_filter_info)) == 0) {
3748                         return it;
3749                 }
3750         }
3751         return NULL;
3752 }
3753
3754 /* inject a igb 2tuple filter to HW */
3755 static inline void
3756 igb_inject_2uple_filter(struct rte_eth_dev *dev,
3757                            struct e1000_2tuple_filter *filter)
3758 {
3759         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3760         uint32_t ttqf = E1000_TTQF_DISABLE_MASK;
3761         uint32_t imir, imir_ext = E1000_IMIREXT_SIZE_BP;
3762         int i;
3763
3764         i = filter->index;
3765         imir = (uint32_t)(filter->filter_info.dst_port & E1000_IMIR_DSTPORT);
3766         if (filter->filter_info.dst_port_mask == 1) /* 1b means not compare. */
3767                 imir |= E1000_IMIR_PORT_BP;
3768         else
3769                 imir &= ~E1000_IMIR_PORT_BP;
3770
3771         imir |= filter->filter_info.priority << E1000_IMIR_PRIORITY_SHIFT;
3772
3773         ttqf |= E1000_TTQF_QUEUE_ENABLE;
3774         ttqf |= (uint32_t)(filter->queue << E1000_TTQF_QUEUE_SHIFT);
3775         ttqf |= (uint32_t)(filter->filter_info.proto &
3776                                                 E1000_TTQF_PROTOCOL_MASK);
3777         if (filter->filter_info.proto_mask == 0)
3778                 ttqf &= ~E1000_TTQF_MASK_ENABLE;
3779
3780         /* tcp flags bits setting. */
3781         if (filter->filter_info.tcp_flags & TCP_FLAG_ALL) {
3782                 if (filter->filter_info.tcp_flags & TCP_URG_FLAG)
3783                         imir_ext |= E1000_IMIREXT_CTRL_URG;
3784                 if (filter->filter_info.tcp_flags & TCP_ACK_FLAG)
3785                         imir_ext |= E1000_IMIREXT_CTRL_ACK;
3786                 if (filter->filter_info.tcp_flags & TCP_PSH_FLAG)
3787                         imir_ext |= E1000_IMIREXT_CTRL_PSH;
3788                 if (filter->filter_info.tcp_flags & TCP_RST_FLAG)
3789                         imir_ext |= E1000_IMIREXT_CTRL_RST;
3790                 if (filter->filter_info.tcp_flags & TCP_SYN_FLAG)
3791                         imir_ext |= E1000_IMIREXT_CTRL_SYN;
3792                 if (filter->filter_info.tcp_flags & TCP_FIN_FLAG)
3793                         imir_ext |= E1000_IMIREXT_CTRL_FIN;
3794         } else {
3795                 imir_ext |= E1000_IMIREXT_CTRL_BP;
3796         }
3797         E1000_WRITE_REG(hw, E1000_IMIR(i), imir);
3798         E1000_WRITE_REG(hw, E1000_TTQF(i), ttqf);
3799         E1000_WRITE_REG(hw, E1000_IMIREXT(i), imir_ext);
3800 }
3801
3802 /*
3803  * igb_add_2tuple_filter - add a 2tuple filter
3804  *
3805  * @param
3806  * dev: Pointer to struct rte_eth_dev.
3807  * ntuple_filter: ponter to the filter that will be added.
3808  *
3809  * @return
3810  *    - On success, zero.
3811  *    - On failure, a negative value.
3812  */
3813 static int
3814 igb_add_2tuple_filter(struct rte_eth_dev *dev,
3815                         struct rte_eth_ntuple_filter *ntuple_filter)
3816 {
3817         struct e1000_filter_info *filter_info =
3818                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3819         struct e1000_2tuple_filter *filter;
3820         int i, ret;
3821
3822         filter = rte_zmalloc("e1000_2tuple_filter",
3823                         sizeof(struct e1000_2tuple_filter), 0);
3824         if (filter == NULL)
3825                 return -ENOMEM;
3826
3827         ret = ntuple_filter_to_2tuple(ntuple_filter,
3828                                       &filter->filter_info);
3829         if (ret < 0) {
3830                 rte_free(filter);
3831                 return ret;
3832         }
3833         if (igb_2tuple_filter_lookup(&filter_info->twotuple_list,
3834                                          &filter->filter_info) != NULL) {
3835                 PMD_DRV_LOG(ERR, "filter exists.");
3836                 rte_free(filter);
3837                 return -EEXIST;
3838         }
3839         filter->queue = ntuple_filter->queue;
3840
3841         /*
3842          * look for an unused 2tuple filter index,
3843          * and insert the filter to list.
3844          */
3845         for (i = 0; i < E1000_MAX_TTQF_FILTERS; i++) {
3846                 if (!(filter_info->twotuple_mask & (1 << i))) {
3847                         filter_info->twotuple_mask |= 1 << i;
3848                         filter->index = i;
3849                         TAILQ_INSERT_TAIL(&filter_info->twotuple_list,
3850                                           filter,
3851                                           entries);
3852                         break;
3853                 }
3854         }
3855         if (i >= E1000_MAX_TTQF_FILTERS) {
3856                 PMD_DRV_LOG(ERR, "2tuple filters are full.");
3857                 rte_free(filter);
3858                 return -ENOSYS;
3859         }
3860
3861         igb_inject_2uple_filter(dev, filter);
3862         return 0;
3863 }
3864
3865 int
3866 igb_delete_2tuple_filter(struct rte_eth_dev *dev,
3867                         struct e1000_2tuple_filter *filter)
3868 {
3869         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3870         struct e1000_filter_info *filter_info =
3871                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3872
3873         filter_info->twotuple_mask &= ~(1 << filter->index);
3874         TAILQ_REMOVE(&filter_info->twotuple_list, filter, entries);
3875         rte_free(filter);
3876
3877         E1000_WRITE_REG(hw, E1000_TTQF(filter->index), E1000_TTQF_DISABLE_MASK);
3878         E1000_WRITE_REG(hw, E1000_IMIR(filter->index), 0);
3879         E1000_WRITE_REG(hw, E1000_IMIREXT(filter->index), 0);
3880         return 0;
3881 }
3882
3883 /*
3884  * igb_remove_2tuple_filter - remove a 2tuple filter
3885  *
3886  * @param
3887  * dev: Pointer to struct rte_eth_dev.
3888  * ntuple_filter: ponter to the filter that will be removed.
3889  *
3890  * @return
3891  *    - On success, zero.
3892  *    - On failure, a negative value.
3893  */
3894 static int
3895 igb_remove_2tuple_filter(struct rte_eth_dev *dev,
3896                         struct rte_eth_ntuple_filter *ntuple_filter)
3897 {
3898         struct e1000_filter_info *filter_info =
3899                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3900         struct e1000_2tuple_filter_info filter_2tuple;
3901         struct e1000_2tuple_filter *filter;
3902         int ret;
3903
3904         memset(&filter_2tuple, 0, sizeof(struct e1000_2tuple_filter_info));
3905         ret = ntuple_filter_to_2tuple(ntuple_filter,
3906                                       &filter_2tuple);
3907         if (ret < 0)
3908                 return ret;
3909
3910         filter = igb_2tuple_filter_lookup(&filter_info->twotuple_list,
3911                                          &filter_2tuple);
3912         if (filter == NULL) {
3913                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
3914                 return -ENOENT;
3915         }
3916
3917         igb_delete_2tuple_filter(dev, filter);
3918
3919         return 0;
3920 }
3921
3922 /* inject a igb flex filter to HW */
3923 static inline void
3924 igb_inject_flex_filter(struct rte_eth_dev *dev,
3925                            struct e1000_flex_filter *filter)
3926 {
3927         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3928         uint32_t wufc, queueing;
3929         uint32_t reg_off;
3930         uint8_t i, j = 0;
3931
3932         wufc = E1000_READ_REG(hw, E1000_WUFC);
3933         if (filter->index < E1000_MAX_FHFT)
3934                 reg_off = E1000_FHFT(filter->index);
3935         else
3936                 reg_off = E1000_FHFT_EXT(filter->index - E1000_MAX_FHFT);
3937
3938         E1000_WRITE_REG(hw, E1000_WUFC, wufc | E1000_WUFC_FLEX_HQ |
3939                         (E1000_WUFC_FLX0 << filter->index));
3940         queueing = filter->filter_info.len |
3941                 (filter->queue << E1000_FHFT_QUEUEING_QUEUE_SHIFT) |
3942                 (filter->filter_info.priority <<
3943                         E1000_FHFT_QUEUEING_PRIO_SHIFT);
3944         E1000_WRITE_REG(hw, reg_off + E1000_FHFT_QUEUEING_OFFSET,
3945                         queueing);
3946
3947         for (i = 0; i < E1000_FLEX_FILTERS_MASK_SIZE; i++) {
3948                 E1000_WRITE_REG(hw, reg_off,
3949                                 filter->filter_info.dwords[j]);
3950                 reg_off += sizeof(uint32_t);
3951                 E1000_WRITE_REG(hw, reg_off,
3952                                 filter->filter_info.dwords[++j]);
3953                 reg_off += sizeof(uint32_t);
3954                 E1000_WRITE_REG(hw, reg_off,
3955                         (uint32_t)filter->filter_info.mask[i]);
3956                 reg_off += sizeof(uint32_t) * 2;
3957                 ++j;
3958         }
3959 }
3960
3961 static inline struct e1000_flex_filter *
3962 eth_igb_flex_filter_lookup(struct e1000_flex_filter_list *filter_list,
3963                         struct e1000_flex_filter_info *key)
3964 {
3965         struct e1000_flex_filter *it;
3966
3967         TAILQ_FOREACH(it, filter_list, entries) {
3968                 if (memcmp(key, &it->filter_info,
3969                         sizeof(struct e1000_flex_filter_info)) == 0)
3970                         return it;
3971         }
3972
3973         return NULL;
3974 }
3975
3976 /* remove a flex byte filter
3977  * @param
3978  * dev: Pointer to struct rte_eth_dev.
3979  * filter: the pointer of the filter will be removed.
3980  */
3981 void
3982 igb_remove_flex_filter(struct rte_eth_dev *dev,
3983                         struct e1000_flex_filter *filter)
3984 {
3985         struct e1000_filter_info *filter_info =
3986                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3987         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3988         uint32_t wufc, i;
3989         uint32_t reg_off;
3990
3991         wufc = E1000_READ_REG(hw, E1000_WUFC);
3992         if (filter->index < E1000_MAX_FHFT)
3993                 reg_off = E1000_FHFT(filter->index);
3994         else
3995                 reg_off = E1000_FHFT_EXT(filter->index - E1000_MAX_FHFT);
3996
3997         for (i = 0; i < E1000_FHFT_SIZE_IN_DWD; i++)
3998                 E1000_WRITE_REG(hw, reg_off + i * sizeof(uint32_t), 0);
3999
4000         E1000_WRITE_REG(hw, E1000_WUFC, wufc &
4001                 (~(E1000_WUFC_FLX0 << filter->index)));
4002
4003         filter_info->flex_mask &= ~(1 << filter->index);
4004         TAILQ_REMOVE(&filter_info->flex_list, filter, entries);
4005         rte_free(filter);
4006 }
4007
4008 int
4009 eth_igb_add_del_flex_filter(struct rte_eth_dev *dev,
4010                         struct rte_eth_flex_filter *filter,
4011                         bool add)
4012 {
4013         struct e1000_filter_info *filter_info =
4014                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4015         struct e1000_flex_filter *flex_filter, *it;
4016         uint32_t mask;
4017         uint8_t shift, i;
4018
4019         flex_filter = rte_zmalloc("e1000_flex_filter",
4020                         sizeof(struct e1000_flex_filter), 0);
4021         if (flex_filter == NULL)
4022                 return -ENOMEM;
4023
4024         flex_filter->filter_info.len = filter->len;
4025         flex_filter->filter_info.priority = filter->priority;
4026         memcpy(flex_filter->filter_info.dwords, filter->bytes, filter->len);
4027         for (i = 0; i < RTE_ALIGN(filter->len, CHAR_BIT) / CHAR_BIT; i++) {
4028                 mask = 0;
4029                 /* reverse bits in flex filter's mask*/
4030                 for (shift = 0; shift < CHAR_BIT; shift++) {
4031                         if (filter->mask[i] & (0x01 << shift))
4032                                 mask |= (0x80 >> shift);
4033                 }
4034                 flex_filter->filter_info.mask[i] = mask;
4035         }
4036
4037         it = eth_igb_flex_filter_lookup(&filter_info->flex_list,
4038                                 &flex_filter->filter_info);
4039         if (it == NULL && !add) {
4040                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
4041                 rte_free(flex_filter);
4042                 return -ENOENT;
4043         }
4044         if (it != NULL && add) {
4045                 PMD_DRV_LOG(ERR, "filter exists.");
4046                 rte_free(flex_filter);
4047                 return -EEXIST;
4048         }
4049
4050         if (add) {
4051                 flex_filter->queue = filter->queue;
4052                 /*
4053                  * look for an unused flex filter index
4054                  * and insert the filter into the list.
4055                  */
4056                 for (i = 0; i < E1000_MAX_FLEX_FILTERS; i++) {
4057                         if (!(filter_info->flex_mask & (1 << i))) {
4058                                 filter_info->flex_mask |= 1 << i;
4059                                 flex_filter->index = i;
4060                                 TAILQ_INSERT_TAIL(&filter_info->flex_list,
4061                                         flex_filter,
4062                                         entries);
4063                                 break;
4064                         }
4065                 }
4066                 if (i >= E1000_MAX_FLEX_FILTERS) {
4067                         PMD_DRV_LOG(ERR, "flex filters are full.");
4068                         rte_free(flex_filter);
4069                         return -ENOSYS;
4070                 }
4071
4072                 igb_inject_flex_filter(dev, flex_filter);
4073
4074         } else {
4075                 igb_remove_flex_filter(dev, it);
4076                 rte_free(flex_filter);
4077         }
4078
4079         return 0;
4080 }
4081
4082 static int
4083 eth_igb_get_flex_filter(struct rte_eth_dev *dev,
4084                         struct rte_eth_flex_filter *filter)
4085 {
4086         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4087         struct e1000_filter_info *filter_info =
4088                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4089         struct e1000_flex_filter flex_filter, *it;
4090         uint32_t wufc, queueing, wufc_en = 0;
4091
4092         memset(&flex_filter, 0, sizeof(struct e1000_flex_filter));
4093         flex_filter.filter_info.len = filter->len;
4094         flex_filter.filter_info.priority = filter->priority;
4095         memcpy(flex_filter.filter_info.dwords, filter->bytes, filter->len);
4096         memcpy(flex_filter.filter_info.mask, filter->mask,
4097                         RTE_ALIGN(filter->len, sizeof(char)) / sizeof(char));
4098
4099         it = eth_igb_flex_filter_lookup(&filter_info->flex_list,
4100                                 &flex_filter.filter_info);
4101         if (it == NULL) {
4102                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
4103                 return -ENOENT;
4104         }
4105
4106         wufc = E1000_READ_REG(hw, E1000_WUFC);
4107         wufc_en = E1000_WUFC_FLEX_HQ | (E1000_WUFC_FLX0 << it->index);
4108
4109         if ((wufc & wufc_en) == wufc_en) {
4110                 uint32_t reg_off = 0;
4111                 if (it->index < E1000_MAX_FHFT)
4112                         reg_off = E1000_FHFT(it->index);
4113                 else
4114                         reg_off = E1000_FHFT_EXT(it->index - E1000_MAX_FHFT);
4115
4116                 queueing = E1000_READ_REG(hw,
4117                                 reg_off + E1000_FHFT_QUEUEING_OFFSET);
4118                 filter->len = queueing & E1000_FHFT_QUEUEING_LEN;
4119                 filter->priority = (queueing & E1000_FHFT_QUEUEING_PRIO) >>
4120                         E1000_FHFT_QUEUEING_PRIO_SHIFT;
4121                 filter->queue = (queueing & E1000_FHFT_QUEUEING_QUEUE) >>
4122                         E1000_FHFT_QUEUEING_QUEUE_SHIFT;
4123                 return 0;
4124         }
4125         return -ENOENT;
4126 }
4127
4128 static int
4129 eth_igb_flex_filter_handle(struct rte_eth_dev *dev,
4130                         enum rte_filter_op filter_op,
4131                         void *arg)
4132 {
4133         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4134         struct rte_eth_flex_filter *filter;
4135         int ret = 0;
4136
4137         MAC_TYPE_FILTER_SUP_EXT(hw->mac.type);
4138
4139         if (filter_op == RTE_ETH_FILTER_NOP)
4140                 return ret;
4141
4142         if (arg == NULL) {
4143                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
4144                             filter_op);
4145                 return -EINVAL;
4146         }
4147
4148         filter = (struct rte_eth_flex_filter *)arg;
4149         if (filter->len == 0 || filter->len > E1000_MAX_FLEX_FILTER_LEN
4150             || filter->len % sizeof(uint64_t) != 0) {
4151                 PMD_DRV_LOG(ERR, "filter's length is out of range");
4152                 return -EINVAL;
4153         }
4154         if (filter->priority > E1000_MAX_FLEX_FILTER_PRI) {
4155                 PMD_DRV_LOG(ERR, "filter's priority is out of range");
4156                 return -EINVAL;
4157         }
4158
4159         switch (filter_op) {
4160         case RTE_ETH_FILTER_ADD:
4161                 ret = eth_igb_add_del_flex_filter(dev, filter, TRUE);
4162                 break;
4163         case RTE_ETH_FILTER_DELETE:
4164                 ret = eth_igb_add_del_flex_filter(dev, filter, FALSE);
4165                 break;
4166         case RTE_ETH_FILTER_GET:
4167                 ret = eth_igb_get_flex_filter(dev, filter);
4168                 break;
4169         default:
4170                 PMD_DRV_LOG(ERR, "unsupported operation %u", filter_op);
4171                 ret = -EINVAL;
4172                 break;
4173         }
4174
4175         return ret;
4176 }
4177
4178 /* translate elements in struct rte_eth_ntuple_filter to struct e1000_5tuple_filter_info*/
4179 static inline int
4180 ntuple_filter_to_5tuple_82576(struct rte_eth_ntuple_filter *filter,
4181                         struct e1000_5tuple_filter_info *filter_info)
4182 {
4183         if (filter->queue >= IGB_MAX_RX_QUEUE_NUM_82576)
4184                 return -EINVAL;
4185         if (filter->priority > E1000_2TUPLE_MAX_PRI)
4186                 return -EINVAL;  /* filter index is out of range. */
4187         if (filter->tcp_flags > TCP_FLAG_ALL)
4188                 return -EINVAL;  /* flags is invalid. */
4189
4190         switch (filter->dst_ip_mask) {
4191         case UINT32_MAX:
4192                 filter_info->dst_ip_mask = 0;
4193                 filter_info->dst_ip = filter->dst_ip;
4194                 break;
4195         case 0:
4196                 filter_info->dst_ip_mask = 1;
4197                 break;
4198         default:
4199                 PMD_DRV_LOG(ERR, "invalid dst_ip mask.");
4200                 return -EINVAL;
4201         }
4202
4203         switch (filter->src_ip_mask) {
4204         case UINT32_MAX:
4205                 filter_info->src_ip_mask = 0;
4206                 filter_info->src_ip = filter->src_ip;
4207                 break;
4208         case 0:
4209                 filter_info->src_ip_mask = 1;
4210                 break;
4211         default:
4212                 PMD_DRV_LOG(ERR, "invalid src_ip mask.");
4213                 return -EINVAL;
4214         }
4215
4216         switch (filter->dst_port_mask) {
4217         case UINT16_MAX:
4218                 filter_info->dst_port_mask = 0;
4219                 filter_info->dst_port = filter->dst_port;
4220                 break;
4221         case 0:
4222                 filter_info->dst_port_mask = 1;
4223                 break;
4224         default:
4225                 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
4226                 return -EINVAL;
4227         }
4228
4229         switch (filter->src_port_mask) {
4230         case UINT16_MAX:
4231                 filter_info->src_port_mask = 0;
4232                 filter_info->src_port = filter->src_port;
4233                 break;
4234         case 0:
4235                 filter_info->src_port_mask = 1;
4236                 break;
4237         default:
4238                 PMD_DRV_LOG(ERR, "invalid src_port mask.");
4239                 return -EINVAL;
4240         }
4241
4242         switch (filter->proto_mask) {
4243         case UINT8_MAX:
4244                 filter_info->proto_mask = 0;
4245                 filter_info->proto = filter->proto;
4246                 break;
4247         case 0:
4248                 filter_info->proto_mask = 1;
4249                 break;
4250         default:
4251                 PMD_DRV_LOG(ERR, "invalid protocol mask.");
4252                 return -EINVAL;
4253         }
4254
4255         filter_info->priority = (uint8_t)filter->priority;
4256         if (filter->flags & RTE_NTUPLE_FLAGS_TCP_FLAG)
4257                 filter_info->tcp_flags = filter->tcp_flags;
4258         else
4259                 filter_info->tcp_flags = 0;
4260
4261         return 0;
4262 }
4263
4264 static inline struct e1000_5tuple_filter *
4265 igb_5tuple_filter_lookup_82576(struct e1000_5tuple_filter_list *filter_list,
4266                         struct e1000_5tuple_filter_info *key)
4267 {
4268         struct e1000_5tuple_filter *it;
4269
4270         TAILQ_FOREACH(it, filter_list, entries) {
4271                 if (memcmp(key, &it->filter_info,
4272                         sizeof(struct e1000_5tuple_filter_info)) == 0) {
4273                         return it;
4274                 }
4275         }
4276         return NULL;
4277 }
4278
4279 /* inject a igb 5-tuple filter to HW */
4280 static inline void
4281 igb_inject_5tuple_filter_82576(struct rte_eth_dev *dev,
4282                            struct e1000_5tuple_filter *filter)
4283 {
4284         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4285         uint32_t ftqf = E1000_FTQF_VF_BP | E1000_FTQF_MASK;
4286         uint32_t spqf, imir, imir_ext = E1000_IMIREXT_SIZE_BP;
4287         uint8_t i;
4288
4289         i = filter->index;
4290         ftqf |= filter->filter_info.proto & E1000_FTQF_PROTOCOL_MASK;
4291         if (filter->filter_info.src_ip_mask == 0) /* 0b means compare. */
4292                 ftqf &= ~E1000_FTQF_MASK_SOURCE_ADDR_BP;
4293         if (filter->filter_info.dst_ip_mask == 0)
4294                 ftqf &= ~E1000_FTQF_MASK_DEST_ADDR_BP;
4295         if (filter->filter_info.src_port_mask == 0)
4296                 ftqf &= ~E1000_FTQF_MASK_SOURCE_PORT_BP;
4297         if (filter->filter_info.proto_mask == 0)
4298                 ftqf &= ~E1000_FTQF_MASK_PROTO_BP;
4299         ftqf |= (filter->queue << E1000_FTQF_QUEUE_SHIFT) &
4300                 E1000_FTQF_QUEUE_MASK;
4301         ftqf |= E1000_FTQF_QUEUE_ENABLE;
4302         E1000_WRITE_REG(hw, E1000_FTQF(i), ftqf);
4303         E1000_WRITE_REG(hw, E1000_DAQF(i), filter->filter_info.dst_ip);
4304         E1000_WRITE_REG(hw, E1000_SAQF(i), filter->filter_info.src_ip);
4305
4306         spqf = filter->filter_info.src_port & E1000_SPQF_SRCPORT;
4307         E1000_WRITE_REG(hw, E1000_SPQF(i), spqf);
4308
4309         imir = (uint32_t)(filter->filter_info.dst_port & E1000_IMIR_DSTPORT);
4310         if (filter->filter_info.dst_port_mask == 1) /* 1b means not compare. */
4311                 imir |= E1000_IMIR_PORT_BP;
4312         else
4313                 imir &= ~E1000_IMIR_PORT_BP;
4314         imir |= filter->filter_info.priority << E1000_IMIR_PRIORITY_SHIFT;
4315
4316         /* tcp flags bits setting. */
4317         if (filter->filter_info.tcp_flags & TCP_FLAG_ALL) {
4318                 if (filter->filter_info.tcp_flags & TCP_URG_FLAG)
4319                         imir_ext |= E1000_IMIREXT_CTRL_URG;
4320                 if (filter->filter_info.tcp_flags & TCP_ACK_FLAG)
4321                         imir_ext |= E1000_IMIREXT_CTRL_ACK;
4322                 if (filter->filter_info.tcp_flags & TCP_PSH_FLAG)
4323                         imir_ext |= E1000_IMIREXT_CTRL_PSH;
4324                 if (filter->filter_info.tcp_flags & TCP_RST_FLAG)
4325                         imir_ext |= E1000_IMIREXT_CTRL_RST;
4326                 if (filter->filter_info.tcp_flags & TCP_SYN_FLAG)
4327                         imir_ext |= E1000_IMIREXT_CTRL_SYN;
4328                 if (filter->filter_info.tcp_flags & TCP_FIN_FLAG)
4329                         imir_ext |= E1000_IMIREXT_CTRL_FIN;
4330         } else {
4331                 imir_ext |= E1000_IMIREXT_CTRL_BP;
4332         }
4333         E1000_WRITE_REG(hw, E1000_IMIR(i), imir);
4334         E1000_WRITE_REG(hw, E1000_IMIREXT(i), imir_ext);
4335 }
4336
4337 /*
4338  * igb_add_5tuple_filter_82576 - add a 5tuple filter
4339  *
4340  * @param
4341  * dev: Pointer to struct rte_eth_dev.
4342  * ntuple_filter: ponter to the filter that will be added.
4343  *
4344  * @return
4345  *    - On success, zero.
4346  *    - On failure, a negative value.
4347  */
4348 static int
4349 igb_add_5tuple_filter_82576(struct rte_eth_dev *dev,
4350                         struct rte_eth_ntuple_filter *ntuple_filter)
4351 {
4352         struct e1000_filter_info *filter_info =
4353                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4354         struct e1000_5tuple_filter *filter;
4355         uint8_t i;
4356         int ret;
4357
4358         filter = rte_zmalloc("e1000_5tuple_filter",
4359                         sizeof(struct e1000_5tuple_filter), 0);
4360         if (filter == NULL)
4361                 return -ENOMEM;
4362
4363         ret = ntuple_filter_to_5tuple_82576(ntuple_filter,
4364                                             &filter->filter_info);
4365         if (ret < 0) {
4366                 rte_free(filter);
4367                 return ret;
4368         }
4369
4370         if (igb_5tuple_filter_lookup_82576(&filter_info->fivetuple_list,
4371                                          &filter->filter_info) != NULL) {
4372                 PMD_DRV_LOG(ERR, "filter exists.");
4373                 rte_free(filter);
4374                 return -EEXIST;
4375         }
4376         filter->queue = ntuple_filter->queue;
4377
4378         /*
4379          * look for an unused 5tuple filter index,
4380          * and insert the filter to list.
4381          */
4382         for (i = 0; i < E1000_MAX_FTQF_FILTERS; i++) {
4383                 if (!(filter_info->fivetuple_mask & (1 << i))) {
4384                         filter_info->fivetuple_mask |= 1 << i;
4385                         filter->index = i;
4386                         TAILQ_INSERT_TAIL(&filter_info->fivetuple_list,
4387                                           filter,
4388                                           entries);
4389                         break;
4390                 }
4391         }
4392         if (i >= E1000_MAX_FTQF_FILTERS) {
4393                 PMD_DRV_LOG(ERR, "5tuple filters are full.");
4394                 rte_free(filter);
4395                 return -ENOSYS;
4396         }
4397
4398         igb_inject_5tuple_filter_82576(dev, filter);
4399         return 0;
4400 }
4401
4402 int
4403 igb_delete_5tuple_filter_82576(struct rte_eth_dev *dev,
4404                                 struct e1000_5tuple_filter *filter)
4405 {
4406         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4407         struct e1000_filter_info *filter_info =
4408                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4409
4410         filter_info->fivetuple_mask &= ~(1 << filter->index);
4411         TAILQ_REMOVE(&filter_info->fivetuple_list, filter, entries);
4412         rte_free(filter);
4413
4414         E1000_WRITE_REG(hw, E1000_FTQF(filter->index),
4415                         E1000_FTQF_VF_BP | E1000_FTQF_MASK);
4416         E1000_WRITE_REG(hw, E1000_DAQF(filter->index), 0);
4417         E1000_WRITE_REG(hw, E1000_SAQF(filter->index), 0);
4418         E1000_WRITE_REG(hw, E1000_SPQF(filter->index), 0);
4419         E1000_WRITE_REG(hw, E1000_IMIR(filter->index), 0);
4420         E1000_WRITE_REG(hw, E1000_IMIREXT(filter->index), 0);
4421         return 0;
4422 }
4423
4424 /*
4425  * igb_remove_5tuple_filter_82576 - remove a 5tuple filter
4426  *
4427  * @param
4428  * dev: Pointer to struct rte_eth_dev.
4429  * ntuple_filter: ponter to the filter that will be removed.
4430  *
4431  * @return
4432  *    - On success, zero.
4433  *    - On failure, a negative value.
4434  */
4435 static int
4436 igb_remove_5tuple_filter_82576(struct rte_eth_dev *dev,
4437                                 struct rte_eth_ntuple_filter *ntuple_filter)
4438 {
4439         struct e1000_filter_info *filter_info =
4440                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4441         struct e1000_5tuple_filter_info filter_5tuple;
4442         struct e1000_5tuple_filter *filter;
4443         int ret;
4444
4445         memset(&filter_5tuple, 0, sizeof(struct e1000_5tuple_filter_info));
4446         ret = ntuple_filter_to_5tuple_82576(ntuple_filter,
4447                                             &filter_5tuple);
4448         if (ret < 0)
4449                 return ret;
4450
4451         filter = igb_5tuple_filter_lookup_82576(&filter_info->fivetuple_list,
4452                                          &filter_5tuple);
4453         if (filter == NULL) {
4454                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
4455                 return -ENOENT;
4456         }
4457
4458         igb_delete_5tuple_filter_82576(dev, filter);
4459
4460         return 0;
4461 }
4462
4463 static int
4464 eth_igb_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
4465 {
4466         uint32_t rctl;
4467         struct e1000_hw *hw;
4468         struct rte_eth_dev_info dev_info;
4469         uint32_t frame_size = mtu + (ETHER_HDR_LEN + ETHER_CRC_LEN +
4470                                      VLAN_TAG_SIZE);
4471
4472         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4473
4474 #ifdef RTE_LIBRTE_82571_SUPPORT
4475         /* XXX: not bigger than max_rx_pktlen */
4476         if (hw->mac.type == e1000_82571)
4477                 return -ENOTSUP;
4478 #endif
4479         eth_igb_infos_get(dev, &dev_info);
4480
4481         /* check that mtu is within the allowed range */
4482         if ((mtu < ETHER_MIN_MTU) ||
4483             (frame_size > dev_info.max_rx_pktlen))
4484                 return -EINVAL;
4485
4486         /* refuse mtu that requires the support of scattered packets when this
4487          * feature has not been enabled before. */
4488         if (!dev->data->scattered_rx &&
4489             frame_size > dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)
4490                 return -EINVAL;
4491
4492         rctl = E1000_READ_REG(hw, E1000_RCTL);
4493
4494         /* switch to jumbo mode if needed */
4495         if (frame_size > ETHER_MAX_LEN) {
4496                 dev->data->dev_conf.rxmode.jumbo_frame = 1;
4497                 rctl |= E1000_RCTL_LPE;
4498         } else {
4499                 dev->data->dev_conf.rxmode.jumbo_frame = 0;
4500                 rctl &= ~E1000_RCTL_LPE;
4501         }
4502         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
4503
4504         /* update max frame size */
4505         dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
4506
4507         E1000_WRITE_REG(hw, E1000_RLPML,
4508                         dev->data->dev_conf.rxmode.max_rx_pkt_len);
4509
4510         return 0;
4511 }
4512
4513 /*
4514  * igb_add_del_ntuple_filter - add or delete a ntuple filter
4515  *
4516  * @param
4517  * dev: Pointer to struct rte_eth_dev.
4518  * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
4519  * add: if true, add filter, if false, remove filter
4520  *
4521  * @return
4522  *    - On success, zero.
4523  *    - On failure, a negative value.
4524  */
4525 int
4526 igb_add_del_ntuple_filter(struct rte_eth_dev *dev,
4527                         struct rte_eth_ntuple_filter *ntuple_filter,
4528                         bool add)
4529 {
4530         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4531         int ret;
4532
4533         switch (ntuple_filter->flags) {
4534         case RTE_5TUPLE_FLAGS:
4535         case (RTE_5TUPLE_FLAGS | RTE_NTUPLE_FLAGS_TCP_FLAG):
4536                 if (hw->mac.type != e1000_82576)
4537                         return -ENOTSUP;
4538                 if (add)
4539                         ret = igb_add_5tuple_filter_82576(dev,
4540                                                           ntuple_filter);
4541                 else
4542                         ret = igb_remove_5tuple_filter_82576(dev,
4543                                                              ntuple_filter);
4544                 break;
4545         case RTE_2TUPLE_FLAGS:
4546         case (RTE_2TUPLE_FLAGS | RTE_NTUPLE_FLAGS_TCP_FLAG):
4547                 if (hw->mac.type != e1000_82580 && hw->mac.type != e1000_i350 &&
4548                         hw->mac.type != e1000_i210 &&
4549                         hw->mac.type != e1000_i211)
4550                         return -ENOTSUP;
4551                 if (add)
4552                         ret = igb_add_2tuple_filter(dev, ntuple_filter);
4553                 else
4554                         ret = igb_remove_2tuple_filter(dev, ntuple_filter);
4555                 break;
4556         default:
4557                 ret = -EINVAL;
4558                 break;
4559         }
4560
4561         return ret;
4562 }
4563
4564 /*
4565  * igb_get_ntuple_filter - get a ntuple filter
4566  *
4567  * @param
4568  * dev: Pointer to struct rte_eth_dev.
4569  * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
4570  *
4571  * @return
4572  *    - On success, zero.
4573  *    - On failure, a negative value.
4574  */
4575 static int
4576 igb_get_ntuple_filter(struct rte_eth_dev *dev,
4577                         struct rte_eth_ntuple_filter *ntuple_filter)
4578 {
4579         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4580         struct e1000_filter_info *filter_info =
4581                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4582         struct e1000_5tuple_filter_info filter_5tuple;
4583         struct e1000_2tuple_filter_info filter_2tuple;
4584         struct e1000_5tuple_filter *p_5tuple_filter;
4585         struct e1000_2tuple_filter *p_2tuple_filter;
4586         int ret;
4587
4588         switch (ntuple_filter->flags) {
4589         case RTE_5TUPLE_FLAGS:
4590         case (RTE_5TUPLE_FLAGS | RTE_NTUPLE_FLAGS_TCP_FLAG):
4591                 if (hw->mac.type != e1000_82576)
4592                         return -ENOTSUP;
4593                 memset(&filter_5tuple,
4594                         0,
4595                         sizeof(struct e1000_5tuple_filter_info));
4596                 ret = ntuple_filter_to_5tuple_82576(ntuple_filter,
4597                                                     &filter_5tuple);
4598                 if (ret < 0)
4599                         return ret;
4600                 p_5tuple_filter = igb_5tuple_filter_lookup_82576(
4601                                         &filter_info->fivetuple_list,
4602                                         &filter_5tuple);
4603                 if (p_5tuple_filter == NULL) {
4604                         PMD_DRV_LOG(ERR, "filter doesn't exist.");
4605                         return -ENOENT;
4606                 }
4607                 ntuple_filter->queue = p_5tuple_filter->queue;
4608                 break;
4609         case RTE_2TUPLE_FLAGS:
4610         case (RTE_2TUPLE_FLAGS | RTE_NTUPLE_FLAGS_TCP_FLAG):
4611                 if (hw->mac.type != e1000_82580 && hw->mac.type != e1000_i350)
4612                         return -ENOTSUP;
4613                 memset(&filter_2tuple,
4614                         0,
4615                         sizeof(struct e1000_2tuple_filter_info));
4616                 ret = ntuple_filter_to_2tuple(ntuple_filter, &filter_2tuple);
4617                 if (ret < 0)
4618                         return ret;
4619                 p_2tuple_filter = igb_2tuple_filter_lookup(
4620                                         &filter_info->twotuple_list,
4621                                         &filter_2tuple);
4622                 if (p_2tuple_filter == NULL) {
4623                         PMD_DRV_LOG(ERR, "filter doesn't exist.");
4624                         return -ENOENT;
4625                 }
4626                 ntuple_filter->queue = p_2tuple_filter->queue;
4627                 break;
4628         default:
4629                 ret = -EINVAL;
4630                 break;
4631         }
4632
4633         return 0;
4634 }
4635
4636 /*
4637  * igb_ntuple_filter_handle - Handle operations for ntuple filter.
4638  * @dev: pointer to rte_eth_dev structure
4639  * @filter_op:operation will be taken.
4640  * @arg: a pointer to specific structure corresponding to the filter_op
4641  */
4642 static int
4643 igb_ntuple_filter_handle(struct rte_eth_dev *dev,
4644                                 enum rte_filter_op filter_op,
4645                                 void *arg)
4646 {
4647         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4648         int ret;
4649
4650         MAC_TYPE_FILTER_SUP(hw->mac.type);
4651
4652         if (filter_op == RTE_ETH_FILTER_NOP)
4653                 return 0;
4654
4655         if (arg == NULL) {
4656                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
4657                             filter_op);
4658                 return -EINVAL;
4659         }
4660
4661         switch (filter_op) {
4662         case RTE_ETH_FILTER_ADD:
4663                 ret = igb_add_del_ntuple_filter(dev,
4664                         (struct rte_eth_ntuple_filter *)arg,
4665                         TRUE);
4666                 break;
4667         case RTE_ETH_FILTER_DELETE:
4668                 ret = igb_add_del_ntuple_filter(dev,
4669                         (struct rte_eth_ntuple_filter *)arg,
4670                         FALSE);
4671                 break;
4672         case RTE_ETH_FILTER_GET:
4673                 ret = igb_get_ntuple_filter(dev,
4674                         (struct rte_eth_ntuple_filter *)arg);
4675                 break;
4676         default:
4677                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
4678                 ret = -EINVAL;
4679                 break;
4680         }
4681         return ret;
4682 }
4683
4684 static inline int
4685 igb_ethertype_filter_lookup(struct e1000_filter_info *filter_info,
4686                         uint16_t ethertype)
4687 {
4688         int i;
4689
4690         for (i = 0; i < E1000_MAX_ETQF_FILTERS; i++) {
4691                 if (filter_info->ethertype_filters[i].ethertype == ethertype &&
4692                     (filter_info->ethertype_mask & (1 << i)))
4693                         return i;
4694         }
4695         return -1;
4696 }
4697
4698 static inline int
4699 igb_ethertype_filter_insert(struct e1000_filter_info *filter_info,
4700                         uint16_t ethertype, uint32_t etqf)
4701 {
4702         int i;
4703
4704         for (i = 0; i < E1000_MAX_ETQF_FILTERS; i++) {
4705                 if (!(filter_info->ethertype_mask & (1 << i))) {
4706                         filter_info->ethertype_mask |= 1 << i;
4707                         filter_info->ethertype_filters[i].ethertype = ethertype;
4708                         filter_info->ethertype_filters[i].etqf = etqf;
4709                         return i;
4710                 }
4711         }
4712         return -1;
4713 }
4714
4715 int
4716 igb_ethertype_filter_remove(struct e1000_filter_info *filter_info,
4717                         uint8_t idx)
4718 {
4719         if (idx >= E1000_MAX_ETQF_FILTERS)
4720                 return -1;
4721         filter_info->ethertype_mask &= ~(1 << idx);
4722         filter_info->ethertype_filters[idx].ethertype = 0;
4723         filter_info->ethertype_filters[idx].etqf = 0;
4724         return idx;
4725 }
4726
4727
4728 int
4729 igb_add_del_ethertype_filter(struct rte_eth_dev *dev,
4730                         struct rte_eth_ethertype_filter *filter,
4731                         bool add)
4732 {
4733         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4734         struct e1000_filter_info *filter_info =
4735                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4736         uint32_t etqf = 0;
4737         int ret;
4738
4739         if (filter->ether_type == ETHER_TYPE_IPv4 ||
4740                 filter->ether_type == ETHER_TYPE_IPv6) {
4741                 PMD_DRV_LOG(ERR, "unsupported ether_type(0x%04x) in"
4742                         " ethertype filter.", filter->ether_type);
4743                 return -EINVAL;
4744         }
4745
4746         if (filter->flags & RTE_ETHTYPE_FLAGS_MAC) {
4747                 PMD_DRV_LOG(ERR, "mac compare is unsupported.");
4748                 return -EINVAL;
4749         }
4750         if (filter->flags & RTE_ETHTYPE_FLAGS_DROP) {
4751                 PMD_DRV_LOG(ERR, "drop option is unsupported.");
4752                 return -EINVAL;
4753         }
4754
4755         ret = igb_ethertype_filter_lookup(filter_info, filter->ether_type);
4756         if (ret >= 0 && add) {
4757                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter exists.",
4758                             filter->ether_type);
4759                 return -EEXIST;
4760         }
4761         if (ret < 0 && !add) {
4762                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
4763                             filter->ether_type);
4764                 return -ENOENT;
4765         }
4766
4767         if (add) {
4768                 etqf |= E1000_ETQF_FILTER_ENABLE | E1000_ETQF_QUEUE_ENABLE;
4769                 etqf |= (uint32_t)(filter->ether_type & E1000_ETQF_ETHERTYPE);
4770                 etqf |= filter->queue << E1000_ETQF_QUEUE_SHIFT;
4771                 ret = igb_ethertype_filter_insert(filter_info,
4772                                 filter->ether_type, etqf);
4773                 if (ret < 0) {
4774                         PMD_DRV_LOG(ERR, "ethertype filters are full.");
4775                         return -ENOSYS;
4776                 }
4777         } else {
4778                 ret = igb_ethertype_filter_remove(filter_info, (uint8_t)ret);
4779                 if (ret < 0)
4780                         return -ENOSYS;
4781         }
4782         E1000_WRITE_REG(hw, E1000_ETQF(ret), etqf);
4783         E1000_WRITE_FLUSH(hw);
4784
4785         return 0;
4786 }
4787
4788 static int
4789 igb_get_ethertype_filter(struct rte_eth_dev *dev,
4790                         struct rte_eth_ethertype_filter *filter)
4791 {
4792         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4793         struct e1000_filter_info *filter_info =
4794                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4795         uint32_t etqf;
4796         int ret;
4797
4798         ret = igb_ethertype_filter_lookup(filter_info, filter->ether_type);
4799         if (ret < 0) {
4800                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
4801                             filter->ether_type);
4802                 return -ENOENT;
4803         }
4804
4805         etqf = E1000_READ_REG(hw, E1000_ETQF(ret));
4806         if (etqf & E1000_ETQF_FILTER_ENABLE) {
4807                 filter->ether_type = etqf & E1000_ETQF_ETHERTYPE;
4808                 filter->flags = 0;
4809                 filter->queue = (etqf & E1000_ETQF_QUEUE) >>
4810                                 E1000_ETQF_QUEUE_SHIFT;
4811                 return 0;
4812         }
4813
4814         return -ENOENT;
4815 }
4816
4817 /*
4818  * igb_ethertype_filter_handle - Handle operations for ethertype filter.
4819  * @dev: pointer to rte_eth_dev structure
4820  * @filter_op:operation will be taken.
4821  * @arg: a pointer to specific structure corresponding to the filter_op
4822  */
4823 static int
4824 igb_ethertype_filter_handle(struct rte_eth_dev *dev,
4825                                 enum rte_filter_op filter_op,
4826                                 void *arg)
4827 {
4828         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4829         int ret;
4830
4831         MAC_TYPE_FILTER_SUP(hw->mac.type);
4832
4833         if (filter_op == RTE_ETH_FILTER_NOP)
4834                 return 0;
4835
4836         if (arg == NULL) {
4837                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
4838                             filter_op);
4839                 return -EINVAL;
4840         }
4841
4842         switch (filter_op) {
4843         case RTE_ETH_FILTER_ADD:
4844                 ret = igb_add_del_ethertype_filter(dev,
4845                         (struct rte_eth_ethertype_filter *)arg,
4846                         TRUE);
4847                 break;
4848         case RTE_ETH_FILTER_DELETE:
4849                 ret = igb_add_del_ethertype_filter(dev,
4850                         (struct rte_eth_ethertype_filter *)arg,
4851                         FALSE);
4852                 break;
4853         case RTE_ETH_FILTER_GET:
4854                 ret = igb_get_ethertype_filter(dev,
4855                         (struct rte_eth_ethertype_filter *)arg);
4856                 break;
4857         default:
4858                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
4859                 ret = -EINVAL;
4860                 break;
4861         }
4862         return ret;
4863 }
4864
4865 static int
4866 eth_igb_filter_ctrl(struct rte_eth_dev *dev,
4867                      enum rte_filter_type filter_type,
4868                      enum rte_filter_op filter_op,
4869                      void *arg)
4870 {
4871         int ret = 0;
4872
4873         switch (filter_type) {
4874         case RTE_ETH_FILTER_NTUPLE:
4875                 ret = igb_ntuple_filter_handle(dev, filter_op, arg);
4876                 break;
4877         case RTE_ETH_FILTER_ETHERTYPE:
4878                 ret = igb_ethertype_filter_handle(dev, filter_op, arg);
4879                 break;
4880         case RTE_ETH_FILTER_SYN:
4881                 ret = eth_igb_syn_filter_handle(dev, filter_op, arg);
4882                 break;
4883         case RTE_ETH_FILTER_FLEXIBLE:
4884                 ret = eth_igb_flex_filter_handle(dev, filter_op, arg);
4885                 break;
4886         case RTE_ETH_FILTER_GENERIC:
4887                 if (filter_op != RTE_ETH_FILTER_GET)
4888                         return -EINVAL;
4889                 *(const void **)arg = &igb_flow_ops;
4890                 break;
4891         default:
4892                 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
4893                                                         filter_type);
4894                 break;
4895         }
4896
4897         return ret;
4898 }
4899
4900 static int
4901 eth_igb_set_mc_addr_list(struct rte_eth_dev *dev,
4902                          struct ether_addr *mc_addr_set,
4903                          uint32_t nb_mc_addr)
4904 {
4905         struct e1000_hw *hw;
4906
4907         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4908         e1000_update_mc_addr_list(hw, (u8 *)mc_addr_set, nb_mc_addr);
4909         return 0;
4910 }
4911
4912 static uint64_t
4913 igb_read_systime_cyclecounter(struct rte_eth_dev *dev)
4914 {
4915         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4916         uint64_t systime_cycles;
4917
4918         switch (hw->mac.type) {
4919         case e1000_i210:
4920         case e1000_i211:
4921                 /*
4922                  * Need to read System Time Residue Register to be able
4923                  * to read the other two registers.
4924                  */
4925                 E1000_READ_REG(hw, E1000_SYSTIMR);
4926                 /* SYSTIMEL stores ns and SYSTIMEH stores seconds. */
4927                 systime_cycles = (uint64_t)E1000_READ_REG(hw, E1000_SYSTIML);
4928                 systime_cycles += (uint64_t)E1000_READ_REG(hw, E1000_SYSTIMH)
4929                                 * NSEC_PER_SEC;
4930                 break;
4931         case e1000_82580:
4932         case e1000_i350:
4933         case e1000_i354:
4934                 /*
4935                  * Need to read System Time Residue Register to be able
4936                  * to read the other two registers.
4937                  */
4938                 E1000_READ_REG(hw, E1000_SYSTIMR);
4939                 systime_cycles = (uint64_t)E1000_READ_REG(hw, E1000_SYSTIML);
4940                 /* Only the 8 LSB are valid. */
4941                 systime_cycles |= (uint64_t)(E1000_READ_REG(hw, E1000_SYSTIMH)
4942                                 & 0xff) << 32;
4943                 break;
4944         default:
4945                 systime_cycles = (uint64_t)E1000_READ_REG(hw, E1000_SYSTIML);
4946                 systime_cycles |= (uint64_t)E1000_READ_REG(hw, E1000_SYSTIMH)
4947                                 << 32;
4948                 break;
4949         }
4950
4951         return systime_cycles;
4952 }
4953
4954 static uint64_t
4955 igb_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev)
4956 {
4957         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4958         uint64_t rx_tstamp_cycles;
4959
4960         switch (hw->mac.type) {
4961         case e1000_i210:
4962         case e1000_i211:
4963                 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
4964                 rx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_RXSTMPL);
4965                 rx_tstamp_cycles += (uint64_t)E1000_READ_REG(hw, E1000_RXSTMPH)
4966                                 * NSEC_PER_SEC;
4967                 break;
4968         case e1000_82580:
4969         case e1000_i350:
4970         case e1000_i354:
4971                 rx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_RXSTMPL);
4972                 /* Only the 8 LSB are valid. */
4973                 rx_tstamp_cycles |= (uint64_t)(E1000_READ_REG(hw, E1000_RXSTMPH)
4974                                 & 0xff) << 32;
4975                 break;
4976         default:
4977                 rx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_RXSTMPL);
4978                 rx_tstamp_cycles |= (uint64_t)E1000_READ_REG(hw, E1000_RXSTMPH)
4979                                 << 32;
4980                 break;
4981         }
4982
4983         return rx_tstamp_cycles;
4984 }
4985
4986 static uint64_t
4987 igb_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev)
4988 {
4989         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4990         uint64_t tx_tstamp_cycles;
4991
4992         switch (hw->mac.type) {
4993         case e1000_i210:
4994         case e1000_i211:
4995                 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
4996                 tx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_TXSTMPL);
4997                 tx_tstamp_cycles += (uint64_t)E1000_READ_REG(hw, E1000_TXSTMPH)
4998                                 * NSEC_PER_SEC;
4999                 break;
5000         case e1000_82580:
5001         case e1000_i350:
5002         case e1000_i354:
5003                 tx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_TXSTMPL);
5004                 /* Only the 8 LSB are valid. */
5005                 tx_tstamp_cycles |= (uint64_t)(E1000_READ_REG(hw, E1000_TXSTMPH)
5006                                 & 0xff) << 32;
5007                 break;
5008         default:
5009                 tx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_TXSTMPL);
5010                 tx_tstamp_cycles |= (uint64_t)E1000_READ_REG(hw, E1000_TXSTMPH)
5011                                 << 32;
5012                 break;
5013         }
5014
5015         return tx_tstamp_cycles;
5016 }
5017
5018 static void
5019 igb_start_timecounters(struct rte_eth_dev *dev)
5020 {
5021         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5022         struct e1000_adapter *adapter =
5023                 (struct e1000_adapter *)dev->data->dev_private;
5024         uint32_t incval = 1;
5025         uint32_t shift = 0;
5026         uint64_t mask = E1000_CYCLECOUNTER_MASK;
5027
5028         switch (hw->mac.type) {
5029         case e1000_82580:
5030         case e1000_i350:
5031         case e1000_i354:
5032                 /* 32 LSB bits + 8 MSB bits = 40 bits */
5033                 mask = (1ULL << 40) - 1;
5034                 /* fall-through */
5035         case e1000_i210:
5036         case e1000_i211:
5037                 /*
5038                  * Start incrementing the register
5039                  * used to timestamp PTP packets.
5040                  */
5041                 E1000_WRITE_REG(hw, E1000_TIMINCA, incval);
5042                 break;
5043         case e1000_82576:
5044                 incval = E1000_INCVALUE_82576;
5045                 shift = IGB_82576_TSYNC_SHIFT;
5046                 E1000_WRITE_REG(hw, E1000_TIMINCA,
5047                                 E1000_INCPERIOD_82576 | incval);
5048                 break;
5049         default:
5050                 /* Not supported */
5051                 return;
5052         }
5053
5054         memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter));
5055         memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
5056         memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
5057
5058         adapter->systime_tc.cc_mask = mask;
5059         adapter->systime_tc.cc_shift = shift;
5060         adapter->systime_tc.nsec_mask = (1ULL << shift) - 1;
5061
5062         adapter->rx_tstamp_tc.cc_mask = mask;
5063         adapter->rx_tstamp_tc.cc_shift = shift;
5064         adapter->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
5065
5066         adapter->tx_tstamp_tc.cc_mask = mask;
5067         adapter->tx_tstamp_tc.cc_shift = shift;
5068         adapter->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
5069 }
5070
5071 static int
5072 igb_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
5073 {
5074         struct e1000_adapter *adapter =
5075                         (struct e1000_adapter *)dev->data->dev_private;
5076
5077         adapter->systime_tc.nsec += delta;
5078         adapter->rx_tstamp_tc.nsec += delta;
5079         adapter->tx_tstamp_tc.nsec += delta;
5080
5081         return 0;
5082 }
5083
5084 static int
5085 igb_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
5086 {
5087         uint64_t ns;
5088         struct e1000_adapter *adapter =
5089                         (struct e1000_adapter *)dev->data->dev_private;
5090
5091         ns = rte_timespec_to_ns(ts);
5092
5093         /* Set the timecounters to a new value. */
5094         adapter->systime_tc.nsec = ns;
5095         adapter->rx_tstamp_tc.nsec = ns;
5096         adapter->tx_tstamp_tc.nsec = ns;
5097
5098         return 0;
5099 }
5100
5101 static int
5102 igb_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
5103 {
5104         uint64_t ns, systime_cycles;
5105         struct e1000_adapter *adapter =
5106                         (struct e1000_adapter *)dev->data->dev_private;
5107
5108         systime_cycles = igb_read_systime_cyclecounter(dev);
5109         ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles);
5110         *ts = rte_ns_to_timespec(ns);
5111
5112         return 0;
5113 }
5114
5115 static int
5116 igb_timesync_enable(struct rte_eth_dev *dev)
5117 {
5118         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5119         uint32_t tsync_ctl;
5120         uint32_t tsauxc;
5121
5122         /* Stop the timesync system time. */
5123         E1000_WRITE_REG(hw, E1000_TIMINCA, 0x0);
5124         /* Reset the timesync system time value. */
5125         switch (hw->mac.type) {
5126         case e1000_82580:
5127         case e1000_i350:
5128         case e1000_i354:
5129         case e1000_i210:
5130         case e1000_i211:
5131                 E1000_WRITE_REG(hw, E1000_SYSTIMR, 0x0);
5132                 /* fall-through */
5133         case e1000_82576:
5134                 E1000_WRITE_REG(hw, E1000_SYSTIML, 0x0);
5135                 E1000_WRITE_REG(hw, E1000_SYSTIMH, 0x0);
5136                 break;
5137         default:
5138                 /* Not supported. */
5139                 return -ENOTSUP;
5140         }
5141
5142         /* Enable system time for it isn't on by default. */
5143         tsauxc = E1000_READ_REG(hw, E1000_TSAUXC);
5144         tsauxc &= ~E1000_TSAUXC_DISABLE_SYSTIME;
5145         E1000_WRITE_REG(hw, E1000_TSAUXC, tsauxc);
5146
5147         igb_start_timecounters(dev);
5148
5149         /* Enable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
5150         E1000_WRITE_REG(hw, E1000_ETQF(E1000_ETQF_FILTER_1588),
5151                         (ETHER_TYPE_1588 |
5152                          E1000_ETQF_FILTER_ENABLE |
5153                          E1000_ETQF_1588));
5154
5155         /* Enable timestamping of received PTP packets. */
5156         tsync_ctl = E1000_READ_REG(hw, E1000_TSYNCRXCTL);
5157         tsync_ctl |= E1000_TSYNCRXCTL_ENABLED;
5158         E1000_WRITE_REG(hw, E1000_TSYNCRXCTL, tsync_ctl);
5159
5160         /* Enable Timestamping of transmitted PTP packets. */
5161         tsync_ctl = E1000_READ_REG(hw, E1000_TSYNCTXCTL);
5162         tsync_ctl |= E1000_TSYNCTXCTL_ENABLED;
5163         E1000_WRITE_REG(hw, E1000_TSYNCTXCTL, tsync_ctl);
5164
5165         return 0;
5166 }
5167
5168 static int
5169 igb_timesync_disable(struct rte_eth_dev *dev)
5170 {
5171         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5172         uint32_t tsync_ctl;
5173
5174         /* Disable timestamping of transmitted PTP packets. */
5175         tsync_ctl = E1000_READ_REG(hw, E1000_TSYNCTXCTL);
5176         tsync_ctl &= ~E1000_TSYNCTXCTL_ENABLED;
5177         E1000_WRITE_REG(hw, E1000_TSYNCTXCTL, tsync_ctl);
5178
5179         /* Disable timestamping of received PTP packets. */
5180         tsync_ctl = E1000_READ_REG(hw, E1000_TSYNCRXCTL);
5181         tsync_ctl &= ~E1000_TSYNCRXCTL_ENABLED;
5182         E1000_WRITE_REG(hw, E1000_TSYNCRXCTL, tsync_ctl);
5183
5184         /* Disable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
5185         E1000_WRITE_REG(hw, E1000_ETQF(E1000_ETQF_FILTER_1588), 0);
5186
5187         /* Stop incrementating the System Time registers. */
5188         E1000_WRITE_REG(hw, E1000_TIMINCA, 0);
5189
5190         return 0;
5191 }
5192
5193 static int
5194 igb_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
5195                                struct timespec *timestamp,
5196                                uint32_t flags __rte_unused)
5197 {
5198         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5199         struct e1000_adapter *adapter =
5200                         (struct e1000_adapter *)dev->data->dev_private;
5201         uint32_t tsync_rxctl;
5202         uint64_t rx_tstamp_cycles;
5203         uint64_t ns;
5204
5205         tsync_rxctl = E1000_READ_REG(hw, E1000_TSYNCRXCTL);
5206         if ((tsync_rxctl & E1000_TSYNCRXCTL_VALID) == 0)
5207                 return -EINVAL;
5208
5209         rx_tstamp_cycles = igb_read_rx_tstamp_cyclecounter(dev);
5210         ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles);
5211         *timestamp = rte_ns_to_timespec(ns);
5212
5213         return  0;
5214 }
5215
5216 static int
5217 igb_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
5218                                struct timespec *timestamp)
5219 {
5220         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5221         struct e1000_adapter *adapter =
5222                         (struct e1000_adapter *)dev->data->dev_private;
5223         uint32_t tsync_txctl;
5224         uint64_t tx_tstamp_cycles;
5225         uint64_t ns;
5226
5227         tsync_txctl = E1000_READ_REG(hw, E1000_TSYNCTXCTL);
5228         if ((tsync_txctl & E1000_TSYNCTXCTL_VALID) == 0)
5229                 return -EINVAL;
5230
5231         tx_tstamp_cycles = igb_read_tx_tstamp_cyclecounter(dev);
5232         ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles);
5233         *timestamp = rte_ns_to_timespec(ns);
5234
5235         return  0;
5236 }
5237
5238 static int
5239 eth_igb_get_reg_length(struct rte_eth_dev *dev __rte_unused)
5240 {
5241         int count = 0;
5242         int g_ind = 0;
5243         const struct reg_info *reg_group;
5244
5245         while ((reg_group = igb_regs[g_ind++]))
5246                 count += igb_reg_group_count(reg_group);
5247
5248         return count;
5249 }
5250
5251 static int
5252 igbvf_get_reg_length(struct rte_eth_dev *dev __rte_unused)
5253 {
5254         int count = 0;
5255         int g_ind = 0;
5256         const struct reg_info *reg_group;
5257
5258         while ((reg_group = igbvf_regs[g_ind++]))
5259                 count += igb_reg_group_count(reg_group);
5260
5261         return count;
5262 }
5263
5264 static int
5265 eth_igb_get_regs(struct rte_eth_dev *dev,
5266         struct rte_dev_reg_info *regs)
5267 {
5268         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5269         uint32_t *data = regs->data;
5270         int g_ind = 0;
5271         int count = 0;
5272         const struct reg_info *reg_group;
5273
5274         if (data == NULL) {
5275                 regs->length = eth_igb_get_reg_length(dev);
5276                 regs->width = sizeof(uint32_t);
5277                 return 0;
5278         }
5279
5280         /* Support only full register dump */
5281         if ((regs->length == 0) ||
5282             (regs->length == (uint32_t)eth_igb_get_reg_length(dev))) {
5283                 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
5284                         hw->device_id;
5285                 while ((reg_group = igb_regs[g_ind++]))
5286                         count += igb_read_regs_group(dev, &data[count],
5287                                                         reg_group);
5288                 return 0;
5289         }
5290
5291         return -ENOTSUP;
5292 }
5293
5294 static int
5295 igbvf_get_regs(struct rte_eth_dev *dev,
5296         struct rte_dev_reg_info *regs)
5297 {
5298         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5299         uint32_t *data = regs->data;
5300         int g_ind = 0;
5301         int count = 0;
5302         const struct reg_info *reg_group;
5303
5304         if (data == NULL) {
5305                 regs->length = igbvf_get_reg_length(dev);
5306                 regs->width = sizeof(uint32_t);
5307                 return 0;
5308         }
5309
5310         /* Support only full register dump */
5311         if ((regs->length == 0) ||
5312             (regs->length == (uint32_t)igbvf_get_reg_length(dev))) {
5313                 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
5314                         hw->device_id;
5315                 while ((reg_group = igbvf_regs[g_ind++]))
5316                         count += igb_read_regs_group(dev, &data[count],
5317                                                         reg_group);
5318                 return 0;
5319         }
5320
5321         return -ENOTSUP;
5322 }
5323
5324 static int
5325 eth_igb_get_eeprom_length(struct rte_eth_dev *dev)
5326 {
5327         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5328
5329         /* Return unit is byte count */
5330         return hw->nvm.word_size * 2;
5331 }
5332
5333 static int
5334 eth_igb_get_eeprom(struct rte_eth_dev *dev,
5335         struct rte_dev_eeprom_info *in_eeprom)
5336 {
5337         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5338         struct e1000_nvm_info *nvm = &hw->nvm;
5339         uint16_t *data = in_eeprom->data;
5340         int first, length;
5341
5342         first = in_eeprom->offset >> 1;
5343         length = in_eeprom->length >> 1;
5344         if ((first >= hw->nvm.word_size) ||
5345             ((first + length) >= hw->nvm.word_size))
5346                 return -EINVAL;
5347
5348         in_eeprom->magic = hw->vendor_id |
5349                 ((uint32_t)hw->device_id << 16);
5350
5351         if ((nvm->ops.read) == NULL)
5352                 return -ENOTSUP;
5353
5354         return nvm->ops.read(hw, first, length, data);
5355 }
5356
5357 static int
5358 eth_igb_set_eeprom(struct rte_eth_dev *dev,
5359         struct rte_dev_eeprom_info *in_eeprom)
5360 {
5361         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5362         struct e1000_nvm_info *nvm = &hw->nvm;
5363         uint16_t *data = in_eeprom->data;
5364         int first, length;
5365
5366         first = in_eeprom->offset >> 1;
5367         length = in_eeprom->length >> 1;
5368         if ((first >= hw->nvm.word_size) ||
5369             ((first + length) >= hw->nvm.word_size))
5370                 return -EINVAL;
5371
5372         in_eeprom->magic = (uint32_t)hw->vendor_id |
5373                 ((uint32_t)hw->device_id << 16);
5374
5375         if ((nvm->ops.write) == NULL)
5376                 return -ENOTSUP;
5377         return nvm->ops.write(hw,  first, length, data);
5378 }
5379
5380 static int
5381 eth_igb_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
5382 {
5383         struct e1000_hw *hw =
5384                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5385         uint32_t mask = 1 << queue_id;
5386
5387         E1000_WRITE_REG(hw, E1000_EIMC, mask);
5388         E1000_WRITE_FLUSH(hw);
5389
5390         return 0;
5391 }
5392
5393 static int
5394 eth_igb_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
5395 {
5396         struct e1000_hw *hw =
5397                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5398         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5399         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5400         uint32_t mask = 1 << queue_id;
5401         uint32_t regval;
5402
5403         regval = E1000_READ_REG(hw, E1000_EIMS);
5404         E1000_WRITE_REG(hw, E1000_EIMS, regval | mask);
5405         E1000_WRITE_FLUSH(hw);
5406
5407         rte_intr_enable(intr_handle);
5408
5409         return 0;
5410 }
5411
5412 static void
5413 eth_igb_write_ivar(struct e1000_hw *hw, uint8_t  msix_vector,
5414                    uint8_t index, uint8_t offset)
5415 {
5416         uint32_t val = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index);
5417
5418         /* clear bits */
5419         val &= ~((uint32_t)0xFF << offset);
5420
5421         /* write vector and valid bit */
5422         val |= (msix_vector | E1000_IVAR_VALID) << offset;
5423
5424         E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, val);
5425 }
5426
5427 static void
5428 eth_igb_assign_msix_vector(struct e1000_hw *hw, int8_t direction,
5429                            uint8_t queue, uint8_t msix_vector)
5430 {
5431         uint32_t tmp = 0;
5432
5433         if (hw->mac.type == e1000_82575) {
5434                 if (direction == 0)
5435                         tmp = E1000_EICR_RX_QUEUE0 << queue;
5436                 else if (direction == 1)
5437                         tmp = E1000_EICR_TX_QUEUE0 << queue;
5438                 E1000_WRITE_REG(hw, E1000_MSIXBM(msix_vector), tmp);
5439         } else if (hw->mac.type == e1000_82576) {
5440                 if ((direction == 0) || (direction == 1))
5441                         eth_igb_write_ivar(hw, msix_vector, queue & 0x7,
5442                                            ((queue & 0x8) << 1) +
5443                                            8 * direction);
5444         } else if ((hw->mac.type == e1000_82580) ||
5445                         (hw->mac.type == e1000_i350) ||
5446                         (hw->mac.type == e1000_i354) ||
5447                         (hw->mac.type == e1000_i210) ||
5448                         (hw->mac.type == e1000_i211)) {
5449                 if ((direction == 0) || (direction == 1))
5450                         eth_igb_write_ivar(hw, msix_vector,
5451                                            queue >> 1,
5452                                            ((queue & 0x1) << 4) +
5453                                            8 * direction);
5454         }
5455 }
5456
5457 /* Sets up the hardware to generate MSI-X interrupts properly
5458  * @hw
5459  *  board private structure
5460  */
5461 static void
5462 eth_igb_configure_msix_intr(struct rte_eth_dev *dev)
5463 {
5464         int queue_id;
5465         uint32_t tmpval, regval, intr_mask;
5466         struct e1000_hw *hw =
5467                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5468         uint32_t vec = E1000_MISC_VEC_ID;
5469         uint32_t base = E1000_MISC_VEC_ID;
5470         uint32_t misc_shift = 0;
5471         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5472         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5473
5474         /* won't configure msix register if no mapping is done
5475          * between intr vector and event fd
5476          */
5477         if (!rte_intr_dp_is_en(intr_handle))
5478                 return;
5479
5480         if (rte_intr_allow_others(intr_handle)) {
5481                 vec = base = E1000_RX_VEC_START;
5482                 misc_shift = 1;
5483         }
5484
5485         /* set interrupt vector for other causes */
5486         if (hw->mac.type == e1000_82575) {
5487                 tmpval = E1000_READ_REG(hw, E1000_CTRL_EXT);
5488                 /* enable MSI-X PBA support */
5489                 tmpval |= E1000_CTRL_EXT_PBA_CLR;
5490
5491                 /* Auto-Mask interrupts upon ICR read */
5492                 tmpval |= E1000_CTRL_EXT_EIAME;
5493                 tmpval |= E1000_CTRL_EXT_IRCA;
5494
5495                 E1000_WRITE_REG(hw, E1000_CTRL_EXT, tmpval);
5496
5497                 /* enable msix_other interrupt */
5498                 E1000_WRITE_REG_ARRAY(hw, E1000_MSIXBM(0), 0, E1000_EIMS_OTHER);
5499                 regval = E1000_READ_REG(hw, E1000_EIAC);
5500                 E1000_WRITE_REG(hw, E1000_EIAC, regval | E1000_EIMS_OTHER);
5501                 regval = E1000_READ_REG(hw, E1000_EIAM);
5502                 E1000_WRITE_REG(hw, E1000_EIMS, regval | E1000_EIMS_OTHER);
5503         } else if ((hw->mac.type == e1000_82576) ||
5504                         (hw->mac.type == e1000_82580) ||
5505                         (hw->mac.type == e1000_i350) ||
5506                         (hw->mac.type == e1000_i354) ||
5507                         (hw->mac.type == e1000_i210) ||
5508                         (hw->mac.type == e1000_i211)) {
5509                 /* turn on MSI-X capability first */
5510                 E1000_WRITE_REG(hw, E1000_GPIE, E1000_GPIE_MSIX_MODE |
5511                                         E1000_GPIE_PBA | E1000_GPIE_EIAME |
5512                                         E1000_GPIE_NSICR);
5513                 intr_mask = RTE_LEN2MASK(intr_handle->nb_efd, uint32_t) <<
5514                         misc_shift;
5515                 regval = E1000_READ_REG(hw, E1000_EIAC);
5516                 E1000_WRITE_REG(hw, E1000_EIAC, regval | intr_mask);
5517
5518                 /* enable msix_other interrupt */
5519                 regval = E1000_READ_REG(hw, E1000_EIMS);
5520                 E1000_WRITE_REG(hw, E1000_EIMS, regval | intr_mask);
5521                 tmpval = (dev->data->nb_rx_queues | E1000_IVAR_VALID) << 8;
5522                 E1000_WRITE_REG(hw, E1000_IVAR_MISC, tmpval);
5523         }
5524
5525         /* use EIAM to auto-mask when MSI-X interrupt
5526          * is asserted, this saves a register write for every interrupt
5527          */
5528         intr_mask = RTE_LEN2MASK(intr_handle->nb_efd, uint32_t) <<
5529                 misc_shift;
5530         regval = E1000_READ_REG(hw, E1000_EIAM);
5531         E1000_WRITE_REG(hw, E1000_EIAM, regval | intr_mask);
5532
5533         for (queue_id = 0; queue_id < dev->data->nb_rx_queues; queue_id++) {
5534                 eth_igb_assign_msix_vector(hw, 0, queue_id, vec);
5535                 intr_handle->intr_vec[queue_id] = vec;
5536                 if (vec < base + intr_handle->nb_efd - 1)
5537                         vec++;
5538         }
5539
5540         E1000_WRITE_FLUSH(hw);
5541 }
5542
5543 /* restore n-tuple filter */
5544 static inline void
5545 igb_ntuple_filter_restore(struct rte_eth_dev *dev)
5546 {
5547         struct e1000_filter_info *filter_info =
5548                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5549         struct e1000_5tuple_filter *p_5tuple;
5550         struct e1000_2tuple_filter *p_2tuple;
5551
5552         TAILQ_FOREACH(p_5tuple, &filter_info->fivetuple_list, entries) {
5553                 igb_inject_5tuple_filter_82576(dev, p_5tuple);
5554         }
5555
5556         TAILQ_FOREACH(p_2tuple, &filter_info->twotuple_list, entries) {
5557                 igb_inject_2uple_filter(dev, p_2tuple);
5558         }
5559 }
5560
5561 /* restore SYN filter */
5562 static inline void
5563 igb_syn_filter_restore(struct rte_eth_dev *dev)
5564 {
5565         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5566         struct e1000_filter_info *filter_info =
5567                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5568         uint32_t synqf;
5569
5570         synqf = filter_info->syn_info;
5571
5572         if (synqf & E1000_SYN_FILTER_ENABLE) {
5573                 E1000_WRITE_REG(hw, E1000_SYNQF(0), synqf);
5574                 E1000_WRITE_FLUSH(hw);
5575         }
5576 }
5577
5578 /* restore ethernet type filter */
5579 static inline void
5580 igb_ethertype_filter_restore(struct rte_eth_dev *dev)
5581 {
5582         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5583         struct e1000_filter_info *filter_info =
5584                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5585         int i;
5586
5587         for (i = 0; i < E1000_MAX_ETQF_FILTERS; i++) {
5588                 if (filter_info->ethertype_mask & (1 << i)) {
5589                         E1000_WRITE_REG(hw, E1000_ETQF(i),
5590                                 filter_info->ethertype_filters[i].etqf);
5591                         E1000_WRITE_FLUSH(hw);
5592                 }
5593         }
5594 }
5595
5596 /* restore flex byte filter */
5597 static inline void
5598 igb_flex_filter_restore(struct rte_eth_dev *dev)
5599 {
5600         struct e1000_filter_info *filter_info =
5601                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5602         struct e1000_flex_filter *flex_filter;
5603
5604         TAILQ_FOREACH(flex_filter, &filter_info->flex_list, entries) {
5605                 igb_inject_flex_filter(dev, flex_filter);
5606         }
5607 }
5608
5609 /* restore all types filter */
5610 static int
5611 igb_filter_restore(struct rte_eth_dev *dev)
5612 {
5613         igb_ntuple_filter_restore(dev);
5614         igb_ethertype_filter_restore(dev);
5615         igb_syn_filter_restore(dev);
5616         igb_flex_filter_restore(dev);
5617
5618         return 0;
5619 }
5620
5621 RTE_PMD_REGISTER_PCI(net_e1000_igb, rte_igb_pmd);
5622 RTE_PMD_REGISTER_PCI_TABLE(net_e1000_igb, pci_id_igb_map);
5623 RTE_PMD_REGISTER_KMOD_DEP(net_e1000_igb, "* igb_uio | uio_pci_generic | vfio-pci");
5624 RTE_PMD_REGISTER_PCI(net_e1000_igb_vf, rte_igbvf_pmd);
5625 RTE_PMD_REGISTER_PCI_TABLE(net_e1000_igb_vf, pci_id_igbvf_map);
5626 RTE_PMD_REGISTER_KMOD_DEP(net_e1000_igb_vf, "* igb_uio | vfio-pci");