drivers/net/e1000/igb_ethdev.c

   1 /*-
   2  *   BSD LICENSE
   3  *
   4  *   Copyright(c) 2010-2016 Intel Corporation. All rights reserved.
   5  *   All rights reserved.
   6  *
   7  *   Redistribution and use in source and binary forms, with or without
   8  *   modification, are permitted provided that the following conditions
   9  *   are met:
  10  *
  11  *     * Redistributions of source code must retain the above copyright
  12  *       notice, this list of conditions and the following disclaimer.
  13  *     * Redistributions in binary form must reproduce the above copyright
  14  *       notice, this list of conditions and the following disclaimer in
  15  *       the documentation and/or other materials provided with the
  16  *       distribution.
  17  *     * Neither the name of Intel Corporation nor the names of its
  18  *       contributors may be used to endorse or promote products derived
  19  *       from this software without specific prior written permission.
  20  *
  21  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 #include <sys/queue.h>
  35 #include <stdio.h>
  36 #include <errno.h>
  37 #include <stdint.h>
  38 #include <stdarg.h>
  39
  40 #include <rte_common.h>
  41 #include <rte_interrupts.h>
  42 #include <rte_byteorder.h>
  43 #include <rte_log.h>
  44 #include <rte_debug.h>
  45 #include <rte_pci.h>
  46 #include <rte_bus_pci.h>
  47 #include <rte_ether.h>
  48 #include <rte_ethdev.h>
  49 #include <rte_ethdev_pci.h>
  50 #include <rte_memory.h>
  51 #include <rte_eal.h>
  52 #include <rte_atomic.h>
  53 #include <rte_malloc.h>
  54 #include <rte_dev.h>
  55
  56 #include "e1000_logs.h"
  57 #include "base/e1000_api.h"
  58 #include "e1000_ethdev.h"
  59 #include "igb_regs.h"
  60
  61 /*
  62  * Default values for port configuration
  63  */
  64 #define IGB_DEFAULT_RX_FREE_THRESH  32
  65
  66 #define IGB_DEFAULT_RX_PTHRESH      ((hw->mac.type == e1000_i354) ? 12 : 8)
  67 #define IGB_DEFAULT_RX_HTHRESH      8
  68 #define IGB_DEFAULT_RX_WTHRESH      ((hw->mac.type == e1000_82576) ? 1 : 4)
  69
  70 #define IGB_DEFAULT_TX_PTHRESH      ((hw->mac.type == e1000_i354) ? 20 : 8)
  71 #define IGB_DEFAULT_TX_HTHRESH      1
  72 #define IGB_DEFAULT_TX_WTHRESH      ((hw->mac.type == e1000_82576) ? 1 : 16)
  73
  74 #define IGB_HKEY_MAX_INDEX 10
  75
  76 /* Bit shift and mask */
  77 #define IGB_4_BIT_WIDTH  (CHAR_BIT / 2)
  78 #define IGB_4_BIT_MASK   RTE_LEN2MASK(IGB_4_BIT_WIDTH, uint8_t)
  79 #define IGB_8_BIT_WIDTH  CHAR_BIT
  80 #define IGB_8_BIT_MASK   UINT8_MAX
  81
  82 /* Additional timesync values. */
  83 #define E1000_CYCLECOUNTER_MASK      0xffffffffffffffffULL
  84 #define E1000_ETQF_FILTER_1588       3
  85 #define IGB_82576_TSYNC_SHIFT        16
  86 #define E1000_INCPERIOD_82576        (1 << E1000_TIMINCA_16NS_SHIFT)
  87 #define E1000_INCVALUE_82576         (16 << IGB_82576_TSYNC_SHIFT)
  88 #define E1000_TSAUXC_DISABLE_SYSTIME 0x80000000
  89
  90 #define E1000_VTIVAR_MISC                0x01740
  91 #define E1000_VTIVAR_MISC_MASK           0xFF
  92 #define E1000_VTIVAR_VALID               0x80
  93 #define E1000_VTIVAR_MISC_MAILBOX        0
  94 #define E1000_VTIVAR_MISC_INTR_MASK      0x3
  95
  96 /* External VLAN Enable bit mask */
  97 #define E1000_CTRL_EXT_EXT_VLAN      (1 << 26)
  98
  99 /* External VLAN Ether Type bit mask and shift */
 100 #define E1000_VET_VET_EXT            0xFFFF0000
 101 #define E1000_VET_VET_EXT_SHIFT      16
 102
 103 static int  eth_igb_configure(struct rte_eth_dev *dev);
 104 static int  eth_igb_start(struct rte_eth_dev *dev);
 105 static void eth_igb_stop(struct rte_eth_dev *dev);
 106 static int  eth_igb_dev_set_link_up(struct rte_eth_dev *dev);
 107 static int  eth_igb_dev_set_link_down(struct rte_eth_dev *dev);
 108 static void eth_igb_close(struct rte_eth_dev *dev);
 109 static void eth_igb_promiscuous_enable(struct rte_eth_dev *dev);
 110 static void eth_igb_promiscuous_disable(struct rte_eth_dev *dev);
 111 static void eth_igb_allmulticast_enable(struct rte_eth_dev *dev);
 112 static void eth_igb_allmulticast_disable(struct rte_eth_dev *dev);
 113 static int  eth_igb_link_update(struct rte_eth_dev *dev,
 114                                 int wait_to_complete);
 115 static int eth_igb_stats_get(struct rte_eth_dev *dev,
 116                                 struct rte_eth_stats *rte_stats);
 117 static int eth_igb_xstats_get(struct rte_eth_dev *dev,
 118                               struct rte_eth_xstat *xstats, unsigned n);
 119 static int eth_igb_xstats_get_by_id(struct rte_eth_dev *dev,
 120                 const uint64_t *ids,
 121                 uint64_t *values, unsigned int n);
 122 static int eth_igb_xstats_get_names(struct rte_eth_dev *dev,
 123                                     struct rte_eth_xstat_name *xstats_names,
 124                                     unsigned int size);
 125 static int eth_igb_xstats_get_names_by_id(struct rte_eth_dev *dev,
 126                 struct rte_eth_xstat_name *xstats_names, const uint64_t *ids,
 127                 unsigned int limit);
 128 static void eth_igb_stats_reset(struct rte_eth_dev *dev);
 129 static void eth_igb_xstats_reset(struct rte_eth_dev *dev);
 130 static int eth_igb_fw_version_get(struct rte_eth_dev *dev,
 131                                    char *fw_version, size_t fw_size);
 132 static void eth_igb_infos_get(struct rte_eth_dev *dev,
 133                               struct rte_eth_dev_info *dev_info);
 134 static const uint32_t *eth_igb_supported_ptypes_get(struct rte_eth_dev *dev);
 135 static void eth_igbvf_infos_get(struct rte_eth_dev *dev,
 136                                 struct rte_eth_dev_info *dev_info);
 137 static int  eth_igb_flow_ctrl_get(struct rte_eth_dev *dev,
 138                                 struct rte_eth_fc_conf *fc_conf);
 139 static int  eth_igb_flow_ctrl_set(struct rte_eth_dev *dev,
 140                                 struct rte_eth_fc_conf *fc_conf);
 141 static int eth_igb_lsc_interrupt_setup(struct rte_eth_dev *dev, uint8_t on);
 142 static int eth_igb_rxq_interrupt_setup(struct rte_eth_dev *dev);
 143 static int eth_igb_interrupt_get_status(struct rte_eth_dev *dev);
 144 static int eth_igb_interrupt_action(struct rte_eth_dev *dev,
 145                                     struct rte_intr_handle *handle);
 146 static void eth_igb_interrupt_handler(void *param);
 147 static int  igb_hardware_init(struct e1000_hw *hw);
 148 static void igb_hw_control_acquire(struct e1000_hw *hw);
 149 static void igb_hw_control_release(struct e1000_hw *hw);
 150 static void igb_init_manageability(struct e1000_hw *hw);
 151 static void igb_release_manageability(struct e1000_hw *hw);
 152
 153 static int  eth_igb_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
 154
 155 static int eth_igb_vlan_filter_set(struct rte_eth_dev *dev,
 156                 uint16_t vlan_id, int on);
 157 static int eth_igb_vlan_tpid_set(struct rte_eth_dev *dev,
 158                                  enum rte_vlan_type vlan_type,
 159                                  uint16_t tpid_id);
 160 static int eth_igb_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 161
 162 static void igb_vlan_hw_filter_enable(struct rte_eth_dev *dev);
 163 static void igb_vlan_hw_filter_disable(struct rte_eth_dev *dev);
 164 static void igb_vlan_hw_strip_enable(struct rte_eth_dev *dev);
 165 static void igb_vlan_hw_strip_disable(struct rte_eth_dev *dev);
 166 static void igb_vlan_hw_extend_enable(struct rte_eth_dev *dev);
 167 static void igb_vlan_hw_extend_disable(struct rte_eth_dev *dev);
 168
 169 static int eth_igb_led_on(struct rte_eth_dev *dev);
 170 static int eth_igb_led_off(struct rte_eth_dev *dev);
 171
 172 static void igb_intr_disable(struct e1000_hw *hw);
 173 static int  igb_get_rx_buffer_size(struct e1000_hw *hw);
 174 static int eth_igb_rar_set(struct rte_eth_dev *dev,
 175                            struct ether_addr *mac_addr,
 176                            uint32_t index, uint32_t pool);
 177 static void eth_igb_rar_clear(struct rte_eth_dev *dev, uint32_t index);
 178 static void eth_igb_default_mac_addr_set(struct rte_eth_dev *dev,
 179                 struct ether_addr *addr);
 180
 181 static void igbvf_intr_disable(struct e1000_hw *hw);
 182 static int igbvf_dev_configure(struct rte_eth_dev *dev);
 183 static int igbvf_dev_start(struct rte_eth_dev *dev);
 184 static void igbvf_dev_stop(struct rte_eth_dev *dev);
 185 static void igbvf_dev_close(struct rte_eth_dev *dev);
 186 static void igbvf_promiscuous_enable(struct rte_eth_dev *dev);
 187 static void igbvf_promiscuous_disable(struct rte_eth_dev *dev);
 188 static void igbvf_allmulticast_enable(struct rte_eth_dev *dev);
 189 static void igbvf_allmulticast_disable(struct rte_eth_dev *dev);
 190 static int eth_igbvf_link_update(struct e1000_hw *hw);
 191 static int eth_igbvf_stats_get(struct rte_eth_dev *dev,
 192                                 struct rte_eth_stats *rte_stats);
 193 static int eth_igbvf_xstats_get(struct rte_eth_dev *dev,
 194                                 struct rte_eth_xstat *xstats, unsigned n);
 195 static int eth_igbvf_xstats_get_names(struct rte_eth_dev *dev,
 196                                       struct rte_eth_xstat_name *xstats_names,
 197                                       unsigned limit);
 198 static void eth_igbvf_stats_reset(struct rte_eth_dev *dev);
 199 static int igbvf_vlan_filter_set(struct rte_eth_dev *dev,
 200                 uint16_t vlan_id, int on);
 201 static int igbvf_set_vfta(struct e1000_hw *hw, uint16_t vid, bool on);
 202 static void igbvf_set_vfta_all(struct rte_eth_dev *dev, bool on);
 203 static void igbvf_default_mac_addr_set(struct rte_eth_dev *dev,
 204                 struct ether_addr *addr);
 205 static int igbvf_get_reg_length(struct rte_eth_dev *dev);
 206 static int igbvf_get_regs(struct rte_eth_dev *dev,
 207                 struct rte_dev_reg_info *regs);
 208
 209 static int eth_igb_rss_reta_update(struct rte_eth_dev *dev,
 210                                    struct rte_eth_rss_reta_entry64 *reta_conf,
 211                                    uint16_t reta_size);
 212 static int eth_igb_rss_reta_query(struct rte_eth_dev *dev,
 213                                   struct rte_eth_rss_reta_entry64 *reta_conf,
 214                                   uint16_t reta_size);
 215
 216 static int eth_igb_syn_filter_get(struct rte_eth_dev *dev,
 217                         struct rte_eth_syn_filter *filter);
 218 static int eth_igb_syn_filter_handle(struct rte_eth_dev *dev,
 219                         enum rte_filter_op filter_op,
 220                         void *arg);
 221 static int igb_add_2tuple_filter(struct rte_eth_dev *dev,
 222                         struct rte_eth_ntuple_filter *ntuple_filter);
 223 static int igb_remove_2tuple_filter(struct rte_eth_dev *dev,
 224                         struct rte_eth_ntuple_filter *ntuple_filter);
 225 static int eth_igb_get_flex_filter(struct rte_eth_dev *dev,
 226                         struct rte_eth_flex_filter *filter);
 227 static int eth_igb_flex_filter_handle(struct rte_eth_dev *dev,
 228                         enum rte_filter_op filter_op,
 229                         void *arg);
 230 static int igb_add_5tuple_filter_82576(struct rte_eth_dev *dev,
 231                         struct rte_eth_ntuple_filter *ntuple_filter);
 232 static int igb_remove_5tuple_filter_82576(struct rte_eth_dev *dev,
 233                         struct rte_eth_ntuple_filter *ntuple_filter);
 234 static int igb_get_ntuple_filter(struct rte_eth_dev *dev,
 235                         struct rte_eth_ntuple_filter *filter);
 236 static int igb_ntuple_filter_handle(struct rte_eth_dev *dev,
 237                                 enum rte_filter_op filter_op,
 238                                 void *arg);
 239 static int igb_ethertype_filter_handle(struct rte_eth_dev *dev,
 240                                 enum rte_filter_op filter_op,
 241                                 void *arg);
 242 static int igb_get_ethertype_filter(struct rte_eth_dev *dev,
 243                         struct rte_eth_ethertype_filter *filter);
 244 static int eth_igb_filter_ctrl(struct rte_eth_dev *dev,
 245                      enum rte_filter_type filter_type,
 246                      enum rte_filter_op filter_op,
 247                      void *arg);
 248 static int eth_igb_get_reg_length(struct rte_eth_dev *dev);
 249 static int eth_igb_get_regs(struct rte_eth_dev *dev,
 250                 struct rte_dev_reg_info *regs);
 251 static int eth_igb_get_eeprom_length(struct rte_eth_dev *dev);
 252 static int eth_igb_get_eeprom(struct rte_eth_dev *dev,
 253                 struct rte_dev_eeprom_info *eeprom);
 254 static int eth_igb_set_eeprom(struct rte_eth_dev *dev,
 255                 struct rte_dev_eeprom_info *eeprom);
 256 static int eth_igb_set_mc_addr_list(struct rte_eth_dev *dev,
 257                                     struct ether_addr *mc_addr_set,
 258                                     uint32_t nb_mc_addr);
 259 static int igb_timesync_enable(struct rte_eth_dev *dev);
 260 static int igb_timesync_disable(struct rte_eth_dev *dev);
 261 static int igb_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
 262                                           struct timespec *timestamp,
 263                                           uint32_t flags);
 264 static int igb_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
 265                                           struct timespec *timestamp);
 266 static int igb_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);
 267 static int igb_timesync_read_time(struct rte_eth_dev *dev,
 268                                   struct timespec *timestamp);
 269 static int igb_timesync_write_time(struct rte_eth_dev *dev,
 270                                    const struct timespec *timestamp);
 271 static int eth_igb_rx_queue_intr_enable(struct rte_eth_dev *dev,
 272                                         uint16_t queue_id);
 273 static int eth_igb_rx_queue_intr_disable(struct rte_eth_dev *dev,
 274                                          uint16_t queue_id);
 275 static void eth_igb_assign_msix_vector(struct e1000_hw *hw, int8_t direction,
 276                                        uint8_t queue, uint8_t msix_vector);
 277 static void eth_igb_write_ivar(struct e1000_hw *hw, uint8_t msix_vector,
 278                                uint8_t index, uint8_t offset);
 279 static void eth_igb_configure_msix_intr(struct rte_eth_dev *dev);
 280 static void eth_igbvf_interrupt_handler(void *param);
 281 static void igbvf_mbx_process(struct rte_eth_dev *dev);
 282 static int igb_filter_restore(struct rte_eth_dev *dev);
 283
 284 /*
 285  * Define VF Stats MACRO for Non "cleared on read" register
 286  */
 287 #define UPDATE_VF_STAT(reg, last, cur)            \
 288 {                                                 \
 289         u32 latest = E1000_READ_REG(hw, reg);     \
 290         cur += (latest - last) & UINT_MAX;        \
 291         last = latest;                            \
 292 }
 293
 294 #define IGB_FC_PAUSE_TIME 0x0680
 295 #define IGB_LINK_UPDATE_CHECK_TIMEOUT  90  /* 9s */
 296 #define IGB_LINK_UPDATE_CHECK_INTERVAL 100 /* ms */
 297
 298 #define IGBVF_PMD_NAME "rte_igbvf_pmd"     /* PMD name */
 299
 300 static enum e1000_fc_mode igb_fc_setting = e1000_fc_full;
 301
 302 /*
 303  * The set of PCI devices this driver supports
 304  */
 305 static const struct rte_pci_id pci_id_igb_map[] = {
 306         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576) },
 307         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_FIBER) },
 308         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_SERDES) },
 309         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_QUAD_COPPER) },
 310         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_QUAD_COPPER_ET2) },
 311         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_NS) },
 312         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_NS_SERDES) },
 313         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_SERDES_QUAD) },
 314
 315         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82575EB_COPPER) },
 316         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82575EB_FIBER_SERDES) },
 317         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82575GB_QUAD_COPPER) },
 318
 319         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82580_COPPER) },
 320         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82580_FIBER) },
 321         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82580_SERDES) },
 322         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82580_SGMII) },
 323         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82580_COPPER_DUAL) },
 324         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82580_QUAD_FIBER) },
 325
 326         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_COPPER) },
 327         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_FIBER) },
 328         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_SERDES) },
 329         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_SGMII) },
 330         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_DA4) },
 331         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_COPPER) },
 332         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_COPPER_OEM1) },
 333         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_COPPER_IT) },
 334         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_FIBER) },
 335         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_SERDES) },
 336         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_SGMII) },
 337         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_COPPER_FLASHLESS) },
 338         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_SERDES_FLASHLESS) },
 339         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I211_COPPER) },
 340         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I354_BACKPLANE_1GBPS) },
 341         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I354_SGMII) },
 342         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I354_BACKPLANE_2_5GBPS) },
 343         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_DH89XXCC_SGMII) },
 344         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_DH89XXCC_SERDES) },
 345         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_DH89XXCC_BACKPLANE) },
 346         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_DH89XXCC_SFP) },
 347         { .vendor_id = 0, /* sentinel */ },
 348 };
 349
 350 /*
 351  * The set of PCI devices this driver supports (for 82576&I350 VF)
 352  */
 353 static const struct rte_pci_id pci_id_igbvf_map[] = {
 354         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_VF) },
 355         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_VF_HV) },
 356         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_VF) },
 357         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_VF_HV) },
 358         { .vendor_id = 0, /* sentinel */ },
 359 };
 360
 361 static const struct rte_eth_desc_lim rx_desc_lim = {
 362         .nb_max = E1000_MAX_RING_DESC,
 363         .nb_min = E1000_MIN_RING_DESC,
 364         .nb_align = IGB_RXD_ALIGN,
 365 };
 366
 367 static const struct rte_eth_desc_lim tx_desc_lim = {
 368         .nb_max = E1000_MAX_RING_DESC,
 369         .nb_min = E1000_MIN_RING_DESC,
 370         .nb_align = IGB_RXD_ALIGN,
 371         .nb_seg_max = IGB_TX_MAX_SEG,
 372         .nb_mtu_seg_max = IGB_TX_MAX_MTU_SEG,
 373 };
 374
 375 static const struct eth_dev_ops eth_igb_ops = {
 376         .dev_configure        = eth_igb_configure,
 377         .dev_start            = eth_igb_start,
 378         .dev_stop             = eth_igb_stop,
 379         .dev_set_link_up      = eth_igb_dev_set_link_up,
 380         .dev_set_link_down    = eth_igb_dev_set_link_down,
 381         .dev_close            = eth_igb_close,
 382         .promiscuous_enable   = eth_igb_promiscuous_enable,
 383         .promiscuous_disable  = eth_igb_promiscuous_disable,
 384         .allmulticast_enable  = eth_igb_allmulticast_enable,
 385         .allmulticast_disable = eth_igb_allmulticast_disable,
 386         .link_update          = eth_igb_link_update,
 387         .stats_get            = eth_igb_stats_get,
 388         .xstats_get           = eth_igb_xstats_get,
 389         .xstats_get_by_id     = eth_igb_xstats_get_by_id,
 390         .xstats_get_names_by_id = eth_igb_xstats_get_names_by_id,
 391         .xstats_get_names     = eth_igb_xstats_get_names,
 392         .stats_reset          = eth_igb_stats_reset,
 393         .xstats_reset         = eth_igb_xstats_reset,
 394         .fw_version_get       = eth_igb_fw_version_get,
 395         .dev_infos_get        = eth_igb_infos_get,
 396         .dev_supported_ptypes_get = eth_igb_supported_ptypes_get,
 397         .mtu_set              = eth_igb_mtu_set,
 398         .vlan_filter_set      = eth_igb_vlan_filter_set,
 399         .vlan_tpid_set        = eth_igb_vlan_tpid_set,
 400         .vlan_offload_set     = eth_igb_vlan_offload_set,
 401         .rx_queue_setup       = eth_igb_rx_queue_setup,
 402         .rx_queue_intr_enable = eth_igb_rx_queue_intr_enable,
 403         .rx_queue_intr_disable = eth_igb_rx_queue_intr_disable,
 404         .rx_queue_release     = eth_igb_rx_queue_release,
 405         .rx_queue_count       = eth_igb_rx_queue_count,
 406         .rx_descriptor_done   = eth_igb_rx_descriptor_done,
 407         .rx_descriptor_status = eth_igb_rx_descriptor_status,
 408         .tx_descriptor_status = eth_igb_tx_descriptor_status,
 409         .tx_queue_setup       = eth_igb_tx_queue_setup,
 410         .tx_queue_release     = eth_igb_tx_queue_release,
 411         .tx_done_cleanup      = eth_igb_tx_done_cleanup,
 412         .dev_led_on           = eth_igb_led_on,
 413         .dev_led_off          = eth_igb_led_off,
 414         .flow_ctrl_get        = eth_igb_flow_ctrl_get,
 415         .flow_ctrl_set        = eth_igb_flow_ctrl_set,
 416         .mac_addr_add         = eth_igb_rar_set,
 417         .mac_addr_remove      = eth_igb_rar_clear,
 418         .mac_addr_set         = eth_igb_default_mac_addr_set,
 419         .reta_update          = eth_igb_rss_reta_update,
 420         .reta_query           = eth_igb_rss_reta_query,
 421         .rss_hash_update      = eth_igb_rss_hash_update,
 422         .rss_hash_conf_get    = eth_igb_rss_hash_conf_get,
 423         .filter_ctrl          = eth_igb_filter_ctrl,
 424         .set_mc_addr_list     = eth_igb_set_mc_addr_list,
 425         .rxq_info_get         = igb_rxq_info_get,
 426         .txq_info_get         = igb_txq_info_get,
 427         .timesync_enable      = igb_timesync_enable,
 428         .timesync_disable     = igb_timesync_disable,
 429         .timesync_read_rx_timestamp = igb_timesync_read_rx_timestamp,
 430         .timesync_read_tx_timestamp = igb_timesync_read_tx_timestamp,
 431         .get_reg              = eth_igb_get_regs,
 432         .get_eeprom_length    = eth_igb_get_eeprom_length,
 433         .get_eeprom           = eth_igb_get_eeprom,
 434         .set_eeprom           = eth_igb_set_eeprom,
 435         .timesync_adjust_time = igb_timesync_adjust_time,
 436         .timesync_read_time   = igb_timesync_read_time,
 437         .timesync_write_time  = igb_timesync_write_time,
 438 };
 439
 440 /*
 441  * dev_ops for virtual function, bare necessities for basic vf
 442  * operation have been implemented
 443  */
 444 static const struct eth_dev_ops igbvf_eth_dev_ops = {
 445         .dev_configure        = igbvf_dev_configure,
 446         .dev_start            = igbvf_dev_start,
 447         .dev_stop             = igbvf_dev_stop,
 448         .dev_close            = igbvf_dev_close,
 449         .promiscuous_enable   = igbvf_promiscuous_enable,
 450         .promiscuous_disable  = igbvf_promiscuous_disable,
 451         .allmulticast_enable  = igbvf_allmulticast_enable,
 452         .allmulticast_disable = igbvf_allmulticast_disable,
 453         .link_update          = eth_igb_link_update,
 454         .stats_get            = eth_igbvf_stats_get,
 455         .xstats_get           = eth_igbvf_xstats_get,
 456         .xstats_get_names     = eth_igbvf_xstats_get_names,
 457         .stats_reset          = eth_igbvf_stats_reset,
 458         .xstats_reset         = eth_igbvf_stats_reset,
 459         .vlan_filter_set      = igbvf_vlan_filter_set,
 460         .dev_infos_get        = eth_igbvf_infos_get,
 461         .dev_supported_ptypes_get = eth_igb_supported_ptypes_get,
 462         .rx_queue_setup       = eth_igb_rx_queue_setup,
 463         .rx_queue_release     = eth_igb_rx_queue_release,
 464         .tx_queue_setup       = eth_igb_tx_queue_setup,
 465         .tx_queue_release     = eth_igb_tx_queue_release,
 466         .set_mc_addr_list     = eth_igb_set_mc_addr_list,
 467         .rxq_info_get         = igb_rxq_info_get,
 468         .txq_info_get         = igb_txq_info_get,
 469         .mac_addr_set         = igbvf_default_mac_addr_set,
 470         .get_reg              = igbvf_get_regs,
 471 };
 472
 473 /* store statistics names and its offset in stats structure */
 474 struct rte_igb_xstats_name_off {
 475         char name[RTE_ETH_XSTATS_NAME_SIZE];
 476         unsigned offset;
 477 };
 478
 479 static const struct rte_igb_xstats_name_off rte_igb_stats_strings[] = {
 480         {"rx_crc_errors", offsetof(struct e1000_hw_stats, crcerrs)},
 481         {"rx_align_errors", offsetof(struct e1000_hw_stats, algnerrc)},
 482         {"rx_symbol_errors", offsetof(struct e1000_hw_stats, symerrs)},
 483         {"rx_missed_packets", offsetof(struct e1000_hw_stats, mpc)},
 484         {"tx_single_collision_packets", offsetof(struct e1000_hw_stats, scc)},
 485         {"tx_multiple_collision_packets", offsetof(struct e1000_hw_stats, mcc)},
 486         {"tx_excessive_collision_packets", offsetof(struct e1000_hw_stats,
 487                 ecol)},
 488         {"tx_late_collisions", offsetof(struct e1000_hw_stats, latecol)},
 489         {"tx_total_collisions", offsetof(struct e1000_hw_stats, colc)},
 490         {"tx_deferred_packets", offsetof(struct e1000_hw_stats, dc)},
 491         {"tx_no_carrier_sense_packets", offsetof(struct e1000_hw_stats, tncrs)},
 492         {"rx_carrier_ext_errors", offsetof(struct e1000_hw_stats, cexterr)},
 493         {"rx_length_errors", offsetof(struct e1000_hw_stats, rlec)},
 494         {"rx_xon_packets", offsetof(struct e1000_hw_stats, xonrxc)},
 495         {"tx_xon_packets", offsetof(struct e1000_hw_stats, xontxc)},
 496         {"rx_xoff_packets", offsetof(struct e1000_hw_stats, xoffrxc)},
 497         {"tx_xoff_packets", offsetof(struct e1000_hw_stats, xofftxc)},
 498         {"rx_flow_control_unsupported_packets", offsetof(struct e1000_hw_stats,
 499                 fcruc)},
 500         {"rx_size_64_packets", offsetof(struct e1000_hw_stats, prc64)},
 501         {"rx_size_65_to_127_packets", offsetof(struct e1000_hw_stats, prc127)},
 502         {"rx_size_128_to_255_packets", offsetof(struct e1000_hw_stats, prc255)},
 503         {"rx_size_256_to_511_packets", offsetof(struct e1000_hw_stats, prc511)},
 504         {"rx_size_512_to_1023_packets", offsetof(struct e1000_hw_stats,
 505                 prc1023)},
 506         {"rx_size_1024_to_max_packets", offsetof(struct e1000_hw_stats,
 507                 prc1522)},
 508         {"rx_broadcast_packets", offsetof(struct e1000_hw_stats, bprc)},
 509         {"rx_multicast_packets", offsetof(struct e1000_hw_stats, mprc)},
 510         {"rx_undersize_errors", offsetof(struct e1000_hw_stats, ruc)},
 511         {"rx_fragment_errors", offsetof(struct e1000_hw_stats, rfc)},
 512         {"rx_oversize_errors", offsetof(struct e1000_hw_stats, roc)},
 513         {"rx_jabber_errors", offsetof(struct e1000_hw_stats, rjc)},
 514         {"rx_management_packets", offsetof(struct e1000_hw_stats, mgprc)},
 515         {"rx_management_dropped", offsetof(struct e1000_hw_stats, mgpdc)},
 516         {"tx_management_packets", offsetof(struct e1000_hw_stats, mgptc)},
 517         {"rx_total_packets", offsetof(struct e1000_hw_stats, tpr)},
 518         {"tx_total_packets", offsetof(struct e1000_hw_stats, tpt)},
 519         {"rx_total_bytes", offsetof(struct e1000_hw_stats, tor)},
 520         {"tx_total_bytes", offsetof(struct e1000_hw_stats, tot)},
 521         {"tx_size_64_packets", offsetof(struct e1000_hw_stats, ptc64)},
 522         {"tx_size_65_to_127_packets", offsetof(struct e1000_hw_stats, ptc127)},
 523         {"tx_size_128_to_255_packets", offsetof(struct e1000_hw_stats, ptc255)},
 524         {"tx_size_256_to_511_packets", offsetof(struct e1000_hw_stats, ptc511)},
 525         {"tx_size_512_to_1023_packets", offsetof(struct e1000_hw_stats,
 526                 ptc1023)},
 527         {"tx_size_1023_to_max_packets", offsetof(struct e1000_hw_stats,
 528                 ptc1522)},
 529         {"tx_multicast_packets", offsetof(struct e1000_hw_stats, mptc)},
 530         {"tx_broadcast_packets", offsetof(struct e1000_hw_stats, bptc)},
 531         {"tx_tso_packets", offsetof(struct e1000_hw_stats, tsctc)},
 532         {"tx_tso_errors", offsetof(struct e1000_hw_stats, tsctfc)},
 533         {"rx_sent_to_host_packets", offsetof(struct e1000_hw_stats, rpthc)},
 534         {"tx_sent_by_host_packets", offsetof(struct e1000_hw_stats, hgptc)},
 535         {"rx_code_violation_packets", offsetof(struct e1000_hw_stats, scvpc)},
 536
 537         {"interrupt_assert_count", offsetof(struct e1000_hw_stats, iac)},
 538 };
 539
 540 #define IGB_NB_XSTATS (sizeof(rte_igb_stats_strings) / \
 541                 sizeof(rte_igb_stats_strings[0]))
 542
 543 static const struct rte_igb_xstats_name_off rte_igbvf_stats_strings[] = {
 544         {"rx_multicast_packets", offsetof(struct e1000_vf_stats, mprc)},
 545         {"rx_good_loopback_packets", offsetof(struct e1000_vf_stats, gprlbc)},
 546         {"tx_good_loopback_packets", offsetof(struct e1000_vf_stats, gptlbc)},
 547         {"rx_good_loopback_bytes", offsetof(struct e1000_vf_stats, gorlbc)},
 548         {"tx_good_loopback_bytes", offsetof(struct e1000_vf_stats, gotlbc)},
 549 };
 550
 551 #define IGBVF_NB_XSTATS (sizeof(rte_igbvf_stats_strings) / \
 552                 sizeof(rte_igbvf_stats_strings[0]))
 553
 554 /**
 555  * Atomically reads the link status information from global
 556  * structure rte_eth_dev.
 557  *
 558  * @param dev
 559  *   - Pointer to the structure rte_eth_dev to read from.
 560  *   - Pointer to the buffer to be saved with the link status.
 561  *
 562  * @return
 563  *   - On success, zero.
 564  *   - On failure, negative value.
 565  */
 566 static inline int
 567 rte_igb_dev_atomic_read_link_status(struct rte_eth_dev *dev,
 568                                 struct rte_eth_link *link)
 569 {
 570         struct rte_eth_link *dst = link;
 571         struct rte_eth_link *src = &(dev->data->dev_link);
 572
 573         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 574                                         *(uint64_t *)src) == 0)
 575                 return -1;
 576
 577         return 0;
 578 }
 579
 580 /**
 581  * Atomically writes the link status information into global
 582  * structure rte_eth_dev.
 583  *
 584  * @param dev
 585  *   - Pointer to the structure rte_eth_dev to read from.
 586  *   - Pointer to the buffer to be saved with the link status.
 587  *
 588  * @return
 589  *   - On success, zero.
 590  *   - On failure, negative value.
 591  */
 592 static inline int
 593 rte_igb_dev_atomic_write_link_status(struct rte_eth_dev *dev,
 594                                 struct rte_eth_link *link)
 595 {
 596         struct rte_eth_link *dst = &(dev->data->dev_link);
 597         struct rte_eth_link *src = link;
 598
 599         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 600                                         *(uint64_t *)src) == 0)
 601                 return -1;
 602
 603         return 0;
 604 }
 605
 606 static inline void
 607 igb_intr_enable(struct rte_eth_dev *dev)
 608 {
 609         struct e1000_interrupt *intr =
 610                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
 611         struct e1000_hw *hw =
 612                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 613
 614         E1000_WRITE_REG(hw, E1000_IMS, intr->mask);
 615         E1000_WRITE_FLUSH(hw);
 616 }
 617
 618 static void
 619 igb_intr_disable(struct e1000_hw *hw)
 620 {
 621         E1000_WRITE_REG(hw, E1000_IMC, ~0);
 622         E1000_WRITE_FLUSH(hw);
 623 }
 624
 625 static inline void
 626 igbvf_intr_enable(struct rte_eth_dev *dev)
 627 {
 628         struct e1000_hw *hw =
 629                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 630
 631         /* only for mailbox */
 632         E1000_WRITE_REG(hw, E1000_EIAM, 1 << E1000_VTIVAR_MISC_MAILBOX);
 633         E1000_WRITE_REG(hw, E1000_EIAC, 1 << E1000_VTIVAR_MISC_MAILBOX);
 634         E1000_WRITE_REG(hw, E1000_EIMS, 1 << E1000_VTIVAR_MISC_MAILBOX);
 635         E1000_WRITE_FLUSH(hw);
 636 }
 637
 638 /* only for mailbox now. If RX/TX needed, should extend this function.  */
 639 static void
 640 igbvf_set_ivar_map(struct e1000_hw *hw, uint8_t msix_vector)
 641 {
 642         uint32_t tmp = 0;
 643
 644         /* mailbox */
 645         tmp |= (msix_vector & E1000_VTIVAR_MISC_INTR_MASK);
 646         tmp |= E1000_VTIVAR_VALID;
 647         E1000_WRITE_REG(hw, E1000_VTIVAR_MISC, tmp);
 648 }
 649
 650 static void
 651 eth_igbvf_configure_msix_intr(struct rte_eth_dev *dev)
 652 {
 653         struct e1000_hw *hw =
 654                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 655
 656         /* Configure VF other cause ivar */
 657         igbvf_set_ivar_map(hw, E1000_VTIVAR_MISC_MAILBOX);
 658 }
 659
 660 static inline int32_t
 661 igb_pf_reset_hw(struct e1000_hw *hw)
 662 {
 663         uint32_t ctrl_ext;
 664         int32_t status;
 665
 666         status = e1000_reset_hw(hw);
 667
 668         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
 669         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
 670         ctrl_ext |= E1000_CTRL_EXT_PFRSTD;
 671         E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
 672         E1000_WRITE_FLUSH(hw);
 673
 674         return status;
 675 }
 676
 677 static void
 678 igb_identify_hardware(struct rte_eth_dev *dev, struct rte_pci_device *pci_dev)
 679 {
 680         struct e1000_hw *hw =
 681                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 682
 683
 684         hw->vendor_id = pci_dev->id.vendor_id;
 685         hw->device_id = pci_dev->id.device_id;
 686         hw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
 687         hw->subsystem_device_id = pci_dev->id.subsystem_device_id;
 688
 689         e1000_set_mac_type(hw);
 690
 691         /* need to check if it is a vf device below */
 692 }
 693
 694 static int
 695 igb_reset_swfw_lock(struct e1000_hw *hw)
 696 {
 697         int ret_val;
 698
 699         /*
 700          * Do mac ops initialization manually here, since we will need
 701          * some function pointers set by this call.
 702          */
 703         ret_val = e1000_init_mac_params(hw);
 704         if (ret_val)
 705                 return ret_val;
 706
 707         /*
 708          * SMBI lock should not fail in this early stage. If this is the case,
 709          * it is due to an improper exit of the application.
 710          * So force the release of the faulty lock.
 711          */
 712         if (e1000_get_hw_semaphore_generic(hw) < 0) {
 713                 PMD_DRV_LOG(DEBUG, "SMBI lock released");
 714         }
 715         e1000_put_hw_semaphore_generic(hw);
 716
 717         if (hw->mac.ops.acquire_swfw_sync != NULL) {
 718                 uint16_t mask;
 719
 720                 /*
 721                  * Phy lock should not fail in this early stage. If this is the case,
 722                  * it is due to an improper exit of the application.
 723                  * So force the release of the faulty lock.
 724                  */
 725                 mask = E1000_SWFW_PHY0_SM << hw->bus.func;
 726                 if (hw->bus.func > E1000_FUNC_1)
 727                         mask <<= 2;
 728                 if (hw->mac.ops.acquire_swfw_sync(hw, mask) < 0) {
 729                         PMD_DRV_LOG(DEBUG, "SWFW phy%d lock released",
 730                                     hw->bus.func);
 731                 }
 732                 hw->mac.ops.release_swfw_sync(hw, mask);
 733
 734                 /*
 735                  * This one is more tricky since it is common to all ports; but
 736                  * swfw_sync retries last long enough (1s) to be almost sure that if
 737                  * lock can not be taken it is due to an improper lock of the
 738                  * semaphore.
 739                  */
 740                 mask = E1000_SWFW_EEP_SM;
 741                 if (hw->mac.ops.acquire_swfw_sync(hw, mask) < 0) {
 742                         PMD_DRV_LOG(DEBUG, "SWFW common locks released");
 743                 }
 744                 hw->mac.ops.release_swfw_sync(hw, mask);
 745         }
 746
 747         return E1000_SUCCESS;
 748 }
 749
 750 /* Remove all ntuple filters of the device */
 751 static int igb_ntuple_filter_uninit(struct rte_eth_dev *eth_dev)
 752 {
 753         struct e1000_filter_info *filter_info =
 754                 E1000_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
 755         struct e1000_5tuple_filter *p_5tuple;
 756         struct e1000_2tuple_filter *p_2tuple;
 757
 758         while ((p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list))) {
 759                 TAILQ_REMOVE(&filter_info->fivetuple_list,
 760                         p_5tuple, entries);
 761                         rte_free(p_5tuple);
 762         }
 763         filter_info->fivetuple_mask = 0;
 764         while ((p_2tuple = TAILQ_FIRST(&filter_info->twotuple_list))) {
 765                 TAILQ_REMOVE(&filter_info->twotuple_list,
 766                         p_2tuple, entries);
 767                         rte_free(p_2tuple);
 768         }
 769         filter_info->twotuple_mask = 0;
 770
 771         return 0;
 772 }
 773
 774 /* Remove all flex filters of the device */
 775 static int igb_flex_filter_uninit(struct rte_eth_dev *eth_dev)
 776 {
 777         struct e1000_filter_info *filter_info =
 778                 E1000_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
 779         struct e1000_flex_filter *p_flex;
 780
 781         while ((p_flex = TAILQ_FIRST(&filter_info->flex_list))) {
 782                 TAILQ_REMOVE(&filter_info->flex_list, p_flex, entries);
 783                 rte_free(p_flex);
 784         }
 785         filter_info->flex_mask = 0;
 786
 787         return 0;
 788 }
 789
 790 static int
 791 eth_igb_dev_init(struct rte_eth_dev *eth_dev)
 792 {
 793         int error = 0;
 794         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
 795         struct e1000_hw *hw =
 796                 E1000_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 797         struct e1000_vfta * shadow_vfta =
 798                 E1000_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
 799         struct e1000_filter_info *filter_info =
 800                 E1000_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
 801         struct e1000_adapter *adapter =
 802                 E1000_DEV_PRIVATE(eth_dev->data->dev_private);
 803
 804         uint32_t ctrl_ext;
 805
 806         eth_dev->dev_ops = &eth_igb_ops;
 807         eth_dev->rx_pkt_burst = &eth_igb_recv_pkts;
 808         eth_dev->tx_pkt_burst = &eth_igb_xmit_pkts;
 809         eth_dev->tx_pkt_prepare = &eth_igb_prep_pkts;
 810
 811         /* for secondary processes, we don't initialise any further as primary
 812          * has already done this work. Only check we don't need a different
 813          * RX function */
 814         if (rte_eal_process_type() != RTE_PROC_PRIMARY){
 815                 if (eth_dev->data->scattered_rx)
 816                         eth_dev->rx_pkt_burst = &eth_igb_recv_scattered_pkts;
 817                 return 0;
 818         }
 819
 820         rte_eth_copy_pci_info(eth_dev, pci_dev);
 821
 822         hw->hw_addr= (void *)pci_dev->mem_resource[0].addr;
 823
 824         igb_identify_hardware(eth_dev, pci_dev);
 825         if (e1000_setup_init_funcs(hw, FALSE) != E1000_SUCCESS) {
 826                 error = -EIO;
 827                 goto err_late;
 828         }
 829
 830         e1000_get_bus_info(hw);
 831
 832         /* Reset any pending lock */
 833         if (igb_reset_swfw_lock(hw) != E1000_SUCCESS) {
 834                 error = -EIO;
 835                 goto err_late;
 836         }
 837
 838         /* Finish initialization */
 839         if (e1000_setup_init_funcs(hw, TRUE) != E1000_SUCCESS) {
 840                 error = -EIO;
 841                 goto err_late;
 842         }
 843
 844         hw->mac.autoneg = 1;
 845         hw->phy.autoneg_wait_to_complete = 0;
 846         hw->phy.autoneg_advertised = E1000_ALL_SPEED_DUPLEX;
 847
 848         /* Copper options */
 849         if (hw->phy.media_type == e1000_media_type_copper) {
 850                 hw->phy.mdix = 0; /* AUTO_ALL_MODES */
 851                 hw->phy.disable_polarity_correction = 0;
 852                 hw->phy.ms_type = e1000_ms_hw_default;
 853         }
 854
 855         /*
 856          * Start from a known state, this is important in reading the nvm
 857          * and mac from that.
 858          */
 859         igb_pf_reset_hw(hw);
 860
 861         /* Make sure we have a good EEPROM before we read from it */
 862         if (e1000_validate_nvm_checksum(hw) < 0) {
 863                 /*
 864                  * Some PCI-E parts fail the first check due to
 865                  * the link being in sleep state, call it again,
 866                  * if it fails a second time its a real issue.
 867                  */
 868                 if (e1000_validate_nvm_checksum(hw) < 0) {
 869                         PMD_INIT_LOG(ERR, "EEPROM checksum invalid");
 870                         error = -EIO;
 871                         goto err_late;
 872                 }
 873         }
 874
 875         /* Read the permanent MAC address out of the EEPROM */
 876         if (e1000_read_mac_addr(hw) != 0) {
 877                 PMD_INIT_LOG(ERR, "EEPROM error while reading MAC address");
 878                 error = -EIO;
 879                 goto err_late;
 880         }
 881
 882         /* Allocate memory for storing MAC addresses */
 883         eth_dev->data->mac_addrs = rte_zmalloc("e1000",
 884                 ETHER_ADDR_LEN * hw->mac.rar_entry_count, 0);
 885         if (eth_dev->data->mac_addrs == NULL) {
 886                 PMD_INIT_LOG(ERR, "Failed to allocate %d bytes needed to "
 887                                                 "store MAC addresses",
 888                                 ETHER_ADDR_LEN * hw->mac.rar_entry_count);
 889                 error = -ENOMEM;
 890                 goto err_late;
 891         }
 892
 893         /* Copy the permanent MAC address */
 894         ether_addr_copy((struct ether_addr *)hw->mac.addr, &eth_dev->data->mac_addrs[0]);
 895
 896         /* initialize the vfta */
 897         memset(shadow_vfta, 0, sizeof(*shadow_vfta));
 898
 899         /* Now initialize the hardware */
 900         if (igb_hardware_init(hw) != 0) {
 901                 PMD_INIT_LOG(ERR, "Hardware initialization failed");
 902                 rte_free(eth_dev->data->mac_addrs);
 903                 eth_dev->data->mac_addrs = NULL;
 904                 error = -ENODEV;
 905                 goto err_late;
 906         }
 907         hw->mac.get_link_status = 1;
 908         adapter->stopped = 0;
 909
 910         /* Indicate SOL/IDER usage */
 911         if (e1000_check_reset_block(hw) < 0) {
 912                 PMD_INIT_LOG(ERR, "PHY reset is blocked due to"
 913                                         "SOL/IDER session");
 914         }
 915
 916         /* initialize PF if max_vfs not zero */
 917         igb_pf_host_init(eth_dev);
 918
 919         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
 920         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
 921         ctrl_ext |= E1000_CTRL_EXT_PFRSTD;
 922         E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
 923         E1000_WRITE_FLUSH(hw);
 924
 925         PMD_INIT_LOG(DEBUG, "port_id %d vendorID=0x%x deviceID=0x%x",
 926                      eth_dev->data->port_id, pci_dev->id.vendor_id,
 927                      pci_dev->id.device_id);
 928
 929         rte_intr_callback_register(&pci_dev->intr_handle,
 930                                    eth_igb_interrupt_handler,
 931                                    (void *)eth_dev);
 932
 933         /* enable uio/vfio intr/eventfd mapping */
 934         rte_intr_enable(&pci_dev->intr_handle);
 935
 936         /* enable support intr */
 937         igb_intr_enable(eth_dev);
 938
 939         /* initialize filter info */
 940         memset(filter_info, 0,
 941                sizeof(struct e1000_filter_info));
 942
 943         TAILQ_INIT(&filter_info->flex_list);
 944         TAILQ_INIT(&filter_info->twotuple_list);
 945         TAILQ_INIT(&filter_info->fivetuple_list);
 946
 947         TAILQ_INIT(&igb_filter_ntuple_list);
 948         TAILQ_INIT(&igb_filter_ethertype_list);
 949         TAILQ_INIT(&igb_filter_syn_list);
 950         TAILQ_INIT(&igb_filter_flex_list);
 951         TAILQ_INIT(&igb_flow_list);
 952
 953         return 0;
 954
 955 err_late:
 956         igb_hw_control_release(hw);
 957
 958         return error;
 959 }
 960
 961 static int
 962 eth_igb_dev_uninit(struct rte_eth_dev *eth_dev)
 963 {
 964         struct rte_pci_device *pci_dev;
 965         struct rte_intr_handle *intr_handle;
 966         struct e1000_hw *hw;
 967         struct e1000_adapter *adapter =
 968                 E1000_DEV_PRIVATE(eth_dev->data->dev_private);
 969         struct e1000_filter_info *filter_info =
 970                 E1000_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
 971
 972         PMD_INIT_FUNC_TRACE();
 973
 974         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
 975                 return -EPERM;
 976
 977         hw = E1000_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 978         pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
 979         intr_handle = &pci_dev->intr_handle;
 980
 981         if (adapter->stopped == 0)
 982                 eth_igb_close(eth_dev);
 983
 984         eth_dev->dev_ops = NULL;
 985         eth_dev->rx_pkt_burst = NULL;
 986         eth_dev->tx_pkt_burst = NULL;
 987
 988         /* Reset any pending lock */
 989         igb_reset_swfw_lock(hw);
 990
 991         rte_free(eth_dev->data->mac_addrs);
 992         eth_dev->data->mac_addrs = NULL;
 993
 994         /* uninitialize PF if max_vfs not zero */
 995         igb_pf_host_uninit(eth_dev);
 996
 997         /* disable uio intr before callback unregister */
 998         rte_intr_disable(intr_handle);
 999         rte_intr_callback_unregister(intr_handle,
1000                                      eth_igb_interrupt_handler, eth_dev);
1001
1002         /* clear the SYN filter info */
1003         filter_info->syn_info = 0;
1004
1005         /* clear the ethertype filters info */
1006         filter_info->ethertype_mask = 0;
1007         memset(filter_info->ethertype_filters, 0,
1008                 E1000_MAX_ETQF_FILTERS * sizeof(struct igb_ethertype_filter));
1009
1010         /* remove all ntuple filters of the device */
1011         igb_ntuple_filter_uninit(eth_dev);
1012
1013         /* remove all flex filters of the device */
1014         igb_flex_filter_uninit(eth_dev);
1015
1016         /* clear all the filters list */
1017         igb_filterlist_flush(eth_dev);
1018
1019         return 0;
1020 }
1021
1022 /*
1023  * Virtual Function device init
1024  */
1025 static int
1026 eth_igbvf_dev_init(struct rte_eth_dev *eth_dev)
1027 {
1028         struct rte_pci_device *pci_dev;
1029         struct rte_intr_handle *intr_handle;
1030         struct e1000_adapter *adapter =
1031                 E1000_DEV_PRIVATE(eth_dev->data->dev_private);
1032         struct e1000_hw *hw =
1033                 E1000_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1034         int diag;
1035         struct ether_addr *perm_addr = (struct ether_addr *)hw->mac.perm_addr;
1036
1037         PMD_INIT_FUNC_TRACE();
1038
1039         eth_dev->dev_ops = &igbvf_eth_dev_ops;
1040         eth_dev->rx_pkt_burst = &eth_igb_recv_pkts;
1041         eth_dev->tx_pkt_burst = &eth_igb_xmit_pkts;
1042         eth_dev->tx_pkt_prepare = &eth_igb_prep_pkts;
1043
1044         /* for secondary processes, we don't initialise any further as primary
1045          * has already done this work. Only check we don't need a different
1046          * RX function */
1047         if (rte_eal_process_type() != RTE_PROC_PRIMARY){
1048                 if (eth_dev->data->scattered_rx)
1049                         eth_dev->rx_pkt_burst = &eth_igb_recv_scattered_pkts;
1050                 return 0;
1051         }
1052
1053         pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1054         rte_eth_copy_pci_info(eth_dev, pci_dev);
1055
1056         hw->device_id = pci_dev->id.device_id;
1057         hw->vendor_id = pci_dev->id.vendor_id;
1058         hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
1059         adapter->stopped = 0;
1060
1061         /* Initialize the shared code (base driver) */
1062         diag = e1000_setup_init_funcs(hw, TRUE);
1063         if (diag != 0) {
1064                 PMD_INIT_LOG(ERR, "Shared code init failed for igbvf: %d",
1065                         diag);
1066                 return -EIO;
1067         }
1068
1069         /* init_mailbox_params */
1070         hw->mbx.ops.init_params(hw);
1071
1072         /* Disable the interrupts for VF */
1073         igbvf_intr_disable(hw);
1074
1075         diag = hw->mac.ops.reset_hw(hw);
1076
1077         /* Allocate memory for storing MAC addresses */
1078         eth_dev->data->mac_addrs = rte_zmalloc("igbvf", ETHER_ADDR_LEN *
1079                 hw->mac.rar_entry_count, 0);
1080         if (eth_dev->data->mac_addrs == NULL) {
1081                 PMD_INIT_LOG(ERR,
1082                         "Failed to allocate %d bytes needed to store MAC "
1083                         "addresses",
1084                         ETHER_ADDR_LEN * hw->mac.rar_entry_count);
1085                 return -ENOMEM;
1086         }
1087
1088         /* Generate a random MAC address, if none was assigned by PF. */
1089         if (is_zero_ether_addr(perm_addr)) {
1090                 eth_random_addr(perm_addr->addr_bytes);
1091                 PMD_INIT_LOG(INFO, "\tVF MAC address not assigned by Host PF");
1092                 PMD_INIT_LOG(INFO, "\tAssign randomly generated MAC address "
1093                              "%02x:%02x:%02x:%02x:%02x:%02x",
1094                              perm_addr->addr_bytes[0],
1095                              perm_addr->addr_bytes[1],
1096                              perm_addr->addr_bytes[2],
1097                              perm_addr->addr_bytes[3],
1098                              perm_addr->addr_bytes[4],
1099                              perm_addr->addr_bytes[5]);
1100         }
1101
1102         diag = e1000_rar_set(hw, perm_addr->addr_bytes, 0);
1103         if (diag) {
1104                 rte_free(eth_dev->data->mac_addrs);
1105                 eth_dev->data->mac_addrs = NULL;
1106                 return diag;
1107         }
1108         /* Copy the permanent MAC address */
1109         ether_addr_copy((struct ether_addr *) hw->mac.perm_addr,
1110                         &eth_dev->data->mac_addrs[0]);
1111
1112         PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x "
1113                      "mac.type=%s",
1114                      eth_dev->data->port_id, pci_dev->id.vendor_id,
1115                      pci_dev->id.device_id, "igb_mac_82576_vf");
1116
1117         intr_handle = &pci_dev->intr_handle;
1118         rte_intr_callback_register(intr_handle,
1119                                    eth_igbvf_interrupt_handler, eth_dev);
1120
1121         return 0;
1122 }
1123
1124 static int
1125 eth_igbvf_dev_uninit(struct rte_eth_dev *eth_dev)
1126 {
1127         struct e1000_adapter *adapter =
1128                 E1000_DEV_PRIVATE(eth_dev->data->dev_private);
1129         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1130
1131         PMD_INIT_FUNC_TRACE();
1132
1133         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1134                 return -EPERM;
1135
1136         if (adapter->stopped == 0)
1137                 igbvf_dev_close(eth_dev);
1138
1139         eth_dev->dev_ops = NULL;
1140         eth_dev->rx_pkt_burst = NULL;
1141         eth_dev->tx_pkt_burst = NULL;
1142
1143         rte_free(eth_dev->data->mac_addrs);
1144         eth_dev->data->mac_addrs = NULL;
1145
1146         /* disable uio intr before callback unregister */
1147         rte_intr_disable(&pci_dev->intr_handle);
1148         rte_intr_callback_unregister(&pci_dev->intr_handle,
1149                                      eth_igbvf_interrupt_handler,
1150                                      (void *)eth_dev);
1151
1152         return 0;
1153 }
1154
1155 static int eth_igb_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
1156         struct rte_pci_device *pci_dev)
1157 {
1158         return rte_eth_dev_pci_generic_probe(pci_dev,
1159                 sizeof(struct e1000_adapter), eth_igb_dev_init);
1160 }
1161
1162 static int eth_igb_pci_remove(struct rte_pci_device *pci_dev)
1163 {
1164         return rte_eth_dev_pci_generic_remove(pci_dev, eth_igb_dev_uninit);
1165 }
1166
1167 static struct rte_pci_driver rte_igb_pmd = {
1168         .id_table = pci_id_igb_map,
1169         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC |
1170                      RTE_PCI_DRV_IOVA_AS_VA,
1171         .probe = eth_igb_pci_probe,
1172         .remove = eth_igb_pci_remove,
1173 };
1174
1175
1176 static int eth_igbvf_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
1177         struct rte_pci_device *pci_dev)
1178 {
1179         return rte_eth_dev_pci_generic_probe(pci_dev,
1180                 sizeof(struct e1000_adapter), eth_igbvf_dev_init);
1181 }
1182
1183 static int eth_igbvf_pci_remove(struct rte_pci_device *pci_dev)
1184 {
1185         return rte_eth_dev_pci_generic_remove(pci_dev, eth_igbvf_dev_uninit);
1186 }
1187
1188 /*
1189  * virtual function driver struct
1190  */
1191 static struct rte_pci_driver rte_igbvf_pmd = {
1192         .id_table = pci_id_igbvf_map,
1193         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_IOVA_AS_VA,
1194         .probe = eth_igbvf_pci_probe,
1195         .remove = eth_igbvf_pci_remove,
1196 };
1197
1198 static void
1199 igb_vmdq_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1200 {
1201         struct e1000_hw *hw =
1202                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1203         /* RCTL: enable VLAN filter since VMDq always use VLAN filter */
1204         uint32_t rctl = E1000_READ_REG(hw, E1000_RCTL);
1205         rctl |= E1000_RCTL_VFE;
1206         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1207 }
1208
1209 static int
1210 igb_check_mq_mode(struct rte_eth_dev *dev)
1211 {
1212         enum rte_eth_rx_mq_mode rx_mq_mode = dev->data->dev_conf.rxmode.mq_mode;
1213         enum rte_eth_tx_mq_mode tx_mq_mode = dev->data->dev_conf.txmode.mq_mode;
1214         uint16_t nb_rx_q = dev->data->nb_rx_queues;
1215         uint16_t nb_tx_q = dev->data->nb_rx_queues;
1216
1217         if ((rx_mq_mode & ETH_MQ_RX_DCB_FLAG) ||
1218             tx_mq_mode == ETH_MQ_TX_DCB ||
1219             tx_mq_mode == ETH_MQ_TX_VMDQ_DCB) {
1220                 PMD_INIT_LOG(ERR, "DCB mode is not supported.");
1221                 return -EINVAL;
1222         }
1223         if (RTE_ETH_DEV_SRIOV(dev).active != 0) {
1224                 /* Check multi-queue mode.
1225                  * To no break software we accept ETH_MQ_RX_NONE as this might
1226                  * be used to turn off VLAN filter.
1227                  */
1228
1229                 if (rx_mq_mode == ETH_MQ_RX_NONE ||
1230                     rx_mq_mode == ETH_MQ_RX_VMDQ_ONLY) {
1231                         dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_ONLY;
1232                         RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool = 1;
1233                 } else {
1234                         /* Only support one queue on VFs.
1235                          * RSS together with SRIOV is not supported.
1236                          */
1237                         PMD_INIT_LOG(ERR, "SRIOV is active,"
1238                                         " wrong mq_mode rx %d.",
1239                                         rx_mq_mode);
1240                         return -EINVAL;
1241                 }
1242                 /* TX mode is not used here, so mode might be ignored.*/
1243                 if (tx_mq_mode != ETH_MQ_TX_VMDQ_ONLY) {
1244                         /* SRIOV only works in VMDq enable mode */
1245                         PMD_INIT_LOG(WARNING, "SRIOV is active,"
1246                                         " TX mode %d is not supported. "
1247                                         " Driver will behave as %d mode.",
1248                                         tx_mq_mode, ETH_MQ_TX_VMDQ_ONLY);
1249                 }
1250
1251                 /* check valid queue number */
1252                 if ((nb_rx_q > 1) || (nb_tx_q > 1)) {
1253                         PMD_INIT_LOG(ERR, "SRIOV is active,"
1254                                         " only support one queue on VFs.");
1255                         return -EINVAL;
1256                 }
1257         } else {
1258                 /* To no break software that set invalid mode, only display
1259                  * warning if invalid mode is used.
1260                  */
1261                 if (rx_mq_mode != ETH_MQ_RX_NONE &&
1262                     rx_mq_mode != ETH_MQ_RX_VMDQ_ONLY &&
1263                     rx_mq_mode != ETH_MQ_RX_RSS) {
1264                         /* RSS together with VMDq not supported*/
1265                         PMD_INIT_LOG(ERR, "RX mode %d is not supported.",
1266                                      rx_mq_mode);
1267                         return -EINVAL;
1268                 }
1269
1270                 if (tx_mq_mode != ETH_MQ_TX_NONE &&
1271                     tx_mq_mode != ETH_MQ_TX_VMDQ_ONLY) {
1272                         PMD_INIT_LOG(WARNING, "TX mode %d is not supported."
1273                                         " Due to txmode is meaningless in this"
1274                                         " driver, just ignore.",
1275                                         tx_mq_mode);
1276                 }
1277         }
1278         return 0;
1279 }
1280
1281 static int
1282 eth_igb_configure(struct rte_eth_dev *dev)
1283 {
1284         struct e1000_interrupt *intr =
1285                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
1286         int ret;
1287
1288         PMD_INIT_FUNC_TRACE();
1289
1290         /* multipe queue mode checking */
1291         ret  = igb_check_mq_mode(dev);
1292         if (ret != 0) {
1293                 PMD_DRV_LOG(ERR, "igb_check_mq_mode fails with %d.",
1294                             ret);
1295                 return ret;
1296         }
1297
1298         intr->flags |= E1000_FLAG_NEED_LINK_UPDATE;
1299         PMD_INIT_FUNC_TRACE();
1300
1301         return 0;
1302 }
1303
1304 static int
1305 eth_igb_start(struct rte_eth_dev *dev)
1306 {
1307         struct e1000_hw *hw =
1308                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1309         struct e1000_adapter *adapter =
1310                 E1000_DEV_PRIVATE(dev->data->dev_private);
1311         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1312         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1313         int ret, mask;
1314         uint32_t intr_vector = 0;
1315         uint32_t ctrl_ext;
1316         uint32_t *speeds;
1317         int num_speeds;
1318         bool autoneg;
1319
1320         PMD_INIT_FUNC_TRACE();
1321
1322         /* disable uio/vfio intr/eventfd mapping */
1323         rte_intr_disable(intr_handle);
1324
1325         /* Power up the phy. Needed to make the link go Up */
1326         eth_igb_dev_set_link_up(dev);
1327
1328         /*
1329          * Packet Buffer Allocation (PBA)
1330          * Writing PBA sets the receive portion of the buffer
1331          * the remainder is used for the transmit buffer.
1332          */
1333         if (hw->mac.type == e1000_82575) {
1334                 uint32_t pba;
1335
1336                 pba = E1000_PBA_32K; /* 32K for Rx, 16K for Tx */
1337                 E1000_WRITE_REG(hw, E1000_PBA, pba);
1338         }
1339
1340         /* Put the address into the Receive Address Array */
1341         e1000_rar_set(hw, hw->mac.addr, 0);
1342
1343         /* Initialize the hardware */
1344         if (igb_hardware_init(hw)) {
1345                 PMD_INIT_LOG(ERR, "Unable to initialize the hardware");
1346                 return -EIO;
1347         }
1348         adapter->stopped = 0;
1349
1350         E1000_WRITE_REG(hw, E1000_VET, ETHER_TYPE_VLAN << 16 | ETHER_TYPE_VLAN);
1351
1352         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
1353         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
1354         ctrl_ext |= E1000_CTRL_EXT_PFRSTD;
1355         E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
1356         E1000_WRITE_FLUSH(hw);
1357
1358         /* configure PF module if SRIOV enabled */
1359         igb_pf_host_configure(dev);
1360
1361         /* check and configure queue intr-vector mapping */
1362         if ((rte_intr_cap_multiple(intr_handle) ||
1363              !RTE_ETH_DEV_SRIOV(dev).active) &&
1364             dev->data->dev_conf.intr_conf.rxq != 0) {
1365                 intr_vector = dev->data->nb_rx_queues;
1366                 if (rte_intr_efd_enable(intr_handle, intr_vector))
1367                         return -1;
1368         }
1369
1370         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
1371                 intr_handle->intr_vec =
1372                         rte_zmalloc("intr_vec",
1373                                     dev->data->nb_rx_queues * sizeof(int), 0);
1374                 if (intr_handle->intr_vec == NULL) {
1375                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
1376                                      " intr_vec", dev->data->nb_rx_queues);
1377                         return -ENOMEM;
1378                 }
1379         }
1380
1381         /* confiugre msix for rx interrupt */
1382         eth_igb_configure_msix_intr(dev);
1383
1384         /* Configure for OS presence */
1385         igb_init_manageability(hw);
1386
1387         eth_igb_tx_init(dev);
1388
1389         /* This can fail when allocating mbufs for descriptor rings */
1390         ret = eth_igb_rx_init(dev);
1391         if (ret) {
1392                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
1393                 igb_dev_clear_queues(dev);
1394                 return ret;
1395         }
1396
1397         e1000_clear_hw_cntrs_base_generic(hw);
1398
1399         /*
1400          * VLAN Offload Settings
1401          */
1402         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK | \
1403                         ETH_VLAN_EXTEND_MASK;
1404         ret = eth_igb_vlan_offload_set(dev, mask);
1405         if (ret) {
1406                 PMD_INIT_LOG(ERR, "Unable to set vlan offload");
1407                 igb_dev_clear_queues(dev);
1408                 return ret;
1409         }
1410
1411         if (dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_VMDQ_ONLY) {
1412                 /* Enable VLAN filter since VMDq always use VLAN filter */
1413                 igb_vmdq_vlan_hw_filter_enable(dev);
1414         }
1415
1416         if ((hw->mac.type == e1000_82576) || (hw->mac.type == e1000_82580) ||
1417                 (hw->mac.type == e1000_i350) || (hw->mac.type == e1000_i210) ||
1418                 (hw->mac.type == e1000_i211)) {
1419                 /* Configure EITR with the maximum possible value (0xFFFF) */
1420                 E1000_WRITE_REG(hw, E1000_EITR(0), 0xFFFF);
1421         }
1422
1423         /* Setup link speed and duplex */
1424         speeds = &dev->data->dev_conf.link_speeds;
1425         if (*speeds == ETH_LINK_SPEED_AUTONEG) {
1426                 hw->phy.autoneg_advertised = E1000_ALL_SPEED_DUPLEX;
1427                 hw->mac.autoneg = 1;
1428         } else {
1429                 num_speeds = 0;
1430                 autoneg = (*speeds & ETH_LINK_SPEED_FIXED) == 0;
1431
1432                 /* Reset */
1433                 hw->phy.autoneg_advertised = 0;
1434
1435                 if (*speeds & ~(ETH_LINK_SPEED_10M_HD | ETH_LINK_SPEED_10M |
1436                                 ETH_LINK_SPEED_100M_HD | ETH_LINK_SPEED_100M |
1437                                 ETH_LINK_SPEED_1G | ETH_LINK_SPEED_FIXED)) {
1438                         num_speeds = -1;
1439                         goto error_invalid_config;
1440                 }
1441                 if (*speeds & ETH_LINK_SPEED_10M_HD) {
1442                         hw->phy.autoneg_advertised |= ADVERTISE_10_HALF;
1443                         num_speeds++;
1444                 }
1445                 if (*speeds & ETH_LINK_SPEED_10M) {
1446                         hw->phy.autoneg_advertised |= ADVERTISE_10_FULL;
1447                         num_speeds++;
1448                 }
1449                 if (*speeds & ETH_LINK_SPEED_100M_HD) {
1450                         hw->phy.autoneg_advertised |= ADVERTISE_100_HALF;
1451                         num_speeds++;
1452                 }
1453                 if (*speeds & ETH_LINK_SPEED_100M) {
1454                         hw->phy.autoneg_advertised |= ADVERTISE_100_FULL;
1455                         num_speeds++;
1456                 }
1457                 if (*speeds & ETH_LINK_SPEED_1G) {
1458                         hw->phy.autoneg_advertised |= ADVERTISE_1000_FULL;
1459                         num_speeds++;
1460                 }
1461                 if (num_speeds == 0 || (!autoneg && (num_speeds > 1)))
1462                         goto error_invalid_config;
1463
1464                 /* Set/reset the mac.autoneg based on the link speed,
1465                  * fixed or not
1466                  */
1467                 if (!autoneg) {
1468                         hw->mac.autoneg = 0;
1469                         hw->mac.forced_speed_duplex =
1470                                         hw->phy.autoneg_advertised;
1471                 } else {
1472                         hw->mac.autoneg = 1;
1473                 }
1474         }
1475
1476         e1000_setup_link(hw);
1477
1478         if (rte_intr_allow_others(intr_handle)) {
1479                 /* check if lsc interrupt is enabled */
1480                 if (dev->data->dev_conf.intr_conf.lsc != 0)
1481                         eth_igb_lsc_interrupt_setup(dev, TRUE);
1482                 else
1483                         eth_igb_lsc_interrupt_setup(dev, FALSE);
1484         } else {
1485                 rte_intr_callback_unregister(intr_handle,
1486                                              eth_igb_interrupt_handler,
1487                                              (void *)dev);
1488                 if (dev->data->dev_conf.intr_conf.lsc != 0)
1489                         PMD_INIT_LOG(INFO, "lsc won't enable because of"
1490                                      " no intr multiplex");
1491         }
1492
1493         /* check if rxq interrupt is enabled */
1494         if (dev->data->dev_conf.intr_conf.rxq != 0 &&
1495             rte_intr_dp_is_en(intr_handle))
1496                 eth_igb_rxq_interrupt_setup(dev);
1497
1498         /* enable uio/vfio intr/eventfd mapping */
1499         rte_intr_enable(intr_handle);
1500
1501         /* resume enabled intr since hw reset */
1502         igb_intr_enable(dev);
1503
1504         /* restore all types filter */
1505         igb_filter_restore(dev);
1506
1507         PMD_INIT_LOG(DEBUG, "<<");
1508
1509         return 0;
1510
1511 error_invalid_config:
1512         PMD_INIT_LOG(ERR, "Invalid advertised speeds (%u) for port %u",
1513                      dev->data->dev_conf.link_speeds, dev->data->port_id);
1514         igb_dev_clear_queues(dev);
1515         return -EINVAL;
1516 }
1517
1518 /*********************************************************************
1519  *
1520  *  This routine disables all traffic on the adapter by issuing a
1521  *  global reset on the MAC.
1522  *
1523  **********************************************************************/
1524 static void
1525 eth_igb_stop(struct rte_eth_dev *dev)
1526 {
1527         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1528         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1529         struct rte_eth_link link;
1530         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1531
1532         igb_intr_disable(hw);
1533
1534         /* disable intr eventfd mapping */
1535         rte_intr_disable(intr_handle);
1536
1537         igb_pf_reset_hw(hw);
1538         E1000_WRITE_REG(hw, E1000_WUC, 0);
1539
1540         /* Set bit for Go Link disconnect */
1541         if (hw->mac.type >= e1000_82580) {
1542                 uint32_t phpm_reg;
1543
1544                 phpm_reg = E1000_READ_REG(hw, E1000_82580_PHY_POWER_MGMT);
1545                 phpm_reg |= E1000_82580_PM_GO_LINKD;
1546                 E1000_WRITE_REG(hw, E1000_82580_PHY_POWER_MGMT, phpm_reg);
1547         }
1548
1549         /* Power down the phy. Needed to make the link go Down */
1550         eth_igb_dev_set_link_down(dev);
1551
1552         igb_dev_clear_queues(dev);
1553
1554         /* clear the recorded link status */
1555         memset(&link, 0, sizeof(link));
1556         rte_igb_dev_atomic_write_link_status(dev, &link);
1557
1558         if (!rte_intr_allow_others(intr_handle))
1559                 /* resume to the default handler */
1560                 rte_intr_callback_register(intr_handle,
1561                                            eth_igb_interrupt_handler,
1562                                            (void *)dev);
1563
1564         /* Clean datapath event and queue/vec mapping */
1565         rte_intr_efd_disable(intr_handle);
1566         if (intr_handle->intr_vec != NULL) {
1567                 rte_free(intr_handle->intr_vec);
1568                 intr_handle->intr_vec = NULL;
1569         }
1570 }
1571
1572 static int
1573 eth_igb_dev_set_link_up(struct rte_eth_dev *dev)
1574 {
1575         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1576
1577         if (hw->phy.media_type == e1000_media_type_copper)
1578                 e1000_power_up_phy(hw);
1579         else
1580                 e1000_power_up_fiber_serdes_link(hw);
1581
1582         return 0;
1583 }
1584
1585 static int
1586 eth_igb_dev_set_link_down(struct rte_eth_dev *dev)
1587 {
1588         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1589
1590         if (hw->phy.media_type == e1000_media_type_copper)
1591                 e1000_power_down_phy(hw);
1592         else
1593                 e1000_shutdown_fiber_serdes_link(hw);
1594
1595         return 0;
1596 }
1597
1598 static void
1599 eth_igb_close(struct rte_eth_dev *dev)
1600 {
1601         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1602         struct e1000_adapter *adapter =
1603                 E1000_DEV_PRIVATE(dev->data->dev_private);
1604         struct rte_eth_link link;
1605         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1606         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1607
1608         eth_igb_stop(dev);
1609         adapter->stopped = 1;
1610
1611         e1000_phy_hw_reset(hw);
1612         igb_release_manageability(hw);
1613         igb_hw_control_release(hw);
1614
1615         /* Clear bit for Go Link disconnect */
1616         if (hw->mac.type >= e1000_82580) {
1617                 uint32_t phpm_reg;
1618
1619                 phpm_reg = E1000_READ_REG(hw, E1000_82580_PHY_POWER_MGMT);
1620                 phpm_reg &= ~E1000_82580_PM_GO_LINKD;
1621                 E1000_WRITE_REG(hw, E1000_82580_PHY_POWER_MGMT, phpm_reg);
1622         }
1623
1624         igb_dev_free_queues(dev);
1625
1626         if (intr_handle->intr_vec) {
1627                 rte_free(intr_handle->intr_vec);
1628                 intr_handle->intr_vec = NULL;
1629         }
1630
1631         memset(&link, 0, sizeof(link));
1632         rte_igb_dev_atomic_write_link_status(dev, &link);
1633 }
1634
1635 static int
1636 igb_get_rx_buffer_size(struct e1000_hw *hw)
1637 {
1638         uint32_t rx_buf_size;
1639         if (hw->mac.type == e1000_82576) {
1640                 rx_buf_size = (E1000_READ_REG(hw, E1000_RXPBS) & 0xffff) << 10;
1641         } else if (hw->mac.type == e1000_82580 || hw->mac.type == e1000_i350) {
1642                 /* PBS needs to be translated according to a lookup table */
1643                 rx_buf_size = (E1000_READ_REG(hw, E1000_RXPBS) & 0xf);
1644                 rx_buf_size = (uint32_t) e1000_rxpbs_adjust_82580(rx_buf_size);
1645                 rx_buf_size = (rx_buf_size << 10);
1646         } else if (hw->mac.type == e1000_i210 || hw->mac.type == e1000_i211) {
1647                 rx_buf_size = (E1000_READ_REG(hw, E1000_RXPBS) & 0x3f) << 10;
1648         } else {
1649                 rx_buf_size = (E1000_READ_REG(hw, E1000_PBA) & 0xffff) << 10;
1650         }
1651
1652         return rx_buf_size;
1653 }
1654
1655 /*********************************************************************
1656  *
1657  *  Initialize the hardware
1658  *
1659  **********************************************************************/
1660 static int
1661 igb_hardware_init(struct e1000_hw *hw)
1662 {
1663         uint32_t rx_buf_size;
1664         int diag;
1665
1666         /* Let the firmware know the OS is in control */
1667         igb_hw_control_acquire(hw);
1668
1669         /*
1670          * These parameters control the automatic generation (Tx) and
1671          * response (Rx) to Ethernet PAUSE frames.
1672          * - High water mark should allow for at least two standard size (1518)
1673          *   frames to be received after sending an XOFF.
1674          * - Low water mark works best when it is very near the high water mark.
1675          *   This allows the receiver to restart by sending XON when it has
1676          *   drained a bit. Here we use an arbitrary value of 1500 which will
1677          *   restart after one full frame is pulled from the buffer. There
1678          *   could be several smaller frames in the buffer and if so they will
1679          *   not trigger the XON until their total number reduces the buffer
1680          *   by 1500.
1681          * - The pause time is fairly large at 1000 x 512ns = 512 usec.
1682          */
1683         rx_buf_size = igb_get_rx_buffer_size(hw);
1684
1685         hw->fc.high_water = rx_buf_size - (ETHER_MAX_LEN * 2);
1686         hw->fc.low_water = hw->fc.high_water - 1500;
1687         hw->fc.pause_time = IGB_FC_PAUSE_TIME;
1688         hw->fc.send_xon = 1;
1689
1690         /* Set Flow control, use the tunable location if sane */
1691         if ((igb_fc_setting != e1000_fc_none) && (igb_fc_setting < 4))
1692                 hw->fc.requested_mode = igb_fc_setting;
1693         else
1694                 hw->fc.requested_mode = e1000_fc_none;
1695
1696         /* Issue a global reset */
1697         igb_pf_reset_hw(hw);
1698         E1000_WRITE_REG(hw, E1000_WUC, 0);
1699
1700         diag = e1000_init_hw(hw);
1701         if (diag < 0)
1702                 return diag;
1703
1704         E1000_WRITE_REG(hw, E1000_VET, ETHER_TYPE_VLAN << 16 | ETHER_TYPE_VLAN);
1705         e1000_get_phy_info(hw);
1706         e1000_check_for_link(hw);
1707
1708         return 0;
1709 }
1710
1711 /* This function is based on igb_update_stats_counters() in igb/if_igb.c */
1712 static void
1713 igb_read_stats_registers(struct e1000_hw *hw, struct e1000_hw_stats *stats)
1714 {
1715         int pause_frames;
1716
1717         uint64_t old_gprc  = stats->gprc;
1718         uint64_t old_gptc  = stats->gptc;
1719         uint64_t old_tpr   = stats->tpr;
1720         uint64_t old_tpt   = stats->tpt;
1721         uint64_t old_rpthc = stats->rpthc;
1722         uint64_t old_hgptc = stats->hgptc;
1723
1724         if(hw->phy.media_type == e1000_media_type_copper ||
1725             (E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU)) {
1726                 stats->symerrs +=
1727                     E1000_READ_REG(hw,E1000_SYMERRS);
1728                 stats->sec += E1000_READ_REG(hw, E1000_SEC);
1729         }
1730
1731         stats->crcerrs += E1000_READ_REG(hw, E1000_CRCERRS);
1732         stats->mpc += E1000_READ_REG(hw, E1000_MPC);
1733         stats->scc += E1000_READ_REG(hw, E1000_SCC);
1734         stats->ecol += E1000_READ_REG(hw, E1000_ECOL);
1735
1736         stats->mcc += E1000_READ_REG(hw, E1000_MCC);
1737         stats->latecol += E1000_READ_REG(hw, E1000_LATECOL);
1738         stats->colc += E1000_READ_REG(hw, E1000_COLC);
1739         stats->dc += E1000_READ_REG(hw, E1000_DC);
1740         stats->rlec += E1000_READ_REG(hw, E1000_RLEC);
1741         stats->xonrxc += E1000_READ_REG(hw, E1000_XONRXC);
1742         stats->xontxc += E1000_READ_REG(hw, E1000_XONTXC);
1743         /*
1744         ** For watchdog management we need to know if we have been
1745         ** paused during the last interval, so capture that here.
1746         */
1747         pause_frames = E1000_READ_REG(hw, E1000_XOFFRXC);
1748         stats->xoffrxc += pause_frames;
1749         stats->xofftxc += E1000_READ_REG(hw, E1000_XOFFTXC);
1750         stats->fcruc += E1000_READ_REG(hw, E1000_FCRUC);
1751         stats->prc64 += E1000_READ_REG(hw, E1000_PRC64);
1752         stats->prc127 += E1000_READ_REG(hw, E1000_PRC127);
1753         stats->prc255 += E1000_READ_REG(hw, E1000_PRC255);
1754         stats->prc511 += E1000_READ_REG(hw, E1000_PRC511);
1755         stats->prc1023 += E1000_READ_REG(hw, E1000_PRC1023);
1756         stats->prc1522 += E1000_READ_REG(hw, E1000_PRC1522);
1757         stats->gprc += E1000_READ_REG(hw, E1000_GPRC);
1758         stats->bprc += E1000_READ_REG(hw, E1000_BPRC);
1759         stats->mprc += E1000_READ_REG(hw, E1000_MPRC);
1760         stats->gptc += E1000_READ_REG(hw, E1000_GPTC);
1761
1762         /* For the 64-bit byte counters the low dword must be read first. */
1763         /* Both registers clear on the read of the high dword */
1764
1765         /* Workaround CRC bytes included in size, take away 4 bytes/packet */
1766         stats->gorc += E1000_READ_REG(hw, E1000_GORCL);
1767         stats->gorc += ((uint64_t)E1000_READ_REG(hw, E1000_GORCH) << 32);
1768         stats->gorc -= (stats->gprc - old_gprc) * ETHER_CRC_LEN;
1769         stats->gotc += E1000_READ_REG(hw, E1000_GOTCL);
1770         stats->gotc += ((uint64_t)E1000_READ_REG(hw, E1000_GOTCH) << 32);
1771         stats->gotc -= (stats->gptc - old_gptc) * ETHER_CRC_LEN;
1772
1773         stats->rnbc += E1000_READ_REG(hw, E1000_RNBC);
1774         stats->ruc += E1000_READ_REG(hw, E1000_RUC);
1775         stats->rfc += E1000_READ_REG(hw, E1000_RFC);
1776         stats->roc += E1000_READ_REG(hw, E1000_ROC);
1777         stats->rjc += E1000_READ_REG(hw, E1000_RJC);
1778
1779         stats->tpr += E1000_READ_REG(hw, E1000_TPR);
1780         stats->tpt += E1000_READ_REG(hw, E1000_TPT);
1781
1782         stats->tor += E1000_READ_REG(hw, E1000_TORL);
1783         stats->tor += ((uint64_t)E1000_READ_REG(hw, E1000_TORH) << 32);
1784         stats->tor -= (stats->tpr - old_tpr) * ETHER_CRC_LEN;
1785         stats->tot += E1000_READ_REG(hw, E1000_TOTL);
1786         stats->tot += ((uint64_t)E1000_READ_REG(hw, E1000_TOTH) << 32);
1787         stats->tot -= (stats->tpt - old_tpt) * ETHER_CRC_LEN;
1788
1789         stats->ptc64 += E1000_READ_REG(hw, E1000_PTC64);
1790         stats->ptc127 += E1000_READ_REG(hw, E1000_PTC127);
1791         stats->ptc255 += E1000_READ_REG(hw, E1000_PTC255);
1792         stats->ptc511 += E1000_READ_REG(hw, E1000_PTC511);
1793         stats->ptc1023 += E1000_READ_REG(hw, E1000_PTC1023);
1794         stats->ptc1522 += E1000_READ_REG(hw, E1000_PTC1522);
1795         stats->mptc += E1000_READ_REG(hw, E1000_MPTC);
1796         stats->bptc += E1000_READ_REG(hw, E1000_BPTC);
1797
1798         /* Interrupt Counts */
1799
1800         stats->iac += E1000_READ_REG(hw, E1000_IAC);
1801         stats->icrxptc += E1000_READ_REG(hw, E1000_ICRXPTC);
1802         stats->icrxatc += E1000_READ_REG(hw, E1000_ICRXATC);
1803         stats->ictxptc += E1000_READ_REG(hw, E1000_ICTXPTC);
1804         stats->ictxatc += E1000_READ_REG(hw, E1000_ICTXATC);
1805         stats->ictxqec += E1000_READ_REG(hw, E1000_ICTXQEC);
1806         stats->ictxqmtc += E1000_READ_REG(hw, E1000_ICTXQMTC);
1807         stats->icrxdmtc += E1000_READ_REG(hw, E1000_ICRXDMTC);
1808         stats->icrxoc += E1000_READ_REG(hw, E1000_ICRXOC);
1809
1810         /* Host to Card Statistics */
1811
1812         stats->cbtmpc += E1000_READ_REG(hw, E1000_CBTMPC);
1813         stats->htdpmc += E1000_READ_REG(hw, E1000_HTDPMC);
1814         stats->cbrdpc += E1000_READ_REG(hw, E1000_CBRDPC);
1815         stats->cbrmpc += E1000_READ_REG(hw, E1000_CBRMPC);
1816         stats->rpthc += E1000_READ_REG(hw, E1000_RPTHC);
1817         stats->hgptc += E1000_READ_REG(hw, E1000_HGPTC);
1818         stats->htcbdpc += E1000_READ_REG(hw, E1000_HTCBDPC);
1819         stats->hgorc += E1000_READ_REG(hw, E1000_HGORCL);
1820         stats->hgorc += ((uint64_t)E1000_READ_REG(hw, E1000_HGORCH) << 32);
1821         stats->hgorc -= (stats->rpthc - old_rpthc) * ETHER_CRC_LEN;
1822         stats->hgotc += E1000_READ_REG(hw, E1000_HGOTCL);
1823         stats->hgotc += ((uint64_t)E1000_READ_REG(hw, E1000_HGOTCH) << 32);
1824         stats->hgotc -= (stats->hgptc - old_hgptc) * ETHER_CRC_LEN;
1825         stats->lenerrs += E1000_READ_REG(hw, E1000_LENERRS);
1826         stats->scvpc += E1000_READ_REG(hw, E1000_SCVPC);
1827         stats->hrmpc += E1000_READ_REG(hw, E1000_HRMPC);
1828
1829         stats->algnerrc += E1000_READ_REG(hw, E1000_ALGNERRC);
1830         stats->rxerrc += E1000_READ_REG(hw, E1000_RXERRC);
1831         stats->tncrs += E1000_READ_REG(hw, E1000_TNCRS);
1832         stats->cexterr += E1000_READ_REG(hw, E1000_CEXTERR);
1833         stats->tsctc += E1000_READ_REG(hw, E1000_TSCTC);
1834         stats->tsctfc += E1000_READ_REG(hw, E1000_TSCTFC);
1835 }
1836
1837 static int
1838 eth_igb_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *rte_stats)
1839 {
1840         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1841         struct e1000_hw_stats *stats =
1842                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1843
1844         igb_read_stats_registers(hw, stats);
1845
1846         if (rte_stats == NULL)
1847                 return -EINVAL;
1848
1849         /* Rx Errors */
1850         rte_stats->imissed = stats->mpc;
1851         rte_stats->ierrors = stats->crcerrs +
1852                              stats->rlec + stats->ruc + stats->roc +
1853                              stats->rxerrc + stats->algnerrc + stats->cexterr;
1854
1855         /* Tx Errors */
1856         rte_stats->oerrors = stats->ecol + stats->latecol;
1857
1858         rte_stats->ipackets = stats->gprc;
1859         rte_stats->opackets = stats->gptc;
1860         rte_stats->ibytes   = stats->gorc;
1861         rte_stats->obytes   = stats->gotc;
1862         return 0;
1863 }
1864
1865 static void
1866 eth_igb_stats_reset(struct rte_eth_dev *dev)
1867 {
1868         struct e1000_hw_stats *hw_stats =
1869                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1870
1871         /* HW registers are cleared on read */
1872         eth_igb_stats_get(dev, NULL);
1873
1874         /* Reset software totals */
1875         memset(hw_stats, 0, sizeof(*hw_stats));
1876 }
1877
1878 static void
1879 eth_igb_xstats_reset(struct rte_eth_dev *dev)
1880 {
1881         struct e1000_hw_stats *stats =
1882                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1883
1884         /* HW registers are cleared on read */
1885         eth_igb_xstats_get(dev, NULL, IGB_NB_XSTATS);
1886
1887         /* Reset software totals */
1888         memset(stats, 0, sizeof(*stats));
1889 }
1890
1891 static int eth_igb_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
1892         struct rte_eth_xstat_name *xstats_names,
1893         __rte_unused unsigned int size)
1894 {
1895         unsigned i;
1896
1897         if (xstats_names == NULL)
1898                 return IGB_NB_XSTATS;
1899
1900         /* Note: limit checked in rte_eth_xstats_names() */
1901
1902         for (i = 0; i < IGB_NB_XSTATS; i++) {
1903                 snprintf(xstats_names[i].name, sizeof(xstats_names[i].name),
1904                          "%s", rte_igb_stats_strings[i].name);
1905         }
1906
1907         return IGB_NB_XSTATS;
1908 }
1909
1910 static int eth_igb_xstats_get_names_by_id(struct rte_eth_dev *dev,
1911                 struct rte_eth_xstat_name *xstats_names, const uint64_t *ids,
1912                 unsigned int limit)
1913 {
1914         unsigned int i;
1915
1916         if (!ids) {
1917                 if (xstats_names == NULL)
1918                         return IGB_NB_XSTATS;
1919
1920                 for (i = 0; i < IGB_NB_XSTATS; i++)
1921                         snprintf(xstats_names[i].name,
1922                                         sizeof(xstats_names[i].name),
1923                                         "%s", rte_igb_stats_strings[i].name);
1924
1925                 return IGB_NB_XSTATS;
1926
1927         } else {
1928                 struct rte_eth_xstat_name xstats_names_copy[IGB_NB_XSTATS];
1929
1930                 eth_igb_xstats_get_names_by_id(dev, xstats_names_copy, NULL,
1931                                 IGB_NB_XSTATS);
1932
1933                 for (i = 0; i < limit; i++) {
1934                         if (ids[i] >= IGB_NB_XSTATS) {
1935                                 PMD_INIT_LOG(ERR, "id value isn't valid");
1936                                 return -1;
1937                         }
1938                         strcpy(xstats_names[i].name,
1939                                         xstats_names_copy[ids[i]].name);
1940                 }
1941                 return limit;
1942         }
1943 }
1944
1945 static int
1946 eth_igb_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
1947                    unsigned n)
1948 {
1949         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1950         struct e1000_hw_stats *hw_stats =
1951                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1952         unsigned i;
1953
1954         if (n < IGB_NB_XSTATS)
1955                 return IGB_NB_XSTATS;
1956
1957         igb_read_stats_registers(hw, hw_stats);
1958
1959         /* If this is a reset xstats is NULL, and we have cleared the
1960          * registers by reading them.
1961          */
1962         if (!xstats)
1963                 return 0;
1964
1965         /* Extended stats */
1966         for (i = 0; i < IGB_NB_XSTATS; i++) {
1967                 xstats[i].id = i;
1968                 xstats[i].value = *(uint64_t *)(((char *)hw_stats) +
1969                         rte_igb_stats_strings[i].offset);
1970         }
1971
1972         return IGB_NB_XSTATS;
1973 }
1974
1975 static int
1976 eth_igb_xstats_get_by_id(struct rte_eth_dev *dev, const uint64_t *ids,
1977                 uint64_t *values, unsigned int n)
1978 {
1979         unsigned int i;
1980
1981         if (!ids) {
1982                 struct e1000_hw *hw =
1983                         E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1984                 struct e1000_hw_stats *hw_stats =
1985                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1986
1987                 if (n < IGB_NB_XSTATS)
1988                         return IGB_NB_XSTATS;
1989
1990                 igb_read_stats_registers(hw, hw_stats);
1991
1992                 /* If this is a reset xstats is NULL, and we have cleared the
1993                  * registers by reading them.
1994                  */
1995                 if (!values)
1996                         return 0;
1997
1998                 /* Extended stats */
1999                 for (i = 0; i < IGB_NB_XSTATS; i++)
2000                         values[i] = *(uint64_t *)(((char *)hw_stats) +
2001                                         rte_igb_stats_strings[i].offset);
2002
2003                 return IGB_NB_XSTATS;
2004
2005         } else {
2006                 uint64_t values_copy[IGB_NB_XSTATS];
2007
2008                 eth_igb_xstats_get_by_id(dev, NULL, values_copy,
2009                                 IGB_NB_XSTATS);
2010
2011                 for (i = 0; i < n; i++) {
2012                         if (ids[i] >= IGB_NB_XSTATS) {
2013                                 PMD_INIT_LOG(ERR, "id value isn't valid");
2014                                 return -1;
2015                         }
2016                         values[i] = values_copy[ids[i]];
2017                 }
2018                 return n;
2019         }
2020 }
2021
2022 static void
2023 igbvf_read_stats_registers(struct e1000_hw *hw, struct e1000_vf_stats *hw_stats)
2024 {
2025         /* Good Rx packets, include VF loopback */
2026         UPDATE_VF_STAT(E1000_VFGPRC,
2027             hw_stats->last_gprc, hw_stats->gprc);
2028
2029         /* Good Rx octets, include VF loopback */
2030         UPDATE_VF_STAT(E1000_VFGORC,
2031             hw_stats->last_gorc, hw_stats->gorc);
2032
2033         /* Good Tx packets, include VF loopback */
2034         UPDATE_VF_STAT(E1000_VFGPTC,
2035             hw_stats->last_gptc, hw_stats->gptc);
2036
2037         /* Good Tx octets, include VF loopback */
2038         UPDATE_VF_STAT(E1000_VFGOTC,
2039             hw_stats->last_gotc, hw_stats->gotc);
2040
2041         /* Rx Multicst packets */
2042         UPDATE_VF_STAT(E1000_VFMPRC,
2043             hw_stats->last_mprc, hw_stats->mprc);
2044
2045         /* Good Rx loopback packets */
2046         UPDATE_VF_STAT(E1000_VFGPRLBC,
2047             hw_stats->last_gprlbc, hw_stats->gprlbc);
2048
2049         /* Good Rx loopback octets */
2050         UPDATE_VF_STAT(E1000_VFGORLBC,
2051             hw_stats->last_gorlbc, hw_stats->gorlbc);
2052
2053         /* Good Tx loopback packets */
2054         UPDATE_VF_STAT(E1000_VFGPTLBC,
2055             hw_stats->last_gptlbc, hw_stats->gptlbc);
2056
2057         /* Good Tx loopback octets */
2058         UPDATE_VF_STAT(E1000_VFGOTLBC,
2059             hw_stats->last_gotlbc, hw_stats->gotlbc);
2060 }
2061
2062 static int eth_igbvf_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
2063                                      struct rte_eth_xstat_name *xstats_names,
2064                                      __rte_unused unsigned limit)
2065 {
2066         unsigned i;
2067
2068         if (xstats_names != NULL)
2069                 for (i = 0; i < IGBVF_NB_XSTATS; i++) {
2070                         snprintf(xstats_names[i].name,
2071                                 sizeof(xstats_names[i].name), "%s",
2072                                 rte_igbvf_stats_strings[i].name);
2073                 }
2074         return IGBVF_NB_XSTATS;
2075 }
2076
2077 static int
2078 eth_igbvf_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
2079                      unsigned n)
2080 {
2081         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2082         struct e1000_vf_stats *hw_stats = (struct e1000_vf_stats *)
2083                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2084         unsigned i;
2085
2086         if (n < IGBVF_NB_XSTATS)
2087                 return IGBVF_NB_XSTATS;
2088
2089         igbvf_read_stats_registers(hw, hw_stats);
2090
2091         if (!xstats)
2092                 return 0;
2093
2094         for (i = 0; i < IGBVF_NB_XSTATS; i++) {
2095                 xstats[i].id = i;
2096                 xstats[i].value = *(uint64_t *)(((char *)hw_stats) +
2097                         rte_igbvf_stats_strings[i].offset);
2098         }
2099
2100         return IGBVF_NB_XSTATS;
2101 }
2102
2103 static int
2104 eth_igbvf_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *rte_stats)
2105 {
2106         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2107         struct e1000_vf_stats *hw_stats = (struct e1000_vf_stats *)
2108                           E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2109
2110         igbvf_read_stats_registers(hw, hw_stats);
2111
2112         if (rte_stats == NULL)
2113                 return -EINVAL;
2114
2115         rte_stats->ipackets = hw_stats->gprc;
2116         rte_stats->ibytes = hw_stats->gorc;
2117         rte_stats->opackets = hw_stats->gptc;
2118         rte_stats->obytes = hw_stats->gotc;
2119         return 0;
2120 }
2121
2122 static void
2123 eth_igbvf_stats_reset(struct rte_eth_dev *dev)
2124 {
2125         struct e1000_vf_stats *hw_stats = (struct e1000_vf_stats*)
2126                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2127
2128         /* Sync HW register to the last stats */
2129         eth_igbvf_stats_get(dev, NULL);
2130
2131         /* reset HW current stats*/
2132         memset(&hw_stats->gprc, 0, sizeof(*hw_stats) -
2133                offsetof(struct e1000_vf_stats, gprc));
2134 }
2135
2136 static int
2137 eth_igb_fw_version_get(struct rte_eth_dev *dev, char *fw_version,
2138                        size_t fw_size)
2139 {
2140         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2141         struct e1000_fw_version fw;
2142         int ret;
2143
2144         e1000_get_fw_version(hw, &fw);
2145
2146         switch (hw->mac.type) {
2147         case e1000_i210:
2148         case e1000_i211:
2149                 if (!(e1000_get_flash_presence_i210(hw))) {
2150                         ret = snprintf(fw_version, fw_size,
2151                                  "%2d.%2d-%d",
2152                                  fw.invm_major, fw.invm_minor,
2153                                  fw.invm_img_type);
2154                         break;
2155                 }
2156                 /* fall through */
2157         default:
2158                 /* if option rom is valid, display its version too */
2159                 if (fw.or_valid) {
2160                         ret = snprintf(fw_version, fw_size,
2161                                  "%d.%d, 0x%08x, %d.%d.%d",
2162                                  fw.eep_major, fw.eep_minor, fw.etrack_id,
2163                                  fw.or_major, fw.or_build, fw.or_patch);
2164                 /* no option rom */
2165                 } else {
2166                         if (fw.etrack_id != 0X0000) {
2167                                 ret = snprintf(fw_version, fw_size,
2168                                          "%d.%d, 0x%08x",
2169                                          fw.eep_major, fw.eep_minor,
2170                                          fw.etrack_id);
2171                         } else {
2172                                 ret = snprintf(fw_version, fw_size,
2173                                          "%d.%d.%d",
2174                                          fw.eep_major, fw.eep_minor,
2175                                          fw.eep_build);
2176                         }
2177                 }
2178                 break;
2179         }
2180
2181         ret += 1; /* add the size of '\0' */
2182         if (fw_size < (u32)ret)
2183                 return ret;
2184         else
2185                 return 0;
2186 }
2187
2188 static void
2189 eth_igb_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
2190 {
2191         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2192
2193         dev_info->pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2194         dev_info->min_rx_bufsize = 256; /* See BSIZE field of RCTL register. */
2195         dev_info->max_rx_pktlen  = 0x3FFF; /* See RLPML register. */
2196         dev_info->max_mac_addrs = hw->mac.rar_entry_count;
2197         dev_info->rx_offload_capa =
2198                 DEV_RX_OFFLOAD_VLAN_STRIP |
2199                 DEV_RX_OFFLOAD_IPV4_CKSUM |
2200                 DEV_RX_OFFLOAD_UDP_CKSUM  |
2201                 DEV_RX_OFFLOAD_TCP_CKSUM;
2202         dev_info->tx_offload_capa =
2203                 DEV_TX_OFFLOAD_VLAN_INSERT |
2204                 DEV_TX_OFFLOAD_IPV4_CKSUM  |
2205                 DEV_TX_OFFLOAD_UDP_CKSUM   |
2206                 DEV_TX_OFFLOAD_TCP_CKSUM   |
2207                 DEV_TX_OFFLOAD_SCTP_CKSUM  |
2208                 DEV_TX_OFFLOAD_TCP_TSO;
2209
2210         switch (hw->mac.type) {
2211         case e1000_82575:
2212                 dev_info->max_rx_queues = 4;
2213                 dev_info->max_tx_queues = 4;
2214                 dev_info->max_vmdq_pools = 0;
2215                 break;
2216
2217         case e1000_82576:
2218                 dev_info->max_rx_queues = 16;
2219                 dev_info->max_tx_queues = 16;
2220                 dev_info->max_vmdq_pools = ETH_8_POOLS;
2221                 dev_info->vmdq_queue_num = 16;
2222                 break;
2223
2224         case e1000_82580:
2225                 dev_info->max_rx_queues = 8;
2226                 dev_info->max_tx_queues = 8;
2227                 dev_info->max_vmdq_pools = ETH_8_POOLS;
2228                 dev_info->vmdq_queue_num = 8;
2229                 break;
2230
2231         case e1000_i350:
2232                 dev_info->max_rx_queues = 8;
2233                 dev_info->max_tx_queues = 8;
2234                 dev_info->max_vmdq_pools = ETH_8_POOLS;
2235                 dev_info->vmdq_queue_num = 8;
2236                 break;
2237
2238         case e1000_i354:
2239                 dev_info->max_rx_queues = 8;
2240                 dev_info->max_tx_queues = 8;
2241                 break;
2242
2243         case e1000_i210:
2244                 dev_info->max_rx_queues = 4;
2245                 dev_info->max_tx_queues = 4;
2246                 dev_info->max_vmdq_pools = 0;
2247                 break;
2248
2249         case e1000_i211:
2250                 dev_info->max_rx_queues = 2;
2251                 dev_info->max_tx_queues = 2;
2252                 dev_info->max_vmdq_pools = 0;
2253                 break;
2254
2255         default:
2256                 /* Should not happen */
2257                 break;
2258         }
2259         dev_info->hash_key_size = IGB_HKEY_MAX_INDEX * sizeof(uint32_t);
2260         dev_info->reta_size = ETH_RSS_RETA_SIZE_128;
2261         dev_info->flow_type_rss_offloads = IGB_RSS_OFFLOAD_ALL;
2262
2263         dev_info->default_rxconf = (struct rte_eth_rxconf) {
2264                 .rx_thresh = {
2265                         .pthresh = IGB_DEFAULT_RX_PTHRESH,
2266                         .hthresh = IGB_DEFAULT_RX_HTHRESH,
2267                         .wthresh = IGB_DEFAULT_RX_WTHRESH,
2268                 },
2269                 .rx_free_thresh = IGB_DEFAULT_RX_FREE_THRESH,
2270                 .rx_drop_en = 0,
2271         };
2272
2273         dev_info->default_txconf = (struct rte_eth_txconf) {
2274                 .tx_thresh = {
2275                         .pthresh = IGB_DEFAULT_TX_PTHRESH,
2276                         .hthresh = IGB_DEFAULT_TX_HTHRESH,
2277                         .wthresh = IGB_DEFAULT_TX_WTHRESH,
2278                 },
2279                 .txq_flags = 0,
2280         };
2281
2282         dev_info->rx_desc_lim = rx_desc_lim;
2283         dev_info->tx_desc_lim = tx_desc_lim;
2284
2285         dev_info->speed_capa = ETH_LINK_SPEED_10M_HD | ETH_LINK_SPEED_10M |
2286                         ETH_LINK_SPEED_100M_HD | ETH_LINK_SPEED_100M |
2287                         ETH_LINK_SPEED_1G;
2288 }
2289
2290 static const uint32_t *
2291 eth_igb_supported_ptypes_get(struct rte_eth_dev *dev)
2292 {
2293         static const uint32_t ptypes[] = {
2294                 /* refers to igb_rxd_pkt_info_to_pkt_type() */
2295                 RTE_PTYPE_L2_ETHER,
2296                 RTE_PTYPE_L3_IPV4,
2297                 RTE_PTYPE_L3_IPV4_EXT,
2298                 RTE_PTYPE_L3_IPV6,
2299                 RTE_PTYPE_L3_IPV6_EXT,
2300                 RTE_PTYPE_L4_TCP,
2301                 RTE_PTYPE_L4_UDP,
2302                 RTE_PTYPE_L4_SCTP,
2303                 RTE_PTYPE_TUNNEL_IP,
2304                 RTE_PTYPE_INNER_L3_IPV6,
2305                 RTE_PTYPE_INNER_L3_IPV6_EXT,
2306                 RTE_PTYPE_INNER_L4_TCP,
2307                 RTE_PTYPE_INNER_L4_UDP,
2308                 RTE_PTYPE_UNKNOWN
2309         };
2310
2311         if (dev->rx_pkt_burst == eth_igb_recv_pkts ||
2312             dev->rx_pkt_burst == eth_igb_recv_scattered_pkts)
2313                 return ptypes;
2314         return NULL;
2315 }
2316
2317 static void
2318 eth_igbvf_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
2319 {
2320         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2321
2322         dev_info->pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2323         dev_info->min_rx_bufsize = 256; /* See BSIZE field of RCTL register. */
2324         dev_info->max_rx_pktlen  = 0x3FFF; /* See RLPML register. */
2325         dev_info->max_mac_addrs = hw->mac.rar_entry_count;
2326         dev_info->rx_offload_capa = DEV_RX_OFFLOAD_VLAN_STRIP |
2327                                 DEV_RX_OFFLOAD_IPV4_CKSUM |
2328                                 DEV_RX_OFFLOAD_UDP_CKSUM  |
2329                                 DEV_RX_OFFLOAD_TCP_CKSUM;
2330         dev_info->tx_offload_capa = DEV_TX_OFFLOAD_VLAN_INSERT |
2331                                 DEV_TX_OFFLOAD_IPV4_CKSUM  |
2332                                 DEV_TX_OFFLOAD_UDP_CKSUM   |
2333                                 DEV_TX_OFFLOAD_TCP_CKSUM   |
2334                                 DEV_TX_OFFLOAD_SCTP_CKSUM  |
2335                                 DEV_TX_OFFLOAD_TCP_TSO;
2336         switch (hw->mac.type) {
2337         case e1000_vfadapt:
2338                 dev_info->max_rx_queues = 2;
2339                 dev_info->max_tx_queues = 2;
2340                 break;
2341         case e1000_vfadapt_i350:
2342                 dev_info->max_rx_queues = 1;
2343                 dev_info->max_tx_queues = 1;
2344                 break;
2345         default:
2346                 /* Should not happen */
2347                 break;
2348         }
2349
2350         dev_info->default_rxconf = (struct rte_eth_rxconf) {
2351                 .rx_thresh = {
2352                         .pthresh = IGB_DEFAULT_RX_PTHRESH,
2353                         .hthresh = IGB_DEFAULT_RX_HTHRESH,
2354                         .wthresh = IGB_DEFAULT_RX_WTHRESH,
2355                 },
2356                 .rx_free_thresh = IGB_DEFAULT_RX_FREE_THRESH,
2357                 .rx_drop_en = 0,
2358         };
2359
2360         dev_info->default_txconf = (struct rte_eth_txconf) {
2361                 .tx_thresh = {
2362                         .pthresh = IGB_DEFAULT_TX_PTHRESH,
2363                         .hthresh = IGB_DEFAULT_TX_HTHRESH,
2364                         .wthresh = IGB_DEFAULT_TX_WTHRESH,
2365                 },
2366                 .txq_flags = 0,
2367         };
2368
2369         dev_info->rx_desc_lim = rx_desc_lim;
2370         dev_info->tx_desc_lim = tx_desc_lim;
2371 }
2372
2373 /* return 0 means link status changed, -1 means not changed */
2374 static int
2375 eth_igb_link_update(struct rte_eth_dev *dev, int wait_to_complete)
2376 {
2377         struct e1000_hw *hw =
2378                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2379         struct rte_eth_link link, old;
2380         int link_check, count;
2381
2382         link_check = 0;
2383         hw->mac.get_link_status = 1;
2384
2385         /* possible wait-to-complete in up to 9 seconds */
2386         for (count = 0; count < IGB_LINK_UPDATE_CHECK_TIMEOUT; count ++) {
2387                 /* Read the real link status */
2388                 switch (hw->phy.media_type) {
2389                 case e1000_media_type_copper:
2390                         /* Do the work to read phy */
2391                         e1000_check_for_link(hw);
2392                         link_check = !hw->mac.get_link_status;
2393                         break;
2394
2395                 case e1000_media_type_fiber:
2396                         e1000_check_for_link(hw);
2397                         link_check = (E1000_READ_REG(hw, E1000_STATUS) &
2398                                       E1000_STATUS_LU);
2399                         break;
2400
2401                 case e1000_media_type_internal_serdes:
2402                         e1000_check_for_link(hw);
2403                         link_check = hw->mac.serdes_has_link;
2404                         break;
2405
2406                 /* VF device is type_unknown */
2407                 case e1000_media_type_unknown:
2408                         eth_igbvf_link_update(hw);
2409                         link_check = !hw->mac.get_link_status;
2410                         break;
2411
2412                 default:
2413                         break;
2414                 }
2415                 if (link_check || wait_to_complete == 0)
2416                         break;
2417                 rte_delay_ms(IGB_LINK_UPDATE_CHECK_INTERVAL);
2418         }
2419         memset(&link, 0, sizeof(link));
2420         rte_igb_dev_atomic_read_link_status(dev, &link);
2421         old = link;
2422
2423         /* Now we check if a transition has happened */
2424         if (link_check) {
2425                 uint16_t duplex, speed;
2426                 hw->mac.ops.get_link_up_info(hw, &speed, &duplex);
2427                 link.link_duplex = (duplex == FULL_DUPLEX) ?
2428                                 ETH_LINK_FULL_DUPLEX :
2429                                 ETH_LINK_HALF_DUPLEX;
2430                 link.link_speed = speed;
2431                 link.link_status = ETH_LINK_UP;
2432                 link.link_autoneg = !(dev->data->dev_conf.link_speeds &
2433                                 ETH_LINK_SPEED_FIXED);
2434         } else if (!link_check) {
2435                 link.link_speed = 0;
2436                 link.link_duplex = ETH_LINK_HALF_DUPLEX;
2437                 link.link_status = ETH_LINK_DOWN;
2438                 link.link_autoneg = ETH_LINK_SPEED_FIXED;
2439         }
2440         rte_igb_dev_atomic_write_link_status(dev, &link);
2441
2442         /* not changed */
2443         if (old.link_status == link.link_status)
2444                 return -1;
2445
2446         /* changed */
2447         return 0;
2448 }
2449
2450 /*
2451  * igb_hw_control_acquire sets CTRL_EXT:DRV_LOAD bit.
2452  * For ASF and Pass Through versions of f/w this means
2453  * that the driver is loaded.
2454  */
2455 static void
2456 igb_hw_control_acquire(struct e1000_hw *hw)
2457 {
2458         uint32_t ctrl_ext;
2459
2460         /* Let firmware know the driver has taken over */
2461         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
2462         E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
2463 }
2464
2465 /*
2466  * igb_hw_control_release resets CTRL_EXT:DRV_LOAD bit.
2467  * For ASF and Pass Through versions of f/w this means that the
2468  * driver is no longer loaded.
2469  */
2470 static void
2471 igb_hw_control_release(struct e1000_hw *hw)
2472 {
2473         uint32_t ctrl_ext;
2474
2475         /* Let firmware taken over control of h/w */
2476         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
2477         E1000_WRITE_REG(hw, E1000_CTRL_EXT,
2478                         ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
2479 }
2480
2481 /*
2482  * Bit of a misnomer, what this really means is
2483  * to enable OS management of the system... aka
2484  * to disable special hardware management features.
2485  */
2486 static void
2487 igb_init_manageability(struct e1000_hw *hw)
2488 {
2489         if (e1000_enable_mng_pass_thru(hw)) {
2490                 uint32_t manc2h = E1000_READ_REG(hw, E1000_MANC2H);
2491                 uint32_t manc = E1000_READ_REG(hw, E1000_MANC);
2492
2493                 /* disable hardware interception of ARP */
2494                 manc &= ~(E1000_MANC_ARP_EN);
2495
2496                 /* enable receiving management packets to the host */
2497                 manc |= E1000_MANC_EN_MNG2HOST;
2498                 manc2h |= 1 << 5;  /* Mng Port 623 */
2499                 manc2h |= 1 << 6;  /* Mng Port 664 */
2500                 E1000_WRITE_REG(hw, E1000_MANC2H, manc2h);
2501                 E1000_WRITE_REG(hw, E1000_MANC, manc);
2502         }
2503 }
2504
2505 static void
2506 igb_release_manageability(struct e1000_hw *hw)
2507 {
2508         if (e1000_enable_mng_pass_thru(hw)) {
2509                 uint32_t manc = E1000_READ_REG(hw, E1000_MANC);
2510
2511                 manc |= E1000_MANC_ARP_EN;
2512                 manc &= ~E1000_MANC_EN_MNG2HOST;
2513
2514                 E1000_WRITE_REG(hw, E1000_MANC, manc);
2515         }
2516 }
2517
2518 static void
2519 eth_igb_promiscuous_enable(struct rte_eth_dev *dev)
2520 {
2521         struct e1000_hw *hw =
2522                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2523         uint32_t rctl;
2524
2525         rctl = E1000_READ_REG(hw, E1000_RCTL);
2526         rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
2527         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2528 }
2529
2530 static void
2531 eth_igb_promiscuous_disable(struct rte_eth_dev *dev)
2532 {
2533         struct e1000_hw *hw =
2534                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2535         uint32_t rctl;
2536
2537         rctl = E1000_READ_REG(hw, E1000_RCTL);
2538         rctl &= (~E1000_RCTL_UPE);
2539         if (dev->data->all_multicast == 1)
2540                 rctl |= E1000_RCTL_MPE;
2541         else
2542                 rctl &= (~E1000_RCTL_MPE);
2543         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2544 }
2545
2546 static void
2547 eth_igb_allmulticast_enable(struct rte_eth_dev *dev)
2548 {
2549         struct e1000_hw *hw =
2550                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2551         uint32_t rctl;
2552
2553         rctl = E1000_READ_REG(hw, E1000_RCTL);
2554         rctl |= E1000_RCTL_MPE;
2555         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2556 }
2557
2558 static void
2559 eth_igb_allmulticast_disable(struct rte_eth_dev *dev)
2560 {
2561         struct e1000_hw *hw =
2562                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2563         uint32_t rctl;
2564
2565         if (dev->data->promiscuous == 1)
2566                 return; /* must remain in all_multicast mode */
2567         rctl = E1000_READ_REG(hw, E1000_RCTL);
2568         rctl &= (~E1000_RCTL_MPE);
2569         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2570 }
2571
2572 static int
2573 eth_igb_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
2574 {
2575         struct e1000_hw *hw =
2576                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2577         struct e1000_vfta * shadow_vfta =
2578                 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
2579         uint32_t vfta;
2580         uint32_t vid_idx;
2581         uint32_t vid_bit;
2582
2583         vid_idx = (uint32_t) ((vlan_id >> E1000_VFTA_ENTRY_SHIFT) &
2584                               E1000_VFTA_ENTRY_MASK);
2585         vid_bit = (uint32_t) (1 << (vlan_id & E1000_VFTA_ENTRY_BIT_SHIFT_MASK));
2586         vfta = E1000_READ_REG_ARRAY(hw, E1000_VFTA, vid_idx);
2587         if (on)
2588                 vfta |= vid_bit;
2589         else
2590                 vfta &= ~vid_bit;
2591         E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, vid_idx, vfta);
2592
2593         /* update local VFTA copy */
2594         shadow_vfta->vfta[vid_idx] = vfta;
2595
2596         return 0;
2597 }
2598
2599 static int
2600 eth_igb_vlan_tpid_set(struct rte_eth_dev *dev,
2601                       enum rte_vlan_type vlan_type,
2602                       uint16_t tpid)
2603 {
2604         struct e1000_hw *hw =
2605                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2606         uint32_t reg, qinq;
2607
2608         qinq = E1000_READ_REG(hw, E1000_CTRL_EXT);
2609         qinq &= E1000_CTRL_EXT_EXT_VLAN;
2610
2611         /* only outer TPID of double VLAN can be configured*/
2612         if (qinq && vlan_type == ETH_VLAN_TYPE_OUTER) {
2613                 reg = E1000_READ_REG(hw, E1000_VET);
2614                 reg = (reg & (~E1000_VET_VET_EXT)) |
2615                         ((uint32_t)tpid << E1000_VET_VET_EXT_SHIFT);
2616                 E1000_WRITE_REG(hw, E1000_VET, reg);
2617
2618                 return 0;
2619         }
2620
2621         /* all other TPID values are read-only*/
2622         PMD_DRV_LOG(ERR, "Not supported");
2623
2624         return -ENOTSUP;
2625 }
2626
2627 static void
2628 igb_vlan_hw_filter_disable(struct rte_eth_dev *dev)
2629 {
2630         struct e1000_hw *hw =
2631                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2632         uint32_t reg;
2633
2634         /* Filter Table Disable */
2635         reg = E1000_READ_REG(hw, E1000_RCTL);
2636         reg &= ~E1000_RCTL_CFIEN;
2637         reg &= ~E1000_RCTL_VFE;
2638         E1000_WRITE_REG(hw, E1000_RCTL, reg);
2639 }
2640
2641 static void
2642 igb_vlan_hw_filter_enable(struct rte_eth_dev *dev)
2643 {
2644         struct e1000_hw *hw =
2645                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2646         struct e1000_vfta * shadow_vfta =
2647                 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
2648         uint32_t reg;
2649         int i;
2650
2651         /* Filter Table Enable, CFI not used for packet acceptance */
2652         reg = E1000_READ_REG(hw, E1000_RCTL);
2653         reg &= ~E1000_RCTL_CFIEN;
2654         reg |= E1000_RCTL_VFE;
2655         E1000_WRITE_REG(hw, E1000_RCTL, reg);
2656
2657         /* restore VFTA table */
2658         for (i = 0; i < IGB_VFTA_SIZE; i++)
2659                 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, i, shadow_vfta->vfta[i]);
2660 }
2661
2662 static void
2663 igb_vlan_hw_strip_disable(struct rte_eth_dev *dev)
2664 {
2665         struct e1000_hw *hw =
2666                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2667         uint32_t reg;
2668
2669         /* VLAN Mode Disable */
2670         reg = E1000_READ_REG(hw, E1000_CTRL);
2671         reg &= ~E1000_CTRL_VME;
2672         E1000_WRITE_REG(hw, E1000_CTRL, reg);
2673 }
2674
2675 static void
2676 igb_vlan_hw_strip_enable(struct rte_eth_dev *dev)
2677 {
2678         struct e1000_hw *hw =
2679                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2680         uint32_t reg;
2681
2682         /* VLAN Mode Enable */
2683         reg = E1000_READ_REG(hw, E1000_CTRL);
2684         reg |= E1000_CTRL_VME;
2685         E1000_WRITE_REG(hw, E1000_CTRL, reg);
2686 }
2687
2688 static void
2689 igb_vlan_hw_extend_disable(struct rte_eth_dev *dev)
2690 {
2691         struct e1000_hw *hw =
2692                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2693         uint32_t reg;
2694
2695         /* CTRL_EXT: Extended VLAN */
2696         reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
2697         reg &= ~E1000_CTRL_EXT_EXTEND_VLAN;
2698         E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg);
2699
2700         /* Update maximum packet length */
2701         if (dev->data->dev_conf.rxmode.jumbo_frame == 1)
2702                 E1000_WRITE_REG(hw, E1000_RLPML,
2703                         dev->data->dev_conf.rxmode.max_rx_pkt_len +
2704                                                 VLAN_TAG_SIZE);
2705 }
2706
2707 static void
2708 igb_vlan_hw_extend_enable(struct rte_eth_dev *dev)
2709 {
2710         struct e1000_hw *hw =
2711                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2712         uint32_t reg;
2713
2714         /* CTRL_EXT: Extended VLAN */
2715         reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
2716         reg |= E1000_CTRL_EXT_EXTEND_VLAN;
2717         E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg);
2718
2719         /* Update maximum packet length */
2720         if (dev->data->dev_conf.rxmode.jumbo_frame == 1)
2721                 E1000_WRITE_REG(hw, E1000_RLPML,
2722                         dev->data->dev_conf.rxmode.max_rx_pkt_len +
2723                                                 2 * VLAN_TAG_SIZE);
2724 }
2725
2726 static int
2727 eth_igb_vlan_offload_set(struct rte_eth_dev *dev, int mask)
2728 {
2729         if(mask & ETH_VLAN_STRIP_MASK){
2730                 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
2731                         igb_vlan_hw_strip_enable(dev);
2732                 else
2733                         igb_vlan_hw_strip_disable(dev);
2734         }
2735
2736         if(mask & ETH_VLAN_FILTER_MASK){
2737                 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
2738                         igb_vlan_hw_filter_enable(dev);
2739                 else
2740                         igb_vlan_hw_filter_disable(dev);
2741         }
2742
2743         if(mask & ETH_VLAN_EXTEND_MASK){
2744                 if (dev->data->dev_conf.rxmode.hw_vlan_extend)
2745                         igb_vlan_hw_extend_enable(dev);
2746                 else
2747                         igb_vlan_hw_extend_disable(dev);
2748         }
2749
2750         return 0;
2751 }
2752
2753
2754 /**
2755  * It enables the interrupt mask and then enable the interrupt.
2756  *
2757  * @param dev
2758  *  Pointer to struct rte_eth_dev.
2759  * @param on
2760  *  Enable or Disable
2761  *
2762  * @return
2763  *  - On success, zero.
2764  *  - On failure, a negative value.
2765  */
2766 static int
2767 eth_igb_lsc_interrupt_setup(struct rte_eth_dev *dev, uint8_t on)
2768 {
2769         struct e1000_interrupt *intr =
2770                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2771
2772         if (on)
2773                 intr->mask |= E1000_ICR_LSC;
2774         else
2775                 intr->mask &= ~E1000_ICR_LSC;
2776
2777         return 0;
2778 }
2779
2780 /* It clears the interrupt causes and enables the interrupt.
2781  * It will be called once only during nic initialized.
2782  *
2783  * @param dev
2784  *  Pointer to struct rte_eth_dev.
2785  *
2786  * @return
2787  *  - On success, zero.
2788  *  - On failure, a negative value.
2789  */
2790 static int eth_igb_rxq_interrupt_setup(struct rte_eth_dev *dev)
2791 {
2792         uint32_t mask, regval;
2793         struct e1000_hw *hw =
2794                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2795         struct rte_eth_dev_info dev_info;
2796
2797         memset(&dev_info, 0, sizeof(dev_info));
2798         eth_igb_infos_get(dev, &dev_info);
2799
2800         mask = 0xFFFFFFFF >> (32 - dev_info.max_rx_queues);
2801         regval = E1000_READ_REG(hw, E1000_EIMS);
2802         E1000_WRITE_REG(hw, E1000_EIMS, regval | mask);
2803
2804         return 0;
2805 }
2806
2807 /*
2808  * It reads ICR and gets interrupt causes, check it and set a bit flag
2809  * to update link status.
2810  *
2811  * @param dev
2812  *  Pointer to struct rte_eth_dev.
2813  *
2814  * @return
2815  *  - On success, zero.
2816  *  - On failure, a negative value.
2817  */
2818 static int
2819 eth_igb_interrupt_get_status(struct rte_eth_dev *dev)
2820 {
2821         uint32_t icr;
2822         struct e1000_hw *hw =
2823                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2824         struct e1000_interrupt *intr =
2825                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2826
2827         igb_intr_disable(hw);
2828
2829         /* read-on-clear nic registers here */
2830         icr = E1000_READ_REG(hw, E1000_ICR);
2831
2832         intr->flags = 0;
2833         if (icr & E1000_ICR_LSC) {
2834                 intr->flags |= E1000_FLAG_NEED_LINK_UPDATE;
2835         }
2836
2837         if (icr & E1000_ICR_VMMB)
2838                 intr->flags |= E1000_FLAG_MAILBOX;
2839
2840         return 0;
2841 }
2842
2843 /*
2844  * It executes link_update after knowing an interrupt is prsent.
2845  *
2846  * @param dev
2847  *  Pointer to struct rte_eth_dev.
2848  *
2849  * @return
2850  *  - On success, zero.
2851  *  - On failure, a negative value.
2852  */
2853 static int
2854 eth_igb_interrupt_action(struct rte_eth_dev *dev,
2855                          struct rte_intr_handle *intr_handle)
2856 {
2857         struct e1000_hw *hw =
2858                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2859         struct e1000_interrupt *intr =
2860                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2861         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2862         uint32_t tctl, rctl;
2863         struct rte_eth_link link;
2864         int ret;
2865
2866         if (intr->flags & E1000_FLAG_MAILBOX) {
2867                 igb_pf_mbx_process(dev);
2868                 intr->flags &= ~E1000_FLAG_MAILBOX;
2869         }
2870
2871         igb_intr_enable(dev);
2872         rte_intr_enable(intr_handle);
2873
2874         if (intr->flags & E1000_FLAG_NEED_LINK_UPDATE) {
2875                 intr->flags &= ~E1000_FLAG_NEED_LINK_UPDATE;
2876
2877                 /* set get_link_status to check register later */
2878                 hw->mac.get_link_status = 1;
2879                 ret = eth_igb_link_update(dev, 0);
2880
2881                 /* check if link has changed */
2882                 if (ret < 0)
2883                         return 0;
2884
2885                 memset(&link, 0, sizeof(link));
2886                 rte_igb_dev_atomic_read_link_status(dev, &link);
2887                 if (link.link_status) {
2888                         PMD_INIT_LOG(INFO,
2889                                      " Port %d: Link Up - speed %u Mbps - %s",
2890                                      dev->data->port_id,
2891                                      (unsigned)link.link_speed,
2892                                      link.link_duplex == ETH_LINK_FULL_DUPLEX ?
2893                                      "full-duplex" : "half-duplex");
2894                 } else {
2895                         PMD_INIT_LOG(INFO, " Port %d: Link Down",
2896                                      dev->data->port_id);
2897                 }
2898
2899                 PMD_INIT_LOG(DEBUG, "PCI Address: %04d:%02d:%02d:%d",
2900                              pci_dev->addr.domain,
2901                              pci_dev->addr.bus,
2902                              pci_dev->addr.devid,
2903                              pci_dev->addr.function);
2904                 tctl = E1000_READ_REG(hw, E1000_TCTL);
2905                 rctl = E1000_READ_REG(hw, E1000_RCTL);
2906                 if (link.link_status) {
2907                         /* enable Tx/Rx */
2908                         tctl |= E1000_TCTL_EN;
2909                         rctl |= E1000_RCTL_EN;
2910                 } else {
2911                         /* disable Tx/Rx */
2912                         tctl &= ~E1000_TCTL_EN;
2913                         rctl &= ~E1000_RCTL_EN;
2914                 }
2915                 E1000_WRITE_REG(hw, E1000_TCTL, tctl);
2916                 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2917                 E1000_WRITE_FLUSH(hw);
2918                 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC,
2919                                               NULL, NULL);
2920         }
2921
2922         return 0;
2923 }
2924
2925 /**
2926  * Interrupt handler which shall be registered at first.
2927  *
2928  * @param handle
2929  *  Pointer to interrupt handle.
2930  * @param param
2931  *  The address of parameter (struct rte_eth_dev *) regsitered before.
2932  *
2933  * @return
2934  *  void
2935  */
2936 static void
2937 eth_igb_interrupt_handler(void *param)
2938 {
2939         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
2940
2941         eth_igb_interrupt_get_status(dev);
2942         eth_igb_interrupt_action(dev, dev->intr_handle);
2943 }
2944
2945 static int
2946 eth_igbvf_interrupt_get_status(struct rte_eth_dev *dev)
2947 {
2948         uint32_t eicr;
2949         struct e1000_hw *hw =
2950                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2951         struct e1000_interrupt *intr =
2952                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2953
2954         igbvf_intr_disable(hw);
2955
2956         /* read-on-clear nic registers here */
2957         eicr = E1000_READ_REG(hw, E1000_EICR);
2958         intr->flags = 0;
2959
2960         if (eicr == E1000_VTIVAR_MISC_MAILBOX)
2961                 intr->flags |= E1000_FLAG_MAILBOX;
2962
2963         return 0;
2964 }
2965
2966 void igbvf_mbx_process(struct rte_eth_dev *dev)
2967 {
2968         struct e1000_hw *hw =
2969                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2970         struct e1000_mbx_info *mbx = &hw->mbx;
2971         u32 in_msg = 0;
2972
2973         if (mbx->ops.read(hw, &in_msg, 1, 0))
2974                 return;
2975
2976         /* PF reset VF event */
2977         if (in_msg == E1000_PF_CONTROL_MSG)
2978                 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_RESET,
2979                                               NULL, NULL);
2980 }
2981
2982 static int
2983 eth_igbvf_interrupt_action(struct rte_eth_dev *dev, struct rte_intr_handle *intr_handle)
2984 {
2985         struct e1000_interrupt *intr =
2986                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2987
2988         if (intr->flags & E1000_FLAG_MAILBOX) {
2989                 igbvf_mbx_process(dev);
2990                 intr->flags &= ~E1000_FLAG_MAILBOX;
2991         }
2992
2993         igbvf_intr_enable(dev);
2994         rte_intr_enable(intr_handle);
2995
2996         return 0;
2997 }
2998
2999 static void
3000 eth_igbvf_interrupt_handler(void *param)
3001 {
3002         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
3003
3004         eth_igbvf_interrupt_get_status(dev);
3005         eth_igbvf_interrupt_action(dev, dev->intr_handle);
3006 }
3007
3008 static int
3009 eth_igb_led_on(struct rte_eth_dev *dev)
3010 {
3011         struct e1000_hw *hw;
3012
3013         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3014         return e1000_led_on(hw) == E1000_SUCCESS ? 0 : -ENOTSUP;
3015 }
3016
3017 static int
3018 eth_igb_led_off(struct rte_eth_dev *dev)
3019 {
3020         struct e1000_hw *hw;
3021
3022         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3023         return e1000_led_off(hw) == E1000_SUCCESS ? 0 : -ENOTSUP;
3024 }
3025
3026 static int
3027 eth_igb_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3028 {
3029         struct e1000_hw *hw;
3030         uint32_t ctrl;
3031         int tx_pause;
3032         int rx_pause;
3033
3034         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3035         fc_conf->pause_time = hw->fc.pause_time;
3036         fc_conf->high_water = hw->fc.high_water;
3037         fc_conf->low_water = hw->fc.low_water;
3038         fc_conf->send_xon = hw->fc.send_xon;
3039         fc_conf->autoneg = hw->mac.autoneg;
3040
3041         /*
3042          * Return rx_pause and tx_pause status according to actual setting of
3043          * the TFCE and RFCE bits in the CTRL register.
3044          */
3045         ctrl = E1000_READ_REG(hw, E1000_CTRL);
3046         if (ctrl & E1000_CTRL_TFCE)
3047                 tx_pause = 1;
3048         else
3049                 tx_pause = 0;
3050
3051         if (ctrl & E1000_CTRL_RFCE)
3052                 rx_pause = 1;
3053         else
3054                 rx_pause = 0;
3055
3056         if (rx_pause && tx_pause)
3057                 fc_conf->mode = RTE_FC_FULL;
3058         else if (rx_pause)
3059                 fc_conf->mode = RTE_FC_RX_PAUSE;
3060         else if (tx_pause)
3061                 fc_conf->mode = RTE_FC_TX_PAUSE;
3062         else
3063                 fc_conf->mode = RTE_FC_NONE;
3064
3065         return 0;
3066 }
3067
3068 static int
3069 eth_igb_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3070 {
3071         struct e1000_hw *hw;
3072         int err;
3073         enum e1000_fc_mode rte_fcmode_2_e1000_fcmode[] = {
3074                 e1000_fc_none,
3075                 e1000_fc_rx_pause,
3076                 e1000_fc_tx_pause,
3077                 e1000_fc_full
3078         };
3079         uint32_t rx_buf_size;
3080         uint32_t max_high_water;
3081         uint32_t rctl;
3082
3083         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3084         if (fc_conf->autoneg != hw->mac.autoneg)
3085                 return -ENOTSUP;
3086         rx_buf_size = igb_get_rx_buffer_size(hw);
3087         PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
3088
3089         /* At least reserve one Ethernet frame for watermark */
3090         max_high_water = rx_buf_size - ETHER_MAX_LEN;
3091         if ((fc_conf->high_water > max_high_water) ||
3092             (fc_conf->high_water < fc_conf->low_water)) {
3093                 PMD_INIT_LOG(ERR, "e1000 incorrect high/low water value");
3094                 PMD_INIT_LOG(ERR, "high water must <=  0x%x", max_high_water);
3095                 return -EINVAL;
3096         }
3097
3098         hw->fc.requested_mode = rte_fcmode_2_e1000_fcmode[fc_conf->mode];
3099         hw->fc.pause_time     = fc_conf->pause_time;
3100         hw->fc.high_water     = fc_conf->high_water;
3101         hw->fc.low_water      = fc_conf->low_water;
3102         hw->fc.send_xon       = fc_conf->send_xon;
3103
3104         err = e1000_setup_link_generic(hw);
3105         if (err == E1000_SUCCESS) {
3106
3107                 /* check if we want to forward MAC frames - driver doesn't have native
3108                  * capability to do that, so we'll write the registers ourselves */
3109
3110                 rctl = E1000_READ_REG(hw, E1000_RCTL);
3111
3112                 /* set or clear MFLCN.PMCF bit depending on configuration */
3113                 if (fc_conf->mac_ctrl_frame_fwd != 0)
3114                         rctl |= E1000_RCTL_PMCF;
3115                 else
3116                         rctl &= ~E1000_RCTL_PMCF;
3117
3118                 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
3119                 E1000_WRITE_FLUSH(hw);
3120
3121                 return 0;
3122         }
3123
3124         PMD_INIT_LOG(ERR, "e1000_setup_link_generic = 0x%x", err);
3125         return -EIO;
3126 }
3127
3128 #define E1000_RAH_POOLSEL_SHIFT      (18)
3129 static int
3130 eth_igb_rar_set(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
3131                 uint32_t index, uint32_t pool)
3132 {
3133         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3134         uint32_t rah;
3135
3136         e1000_rar_set(hw, mac_addr->addr_bytes, index);
3137         rah = E1000_READ_REG(hw, E1000_RAH(index));
3138         rah |= (0x1 << (E1000_RAH_POOLSEL_SHIFT + pool));
3139         E1000_WRITE_REG(hw, E1000_RAH(index), rah);
3140         return 0;
3141 }
3142
3143 static void
3144 eth_igb_rar_clear(struct rte_eth_dev *dev, uint32_t index)
3145 {
3146         uint8_t addr[ETHER_ADDR_LEN];
3147         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3148
3149         memset(addr, 0, sizeof(addr));
3150
3151         e1000_rar_set(hw, addr, index);
3152 }
3153
3154 static void
3155 eth_igb_default_mac_addr_set(struct rte_eth_dev *dev,
3156                                 struct ether_addr *addr)
3157 {
3158         eth_igb_rar_clear(dev, 0);
3159
3160         eth_igb_rar_set(dev, (void *)addr, 0, 0);
3161 }
3162 /*
3163  * Virtual Function operations
3164  */
3165 static void
3166 igbvf_intr_disable(struct e1000_hw *hw)
3167 {
3168         PMD_INIT_FUNC_TRACE();
3169
3170         /* Clear interrupt mask to stop from interrupts being generated */
3171         E1000_WRITE_REG(hw, E1000_EIMC, 0xFFFF);
3172
3173         E1000_WRITE_FLUSH(hw);
3174 }
3175
3176 static void
3177 igbvf_stop_adapter(struct rte_eth_dev *dev)
3178 {
3179         u32 reg_val;
3180         u16 i;
3181         struct rte_eth_dev_info dev_info;
3182         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3183
3184         memset(&dev_info, 0, sizeof(dev_info));
3185         eth_igbvf_infos_get(dev, &dev_info);
3186
3187         /* Clear interrupt mask to stop from interrupts being generated */
3188         igbvf_intr_disable(hw);
3189
3190         /* Clear any pending interrupts, flush previous writes */
3191         E1000_READ_REG(hw, E1000_EICR);
3192
3193         /* Disable the transmit unit.  Each queue must be disabled. */
3194         for (i = 0; i < dev_info.max_tx_queues; i++)
3195                 E1000_WRITE_REG(hw, E1000_TXDCTL(i), E1000_TXDCTL_SWFLSH);
3196
3197         /* Disable the receive unit by stopping each queue */
3198         for (i = 0; i < dev_info.max_rx_queues; i++) {
3199                 reg_val = E1000_READ_REG(hw, E1000_RXDCTL(i));
3200                 reg_val &= ~E1000_RXDCTL_QUEUE_ENABLE;
3201                 E1000_WRITE_REG(hw, E1000_RXDCTL(i), reg_val);
3202                 while (E1000_READ_REG(hw, E1000_RXDCTL(i)) & E1000_RXDCTL_QUEUE_ENABLE)
3203                         ;
3204         }
3205
3206         /* flush all queues disables */
3207         E1000_WRITE_FLUSH(hw);
3208         msec_delay(2);
3209 }
3210
3211 static int eth_igbvf_link_update(struct e1000_hw *hw)
3212 {
3213         struct e1000_mbx_info *mbx = &hw->mbx;
3214         struct e1000_mac_info *mac = &hw->mac;
3215         int ret_val = E1000_SUCCESS;
3216
3217         PMD_INIT_LOG(DEBUG, "e1000_check_for_link_vf");
3218
3219         /*
3220          * We only want to run this if there has been a rst asserted.
3221          * in this case that could mean a link change, device reset,
3222          * or a virtual function reset
3223          */
3224
3225         /* If we were hit with a reset or timeout drop the link */
3226         if (!e1000_check_for_rst(hw, 0) || !mbx->timeout)
3227                 mac->get_link_status = TRUE;
3228
3229         if (!mac->get_link_status)
3230                 goto out;
3231
3232         /* if link status is down no point in checking to see if pf is up */
3233         if (!(E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU))
3234                 goto out;
3235
3236         /* if we passed all the tests above then the link is up and we no
3237          * longer need to check for link */
3238         mac->get_link_status = FALSE;
3239
3240 out:
3241         return ret_val;
3242 }
3243
3244
3245 static int
3246 igbvf_dev_configure(struct rte_eth_dev *dev)
3247 {
3248         struct rte_eth_conf* conf = &dev->data->dev_conf;
3249
3250         PMD_INIT_LOG(DEBUG, "Configured Virtual Function port id: %d",
3251                      dev->data->port_id);
3252
3253         /*
3254          * VF has no ability to enable/disable HW CRC
3255          * Keep the persistent behavior the same as Host PF
3256          */
3257 #ifndef RTE_LIBRTE_E1000_PF_DISABLE_STRIP_CRC
3258         if (!conf->rxmode.hw_strip_crc) {
3259                 PMD_INIT_LOG(NOTICE, "VF can't disable HW CRC Strip");
3260                 conf->rxmode.hw_strip_crc = 1;
3261         }
3262 #else
3263         if (conf->rxmode.hw_strip_crc) {
3264                 PMD_INIT_LOG(NOTICE, "VF can't enable HW CRC Strip");
3265                 conf->rxmode.hw_strip_crc = 0;
3266         }
3267 #endif
3268
3269         return 0;
3270 }
3271
3272 static int
3273 igbvf_dev_start(struct rte_eth_dev *dev)
3274 {
3275         struct e1000_hw *hw =
3276                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3277         struct e1000_adapter *adapter =
3278                 E1000_DEV_PRIVATE(dev->data->dev_private);
3279         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3280         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
3281         int ret;
3282         uint32_t intr_vector = 0;
3283
3284         PMD_INIT_FUNC_TRACE();
3285
3286         hw->mac.ops.reset_hw(hw);
3287         adapter->stopped = 0;
3288
3289         /* Set all vfta */
3290         igbvf_set_vfta_all(dev,1);
3291
3292         eth_igbvf_tx_init(dev);
3293
3294         /* This can fail when allocating mbufs for descriptor rings */
3295         ret = eth_igbvf_rx_init(dev);
3296         if (ret) {
3297                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
3298                 igb_dev_clear_queues(dev);
3299                 return ret;
3300         }
3301
3302         /* check and configure queue intr-vector mapping */
3303         if (dev->data->dev_conf.intr_conf.rxq != 0) {
3304                 intr_vector = dev->data->nb_rx_queues;
3305                 ret = rte_intr_efd_enable(intr_handle, intr_vector);
3306                 if (ret)
3307                         return ret;
3308         }
3309
3310         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
3311                 intr_handle->intr_vec =
3312                         rte_zmalloc("intr_vec",
3313                                     dev->data->nb_rx_queues * sizeof(int), 0);
3314                 if (!intr_handle->intr_vec) {
3315                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
3316                                      " intr_vec", dev->data->nb_rx_queues);
3317                         return -ENOMEM;
3318                 }
3319         }
3320
3321         eth_igbvf_configure_msix_intr(dev);
3322
3323         /* enable uio/vfio intr/eventfd mapping */
3324         rte_intr_enable(intr_handle);
3325
3326         /* resume enabled intr since hw reset */
3327         igbvf_intr_enable(dev);
3328
3329         return 0;
3330 }
3331
3332 static void
3333 igbvf_dev_stop(struct rte_eth_dev *dev)
3334 {
3335         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3336         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
3337
3338         PMD_INIT_FUNC_TRACE();
3339
3340         igbvf_stop_adapter(dev);
3341
3342         /*
3343           * Clear what we set, but we still keep shadow_vfta to
3344           * restore after device starts
3345           */
3346         igbvf_set_vfta_all(dev,0);
3347
3348         igb_dev_clear_queues(dev);
3349
3350         /* disable intr eventfd mapping */
3351         rte_intr_disable(intr_handle);
3352
3353         /* Clean datapath event and queue/vec mapping */
3354         rte_intr_efd_disable(intr_handle);
3355         if (intr_handle->intr_vec) {
3356                 rte_free(intr_handle->intr_vec);
3357                 intr_handle->intr_vec = NULL;
3358         }
3359 }
3360
3361 static void
3362 igbvf_dev_close(struct rte_eth_dev *dev)
3363 {
3364         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3365         struct e1000_adapter *adapter =
3366                 E1000_DEV_PRIVATE(dev->data->dev_private);
3367         struct ether_addr addr;
3368
3369         PMD_INIT_FUNC_TRACE();
3370
3371         e1000_reset_hw(hw);
3372
3373         igbvf_dev_stop(dev);
3374         adapter->stopped = 1;
3375         igb_dev_free_queues(dev);
3376
3377         /**
3378          * reprogram the RAR with a zero mac address,
3379          * to ensure that the VF traffic goes to the PF
3380          * after stop, close and detach of the VF.
3381          **/
3382
3383         memset(&addr, 0, sizeof(addr));
3384         igbvf_default_mac_addr_set(dev, &addr);
3385 }
3386
3387 static void
3388 igbvf_promiscuous_enable(struct rte_eth_dev *dev)
3389 {
3390         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3391
3392         /* Set both unicast and multicast promisc */
3393         e1000_promisc_set_vf(hw, e1000_promisc_enabled);
3394 }
3395
3396 static void
3397 igbvf_promiscuous_disable(struct rte_eth_dev *dev)
3398 {
3399         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3400
3401         /* If in allmulticast mode leave multicast promisc */
3402         if (dev->data->all_multicast == 1)
3403                 e1000_promisc_set_vf(hw, e1000_promisc_multicast);
3404         else
3405                 e1000_promisc_set_vf(hw, e1000_promisc_disabled);
3406 }
3407
3408 static void
3409 igbvf_allmulticast_enable(struct rte_eth_dev *dev)
3410 {
3411         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3412
3413         /* In promiscuous mode multicast promisc already set */
3414         if (dev->data->promiscuous == 0)
3415                 e1000_promisc_set_vf(hw, e1000_promisc_multicast);
3416 }
3417
3418 static void
3419 igbvf_allmulticast_disable(struct rte_eth_dev *dev)
3420 {
3421         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3422
3423         /* In promiscuous mode leave multicast promisc enabled */
3424         if (dev->data->promiscuous == 0)
3425                 e1000_promisc_set_vf(hw, e1000_promisc_disabled);
3426 }
3427
3428 static int igbvf_set_vfta(struct e1000_hw *hw, uint16_t vid, bool on)
3429 {
3430         struct e1000_mbx_info *mbx = &hw->mbx;
3431         uint32_t msgbuf[2];
3432         s32 err;
3433
3434         /* After set vlan, vlan strip will also be enabled in igb driver*/
3435         msgbuf[0] = E1000_VF_SET_VLAN;
3436         msgbuf[1] = vid;
3437         /* Setting the 8 bit field MSG INFO to TRUE indicates "add" */
3438         if (on)
3439                 msgbuf[0] |= E1000_VF_SET_VLAN_ADD;
3440
3441         err = mbx->ops.write_posted(hw, msgbuf, 2, 0);
3442         if (err)
3443                 goto mbx_err;
3444
3445         err = mbx->ops.read_posted(hw, msgbuf, 2, 0);
3446         if (err)
3447                 goto mbx_err;
3448
3449         msgbuf[0] &= ~E1000_VT_MSGTYPE_CTS;
3450         if (msgbuf[0] == (E1000_VF_SET_VLAN | E1000_VT_MSGTYPE_NACK))
3451                 err = -EINVAL;
3452
3453 mbx_err:
3454         return err;
3455 }
3456
3457 static void igbvf_set_vfta_all(struct rte_eth_dev *dev, bool on)
3458 {
3459         struct e1000_hw *hw =
3460                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3461         struct e1000_vfta * shadow_vfta =
3462                 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
3463         int i = 0, j = 0, vfta = 0, mask = 1;
3464
3465         for (i = 0; i < IGB_VFTA_SIZE; i++){
3466                 vfta = shadow_vfta->vfta[i];
3467                 if(vfta){
3468                         mask = 1;
3469                         for (j = 0; j < 32; j++){
3470                                 if(vfta & mask)
3471                                         igbvf_set_vfta(hw,
3472                                                 (uint16_t)((i<<5)+j), on);
3473                                 mask<<=1;
3474                         }
3475                 }
3476         }
3477
3478 }
3479
3480 static int
3481 igbvf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
3482 {
3483         struct e1000_hw *hw =
3484                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3485         struct e1000_vfta * shadow_vfta =
3486                 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
3487         uint32_t vid_idx = 0;
3488         uint32_t vid_bit = 0;
3489         int ret = 0;
3490
3491         PMD_INIT_FUNC_TRACE();
3492
3493         /*vind is not used in VF driver, set to 0, check ixgbe_set_vfta_vf*/
3494         ret = igbvf_set_vfta(hw, vlan_id, !!on);
3495         if(ret){
3496                 PMD_INIT_LOG(ERR, "Unable to set VF vlan");
3497                 return ret;
3498         }
3499         vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
3500         vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
3501
3502         /*Save what we set and retore it after device reset*/
3503         if (on)
3504                 shadow_vfta->vfta[vid_idx] |= vid_bit;
3505         else
3506                 shadow_vfta->vfta[vid_idx] &= ~vid_bit;
3507
3508         return 0;
3509 }
3510
3511 static void
3512 igbvf_default_mac_addr_set(struct rte_eth_dev *dev, struct ether_addr *addr)
3513 {
3514         struct e1000_hw *hw =
3515                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3516
3517         /* index is not used by rar_set() */
3518         hw->mac.ops.rar_set(hw, (void *)addr, 0);
3519 }
3520
3521
3522 static int
3523 eth_igb_rss_reta_update(struct rte_eth_dev *dev,
3524                         struct rte_eth_rss_reta_entry64 *reta_conf,
3525                         uint16_t reta_size)
3526 {
3527         uint8_t i, j, mask;
3528         uint32_t reta, r;
3529         uint16_t idx, shift;
3530         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3531
3532         if (reta_size != ETH_RSS_RETA_SIZE_128) {
3533                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
3534                         "(%d) doesn't match the number hardware can supported "
3535                         "(%d)", reta_size, ETH_RSS_RETA_SIZE_128);
3536                 return -EINVAL;
3537         }
3538
3539         for (i = 0; i < reta_size; i += IGB_4_BIT_WIDTH) {
3540                 idx = i / RTE_RETA_GROUP_SIZE;
3541                 shift = i % RTE_RETA_GROUP_SIZE;
3542                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
3543                                                 IGB_4_BIT_MASK);
3544                 if (!mask)
3545                         continue;
3546                 if (mask == IGB_4_BIT_MASK)
3547                         r = 0;
3548                 else
3549                         r = E1000_READ_REG(hw, E1000_RETA(i >> 2));
3550                 for (j = 0, reta = 0; j < IGB_4_BIT_WIDTH; j++) {
3551                         if (mask & (0x1 << j))
3552                                 reta |= reta_conf[idx].reta[shift + j] <<
3553                                                         (CHAR_BIT * j);
3554                         else
3555                                 reta |= r & (IGB_8_BIT_MASK << (CHAR_BIT * j));
3556                 }
3557                 E1000_WRITE_REG(hw, E1000_RETA(i >> 2), reta);
3558         }
3559
3560         return 0;
3561 }
3562
3563 static int
3564 eth_igb_rss_reta_query(struct rte_eth_dev *dev,
3565                        struct rte_eth_rss_reta_entry64 *reta_conf,
3566                        uint16_t reta_size)
3567 {
3568         uint8_t i, j, mask;
3569         uint32_t reta;
3570         uint16_t idx, shift;
3571         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3572
3573         if (reta_size != ETH_RSS_RETA_SIZE_128) {
3574                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
3575                         "(%d) doesn't match the number hardware can supported "
3576                         "(%d)", reta_size, ETH_RSS_RETA_SIZE_128);
3577                 return -EINVAL;
3578         }
3579
3580         for (i = 0; i < reta_size; i += IGB_4_BIT_WIDTH) {
3581                 idx = i / RTE_RETA_GROUP_SIZE;
3582                 shift = i % RTE_RETA_GROUP_SIZE;
3583                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
3584                                                 IGB_4_BIT_MASK);
3585                 if (!mask)
3586                         continue;
3587                 reta = E1000_READ_REG(hw, E1000_RETA(i >> 2));
3588                 for (j = 0; j < IGB_4_BIT_WIDTH; j++) {
3589                         if (mask & (0x1 << j))
3590                                 reta_conf[idx].reta[shift + j] =
3591                                         ((reta >> (CHAR_BIT * j)) &
3592                                                 IGB_8_BIT_MASK);
3593                 }
3594         }
3595
3596         return 0;
3597 }
3598
3599 int
3600 eth_igb_syn_filter_set(struct rte_eth_dev *dev,
3601                         struct rte_eth_syn_filter *filter,
3602                         bool add)
3603 {
3604         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3605         struct e1000_filter_info *filter_info =
3606                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3607         uint32_t synqf, rfctl;
3608
3609         if (filter->queue >= IGB_MAX_RX_QUEUE_NUM)
3610                 return -EINVAL;
3611
3612         synqf = E1000_READ_REG(hw, E1000_SYNQF(0));
3613
3614         if (add) {
3615                 if (synqf & E1000_SYN_FILTER_ENABLE)
3616                         return -EINVAL;
3617
3618                 synqf = (uint32_t)(((filter->queue << E1000_SYN_FILTER_QUEUE_SHIFT) &
3619                         E1000_SYN_FILTER_QUEUE) | E1000_SYN_FILTER_ENABLE);
3620
3621                 rfctl = E1000_READ_REG(hw, E1000_RFCTL);
3622                 if (filter->hig_pri)
3623                         rfctl |= E1000_RFCTL_SYNQFP;
3624                 else
3625                         rfctl &= ~E1000_RFCTL_SYNQFP;
3626
3627                 E1000_WRITE_REG(hw, E1000_RFCTL, rfctl);
3628         } else {
3629                 if (!(synqf & E1000_SYN_FILTER_ENABLE))
3630                         return -ENOENT;
3631                 synqf = 0;
3632         }
3633
3634         filter_info->syn_info = synqf;
3635         E1000_WRITE_REG(hw, E1000_SYNQF(0), synqf);
3636         E1000_WRITE_FLUSH(hw);
3637         return 0;
3638 }
3639
3640 static int
3641 eth_igb_syn_filter_get(struct rte_eth_dev *dev,
3642                         struct rte_eth_syn_filter *filter)
3643 {
3644         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3645         uint32_t synqf, rfctl;
3646
3647         synqf = E1000_READ_REG(hw, E1000_SYNQF(0));
3648         if (synqf & E1000_SYN_FILTER_ENABLE) {
3649                 rfctl = E1000_READ_REG(hw, E1000_RFCTL);
3650                 filter->hig_pri = (rfctl & E1000_RFCTL_SYNQFP) ? 1 : 0;
3651                 filter->queue = (uint8_t)((synqf & E1000_SYN_FILTER_QUEUE) >>
3652                                 E1000_SYN_FILTER_QUEUE_SHIFT);
3653                 return 0;
3654         }
3655
3656         return -ENOENT;
3657 }
3658
3659 static int
3660 eth_igb_syn_filter_handle(struct rte_eth_dev *dev,
3661                         enum rte_filter_op filter_op,
3662                         void *arg)
3663 {
3664         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3665         int ret;
3666
3667         MAC_TYPE_FILTER_SUP(hw->mac.type);
3668
3669         if (filter_op == RTE_ETH_FILTER_NOP)
3670                 return 0;
3671
3672         if (arg == NULL) {
3673                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
3674                             filter_op);
3675                 return -EINVAL;
3676         }
3677
3678         switch (filter_op) {
3679         case RTE_ETH_FILTER_ADD:
3680                 ret = eth_igb_syn_filter_set(dev,
3681                                 (struct rte_eth_syn_filter *)arg,
3682                                 TRUE);
3683                 break;
3684         case RTE_ETH_FILTER_DELETE:
3685                 ret = eth_igb_syn_filter_set(dev,
3686                                 (struct rte_eth_syn_filter *)arg,
3687                                 FALSE);
3688                 break;
3689         case RTE_ETH_FILTER_GET:
3690                 ret = eth_igb_syn_filter_get(dev,
3691                                 (struct rte_eth_syn_filter *)arg);
3692                 break;
3693         default:
3694                 PMD_DRV_LOG(ERR, "unsupported operation %u", filter_op);
3695                 ret = -EINVAL;
3696                 break;
3697         }
3698
3699         return ret;
3700 }
3701
3702 /* translate elements in struct rte_eth_ntuple_filter to struct e1000_2tuple_filter_info*/
3703 static inline int
3704 ntuple_filter_to_2tuple(struct rte_eth_ntuple_filter *filter,
3705                         struct e1000_2tuple_filter_info *filter_info)
3706 {
3707         if (filter->queue >= IGB_MAX_RX_QUEUE_NUM)
3708                 return -EINVAL;
3709         if (filter->priority > E1000_2TUPLE_MAX_PRI)
3710                 return -EINVAL;  /* filter index is out of range. */
3711         if (filter->tcp_flags > TCP_FLAG_ALL)
3712                 return -EINVAL;  /* flags is invalid. */
3713
3714         switch (filter->dst_port_mask) {
3715         case UINT16_MAX:
3716                 filter_info->dst_port_mask = 0;
3717                 filter_info->dst_port = filter->dst_port;
3718                 break;
3719         case 0:
3720                 filter_info->dst_port_mask = 1;
3721                 break;
3722         default:
3723                 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
3724                 return -EINVAL;
3725         }
3726
3727         switch (filter->proto_mask) {
3728         case UINT8_MAX:
3729                 filter_info->proto_mask = 0;
3730                 filter_info->proto = filter->proto;
3731                 break;
3732         case 0:
3733                 filter_info->proto_mask = 1;
3734                 break;
3735         default:
3736                 PMD_DRV_LOG(ERR, "invalid protocol mask.");
3737                 return -EINVAL;
3738         }
3739
3740         filter_info->priority = (uint8_t)filter->priority;
3741         if (filter->flags & RTE_NTUPLE_FLAGS_TCP_FLAG)
3742                 filter_info->tcp_flags = filter->tcp_flags;
3743         else
3744                 filter_info->tcp_flags = 0;
3745
3746         return 0;
3747 }
3748
3749 static inline struct e1000_2tuple_filter *
3750 igb_2tuple_filter_lookup(struct e1000_2tuple_filter_list *filter_list,
3751                         struct e1000_2tuple_filter_info *key)
3752 {
3753         struct e1000_2tuple_filter *it;
3754
3755         TAILQ_FOREACH(it, filter_list, entries) {
3756                 if (memcmp(key, &it->filter_info,
3757                         sizeof(struct e1000_2tuple_filter_info)) == 0) {
3758                         return it;
3759                 }
3760         }
3761         return NULL;
3762 }
3763
3764 /* inject a igb 2tuple filter to HW */
3765 static inline void
3766 igb_inject_2uple_filter(struct rte_eth_dev *dev,
3767                            struct e1000_2tuple_filter *filter)
3768 {
3769         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3770         uint32_t ttqf = E1000_TTQF_DISABLE_MASK;
3771         uint32_t imir, imir_ext = E1000_IMIREXT_SIZE_BP;
3772         int i;
3773
3774         i = filter->index;
3775         imir = (uint32_t)(filter->filter_info.dst_port & E1000_IMIR_DSTPORT);
3776         if (filter->filter_info.dst_port_mask == 1) /* 1b means not compare. */
3777                 imir |= E1000_IMIR_PORT_BP;
3778         else
3779                 imir &= ~E1000_IMIR_PORT_BP;
3780
3781         imir |= filter->filter_info.priority << E1000_IMIR_PRIORITY_SHIFT;
3782
3783         ttqf |= E1000_TTQF_QUEUE_ENABLE;
3784         ttqf |= (uint32_t)(filter->queue << E1000_TTQF_QUEUE_SHIFT);
3785         ttqf |= (uint32_t)(filter->filter_info.proto &
3786                                                 E1000_TTQF_PROTOCOL_MASK);
3787         if (filter->filter_info.proto_mask == 0)
3788                 ttqf &= ~E1000_TTQF_MASK_ENABLE;
3789
3790         /* tcp flags bits setting. */
3791         if (filter->filter_info.tcp_flags & TCP_FLAG_ALL) {
3792                 if (filter->filter_info.tcp_flags & TCP_URG_FLAG)
3793                         imir_ext |= E1000_IMIREXT_CTRL_URG;
3794                 if (filter->filter_info.tcp_flags & TCP_ACK_FLAG)
3795                         imir_ext |= E1000_IMIREXT_CTRL_ACK;
3796                 if (filter->filter_info.tcp_flags & TCP_PSH_FLAG)
3797                         imir_ext |= E1000_IMIREXT_CTRL_PSH;
3798                 if (filter->filter_info.tcp_flags & TCP_RST_FLAG)
3799                         imir_ext |= E1000_IMIREXT_CTRL_RST;
3800                 if (filter->filter_info.tcp_flags & TCP_SYN_FLAG)
3801                         imir_ext |= E1000_IMIREXT_CTRL_SYN;
3802                 if (filter->filter_info.tcp_flags & TCP_FIN_FLAG)
3803                         imir_ext |= E1000_IMIREXT_CTRL_FIN;
3804         } else {
3805                 imir_ext |= E1000_IMIREXT_CTRL_BP;
3806         }
3807         E1000_WRITE_REG(hw, E1000_IMIR(i), imir);
3808         E1000_WRITE_REG(hw, E1000_TTQF(i), ttqf);
3809         E1000_WRITE_REG(hw, E1000_IMIREXT(i), imir_ext);
3810 }
3811
3812 /*
3813  * igb_add_2tuple_filter - add a 2tuple filter
3814  *
3815  * @param
3816  * dev: Pointer to struct rte_eth_dev.
3817  * ntuple_filter: ponter to the filter that will be added.
3818  *
3819  * @return
3820  *    - On success, zero.
3821  *    - On failure, a negative value.
3822  */
3823 static int
3824 igb_add_2tuple_filter(struct rte_eth_dev *dev,
3825                         struct rte_eth_ntuple_filter *ntuple_filter)
3826 {
3827         struct e1000_filter_info *filter_info =
3828                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3829         struct e1000_2tuple_filter *filter;
3830         int i, ret;
3831
3832         filter = rte_zmalloc("e1000_2tuple_filter",
3833                         sizeof(struct e1000_2tuple_filter), 0);
3834         if (filter == NULL)
3835                 return -ENOMEM;
3836
3837         ret = ntuple_filter_to_2tuple(ntuple_filter,
3838                                       &filter->filter_info);
3839         if (ret < 0) {
3840                 rte_free(filter);
3841                 return ret;
3842         }
3843         if (igb_2tuple_filter_lookup(&filter_info->twotuple_list,
3844                                          &filter->filter_info) != NULL) {
3845                 PMD_DRV_LOG(ERR, "filter exists.");
3846                 rte_free(filter);
3847                 return -EEXIST;
3848         }
3849         filter->queue = ntuple_filter->queue;
3850
3851         /*
3852          * look for an unused 2tuple filter index,
3853          * and insert the filter to list.
3854          */
3855         for (i = 0; i < E1000_MAX_TTQF_FILTERS; i++) {
3856                 if (!(filter_info->twotuple_mask & (1 << i))) {
3857                         filter_info->twotuple_mask |= 1 << i;
3858                         filter->index = i;
3859                         TAILQ_INSERT_TAIL(&filter_info->twotuple_list,
3860                                           filter,
3861                                           entries);
3862                         break;
3863                 }
3864         }
3865         if (i >= E1000_MAX_TTQF_FILTERS) {
3866                 PMD_DRV_LOG(ERR, "2tuple filters are full.");
3867                 rte_free(filter);
3868                 return -ENOSYS;
3869         }
3870
3871         igb_inject_2uple_filter(dev, filter);
3872         return 0;
3873 }
3874
3875 int
3876 igb_delete_2tuple_filter(struct rte_eth_dev *dev,
3877                         struct e1000_2tuple_filter *filter)
3878 {
3879         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3880         struct e1000_filter_info *filter_info =
3881                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3882
3883         filter_info->twotuple_mask &= ~(1 << filter->index);
3884         TAILQ_REMOVE(&filter_info->twotuple_list, filter, entries);
3885         rte_free(filter);
3886
3887         E1000_WRITE_REG(hw, E1000_TTQF(filter->index), E1000_TTQF_DISABLE_MASK);
3888         E1000_WRITE_REG(hw, E1000_IMIR(filter->index), 0);
3889         E1000_WRITE_REG(hw, E1000_IMIREXT(filter->index), 0);
3890         return 0;
3891 }
3892
3893 /*
3894  * igb_remove_2tuple_filter - remove a 2tuple filter
3895  *
3896  * @param
3897  * dev: Pointer to struct rte_eth_dev.
3898  * ntuple_filter: ponter to the filter that will be removed.
3899  *
3900  * @return
3901  *    - On success, zero.
3902  *    - On failure, a negative value.
3903  */
3904 static int
3905 igb_remove_2tuple_filter(struct rte_eth_dev *dev,
3906                         struct rte_eth_ntuple_filter *ntuple_filter)
3907 {
3908         struct e1000_filter_info *filter_info =
3909                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3910         struct e1000_2tuple_filter_info filter_2tuple;
3911         struct e1000_2tuple_filter *filter;
3912         int ret;
3913
3914         memset(&filter_2tuple, 0, sizeof(struct e1000_2tuple_filter_info));
3915         ret = ntuple_filter_to_2tuple(ntuple_filter,
3916                                       &filter_2tuple);
3917         if (ret < 0)
3918                 return ret;
3919
3920         filter = igb_2tuple_filter_lookup(&filter_info->twotuple_list,
3921                                          &filter_2tuple);
3922         if (filter == NULL) {
3923                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
3924                 return -ENOENT;
3925         }
3926
3927         igb_delete_2tuple_filter(dev, filter);
3928
3929         return 0;
3930 }
3931
3932 /* inject a igb flex filter to HW */
3933 static inline void
3934 igb_inject_flex_filter(struct rte_eth_dev *dev,
3935                            struct e1000_flex_filter *filter)
3936 {
3937         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3938         uint32_t wufc, queueing;
3939         uint32_t reg_off;
3940         uint8_t i, j = 0;
3941
3942         wufc = E1000_READ_REG(hw, E1000_WUFC);
3943         if (filter->index < E1000_MAX_FHFT)
3944                 reg_off = E1000_FHFT(filter->index);
3945         else
3946                 reg_off = E1000_FHFT_EXT(filter->index - E1000_MAX_FHFT);
3947
3948         E1000_WRITE_REG(hw, E1000_WUFC, wufc | E1000_WUFC_FLEX_HQ |
3949                         (E1000_WUFC_FLX0 << filter->index));
3950         queueing = filter->filter_info.len |
3951                 (filter->queue << E1000_FHFT_QUEUEING_QUEUE_SHIFT) |
3952                 (filter->filter_info.priority <<
3953                         E1000_FHFT_QUEUEING_PRIO_SHIFT);
3954         E1000_WRITE_REG(hw, reg_off + E1000_FHFT_QUEUEING_OFFSET,
3955                         queueing);
3956
3957         for (i = 0; i < E1000_FLEX_FILTERS_MASK_SIZE; i++) {
3958                 E1000_WRITE_REG(hw, reg_off,
3959                                 filter->filter_info.dwords[j]);
3960                 reg_off += sizeof(uint32_t);
3961                 E1000_WRITE_REG(hw, reg_off,
3962                                 filter->filter_info.dwords[++j]);
3963                 reg_off += sizeof(uint32_t);
3964                 E1000_WRITE_REG(hw, reg_off,
3965                         (uint32_t)filter->filter_info.mask[i]);
3966                 reg_off += sizeof(uint32_t) * 2;
3967                 ++j;
3968         }
3969 }
3970
3971 static inline struct e1000_flex_filter *
3972 eth_igb_flex_filter_lookup(struct e1000_flex_filter_list *filter_list,
3973                         struct e1000_flex_filter_info *key)
3974 {
3975         struct e1000_flex_filter *it;
3976
3977         TAILQ_FOREACH(it, filter_list, entries) {
3978                 if (memcmp(key, &it->filter_info,
3979                         sizeof(struct e1000_flex_filter_info)) == 0)
3980                         return it;
3981         }
3982
3983         return NULL;
3984 }
3985
3986 /* remove a flex byte filter
3987  * @param
3988  * dev: Pointer to struct rte_eth_dev.
3989  * filter: the pointer of the filter will be removed.
3990  */
3991 void
3992 igb_remove_flex_filter(struct rte_eth_dev *dev,
3993                         struct e1000_flex_filter *filter)
3994 {
3995         struct e1000_filter_info *filter_info =
3996                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3997         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3998         uint32_t wufc, i;
3999         uint32_t reg_off;
4000
4001         wufc = E1000_READ_REG(hw, E1000_WUFC);
4002         if (filter->index < E1000_MAX_FHFT)
4003                 reg_off = E1000_FHFT(filter->index);
4004         else
4005                 reg_off = E1000_FHFT_EXT(filter->index - E1000_MAX_FHFT);
4006
4007         for (i = 0; i < E1000_FHFT_SIZE_IN_DWD; i++)
4008                 E1000_WRITE_REG(hw, reg_off + i * sizeof(uint32_t), 0);
4009
4010         E1000_WRITE_REG(hw, E1000_WUFC, wufc &
4011                 (~(E1000_WUFC_FLX0 << filter->index)));
4012
4013         filter_info->flex_mask &= ~(1 << filter->index);
4014         TAILQ_REMOVE(&filter_info->flex_list, filter, entries);
4015         rte_free(filter);
4016 }
4017
4018 int
4019 eth_igb_add_del_flex_filter(struct rte_eth_dev *dev,
4020                         struct rte_eth_flex_filter *filter,
4021                         bool add)
4022 {
4023         struct e1000_filter_info *filter_info =
4024                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4025         struct e1000_flex_filter *flex_filter, *it;
4026         uint32_t mask;
4027         uint8_t shift, i;
4028
4029         flex_filter = rte_zmalloc("e1000_flex_filter",
4030                         sizeof(struct e1000_flex_filter), 0);
4031         if (flex_filter == NULL)
4032                 return -ENOMEM;
4033
4034         flex_filter->filter_info.len = filter->len;
4035         flex_filter->filter_info.priority = filter->priority;
4036         memcpy(flex_filter->filter_info.dwords, filter->bytes, filter->len);
4037         for (i = 0; i < RTE_ALIGN(filter->len, CHAR_BIT) / CHAR_BIT; i++) {
4038                 mask = 0;
4039                 /* reverse bits in flex filter's mask*/
4040                 for (shift = 0; shift < CHAR_BIT; shift++) {
4041                         if (filter->mask[i] & (0x01 << shift))
4042                                 mask |= (0x80 >> shift);
4043                 }
4044                 flex_filter->filter_info.mask[i] = mask;
4045         }
4046
4047         it = eth_igb_flex_filter_lookup(&filter_info->flex_list,
4048                                 &flex_filter->filter_info);
4049         if (it == NULL && !add) {
4050                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
4051                 rte_free(flex_filter);
4052                 return -ENOENT;
4053         }
4054         if (it != NULL && add) {
4055                 PMD_DRV_LOG(ERR, "filter exists.");
4056                 rte_free(flex_filter);
4057                 return -EEXIST;
4058         }
4059
4060         if (add) {
4061                 flex_filter->queue = filter->queue;
4062                 /*
4063                  * look for an unused flex filter index
4064                  * and insert the filter into the list.
4065                  */
4066                 for (i = 0; i < E1000_MAX_FLEX_FILTERS; i++) {
4067                         if (!(filter_info->flex_mask & (1 << i))) {
4068                                 filter_info->flex_mask |= 1 << i;
4069                                 flex_filter->index = i;
4070                                 TAILQ_INSERT_TAIL(&filter_info->flex_list,
4071                                         flex_filter,
4072                                         entries);
4073                                 break;
4074                         }
4075                 }
4076                 if (i >= E1000_MAX_FLEX_FILTERS) {
4077                         PMD_DRV_LOG(ERR, "flex filters are full.");
4078                         rte_free(flex_filter);
4079                         return -ENOSYS;
4080                 }
4081
4082                 igb_inject_flex_filter(dev, flex_filter);
4083
4084         } else {
4085                 igb_remove_flex_filter(dev, it);
4086                 rte_free(flex_filter);
4087         }
4088
4089         return 0;
4090 }
4091
4092 static int
4093 eth_igb_get_flex_filter(struct rte_eth_dev *dev,
4094                         struct rte_eth_flex_filter *filter)
4095 {
4096         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4097         struct e1000_filter_info *filter_info =
4098                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4099         struct e1000_flex_filter flex_filter, *it;
4100         uint32_t wufc, queueing, wufc_en = 0;
4101
4102         memset(&flex_filter, 0, sizeof(struct e1000_flex_filter));
4103         flex_filter.filter_info.len = filter->len;
4104         flex_filter.filter_info.priority = filter->priority;
4105         memcpy(flex_filter.filter_info.dwords, filter->bytes, filter->len);
4106         memcpy(flex_filter.filter_info.mask, filter->mask,
4107                         RTE_ALIGN(filter->len, CHAR_BIT) / CHAR_BIT);
4108
4109         it = eth_igb_flex_filter_lookup(&filter_info->flex_list,
4110                                 &flex_filter.filter_info);
4111         if (it == NULL) {
4112                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
4113                 return -ENOENT;
4114         }
4115
4116         wufc = E1000_READ_REG(hw, E1000_WUFC);
4117         wufc_en = E1000_WUFC_FLEX_HQ | (E1000_WUFC_FLX0 << it->index);
4118
4119         if ((wufc & wufc_en) == wufc_en) {
4120                 uint32_t reg_off = 0;
4121                 if (it->index < E1000_MAX_FHFT)
4122                         reg_off = E1000_FHFT(it->index);
4123                 else
4124                         reg_off = E1000_FHFT_EXT(it->index - E1000_MAX_FHFT);
4125
4126                 queueing = E1000_READ_REG(hw,
4127                                 reg_off + E1000_FHFT_QUEUEING_OFFSET);
4128                 filter->len = queueing & E1000_FHFT_QUEUEING_LEN;
4129                 filter->priority = (queueing & E1000_FHFT_QUEUEING_PRIO) >>
4130                         E1000_FHFT_QUEUEING_PRIO_SHIFT;
4131                 filter->queue = (queueing & E1000_FHFT_QUEUEING_QUEUE) >>
4132                         E1000_FHFT_QUEUEING_QUEUE_SHIFT;
4133                 return 0;
4134         }
4135         return -ENOENT;
4136 }
4137
4138 static int
4139 eth_igb_flex_filter_handle(struct rte_eth_dev *dev,
4140                         enum rte_filter_op filter_op,
4141                         void *arg)
4142 {
4143         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4144         struct rte_eth_flex_filter *filter;
4145         int ret = 0;
4146
4147         MAC_TYPE_FILTER_SUP_EXT(hw->mac.type);
4148
4149         if (filter_op == RTE_ETH_FILTER_NOP)
4150                 return ret;
4151
4152         if (arg == NULL) {
4153                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
4154                             filter_op);
4155                 return -EINVAL;
4156         }
4157
4158         filter = (struct rte_eth_flex_filter *)arg;
4159         if (filter->len == 0 || filter->len > E1000_MAX_FLEX_FILTER_LEN
4160             || filter->len % sizeof(uint64_t) != 0) {
4161                 PMD_DRV_LOG(ERR, "filter's length is out of range");
4162                 return -EINVAL;
4163         }
4164         if (filter->priority > E1000_MAX_FLEX_FILTER_PRI) {
4165                 PMD_DRV_LOG(ERR, "filter's priority is out of range");
4166                 return -EINVAL;
4167         }
4168
4169         switch (filter_op) {
4170         case RTE_ETH_FILTER_ADD:
4171                 ret = eth_igb_add_del_flex_filter(dev, filter, TRUE);
4172                 break;
4173         case RTE_ETH_FILTER_DELETE:
4174                 ret = eth_igb_add_del_flex_filter(dev, filter, FALSE);
4175                 break;
4176         case RTE_ETH_FILTER_GET:
4177                 ret = eth_igb_get_flex_filter(dev, filter);
4178                 break;
4179         default:
4180                 PMD_DRV_LOG(ERR, "unsupported operation %u", filter_op);
4181                 ret = -EINVAL;
4182                 break;
4183         }
4184
4185         return ret;
4186 }
4187
4188 /* translate elements in struct rte_eth_ntuple_filter to struct e1000_5tuple_filter_info*/
4189 static inline int
4190 ntuple_filter_to_5tuple_82576(struct rte_eth_ntuple_filter *filter,
4191                         struct e1000_5tuple_filter_info *filter_info)
4192 {
4193         if (filter->queue >= IGB_MAX_RX_QUEUE_NUM_82576)
4194                 return -EINVAL;
4195         if (filter->priority > E1000_2TUPLE_MAX_PRI)
4196                 return -EINVAL;  /* filter index is out of range. */
4197         if (filter->tcp_flags > TCP_FLAG_ALL)
4198                 return -EINVAL;  /* flags is invalid. */
4199
4200         switch (filter->dst_ip_mask) {
4201         case UINT32_MAX:
4202                 filter_info->dst_ip_mask = 0;
4203                 filter_info->dst_ip = filter->dst_ip;
4204                 break;
4205         case 0:
4206                 filter_info->dst_ip_mask = 1;
4207                 break;
4208         default:
4209                 PMD_DRV_LOG(ERR, "invalid dst_ip mask.");
4210                 return -EINVAL;
4211         }
4212
4213         switch (filter->src_ip_mask) {
4214         case UINT32_MAX:
4215                 filter_info->src_ip_mask = 0;
4216                 filter_info->src_ip = filter->src_ip;
4217                 break;
4218         case 0:
4219                 filter_info->src_ip_mask = 1;
4220                 break;
4221         default:
4222                 PMD_DRV_LOG(ERR, "invalid src_ip mask.");
4223                 return -EINVAL;
4224         }
4225
4226         switch (filter->dst_port_mask) {
4227         case UINT16_MAX:
4228                 filter_info->dst_port_mask = 0;
4229                 filter_info->dst_port = filter->dst_port;
4230                 break;
4231         case 0:
4232                 filter_info->dst_port_mask = 1;
4233                 break;
4234         default:
4235                 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
4236                 return -EINVAL;
4237         }
4238
4239         switch (filter->src_port_mask) {
4240         case UINT16_MAX:
4241                 filter_info->src_port_mask = 0;
4242                 filter_info->src_port = filter->src_port;
4243                 break;
4244         case 0:
4245                 filter_info->src_port_mask = 1;
4246                 break;
4247         default:
4248                 PMD_DRV_LOG(ERR, "invalid src_port mask.");
4249                 return -EINVAL;
4250         }
4251
4252         switch (filter->proto_mask) {
4253         case UINT8_MAX:
4254                 filter_info->proto_mask = 0;
4255                 filter_info->proto = filter->proto;
4256                 break;
4257         case 0:
4258                 filter_info->proto_mask = 1;
4259                 break;
4260         default:
4261                 PMD_DRV_LOG(ERR, "invalid protocol mask.");
4262                 return -EINVAL;
4263         }
4264
4265         filter_info->priority = (uint8_t)filter->priority;
4266         if (filter->flags & RTE_NTUPLE_FLAGS_TCP_FLAG)
4267                 filter_info->tcp_flags = filter->tcp_flags;
4268         else
4269                 filter_info->tcp_flags = 0;
4270
4271         return 0;
4272 }
4273
4274 static inline struct e1000_5tuple_filter *
4275 igb_5tuple_filter_lookup_82576(struct e1000_5tuple_filter_list *filter_list,
4276                         struct e1000_5tuple_filter_info *key)
4277 {
4278         struct e1000_5tuple_filter *it;
4279
4280         TAILQ_FOREACH(it, filter_list, entries) {
4281                 if (memcmp(key, &it->filter_info,
4282                         sizeof(struct e1000_5tuple_filter_info)) == 0) {
4283                         return it;
4284                 }
4285         }
4286         return NULL;
4287 }
4288
4289 /* inject a igb 5-tuple filter to HW */
4290 static inline void
4291 igb_inject_5tuple_filter_82576(struct rte_eth_dev *dev,
4292                            struct e1000_5tuple_filter *filter)
4293 {
4294         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4295         uint32_t ftqf = E1000_FTQF_VF_BP | E1000_FTQF_MASK;
4296         uint32_t spqf, imir, imir_ext = E1000_IMIREXT_SIZE_BP;
4297         uint8_t i;
4298
4299         i = filter->index;
4300         ftqf |= filter->filter_info.proto & E1000_FTQF_PROTOCOL_MASK;
4301         if (filter->filter_info.src_ip_mask == 0) /* 0b means compare. */
4302                 ftqf &= ~E1000_FTQF_MASK_SOURCE_ADDR_BP;
4303         if (filter->filter_info.dst_ip_mask == 0)
4304                 ftqf &= ~E1000_FTQF_MASK_DEST_ADDR_BP;
4305         if (filter->filter_info.src_port_mask == 0)
4306                 ftqf &= ~E1000_FTQF_MASK_SOURCE_PORT_BP;
4307         if (filter->filter_info.proto_mask == 0)
4308                 ftqf &= ~E1000_FTQF_MASK_PROTO_BP;
4309         ftqf |= (filter->queue << E1000_FTQF_QUEUE_SHIFT) &
4310                 E1000_FTQF_QUEUE_MASK;
4311         ftqf |= E1000_FTQF_QUEUE_ENABLE;
4312         E1000_WRITE_REG(hw, E1000_FTQF(i), ftqf);
4313         E1000_WRITE_REG(hw, E1000_DAQF(i), filter->filter_info.dst_ip);
4314         E1000_WRITE_REG(hw, E1000_SAQF(i), filter->filter_info.src_ip);
4315
4316         spqf = filter->filter_info.src_port & E1000_SPQF_SRCPORT;
4317         E1000_WRITE_REG(hw, E1000_SPQF(i), spqf);
4318
4319         imir = (uint32_t)(filter->filter_info.dst_port & E1000_IMIR_DSTPORT);
4320         if (filter->filter_info.dst_port_mask == 1) /* 1b means not compare. */
4321                 imir |= E1000_IMIR_PORT_BP;
4322         else
4323                 imir &= ~E1000_IMIR_PORT_BP;
4324         imir |= filter->filter_info.priority << E1000_IMIR_PRIORITY_SHIFT;
4325
4326         /* tcp flags bits setting. */
4327         if (filter->filter_info.tcp_flags & TCP_FLAG_ALL) {
4328                 if (filter->filter_info.tcp_flags & TCP_URG_FLAG)
4329                         imir_ext |= E1000_IMIREXT_CTRL_URG;
4330                 if (filter->filter_info.tcp_flags & TCP_ACK_FLAG)
4331                         imir_ext |= E1000_IMIREXT_CTRL_ACK;
4332                 if (filter->filter_info.tcp_flags & TCP_PSH_FLAG)
4333                         imir_ext |= E1000_IMIREXT_CTRL_PSH;
4334                 if (filter->filter_info.tcp_flags & TCP_RST_FLAG)
4335                         imir_ext |= E1000_IMIREXT_CTRL_RST;
4336                 if (filter->filter_info.tcp_flags & TCP_SYN_FLAG)
4337                         imir_ext |= E1000_IMIREXT_CTRL_SYN;
4338                 if (filter->filter_info.tcp_flags & TCP_FIN_FLAG)
4339                         imir_ext |= E1000_IMIREXT_CTRL_FIN;
4340         } else {
4341                 imir_ext |= E1000_IMIREXT_CTRL_BP;
4342         }
4343         E1000_WRITE_REG(hw, E1000_IMIR(i), imir);
4344         E1000_WRITE_REG(hw, E1000_IMIREXT(i), imir_ext);
4345 }
4346
4347 /*
4348  * igb_add_5tuple_filter_82576 - add a 5tuple filter
4349  *
4350  * @param
4351  * dev: Pointer to struct rte_eth_dev.
4352  * ntuple_filter: ponter to the filter that will be added.
4353  *
4354  * @return
4355  *    - On success, zero.
4356  *    - On failure, a negative value.
4357  */
4358 static int
4359 igb_add_5tuple_filter_82576(struct rte_eth_dev *dev,
4360                         struct rte_eth_ntuple_filter *ntuple_filter)
4361 {
4362         struct e1000_filter_info *filter_info =
4363                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4364         struct e1000_5tuple_filter *filter;
4365         uint8_t i;
4366         int ret;
4367
4368         filter = rte_zmalloc("e1000_5tuple_filter",
4369                         sizeof(struct e1000_5tuple_filter), 0);
4370         if (filter == NULL)
4371                 return -ENOMEM;
4372
4373         ret = ntuple_filter_to_5tuple_82576(ntuple_filter,
4374                                             &filter->filter_info);
4375         if (ret < 0) {
4376                 rte_free(filter);
4377                 return ret;
4378         }
4379
4380         if (igb_5tuple_filter_lookup_82576(&filter_info->fivetuple_list,
4381                                          &filter->filter_info) != NULL) {
4382                 PMD_DRV_LOG(ERR, "filter exists.");
4383                 rte_free(filter);
4384                 return -EEXIST;
4385         }
4386         filter->queue = ntuple_filter->queue;
4387
4388         /*
4389          * look for an unused 5tuple filter index,
4390          * and insert the filter to list.
4391          */
4392         for (i = 0; i < E1000_MAX_FTQF_FILTERS; i++) {
4393                 if (!(filter_info->fivetuple_mask & (1 << i))) {
4394                         filter_info->fivetuple_mask |= 1 << i;
4395                         filter->index = i;
4396                         TAILQ_INSERT_TAIL(&filter_info->fivetuple_list,
4397                                           filter,
4398                                           entries);
4399                         break;
4400                 }
4401         }
4402         if (i >= E1000_MAX_FTQF_FILTERS) {
4403                 PMD_DRV_LOG(ERR, "5tuple filters are full.");
4404                 rte_free(filter);
4405                 return -ENOSYS;
4406         }
4407
4408         igb_inject_5tuple_filter_82576(dev, filter);
4409         return 0;
4410 }
4411
4412 int
4413 igb_delete_5tuple_filter_82576(struct rte_eth_dev *dev,
4414                                 struct e1000_5tuple_filter *filter)
4415 {
4416         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4417         struct e1000_filter_info *filter_info =
4418                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4419
4420         filter_info->fivetuple_mask &= ~(1 << filter->index);
4421         TAILQ_REMOVE(&filter_info->fivetuple_list, filter, entries);
4422         rte_free(filter);
4423
4424         E1000_WRITE_REG(hw, E1000_FTQF(filter->index),
4425                         E1000_FTQF_VF_BP | E1000_FTQF_MASK);
4426         E1000_WRITE_REG(hw, E1000_DAQF(filter->index), 0);
4427         E1000_WRITE_REG(hw, E1000_SAQF(filter->index), 0);
4428         E1000_WRITE_REG(hw, E1000_SPQF(filter->index), 0);
4429         E1000_WRITE_REG(hw, E1000_IMIR(filter->index), 0);
4430         E1000_WRITE_REG(hw, E1000_IMIREXT(filter->index), 0);
4431         return 0;
4432 }
4433
4434 /*
4435  * igb_remove_5tuple_filter_82576 - remove a 5tuple filter
4436  *
4437  * @param
4438  * dev: Pointer to struct rte_eth_dev.
4439  * ntuple_filter: ponter to the filter that will be removed.
4440  *
4441  * @return
4442  *    - On success, zero.
4443  *    - On failure, a negative value.
4444  */
4445 static int
4446 igb_remove_5tuple_filter_82576(struct rte_eth_dev *dev,
4447                                 struct rte_eth_ntuple_filter *ntuple_filter)
4448 {
4449         struct e1000_filter_info *filter_info =
4450                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4451         struct e1000_5tuple_filter_info filter_5tuple;
4452         struct e1000_5tuple_filter *filter;
4453         int ret;
4454
4455         memset(&filter_5tuple, 0, sizeof(struct e1000_5tuple_filter_info));
4456         ret = ntuple_filter_to_5tuple_82576(ntuple_filter,
4457                                             &filter_5tuple);
4458         if (ret < 0)
4459                 return ret;
4460
4461         filter = igb_5tuple_filter_lookup_82576(&filter_info->fivetuple_list,
4462                                          &filter_5tuple);
4463         if (filter == NULL) {
4464                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
4465                 return -ENOENT;
4466         }
4467
4468         igb_delete_5tuple_filter_82576(dev, filter);
4469
4470         return 0;
4471 }
4472
4473 static int
4474 eth_igb_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
4475 {
4476         uint32_t rctl;
4477         struct e1000_hw *hw;
4478         struct rte_eth_dev_info dev_info;
4479         uint32_t frame_size = mtu + (ETHER_HDR_LEN + ETHER_CRC_LEN +
4480                                      VLAN_TAG_SIZE);
4481
4482         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4483
4484 #ifdef RTE_LIBRTE_82571_SUPPORT
4485         /* XXX: not bigger than max_rx_pktlen */
4486         if (hw->mac.type == e1000_82571)
4487                 return -ENOTSUP;
4488 #endif
4489         eth_igb_infos_get(dev, &dev_info);
4490
4491         /* check that mtu is within the allowed range */
4492         if ((mtu < ETHER_MIN_MTU) ||
4493             (frame_size > dev_info.max_rx_pktlen))
4494                 return -EINVAL;
4495
4496         /* refuse mtu that requires the support of scattered packets when this
4497          * feature has not been enabled before. */
4498         if (!dev->data->scattered_rx &&
4499             frame_size > dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)
4500                 return -EINVAL;
4501
4502         rctl = E1000_READ_REG(hw, E1000_RCTL);
4503
4504         /* switch to jumbo mode if needed */
4505         if (frame_size > ETHER_MAX_LEN) {
4506                 dev->data->dev_conf.rxmode.jumbo_frame = 1;
4507                 rctl |= E1000_RCTL_LPE;
4508         } else {
4509                 dev->data->dev_conf.rxmode.jumbo_frame = 0;
4510                 rctl &= ~E1000_RCTL_LPE;
4511         }
4512         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
4513
4514         /* update max frame size */
4515         dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
4516
4517         E1000_WRITE_REG(hw, E1000_RLPML,
4518                         dev->data->dev_conf.rxmode.max_rx_pkt_len);
4519
4520         return 0;
4521 }
4522
4523 /*
4524  * igb_add_del_ntuple_filter - add or delete a ntuple filter
4525  *
4526  * @param
4527  * dev: Pointer to struct rte_eth_dev.
4528  * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
4529  * add: if true, add filter, if false, remove filter
4530  *
4531  * @return
4532  *    - On success, zero.
4533  *    - On failure, a negative value.
4534  */
4535 int
4536 igb_add_del_ntuple_filter(struct rte_eth_dev *dev,
4537                         struct rte_eth_ntuple_filter *ntuple_filter,
4538                         bool add)
4539 {
4540         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4541         int ret;
4542
4543         switch (ntuple_filter->flags) {
4544         case RTE_5TUPLE_FLAGS:
4545         case (RTE_5TUPLE_FLAGS | RTE_NTUPLE_FLAGS_TCP_FLAG):
4546                 if (hw->mac.type != e1000_82576)
4547                         return -ENOTSUP;
4548                 if (add)
4549                         ret = igb_add_5tuple_filter_82576(dev,
4550                                                           ntuple_filter);
4551                 else
4552                         ret = igb_remove_5tuple_filter_82576(dev,
4553                                                              ntuple_filter);
4554                 break;
4555         case RTE_2TUPLE_FLAGS:
4556         case (RTE_2TUPLE_FLAGS | RTE_NTUPLE_FLAGS_TCP_FLAG):
4557                 if (hw->mac.type != e1000_82580 && hw->mac.type != e1000_i350 &&
4558                         hw->mac.type != e1000_i210 &&
4559                         hw->mac.type != e1000_i211)
4560                         return -ENOTSUP;
4561                 if (add)
4562                         ret = igb_add_2tuple_filter(dev, ntuple_filter);
4563                 else
4564                         ret = igb_remove_2tuple_filter(dev, ntuple_filter);
4565                 break;
4566         default:
4567                 ret = -EINVAL;
4568                 break;
4569         }
4570
4571         return ret;
4572 }
4573
4574 /*
4575  * igb_get_ntuple_filter - get a ntuple filter
4576  *
4577  * @param
4578  * dev: Pointer to struct rte_eth_dev.
4579  * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
4580  *
4581  * @return
4582  *    - On success, zero.
4583  *    - On failure, a negative value.
4584  */
4585 static int
4586 igb_get_ntuple_filter(struct rte_eth_dev *dev,
4587                         struct rte_eth_ntuple_filter *ntuple_filter)
4588 {
4589         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4590         struct e1000_filter_info *filter_info =
4591                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4592         struct e1000_5tuple_filter_info filter_5tuple;
4593         struct e1000_2tuple_filter_info filter_2tuple;
4594         struct e1000_5tuple_filter *p_5tuple_filter;
4595         struct e1000_2tuple_filter *p_2tuple_filter;
4596         int ret;
4597
4598         switch (ntuple_filter->flags) {
4599         case RTE_5TUPLE_FLAGS:
4600         case (RTE_5TUPLE_FLAGS | RTE_NTUPLE_FLAGS_TCP_FLAG):
4601                 if (hw->mac.type != e1000_82576)
4602                         return -ENOTSUP;
4603                 memset(&filter_5tuple,
4604                         0,
4605                         sizeof(struct e1000_5tuple_filter_info));
4606                 ret = ntuple_filter_to_5tuple_82576(ntuple_filter,
4607                                                     &filter_5tuple);
4608                 if (ret < 0)
4609                         return ret;
4610                 p_5tuple_filter = igb_5tuple_filter_lookup_82576(
4611                                         &filter_info->fivetuple_list,
4612                                         &filter_5tuple);
4613                 if (p_5tuple_filter == NULL) {
4614                         PMD_DRV_LOG(ERR, "filter doesn't exist.");
4615                         return -ENOENT;
4616                 }
4617                 ntuple_filter->queue = p_5tuple_filter->queue;
4618                 break;
4619         case RTE_2TUPLE_FLAGS:
4620         case (RTE_2TUPLE_FLAGS | RTE_NTUPLE_FLAGS_TCP_FLAG):
4621                 if (hw->mac.type != e1000_82580 && hw->mac.type != e1000_i350)
4622                         return -ENOTSUP;
4623                 memset(&filter_2tuple,
4624                         0,
4625                         sizeof(struct e1000_2tuple_filter_info));
4626                 ret = ntuple_filter_to_2tuple(ntuple_filter, &filter_2tuple);
4627                 if (ret < 0)
4628                         return ret;
4629                 p_2tuple_filter = igb_2tuple_filter_lookup(
4630                                         &filter_info->twotuple_list,
4631                                         &filter_2tuple);
4632                 if (p_2tuple_filter == NULL) {
4633                         PMD_DRV_LOG(ERR, "filter doesn't exist.");
4634                         return -ENOENT;
4635                 }
4636                 ntuple_filter->queue = p_2tuple_filter->queue;
4637                 break;
4638         default:
4639                 ret = -EINVAL;
4640                 break;
4641         }
4642
4643         return 0;
4644 }
4645
4646 /*
4647  * igb_ntuple_filter_handle - Handle operations for ntuple filter.
4648  * @dev: pointer to rte_eth_dev structure
4649  * @filter_op:operation will be taken.
4650  * @arg: a pointer to specific structure corresponding to the filter_op
4651  */
4652 static int
4653 igb_ntuple_filter_handle(struct rte_eth_dev *dev,
4654                                 enum rte_filter_op filter_op,
4655                                 void *arg)
4656 {
4657         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4658         int ret;
4659
4660         MAC_TYPE_FILTER_SUP(hw->mac.type);
4661
4662         if (filter_op == RTE_ETH_FILTER_NOP)
4663                 return 0;
4664
4665         if (arg == NULL) {
4666                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
4667                             filter_op);
4668                 return -EINVAL;
4669         }
4670
4671         switch (filter_op) {
4672         case RTE_ETH_FILTER_ADD:
4673                 ret = igb_add_del_ntuple_filter(dev,
4674                         (struct rte_eth_ntuple_filter *)arg,
4675                         TRUE);
4676                 break;
4677         case RTE_ETH_FILTER_DELETE:
4678                 ret = igb_add_del_ntuple_filter(dev,
4679                         (struct rte_eth_ntuple_filter *)arg,
4680                         FALSE);
4681                 break;
4682         case RTE_ETH_FILTER_GET:
4683                 ret = igb_get_ntuple_filter(dev,
4684                         (struct rte_eth_ntuple_filter *)arg);
4685                 break;
4686         default:
4687                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
4688                 ret = -EINVAL;
4689                 break;
4690         }
4691         return ret;
4692 }
4693
4694 static inline int
4695 igb_ethertype_filter_lookup(struct e1000_filter_info *filter_info,
4696                         uint16_t ethertype)
4697 {
4698         int i;
4699
4700         for (i = 0; i < E1000_MAX_ETQF_FILTERS; i++) {
4701                 if (filter_info->ethertype_filters[i].ethertype == ethertype &&
4702                     (filter_info->ethertype_mask & (1 << i)))
4703                         return i;
4704         }
4705         return -1;
4706 }
4707
4708 static inline int
4709 igb_ethertype_filter_insert(struct e1000_filter_info *filter_info,
4710                         uint16_t ethertype, uint32_t etqf)
4711 {
4712         int i;
4713
4714         for (i = 0; i < E1000_MAX_ETQF_FILTERS; i++) {
4715                 if (!(filter_info->ethertype_mask & (1 << i))) {
4716                         filter_info->ethertype_mask |= 1 << i;
4717                         filter_info->ethertype_filters[i].ethertype = ethertype;
4718                         filter_info->ethertype_filters[i].etqf = etqf;
4719                         return i;
4720                 }
4721         }
4722         return -1;
4723 }
4724
4725 int
4726 igb_ethertype_filter_remove(struct e1000_filter_info *filter_info,
4727                         uint8_t idx)
4728 {
4729         if (idx >= E1000_MAX_ETQF_FILTERS)
4730                 return -1;
4731         filter_info->ethertype_mask &= ~(1 << idx);
4732         filter_info->ethertype_filters[idx].ethertype = 0;
4733         filter_info->ethertype_filters[idx].etqf = 0;
4734         return idx;
4735 }
4736
4737
4738 int
4739 igb_add_del_ethertype_filter(struct rte_eth_dev *dev,
4740                         struct rte_eth_ethertype_filter *filter,
4741                         bool add)
4742 {
4743         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4744         struct e1000_filter_info *filter_info =
4745                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4746         uint32_t etqf = 0;
4747         int ret;
4748
4749         if (filter->ether_type == ETHER_TYPE_IPv4 ||
4750                 filter->ether_type == ETHER_TYPE_IPv6) {
4751                 PMD_DRV_LOG(ERR, "unsupported ether_type(0x%04x) in"
4752                         " ethertype filter.", filter->ether_type);
4753                 return -EINVAL;
4754         }
4755
4756         if (filter->flags & RTE_ETHTYPE_FLAGS_MAC) {
4757                 PMD_DRV_LOG(ERR, "mac compare is unsupported.");
4758                 return -EINVAL;
4759         }
4760         if (filter->flags & RTE_ETHTYPE_FLAGS_DROP) {
4761                 PMD_DRV_LOG(ERR, "drop option is unsupported.");
4762                 return -EINVAL;
4763         }
4764
4765         ret = igb_ethertype_filter_lookup(filter_info, filter->ether_type);
4766         if (ret >= 0 && add) {
4767                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter exists.",
4768                             filter->ether_type);
4769                 return -EEXIST;
4770         }
4771         if (ret < 0 && !add) {
4772                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
4773                             filter->ether_type);
4774                 return -ENOENT;
4775         }
4776
4777         if (add) {
4778                 etqf |= E1000_ETQF_FILTER_ENABLE | E1000_ETQF_QUEUE_ENABLE;
4779                 etqf |= (uint32_t)(filter->ether_type & E1000_ETQF_ETHERTYPE);
4780                 etqf |= filter->queue << E1000_ETQF_QUEUE_SHIFT;
4781                 ret = igb_ethertype_filter_insert(filter_info,
4782                                 filter->ether_type, etqf);
4783                 if (ret < 0) {
4784                         PMD_DRV_LOG(ERR, "ethertype filters are full.");
4785                         return -ENOSYS;
4786                 }
4787         } else {
4788                 ret = igb_ethertype_filter_remove(filter_info, (uint8_t)ret);
4789                 if (ret < 0)
4790                         return -ENOSYS;
4791         }
4792         E1000_WRITE_REG(hw, E1000_ETQF(ret), etqf);
4793         E1000_WRITE_FLUSH(hw);
4794
4795         return 0;
4796 }
4797
4798 static int
4799 igb_get_ethertype_filter(struct rte_eth_dev *dev,
4800                         struct rte_eth_ethertype_filter *filter)
4801 {
4802         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4803         struct e1000_filter_info *filter_info =
4804                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4805         uint32_t etqf;
4806         int ret;
4807
4808         ret = igb_ethertype_filter_lookup(filter_info, filter->ether_type);
4809         if (ret < 0) {
4810                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
4811                             filter->ether_type);
4812                 return -ENOENT;
4813         }
4814
4815         etqf = E1000_READ_REG(hw, E1000_ETQF(ret));
4816         if (etqf & E1000_ETQF_FILTER_ENABLE) {
4817                 filter->ether_type = etqf & E1000_ETQF_ETHERTYPE;
4818                 filter->flags = 0;
4819                 filter->queue = (etqf & E1000_ETQF_QUEUE) >>
4820                                 E1000_ETQF_QUEUE_SHIFT;
4821                 return 0;
4822         }
4823
4824         return -ENOENT;
4825 }
4826
4827 /*
4828  * igb_ethertype_filter_handle - Handle operations for ethertype filter.
4829  * @dev: pointer to rte_eth_dev structure
4830  * @filter_op:operation will be taken.
4831  * @arg: a pointer to specific structure corresponding to the filter_op
4832  */
4833 static int
4834 igb_ethertype_filter_handle(struct rte_eth_dev *dev,
4835                                 enum rte_filter_op filter_op,
4836                                 void *arg)
4837 {
4838         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4839         int ret;
4840
4841         MAC_TYPE_FILTER_SUP(hw->mac.type);
4842
4843         if (filter_op == RTE_ETH_FILTER_NOP)
4844                 return 0;
4845
4846         if (arg == NULL) {
4847                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
4848                             filter_op);
4849                 return -EINVAL;
4850         }
4851
4852         switch (filter_op) {
4853         case RTE_ETH_FILTER_ADD:
4854                 ret = igb_add_del_ethertype_filter(dev,
4855                         (struct rte_eth_ethertype_filter *)arg,
4856                         TRUE);
4857                 break;
4858         case RTE_ETH_FILTER_DELETE:
4859                 ret = igb_add_del_ethertype_filter(dev,
4860                         (struct rte_eth_ethertype_filter *)arg,
4861                         FALSE);
4862                 break;
4863         case RTE_ETH_FILTER_GET:
4864                 ret = igb_get_ethertype_filter(dev,
4865                         (struct rte_eth_ethertype_filter *)arg);
4866                 break;
4867         default:
4868                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
4869                 ret = -EINVAL;
4870                 break;
4871         }
4872         return ret;
4873 }
4874
4875 static int
4876 eth_igb_filter_ctrl(struct rte_eth_dev *dev,
4877                      enum rte_filter_type filter_type,
4878                      enum rte_filter_op filter_op,
4879                      void *arg)
4880 {
4881         int ret = 0;
4882
4883         switch (filter_type) {
4884         case RTE_ETH_FILTER_NTUPLE:
4885                 ret = igb_ntuple_filter_handle(dev, filter_op, arg);
4886                 break;
4887         case RTE_ETH_FILTER_ETHERTYPE:
4888                 ret = igb_ethertype_filter_handle(dev, filter_op, arg);
4889                 break;
4890         case RTE_ETH_FILTER_SYN:
4891                 ret = eth_igb_syn_filter_handle(dev, filter_op, arg);
4892                 break;
4893         case RTE_ETH_FILTER_FLEXIBLE:
4894                 ret = eth_igb_flex_filter_handle(dev, filter_op, arg);
4895                 break;
4896         case RTE_ETH_FILTER_GENERIC:
4897                 if (filter_op != RTE_ETH_FILTER_GET)
4898                         return -EINVAL;
4899                 *(const void **)arg = &igb_flow_ops;
4900                 break;
4901         default:
4902                 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
4903                                                         filter_type);
4904                 break;
4905         }
4906
4907         return ret;
4908 }
4909
4910 static int
4911 eth_igb_set_mc_addr_list(struct rte_eth_dev *dev,
4912                          struct ether_addr *mc_addr_set,
4913                          uint32_t nb_mc_addr)
4914 {
4915         struct e1000_hw *hw;
4916
4917         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4918         e1000_update_mc_addr_list(hw, (u8 *)mc_addr_set, nb_mc_addr);
4919         return 0;
4920 }
4921
4922 static uint64_t
4923 igb_read_systime_cyclecounter(struct rte_eth_dev *dev)
4924 {
4925         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4926         uint64_t systime_cycles;
4927
4928         switch (hw->mac.type) {
4929         case e1000_i210:
4930         case e1000_i211:
4931                 /*
4932                  * Need to read System Time Residue Register to be able
4933                  * to read the other two registers.
4934                  */
4935                 E1000_READ_REG(hw, E1000_SYSTIMR);
4936                 /* SYSTIMEL stores ns and SYSTIMEH stores seconds. */
4937                 systime_cycles = (uint64_t)E1000_READ_REG(hw, E1000_SYSTIML);
4938                 systime_cycles += (uint64_t)E1000_READ_REG(hw, E1000_SYSTIMH)
4939                                 * NSEC_PER_SEC;
4940                 break;
4941         case e1000_82580:
4942         case e1000_i350:
4943         case e1000_i354:
4944                 /*
4945                  * Need to read System Time Residue Register to be able
4946                  * to read the other two registers.
4947                  */
4948                 E1000_READ_REG(hw, E1000_SYSTIMR);
4949                 systime_cycles = (uint64_t)E1000_READ_REG(hw, E1000_SYSTIML);
4950                 /* Only the 8 LSB are valid. */
4951                 systime_cycles |= (uint64_t)(E1000_READ_REG(hw, E1000_SYSTIMH)
4952                                 & 0xff) << 32;
4953                 break;
4954         default:
4955                 systime_cycles = (uint64_t)E1000_READ_REG(hw, E1000_SYSTIML);
4956                 systime_cycles |= (uint64_t)E1000_READ_REG(hw, E1000_SYSTIMH)
4957                                 << 32;
4958                 break;
4959         }
4960
4961         return systime_cycles;
4962 }
4963
4964 static uint64_t
4965 igb_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev)
4966 {
4967         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4968         uint64_t rx_tstamp_cycles;
4969
4970         switch (hw->mac.type) {
4971         case e1000_i210:
4972         case e1000_i211:
4973                 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
4974                 rx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_RXSTMPL);
4975                 rx_tstamp_cycles += (uint64_t)E1000_READ_REG(hw, E1000_RXSTMPH)
4976                                 * NSEC_PER_SEC;
4977                 break;
4978         case e1000_82580:
4979         case e1000_i350:
4980         case e1000_i354:
4981                 rx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_RXSTMPL);
4982                 /* Only the 8 LSB are valid. */
4983                 rx_tstamp_cycles |= (uint64_t)(E1000_READ_REG(hw, E1000_RXSTMPH)
4984                                 & 0xff) << 32;
4985                 break;
4986         default:
4987                 rx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_RXSTMPL);
4988                 rx_tstamp_cycles |= (uint64_t)E1000_READ_REG(hw, E1000_RXSTMPH)
4989                                 << 32;
4990                 break;
4991         }
4992
4993         return rx_tstamp_cycles;
4994 }
4995
4996 static uint64_t
4997 igb_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev)
4998 {
4999         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5000         uint64_t tx_tstamp_cycles;
5001
5002         switch (hw->mac.type) {
5003         case e1000_i210:
5004         case e1000_i211:
5005                 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
5006                 tx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_TXSTMPL);
5007                 tx_tstamp_cycles += (uint64_t)E1000_READ_REG(hw, E1000_TXSTMPH)
5008                                 * NSEC_PER_SEC;
5009                 break;
5010         case e1000_82580:
5011         case e1000_i350:
5012         case e1000_i354:
5013                 tx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_TXSTMPL);
5014                 /* Only the 8 LSB are valid. */
5015                 tx_tstamp_cycles |= (uint64_t)(E1000_READ_REG(hw, E1000_TXSTMPH)
5016                                 & 0xff) << 32;
5017                 break;
5018         default:
5019                 tx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_TXSTMPL);
5020                 tx_tstamp_cycles |= (uint64_t)E1000_READ_REG(hw, E1000_TXSTMPH)
5021                                 << 32;
5022                 break;
5023         }
5024
5025         return tx_tstamp_cycles;
5026 }
5027
5028 static void
5029 igb_start_timecounters(struct rte_eth_dev *dev)
5030 {
5031         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5032         struct e1000_adapter *adapter =
5033                 (struct e1000_adapter *)dev->data->dev_private;
5034         uint32_t incval = 1;
5035         uint32_t shift = 0;
5036         uint64_t mask = E1000_CYCLECOUNTER_MASK;
5037
5038         switch (hw->mac.type) {
5039         case e1000_82580:
5040         case e1000_i350:
5041         case e1000_i354:
5042                 /* 32 LSB bits + 8 MSB bits = 40 bits */
5043                 mask = (1ULL << 40) - 1;
5044                 /* fall-through */
5045         case e1000_i210:
5046         case e1000_i211:
5047                 /*
5048                  * Start incrementing the register
5049                  * used to timestamp PTP packets.
5050                  */
5051                 E1000_WRITE_REG(hw, E1000_TIMINCA, incval);
5052                 break;
5053         case e1000_82576:
5054                 incval = E1000_INCVALUE_82576;
5055                 shift = IGB_82576_TSYNC_SHIFT;
5056                 E1000_WRITE_REG(hw, E1000_TIMINCA,
5057                                 E1000_INCPERIOD_82576 | incval);
5058                 break;
5059         default:
5060                 /* Not supported */
5061                 return;
5062         }
5063
5064         memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter));
5065         memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
5066         memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
5067
5068         adapter->systime_tc.cc_mask = mask;
5069         adapter->systime_tc.cc_shift = shift;
5070         adapter->systime_tc.nsec_mask = (1ULL << shift) - 1;
5071
5072         adapter->rx_tstamp_tc.cc_mask = mask;
5073         adapter->rx_tstamp_tc.cc_shift = shift;
5074         adapter->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
5075
5076         adapter->tx_tstamp_tc.cc_mask = mask;
5077         adapter->tx_tstamp_tc.cc_shift = shift;
5078         adapter->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
5079 }
5080
5081 static int
5082 igb_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
5083 {
5084         struct e1000_adapter *adapter =
5085                         (struct e1000_adapter *)dev->data->dev_private;
5086
5087         adapter->systime_tc.nsec += delta;
5088         adapter->rx_tstamp_tc.nsec += delta;
5089         adapter->tx_tstamp_tc.nsec += delta;
5090
5091         return 0;
5092 }
5093
5094 static int
5095 igb_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
5096 {
5097         uint64_t ns;
5098         struct e1000_adapter *adapter =
5099                         (struct e1000_adapter *)dev->data->dev_private;
5100
5101         ns = rte_timespec_to_ns(ts);
5102
5103         /* Set the timecounters to a new value. */
5104         adapter->systime_tc.nsec = ns;
5105         adapter->rx_tstamp_tc.nsec = ns;
5106         adapter->tx_tstamp_tc.nsec = ns;
5107
5108         return 0;
5109 }
5110
5111 static int
5112 igb_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
5113 {
5114         uint64_t ns, systime_cycles;
5115         struct e1000_adapter *adapter =
5116                         (struct e1000_adapter *)dev->data->dev_private;
5117
5118         systime_cycles = igb_read_systime_cyclecounter(dev);
5119         ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles);
5120         *ts = rte_ns_to_timespec(ns);
5121
5122         return 0;
5123 }
5124
5125 static int
5126 igb_timesync_enable(struct rte_eth_dev *dev)
5127 {
5128         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5129         uint32_t tsync_ctl;
5130         uint32_t tsauxc;
5131
5132         /* Stop the timesync system time. */
5133         E1000_WRITE_REG(hw, E1000_TIMINCA, 0x0);
5134         /* Reset the timesync system time value. */
5135         switch (hw->mac.type) {
5136         case e1000_82580:
5137         case e1000_i350:
5138         case e1000_i354:
5139         case e1000_i210:
5140         case e1000_i211:
5141                 E1000_WRITE_REG(hw, E1000_SYSTIMR, 0x0);
5142                 /* fall-through */
5143         case e1000_82576:
5144                 E1000_WRITE_REG(hw, E1000_SYSTIML, 0x0);
5145                 E1000_WRITE_REG(hw, E1000_SYSTIMH, 0x0);
5146                 break;
5147         default:
5148                 /* Not supported. */
5149                 return -ENOTSUP;
5150         }
5151
5152         /* Enable system time for it isn't on by default. */
5153         tsauxc = E1000_READ_REG(hw, E1000_TSAUXC);
5154         tsauxc &= ~E1000_TSAUXC_DISABLE_SYSTIME;
5155         E1000_WRITE_REG(hw, E1000_TSAUXC, tsauxc);
5156
5157         igb_start_timecounters(dev);
5158
5159         /* Enable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
5160         E1000_WRITE_REG(hw, E1000_ETQF(E1000_ETQF_FILTER_1588),
5161                         (ETHER_TYPE_1588 |
5162                          E1000_ETQF_FILTER_ENABLE |
5163                          E1000_ETQF_1588));
5164
5165         /* Enable timestamping of received PTP packets. */
5166         tsync_ctl = E1000_READ_REG(hw, E1000_TSYNCRXCTL);
5167         tsync_ctl |= E1000_TSYNCRXCTL_ENABLED;
5168         E1000_WRITE_REG(hw, E1000_TSYNCRXCTL, tsync_ctl);
5169
5170         /* Enable Timestamping of transmitted PTP packets. */
5171         tsync_ctl = E1000_READ_REG(hw, E1000_TSYNCTXCTL);
5172         tsync_ctl |= E1000_TSYNCTXCTL_ENABLED;
5173         E1000_WRITE_REG(hw, E1000_TSYNCTXCTL, tsync_ctl);
5174
5175         return 0;
5176 }
5177
5178 static int
5179 igb_timesync_disable(struct rte_eth_dev *dev)
5180 {
5181         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5182         uint32_t tsync_ctl;
5183
5184         /* Disable timestamping of transmitted PTP packets. */
5185         tsync_ctl = E1000_READ_REG(hw, E1000_TSYNCTXCTL);
5186         tsync_ctl &= ~E1000_TSYNCTXCTL_ENABLED;
5187         E1000_WRITE_REG(hw, E1000_TSYNCTXCTL, tsync_ctl);
5188
5189         /* Disable timestamping of received PTP packets. */
5190         tsync_ctl = E1000_READ_REG(hw, E1000_TSYNCRXCTL);
5191         tsync_ctl &= ~E1000_TSYNCRXCTL_ENABLED;
5192         E1000_WRITE_REG(hw, E1000_TSYNCRXCTL, tsync_ctl);
5193
5194         /* Disable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
5195         E1000_WRITE_REG(hw, E1000_ETQF(E1000_ETQF_FILTER_1588), 0);
5196
5197         /* Stop incrementating the System Time registers. */
5198         E1000_WRITE_REG(hw, E1000_TIMINCA, 0);
5199
5200         return 0;
5201 }
5202
5203 static int
5204 igb_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
5205                                struct timespec *timestamp,
5206                                uint32_t flags __rte_unused)
5207 {
5208         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5209         struct e1000_adapter *adapter =
5210                         (struct e1000_adapter *)dev->data->dev_private;
5211         uint32_t tsync_rxctl;
5212         uint64_t rx_tstamp_cycles;
5213         uint64_t ns;
5214
5215         tsync_rxctl = E1000_READ_REG(hw, E1000_TSYNCRXCTL);
5216         if ((tsync_rxctl & E1000_TSYNCRXCTL_VALID) == 0)
5217                 return -EINVAL;
5218
5219         rx_tstamp_cycles = igb_read_rx_tstamp_cyclecounter(dev);
5220         ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles);
5221         *timestamp = rte_ns_to_timespec(ns);
5222
5223         return  0;
5224 }
5225
5226 static int
5227 igb_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
5228                                struct timespec *timestamp)
5229 {
5230         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5231         struct e1000_adapter *adapter =
5232                         (struct e1000_adapter *)dev->data->dev_private;
5233         uint32_t tsync_txctl;
5234         uint64_t tx_tstamp_cycles;
5235         uint64_t ns;
5236
5237         tsync_txctl = E1000_READ_REG(hw, E1000_TSYNCTXCTL);
5238         if ((tsync_txctl & E1000_TSYNCTXCTL_VALID) == 0)
5239                 return -EINVAL;
5240
5241         tx_tstamp_cycles = igb_read_tx_tstamp_cyclecounter(dev);
5242         ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles);
5243         *timestamp = rte_ns_to_timespec(ns);
5244
5245         return  0;
5246 }
5247
5248 static int
5249 eth_igb_get_reg_length(struct rte_eth_dev *dev __rte_unused)
5250 {
5251         int count = 0;
5252         int g_ind = 0;
5253         const struct reg_info *reg_group;
5254
5255         while ((reg_group = igb_regs[g_ind++]))
5256                 count += igb_reg_group_count(reg_group);
5257
5258         return count;
5259 }
5260
5261 static int
5262 igbvf_get_reg_length(struct rte_eth_dev *dev __rte_unused)
5263 {
5264         int count = 0;
5265         int g_ind = 0;
5266         const struct reg_info *reg_group;
5267
5268         while ((reg_group = igbvf_regs[g_ind++]))
5269                 count += igb_reg_group_count(reg_group);
5270
5271         return count;
5272 }
5273
5274 static int
5275 eth_igb_get_regs(struct rte_eth_dev *dev,
5276         struct rte_dev_reg_info *regs)
5277 {
5278         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5279         uint32_t *data = regs->data;
5280         int g_ind = 0;
5281         int count = 0;
5282         const struct reg_info *reg_group;
5283
5284         if (data == NULL) {
5285                 regs->length = eth_igb_get_reg_length(dev);
5286                 regs->width = sizeof(uint32_t);
5287                 return 0;
5288         }
5289
5290         /* Support only full register dump */
5291         if ((regs->length == 0) ||
5292             (regs->length == (uint32_t)eth_igb_get_reg_length(dev))) {
5293                 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
5294                         hw->device_id;
5295                 while ((reg_group = igb_regs[g_ind++]))
5296                         count += igb_read_regs_group(dev, &data[count],
5297                                                         reg_group);
5298                 return 0;
5299         }
5300
5301         return -ENOTSUP;
5302 }
5303
5304 static int
5305 igbvf_get_regs(struct rte_eth_dev *dev,
5306         struct rte_dev_reg_info *regs)
5307 {
5308         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5309         uint32_t *data = regs->data;
5310         int g_ind = 0;
5311         int count = 0;
5312         const struct reg_info *reg_group;
5313
5314         if (data == NULL) {
5315                 regs->length = igbvf_get_reg_length(dev);
5316                 regs->width = sizeof(uint32_t);
5317                 return 0;
5318         }
5319
5320         /* Support only full register dump */
5321         if ((regs->length == 0) ||
5322             (regs->length == (uint32_t)igbvf_get_reg_length(dev))) {
5323                 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
5324                         hw->device_id;
5325                 while ((reg_group = igbvf_regs[g_ind++]))
5326                         count += igb_read_regs_group(dev, &data[count],
5327                                                         reg_group);
5328                 return 0;
5329         }
5330
5331         return -ENOTSUP;
5332 }
5333
5334 static int
5335 eth_igb_get_eeprom_length(struct rte_eth_dev *dev)
5336 {
5337         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5338
5339         /* Return unit is byte count */
5340         return hw->nvm.word_size * 2;
5341 }
5342
5343 static int
5344 eth_igb_get_eeprom(struct rte_eth_dev *dev,
5345         struct rte_dev_eeprom_info *in_eeprom)
5346 {
5347         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5348         struct e1000_nvm_info *nvm = &hw->nvm;
5349         uint16_t *data = in_eeprom->data;
5350         int first, length;
5351
5352         first = in_eeprom->offset >> 1;
5353         length = in_eeprom->length >> 1;
5354         if ((first >= hw->nvm.word_size) ||
5355             ((first + length) >= hw->nvm.word_size))
5356                 return -EINVAL;
5357
5358         in_eeprom->magic = hw->vendor_id |
5359                 ((uint32_t)hw->device_id << 16);
5360
5361         if ((nvm->ops.read) == NULL)
5362                 return -ENOTSUP;
5363
5364         return nvm->ops.read(hw, first, length, data);
5365 }
5366
5367 static int
5368 eth_igb_set_eeprom(struct rte_eth_dev *dev,
5369         struct rte_dev_eeprom_info *in_eeprom)
5370 {
5371         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5372         struct e1000_nvm_info *nvm = &hw->nvm;
5373         uint16_t *data = in_eeprom->data;
5374         int first, length;
5375
5376         first = in_eeprom->offset >> 1;
5377         length = in_eeprom->length >> 1;
5378         if ((first >= hw->nvm.word_size) ||
5379             ((first + length) >= hw->nvm.word_size))
5380                 return -EINVAL;
5381
5382         in_eeprom->magic = (uint32_t)hw->vendor_id |
5383                 ((uint32_t)hw->device_id << 16);
5384
5385         if ((nvm->ops.write) == NULL)
5386                 return -ENOTSUP;
5387         return nvm->ops.write(hw,  first, length, data);
5388 }
5389
5390 static int
5391 eth_igb_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
5392 {
5393         struct e1000_hw *hw =
5394                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5395         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5396         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5397         uint32_t vec = E1000_MISC_VEC_ID;
5398
5399         if (rte_intr_allow_others(intr_handle))
5400                 vec = E1000_RX_VEC_START;
5401
5402         uint32_t mask = 1 << (queue_id + vec);
5403
5404         E1000_WRITE_REG(hw, E1000_EIMC, mask);
5405         E1000_WRITE_FLUSH(hw);
5406
5407         return 0;
5408 }
5409
5410 static int
5411 eth_igb_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
5412 {
5413         struct e1000_hw *hw =
5414                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5415         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5416         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5417         uint32_t vec = E1000_MISC_VEC_ID;
5418
5419         if (rte_intr_allow_others(intr_handle))
5420                 vec = E1000_RX_VEC_START;
5421
5422         uint32_t mask = 1 << (queue_id + vec);
5423         uint32_t regval;
5424
5425         regval = E1000_READ_REG(hw, E1000_EIMS);
5426         E1000_WRITE_REG(hw, E1000_EIMS, regval | mask);
5427         E1000_WRITE_FLUSH(hw);
5428
5429         rte_intr_enable(intr_handle);
5430
5431         return 0;
5432 }
5433
5434 static void
5435 eth_igb_write_ivar(struct e1000_hw *hw, uint8_t  msix_vector,
5436                    uint8_t index, uint8_t offset)
5437 {
5438         uint32_t val = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index);
5439
5440         /* clear bits */
5441         val &= ~((uint32_t)0xFF << offset);
5442
5443         /* write vector and valid bit */
5444         val |= (msix_vector | E1000_IVAR_VALID) << offset;
5445
5446         E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, val);
5447 }
5448
5449 static void
5450 eth_igb_assign_msix_vector(struct e1000_hw *hw, int8_t direction,
5451                            uint8_t queue, uint8_t msix_vector)
5452 {
5453         uint32_t tmp = 0;
5454
5455         if (hw->mac.type == e1000_82575) {
5456                 if (direction == 0)
5457                         tmp = E1000_EICR_RX_QUEUE0 << queue;
5458                 else if (direction == 1)
5459                         tmp = E1000_EICR_TX_QUEUE0 << queue;
5460                 E1000_WRITE_REG(hw, E1000_MSIXBM(msix_vector), tmp);
5461         } else if (hw->mac.type == e1000_82576) {
5462                 if ((direction == 0) || (direction == 1))
5463                         eth_igb_write_ivar(hw, msix_vector, queue & 0x7,
5464                                            ((queue & 0x8) << 1) +
5465                                            8 * direction);
5466         } else if ((hw->mac.type == e1000_82580) ||
5467                         (hw->mac.type == e1000_i350) ||
5468                         (hw->mac.type == e1000_i354) ||
5469                         (hw->mac.type == e1000_i210) ||
5470                         (hw->mac.type == e1000_i211)) {
5471                 if ((direction == 0) || (direction == 1))
5472                         eth_igb_write_ivar(hw, msix_vector,
5473                                            queue >> 1,
5474                                            ((queue & 0x1) << 4) +
5475                                            8 * direction);
5476         }
5477 }
5478
5479 /* Sets up the hardware to generate MSI-X interrupts properly
5480  * @hw
5481  *  board private structure
5482  */
5483 static void
5484 eth_igb_configure_msix_intr(struct rte_eth_dev *dev)
5485 {
5486         int queue_id;
5487         uint32_t tmpval, regval, intr_mask;
5488         struct e1000_hw *hw =
5489                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5490         uint32_t vec = E1000_MISC_VEC_ID;
5491         uint32_t base = E1000_MISC_VEC_ID;
5492         uint32_t misc_shift = 0;
5493         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5494         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5495
5496         /* won't configure msix register if no mapping is done
5497          * between intr vector and event fd
5498          */
5499         if (!rte_intr_dp_is_en(intr_handle))
5500                 return;
5501
5502         if (rte_intr_allow_others(intr_handle)) {
5503                 vec = base = E1000_RX_VEC_START;
5504                 misc_shift = 1;
5505         }
5506
5507         /* set interrupt vector for other causes */
5508         if (hw->mac.type == e1000_82575) {
5509                 tmpval = E1000_READ_REG(hw, E1000_CTRL_EXT);
5510                 /* enable MSI-X PBA support */
5511                 tmpval |= E1000_CTRL_EXT_PBA_CLR;
5512
5513                 /* Auto-Mask interrupts upon ICR read */
5514                 tmpval |= E1000_CTRL_EXT_EIAME;
5515                 tmpval |= E1000_CTRL_EXT_IRCA;
5516
5517                 E1000_WRITE_REG(hw, E1000_CTRL_EXT, tmpval);
5518
5519                 /* enable msix_other interrupt */
5520                 E1000_WRITE_REG_ARRAY(hw, E1000_MSIXBM(0), 0, E1000_EIMS_OTHER);
5521                 regval = E1000_READ_REG(hw, E1000_EIAC);
5522                 E1000_WRITE_REG(hw, E1000_EIAC, regval | E1000_EIMS_OTHER);
5523                 regval = E1000_READ_REG(hw, E1000_EIAM);
5524                 E1000_WRITE_REG(hw, E1000_EIMS, regval | E1000_EIMS_OTHER);
5525         } else if ((hw->mac.type == e1000_82576) ||
5526                         (hw->mac.type == e1000_82580) ||
5527                         (hw->mac.type == e1000_i350) ||
5528                         (hw->mac.type == e1000_i354) ||
5529                         (hw->mac.type == e1000_i210) ||
5530                         (hw->mac.type == e1000_i211)) {
5531                 /* turn on MSI-X capability first */
5532                 E1000_WRITE_REG(hw, E1000_GPIE, E1000_GPIE_MSIX_MODE |
5533                                         E1000_GPIE_PBA | E1000_GPIE_EIAME |
5534                                         E1000_GPIE_NSICR);
5535                 intr_mask = RTE_LEN2MASK(intr_handle->nb_efd, uint32_t) <<
5536                         misc_shift;
5537                 regval = E1000_READ_REG(hw, E1000_EIAC);
5538                 E1000_WRITE_REG(hw, E1000_EIAC, regval | intr_mask);
5539
5540                 /* enable msix_other interrupt */
5541                 regval = E1000_READ_REG(hw, E1000_EIMS);
5542                 E1000_WRITE_REG(hw, E1000_EIMS, regval | intr_mask);
5543                 tmpval = (dev->data->nb_rx_queues | E1000_IVAR_VALID) << 8;
5544                 E1000_WRITE_REG(hw, E1000_IVAR_MISC, tmpval);
5545         }
5546
5547         /* use EIAM to auto-mask when MSI-X interrupt
5548          * is asserted, this saves a register write for every interrupt
5549          */
5550         intr_mask = RTE_LEN2MASK(intr_handle->nb_efd, uint32_t) <<
5551                 misc_shift;
5552         regval = E1000_READ_REG(hw, E1000_EIAM);
5553         E1000_WRITE_REG(hw, E1000_EIAM, regval | intr_mask);
5554
5555         for (queue_id = 0; queue_id < dev->data->nb_rx_queues; queue_id++) {
5556                 eth_igb_assign_msix_vector(hw, 0, queue_id, vec);
5557                 intr_handle->intr_vec[queue_id] = vec;
5558                 if (vec < base + intr_handle->nb_efd - 1)
5559                         vec++;
5560         }
5561
5562         E1000_WRITE_FLUSH(hw);
5563 }
5564
5565 /* restore n-tuple filter */
5566 static inline void
5567 igb_ntuple_filter_restore(struct rte_eth_dev *dev)
5568 {
5569         struct e1000_filter_info *filter_info =
5570                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5571         struct e1000_5tuple_filter *p_5tuple;
5572         struct e1000_2tuple_filter *p_2tuple;
5573
5574         TAILQ_FOREACH(p_5tuple, &filter_info->fivetuple_list, entries) {
5575                 igb_inject_5tuple_filter_82576(dev, p_5tuple);
5576         }
5577
5578         TAILQ_FOREACH(p_2tuple, &filter_info->twotuple_list, entries) {
5579                 igb_inject_2uple_filter(dev, p_2tuple);
5580         }
5581 }
5582
5583 /* restore SYN filter */
5584 static inline void
5585 igb_syn_filter_restore(struct rte_eth_dev *dev)
5586 {
5587         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5588         struct e1000_filter_info *filter_info =
5589                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5590         uint32_t synqf;
5591
5592         synqf = filter_info->syn_info;
5593
5594         if (synqf & E1000_SYN_FILTER_ENABLE) {
5595                 E1000_WRITE_REG(hw, E1000_SYNQF(0), synqf);
5596                 E1000_WRITE_FLUSH(hw);
5597         }
5598 }
5599
5600 /* restore ethernet type filter */
5601 static inline void
5602 igb_ethertype_filter_restore(struct rte_eth_dev *dev)
5603 {
5604         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5605         struct e1000_filter_info *filter_info =
5606                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5607         int i;
5608
5609         for (i = 0; i < E1000_MAX_ETQF_FILTERS; i++) {
5610                 if (filter_info->ethertype_mask & (1 << i)) {
5611                         E1000_WRITE_REG(hw, E1000_ETQF(i),
5612                                 filter_info->ethertype_filters[i].etqf);
5613                         E1000_WRITE_FLUSH(hw);
5614                 }
5615         }
5616 }
5617
5618 /* restore flex byte filter */
5619 static inline void
5620 igb_flex_filter_restore(struct rte_eth_dev *dev)
5621 {
5622         struct e1000_filter_info *filter_info =
5623                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5624         struct e1000_flex_filter *flex_filter;
5625
5626         TAILQ_FOREACH(flex_filter, &filter_info->flex_list, entries) {
5627                 igb_inject_flex_filter(dev, flex_filter);
5628         }
5629 }
5630
5631 /* restore all types filter */
5632 static int
5633 igb_filter_restore(struct rte_eth_dev *dev)
5634 {
5635         igb_ntuple_filter_restore(dev);
5636         igb_ethertype_filter_restore(dev);
5637         igb_syn_filter_restore(dev);
5638         igb_flex_filter_restore(dev);
5639
5640         return 0;
5641 }
5642
5643 RTE_PMD_REGISTER_PCI(net_e1000_igb, rte_igb_pmd);
5644 RTE_PMD_REGISTER_PCI_TABLE(net_e1000_igb, pci_id_igb_map);
5645 RTE_PMD_REGISTER_KMOD_DEP(net_e1000_igb, "* igb_uio | uio_pci_generic | vfio-pci");
5646 RTE_PMD_REGISTER_PCI(net_e1000_igb_vf, rte_igbvf_pmd);
5647 RTE_PMD_REGISTER_PCI_TABLE(net_e1000_igb_vf, pci_id_igbvf_map);
5648 RTE_PMD_REGISTER_KMOD_DEP(net_e1000_igb_vf, "* igb_uio | vfio-pci");