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42 #include <rte_interrupts.h>
44 #include <rte_debug.h>
46 #include <rte_ether.h>
47 #include <rte_ethdev.h>
48 #include <rte_memcpy.h>
49 #include <rte_malloc.h>
50 #include <rte_random.h>
52 #include "base/e1000_defines.h"
53 #include "base/e1000_regs.h"
54 #include "base/e1000_hw.h"
55 #include "e1000_ethdev.h"
57 static inline uint16_t
58 dev_num_vf(struct rte_eth_dev *eth_dev)
60 return eth_dev->pci_dev->max_vfs;
64 int igb_vf_perm_addr_gen(struct rte_eth_dev *dev, uint16_t vf_num)
66 unsigned char vf_mac_addr[ETHER_ADDR_LEN];
67 struct e1000_vf_info *vfinfo =
68 *E1000_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
71 for (vfn = 0; vfn < vf_num; vfn++) {
72 eth_random_addr(vf_mac_addr);
73 /* keep the random address as default */
74 memcpy(vfinfo[vfn].vf_mac_addresses, vf_mac_addr,
82 igb_mb_intr_setup(struct rte_eth_dev *dev)
84 struct e1000_interrupt *intr =
85 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
87 intr->mask |= E1000_ICR_VMMB;
92 void igb_pf_host_init(struct rte_eth_dev *eth_dev)
94 struct e1000_vf_info **vfinfo =
95 E1000_DEV_PRIVATE_TO_P_VFDATA(eth_dev->data->dev_private);
97 E1000_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
101 RTE_ETH_DEV_SRIOV(eth_dev).active = 0;
102 if (0 == (vf_num = dev_num_vf(eth_dev)))
105 if (hw->mac.type == e1000_i350)
107 else if(hw->mac.type == e1000_82576)
108 /* per datasheet, it should be 2, but 1 seems correct */
113 *vfinfo = rte_zmalloc("vf_info", sizeof(struct e1000_vf_info) * vf_num, 0);
115 rte_panic("Cannot allocate memory for private VF data\n");
117 RTE_ETH_DEV_SRIOV(eth_dev).active = ETH_8_POOLS;
118 RTE_ETH_DEV_SRIOV(eth_dev).nb_q_per_pool = nb_queue;
119 RTE_ETH_DEV_SRIOV(eth_dev).def_vmdq_idx = vf_num;
120 RTE_ETH_DEV_SRIOV(eth_dev).def_pool_q_idx = (uint16_t)(vf_num * nb_queue);
122 igb_vf_perm_addr_gen(eth_dev, vf_num);
124 /* set mb interrupt mask */
125 igb_mb_intr_setup(eth_dev);
130 void igb_pf_host_uninit(struct rte_eth_dev *dev)
132 struct e1000_vf_info **vfinfo;
135 PMD_INIT_FUNC_TRACE();
137 vfinfo = E1000_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
139 RTE_ETH_DEV_SRIOV(dev).active = 0;
140 RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool = 0;
141 RTE_ETH_DEV_SRIOV(dev).def_vmdq_idx = 0;
142 RTE_ETH_DEV_SRIOV(dev).def_pool_q_idx = 0;
144 vf_num = dev_num_vf(dev);
152 #define E1000_RAH_POOLSEL_SHIFT (18)
153 int igb_pf_host_configure(struct rte_eth_dev *eth_dev)
157 struct e1000_hw *hw =
158 E1000_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
163 if (0 == (vf_num = dev_num_vf(eth_dev)))
166 /* enable VMDq and set the default pool for PF */
167 vtctl = E1000_READ_REG(hw, E1000_VT_CTL);
168 vtctl &= ~E1000_VT_CTL_DEFAULT_POOL_MASK;
169 vtctl |= RTE_ETH_DEV_SRIOV(eth_dev).def_vmdq_idx
170 << E1000_VT_CTL_DEFAULT_POOL_SHIFT;
171 vtctl |= E1000_VT_CTL_VM_REPL_EN;
172 E1000_WRITE_REG(hw, E1000_VT_CTL, vtctl);
174 /* Enable pools reserved to PF only */
175 E1000_WRITE_REG(hw, E1000_VFRE, (~0U) << vf_num);
176 E1000_WRITE_REG(hw, E1000_VFTE, (~0U) << vf_num);
178 /* PFDMA Tx General Switch Control Enables VMDQ loopback */
179 if (hw->mac.type == e1000_i350)
180 E1000_WRITE_REG(hw, E1000_TXSWC, E1000_DTXSWC_VMDQ_LOOPBACK_EN);
182 E1000_WRITE_REG(hw, E1000_DTXSWC, E1000_DTXSWC_VMDQ_LOOPBACK_EN);
184 /* clear VMDq map to perment rar 0 */
185 rah = E1000_READ_REG(hw, E1000_RAH(0));
186 rah &= ~ (0xFF << E1000_RAH_POOLSEL_SHIFT);
187 E1000_WRITE_REG(hw, E1000_RAH(0), rah);
189 /* clear VMDq map to scan rar 32 */
190 rah = E1000_READ_REG(hw, E1000_RAH(hw->mac.rar_entry_count));
191 rah &= ~ (0xFF << E1000_RAH_POOLSEL_SHIFT);
192 E1000_WRITE_REG(hw, E1000_RAH(hw->mac.rar_entry_count), rah);
194 /* set VMDq map to default PF pool */
195 rah = E1000_READ_REG(hw, E1000_RAH(0));
196 rah |= (0x1 << (RTE_ETH_DEV_SRIOV(eth_dev).def_vmdq_idx +
197 E1000_RAH_POOLSEL_SHIFT));
198 E1000_WRITE_REG(hw, E1000_RAH(0), rah);
201 * enable vlan filtering and allow all vlan tags through
203 vlanctrl = E1000_READ_REG(hw, E1000_RCTL);
204 vlanctrl |= E1000_RCTL_VFE ; /* enable vlan filters */
205 E1000_WRITE_REG(hw, E1000_RCTL, vlanctrl);
207 /* VFTA - enable all vlan filters */
208 for (i = 0; i < IGB_VFTA_SIZE; i++) {
209 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, i, 0xFFFFFFFF);
212 /* Enable/Disable MAC Anti-Spoofing */
213 e1000_vmdq_set_anti_spoofing_pf(hw, FALSE, vf_num);
219 set_rx_mode(struct rte_eth_dev *dev)
221 struct rte_eth_dev_data *dev_data = dev->data;
222 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
223 uint32_t fctrl, vmolr = E1000_VMOLR_BAM | E1000_VMOLR_AUPE;
224 uint16_t vfn = dev_num_vf(dev);
226 /* Check for Promiscuous and All Multicast modes */
227 fctrl = E1000_READ_REG(hw, E1000_RCTL);
229 /* set all bits that we expect to always be set */
230 fctrl &= ~E1000_RCTL_SBP; /* disable store-bad-packets */
231 fctrl |= E1000_RCTL_BAM;
233 /* clear the bits we are changing the status of */
234 fctrl &= ~(E1000_RCTL_UPE | E1000_RCTL_MPE);
236 if (dev_data->promiscuous) {
237 fctrl |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
238 vmolr |= (E1000_VMOLR_ROPE | E1000_VMOLR_MPME);
240 if (dev_data->all_multicast) {
241 fctrl |= E1000_RCTL_MPE;
242 vmolr |= E1000_VMOLR_MPME;
244 vmolr |= E1000_VMOLR_ROMPE;
248 if ((hw->mac.type == e1000_82576) ||
249 (hw->mac.type == e1000_i350)) {
250 vmolr |= E1000_READ_REG(hw, E1000_VMOLR(vfn)) &
251 ~(E1000_VMOLR_MPME | E1000_VMOLR_ROMPE |
253 E1000_WRITE_REG(hw, E1000_VMOLR(vfn), vmolr);
256 E1000_WRITE_REG(hw, E1000_RCTL, fctrl);
260 igb_vf_reset_event(struct rte_eth_dev *dev, uint16_t vf)
262 struct e1000_hw *hw =
263 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
264 struct e1000_vf_info *vfinfo =
265 *(E1000_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private));
266 uint32_t vmolr = E1000_READ_REG(hw, E1000_VMOLR(vf));
268 vmolr |= (E1000_VMOLR_ROPE | E1000_VMOLR_ROMPE |
269 E1000_VMOLR_BAM | E1000_VMOLR_AUPE);
270 E1000_WRITE_REG(hw, E1000_VMOLR(vf), vmolr);
272 E1000_WRITE_REG(hw, E1000_VMVIR(vf), 0);
274 /* reset multicast table array for vf */
275 vfinfo[vf].num_vf_mc_hashes = 0;
282 igb_vf_reset_msg(struct rte_eth_dev *dev, uint16_t vf)
284 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
287 /* enable transmit and receive for vf */
288 reg = E1000_READ_REG(hw, E1000_VFTE);
289 reg |= (reg | (1 << vf));
290 E1000_WRITE_REG(hw, E1000_VFTE, reg);
292 reg = E1000_READ_REG(hw, E1000_VFRE);
293 reg |= (reg | (1 << vf));
294 E1000_WRITE_REG(hw, E1000_VFRE, reg);
296 igb_vf_reset_event(dev, vf);
300 igb_vf_reset(struct rte_eth_dev *dev, uint16_t vf, uint32_t *msgbuf)
302 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
303 struct e1000_vf_info *vfinfo =
304 *(E1000_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private));
305 unsigned char *vf_mac = vfinfo[vf].vf_mac_addresses;
306 int rar_entry = hw->mac.rar_entry_count - (vf + 1);
307 uint8_t *new_mac = (uint8_t *)(&msgbuf[1]);
310 igb_vf_reset_msg(dev, vf);
312 hw->mac.ops.rar_set(hw, vf_mac, rar_entry);
313 rah = E1000_READ_REG(hw, E1000_RAH(rar_entry));
314 rah |= (0x1 << (vf + E1000_RAH_POOLSEL_SHIFT));
315 E1000_WRITE_REG(hw, E1000_RAH(rar_entry), rah);
317 /* reply to reset with ack and vf mac address */
318 msgbuf[0] = E1000_VF_RESET | E1000_VT_MSGTYPE_ACK;
319 rte_memcpy(new_mac, vf_mac, ETHER_ADDR_LEN);
320 e1000_write_mbx(hw, msgbuf, 3, vf);
326 igb_vf_set_mac_addr(struct rte_eth_dev *dev, uint32_t vf, uint32_t *msgbuf)
328 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
329 struct e1000_vf_info *vfinfo =
330 *(E1000_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private));
331 int rar_entry = hw->mac.rar_entry_count - (vf + 1);
332 uint8_t *new_mac = (uint8_t *)(&msgbuf[1]);
335 if (is_unicast_ether_addr((struct ether_addr *)new_mac)) {
336 if (!is_zero_ether_addr((struct ether_addr *)new_mac))
337 rte_memcpy(vfinfo[vf].vf_mac_addresses, new_mac,
338 sizeof(vfinfo[vf].vf_mac_addresses));
339 hw->mac.ops.rar_set(hw, new_mac, rar_entry);
340 rah = E1000_READ_REG(hw, E1000_RAH(rar_entry));
341 rah |= (0x1 << (E1000_RAH_POOLSEL_SHIFT + vf));
342 E1000_WRITE_REG(hw, E1000_RAH(rar_entry), rah);
349 igb_vf_set_multicast(struct rte_eth_dev *dev, __rte_unused uint32_t vf, uint32_t *msgbuf)
355 int entries = (msgbuf[0] & E1000_VT_MSGINFO_MASK) >>
356 E1000_VT_MSGINFO_SHIFT;
357 uint16_t *hash_list = (uint16_t *)&msgbuf[1];
358 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
359 struct e1000_vf_info *vfinfo =
360 *(E1000_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private));
362 /* only so many hash values supported */
363 entries = RTE_MIN(entries, E1000_MAX_VF_MC_ENTRIES);
366 * salt away the number of multi cast addresses assigned
367 * to this VF for later use to restore when the PF multi cast
370 vfinfo->num_vf_mc_hashes = (uint16_t)entries;
373 * VFs are limited to using the MTA hash table for their multicast
376 for (i = 0; i < entries; i++) {
377 vfinfo->vf_mc_hashes[i] = hash_list[i];
380 for (i = 0; i < vfinfo->num_vf_mc_hashes; i++) {
381 vector_reg = (vfinfo->vf_mc_hashes[i] >> 5) & 0x7F;
382 vector_bit = vfinfo->vf_mc_hashes[i] & 0x1F;
383 mta_reg = E1000_READ_REG_ARRAY(hw, E1000_MTA, vector_reg);
384 mta_reg |= (1 << vector_bit);
385 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, vector_reg, mta_reg);
392 igb_vf_set_vlan(struct rte_eth_dev *dev, uint32_t vf, uint32_t *msgbuf)
395 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
396 struct e1000_vf_info *vfinfo =
397 *(E1000_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private));
398 uint32_t vid_idx, vid_bit, vfta;
400 add = (msgbuf[0] & E1000_VT_MSGINFO_MASK)
401 >> E1000_VT_MSGINFO_SHIFT;
402 vid = (msgbuf[1] & E1000_VLVF_VLANID_MASK);
405 vfinfo[vf].vlan_count++;
406 else if (vfinfo[vf].vlan_count)
407 vfinfo[vf].vlan_count--;
409 vid_idx = (uint32_t)((vid >> E1000_VFTA_ENTRY_SHIFT) &
410 E1000_VFTA_ENTRY_MASK);
411 vid_bit = (uint32_t)(1 << (vid & E1000_VFTA_ENTRY_BIT_SHIFT_MASK));
412 vfta = E1000_READ_REG_ARRAY(hw, E1000_VFTA, vid_idx);
418 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, vid_idx, vfta);
419 E1000_WRITE_FLUSH(hw);
425 igb_vf_set_rlpml(struct rte_eth_dev *dev, uint32_t vf, uint32_t *msgbuf)
427 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
428 uint16_t rlpml = msgbuf[1] & E1000_VMOLR_RLPML_MASK;
429 uint32_t max_frame = rlpml + ETHER_HDR_LEN + ETHER_CRC_LEN;
432 if ((max_frame < ETHER_MIN_LEN) || (max_frame > ETHER_MAX_JUMBO_FRAME_LEN))
435 vmolr = E1000_READ_REG(hw, E1000_VMOLR(vf));
437 vmolr &= ~E1000_VMOLR_RLPML_MASK;
440 /* Enable Long Packet support */
441 vmolr |= E1000_VMOLR_LPE;
443 E1000_WRITE_REG(hw, E1000_VMOLR(vf), vmolr);
444 E1000_WRITE_FLUSH(hw);
450 igb_rcv_msg_from_vf(struct rte_eth_dev *dev, uint16_t vf)
452 uint16_t mbx_size = E1000_VFMAILBOX_SIZE;
453 uint32_t msgbuf[E1000_VFMAILBOX_SIZE];
455 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
457 retval = e1000_read_mbx(hw, msgbuf, mbx_size, vf);
459 PMD_INIT_LOG(ERR, "Error mbx recv msg from VF %d", vf);
463 /* do nothing with the message already processed */
464 if (msgbuf[0] & (E1000_VT_MSGTYPE_ACK | E1000_VT_MSGTYPE_NACK))
467 /* flush the ack before we write any messages back */
468 E1000_WRITE_FLUSH(hw);
470 /* perform VF reset */
471 if (msgbuf[0] == E1000_VF_RESET) {
472 return igb_vf_reset(dev, vf, msgbuf);
475 /* check & process VF to PF mailbox message */
476 switch ((msgbuf[0] & 0xFFFF)) {
477 case E1000_VF_SET_MAC_ADDR:
478 retval = igb_vf_set_mac_addr(dev, vf, msgbuf);
480 case E1000_VF_SET_MULTICAST:
481 retval = igb_vf_set_multicast(dev, vf, msgbuf);
483 case E1000_VF_SET_LPE:
484 retval = igb_vf_set_rlpml(dev, vf, msgbuf);
486 case E1000_VF_SET_VLAN:
487 retval = igb_vf_set_vlan(dev, vf, msgbuf);
490 PMD_INIT_LOG(DEBUG, "Unhandled Msg %8.8x",
491 (unsigned) msgbuf[0]);
492 retval = E1000_ERR_MBX;
496 /* response the VF according to the message process result */
498 msgbuf[0] |= E1000_VT_MSGTYPE_NACK;
500 msgbuf[0] |= E1000_VT_MSGTYPE_ACK;
502 msgbuf[0] |= E1000_VT_MSGTYPE_CTS;
504 e1000_write_mbx(hw, msgbuf, 1, vf);
510 igb_rcv_ack_from_vf(struct rte_eth_dev *dev, uint16_t vf)
512 uint32_t msg = E1000_VT_MSGTYPE_NACK;
513 struct e1000_hw *hw =
514 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
516 e1000_write_mbx(hw, &msg, 1, vf);
519 void igb_pf_mbx_process(struct rte_eth_dev *eth_dev)
522 struct e1000_hw *hw =
523 E1000_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
525 for (vf = 0; vf < dev_num_vf(eth_dev); vf++) {
526 /* check & process vf function level reset */
527 if (!e1000_check_for_rst(hw, vf))
528 igb_vf_reset_event(eth_dev, vf);
530 /* check & process vf mailbox messages */
531 if (!e1000_check_for_msg(hw, vf))
532 igb_rcv_msg_from_vf(eth_dev, vf);
534 /* check & process acks from vf */
535 if (!e1000_check_for_ack(hw, vf))
536 igb_rcv_ack_from_vf(eth_dev, vf);