drivers/net/ena/ena_ethdev.c

   1 /*-
   2 * BSD LICENSE
   3 *
   4 * Copyright (c) 2015-2016 Amazon.com, Inc. or its affiliates.
   5 * All rights reserved.
   6 *
   7 * Redistribution and use in source and binary forms, with or without
   8 * modification, are permitted provided that the following conditions
   9 * are met:
  10 *
  11 * * Redistributions of source code must retain the above copyright
  12 * notice, this list of conditions and the following disclaimer.
  13 * * Redistributions in binary form must reproduce the above copyright
  14 * notice, this list of conditions and the following disclaimer in
  15 * the documentation and/or other materials provided with the
  16 * distribution.
  17 * * Neither the name of copyright holder nor the names of its
  18 * contributors may be used to endorse or promote products derived
  19 * from this software without specific prior written permission.
  20 *
  21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32 */
  33
  34 #include <rte_ether.h>
  35 #include <rte_ethdev_driver.h>
  36 #include <rte_ethdev_pci.h>
  37 #include <rte_tcp.h>
  38 #include <rte_atomic.h>
  39 #include <rte_dev.h>
  40 #include <rte_errno.h>
  41 #include <rte_version.h>
  42 #include <rte_eal_memconfig.h>
  43 #include <rte_net.h>
  44
  45 #include "ena_ethdev.h"
  46 #include "ena_logs.h"
  47 #include "ena_platform.h"
  48 #include "ena_com.h"
  49 #include "ena_eth_com.h"
  50
  51 #include <ena_common_defs.h>
  52 #include <ena_regs_defs.h>
  53 #include <ena_admin_defs.h>
  54 #include <ena_eth_io_defs.h>
  55
  56 #define DRV_MODULE_VER_MAJOR    1
  57 #define DRV_MODULE_VER_MINOR    1
  58 #define DRV_MODULE_VER_SUBMINOR 1
  59
  60 #define ENA_IO_TXQ_IDX(q)       (2 * (q))
  61 #define ENA_IO_RXQ_IDX(q)       (2 * (q) + 1)
  62 /*reverse version of ENA_IO_RXQ_IDX*/
  63 #define ENA_IO_RXQ_IDX_REV(q)   ((q - 1) / 2)
  64
  65 /* While processing submitted and completed descriptors (rx and tx path
  66  * respectively) in a loop it is desired to:
  67  *  - perform batch submissions while populating sumbissmion queue
  68  *  - avoid blocking transmission of other packets during cleanup phase
  69  * Hence the utilization ratio of 1/8 of a queue size.
  70  */
  71 #define ENA_RING_DESCS_RATIO(ring_size) (ring_size / 8)
  72
  73 #define __MERGE_64B_H_L(h, l) (((uint64_t)h << 32) | l)
  74 #define TEST_BIT(val, bit_shift) (val & (1UL << bit_shift))
  75
  76 #define GET_L4_HDR_LEN(mbuf)                                    \
  77         ((rte_pktmbuf_mtod_offset(mbuf, struct tcp_hdr *,       \
  78                 mbuf->l3_len + mbuf->l2_len)->data_off) >> 4)
  79
  80 #define ENA_RX_RSS_TABLE_LOG_SIZE  7
  81 #define ENA_RX_RSS_TABLE_SIZE   (1 << ENA_RX_RSS_TABLE_LOG_SIZE)
  82 #define ENA_HASH_KEY_SIZE       40
  83 #define ENA_ETH_SS_STATS        0xFF
  84 #define ETH_GSTRING_LEN 32
  85
  86 #define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
  87
  88 #define ENA_MAX_RING_DESC       ENA_DEFAULT_RING_SIZE
  89 #define ENA_MIN_RING_DESC       128
  90
  91 enum ethtool_stringset {
  92         ETH_SS_TEST             = 0,
  93         ETH_SS_STATS,
  94 };
  95
  96 struct ena_stats {
  97         char name[ETH_GSTRING_LEN];
  98         int stat_offset;
  99 };
 100
 101 #define ENA_STAT_ENA_COM_ENTRY(stat) { \
 102         .name = #stat, \
 103         .stat_offset = offsetof(struct ena_com_stats_admin, stat) \
 104 }
 105
 106 #define ENA_STAT_ENTRY(stat, stat_type) { \
 107         .name = #stat, \
 108         .stat_offset = offsetof(struct ena_stats_##stat_type, stat) \
 109 }
 110
 111 #define ENA_STAT_RX_ENTRY(stat) \
 112         ENA_STAT_ENTRY(stat, rx)
 113
 114 #define ENA_STAT_TX_ENTRY(stat) \
 115         ENA_STAT_ENTRY(stat, tx)
 116
 117 #define ENA_STAT_GLOBAL_ENTRY(stat) \
 118         ENA_STAT_ENTRY(stat, dev)
 119
 120 /*
 121  * Each rte_memzone should have unique name.
 122  * To satisfy it, count number of allocation and add it to name.
 123  */
 124 uint32_t ena_alloc_cnt;
 125
 126 static const struct ena_stats ena_stats_global_strings[] = {
 127         ENA_STAT_GLOBAL_ENTRY(tx_timeout),
 128         ENA_STAT_GLOBAL_ENTRY(io_suspend),
 129         ENA_STAT_GLOBAL_ENTRY(io_resume),
 130         ENA_STAT_GLOBAL_ENTRY(wd_expired),
 131         ENA_STAT_GLOBAL_ENTRY(interface_up),
 132         ENA_STAT_GLOBAL_ENTRY(interface_down),
 133         ENA_STAT_GLOBAL_ENTRY(admin_q_pause),
 134 };
 135
 136 static const struct ena_stats ena_stats_tx_strings[] = {
 137         ENA_STAT_TX_ENTRY(cnt),
 138         ENA_STAT_TX_ENTRY(bytes),
 139         ENA_STAT_TX_ENTRY(queue_stop),
 140         ENA_STAT_TX_ENTRY(queue_wakeup),
 141         ENA_STAT_TX_ENTRY(dma_mapping_err),
 142         ENA_STAT_TX_ENTRY(linearize),
 143         ENA_STAT_TX_ENTRY(linearize_failed),
 144         ENA_STAT_TX_ENTRY(tx_poll),
 145         ENA_STAT_TX_ENTRY(doorbells),
 146         ENA_STAT_TX_ENTRY(prepare_ctx_err),
 147         ENA_STAT_TX_ENTRY(missing_tx_comp),
 148         ENA_STAT_TX_ENTRY(bad_req_id),
 149 };
 150
 151 static const struct ena_stats ena_stats_rx_strings[] = {
 152         ENA_STAT_RX_ENTRY(cnt),
 153         ENA_STAT_RX_ENTRY(bytes),
 154         ENA_STAT_RX_ENTRY(refil_partial),
 155         ENA_STAT_RX_ENTRY(bad_csum),
 156         ENA_STAT_RX_ENTRY(page_alloc_fail),
 157         ENA_STAT_RX_ENTRY(skb_alloc_fail),
 158         ENA_STAT_RX_ENTRY(dma_mapping_err),
 159         ENA_STAT_RX_ENTRY(bad_desc_num),
 160         ENA_STAT_RX_ENTRY(small_copy_len_pkt),
 161 };
 162
 163 static const struct ena_stats ena_stats_ena_com_strings[] = {
 164         ENA_STAT_ENA_COM_ENTRY(aborted_cmd),
 165         ENA_STAT_ENA_COM_ENTRY(submitted_cmd),
 166         ENA_STAT_ENA_COM_ENTRY(completed_cmd),
 167         ENA_STAT_ENA_COM_ENTRY(out_of_space),
 168         ENA_STAT_ENA_COM_ENTRY(no_completion),
 169 };
 170
 171 #define ENA_STATS_ARRAY_GLOBAL  ARRAY_SIZE(ena_stats_global_strings)
 172 #define ENA_STATS_ARRAY_TX      ARRAY_SIZE(ena_stats_tx_strings)
 173 #define ENA_STATS_ARRAY_RX      ARRAY_SIZE(ena_stats_rx_strings)
 174 #define ENA_STATS_ARRAY_ENA_COM ARRAY_SIZE(ena_stats_ena_com_strings)
 175
 176 #define QUEUE_OFFLOADS (DEV_TX_OFFLOAD_TCP_CKSUM |\
 177                         DEV_TX_OFFLOAD_UDP_CKSUM |\
 178                         DEV_TX_OFFLOAD_IPV4_CKSUM |\
 179                         DEV_TX_OFFLOAD_TCP_TSO)
 180 #define MBUF_OFFLOADS (PKT_TX_L4_MASK |\
 181                        PKT_TX_IP_CKSUM |\
 182                        PKT_TX_TCP_SEG)
 183
 184 /** Vendor ID used by Amazon devices */
 185 #define PCI_VENDOR_ID_AMAZON 0x1D0F
 186 /** Amazon devices */
 187 #define PCI_DEVICE_ID_ENA_VF    0xEC20
 188 #define PCI_DEVICE_ID_ENA_LLQ_VF        0xEC21
 189
 190 #define ENA_TX_OFFLOAD_MASK     (\
 191         PKT_TX_L4_MASK |         \
 192         PKT_TX_IP_CKSUM |        \
 193         PKT_TX_TCP_SEG)
 194
 195 #define ENA_TX_OFFLOAD_NOTSUP_MASK      \
 196         (PKT_TX_OFFLOAD_MASK ^ ENA_TX_OFFLOAD_MASK)
 197
 198 int ena_logtype_init;
 199 int ena_logtype_driver;
 200
 201 static const struct rte_pci_id pci_id_ena_map[] = {
 202         { RTE_PCI_DEVICE(PCI_VENDOR_ID_AMAZON, PCI_DEVICE_ID_ENA_VF) },
 203         { RTE_PCI_DEVICE(PCI_VENDOR_ID_AMAZON, PCI_DEVICE_ID_ENA_LLQ_VF) },
 204         { .device_id = 0 },
 205 };
 206
 207 static struct ena_aenq_handlers aenq_handlers;
 208
 209 static int ena_device_init(struct ena_com_dev *ena_dev,
 210                            struct ena_com_dev_get_features_ctx *get_feat_ctx,
 211                            bool *wd_state);
 212 static int ena_dev_configure(struct rte_eth_dev *dev);
 213 static uint16_t eth_ena_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
 214                                   uint16_t nb_pkts);
 215 static uint16_t eth_ena_prep_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
 216                 uint16_t nb_pkts);
 217 static int ena_tx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,
 218                               uint16_t nb_desc, unsigned int socket_id,
 219                               const struct rte_eth_txconf *tx_conf);
 220 static int ena_rx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,
 221                               uint16_t nb_desc, unsigned int socket_id,
 222                               const struct rte_eth_rxconf *rx_conf,
 223                               struct rte_mempool *mp);
 224 static uint16_t eth_ena_recv_pkts(void *rx_queue,
 225                                   struct rte_mbuf **rx_pkts, uint16_t nb_pkts);
 226 static int ena_populate_rx_queue(struct ena_ring *rxq, unsigned int count);
 227 static void ena_init_rings(struct ena_adapter *adapter);
 228 static int ena_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
 229 static int ena_start(struct rte_eth_dev *dev);
 230 static void ena_stop(struct rte_eth_dev *dev);
 231 static void ena_close(struct rte_eth_dev *dev);
 232 static int ena_dev_reset(struct rte_eth_dev *dev);
 233 static int ena_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats);
 234 static void ena_rx_queue_release_all(struct rte_eth_dev *dev);
 235 static void ena_tx_queue_release_all(struct rte_eth_dev *dev);
 236 static void ena_rx_queue_release(void *queue);
 237 static void ena_tx_queue_release(void *queue);
 238 static void ena_rx_queue_release_bufs(struct ena_ring *ring);
 239 static void ena_tx_queue_release_bufs(struct ena_ring *ring);
 240 static int ena_link_update(struct rte_eth_dev *dev,
 241                            int wait_to_complete);
 242 static int ena_create_io_queue(struct ena_ring *ring);
 243 static void ena_free_io_queues_all(struct ena_adapter *adapter);
 244 static int ena_queue_restart(struct ena_ring *ring);
 245 static int ena_queue_restart_all(struct rte_eth_dev *dev,
 246                                  enum ena_ring_type ring_type);
 247 static void ena_stats_restart(struct rte_eth_dev *dev);
 248 static void ena_infos_get(struct rte_eth_dev *dev,
 249                           struct rte_eth_dev_info *dev_info);
 250 static int ena_rss_reta_update(struct rte_eth_dev *dev,
 251                                struct rte_eth_rss_reta_entry64 *reta_conf,
 252                                uint16_t reta_size);
 253 static int ena_rss_reta_query(struct rte_eth_dev *dev,
 254                               struct rte_eth_rss_reta_entry64 *reta_conf,
 255                               uint16_t reta_size);
 256 static int ena_get_sset_count(struct rte_eth_dev *dev, int sset);
 257 static void ena_interrupt_handler_rte(void *cb_arg);
 258 static void ena_timer_wd_callback(struct rte_timer *timer, void *arg);
 259
 260 static const struct eth_dev_ops ena_dev_ops = {
 261         .dev_configure        = ena_dev_configure,
 262         .dev_infos_get        = ena_infos_get,
 263         .rx_queue_setup       = ena_rx_queue_setup,
 264         .tx_queue_setup       = ena_tx_queue_setup,
 265         .dev_start            = ena_start,
 266         .dev_stop             = ena_stop,
 267         .link_update          = ena_link_update,
 268         .stats_get            = ena_stats_get,
 269         .mtu_set              = ena_mtu_set,
 270         .rx_queue_release     = ena_rx_queue_release,
 271         .tx_queue_release     = ena_tx_queue_release,
 272         .dev_close            = ena_close,
 273         .dev_reset            = ena_dev_reset,
 274         .reta_update          = ena_rss_reta_update,
 275         .reta_query           = ena_rss_reta_query,
 276 };
 277
 278 #define NUMA_NO_NODE    SOCKET_ID_ANY
 279
 280 static inline int ena_cpu_to_node(int cpu)
 281 {
 282         struct rte_config *config = rte_eal_get_configuration();
 283         struct rte_fbarray *arr = &config->mem_config->memzones;
 284         const struct rte_memzone *mz;
 285
 286         if (unlikely(cpu >= RTE_MAX_MEMZONE))
 287                 return NUMA_NO_NODE;
 288
 289         mz = rte_fbarray_get(arr, cpu);
 290
 291         return mz->socket_id;
 292 }
 293
 294 static inline void ena_rx_mbuf_prepare(struct rte_mbuf *mbuf,
 295                                        struct ena_com_rx_ctx *ena_rx_ctx)
 296 {
 297         uint64_t ol_flags = 0;
 298         uint32_t packet_type = 0;
 299
 300         if (ena_rx_ctx->l4_proto == ENA_ETH_IO_L4_PROTO_TCP)
 301                 packet_type |= RTE_PTYPE_L4_TCP;
 302         else if (ena_rx_ctx->l4_proto == ENA_ETH_IO_L4_PROTO_UDP)
 303                 packet_type |= RTE_PTYPE_L4_UDP;
 304
 305         if (ena_rx_ctx->l3_proto == ENA_ETH_IO_L3_PROTO_IPV4)
 306                 packet_type |= RTE_PTYPE_L3_IPV4;
 307         else if (ena_rx_ctx->l3_proto == ENA_ETH_IO_L3_PROTO_IPV6)
 308                 packet_type |= RTE_PTYPE_L3_IPV6;
 309
 310         if (unlikely(ena_rx_ctx->l4_csum_err))
 311                 ol_flags |= PKT_RX_L4_CKSUM_BAD;
 312         if (unlikely(ena_rx_ctx->l3_csum_err))
 313                 ol_flags |= PKT_RX_IP_CKSUM_BAD;
 314
 315         mbuf->ol_flags = ol_flags;
 316         mbuf->packet_type = packet_type;
 317 }
 318
 319 static inline void ena_tx_mbuf_prepare(struct rte_mbuf *mbuf,
 320                                        struct ena_com_tx_ctx *ena_tx_ctx,
 321                                        uint64_t queue_offloads)
 322 {
 323         struct ena_com_tx_meta *ena_meta = &ena_tx_ctx->ena_meta;
 324
 325         if ((mbuf->ol_flags & MBUF_OFFLOADS) &&
 326             (queue_offloads & QUEUE_OFFLOADS)) {
 327                 /* check if TSO is required */
 328                 if ((mbuf->ol_flags & PKT_TX_TCP_SEG) &&
 329                     (queue_offloads & DEV_TX_OFFLOAD_TCP_TSO)) {
 330                         ena_tx_ctx->tso_enable = true;
 331
 332                         ena_meta->l4_hdr_len = GET_L4_HDR_LEN(mbuf);
 333                 }
 334
 335                 /* check if L3 checksum is needed */
 336                 if ((mbuf->ol_flags & PKT_TX_IP_CKSUM) &&
 337                     (queue_offloads & DEV_TX_OFFLOAD_IPV4_CKSUM))
 338                         ena_tx_ctx->l3_csum_enable = true;
 339
 340                 if (mbuf->ol_flags & PKT_TX_IPV6) {
 341                         ena_tx_ctx->l3_proto = ENA_ETH_IO_L3_PROTO_IPV6;
 342                 } else {
 343                         ena_tx_ctx->l3_proto = ENA_ETH_IO_L3_PROTO_IPV4;
 344
 345                         /* set don't fragment (DF) flag */
 346                         if (mbuf->packet_type &
 347                                 (RTE_PTYPE_L4_NONFRAG
 348                                  | RTE_PTYPE_INNER_L4_NONFRAG))
 349                                 ena_tx_ctx->df = true;
 350                 }
 351
 352                 /* check if L4 checksum is needed */
 353                 if ((mbuf->ol_flags & PKT_TX_TCP_CKSUM) &&
 354                     (queue_offloads & DEV_TX_OFFLOAD_TCP_CKSUM)) {
 355                         ena_tx_ctx->l4_proto = ENA_ETH_IO_L4_PROTO_TCP;
 356                         ena_tx_ctx->l4_csum_enable = true;
 357                 } else if ((mbuf->ol_flags & PKT_TX_UDP_CKSUM) &&
 358                            (queue_offloads & DEV_TX_OFFLOAD_UDP_CKSUM)) {
 359                         ena_tx_ctx->l4_proto = ENA_ETH_IO_L4_PROTO_UDP;
 360                         ena_tx_ctx->l4_csum_enable = true;
 361                 } else {
 362                         ena_tx_ctx->l4_proto = ENA_ETH_IO_L4_PROTO_UNKNOWN;
 363                         ena_tx_ctx->l4_csum_enable = false;
 364                 }
 365
 366                 ena_meta->mss = mbuf->tso_segsz;
 367                 ena_meta->l3_hdr_len = mbuf->l3_len;
 368                 ena_meta->l3_hdr_offset = mbuf->l2_len;
 369
 370                 ena_tx_ctx->meta_valid = true;
 371         } else {
 372                 ena_tx_ctx->meta_valid = false;
 373         }
 374 }
 375
 376 static inline int validate_rx_req_id(struct ena_ring *rx_ring, uint16_t req_id)
 377 {
 378         if (likely(req_id < rx_ring->ring_size))
 379                 return 0;
 380
 381         RTE_LOG(ERR, PMD, "Invalid rx req_id: %hu\n", req_id);
 382
 383         rx_ring->adapter->reset_reason = ENA_REGS_RESET_INV_RX_REQ_ID;
 384         rx_ring->adapter->trigger_reset = true;
 385
 386         return -EFAULT;
 387 }
 388
 389 static int validate_tx_req_id(struct ena_ring *tx_ring, u16 req_id)
 390 {
 391         struct ena_tx_buffer *tx_info = NULL;
 392
 393         if (likely(req_id < tx_ring->ring_size)) {
 394                 tx_info = &tx_ring->tx_buffer_info[req_id];
 395                 if (likely(tx_info->mbuf))
 396                         return 0;
 397         }
 398
 399         if (tx_info)
 400                 RTE_LOG(ERR, PMD, "tx_info doesn't have valid mbuf\n");
 401         else
 402                 RTE_LOG(ERR, PMD, "Invalid req_id: %hu\n", req_id);
 403
 404         /* Trigger device reset */
 405         tx_ring->adapter->reset_reason = ENA_REGS_RESET_INV_TX_REQ_ID;
 406         tx_ring->adapter->trigger_reset = true;
 407         return -EFAULT;
 408 }
 409
 410 static void ena_config_host_info(struct ena_com_dev *ena_dev)
 411 {
 412         struct ena_admin_host_info *host_info;
 413         int rc;
 414
 415         /* Allocate only the host info */
 416         rc = ena_com_allocate_host_info(ena_dev);
 417         if (rc) {
 418                 RTE_LOG(ERR, PMD, "Cannot allocate host info\n");
 419                 return;
 420         }
 421
 422         host_info = ena_dev->host_attr.host_info;
 423
 424         host_info->os_type = ENA_ADMIN_OS_DPDK;
 425         host_info->kernel_ver = RTE_VERSION;
 426         snprintf((char *)host_info->kernel_ver_str,
 427                  sizeof(host_info->kernel_ver_str),
 428                  "%s", rte_version());
 429         host_info->os_dist = RTE_VERSION;
 430         snprintf((char *)host_info->os_dist_str,
 431                  sizeof(host_info->os_dist_str),
 432                  "%s", rte_version());
 433         host_info->driver_version =
 434                 (DRV_MODULE_VER_MAJOR) |
 435                 (DRV_MODULE_VER_MINOR << ENA_ADMIN_HOST_INFO_MINOR_SHIFT) |
 436                 (DRV_MODULE_VER_SUBMINOR <<
 437                         ENA_ADMIN_HOST_INFO_SUB_MINOR_SHIFT);
 438
 439         rc = ena_com_set_host_attributes(ena_dev);
 440         if (rc) {
 441                 if (rc == -ENA_COM_UNSUPPORTED)
 442                         RTE_LOG(WARNING, PMD, "Cannot set host attributes\n");
 443                 else
 444                         RTE_LOG(ERR, PMD, "Cannot set host attributes\n");
 445
 446                 goto err;
 447         }
 448
 449         return;
 450
 451 err:
 452         ena_com_delete_host_info(ena_dev);
 453 }
 454
 455 static int
 456 ena_get_sset_count(struct rte_eth_dev *dev, int sset)
 457 {
 458         if (sset != ETH_SS_STATS)
 459                 return -EOPNOTSUPP;
 460
 461          /* Workaround for clang:
 462          * touch internal structures to prevent
 463          * compiler error
 464          */
 465         ENA_TOUCH(ena_stats_global_strings);
 466         ENA_TOUCH(ena_stats_tx_strings);
 467         ENA_TOUCH(ena_stats_rx_strings);
 468         ENA_TOUCH(ena_stats_ena_com_strings);
 469
 470         return  dev->data->nb_tx_queues *
 471                 (ENA_STATS_ARRAY_TX + ENA_STATS_ARRAY_RX) +
 472                 ENA_STATS_ARRAY_GLOBAL + ENA_STATS_ARRAY_ENA_COM;
 473 }
 474
 475 static void ena_config_debug_area(struct ena_adapter *adapter)
 476 {
 477         u32 debug_area_size;
 478         int rc, ss_count;
 479
 480         ss_count = ena_get_sset_count(adapter->rte_dev, ETH_SS_STATS);
 481         if (ss_count <= 0) {
 482                 RTE_LOG(ERR, PMD, "SS count is negative\n");
 483                 return;
 484         }
 485
 486         /* allocate 32 bytes for each string and 64bit for the value */
 487         debug_area_size = ss_count * ETH_GSTRING_LEN + sizeof(u64) * ss_count;
 488
 489         rc = ena_com_allocate_debug_area(&adapter->ena_dev, debug_area_size);
 490         if (rc) {
 491                 RTE_LOG(ERR, PMD, "Cannot allocate debug area\n");
 492                 return;
 493         }
 494
 495         rc = ena_com_set_host_attributes(&adapter->ena_dev);
 496         if (rc) {
 497                 if (rc == -ENA_COM_UNSUPPORTED)
 498                         RTE_LOG(WARNING, PMD, "Cannot set host attributes\n");
 499                 else
 500                         RTE_LOG(ERR, PMD, "Cannot set host attributes\n");
 501
 502                 goto err;
 503         }
 504
 505         return;
 506 err:
 507         ena_com_delete_debug_area(&adapter->ena_dev);
 508 }
 509
 510 static void ena_close(struct rte_eth_dev *dev)
 511 {
 512         struct ena_adapter *adapter =
 513                 (struct ena_adapter *)(dev->data->dev_private);
 514
 515         if (adapter->state == ENA_ADAPTER_STATE_RUNNING)
 516                 ena_stop(dev);
 517         adapter->state = ENA_ADAPTER_STATE_CLOSED;
 518
 519         ena_rx_queue_release_all(dev);
 520         ena_tx_queue_release_all(dev);
 521 }
 522
 523 static int
 524 ena_dev_reset(struct rte_eth_dev *dev)
 525 {
 526         struct rte_mempool *mb_pool_rx[ENA_MAX_NUM_QUEUES];
 527         struct rte_eth_dev *eth_dev;
 528         struct rte_pci_device *pci_dev;
 529         struct rte_intr_handle *intr_handle;
 530         struct ena_com_dev *ena_dev;
 531         struct ena_com_dev_get_features_ctx get_feat_ctx;
 532         struct ena_adapter *adapter;
 533         int nb_queues;
 534         int rc, i;
 535         bool wd_state;
 536
 537         adapter = (struct ena_adapter *)(dev->data->dev_private);
 538         ena_dev = &adapter->ena_dev;
 539         eth_dev = adapter->rte_dev;
 540         pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
 541         intr_handle = &pci_dev->intr_handle;
 542         nb_queues = eth_dev->data->nb_rx_queues;
 543
 544         ena_com_set_admin_running_state(ena_dev, false);
 545
 546         rc = ena_com_dev_reset(ena_dev, adapter->reset_reason);
 547         if (rc)
 548                 RTE_LOG(ERR, PMD, "Device reset failed\n");
 549
 550         for (i = 0; i < nb_queues; i++)
 551                 mb_pool_rx[i] = adapter->rx_ring[i].mb_pool;
 552
 553         ena_rx_queue_release_all(eth_dev);
 554         ena_tx_queue_release_all(eth_dev);
 555
 556         rte_intr_disable(intr_handle);
 557
 558         ena_com_abort_admin_commands(ena_dev);
 559         ena_com_wait_for_abort_completion(ena_dev);
 560         ena_com_admin_destroy(ena_dev);
 561         ena_com_mmio_reg_read_request_destroy(ena_dev);
 562
 563         rc = ena_device_init(ena_dev, &get_feat_ctx, &wd_state);
 564         if (rc) {
 565                 PMD_INIT_LOG(CRIT, "Cannot initialize device\n");
 566                 return rc;
 567         }
 568         adapter->wd_state = wd_state;
 569
 570         rte_intr_enable(intr_handle);
 571         ena_com_set_admin_polling_mode(ena_dev, false);
 572         ena_com_admin_aenq_enable(ena_dev);
 573
 574         for (i = 0; i < nb_queues; ++i)
 575                 ena_rx_queue_setup(eth_dev, i, adapter->rx_ring_size, 0, NULL,
 576                         mb_pool_rx[i]);
 577
 578         for (i = 0; i < nb_queues; ++i)
 579                 ena_tx_queue_setup(eth_dev, i, adapter->tx_ring_size, 0, NULL);
 580
 581         adapter->trigger_reset = false;
 582
 583         return 0;
 584 }
 585
 586 static int ena_rss_reta_update(struct rte_eth_dev *dev,
 587                                struct rte_eth_rss_reta_entry64 *reta_conf,
 588                                uint16_t reta_size)
 589 {
 590         struct ena_adapter *adapter =
 591                 (struct ena_adapter *)(dev->data->dev_private);
 592         struct ena_com_dev *ena_dev = &adapter->ena_dev;
 593         int rc, i;
 594         u16 entry_value;
 595         int conf_idx;
 596         int idx;
 597
 598         if ((reta_size == 0) || (reta_conf == NULL))
 599                 return -EINVAL;
 600
 601         if (reta_size > ENA_RX_RSS_TABLE_SIZE) {
 602                 RTE_LOG(WARNING, PMD,
 603                         "indirection table %d is bigger than supported (%d)\n",
 604                         reta_size, ENA_RX_RSS_TABLE_SIZE);
 605                 return -EINVAL;
 606         }
 607
 608         for (i = 0 ; i < reta_size ; i++) {
 609                 /* each reta_conf is for 64 entries.
 610                  * to support 128 we use 2 conf of 64
 611                  */
 612                 conf_idx = i / RTE_RETA_GROUP_SIZE;
 613                 idx = i % RTE_RETA_GROUP_SIZE;
 614                 if (TEST_BIT(reta_conf[conf_idx].mask, idx)) {
 615                         entry_value =
 616                                 ENA_IO_RXQ_IDX(reta_conf[conf_idx].reta[idx]);
 617
 618                         rc = ena_com_indirect_table_fill_entry(ena_dev,
 619                                                                i,
 620                                                                entry_value);
 621                         if (unlikely(rc && rc != ENA_COM_UNSUPPORTED)) {
 622                                 RTE_LOG(ERR, PMD,
 623                                         "Cannot fill indirect table\n");
 624                                 return rc;
 625                         }
 626                 }
 627         }
 628
 629         rc = ena_com_indirect_table_set(ena_dev);
 630         if (unlikely(rc && rc != ENA_COM_UNSUPPORTED)) {
 631                 RTE_LOG(ERR, PMD, "Cannot flush the indirect table\n");
 632                 return rc;
 633         }
 634
 635         RTE_LOG(DEBUG, PMD, "%s(): RSS configured %d entries  for port %d\n",
 636                 __func__, reta_size, adapter->rte_dev->data->port_id);
 637
 638         return 0;
 639 }
 640
 641 /* Query redirection table. */
 642 static int ena_rss_reta_query(struct rte_eth_dev *dev,
 643                               struct rte_eth_rss_reta_entry64 *reta_conf,
 644                               uint16_t reta_size)
 645 {
 646         struct ena_adapter *adapter =
 647                 (struct ena_adapter *)(dev->data->dev_private);
 648         struct ena_com_dev *ena_dev = &adapter->ena_dev;
 649         int rc;
 650         int i;
 651         u32 indirect_table[ENA_RX_RSS_TABLE_SIZE] = {0};
 652         int reta_conf_idx;
 653         int reta_idx;
 654
 655         if (reta_size == 0 || reta_conf == NULL ||
 656             (reta_size > RTE_RETA_GROUP_SIZE && ((reta_conf + 1) == NULL)))
 657                 return -EINVAL;
 658
 659         rc = ena_com_indirect_table_get(ena_dev, indirect_table);
 660         if (unlikely(rc && rc != ENA_COM_UNSUPPORTED)) {
 661                 RTE_LOG(ERR, PMD, "cannot get indirect table\n");
 662                 return -ENOTSUP;
 663         }
 664
 665         for (i = 0 ; i < reta_size ; i++) {
 666                 reta_conf_idx = i / RTE_RETA_GROUP_SIZE;
 667                 reta_idx = i % RTE_RETA_GROUP_SIZE;
 668                 if (TEST_BIT(reta_conf[reta_conf_idx].mask, reta_idx))
 669                         reta_conf[reta_conf_idx].reta[reta_idx] =
 670                                 ENA_IO_RXQ_IDX_REV(indirect_table[i]);
 671         }
 672
 673         return 0;
 674 }
 675
 676 static int ena_rss_init_default(struct ena_adapter *adapter)
 677 {
 678         struct ena_com_dev *ena_dev = &adapter->ena_dev;
 679         uint16_t nb_rx_queues = adapter->rte_dev->data->nb_rx_queues;
 680         int rc, i;
 681         u32 val;
 682
 683         rc = ena_com_rss_init(ena_dev, ENA_RX_RSS_TABLE_LOG_SIZE);
 684         if (unlikely(rc)) {
 685                 RTE_LOG(ERR, PMD, "Cannot init indirect table\n");
 686                 goto err_rss_init;
 687         }
 688
 689         for (i = 0; i < ENA_RX_RSS_TABLE_SIZE; i++) {
 690                 val = i % nb_rx_queues;
 691                 rc = ena_com_indirect_table_fill_entry(ena_dev, i,
 692                                                        ENA_IO_RXQ_IDX(val));
 693                 if (unlikely(rc && (rc != ENA_COM_UNSUPPORTED))) {
 694                         RTE_LOG(ERR, PMD, "Cannot fill indirect table\n");
 695                         goto err_fill_indir;
 696                 }
 697         }
 698
 699         rc = ena_com_fill_hash_function(ena_dev, ENA_ADMIN_CRC32, NULL,
 700                                         ENA_HASH_KEY_SIZE, 0xFFFFFFFF);
 701         if (unlikely(rc && (rc != ENA_COM_UNSUPPORTED))) {
 702                 RTE_LOG(INFO, PMD, "Cannot fill hash function\n");
 703                 goto err_fill_indir;
 704         }
 705
 706         rc = ena_com_set_default_hash_ctrl(ena_dev);
 707         if (unlikely(rc && (rc != ENA_COM_UNSUPPORTED))) {
 708                 RTE_LOG(INFO, PMD, "Cannot fill hash control\n");
 709                 goto err_fill_indir;
 710         }
 711
 712         rc = ena_com_indirect_table_set(ena_dev);
 713         if (unlikely(rc && (rc != ENA_COM_UNSUPPORTED))) {
 714                 RTE_LOG(ERR, PMD, "Cannot flush the indirect table\n");
 715                 goto err_fill_indir;
 716         }
 717         RTE_LOG(DEBUG, PMD, "RSS configured for port %d\n",
 718                 adapter->rte_dev->data->port_id);
 719
 720         return 0;
 721
 722 err_fill_indir:
 723         ena_com_rss_destroy(ena_dev);
 724 err_rss_init:
 725
 726         return rc;
 727 }
 728
 729 static void ena_rx_queue_release_all(struct rte_eth_dev *dev)
 730 {
 731         struct ena_ring **queues = (struct ena_ring **)dev->data->rx_queues;
 732         int nb_queues = dev->data->nb_rx_queues;
 733         int i;
 734
 735         for (i = 0; i < nb_queues; i++)
 736                 ena_rx_queue_release(queues[i]);
 737 }
 738
 739 static void ena_tx_queue_release_all(struct rte_eth_dev *dev)
 740 {
 741         struct ena_ring **queues = (struct ena_ring **)dev->data->tx_queues;
 742         int nb_queues = dev->data->nb_tx_queues;
 743         int i;
 744
 745         for (i = 0; i < nb_queues; i++)
 746                 ena_tx_queue_release(queues[i]);
 747 }
 748
 749 static void ena_rx_queue_release(void *queue)
 750 {
 751         struct ena_ring *ring = (struct ena_ring *)queue;
 752
 753         ena_assert_msg(ring->configured,
 754                        "API violation - releasing not configured queue");
 755         ena_assert_msg(ring->adapter->state != ENA_ADAPTER_STATE_RUNNING,
 756                        "API violation");
 757
 758         /* Free ring resources */
 759         if (ring->rx_buffer_info)
 760                 rte_free(ring->rx_buffer_info);
 761         ring->rx_buffer_info = NULL;
 762
 763         if (ring->empty_rx_reqs)
 764                 rte_free(ring->empty_rx_reqs);
 765         ring->empty_rx_reqs = NULL;
 766
 767         ring->configured = 0;
 768
 769         RTE_LOG(NOTICE, PMD, "RX Queue %d:%d released\n",
 770                 ring->port_id, ring->id);
 771 }
 772
 773 static void ena_tx_queue_release(void *queue)
 774 {
 775         struct ena_ring *ring = (struct ena_ring *)queue;
 776
 777         ena_assert_msg(ring->configured,
 778                        "API violation. Releasing not configured queue");
 779         ena_assert_msg(ring->adapter->state != ENA_ADAPTER_STATE_RUNNING,
 780                        "API violation");
 781
 782         /* Free all bufs */
 783         ena_tx_queue_release_bufs(ring);
 784
 785         /* Free ring resources */
 786         if (ring->tx_buffer_info)
 787                 rte_free(ring->tx_buffer_info);
 788
 789         if (ring->empty_tx_reqs)
 790                 rte_free(ring->empty_tx_reqs);
 791
 792         ring->empty_tx_reqs = NULL;
 793         ring->tx_buffer_info = NULL;
 794
 795         ring->configured = 0;
 796
 797         RTE_LOG(NOTICE, PMD, "TX Queue %d:%d released\n",
 798                 ring->port_id, ring->id);
 799 }
 800
 801 static void ena_rx_queue_release_bufs(struct ena_ring *ring)
 802 {
 803         unsigned int ring_mask = ring->ring_size - 1;
 804
 805         while (ring->next_to_clean != ring->next_to_use) {
 806                 struct rte_mbuf *m =
 807                         ring->rx_buffer_info[ring->next_to_clean & ring_mask];
 808
 809                 if (m)
 810                         rte_mbuf_raw_free(m);
 811
 812                 ring->next_to_clean++;
 813         }
 814 }
 815
 816 static void ena_tx_queue_release_bufs(struct ena_ring *ring)
 817 {
 818         unsigned int i;
 819
 820         for (i = 0; i < ring->ring_size; ++i) {
 821                 struct ena_tx_buffer *tx_buf = &ring->tx_buffer_info[i];
 822
 823                 if (tx_buf->mbuf)
 824                         rte_pktmbuf_free(tx_buf->mbuf);
 825
 826                 ring->next_to_clean++;
 827         }
 828 }
 829
 830 static int ena_link_update(struct rte_eth_dev *dev,
 831                            __rte_unused int wait_to_complete)
 832 {
 833         struct rte_eth_link *link = &dev->data->dev_link;
 834         struct ena_adapter *adapter;
 835
 836         adapter = (struct ena_adapter *)(dev->data->dev_private);
 837
 838         link->link_status = adapter->link_status ? ETH_LINK_UP : ETH_LINK_DOWN;
 839         link->link_speed = ETH_SPEED_NUM_NONE;
 840         link->link_duplex = ETH_LINK_FULL_DUPLEX;
 841
 842         return 0;
 843 }
 844
 845 static int ena_queue_restart_all(struct rte_eth_dev *dev,
 846                                  enum ena_ring_type ring_type)
 847 {
 848         struct ena_adapter *adapter =
 849                 (struct ena_adapter *)(dev->data->dev_private);
 850         struct ena_ring *queues = NULL;
 851         int nb_queues;
 852         int i = 0;
 853         int rc = 0;
 854
 855         if (ring_type == ENA_RING_TYPE_RX) {
 856                 queues = adapter->rx_ring;
 857                 nb_queues = dev->data->nb_rx_queues;
 858         } else {
 859                 queues = adapter->tx_ring;
 860                 nb_queues = dev->data->nb_tx_queues;
 861         }
 862         for (i = 0; i < nb_queues; i++) {
 863                 if (queues[i].configured) {
 864                         if (ring_type == ENA_RING_TYPE_RX) {
 865                                 ena_assert_msg(
 866                                         dev->data->rx_queues[i] == &queues[i],
 867                                         "Inconsistent state of rx queues\n");
 868                         } else {
 869                                 ena_assert_msg(
 870                                         dev->data->tx_queues[i] == &queues[i],
 871                                         "Inconsistent state of tx queues\n");
 872                         }
 873
 874                         rc = ena_queue_restart(&queues[i]);
 875
 876                         if (rc) {
 877                                 PMD_INIT_LOG(ERR,
 878                                              "failed to restart queue %d type(%d)",
 879                                              i, ring_type);
 880                                 return rc;
 881                         }
 882                 }
 883         }
 884
 885         return 0;
 886 }
 887
 888 static uint32_t ena_get_mtu_conf(struct ena_adapter *adapter)
 889 {
 890         uint32_t max_frame_len = adapter->max_mtu;
 891
 892         if (adapter->rte_eth_dev_data->dev_conf.rxmode.offloads &
 893             DEV_RX_OFFLOAD_JUMBO_FRAME)
 894                 max_frame_len =
 895                         adapter->rte_eth_dev_data->dev_conf.rxmode.max_rx_pkt_len;
 896
 897         return max_frame_len;
 898 }
 899
 900 static int ena_check_valid_conf(struct ena_adapter *adapter)
 901 {
 902         uint32_t max_frame_len = ena_get_mtu_conf(adapter);
 903
 904         if (max_frame_len > adapter->max_mtu || max_frame_len < ENA_MIN_MTU) {
 905                 PMD_INIT_LOG(ERR, "Unsupported MTU of %d. "
 906                                   "max mtu: %d, min mtu: %d\n",
 907                              max_frame_len, adapter->max_mtu, ENA_MIN_MTU);
 908                 return ENA_COM_UNSUPPORTED;
 909         }
 910
 911         return 0;
 912 }
 913
 914 static int
 915 ena_calc_queue_size(struct ena_com_dev *ena_dev,
 916                     u16 *max_tx_sgl_size,
 917                     struct ena_com_dev_get_features_ctx *get_feat_ctx)
 918 {
 919         uint32_t queue_size = ENA_DEFAULT_RING_SIZE;
 920
 921         queue_size = RTE_MIN(queue_size,
 922                              get_feat_ctx->max_queues.max_cq_depth);
 923         queue_size = RTE_MIN(queue_size,
 924                              get_feat_ctx->max_queues.max_sq_depth);
 925
 926         if (ena_dev->tx_mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_DEV)
 927                 queue_size = RTE_MIN(queue_size,
 928                                      get_feat_ctx->max_queues.max_llq_depth);
 929
 930         /* Round down to power of 2 */
 931         if (!rte_is_power_of_2(queue_size))
 932                 queue_size = rte_align32pow2(queue_size >> 1);
 933
 934         if (unlikely(queue_size == 0)) {
 935                 PMD_INIT_LOG(ERR, "Invalid queue size");
 936                 return -EFAULT;
 937         }
 938
 939         *max_tx_sgl_size = RTE_MIN(ENA_PKT_MAX_BUFS,
 940                 get_feat_ctx->max_queues.max_packet_tx_descs);
 941
 942         return queue_size;
 943 }
 944
 945 static void ena_stats_restart(struct rte_eth_dev *dev)
 946 {
 947         struct ena_adapter *adapter =
 948                 (struct ena_adapter *)(dev->data->dev_private);
 949
 950         rte_atomic64_init(&adapter->drv_stats->ierrors);
 951         rte_atomic64_init(&adapter->drv_stats->oerrors);
 952         rte_atomic64_init(&adapter->drv_stats->rx_nombuf);
 953 }
 954
 955 static int ena_stats_get(struct rte_eth_dev *dev,
 956                           struct rte_eth_stats *stats)
 957 {
 958         struct ena_admin_basic_stats ena_stats;
 959         struct ena_adapter *adapter =
 960                 (struct ena_adapter *)(dev->data->dev_private);
 961         struct ena_com_dev *ena_dev = &adapter->ena_dev;
 962         int rc;
 963
 964         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
 965                 return -ENOTSUP;
 966
 967         memset(&ena_stats, 0, sizeof(ena_stats));
 968         rc = ena_com_get_dev_basic_stats(ena_dev, &ena_stats);
 969         if (unlikely(rc)) {
 970                 RTE_LOG(ERR, PMD, "Could not retrieve statistics from ENA");
 971                 return rc;
 972         }
 973
 974         /* Set of basic statistics from ENA */
 975         stats->ipackets = __MERGE_64B_H_L(ena_stats.rx_pkts_high,
 976                                           ena_stats.rx_pkts_low);
 977         stats->opackets = __MERGE_64B_H_L(ena_stats.tx_pkts_high,
 978                                           ena_stats.tx_pkts_low);
 979         stats->ibytes = __MERGE_64B_H_L(ena_stats.rx_bytes_high,
 980                                         ena_stats.rx_bytes_low);
 981         stats->obytes = __MERGE_64B_H_L(ena_stats.tx_bytes_high,
 982                                         ena_stats.tx_bytes_low);
 983         stats->imissed = __MERGE_64B_H_L(ena_stats.rx_drops_high,
 984                                          ena_stats.rx_drops_low);
 985
 986         /* Driver related stats */
 987         stats->ierrors = rte_atomic64_read(&adapter->drv_stats->ierrors);
 988         stats->oerrors = rte_atomic64_read(&adapter->drv_stats->oerrors);
 989         stats->rx_nombuf = rte_atomic64_read(&adapter->drv_stats->rx_nombuf);
 990         return 0;
 991 }
 992
 993 static int ena_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
 994 {
 995         struct ena_adapter *adapter;
 996         struct ena_com_dev *ena_dev;
 997         int rc = 0;
 998
 999         ena_assert_msg(dev->data != NULL, "Uninitialized device");
1000         ena_assert_msg(dev->data->dev_private != NULL, "Uninitialized device");
1001         adapter = (struct ena_adapter *)(dev->data->dev_private);
1002
1003         ena_dev = &adapter->ena_dev;
1004         ena_assert_msg(ena_dev != NULL, "Uninitialized device");
1005
1006         if (mtu > ena_get_mtu_conf(adapter) || mtu < ENA_MIN_MTU) {
1007                 RTE_LOG(ERR, PMD,
1008                         "Invalid MTU setting. new_mtu: %d "
1009                         "max mtu: %d min mtu: %d\n",
1010                         mtu, ena_get_mtu_conf(adapter), ENA_MIN_MTU);
1011                 return -EINVAL;
1012         }
1013
1014         rc = ena_com_set_dev_mtu(ena_dev, mtu);
1015         if (rc)
1016                 RTE_LOG(ERR, PMD, "Could not set MTU: %d\n", mtu);
1017         else
1018                 RTE_LOG(NOTICE, PMD, "Set MTU: %d\n", mtu);
1019
1020         return rc;
1021 }
1022
1023 static int ena_start(struct rte_eth_dev *dev)
1024 {
1025         struct ena_adapter *adapter =
1026                 (struct ena_adapter *)(dev->data->dev_private);
1027         uint64_t ticks;
1028         int rc = 0;
1029
1030         rc = ena_check_valid_conf(adapter);
1031         if (rc)
1032                 return rc;
1033
1034         rc = ena_queue_restart_all(dev, ENA_RING_TYPE_RX);
1035         if (rc)
1036                 return rc;
1037
1038         rc = ena_queue_restart_all(dev, ENA_RING_TYPE_TX);
1039         if (rc)
1040                 return rc;
1041
1042         if (adapter->rte_dev->data->dev_conf.rxmode.mq_mode &
1043             ETH_MQ_RX_RSS_FLAG && adapter->rte_dev->data->nb_rx_queues > 0) {
1044                 rc = ena_rss_init_default(adapter);
1045                 if (rc)
1046                         return rc;
1047         }
1048
1049         ena_stats_restart(dev);
1050
1051         adapter->timestamp_wd = rte_get_timer_cycles();
1052         adapter->keep_alive_timeout = ENA_DEVICE_KALIVE_TIMEOUT;
1053
1054         ticks = rte_get_timer_hz();
1055         rte_timer_reset(&adapter->timer_wd, ticks, PERIODICAL, rte_lcore_id(),
1056                         ena_timer_wd_callback, adapter);
1057
1058         adapter->state = ENA_ADAPTER_STATE_RUNNING;
1059
1060         return 0;
1061 }
1062
1063 static void ena_stop(struct rte_eth_dev *dev)
1064 {
1065         struct ena_adapter *adapter =
1066                 (struct ena_adapter *)(dev->data->dev_private);
1067
1068         rte_timer_stop_sync(&adapter->timer_wd);
1069         ena_free_io_queues_all(adapter);
1070
1071         adapter->state = ENA_ADAPTER_STATE_STOPPED;
1072 }
1073
1074 static int ena_create_io_queue(struct ena_ring *ring)
1075 {
1076         struct ena_adapter *adapter;
1077         struct ena_com_dev *ena_dev;
1078         struct ena_com_create_io_ctx ctx =
1079                 /* policy set to _HOST just to satisfy icc compiler */
1080                 { ENA_ADMIN_PLACEMENT_POLICY_HOST,
1081                   0, 0, 0, 0, 0 };
1082         uint16_t ena_qid;
1083         int rc;
1084
1085         adapter = ring->adapter;
1086         ena_dev = &adapter->ena_dev;
1087
1088         if (ring->type == ENA_RING_TYPE_TX) {
1089                 ena_qid = ENA_IO_TXQ_IDX(ring->id);
1090                 ctx.direction = ENA_COM_IO_QUEUE_DIRECTION_TX;
1091                 ctx.mem_queue_type = ena_dev->tx_mem_queue_type;
1092                 ctx.queue_size = adapter->tx_ring_size;
1093         } else {
1094                 ena_qid = ENA_IO_RXQ_IDX(ring->id);
1095                 ctx.direction = ENA_COM_IO_QUEUE_DIRECTION_RX;
1096                 ctx.queue_size = adapter->rx_ring_size;
1097         }
1098         ctx.qid = ena_qid;
1099         ctx.msix_vector = -1; /* interrupts not used */
1100         ctx.numa_node = ena_cpu_to_node(ring->id);
1101
1102         rc = ena_com_create_io_queue(ena_dev, &ctx);
1103         if (rc) {
1104                 RTE_LOG(ERR, PMD,
1105                         "failed to create io queue #%d (qid:%d) rc: %d\n",
1106                         ring->id, ena_qid, rc);
1107                 return rc;
1108         }
1109
1110         rc = ena_com_get_io_handlers(ena_dev, ena_qid,
1111                                      &ring->ena_com_io_sq,
1112                                      &ring->ena_com_io_cq);
1113         if (rc) {
1114                 RTE_LOG(ERR, PMD,
1115                         "Failed to get io queue handlers. queue num %d rc: %d\n",
1116                         ring->id, rc);
1117                 ena_com_destroy_io_queue(ena_dev, ena_qid);
1118                 return rc;
1119         }
1120
1121         if (ring->type == ENA_RING_TYPE_TX)
1122                 ena_com_update_numa_node(ring->ena_com_io_cq, ctx.numa_node);
1123
1124         return 0;
1125 }
1126
1127 static void ena_free_io_queues_all(struct ena_adapter *adapter)
1128 {
1129         struct rte_eth_dev *eth_dev = adapter->rte_dev;
1130         struct ena_com_dev *ena_dev = &adapter->ena_dev;
1131         int i;
1132         uint16_t ena_qid;
1133         uint16_t nb_rxq = eth_dev->data->nb_rx_queues;
1134         uint16_t nb_txq = eth_dev->data->nb_tx_queues;
1135
1136         for (i = 0; i < nb_txq; ++i) {
1137                 ena_qid = ENA_IO_TXQ_IDX(i);
1138                 ena_com_destroy_io_queue(ena_dev, ena_qid);
1139         }
1140
1141         for (i = 0; i < nb_rxq; ++i) {
1142                 ena_qid = ENA_IO_RXQ_IDX(i);
1143                 ena_com_destroy_io_queue(ena_dev, ena_qid);
1144
1145                 ena_rx_queue_release_bufs(&adapter->rx_ring[i]);
1146         }
1147 }
1148
1149 static int ena_queue_restart(struct ena_ring *ring)
1150 {
1151         int rc, bufs_num;
1152
1153         ena_assert_msg(ring->configured == 1,
1154                        "Trying to restart unconfigured queue\n");
1155
1156         rc = ena_create_io_queue(ring);
1157         if (rc) {
1158                 PMD_INIT_LOG(ERR, "Failed to create IO queue!\n");
1159                 return rc;
1160         }
1161
1162         ring->next_to_clean = 0;
1163         ring->next_to_use = 0;
1164
1165         if (ring->type == ENA_RING_TYPE_TX)
1166                 return 0;
1167
1168         bufs_num = ring->ring_size - 1;
1169         rc = ena_populate_rx_queue(ring, bufs_num);
1170         if (rc != bufs_num) {
1171                 PMD_INIT_LOG(ERR, "Failed to populate rx ring !");
1172                 return ENA_COM_FAULT;
1173         }
1174
1175         return 0;
1176 }
1177
1178 static int ena_tx_queue_setup(struct rte_eth_dev *dev,
1179                               uint16_t queue_idx,
1180                               uint16_t nb_desc,
1181                               __rte_unused unsigned int socket_id,
1182                               const struct rte_eth_txconf *tx_conf)
1183 {
1184         struct ena_ring *txq = NULL;
1185         struct ena_adapter *adapter =
1186                 (struct ena_adapter *)(dev->data->dev_private);
1187         unsigned int i;
1188
1189         txq = &adapter->tx_ring[queue_idx];
1190
1191         if (txq->configured) {
1192                 RTE_LOG(CRIT, PMD,
1193                         "API violation. Queue %d is already configured\n",
1194                         queue_idx);
1195                 return ENA_COM_FAULT;
1196         }
1197
1198         if (!rte_is_power_of_2(nb_desc)) {
1199                 RTE_LOG(ERR, PMD,
1200                         "Unsupported size of TX queue: %d is not a power of 2.",
1201                         nb_desc);
1202                 return -EINVAL;
1203         }
1204
1205         if (nb_desc > adapter->tx_ring_size) {
1206                 RTE_LOG(ERR, PMD,
1207                         "Unsupported size of TX queue (max size: %d)\n",
1208                         adapter->tx_ring_size);
1209                 return -EINVAL;
1210         }
1211
1212         txq->port_id = dev->data->port_id;
1213         txq->next_to_clean = 0;
1214         txq->next_to_use = 0;
1215         txq->ring_size = nb_desc;
1216
1217         txq->tx_buffer_info = rte_zmalloc("txq->tx_buffer_info",
1218                                           sizeof(struct ena_tx_buffer) *
1219                                           txq->ring_size,
1220                                           RTE_CACHE_LINE_SIZE);
1221         if (!txq->tx_buffer_info) {
1222                 RTE_LOG(ERR, PMD, "failed to alloc mem for tx buffer info\n");
1223                 return -ENOMEM;
1224         }
1225
1226         txq->empty_tx_reqs = rte_zmalloc("txq->empty_tx_reqs",
1227                                          sizeof(u16) * txq->ring_size,
1228                                          RTE_CACHE_LINE_SIZE);
1229         if (!txq->empty_tx_reqs) {
1230                 RTE_LOG(ERR, PMD, "failed to alloc mem for tx reqs\n");
1231                 rte_free(txq->tx_buffer_info);
1232                 return -ENOMEM;
1233         }
1234
1235         for (i = 0; i < txq->ring_size; i++)
1236                 txq->empty_tx_reqs[i] = i;
1237
1238         if (tx_conf != NULL) {
1239                 txq->offloads =
1240                         tx_conf->offloads | dev->data->dev_conf.txmode.offloads;
1241         }
1242
1243         /* Store pointer to this queue in upper layer */
1244         txq->configured = 1;
1245         dev->data->tx_queues[queue_idx] = txq;
1246
1247         return 0;
1248 }
1249
1250 static int ena_rx_queue_setup(struct rte_eth_dev *dev,
1251                               uint16_t queue_idx,
1252                               uint16_t nb_desc,
1253                               __rte_unused unsigned int socket_id,
1254                               __rte_unused const struct rte_eth_rxconf *rx_conf,
1255                               struct rte_mempool *mp)
1256 {
1257         struct ena_adapter *adapter =
1258                 (struct ena_adapter *)(dev->data->dev_private);
1259         struct ena_ring *rxq = NULL;
1260         int i;
1261
1262         rxq = &adapter->rx_ring[queue_idx];
1263         if (rxq->configured) {
1264                 RTE_LOG(CRIT, PMD,
1265                         "API violation. Queue %d is already configured\n",
1266                         queue_idx);
1267                 return ENA_COM_FAULT;
1268         }
1269
1270         if (!rte_is_power_of_2(nb_desc)) {
1271                 RTE_LOG(ERR, PMD,
1272                         "Unsupported size of RX queue: %d is not a power of 2.",
1273                         nb_desc);
1274                 return -EINVAL;
1275         }
1276
1277         if (nb_desc > adapter->rx_ring_size) {
1278                 RTE_LOG(ERR, PMD,
1279                         "Unsupported size of RX queue (max size: %d)\n",
1280                         adapter->rx_ring_size);
1281                 return -EINVAL;
1282         }
1283
1284         rxq->port_id = dev->data->port_id;
1285         rxq->next_to_clean = 0;
1286         rxq->next_to_use = 0;
1287         rxq->ring_size = nb_desc;
1288         rxq->mb_pool = mp;
1289
1290         rxq->rx_buffer_info = rte_zmalloc("rxq->buffer_info",
1291                                           sizeof(struct rte_mbuf *) * nb_desc,
1292                                           RTE_CACHE_LINE_SIZE);
1293         if (!rxq->rx_buffer_info) {
1294                 RTE_LOG(ERR, PMD, "failed to alloc mem for rx buffer info\n");
1295                 return -ENOMEM;
1296         }
1297
1298         rxq->empty_rx_reqs = rte_zmalloc("rxq->empty_rx_reqs",
1299                                          sizeof(uint16_t) * nb_desc,
1300                                          RTE_CACHE_LINE_SIZE);
1301         if (!rxq->empty_rx_reqs) {
1302                 RTE_LOG(ERR, PMD, "failed to alloc mem for empty rx reqs\n");
1303                 rte_free(rxq->rx_buffer_info);
1304                 rxq->rx_buffer_info = NULL;
1305                 return -ENOMEM;
1306         }
1307
1308         for (i = 0; i < nb_desc; i++)
1309                 rxq->empty_tx_reqs[i] = i;
1310
1311         /* Store pointer to this queue in upper layer */
1312         rxq->configured = 1;
1313         dev->data->rx_queues[queue_idx] = rxq;
1314
1315         return 0;
1316 }
1317
1318 static int ena_populate_rx_queue(struct ena_ring *rxq, unsigned int count)
1319 {
1320         unsigned int i;
1321         int rc;
1322         uint16_t ring_size = rxq->ring_size;
1323         uint16_t ring_mask = ring_size - 1;
1324         uint16_t next_to_use = rxq->next_to_use;
1325         uint16_t in_use, req_id;
1326         struct rte_mbuf **mbufs = &rxq->rx_buffer_info[0];
1327
1328         if (unlikely(!count))
1329                 return 0;
1330
1331         in_use = rxq->next_to_use - rxq->next_to_clean;
1332         ena_assert_msg(((in_use + count) < ring_size), "bad ring state");
1333
1334         count = RTE_MIN(count,
1335                         (uint16_t)(ring_size - (next_to_use & ring_mask)));
1336
1337         /* get resources for incoming packets */
1338         rc = rte_mempool_get_bulk(rxq->mb_pool,
1339                                   (void **)(&mbufs[next_to_use & ring_mask]),
1340                                   count);
1341         if (unlikely(rc < 0)) {
1342                 rte_atomic64_inc(&rxq->adapter->drv_stats->rx_nombuf);
1343                 PMD_RX_LOG(DEBUG, "there are no enough free buffers");
1344                 return 0;
1345         }
1346
1347         for (i = 0; i < count; i++) {
1348                 uint16_t next_to_use_masked = next_to_use & ring_mask;
1349                 struct rte_mbuf *mbuf = mbufs[next_to_use_masked];
1350                 struct ena_com_buf ebuf;
1351
1352                 rte_prefetch0(mbufs[((next_to_use + 4) & ring_mask)]);
1353
1354                 req_id = rxq->empty_rx_reqs[next_to_use_masked];
1355                 rc = validate_rx_req_id(rxq, req_id);
1356                 if (unlikely(rc < 0))
1357                         break;
1358
1359                 /* prepare physical address for DMA transaction */
1360                 ebuf.paddr = mbuf->buf_iova + RTE_PKTMBUF_HEADROOM;
1361                 ebuf.len = mbuf->buf_len - RTE_PKTMBUF_HEADROOM;
1362                 /* pass resource to device */
1363                 rc = ena_com_add_single_rx_desc(rxq->ena_com_io_sq,
1364                                                 &ebuf, req_id);
1365                 if (unlikely(rc)) {
1366                         rte_mempool_put_bulk(rxq->mb_pool, (void **)(&mbuf),
1367                                              count - i);
1368                         RTE_LOG(WARNING, PMD, "failed adding rx desc\n");
1369                         break;
1370                 }
1371                 next_to_use++;
1372         }
1373
1374         if (unlikely(i < count))
1375                 RTE_LOG(WARNING, PMD, "refilled rx qid %d with only %d "
1376                         "buffers (from %d)\n", rxq->id, i, count);
1377
1378         /* When we submitted free recources to device... */
1379         if (likely(i > 0)) {
1380                 /* ...let HW know that it can fill buffers with data
1381                  *
1382                  * Add memory barrier to make sure the desc were written before
1383                  * issue a doorbell
1384                  */
1385                 rte_wmb();
1386                 ena_com_write_sq_doorbell(rxq->ena_com_io_sq);
1387
1388                 rxq->next_to_use = next_to_use;
1389         }
1390
1391         return i;
1392 }
1393
1394 static int ena_device_init(struct ena_com_dev *ena_dev,
1395                            struct ena_com_dev_get_features_ctx *get_feat_ctx,
1396                            bool *wd_state)
1397 {
1398         uint32_t aenq_groups;
1399         int rc;
1400         bool readless_supported;
1401
1402         /* Initialize mmio registers */
1403         rc = ena_com_mmio_reg_read_request_init(ena_dev);
1404         if (rc) {
1405                 RTE_LOG(ERR, PMD, "failed to init mmio read less\n");
1406                 return rc;
1407         }
1408
1409         /* The PCIe configuration space revision id indicate if mmio reg
1410          * read is disabled.
1411          */
1412         readless_supported =
1413                 !(((struct rte_pci_device *)ena_dev->dmadev)->id.class_id
1414                                & ENA_MMIO_DISABLE_REG_READ);
1415         ena_com_set_mmio_read_mode(ena_dev, readless_supported);
1416
1417         /* reset device */
1418         rc = ena_com_dev_reset(ena_dev, ENA_REGS_RESET_NORMAL);
1419         if (rc) {
1420                 RTE_LOG(ERR, PMD, "cannot reset device\n");
1421                 goto err_mmio_read_less;
1422         }
1423
1424         /* check FW version */
1425         rc = ena_com_validate_version(ena_dev);
1426         if (rc) {
1427                 RTE_LOG(ERR, PMD, "device version is too low\n");
1428                 goto err_mmio_read_less;
1429         }
1430
1431         ena_dev->dma_addr_bits = ena_com_get_dma_width(ena_dev);
1432
1433         /* ENA device administration layer init */
1434         rc = ena_com_admin_init(ena_dev, &aenq_handlers, true);
1435         if (rc) {
1436                 RTE_LOG(ERR, PMD,
1437                         "cannot initialize ena admin queue with device\n");
1438                 goto err_mmio_read_less;
1439         }
1440
1441         /* To enable the msix interrupts the driver needs to know the number
1442          * of queues. So the driver uses polling mode to retrieve this
1443          * information.
1444          */
1445         ena_com_set_admin_polling_mode(ena_dev, true);
1446
1447         ena_config_host_info(ena_dev);
1448
1449         /* Get Device Attributes and features */
1450         rc = ena_com_get_dev_attr_feat(ena_dev, get_feat_ctx);
1451         if (rc) {
1452                 RTE_LOG(ERR, PMD,
1453                         "cannot get attribute for ena device rc= %d\n", rc);
1454                 goto err_admin_init;
1455         }
1456
1457         aenq_groups = BIT(ENA_ADMIN_LINK_CHANGE) |
1458                       BIT(ENA_ADMIN_NOTIFICATION) |
1459                       BIT(ENA_ADMIN_KEEP_ALIVE) |
1460                       BIT(ENA_ADMIN_FATAL_ERROR) |
1461                       BIT(ENA_ADMIN_WARNING);
1462
1463         aenq_groups &= get_feat_ctx->aenq.supported_groups;
1464         rc = ena_com_set_aenq_config(ena_dev, aenq_groups);
1465         if (rc) {
1466                 RTE_LOG(ERR, PMD, "Cannot configure aenq groups rc: %d\n", rc);
1467                 goto err_admin_init;
1468         }
1469
1470         *wd_state = !!(aenq_groups & BIT(ENA_ADMIN_KEEP_ALIVE));
1471
1472         return 0;
1473
1474 err_admin_init:
1475         ena_com_admin_destroy(ena_dev);
1476
1477 err_mmio_read_less:
1478         ena_com_mmio_reg_read_request_destroy(ena_dev);
1479
1480         return rc;
1481 }
1482
1483 static void ena_interrupt_handler_rte(void *cb_arg)
1484 {
1485         struct ena_adapter *adapter = (struct ena_adapter *)cb_arg;
1486         struct ena_com_dev *ena_dev = &adapter->ena_dev;
1487
1488         ena_com_admin_q_comp_intr_handler(ena_dev);
1489         if (likely(adapter->state != ENA_ADAPTER_STATE_CLOSED))
1490                 ena_com_aenq_intr_handler(ena_dev, adapter);
1491 }
1492
1493 static void check_for_missing_keep_alive(struct ena_adapter *adapter)
1494 {
1495         if (!adapter->wd_state)
1496                 return;
1497
1498         if (adapter->keep_alive_timeout == ENA_HW_HINTS_NO_TIMEOUT)
1499                 return;
1500
1501         if (unlikely((rte_get_timer_cycles() - adapter->timestamp_wd) >=
1502             adapter->keep_alive_timeout)) {
1503                 RTE_LOG(ERR, PMD, "Keep alive timeout\n");
1504                 adapter->reset_reason = ENA_REGS_RESET_KEEP_ALIVE_TO;
1505                 adapter->trigger_reset = true;
1506         }
1507 }
1508
1509 /* Check if admin queue is enabled */
1510 static void check_for_admin_com_state(struct ena_adapter *adapter)
1511 {
1512         if (unlikely(!ena_com_get_admin_running_state(&adapter->ena_dev))) {
1513                 RTE_LOG(ERR, PMD, "ENA admin queue is not in running state!\n");
1514                 adapter->reset_reason = ENA_REGS_RESET_ADMIN_TO;
1515                 adapter->trigger_reset = true;
1516         }
1517 }
1518
1519 static void ena_timer_wd_callback(__rte_unused struct rte_timer *timer,
1520                                   void *arg)
1521 {
1522         struct ena_adapter *adapter = (struct ena_adapter *)arg;
1523         struct rte_eth_dev *dev = adapter->rte_dev;
1524
1525         check_for_missing_keep_alive(adapter);
1526         check_for_admin_com_state(adapter);
1527
1528         if (unlikely(adapter->trigger_reset)) {
1529                 RTE_LOG(ERR, PMD, "Trigger reset is on\n");
1530                 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_RESET,
1531                         NULL);
1532         }
1533 }
1534
1535 static int ena_calc_io_queue_num(__rte_unused struct ena_com_dev *ena_dev,
1536                                  struct ena_com_dev_get_features_ctx *get_feat_ctx)
1537 {
1538         int io_sq_num, io_cq_num, io_queue_num;
1539
1540         io_sq_num = get_feat_ctx->max_queues.max_sq_num;
1541         io_cq_num = get_feat_ctx->max_queues.max_cq_num;
1542
1543         io_queue_num = RTE_MIN(io_sq_num, io_cq_num);
1544
1545         if (unlikely(io_queue_num == 0)) {
1546                 RTE_LOG(ERR, PMD, "Number of IO queues should not be 0\n");
1547                 return -EFAULT;
1548         }
1549
1550         return io_queue_num;
1551 }
1552
1553 static int eth_ena_dev_init(struct rte_eth_dev *eth_dev)
1554 {
1555         struct rte_pci_device *pci_dev;
1556         struct rte_intr_handle *intr_handle;
1557         struct ena_adapter *adapter =
1558                 (struct ena_adapter *)(eth_dev->data->dev_private);
1559         struct ena_com_dev *ena_dev = &adapter->ena_dev;
1560         struct ena_com_dev_get_features_ctx get_feat_ctx;
1561         int queue_size, rc;
1562         u16 tx_sgl_size = 0;
1563
1564         static int adapters_found;
1565         bool wd_state;
1566
1567         memset(adapter, 0, sizeof(struct ena_adapter));
1568         ena_dev = &adapter->ena_dev;
1569
1570         eth_dev->dev_ops = &ena_dev_ops;
1571         eth_dev->rx_pkt_burst = &eth_ena_recv_pkts;
1572         eth_dev->tx_pkt_burst = &eth_ena_xmit_pkts;
1573         eth_dev->tx_pkt_prepare = &eth_ena_prep_pkts;
1574         adapter->rte_eth_dev_data = eth_dev->data;
1575         adapter->rte_dev = eth_dev;
1576
1577         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1578                 return 0;
1579
1580         pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1581         adapter->pdev = pci_dev;
1582
1583         PMD_INIT_LOG(INFO, "Initializing %x:%x:%x.%d",
1584                      pci_dev->addr.domain,
1585                      pci_dev->addr.bus,
1586                      pci_dev->addr.devid,
1587                      pci_dev->addr.function);
1588
1589         intr_handle = &pci_dev->intr_handle;
1590
1591         adapter->regs = pci_dev->mem_resource[ENA_REGS_BAR].addr;
1592         adapter->dev_mem_base = pci_dev->mem_resource[ENA_MEM_BAR].addr;
1593
1594         if (!adapter->regs) {
1595                 PMD_INIT_LOG(CRIT, "Failed to access registers BAR(%d)",
1596                              ENA_REGS_BAR);
1597                 return -ENXIO;
1598         }
1599
1600         ena_dev->reg_bar = adapter->regs;
1601         ena_dev->dmadev = adapter->pdev;
1602
1603         adapter->id_number = adapters_found;
1604
1605         snprintf(adapter->name, ENA_NAME_MAX_LEN, "ena_%d",
1606                  adapter->id_number);
1607
1608         /* device specific initialization routine */
1609         rc = ena_device_init(ena_dev, &get_feat_ctx, &wd_state);
1610         if (rc) {
1611                 PMD_INIT_LOG(CRIT, "Failed to init ENA device");
1612                 goto err;
1613         }
1614         adapter->wd_state = wd_state;
1615
1616         ena_dev->tx_mem_queue_type = ENA_ADMIN_PLACEMENT_POLICY_HOST;
1617         adapter->num_queues = ena_calc_io_queue_num(ena_dev,
1618                                                     &get_feat_ctx);
1619
1620         queue_size = ena_calc_queue_size(ena_dev, &tx_sgl_size, &get_feat_ctx);
1621         if (queue_size <= 0 || adapter->num_queues <= 0) {
1622                 rc = -EFAULT;
1623                 goto err_device_destroy;
1624         }
1625
1626         adapter->tx_ring_size = queue_size;
1627         adapter->rx_ring_size = queue_size;
1628
1629         adapter->max_tx_sgl_size = tx_sgl_size;
1630
1631         /* prepare ring structures */
1632         ena_init_rings(adapter);
1633
1634         ena_config_debug_area(adapter);
1635
1636         /* Set max MTU for this device */
1637         adapter->max_mtu = get_feat_ctx.dev_attr.max_mtu;
1638
1639         /* set device support for TSO */
1640         adapter->tso4_supported = get_feat_ctx.offload.tx &
1641                                   ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_IPV4_MASK;
1642
1643         /* Copy MAC address and point DPDK to it */
1644         eth_dev->data->mac_addrs = (struct ether_addr *)adapter->mac_addr;
1645         ether_addr_copy((struct ether_addr *)get_feat_ctx.dev_attr.mac_addr,
1646                         (struct ether_addr *)adapter->mac_addr);
1647
1648         adapter->drv_stats = rte_zmalloc("adapter stats",
1649                                          sizeof(*adapter->drv_stats),
1650                                          RTE_CACHE_LINE_SIZE);
1651         if (!adapter->drv_stats) {
1652                 RTE_LOG(ERR, PMD, "failed to alloc mem for adapter stats\n");
1653                 rc = -ENOMEM;
1654                 goto err_delete_debug_area;
1655         }
1656
1657         rte_intr_callback_register(intr_handle,
1658                                    ena_interrupt_handler_rte,
1659                                    adapter);
1660         rte_intr_enable(intr_handle);
1661         ena_com_set_admin_polling_mode(ena_dev, false);
1662         ena_com_admin_aenq_enable(ena_dev);
1663
1664         if (adapters_found == 0)
1665                 rte_timer_subsystem_init();
1666         rte_timer_init(&adapter->timer_wd);
1667
1668         adapters_found++;
1669         adapter->state = ENA_ADAPTER_STATE_INIT;
1670
1671         return 0;
1672
1673 err_delete_debug_area:
1674         ena_com_delete_debug_area(ena_dev);
1675
1676 err_device_destroy:
1677         ena_com_delete_host_info(ena_dev);
1678         ena_com_admin_destroy(ena_dev);
1679
1680 err:
1681         return rc;
1682 }
1683
1684 static int eth_ena_dev_uninit(struct rte_eth_dev *eth_dev)
1685 {
1686         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1687         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1688         struct ena_adapter *adapter =
1689                 (struct ena_adapter *)(eth_dev->data->dev_private);
1690
1691         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1692                 return 0;
1693
1694         if (adapter->state != ENA_ADAPTER_STATE_CLOSED)
1695                 ena_close(eth_dev);
1696
1697         eth_dev->dev_ops = NULL;
1698         eth_dev->rx_pkt_burst = NULL;
1699         eth_dev->tx_pkt_burst = NULL;
1700         eth_dev->tx_pkt_prepare = NULL;
1701
1702         rte_free(adapter->drv_stats);
1703         adapter->drv_stats = NULL;
1704
1705         rte_intr_disable(intr_handle);
1706         rte_intr_callback_unregister(intr_handle,
1707                                      ena_interrupt_handler_rte,
1708                                      adapter);
1709
1710         adapter->state = ENA_ADAPTER_STATE_FREE;
1711
1712         return 0;
1713 }
1714
1715 static int ena_dev_configure(struct rte_eth_dev *dev)
1716 {
1717         struct ena_adapter *adapter =
1718                 (struct ena_adapter *)(dev->data->dev_private);
1719
1720         adapter->state = ENA_ADAPTER_STATE_CONFIG;
1721
1722         adapter->tx_selected_offloads = dev->data->dev_conf.txmode.offloads;
1723         adapter->rx_selected_offloads = dev->data->dev_conf.rxmode.offloads;
1724         return 0;
1725 }
1726
1727 static void ena_init_rings(struct ena_adapter *adapter)
1728 {
1729         int i;
1730
1731         for (i = 0; i < adapter->num_queues; i++) {
1732                 struct ena_ring *ring = &adapter->tx_ring[i];
1733
1734                 ring->configured = 0;
1735                 ring->type = ENA_RING_TYPE_TX;
1736                 ring->adapter = adapter;
1737                 ring->id = i;
1738                 ring->tx_mem_queue_type = adapter->ena_dev.tx_mem_queue_type;
1739                 ring->tx_max_header_size = adapter->ena_dev.tx_max_header_size;
1740                 ring->sgl_size = adapter->max_tx_sgl_size;
1741         }
1742
1743         for (i = 0; i < adapter->num_queues; i++) {
1744                 struct ena_ring *ring = &adapter->rx_ring[i];
1745
1746                 ring->configured = 0;
1747                 ring->type = ENA_RING_TYPE_RX;
1748                 ring->adapter = adapter;
1749                 ring->id = i;
1750         }
1751 }
1752
1753 static void ena_infos_get(struct rte_eth_dev *dev,
1754                           struct rte_eth_dev_info *dev_info)
1755 {
1756         struct ena_adapter *adapter;
1757         struct ena_com_dev *ena_dev;
1758         struct ena_com_dev_get_features_ctx feat;
1759         uint64_t rx_feat = 0, tx_feat = 0;
1760         int rc = 0;
1761
1762         ena_assert_msg(dev->data != NULL, "Uninitialized device");
1763         ena_assert_msg(dev->data->dev_private != NULL, "Uninitialized device");
1764         adapter = (struct ena_adapter *)(dev->data->dev_private);
1765
1766         ena_dev = &adapter->ena_dev;
1767         ena_assert_msg(ena_dev != NULL, "Uninitialized device");
1768
1769         dev_info->speed_capa =
1770                         ETH_LINK_SPEED_1G   |
1771                         ETH_LINK_SPEED_2_5G |
1772                         ETH_LINK_SPEED_5G   |
1773                         ETH_LINK_SPEED_10G  |
1774                         ETH_LINK_SPEED_25G  |
1775                         ETH_LINK_SPEED_40G  |
1776                         ETH_LINK_SPEED_50G  |
1777                         ETH_LINK_SPEED_100G;
1778
1779         /* Get supported features from HW */
1780         rc = ena_com_get_dev_attr_feat(ena_dev, &feat);
1781         if (unlikely(rc)) {
1782                 RTE_LOG(ERR, PMD,
1783                         "Cannot get attribute for ena device rc= %d\n", rc);
1784                 return;
1785         }
1786
1787         /* Set Tx & Rx features available for device */
1788         if (feat.offload.tx & ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_IPV4_MASK)
1789                 tx_feat |= DEV_TX_OFFLOAD_TCP_TSO;
1790
1791         if (feat.offload.tx &
1792             ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV4_CSUM_PART_MASK)
1793                 tx_feat |= DEV_TX_OFFLOAD_IPV4_CKSUM |
1794                         DEV_TX_OFFLOAD_UDP_CKSUM |
1795                         DEV_TX_OFFLOAD_TCP_CKSUM;
1796
1797         if (feat.offload.rx_supported &
1798             ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L4_IPV4_CSUM_MASK)
1799                 rx_feat |= DEV_RX_OFFLOAD_IPV4_CKSUM |
1800                         DEV_RX_OFFLOAD_UDP_CKSUM  |
1801                         DEV_RX_OFFLOAD_TCP_CKSUM;
1802
1803         rx_feat |= DEV_RX_OFFLOAD_JUMBO_FRAME;
1804
1805         /* Inform framework about available features */
1806         dev_info->rx_offload_capa = rx_feat;
1807         dev_info->rx_queue_offload_capa = rx_feat;
1808         dev_info->tx_offload_capa = tx_feat;
1809         dev_info->tx_queue_offload_capa = tx_feat;
1810
1811         dev_info->min_rx_bufsize = ENA_MIN_FRAME_LEN;
1812         dev_info->max_rx_pktlen  = adapter->max_mtu;
1813         dev_info->max_mac_addrs = 1;
1814
1815         dev_info->max_rx_queues = adapter->num_queues;
1816         dev_info->max_tx_queues = adapter->num_queues;
1817         dev_info->reta_size = ENA_RX_RSS_TABLE_SIZE;
1818
1819         adapter->tx_supported_offloads = tx_feat;
1820         adapter->rx_supported_offloads = rx_feat;
1821
1822         dev_info->rx_desc_lim.nb_max = ENA_MAX_RING_DESC;
1823         dev_info->rx_desc_lim.nb_min = ENA_MIN_RING_DESC;
1824
1825         dev_info->tx_desc_lim.nb_max = ENA_MAX_RING_DESC;
1826         dev_info->tx_desc_lim.nb_min = ENA_MIN_RING_DESC;
1827         dev_info->tx_desc_lim.nb_seg_max = RTE_MIN(ENA_PKT_MAX_BUFS,
1828                                         feat.max_queues.max_packet_tx_descs);
1829         dev_info->tx_desc_lim.nb_mtu_seg_max = RTE_MIN(ENA_PKT_MAX_BUFS,
1830                                         feat.max_queues.max_packet_tx_descs);
1831 }
1832
1833 static uint16_t eth_ena_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,
1834                                   uint16_t nb_pkts)
1835 {
1836         struct ena_ring *rx_ring = (struct ena_ring *)(rx_queue);
1837         unsigned int ring_size = rx_ring->ring_size;
1838         unsigned int ring_mask = ring_size - 1;
1839         uint16_t next_to_clean = rx_ring->next_to_clean;
1840         uint16_t desc_in_use = 0;
1841         uint16_t req_id;
1842         unsigned int recv_idx = 0;
1843         struct rte_mbuf *mbuf = NULL;
1844         struct rte_mbuf *mbuf_head = NULL;
1845         struct rte_mbuf *mbuf_prev = NULL;
1846         struct rte_mbuf **rx_buff_info = rx_ring->rx_buffer_info;
1847         unsigned int completed;
1848
1849         struct ena_com_rx_ctx ena_rx_ctx;
1850         int rc = 0;
1851
1852         /* Check adapter state */
1853         if (unlikely(rx_ring->adapter->state != ENA_ADAPTER_STATE_RUNNING)) {
1854                 RTE_LOG(ALERT, PMD,
1855                         "Trying to receive pkts while device is NOT running\n");
1856                 return 0;
1857         }
1858
1859         desc_in_use = rx_ring->next_to_use - next_to_clean;
1860         if (unlikely(nb_pkts > desc_in_use))
1861                 nb_pkts = desc_in_use;
1862
1863         for (completed = 0; completed < nb_pkts; completed++) {
1864                 int segments = 0;
1865
1866                 ena_rx_ctx.max_bufs = rx_ring->ring_size;
1867                 ena_rx_ctx.ena_bufs = rx_ring->ena_bufs;
1868                 ena_rx_ctx.descs = 0;
1869                 /* receive packet context */
1870                 rc = ena_com_rx_pkt(rx_ring->ena_com_io_cq,
1871                                     rx_ring->ena_com_io_sq,
1872                                     &ena_rx_ctx);
1873                 if (unlikely(rc)) {
1874                         RTE_LOG(ERR, PMD, "ena_com_rx_pkt error %d\n", rc);
1875                         rx_ring->adapter->trigger_reset = true;
1876                         return 0;
1877                 }
1878
1879                 if (unlikely(ena_rx_ctx.descs == 0))
1880                         break;
1881
1882                 while (segments < ena_rx_ctx.descs) {
1883                         req_id = ena_rx_ctx.ena_bufs[segments].req_id;
1884                         rc = validate_rx_req_id(rx_ring, req_id);
1885                         if (unlikely(rc))
1886                                 break;
1887
1888                         mbuf = rx_buff_info[req_id];
1889                         mbuf->data_len = ena_rx_ctx.ena_bufs[segments].len;
1890                         mbuf->data_off = RTE_PKTMBUF_HEADROOM;
1891                         mbuf->refcnt = 1;
1892                         mbuf->next = NULL;
1893                         if (unlikely(segments == 0)) {
1894                                 mbuf->nb_segs = ena_rx_ctx.descs;
1895                                 mbuf->port = rx_ring->port_id;
1896                                 mbuf->pkt_len = 0;
1897                                 mbuf_head = mbuf;
1898                         } else {
1899                                 /* for multi-segment pkts create mbuf chain */
1900                                 mbuf_prev->next = mbuf;
1901                         }
1902                         mbuf_head->pkt_len += mbuf->data_len;
1903
1904                         mbuf_prev = mbuf;
1905                         rx_ring->empty_rx_reqs[next_to_clean & ring_mask] =
1906                                 req_id;
1907                         segments++;
1908                         next_to_clean++;
1909                 }
1910
1911                 /* fill mbuf attributes if any */
1912                 ena_rx_mbuf_prepare(mbuf_head, &ena_rx_ctx);
1913                 mbuf_head->hash.rss = ena_rx_ctx.hash;
1914
1915                 /* pass to DPDK application head mbuf */
1916                 rx_pkts[recv_idx] = mbuf_head;
1917                 recv_idx++;
1918         }
1919
1920         rx_ring->next_to_clean = next_to_clean;
1921
1922         desc_in_use = desc_in_use - completed + 1;
1923         /* Burst refill to save doorbells, memory barriers, const interval */
1924         if (ring_size - desc_in_use > ENA_RING_DESCS_RATIO(ring_size))
1925                 ena_populate_rx_queue(rx_ring, ring_size - desc_in_use);
1926
1927         return recv_idx;
1928 }
1929
1930 static uint16_t
1931 eth_ena_prep_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
1932                 uint16_t nb_pkts)
1933 {
1934         int32_t ret;
1935         uint32_t i;
1936         struct rte_mbuf *m;
1937         struct ena_ring *tx_ring = (struct ena_ring *)(tx_queue);
1938         struct ipv4_hdr *ip_hdr;
1939         uint64_t ol_flags;
1940         uint16_t frag_field;
1941
1942         for (i = 0; i != nb_pkts; i++) {
1943                 m = tx_pkts[i];
1944                 ol_flags = m->ol_flags;
1945
1946                 if (!(ol_flags & PKT_TX_IPV4))
1947                         continue;
1948
1949                 /* If there was not L2 header length specified, assume it is
1950                  * length of the ethernet header.
1951                  */
1952                 if (unlikely(m->l2_len == 0))
1953                         m->l2_len = sizeof(struct ether_hdr);
1954
1955                 ip_hdr = rte_pktmbuf_mtod_offset(m, struct ipv4_hdr *,
1956                                                  m->l2_len);
1957                 frag_field = rte_be_to_cpu_16(ip_hdr->fragment_offset);
1958
1959                 if ((frag_field & IPV4_HDR_DF_FLAG) != 0) {
1960                         m->packet_type |= RTE_PTYPE_L4_NONFRAG;
1961
1962                         /* If IPv4 header has DF flag enabled and TSO support is
1963                          * disabled, partial chcecksum should not be calculated.
1964                          */
1965                         if (!tx_ring->adapter->tso4_supported)
1966                                 continue;
1967                 }
1968
1969                 if ((ol_flags & ENA_TX_OFFLOAD_NOTSUP_MASK) != 0 ||
1970                                 (ol_flags & PKT_TX_L4_MASK) ==
1971                                 PKT_TX_SCTP_CKSUM) {
1972                         rte_errno = -ENOTSUP;
1973                         return i;
1974                 }
1975
1976 #ifdef RTE_LIBRTE_ETHDEV_DEBUG
1977                 ret = rte_validate_tx_offload(m);
1978                 if (ret != 0) {
1979                         rte_errno = ret;
1980                         return i;
1981                 }
1982 #endif
1983
1984                 /* In case we are supposed to TSO and have DF not set (DF=0)
1985                  * hardware must be provided with partial checksum, otherwise
1986                  * it will take care of necessary calculations.
1987                  */
1988
1989                 ret = rte_net_intel_cksum_flags_prepare(m,
1990                         ol_flags & ~PKT_TX_TCP_SEG);
1991                 if (ret != 0) {
1992                         rte_errno = ret;
1993                         return i;
1994                 }
1995         }
1996
1997         return i;
1998 }
1999
2000 static void ena_update_hints(struct ena_adapter *adapter,
2001                              struct ena_admin_ena_hw_hints *hints)
2002 {
2003         if (hints->admin_completion_tx_timeout)
2004                 adapter->ena_dev.admin_queue.completion_timeout =
2005                         hints->admin_completion_tx_timeout * 1000;
2006
2007         if (hints->mmio_read_timeout)
2008                 /* convert to usec */
2009                 adapter->ena_dev.mmio_read.reg_read_to =
2010                         hints->mmio_read_timeout * 1000;
2011
2012         if (hints->driver_watchdog_timeout) {
2013                 if (hints->driver_watchdog_timeout == ENA_HW_HINTS_NO_TIMEOUT)
2014                         adapter->keep_alive_timeout = ENA_HW_HINTS_NO_TIMEOUT;
2015                 else
2016                         // Convert msecs to ticks
2017                         adapter->keep_alive_timeout =
2018                                 (hints->driver_watchdog_timeout *
2019                                 rte_get_timer_hz()) / 1000;
2020         }
2021 }
2022
2023 static int ena_check_and_linearize_mbuf(struct ena_ring *tx_ring,
2024                                         struct rte_mbuf *mbuf)
2025 {
2026         int num_segments, rc;
2027
2028         num_segments = mbuf->nb_segs;
2029
2030         if (likely(num_segments < tx_ring->sgl_size))
2031                 return 0;
2032
2033         rc = rte_pktmbuf_linearize(mbuf);
2034         if (unlikely(rc))
2035                 RTE_LOG(WARNING, PMD, "Mbuf linearize failed\n");
2036
2037         return rc;
2038 }
2039
2040 static uint16_t eth_ena_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
2041                                   uint16_t nb_pkts)
2042 {
2043         struct ena_ring *tx_ring = (struct ena_ring *)(tx_queue);
2044         uint16_t next_to_use = tx_ring->next_to_use;
2045         uint16_t next_to_clean = tx_ring->next_to_clean;
2046         struct rte_mbuf *mbuf;
2047         unsigned int ring_size = tx_ring->ring_size;
2048         unsigned int ring_mask = ring_size - 1;
2049         struct ena_com_tx_ctx ena_tx_ctx;
2050         struct ena_tx_buffer *tx_info;
2051         struct ena_com_buf *ebuf;
2052         uint16_t rc, req_id, total_tx_descs = 0;
2053         uint16_t sent_idx = 0, empty_tx_reqs;
2054         int nb_hw_desc;
2055
2056         /* Check adapter state */
2057         if (unlikely(tx_ring->adapter->state != ENA_ADAPTER_STATE_RUNNING)) {
2058                 RTE_LOG(ALERT, PMD,
2059                         "Trying to xmit pkts while device is NOT running\n");
2060                 return 0;
2061         }
2062
2063         empty_tx_reqs = ring_size - (next_to_use - next_to_clean);
2064         if (nb_pkts > empty_tx_reqs)
2065                 nb_pkts = empty_tx_reqs;
2066
2067         for (sent_idx = 0; sent_idx < nb_pkts; sent_idx++) {
2068                 mbuf = tx_pkts[sent_idx];
2069
2070                 rc = ena_check_and_linearize_mbuf(tx_ring, mbuf);
2071                 if (unlikely(rc))
2072                         break;
2073
2074                 req_id = tx_ring->empty_tx_reqs[next_to_use & ring_mask];
2075                 tx_info = &tx_ring->tx_buffer_info[req_id];
2076                 tx_info->mbuf = mbuf;
2077                 tx_info->num_of_bufs = 0;
2078                 ebuf = tx_info->bufs;
2079
2080                 /* Prepare TX context */
2081                 memset(&ena_tx_ctx, 0x0, sizeof(struct ena_com_tx_ctx));
2082                 memset(&ena_tx_ctx.ena_meta, 0x0,
2083                        sizeof(struct ena_com_tx_meta));
2084                 ena_tx_ctx.ena_bufs = ebuf;
2085                 ena_tx_ctx.req_id = req_id;
2086                 if (tx_ring->tx_mem_queue_type ==
2087                                 ENA_ADMIN_PLACEMENT_POLICY_DEV) {
2088                         /* prepare the push buffer with
2089                          * virtual address of the data
2090                          */
2091                         ena_tx_ctx.header_len =
2092                                 RTE_MIN(mbuf->data_len,
2093                                         tx_ring->tx_max_header_size);
2094                         ena_tx_ctx.push_header =
2095                                 (void *)((char *)mbuf->buf_addr +
2096                                          mbuf->data_off);
2097                 } /* there's no else as we take advantage of memset zeroing */
2098
2099                 /* Set TX offloads flags, if applicable */
2100                 ena_tx_mbuf_prepare(mbuf, &ena_tx_ctx, tx_ring->offloads);
2101
2102                 if (unlikely(mbuf->ol_flags &
2103                              (PKT_RX_L4_CKSUM_BAD | PKT_RX_IP_CKSUM_BAD)))
2104                         rte_atomic64_inc(&tx_ring->adapter->drv_stats->ierrors);
2105
2106                 rte_prefetch0(tx_pkts[(sent_idx + 4) & ring_mask]);
2107
2108                 /* Process first segment taking into
2109                  * consideration pushed header
2110                  */
2111                 if (mbuf->data_len > ena_tx_ctx.header_len) {
2112                         ebuf->paddr = mbuf->buf_iova +
2113                                       mbuf->data_off +
2114                                       ena_tx_ctx.header_len;
2115                         ebuf->len = mbuf->data_len - ena_tx_ctx.header_len;
2116                         ebuf++;
2117                         tx_info->num_of_bufs++;
2118                 }
2119
2120                 while ((mbuf = mbuf->next) != NULL) {
2121                         ebuf->paddr = mbuf->buf_iova + mbuf->data_off;
2122                         ebuf->len = mbuf->data_len;
2123                         ebuf++;
2124                         tx_info->num_of_bufs++;
2125                 }
2126
2127                 ena_tx_ctx.num_bufs = tx_info->num_of_bufs;
2128
2129                 /* Write data to device */
2130                 rc = ena_com_prepare_tx(tx_ring->ena_com_io_sq,
2131                                         &ena_tx_ctx, &nb_hw_desc);
2132                 if (unlikely(rc))
2133                         break;
2134
2135                 tx_info->tx_descs = nb_hw_desc;
2136
2137                 next_to_use++;
2138         }
2139
2140         /* If there are ready packets to be xmitted... */
2141         if (sent_idx > 0) {
2142                 /* ...let HW do its best :-) */
2143                 rte_wmb();
2144                 ena_com_write_sq_doorbell(tx_ring->ena_com_io_sq);
2145
2146                 tx_ring->next_to_use = next_to_use;
2147         }
2148
2149         /* Clear complete packets  */
2150         while (ena_com_tx_comp_req_id_get(tx_ring->ena_com_io_cq, &req_id) >= 0) {
2151                 rc = validate_tx_req_id(tx_ring, req_id);
2152                 if (rc)
2153                         break;
2154
2155                 /* Get Tx info & store how many descs were processed  */
2156                 tx_info = &tx_ring->tx_buffer_info[req_id];
2157                 total_tx_descs += tx_info->tx_descs;
2158
2159                 /* Free whole mbuf chain  */
2160                 mbuf = tx_info->mbuf;
2161                 rte_pktmbuf_free(mbuf);
2162                 tx_info->mbuf = NULL;
2163
2164                 /* Put back descriptor to the ring for reuse */
2165                 tx_ring->empty_tx_reqs[next_to_clean & ring_mask] = req_id;
2166                 next_to_clean++;
2167
2168                 /* If too many descs to clean, leave it for another run */
2169                 if (unlikely(total_tx_descs > ENA_RING_DESCS_RATIO(ring_size)))
2170                         break;
2171         }
2172
2173         if (total_tx_descs > 0) {
2174                 /* acknowledge completion of sent packets */
2175                 ena_com_comp_ack(tx_ring->ena_com_io_sq, total_tx_descs);
2176                 tx_ring->next_to_clean = next_to_clean;
2177         }
2178
2179         return sent_idx;
2180 }
2181
2182 /*********************************************************************
2183  *  PMD configuration
2184  *********************************************************************/
2185 static int eth_ena_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
2186         struct rte_pci_device *pci_dev)
2187 {
2188         return rte_eth_dev_pci_generic_probe(pci_dev,
2189                 sizeof(struct ena_adapter), eth_ena_dev_init);
2190 }
2191
2192 static int eth_ena_pci_remove(struct rte_pci_device *pci_dev)
2193 {
2194         return rte_eth_dev_pci_generic_remove(pci_dev, eth_ena_dev_uninit);
2195 }
2196
2197 static struct rte_pci_driver rte_ena_pmd = {
2198         .id_table = pci_id_ena_map,
2199         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC |
2200                      RTE_PCI_DRV_WC_ACTIVATE,
2201         .probe = eth_ena_pci_probe,
2202         .remove = eth_ena_pci_remove,
2203 };
2204
2205 RTE_PMD_REGISTER_PCI(net_ena, rte_ena_pmd);
2206 RTE_PMD_REGISTER_PCI_TABLE(net_ena, pci_id_ena_map);
2207 RTE_PMD_REGISTER_KMOD_DEP(net_ena, "* igb_uio | uio_pci_generic | vfio-pci");
2208
2209 RTE_INIT(ena_init_log)
2210 {
2211         ena_logtype_init = rte_log_register("pmd.net.ena.init");
2212         if (ena_logtype_init >= 0)
2213                 rte_log_set_level(ena_logtype_init, RTE_LOG_NOTICE);
2214         ena_logtype_driver = rte_log_register("pmd.net.ena.driver");
2215         if (ena_logtype_driver >= 0)
2216                 rte_log_set_level(ena_logtype_driver, RTE_LOG_NOTICE);
2217 }
2218
2219 /******************************************************************************
2220  ******************************** AENQ Handlers *******************************
2221  *****************************************************************************/
2222 static void ena_update_on_link_change(void *adapter_data,
2223                                       struct ena_admin_aenq_entry *aenq_e)
2224 {
2225         struct rte_eth_dev *eth_dev;
2226         struct ena_adapter *adapter;
2227         struct ena_admin_aenq_link_change_desc *aenq_link_desc;
2228         uint32_t status;
2229
2230         adapter = (struct ena_adapter *)adapter_data;
2231         aenq_link_desc = (struct ena_admin_aenq_link_change_desc *)aenq_e;
2232         eth_dev = adapter->rte_dev;
2233
2234         status = get_ena_admin_aenq_link_change_desc_link_status(aenq_link_desc);
2235         adapter->link_status = status;
2236
2237         ena_link_update(eth_dev, 0);
2238         _rte_eth_dev_callback_process(eth_dev, RTE_ETH_EVENT_INTR_LSC, NULL);
2239 }
2240
2241 static void ena_notification(void *data,
2242                              struct ena_admin_aenq_entry *aenq_e)
2243 {
2244         struct ena_adapter *adapter = (struct ena_adapter *)data;
2245         struct ena_admin_ena_hw_hints *hints;
2246
2247         if (aenq_e->aenq_common_desc.group != ENA_ADMIN_NOTIFICATION)
2248                 RTE_LOG(WARNING, PMD, "Invalid group(%x) expected %x\n",
2249                         aenq_e->aenq_common_desc.group,
2250                         ENA_ADMIN_NOTIFICATION);
2251
2252         switch (aenq_e->aenq_common_desc.syndrom) {
2253         case ENA_ADMIN_UPDATE_HINTS:
2254                 hints = (struct ena_admin_ena_hw_hints *)
2255                         (&aenq_e->inline_data_w4);
2256                 ena_update_hints(adapter, hints);
2257                 break;
2258         default:
2259                 RTE_LOG(ERR, PMD, "Invalid aenq notification link state %d\n",
2260                         aenq_e->aenq_common_desc.syndrom);
2261         }
2262 }
2263
2264 static void ena_keep_alive(void *adapter_data,
2265                            __rte_unused struct ena_admin_aenq_entry *aenq_e)
2266 {
2267         struct ena_adapter *adapter = (struct ena_adapter *)adapter_data;
2268
2269         adapter->timestamp_wd = rte_get_timer_cycles();
2270 }
2271
2272 /**
2273  * This handler will called for unknown event group or unimplemented handlers
2274  **/
2275 static void unimplemented_aenq_handler(__rte_unused void *data,
2276                                        __rte_unused struct ena_admin_aenq_entry *aenq_e)
2277 {
2278         RTE_LOG(ERR, PMD, "Unknown event was received or event with "
2279                           "unimplemented handler\n");
2280 }
2281
2282 static struct ena_aenq_handlers aenq_handlers = {
2283         .handlers = {
2284                 [ENA_ADMIN_LINK_CHANGE] = ena_update_on_link_change,
2285                 [ENA_ADMIN_NOTIFICATION] = ena_notification,
2286                 [ENA_ADMIN_KEEP_ALIVE] = ena_keep_alive
2287         },
2288         .unimplemented_handler = unimplemented_aenq_handler
2289 };