drivers/net/ena/ena_ethdev.c

   1 /*-
   2 * BSD LICENSE
   3 *
   4 * Copyright (c) 2015-2016 Amazon.com, Inc. or its affiliates.
   5 * All rights reserved.
   6 *
   7 * Redistribution and use in source and binary forms, with or without
   8 * modification, are permitted provided that the following conditions
   9 * are met:
  10 *
  11 * * Redistributions of source code must retain the above copyright
  12 * notice, this list of conditions and the following disclaimer.
  13 * * Redistributions in binary form must reproduce the above copyright
  14 * notice, this list of conditions and the following disclaimer in
  15 * the documentation and/or other materials provided with the
  16 * distribution.
  17 * * Neither the name of copyright holder nor the names of its
  18 * contributors may be used to endorse or promote products derived
  19 * from this software without specific prior written permission.
  20 *
  21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32 */
  33
  34 #include <rte_ether.h>
  35 #include <rte_ethdev.h>
  36 #include <rte_ethdev_pci.h>
  37 #include <rte_tcp.h>
  38 #include <rte_atomic.h>
  39 #include <rte_dev.h>
  40 #include <rte_errno.h>
  41 #include <rte_version.h>
  42 #include <rte_eal_memconfig.h>
  43 #include <rte_net.h>
  44
  45 #include "ena_ethdev.h"
  46 #include "ena_logs.h"
  47 #include "ena_platform.h"
  48 #include "ena_com.h"
  49 #include "ena_eth_com.h"
  50
  51 #include <ena_common_defs.h>
  52 #include <ena_regs_defs.h>
  53 #include <ena_admin_defs.h>
  54 #include <ena_eth_io_defs.h>
  55
  56 #define DRV_MODULE_VER_MAJOR    1
  57 #define DRV_MODULE_VER_MINOR    0
  58 #define DRV_MODULE_VER_SUBMINOR 0
  59
  60 #define ENA_IO_TXQ_IDX(q)       (2 * (q))
  61 #define ENA_IO_RXQ_IDX(q)       (2 * (q) + 1)
  62 /*reverse version of ENA_IO_RXQ_IDX*/
  63 #define ENA_IO_RXQ_IDX_REV(q)   ((q - 1) / 2)
  64
  65 /* While processing submitted and completed descriptors (rx and tx path
  66  * respectively) in a loop it is desired to:
  67  *  - perform batch submissions while populating sumbissmion queue
  68  *  - avoid blocking transmission of other packets during cleanup phase
  69  * Hence the utilization ratio of 1/8 of a queue size.
  70  */
  71 #define ENA_RING_DESCS_RATIO(ring_size) (ring_size / 8)
  72
  73 #define __MERGE_64B_H_L(h, l) (((uint64_t)h << 32) | l)
  74 #define TEST_BIT(val, bit_shift) (val & (1UL << bit_shift))
  75
  76 #define GET_L4_HDR_LEN(mbuf)                                    \
  77         ((rte_pktmbuf_mtod_offset(mbuf, struct tcp_hdr *,       \
  78                 mbuf->l3_len + mbuf->l2_len)->data_off) >> 4)
  79
  80 #define ENA_RX_RSS_TABLE_LOG_SIZE  7
  81 #define ENA_RX_RSS_TABLE_SIZE   (1 << ENA_RX_RSS_TABLE_LOG_SIZE)
  82 #define ENA_HASH_KEY_SIZE       40
  83 #define ENA_ETH_SS_STATS        0xFF
  84 #define ETH_GSTRING_LEN 32
  85
  86 #define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
  87
  88 enum ethtool_stringset {
  89         ETH_SS_TEST             = 0,
  90         ETH_SS_STATS,
  91 };
  92
  93 struct ena_stats {
  94         char name[ETH_GSTRING_LEN];
  95         int stat_offset;
  96 };
  97
  98 #define ENA_STAT_ENA_COM_ENTRY(stat) { \
  99         .name = #stat, \
 100         .stat_offset = offsetof(struct ena_com_stats_admin, stat) \
 101 }
 102
 103 #define ENA_STAT_ENTRY(stat, stat_type) { \
 104         .name = #stat, \
 105         .stat_offset = offsetof(struct ena_stats_##stat_type, stat) \
 106 }
 107
 108 #define ENA_STAT_RX_ENTRY(stat) \
 109         ENA_STAT_ENTRY(stat, rx)
 110
 111 #define ENA_STAT_TX_ENTRY(stat) \
 112         ENA_STAT_ENTRY(stat, tx)
 113
 114 #define ENA_STAT_GLOBAL_ENTRY(stat) \
 115         ENA_STAT_ENTRY(stat, dev)
 116
 117 static const struct ena_stats ena_stats_global_strings[] = {
 118         ENA_STAT_GLOBAL_ENTRY(tx_timeout),
 119         ENA_STAT_GLOBAL_ENTRY(io_suspend),
 120         ENA_STAT_GLOBAL_ENTRY(io_resume),
 121         ENA_STAT_GLOBAL_ENTRY(wd_expired),
 122         ENA_STAT_GLOBAL_ENTRY(interface_up),
 123         ENA_STAT_GLOBAL_ENTRY(interface_down),
 124         ENA_STAT_GLOBAL_ENTRY(admin_q_pause),
 125 };
 126
 127 static const struct ena_stats ena_stats_tx_strings[] = {
 128         ENA_STAT_TX_ENTRY(cnt),
 129         ENA_STAT_TX_ENTRY(bytes),
 130         ENA_STAT_TX_ENTRY(queue_stop),
 131         ENA_STAT_TX_ENTRY(queue_wakeup),
 132         ENA_STAT_TX_ENTRY(dma_mapping_err),
 133         ENA_STAT_TX_ENTRY(linearize),
 134         ENA_STAT_TX_ENTRY(linearize_failed),
 135         ENA_STAT_TX_ENTRY(tx_poll),
 136         ENA_STAT_TX_ENTRY(doorbells),
 137         ENA_STAT_TX_ENTRY(prepare_ctx_err),
 138         ENA_STAT_TX_ENTRY(missing_tx_comp),
 139         ENA_STAT_TX_ENTRY(bad_req_id),
 140 };
 141
 142 static const struct ena_stats ena_stats_rx_strings[] = {
 143         ENA_STAT_RX_ENTRY(cnt),
 144         ENA_STAT_RX_ENTRY(bytes),
 145         ENA_STAT_RX_ENTRY(refil_partial),
 146         ENA_STAT_RX_ENTRY(bad_csum),
 147         ENA_STAT_RX_ENTRY(page_alloc_fail),
 148         ENA_STAT_RX_ENTRY(skb_alloc_fail),
 149         ENA_STAT_RX_ENTRY(dma_mapping_err),
 150         ENA_STAT_RX_ENTRY(bad_desc_num),
 151         ENA_STAT_RX_ENTRY(small_copy_len_pkt),
 152 };
 153
 154 static const struct ena_stats ena_stats_ena_com_strings[] = {
 155         ENA_STAT_ENA_COM_ENTRY(aborted_cmd),
 156         ENA_STAT_ENA_COM_ENTRY(submitted_cmd),
 157         ENA_STAT_ENA_COM_ENTRY(completed_cmd),
 158         ENA_STAT_ENA_COM_ENTRY(out_of_space),
 159         ENA_STAT_ENA_COM_ENTRY(no_completion),
 160 };
 161
 162 #define ENA_STATS_ARRAY_GLOBAL  ARRAY_SIZE(ena_stats_global_strings)
 163 #define ENA_STATS_ARRAY_TX      ARRAY_SIZE(ena_stats_tx_strings)
 164 #define ENA_STATS_ARRAY_RX      ARRAY_SIZE(ena_stats_rx_strings)
 165 #define ENA_STATS_ARRAY_ENA_COM ARRAY_SIZE(ena_stats_ena_com_strings)
 166
 167 /** Vendor ID used by Amazon devices */
 168 #define PCI_VENDOR_ID_AMAZON 0x1D0F
 169 /** Amazon devices */
 170 #define PCI_DEVICE_ID_ENA_VF    0xEC20
 171 #define PCI_DEVICE_ID_ENA_LLQ_VF        0xEC21
 172
 173 #define ENA_TX_OFFLOAD_MASK     (\
 174         PKT_TX_L4_MASK |         \
 175         PKT_TX_IP_CKSUM |        \
 176         PKT_TX_TCP_SEG)
 177
 178 #define ENA_TX_OFFLOAD_NOTSUP_MASK      \
 179         (PKT_TX_OFFLOAD_MASK ^ ENA_TX_OFFLOAD_MASK)
 180
 181 static const struct rte_pci_id pci_id_ena_map[] = {
 182         { RTE_PCI_DEVICE(PCI_VENDOR_ID_AMAZON, PCI_DEVICE_ID_ENA_VF) },
 183         { RTE_PCI_DEVICE(PCI_VENDOR_ID_AMAZON, PCI_DEVICE_ID_ENA_LLQ_VF) },
 184         { .device_id = 0 },
 185 };
 186
 187 static int ena_device_init(struct ena_com_dev *ena_dev,
 188                            struct ena_com_dev_get_features_ctx *get_feat_ctx);
 189 static int ena_dev_configure(struct rte_eth_dev *dev);
 190 static uint16_t eth_ena_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
 191                                   uint16_t nb_pkts);
 192 static uint16_t eth_ena_prep_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
 193                 uint16_t nb_pkts);
 194 static int ena_tx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,
 195                               uint16_t nb_desc, unsigned int socket_id,
 196                               const struct rte_eth_txconf *tx_conf);
 197 static int ena_rx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,
 198                               uint16_t nb_desc, unsigned int socket_id,
 199                               const struct rte_eth_rxconf *rx_conf,
 200                               struct rte_mempool *mp);
 201 static uint16_t eth_ena_recv_pkts(void *rx_queue,
 202                                   struct rte_mbuf **rx_pkts, uint16_t nb_pkts);
 203 static int ena_populate_rx_queue(struct ena_ring *rxq, unsigned int count);
 204 static void ena_init_rings(struct ena_adapter *adapter);
 205 static int ena_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
 206 static int ena_start(struct rte_eth_dev *dev);
 207 static void ena_close(struct rte_eth_dev *dev);
 208 static int ena_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats);
 209 static void ena_rx_queue_release_all(struct rte_eth_dev *dev);
 210 static void ena_tx_queue_release_all(struct rte_eth_dev *dev);
 211 static void ena_rx_queue_release(void *queue);
 212 static void ena_tx_queue_release(void *queue);
 213 static void ena_rx_queue_release_bufs(struct ena_ring *ring);
 214 static void ena_tx_queue_release_bufs(struct ena_ring *ring);
 215 static int ena_link_update(struct rte_eth_dev *dev,
 216                            int wait_to_complete);
 217 static int ena_queue_restart(struct ena_ring *ring);
 218 static int ena_queue_restart_all(struct rte_eth_dev *dev,
 219                                  enum ena_ring_type ring_type);
 220 static void ena_stats_restart(struct rte_eth_dev *dev);
 221 static void ena_infos_get(struct rte_eth_dev *dev,
 222                           struct rte_eth_dev_info *dev_info);
 223 static int ena_rss_reta_update(struct rte_eth_dev *dev,
 224                                struct rte_eth_rss_reta_entry64 *reta_conf,
 225                                uint16_t reta_size);
 226 static int ena_rss_reta_query(struct rte_eth_dev *dev,
 227                               struct rte_eth_rss_reta_entry64 *reta_conf,
 228                               uint16_t reta_size);
 229 static int ena_get_sset_count(struct rte_eth_dev *dev, int sset);
 230
 231 static const struct eth_dev_ops ena_dev_ops = {
 232         .dev_configure        = ena_dev_configure,
 233         .dev_infos_get        = ena_infos_get,
 234         .rx_queue_setup       = ena_rx_queue_setup,
 235         .tx_queue_setup       = ena_tx_queue_setup,
 236         .dev_start            = ena_start,
 237         .link_update          = ena_link_update,
 238         .stats_get            = ena_stats_get,
 239         .mtu_set              = ena_mtu_set,
 240         .rx_queue_release     = ena_rx_queue_release,
 241         .tx_queue_release     = ena_tx_queue_release,
 242         .dev_close            = ena_close,
 243         .reta_update          = ena_rss_reta_update,
 244         .reta_query           = ena_rss_reta_query,
 245 };
 246
 247 #define NUMA_NO_NODE    SOCKET_ID_ANY
 248
 249 static inline int ena_cpu_to_node(int cpu)
 250 {
 251         struct rte_config *config = rte_eal_get_configuration();
 252
 253         if (likely(cpu < RTE_MAX_MEMZONE))
 254                 return config->mem_config->memzone[cpu].socket_id;
 255
 256         return NUMA_NO_NODE;
 257 }
 258
 259 static inline void ena_rx_mbuf_prepare(struct rte_mbuf *mbuf,
 260                                        struct ena_com_rx_ctx *ena_rx_ctx)
 261 {
 262         uint64_t ol_flags = 0;
 263         uint32_t packet_type = 0;
 264
 265         if (ena_rx_ctx->l4_proto == ENA_ETH_IO_L4_PROTO_TCP)
 266                 packet_type |= RTE_PTYPE_L4_TCP;
 267         else if (ena_rx_ctx->l4_proto == ENA_ETH_IO_L4_PROTO_UDP)
 268                 packet_type |= RTE_PTYPE_L4_UDP;
 269
 270         if (ena_rx_ctx->l3_proto == ENA_ETH_IO_L3_PROTO_IPV4)
 271                 packet_type |= RTE_PTYPE_L3_IPV4;
 272         else if (ena_rx_ctx->l3_proto == ENA_ETH_IO_L3_PROTO_IPV6)
 273                 packet_type |= RTE_PTYPE_L3_IPV6;
 274
 275         if (unlikely(ena_rx_ctx->l4_csum_err))
 276                 ol_flags |= PKT_RX_L4_CKSUM_BAD;
 277         if (unlikely(ena_rx_ctx->l3_csum_err))
 278                 ol_flags |= PKT_RX_IP_CKSUM_BAD;
 279
 280         mbuf->ol_flags = ol_flags;
 281         mbuf->packet_type = packet_type;
 282 }
 283
 284 static inline void ena_tx_mbuf_prepare(struct rte_mbuf *mbuf,
 285                                        struct ena_com_tx_ctx *ena_tx_ctx)
 286 {
 287         struct ena_com_tx_meta *ena_meta = &ena_tx_ctx->ena_meta;
 288
 289         if (mbuf->ol_flags &
 290             (PKT_TX_L4_MASK | PKT_TX_IP_CKSUM | PKT_TX_TCP_SEG)) {
 291                 /* check if TSO is required */
 292                 if (mbuf->ol_flags & PKT_TX_TCP_SEG) {
 293                         ena_tx_ctx->tso_enable = true;
 294
 295                         ena_meta->l4_hdr_len = GET_L4_HDR_LEN(mbuf);
 296                 }
 297
 298                 /* check if L3 checksum is needed */
 299                 if (mbuf->ol_flags & PKT_TX_IP_CKSUM)
 300                         ena_tx_ctx->l3_csum_enable = true;
 301
 302                 if (mbuf->ol_flags & PKT_TX_IPV6) {
 303                         ena_tx_ctx->l3_proto = ENA_ETH_IO_L3_PROTO_IPV6;
 304                 } else {
 305                         ena_tx_ctx->l3_proto = ENA_ETH_IO_L3_PROTO_IPV4;
 306
 307                         /* set don't fragment (DF) flag */
 308                         if (mbuf->packet_type &
 309                                 (RTE_PTYPE_L4_NONFRAG
 310                                  | RTE_PTYPE_INNER_L4_NONFRAG))
 311                                 ena_tx_ctx->df = true;
 312                 }
 313
 314                 /* check if L4 checksum is needed */
 315                 switch (mbuf->ol_flags & PKT_TX_L4_MASK) {
 316                 case PKT_TX_TCP_CKSUM:
 317                         ena_tx_ctx->l4_proto = ENA_ETH_IO_L4_PROTO_TCP;
 318                         ena_tx_ctx->l4_csum_enable = true;
 319                         break;
 320                 case PKT_TX_UDP_CKSUM:
 321                         ena_tx_ctx->l4_proto = ENA_ETH_IO_L4_PROTO_UDP;
 322                         ena_tx_ctx->l4_csum_enable = true;
 323                         break;
 324                 default:
 325                         ena_tx_ctx->l4_proto = ENA_ETH_IO_L4_PROTO_UNKNOWN;
 326                         ena_tx_ctx->l4_csum_enable = false;
 327                         break;
 328                 }
 329
 330                 ena_meta->mss = mbuf->tso_segsz;
 331                 ena_meta->l3_hdr_len = mbuf->l3_len;
 332                 ena_meta->l3_hdr_offset = mbuf->l2_len;
 333                 /* this param needed only for TSO */
 334                 ena_meta->l3_outer_hdr_len = 0;
 335                 ena_meta->l3_outer_hdr_offset = 0;
 336
 337                 ena_tx_ctx->meta_valid = true;
 338         } else {
 339                 ena_tx_ctx->meta_valid = false;
 340         }
 341 }
 342
 343 static void ena_config_host_info(struct ena_com_dev *ena_dev)
 344 {
 345         struct ena_admin_host_info *host_info;
 346         int rc;
 347
 348         /* Allocate only the host info */
 349         rc = ena_com_allocate_host_info(ena_dev);
 350         if (rc) {
 351                 RTE_LOG(ERR, PMD, "Cannot allocate host info\n");
 352                 return;
 353         }
 354
 355         host_info = ena_dev->host_attr.host_info;
 356
 357         host_info->os_type = ENA_ADMIN_OS_DPDK;
 358         host_info->kernel_ver = RTE_VERSION;
 359         snprintf((char *)host_info->kernel_ver_str,
 360                  sizeof(host_info->kernel_ver_str),
 361                  "%s", rte_version());
 362         host_info->os_dist = RTE_VERSION;
 363         snprintf((char *)host_info->os_dist_str,
 364                  sizeof(host_info->os_dist_str),
 365                  "%s", rte_version());
 366         host_info->driver_version =
 367                 (DRV_MODULE_VER_MAJOR) |
 368                 (DRV_MODULE_VER_MINOR << ENA_ADMIN_HOST_INFO_MINOR_SHIFT) |
 369                 (DRV_MODULE_VER_SUBMINOR <<
 370                         ENA_ADMIN_HOST_INFO_SUB_MINOR_SHIFT);
 371
 372         rc = ena_com_set_host_attributes(ena_dev);
 373         if (rc) {
 374                 RTE_LOG(ERR, PMD, "Cannot set host attributes\n");
 375                 if (rc != -EPERM)
 376                         goto err;
 377         }
 378
 379         return;
 380
 381 err:
 382         ena_com_delete_host_info(ena_dev);
 383 }
 384
 385 static int
 386 ena_get_sset_count(struct rte_eth_dev *dev, int sset)
 387 {
 388         if (sset != ETH_SS_STATS)
 389                 return -EOPNOTSUPP;
 390
 391          /* Workaround for clang:
 392          * touch internal structures to prevent
 393          * compiler error
 394          */
 395         ENA_TOUCH(ena_stats_global_strings);
 396         ENA_TOUCH(ena_stats_tx_strings);
 397         ENA_TOUCH(ena_stats_rx_strings);
 398         ENA_TOUCH(ena_stats_ena_com_strings);
 399
 400         return  dev->data->nb_tx_queues *
 401                 (ENA_STATS_ARRAY_TX + ENA_STATS_ARRAY_RX) +
 402                 ENA_STATS_ARRAY_GLOBAL + ENA_STATS_ARRAY_ENA_COM;
 403 }
 404
 405 static void ena_config_debug_area(struct ena_adapter *adapter)
 406 {
 407         u32 debug_area_size;
 408         int rc, ss_count;
 409
 410         ss_count = ena_get_sset_count(adapter->rte_dev, ETH_SS_STATS);
 411         if (ss_count <= 0) {
 412                 RTE_LOG(ERR, PMD, "SS count is negative\n");
 413                 return;
 414         }
 415
 416         /* allocate 32 bytes for each string and 64bit for the value */
 417         debug_area_size = ss_count * ETH_GSTRING_LEN + sizeof(u64) * ss_count;
 418
 419         rc = ena_com_allocate_debug_area(&adapter->ena_dev, debug_area_size);
 420         if (rc) {
 421                 RTE_LOG(ERR, PMD, "Cannot allocate debug area\n");
 422                 return;
 423         }
 424
 425         rc = ena_com_set_host_attributes(&adapter->ena_dev);
 426         if (rc) {
 427                 RTE_LOG(WARNING, PMD, "Cannot set host attributes\n");
 428                 if (rc != -EPERM)
 429                         goto err;
 430         }
 431
 432         return;
 433 err:
 434         ena_com_delete_debug_area(&adapter->ena_dev);
 435 }
 436
 437 static void ena_close(struct rte_eth_dev *dev)
 438 {
 439         struct ena_adapter *adapter =
 440                 (struct ena_adapter *)(dev->data->dev_private);
 441
 442         adapter->state = ENA_ADAPTER_STATE_STOPPED;
 443
 444         ena_rx_queue_release_all(dev);
 445         ena_tx_queue_release_all(dev);
 446 }
 447
 448 static int ena_rss_reta_update(struct rte_eth_dev *dev,
 449                                struct rte_eth_rss_reta_entry64 *reta_conf,
 450                                uint16_t reta_size)
 451 {
 452         struct ena_adapter *adapter =
 453                 (struct ena_adapter *)(dev->data->dev_private);
 454         struct ena_com_dev *ena_dev = &adapter->ena_dev;
 455         int ret, i;
 456         u16 entry_value;
 457         int conf_idx;
 458         int idx;
 459
 460         if ((reta_size == 0) || (reta_conf == NULL))
 461                 return -EINVAL;
 462
 463         if (reta_size > ENA_RX_RSS_TABLE_SIZE) {
 464                 RTE_LOG(WARNING, PMD,
 465                         "indirection table %d is bigger than supported (%d)\n",
 466                         reta_size, ENA_RX_RSS_TABLE_SIZE);
 467                 ret = -EINVAL;
 468                 goto err;
 469         }
 470
 471         for (i = 0 ; i < reta_size ; i++) {
 472                 /* each reta_conf is for 64 entries.
 473                  * to support 128 we use 2 conf of 64
 474                  */
 475                 conf_idx = i / RTE_RETA_GROUP_SIZE;
 476                 idx = i % RTE_RETA_GROUP_SIZE;
 477                 if (TEST_BIT(reta_conf[conf_idx].mask, idx)) {
 478                         entry_value =
 479                                 ENA_IO_RXQ_IDX(reta_conf[conf_idx].reta[idx]);
 480                         ret = ena_com_indirect_table_fill_entry(ena_dev,
 481                                                                 i,
 482                                                                 entry_value);
 483                         if (unlikely(ret && (ret != ENA_COM_PERMISSION))) {
 484                                 RTE_LOG(ERR, PMD,
 485                                         "Cannot fill indirect table\n");
 486                                 ret = -ENOTSUP;
 487                                 goto err;
 488                         }
 489                 }
 490         }
 491
 492         ret = ena_com_indirect_table_set(ena_dev);
 493         if (unlikely(ret && (ret != ENA_COM_PERMISSION))) {
 494                 RTE_LOG(ERR, PMD, "Cannot flush the indirect table\n");
 495                 ret = -ENOTSUP;
 496                 goto err;
 497         }
 498
 499         RTE_LOG(DEBUG, PMD, "%s(): RSS configured %d entries  for port %d\n",
 500                 __func__, reta_size, adapter->rte_dev->data->port_id);
 501 err:
 502         return ret;
 503 }
 504
 505 /* Query redirection table. */
 506 static int ena_rss_reta_query(struct rte_eth_dev *dev,
 507                               struct rte_eth_rss_reta_entry64 *reta_conf,
 508                               uint16_t reta_size)
 509 {
 510         struct ena_adapter *adapter =
 511                 (struct ena_adapter *)(dev->data->dev_private);
 512         struct ena_com_dev *ena_dev = &adapter->ena_dev;
 513         int ret;
 514         int i;
 515         u32 indirect_table[ENA_RX_RSS_TABLE_SIZE] = {0};
 516         int reta_conf_idx;
 517         int reta_idx;
 518
 519         if (reta_size == 0 || reta_conf == NULL ||
 520             (reta_size > RTE_RETA_GROUP_SIZE && ((reta_conf + 1) == NULL)))
 521                 return -EINVAL;
 522
 523         ret = ena_com_indirect_table_get(ena_dev, indirect_table);
 524         if (unlikely(ret && (ret != ENA_COM_PERMISSION))) {
 525                 RTE_LOG(ERR, PMD, "cannot get indirect table\n");
 526                 ret = -ENOTSUP;
 527                 goto err;
 528         }
 529
 530         for (i = 0 ; i < reta_size ; i++) {
 531                 reta_conf_idx = i / RTE_RETA_GROUP_SIZE;
 532                 reta_idx = i % RTE_RETA_GROUP_SIZE;
 533                 if (TEST_BIT(reta_conf[reta_conf_idx].mask, reta_idx))
 534                         reta_conf[reta_conf_idx].reta[reta_idx] =
 535                                 ENA_IO_RXQ_IDX_REV(indirect_table[i]);
 536         }
 537 err:
 538         return ret;
 539 }
 540
 541 static int ena_rss_init_default(struct ena_adapter *adapter)
 542 {
 543         struct ena_com_dev *ena_dev = &adapter->ena_dev;
 544         uint16_t nb_rx_queues = adapter->rte_dev->data->nb_rx_queues;
 545         int rc, i;
 546         u32 val;
 547
 548         rc = ena_com_rss_init(ena_dev, ENA_RX_RSS_TABLE_LOG_SIZE);
 549         if (unlikely(rc)) {
 550                 RTE_LOG(ERR, PMD, "Cannot init indirect table\n");
 551                 goto err_rss_init;
 552         }
 553
 554         for (i = 0; i < ENA_RX_RSS_TABLE_SIZE; i++) {
 555                 val = i % nb_rx_queues;
 556                 rc = ena_com_indirect_table_fill_entry(ena_dev, i,
 557                                                        ENA_IO_RXQ_IDX(val));
 558                 if (unlikely(rc && (rc != ENA_COM_PERMISSION))) {
 559                         RTE_LOG(ERR, PMD, "Cannot fill indirect table\n");
 560                         goto err_fill_indir;
 561                 }
 562         }
 563
 564         rc = ena_com_fill_hash_function(ena_dev, ENA_ADMIN_CRC32, NULL,
 565                                         ENA_HASH_KEY_SIZE, 0xFFFFFFFF);
 566         if (unlikely(rc && (rc != ENA_COM_PERMISSION))) {
 567                 RTE_LOG(INFO, PMD, "Cannot fill hash function\n");
 568                 goto err_fill_indir;
 569         }
 570
 571         rc = ena_com_set_default_hash_ctrl(ena_dev);
 572         if (unlikely(rc && (rc != ENA_COM_PERMISSION))) {
 573                 RTE_LOG(INFO, PMD, "Cannot fill hash control\n");
 574                 goto err_fill_indir;
 575         }
 576
 577         rc = ena_com_indirect_table_set(ena_dev);
 578         if (unlikely(rc && (rc != ENA_COM_PERMISSION))) {
 579                 RTE_LOG(ERR, PMD, "Cannot flush the indirect table\n");
 580                 goto err_fill_indir;
 581         }
 582         RTE_LOG(DEBUG, PMD, "RSS configured for port %d\n",
 583                 adapter->rte_dev->data->port_id);
 584
 585         return 0;
 586
 587 err_fill_indir:
 588         ena_com_rss_destroy(ena_dev);
 589 err_rss_init:
 590
 591         return rc;
 592 }
 593
 594 static void ena_rx_queue_release_all(struct rte_eth_dev *dev)
 595 {
 596         struct ena_ring **queues = (struct ena_ring **)dev->data->rx_queues;
 597         int nb_queues = dev->data->nb_rx_queues;
 598         int i;
 599
 600         for (i = 0; i < nb_queues; i++)
 601                 ena_rx_queue_release(queues[i]);
 602 }
 603
 604 static void ena_tx_queue_release_all(struct rte_eth_dev *dev)
 605 {
 606         struct ena_ring **queues = (struct ena_ring **)dev->data->tx_queues;
 607         int nb_queues = dev->data->nb_tx_queues;
 608         int i;
 609
 610         for (i = 0; i < nb_queues; i++)
 611                 ena_tx_queue_release(queues[i]);
 612 }
 613
 614 static void ena_rx_queue_release(void *queue)
 615 {
 616         struct ena_ring *ring = (struct ena_ring *)queue;
 617         struct ena_adapter *adapter = ring->adapter;
 618         int ena_qid;
 619
 620         ena_assert_msg(ring->configured,
 621                        "API violation - releasing not configured queue");
 622         ena_assert_msg(ring->adapter->state != ENA_ADAPTER_STATE_RUNNING,
 623                        "API violation");
 624
 625         /* Destroy HW queue */
 626         ena_qid = ENA_IO_RXQ_IDX(ring->id);
 627         ena_com_destroy_io_queue(&adapter->ena_dev, ena_qid);
 628
 629         /* Free all bufs */
 630         ena_rx_queue_release_bufs(ring);
 631
 632         /* Free ring resources */
 633         if (ring->rx_buffer_info)
 634                 rte_free(ring->rx_buffer_info);
 635         ring->rx_buffer_info = NULL;
 636
 637         ring->configured = 0;
 638
 639         RTE_LOG(NOTICE, PMD, "RX Queue %d:%d released\n",
 640                 ring->port_id, ring->id);
 641 }
 642
 643 static void ena_tx_queue_release(void *queue)
 644 {
 645         struct ena_ring *ring = (struct ena_ring *)queue;
 646         struct ena_adapter *adapter = ring->adapter;
 647         int ena_qid;
 648
 649         ena_assert_msg(ring->configured,
 650                        "API violation. Releasing not configured queue");
 651         ena_assert_msg(ring->adapter->state != ENA_ADAPTER_STATE_RUNNING,
 652                        "API violation");
 653
 654         /* Destroy HW queue */
 655         ena_qid = ENA_IO_TXQ_IDX(ring->id);
 656         ena_com_destroy_io_queue(&adapter->ena_dev, ena_qid);
 657
 658         /* Free all bufs */
 659         ena_tx_queue_release_bufs(ring);
 660
 661         /* Free ring resources */
 662         if (ring->tx_buffer_info)
 663                 rte_free(ring->tx_buffer_info);
 664
 665         if (ring->empty_tx_reqs)
 666                 rte_free(ring->empty_tx_reqs);
 667
 668         ring->empty_tx_reqs = NULL;
 669         ring->tx_buffer_info = NULL;
 670
 671         ring->configured = 0;
 672
 673         RTE_LOG(NOTICE, PMD, "TX Queue %d:%d released\n",
 674                 ring->port_id, ring->id);
 675 }
 676
 677 static void ena_rx_queue_release_bufs(struct ena_ring *ring)
 678 {
 679         unsigned int ring_mask = ring->ring_size - 1;
 680
 681         while (ring->next_to_clean != ring->next_to_use) {
 682                 struct rte_mbuf *m =
 683                         ring->rx_buffer_info[ring->next_to_clean & ring_mask];
 684
 685                 if (m)
 686                         rte_mbuf_raw_free(m);
 687
 688                 ring->next_to_clean++;
 689         }
 690 }
 691
 692 static void ena_tx_queue_release_bufs(struct ena_ring *ring)
 693 {
 694         unsigned int i;
 695
 696         for (i = 0; i < ring->ring_size; ++i) {
 697                 struct ena_tx_buffer *tx_buf = &ring->tx_buffer_info[i];
 698
 699                 if (tx_buf->mbuf)
 700                         rte_pktmbuf_free(tx_buf->mbuf);
 701
 702                 ring->next_to_clean++;
 703         }
 704 }
 705
 706 static int ena_link_update(struct rte_eth_dev *dev,
 707                            __rte_unused int wait_to_complete)
 708 {
 709         struct rte_eth_link *link = &dev->data->dev_link;
 710
 711         link->link_status = 1;
 712         link->link_speed = ETH_SPEED_NUM_NONE;
 713         link->link_duplex = ETH_LINK_FULL_DUPLEX;
 714
 715         return 0;
 716 }
 717
 718 static int ena_queue_restart_all(struct rte_eth_dev *dev,
 719                                  enum ena_ring_type ring_type)
 720 {
 721         struct ena_adapter *adapter =
 722                 (struct ena_adapter *)(dev->data->dev_private);
 723         struct ena_ring *queues = NULL;
 724         int i = 0;
 725         int rc = 0;
 726
 727         queues = (ring_type == ENA_RING_TYPE_RX) ?
 728                 adapter->rx_ring : adapter->tx_ring;
 729
 730         for (i = 0; i < adapter->num_queues; i++) {
 731                 if (queues[i].configured) {
 732                         if (ring_type == ENA_RING_TYPE_RX) {
 733                                 ena_assert_msg(
 734                                         dev->data->rx_queues[i] == &queues[i],
 735                                         "Inconsistent state of rx queues\n");
 736                         } else {
 737                                 ena_assert_msg(
 738                                         dev->data->tx_queues[i] == &queues[i],
 739                                         "Inconsistent state of tx queues\n");
 740                         }
 741
 742                         rc = ena_queue_restart(&queues[i]);
 743
 744                         if (rc) {
 745                                 PMD_INIT_LOG(ERR,
 746                                              "failed to restart queue %d type(%d)",
 747                                              i, ring_type);
 748                                 return -1;
 749                         }
 750                 }
 751         }
 752
 753         return 0;
 754 }
 755
 756 static uint32_t ena_get_mtu_conf(struct ena_adapter *adapter)
 757 {
 758         uint32_t max_frame_len = adapter->max_mtu;
 759
 760         if (adapter->rte_eth_dev_data->dev_conf.rxmode.jumbo_frame == 1)
 761                 max_frame_len =
 762                         adapter->rte_eth_dev_data->dev_conf.rxmode.max_rx_pkt_len;
 763
 764         return max_frame_len;
 765 }
 766
 767 static int ena_check_valid_conf(struct ena_adapter *adapter)
 768 {
 769         uint32_t max_frame_len = ena_get_mtu_conf(adapter);
 770
 771         if (max_frame_len > adapter->max_mtu) {
 772                 PMD_INIT_LOG(ERR, "Unsupported MTU of %d", max_frame_len);
 773                 return -1;
 774         }
 775
 776         return 0;
 777 }
 778
 779 static int
 780 ena_calc_queue_size(struct ena_com_dev *ena_dev,
 781                     struct ena_com_dev_get_features_ctx *get_feat_ctx)
 782 {
 783         uint32_t queue_size = ENA_DEFAULT_RING_SIZE;
 784
 785         queue_size = RTE_MIN(queue_size,
 786                              get_feat_ctx->max_queues.max_cq_depth);
 787         queue_size = RTE_MIN(queue_size,
 788                              get_feat_ctx->max_queues.max_sq_depth);
 789
 790         if (ena_dev->tx_mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_DEV)
 791                 queue_size = RTE_MIN(queue_size,
 792                                      get_feat_ctx->max_queues.max_llq_depth);
 793
 794         /* Round down to power of 2 */
 795         if (!rte_is_power_of_2(queue_size))
 796                 queue_size = rte_align32pow2(queue_size >> 1);
 797
 798         if (queue_size == 0) {
 799                 PMD_INIT_LOG(ERR, "Invalid queue size");
 800                 return -EFAULT;
 801         }
 802
 803         return queue_size;
 804 }
 805
 806 static void ena_stats_restart(struct rte_eth_dev *dev)
 807 {
 808         struct ena_adapter *adapter =
 809                 (struct ena_adapter *)(dev->data->dev_private);
 810
 811         rte_atomic64_init(&adapter->drv_stats->ierrors);
 812         rte_atomic64_init(&adapter->drv_stats->oerrors);
 813         rte_atomic64_init(&adapter->drv_stats->rx_nombuf);
 814 }
 815
 816 static int ena_stats_get(struct rte_eth_dev *dev,
 817                           struct rte_eth_stats *stats)
 818 {
 819         struct ena_admin_basic_stats ena_stats;
 820         struct ena_adapter *adapter =
 821                 (struct ena_adapter *)(dev->data->dev_private);
 822         struct ena_com_dev *ena_dev = &adapter->ena_dev;
 823         int rc;
 824
 825         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
 826                 return -ENOTSUP;
 827
 828         memset(&ena_stats, 0, sizeof(ena_stats));
 829         rc = ena_com_get_dev_basic_stats(ena_dev, &ena_stats);
 830         if (unlikely(rc)) {
 831                 RTE_LOG(ERR, PMD, "Could not retrieve statistics from ENA");
 832                 return rc;
 833         }
 834
 835         /* Set of basic statistics from ENA */
 836         stats->ipackets = __MERGE_64B_H_L(ena_stats.rx_pkts_high,
 837                                           ena_stats.rx_pkts_low);
 838         stats->opackets = __MERGE_64B_H_L(ena_stats.tx_pkts_high,
 839                                           ena_stats.tx_pkts_low);
 840         stats->ibytes = __MERGE_64B_H_L(ena_stats.rx_bytes_high,
 841                                         ena_stats.rx_bytes_low);
 842         stats->obytes = __MERGE_64B_H_L(ena_stats.tx_bytes_high,
 843                                         ena_stats.tx_bytes_low);
 844         stats->imissed = __MERGE_64B_H_L(ena_stats.rx_drops_high,
 845                                          ena_stats.rx_drops_low);
 846
 847         /* Driver related stats */
 848         stats->ierrors = rte_atomic64_read(&adapter->drv_stats->ierrors);
 849         stats->oerrors = rte_atomic64_read(&adapter->drv_stats->oerrors);
 850         stats->rx_nombuf = rte_atomic64_read(&adapter->drv_stats->rx_nombuf);
 851         return 0;
 852 }
 853
 854 static int ena_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
 855 {
 856         struct ena_adapter *adapter;
 857         struct ena_com_dev *ena_dev;
 858         int rc = 0;
 859
 860         ena_assert_msg(dev->data != NULL, "Uninitialized device");
 861         ena_assert_msg(dev->data->dev_private != NULL, "Uninitialized device");
 862         adapter = (struct ena_adapter *)(dev->data->dev_private);
 863
 864         ena_dev = &adapter->ena_dev;
 865         ena_assert_msg(ena_dev != NULL, "Uninitialized device");
 866
 867         if (mtu > ena_get_mtu_conf(adapter)) {
 868                 RTE_LOG(ERR, PMD,
 869                         "Given MTU (%d) exceeds maximum MTU supported (%d)\n",
 870                         mtu, ena_get_mtu_conf(adapter));
 871                 rc = -EINVAL;
 872                 goto err;
 873         }
 874
 875         rc = ena_com_set_dev_mtu(ena_dev, mtu);
 876         if (rc)
 877                 RTE_LOG(ERR, PMD, "Could not set MTU: %d\n", mtu);
 878         else
 879                 RTE_LOG(NOTICE, PMD, "Set MTU: %d\n", mtu);
 880
 881 err:
 882         return rc;
 883 }
 884
 885 static int ena_start(struct rte_eth_dev *dev)
 886 {
 887         struct ena_adapter *adapter =
 888                 (struct ena_adapter *)(dev->data->dev_private);
 889         int rc = 0;
 890
 891         if (!(adapter->state == ENA_ADAPTER_STATE_CONFIG ||
 892               adapter->state == ENA_ADAPTER_STATE_STOPPED)) {
 893                 PMD_INIT_LOG(ERR, "API violation");
 894                 return -1;
 895         }
 896
 897         rc = ena_check_valid_conf(adapter);
 898         if (rc)
 899                 return rc;
 900
 901         rc = ena_queue_restart_all(dev, ENA_RING_TYPE_RX);
 902         if (rc)
 903                 return rc;
 904
 905         rc = ena_queue_restart_all(dev, ENA_RING_TYPE_TX);
 906         if (rc)
 907                 return rc;
 908
 909         if (adapter->rte_dev->data->dev_conf.rxmode.mq_mode &
 910             ETH_MQ_RX_RSS_FLAG && adapter->rte_dev->data->nb_rx_queues > 0) {
 911                 rc = ena_rss_init_default(adapter);
 912                 if (rc)
 913                         return rc;
 914         }
 915
 916         ena_stats_restart(dev);
 917
 918         adapter->state = ENA_ADAPTER_STATE_RUNNING;
 919
 920         return 0;
 921 }
 922
 923 static int ena_queue_restart(struct ena_ring *ring)
 924 {
 925         int rc, bufs_num;
 926
 927         ena_assert_msg(ring->configured == 1,
 928                        "Trying to restart unconfigured queue\n");
 929
 930         ring->next_to_clean = 0;
 931         ring->next_to_use = 0;
 932
 933         if (ring->type == ENA_RING_TYPE_TX)
 934                 return 0;
 935
 936         bufs_num = ring->ring_size - 1;
 937         rc = ena_populate_rx_queue(ring, bufs_num);
 938         if (rc != bufs_num) {
 939                 PMD_INIT_LOG(ERR, "Failed to populate rx ring !");
 940                 return (-1);
 941         }
 942
 943         return 0;
 944 }
 945
 946 static int ena_tx_queue_setup(struct rte_eth_dev *dev,
 947                               uint16_t queue_idx,
 948                               uint16_t nb_desc,
 949                               __rte_unused unsigned int socket_id,
 950                               __rte_unused const struct rte_eth_txconf *tx_conf)
 951 {
 952         struct ena_com_create_io_ctx ctx =
 953                 /* policy set to _HOST just to satisfy icc compiler */
 954                 { ENA_ADMIN_PLACEMENT_POLICY_HOST,
 955                   ENA_COM_IO_QUEUE_DIRECTION_TX, 0, 0, 0, 0 };
 956         struct ena_ring *txq = NULL;
 957         struct ena_adapter *adapter =
 958                 (struct ena_adapter *)(dev->data->dev_private);
 959         unsigned int i;
 960         int ena_qid;
 961         int rc;
 962         struct ena_com_dev *ena_dev = &adapter->ena_dev;
 963
 964         txq = &adapter->tx_ring[queue_idx];
 965
 966         if (txq->configured) {
 967                 RTE_LOG(CRIT, PMD,
 968                         "API violation. Queue %d is already configured\n",
 969                         queue_idx);
 970                 return -1;
 971         }
 972
 973         if (!rte_is_power_of_2(nb_desc)) {
 974                 RTE_LOG(ERR, PMD,
 975                         "Unsupported size of RX queue: %d is not a power of 2.",
 976                         nb_desc);
 977                 return -EINVAL;
 978         }
 979
 980         if (nb_desc > adapter->tx_ring_size) {
 981                 RTE_LOG(ERR, PMD,
 982                         "Unsupported size of TX queue (max size: %d)\n",
 983                         adapter->tx_ring_size);
 984                 return -EINVAL;
 985         }
 986
 987         ena_qid = ENA_IO_TXQ_IDX(queue_idx);
 988
 989         ctx.direction = ENA_COM_IO_QUEUE_DIRECTION_TX;
 990         ctx.qid = ena_qid;
 991         ctx.msix_vector = -1; /* admin interrupts not used */
 992         ctx.mem_queue_type = ena_dev->tx_mem_queue_type;
 993         ctx.queue_size = adapter->tx_ring_size;
 994         ctx.numa_node = ena_cpu_to_node(queue_idx);
 995
 996         rc = ena_com_create_io_queue(ena_dev, &ctx);
 997         if (rc) {
 998                 RTE_LOG(ERR, PMD,
 999                         "failed to create io TX queue #%d (qid:%d) rc: %d\n",
1000                         queue_idx, ena_qid, rc);
1001         }
1002         txq->ena_com_io_cq = &ena_dev->io_cq_queues[ena_qid];
1003         txq->ena_com_io_sq = &ena_dev->io_sq_queues[ena_qid];
1004
1005         rc = ena_com_get_io_handlers(ena_dev, ena_qid,
1006                                      &txq->ena_com_io_sq,
1007                                      &txq->ena_com_io_cq);
1008         if (rc) {
1009                 RTE_LOG(ERR, PMD,
1010                         "Failed to get TX queue handlers. TX queue num %d rc: %d\n",
1011                         queue_idx, rc);
1012                 ena_com_destroy_io_queue(ena_dev, ena_qid);
1013                 goto err;
1014         }
1015
1016         txq->port_id = dev->data->port_id;
1017         txq->next_to_clean = 0;
1018         txq->next_to_use = 0;
1019         txq->ring_size = nb_desc;
1020
1021         txq->tx_buffer_info = rte_zmalloc("txq->tx_buffer_info",
1022                                           sizeof(struct ena_tx_buffer) *
1023                                           txq->ring_size,
1024                                           RTE_CACHE_LINE_SIZE);
1025         if (!txq->tx_buffer_info) {
1026                 RTE_LOG(ERR, PMD, "failed to alloc mem for tx buffer info\n");
1027                 return -ENOMEM;
1028         }
1029
1030         txq->empty_tx_reqs = rte_zmalloc("txq->empty_tx_reqs",
1031                                          sizeof(u16) * txq->ring_size,
1032                                          RTE_CACHE_LINE_SIZE);
1033         if (!txq->empty_tx_reqs) {
1034                 RTE_LOG(ERR, PMD, "failed to alloc mem for tx reqs\n");
1035                 rte_free(txq->tx_buffer_info);
1036                 return -ENOMEM;
1037         }
1038         for (i = 0; i < txq->ring_size; i++)
1039                 txq->empty_tx_reqs[i] = i;
1040
1041         /* Store pointer to this queue in upper layer */
1042         txq->configured = 1;
1043         dev->data->tx_queues[queue_idx] = txq;
1044 err:
1045         return rc;
1046 }
1047
1048 static int ena_rx_queue_setup(struct rte_eth_dev *dev,
1049                               uint16_t queue_idx,
1050                               uint16_t nb_desc,
1051                               __rte_unused unsigned int socket_id,
1052                               __rte_unused const struct rte_eth_rxconf *rx_conf,
1053                               struct rte_mempool *mp)
1054 {
1055         struct ena_com_create_io_ctx ctx =
1056                 /* policy set to _HOST just to satisfy icc compiler */
1057                 { ENA_ADMIN_PLACEMENT_POLICY_HOST,
1058                   ENA_COM_IO_QUEUE_DIRECTION_RX, 0, 0, 0, 0 };
1059         struct ena_adapter *adapter =
1060                 (struct ena_adapter *)(dev->data->dev_private);
1061         struct ena_ring *rxq = NULL;
1062         uint16_t ena_qid = 0;
1063         int rc = 0;
1064         struct ena_com_dev *ena_dev = &adapter->ena_dev;
1065
1066         rxq = &adapter->rx_ring[queue_idx];
1067         if (rxq->configured) {
1068                 RTE_LOG(CRIT, PMD,
1069                         "API violation. Queue %d is already configured\n",
1070                         queue_idx);
1071                 return -1;
1072         }
1073
1074         if (!rte_is_power_of_2(nb_desc)) {
1075                 RTE_LOG(ERR, PMD,
1076                         "Unsupported size of TX queue: %d is not a power of 2.",
1077                         nb_desc);
1078                 return -EINVAL;
1079         }
1080
1081         if (nb_desc > adapter->rx_ring_size) {
1082                 RTE_LOG(ERR, PMD,
1083                         "Unsupported size of RX queue (max size: %d)\n",
1084                         adapter->rx_ring_size);
1085                 return -EINVAL;
1086         }
1087
1088         ena_qid = ENA_IO_RXQ_IDX(queue_idx);
1089
1090         ctx.qid = ena_qid;
1091         ctx.direction = ENA_COM_IO_QUEUE_DIRECTION_RX;
1092         ctx.mem_queue_type = ENA_ADMIN_PLACEMENT_POLICY_HOST;
1093         ctx.msix_vector = -1; /* admin interrupts not used */
1094         ctx.queue_size = adapter->rx_ring_size;
1095         ctx.numa_node = ena_cpu_to_node(queue_idx);
1096
1097         rc = ena_com_create_io_queue(ena_dev, &ctx);
1098         if (rc)
1099                 RTE_LOG(ERR, PMD, "failed to create io RX queue #%d rc: %d\n",
1100                         queue_idx, rc);
1101
1102         rxq->ena_com_io_cq = &ena_dev->io_cq_queues[ena_qid];
1103         rxq->ena_com_io_sq = &ena_dev->io_sq_queues[ena_qid];
1104
1105         rc = ena_com_get_io_handlers(ena_dev, ena_qid,
1106                                      &rxq->ena_com_io_sq,
1107                                      &rxq->ena_com_io_cq);
1108         if (rc) {
1109                 RTE_LOG(ERR, PMD,
1110                         "Failed to get RX queue handlers. RX queue num %d rc: %d\n",
1111                         queue_idx, rc);
1112                 ena_com_destroy_io_queue(ena_dev, ena_qid);
1113         }
1114
1115         rxq->port_id = dev->data->port_id;
1116         rxq->next_to_clean = 0;
1117         rxq->next_to_use = 0;
1118         rxq->ring_size = nb_desc;
1119         rxq->mb_pool = mp;
1120
1121         rxq->rx_buffer_info = rte_zmalloc("rxq->buffer_info",
1122                                           sizeof(struct rte_mbuf *) * nb_desc,
1123                                           RTE_CACHE_LINE_SIZE);
1124         if (!rxq->rx_buffer_info) {
1125                 RTE_LOG(ERR, PMD, "failed to alloc mem for rx buffer info\n");
1126                 return -ENOMEM;
1127         }
1128
1129         /* Store pointer to this queue in upper layer */
1130         rxq->configured = 1;
1131         dev->data->rx_queues[queue_idx] = rxq;
1132
1133         return rc;
1134 }
1135
1136 static int ena_populate_rx_queue(struct ena_ring *rxq, unsigned int count)
1137 {
1138         unsigned int i;
1139         int rc;
1140         uint16_t ring_size = rxq->ring_size;
1141         uint16_t ring_mask = ring_size - 1;
1142         uint16_t next_to_use = rxq->next_to_use;
1143         uint16_t in_use;
1144         struct rte_mbuf **mbufs = &rxq->rx_buffer_info[0];
1145
1146         if (unlikely(!count))
1147                 return 0;
1148
1149         in_use = rxq->next_to_use - rxq->next_to_clean;
1150         ena_assert_msg(((in_use + count) < ring_size), "bad ring state");
1151
1152         count = RTE_MIN(count,
1153                         (uint16_t)(ring_size - (next_to_use & ring_mask)));
1154
1155         /* get resources for incoming packets */
1156         rc = rte_mempool_get_bulk(rxq->mb_pool,
1157                                   (void **)(&mbufs[next_to_use & ring_mask]),
1158                                   count);
1159         if (unlikely(rc < 0)) {
1160                 rte_atomic64_inc(&rxq->adapter->drv_stats->rx_nombuf);
1161                 PMD_RX_LOG(DEBUG, "there are no enough free buffers");
1162                 return 0;
1163         }
1164
1165         for (i = 0; i < count; i++) {
1166                 uint16_t next_to_use_masked = next_to_use & ring_mask;
1167                 struct rte_mbuf *mbuf = mbufs[next_to_use_masked];
1168                 struct ena_com_buf ebuf;
1169
1170                 rte_prefetch0(mbufs[((next_to_use + 4) & ring_mask)]);
1171                 /* prepare physical address for DMA transaction */
1172                 ebuf.paddr = mbuf->buf_iova + RTE_PKTMBUF_HEADROOM;
1173                 ebuf.len = mbuf->buf_len - RTE_PKTMBUF_HEADROOM;
1174                 /* pass resource to device */
1175                 rc = ena_com_add_single_rx_desc(rxq->ena_com_io_sq,
1176                                                 &ebuf, next_to_use_masked);
1177                 if (unlikely(rc)) {
1178                         rte_mempool_put_bulk(rxq->mb_pool, (void **)(&mbuf),
1179                                              count - i);
1180                         RTE_LOG(WARNING, PMD, "failed adding rx desc\n");
1181                         break;
1182                 }
1183                 next_to_use++;
1184         }
1185
1186         /* When we submitted free recources to device... */
1187         if (i > 0) {
1188                 /* ...let HW know that it can fill buffers with data */
1189                 rte_wmb();
1190                 ena_com_write_sq_doorbell(rxq->ena_com_io_sq);
1191
1192                 rxq->next_to_use = next_to_use;
1193         }
1194
1195         return i;
1196 }
1197
1198 static int ena_device_init(struct ena_com_dev *ena_dev,
1199                            struct ena_com_dev_get_features_ctx *get_feat_ctx)
1200 {
1201         int rc;
1202         bool readless_supported;
1203
1204         /* Initialize mmio registers */
1205         rc = ena_com_mmio_reg_read_request_init(ena_dev);
1206         if (rc) {
1207                 RTE_LOG(ERR, PMD, "failed to init mmio read less\n");
1208                 return rc;
1209         }
1210
1211         /* The PCIe configuration space revision id indicate if mmio reg
1212          * read is disabled.
1213          */
1214         readless_supported =
1215                 !(((struct rte_pci_device *)ena_dev->dmadev)->id.class_id
1216                                & ENA_MMIO_DISABLE_REG_READ);
1217         ena_com_set_mmio_read_mode(ena_dev, readless_supported);
1218
1219         /* reset device */
1220         rc = ena_com_dev_reset(ena_dev);
1221         if (rc) {
1222                 RTE_LOG(ERR, PMD, "cannot reset device\n");
1223                 goto err_mmio_read_less;
1224         }
1225
1226         /* check FW version */
1227         rc = ena_com_validate_version(ena_dev);
1228         if (rc) {
1229                 RTE_LOG(ERR, PMD, "device version is too low\n");
1230                 goto err_mmio_read_less;
1231         }
1232
1233         ena_dev->dma_addr_bits = ena_com_get_dma_width(ena_dev);
1234
1235         /* ENA device administration layer init */
1236         rc = ena_com_admin_init(ena_dev, NULL, true);
1237         if (rc) {
1238                 RTE_LOG(ERR, PMD,
1239                         "cannot initialize ena admin queue with device\n");
1240                 goto err_mmio_read_less;
1241         }
1242
1243         /* To enable the msix interrupts the driver needs to know the number
1244          * of queues. So the driver uses polling mode to retrieve this
1245          * information.
1246          */
1247         ena_com_set_admin_polling_mode(ena_dev, true);
1248
1249         ena_config_host_info(ena_dev);
1250
1251         /* Get Device Attributes and features */
1252         rc = ena_com_get_dev_attr_feat(ena_dev, get_feat_ctx);
1253         if (rc) {
1254                 RTE_LOG(ERR, PMD,
1255                         "cannot get attribute for ena device rc= %d\n", rc);
1256                 goto err_admin_init;
1257         }
1258
1259         return 0;
1260
1261 err_admin_init:
1262         ena_com_admin_destroy(ena_dev);
1263
1264 err_mmio_read_less:
1265         ena_com_mmio_reg_read_request_destroy(ena_dev);
1266
1267         return rc;
1268 }
1269
1270 static int eth_ena_dev_init(struct rte_eth_dev *eth_dev)
1271 {
1272         struct rte_pci_device *pci_dev;
1273         struct ena_adapter *adapter =
1274                 (struct ena_adapter *)(eth_dev->data->dev_private);
1275         struct ena_com_dev *ena_dev = &adapter->ena_dev;
1276         struct ena_com_dev_get_features_ctx get_feat_ctx;
1277         int queue_size, rc;
1278
1279         static int adapters_found;
1280
1281         memset(adapter, 0, sizeof(struct ena_adapter));
1282         ena_dev = &adapter->ena_dev;
1283
1284         eth_dev->dev_ops = &ena_dev_ops;
1285         eth_dev->rx_pkt_burst = &eth_ena_recv_pkts;
1286         eth_dev->tx_pkt_burst = &eth_ena_xmit_pkts;
1287         eth_dev->tx_pkt_prepare = &eth_ena_prep_pkts;
1288         adapter->rte_eth_dev_data = eth_dev->data;
1289         adapter->rte_dev = eth_dev;
1290
1291         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1292                 return 0;
1293
1294         pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1295         adapter->pdev = pci_dev;
1296
1297         PMD_INIT_LOG(INFO, "Initializing %x:%x:%x.%d",
1298                      pci_dev->addr.domain,
1299                      pci_dev->addr.bus,
1300                      pci_dev->addr.devid,
1301                      pci_dev->addr.function);
1302
1303         adapter->regs = pci_dev->mem_resource[ENA_REGS_BAR].addr;
1304         adapter->dev_mem_base = pci_dev->mem_resource[ENA_MEM_BAR].addr;
1305
1306         /* Present ENA_MEM_BAR indicates available LLQ mode.
1307          * Use corresponding policy
1308          */
1309         if (adapter->dev_mem_base)
1310                 ena_dev->tx_mem_queue_type = ENA_ADMIN_PLACEMENT_POLICY_DEV;
1311         else if (adapter->regs)
1312                 ena_dev->tx_mem_queue_type = ENA_ADMIN_PLACEMENT_POLICY_HOST;
1313         else
1314                 PMD_INIT_LOG(CRIT, "Failed to access registers BAR(%d)",
1315                              ENA_REGS_BAR);
1316
1317         ena_dev->reg_bar = adapter->regs;
1318         ena_dev->dmadev = adapter->pdev;
1319
1320         adapter->id_number = adapters_found;
1321
1322         snprintf(adapter->name, ENA_NAME_MAX_LEN, "ena_%d",
1323                  adapter->id_number);
1324
1325         /* device specific initialization routine */
1326         rc = ena_device_init(ena_dev, &get_feat_ctx);
1327         if (rc) {
1328                 PMD_INIT_LOG(CRIT, "Failed to init ENA device");
1329                 return -1;
1330         }
1331
1332         if (ena_dev->tx_mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_DEV) {
1333                 if (get_feat_ctx.max_queues.max_llq_num == 0) {
1334                         PMD_INIT_LOG(ERR,
1335                                      "Trying to use LLQ but llq_num is 0.\n"
1336                                      "Fall back into regular queues.");
1337                         ena_dev->tx_mem_queue_type =
1338                                 ENA_ADMIN_PLACEMENT_POLICY_HOST;
1339                         adapter->num_queues =
1340                                 get_feat_ctx.max_queues.max_sq_num;
1341                 } else {
1342                         adapter->num_queues =
1343                                 get_feat_ctx.max_queues.max_llq_num;
1344                 }
1345         } else {
1346                 adapter->num_queues = get_feat_ctx.max_queues.max_sq_num;
1347         }
1348
1349         queue_size = ena_calc_queue_size(ena_dev, &get_feat_ctx);
1350         if ((queue_size <= 0) || (adapter->num_queues <= 0))
1351                 return -EFAULT;
1352
1353         adapter->tx_ring_size = queue_size;
1354         adapter->rx_ring_size = queue_size;
1355
1356         /* prepare ring structures */
1357         ena_init_rings(adapter);
1358
1359         ena_config_debug_area(adapter);
1360
1361         /* Set max MTU for this device */
1362         adapter->max_mtu = get_feat_ctx.dev_attr.max_mtu;
1363
1364         /* set device support for TSO */
1365         adapter->tso4_supported = get_feat_ctx.offload.tx &
1366                                   ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_IPV4_MASK;
1367
1368         /* Copy MAC address and point DPDK to it */
1369         eth_dev->data->mac_addrs = (struct ether_addr *)adapter->mac_addr;
1370         ether_addr_copy((struct ether_addr *)get_feat_ctx.dev_attr.mac_addr,
1371                         (struct ether_addr *)adapter->mac_addr);
1372
1373         adapter->drv_stats = rte_zmalloc("adapter stats",
1374                                          sizeof(*adapter->drv_stats),
1375                                          RTE_CACHE_LINE_SIZE);
1376         if (!adapter->drv_stats) {
1377                 RTE_LOG(ERR, PMD, "failed to alloc mem for adapter stats\n");
1378                 return -ENOMEM;
1379         }
1380
1381         adapters_found++;
1382         adapter->state = ENA_ADAPTER_STATE_INIT;
1383
1384         return 0;
1385 }
1386
1387 static int ena_dev_configure(struct rte_eth_dev *dev)
1388 {
1389         struct ena_adapter *adapter =
1390                 (struct ena_adapter *)(dev->data->dev_private);
1391
1392         if (!(adapter->state == ENA_ADAPTER_STATE_INIT ||
1393               adapter->state == ENA_ADAPTER_STATE_STOPPED)) {
1394                 PMD_INIT_LOG(ERR, "Illegal adapter state: %d",
1395                              adapter->state);
1396                 return -1;
1397         }
1398
1399         switch (adapter->state) {
1400         case ENA_ADAPTER_STATE_INIT:
1401         case ENA_ADAPTER_STATE_STOPPED:
1402                 adapter->state = ENA_ADAPTER_STATE_CONFIG;
1403                 break;
1404         case ENA_ADAPTER_STATE_CONFIG:
1405                 RTE_LOG(WARNING, PMD,
1406                         "Ivalid driver state while trying to configure device\n");
1407                 break;
1408         default:
1409                 break;
1410         }
1411
1412         return 0;
1413 }
1414
1415 static void ena_init_rings(struct ena_adapter *adapter)
1416 {
1417         int i;
1418
1419         for (i = 0; i < adapter->num_queues; i++) {
1420                 struct ena_ring *ring = &adapter->tx_ring[i];
1421
1422                 ring->configured = 0;
1423                 ring->type = ENA_RING_TYPE_TX;
1424                 ring->adapter = adapter;
1425                 ring->id = i;
1426                 ring->tx_mem_queue_type = adapter->ena_dev.tx_mem_queue_type;
1427                 ring->tx_max_header_size = adapter->ena_dev.tx_max_header_size;
1428         }
1429
1430         for (i = 0; i < adapter->num_queues; i++) {
1431                 struct ena_ring *ring = &adapter->rx_ring[i];
1432
1433                 ring->configured = 0;
1434                 ring->type = ENA_RING_TYPE_RX;
1435                 ring->adapter = adapter;
1436                 ring->id = i;
1437         }
1438 }
1439
1440 static void ena_infos_get(struct rte_eth_dev *dev,
1441                           struct rte_eth_dev_info *dev_info)
1442 {
1443         struct ena_adapter *adapter;
1444         struct ena_com_dev *ena_dev;
1445         struct ena_com_dev_get_features_ctx feat;
1446         uint32_t rx_feat = 0, tx_feat = 0;
1447         int rc = 0;
1448
1449         ena_assert_msg(dev->data != NULL, "Uninitialized device");
1450         ena_assert_msg(dev->data->dev_private != NULL, "Uninitialized device");
1451         adapter = (struct ena_adapter *)(dev->data->dev_private);
1452
1453         ena_dev = &adapter->ena_dev;
1454         ena_assert_msg(ena_dev != NULL, "Uninitialized device");
1455
1456         dev_info->pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1457
1458         dev_info->speed_capa =
1459                         ETH_LINK_SPEED_1G   |
1460                         ETH_LINK_SPEED_2_5G |
1461                         ETH_LINK_SPEED_5G   |
1462                         ETH_LINK_SPEED_10G  |
1463                         ETH_LINK_SPEED_25G  |
1464                         ETH_LINK_SPEED_40G  |
1465                         ETH_LINK_SPEED_50G  |
1466                         ETH_LINK_SPEED_100G;
1467
1468         /* Get supported features from HW */
1469         rc = ena_com_get_dev_attr_feat(ena_dev, &feat);
1470         if (unlikely(rc)) {
1471                 RTE_LOG(ERR, PMD,
1472                         "Cannot get attribute for ena device rc= %d\n", rc);
1473                 return;
1474         }
1475
1476         /* Set Tx & Rx features available for device */
1477         if (feat.offload.tx & ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_IPV4_MASK)
1478                 tx_feat |= DEV_TX_OFFLOAD_TCP_TSO;
1479
1480         if (feat.offload.tx &
1481             ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV4_CSUM_PART_MASK)
1482                 tx_feat |= DEV_TX_OFFLOAD_IPV4_CKSUM |
1483                         DEV_TX_OFFLOAD_UDP_CKSUM |
1484                         DEV_TX_OFFLOAD_TCP_CKSUM;
1485
1486         if (feat.offload.rx_supported &
1487             ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L4_IPV4_CSUM_MASK)
1488                 rx_feat |= DEV_RX_OFFLOAD_IPV4_CKSUM |
1489                         DEV_RX_OFFLOAD_UDP_CKSUM  |
1490                         DEV_RX_OFFLOAD_TCP_CKSUM;
1491
1492         /* Inform framework about available features */
1493         dev_info->rx_offload_capa = rx_feat;
1494         dev_info->tx_offload_capa = tx_feat;
1495
1496         dev_info->min_rx_bufsize = ENA_MIN_FRAME_LEN;
1497         dev_info->max_rx_pktlen  = adapter->max_mtu;
1498         dev_info->max_mac_addrs = 1;
1499
1500         dev_info->max_rx_queues = adapter->num_queues;
1501         dev_info->max_tx_queues = adapter->num_queues;
1502         dev_info->reta_size = ENA_RX_RSS_TABLE_SIZE;
1503 }
1504
1505 static uint16_t eth_ena_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,
1506                                   uint16_t nb_pkts)
1507 {
1508         struct ena_ring *rx_ring = (struct ena_ring *)(rx_queue);
1509         unsigned int ring_size = rx_ring->ring_size;
1510         unsigned int ring_mask = ring_size - 1;
1511         uint16_t next_to_clean = rx_ring->next_to_clean;
1512         uint16_t desc_in_use = 0;
1513         unsigned int recv_idx = 0;
1514         struct rte_mbuf *mbuf = NULL;
1515         struct rte_mbuf *mbuf_head = NULL;
1516         struct rte_mbuf *mbuf_prev = NULL;
1517         struct rte_mbuf **rx_buff_info = rx_ring->rx_buffer_info;
1518         unsigned int completed;
1519
1520         struct ena_com_rx_ctx ena_rx_ctx;
1521         int rc = 0;
1522
1523         /* Check adapter state */
1524         if (unlikely(rx_ring->adapter->state != ENA_ADAPTER_STATE_RUNNING)) {
1525                 RTE_LOG(ALERT, PMD,
1526                         "Trying to receive pkts while device is NOT running\n");
1527                 return 0;
1528         }
1529
1530         desc_in_use = rx_ring->next_to_use - next_to_clean;
1531         if (unlikely(nb_pkts > desc_in_use))
1532                 nb_pkts = desc_in_use;
1533
1534         for (completed = 0; completed < nb_pkts; completed++) {
1535                 int segments = 0;
1536
1537                 ena_rx_ctx.max_bufs = rx_ring->ring_size;
1538                 ena_rx_ctx.ena_bufs = rx_ring->ena_bufs;
1539                 ena_rx_ctx.descs = 0;
1540                 /* receive packet context */
1541                 rc = ena_com_rx_pkt(rx_ring->ena_com_io_cq,
1542                                     rx_ring->ena_com_io_sq,
1543                                     &ena_rx_ctx);
1544                 if (unlikely(rc)) {
1545                         RTE_LOG(ERR, PMD, "ena_com_rx_pkt error %d\n", rc);
1546                         return 0;
1547                 }
1548
1549                 if (unlikely(ena_rx_ctx.descs == 0))
1550                         break;
1551
1552                 while (segments < ena_rx_ctx.descs) {
1553                         mbuf = rx_buff_info[next_to_clean & ring_mask];
1554                         mbuf->data_len = ena_rx_ctx.ena_bufs[segments].len;
1555                         mbuf->data_off = RTE_PKTMBUF_HEADROOM;
1556                         mbuf->refcnt = 1;
1557                         mbuf->next = NULL;
1558                         if (segments == 0) {
1559                                 mbuf->nb_segs = ena_rx_ctx.descs;
1560                                 mbuf->port = rx_ring->port_id;
1561                                 mbuf->pkt_len = 0;
1562                                 mbuf_head = mbuf;
1563                         } else {
1564                                 /* for multi-segment pkts create mbuf chain */
1565                                 mbuf_prev->next = mbuf;
1566                         }
1567                         mbuf_head->pkt_len += mbuf->data_len;
1568
1569                         mbuf_prev = mbuf;
1570                         segments++;
1571                         next_to_clean++;
1572                 }
1573
1574                 /* fill mbuf attributes if any */
1575                 ena_rx_mbuf_prepare(mbuf_head, &ena_rx_ctx);
1576                 mbuf_head->hash.rss = (uint32_t)rx_ring->id;
1577
1578                 /* pass to DPDK application head mbuf */
1579                 rx_pkts[recv_idx] = mbuf_head;
1580                 recv_idx++;
1581         }
1582
1583         rx_ring->next_to_clean = next_to_clean;
1584
1585         desc_in_use = desc_in_use - completed + 1;
1586         /* Burst refill to save doorbells, memory barriers, const interval */
1587         if (ring_size - desc_in_use > ENA_RING_DESCS_RATIO(ring_size))
1588                 ena_populate_rx_queue(rx_ring, ring_size - desc_in_use);
1589
1590         return recv_idx;
1591 }
1592
1593 static uint16_t
1594 eth_ena_prep_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
1595                 uint16_t nb_pkts)
1596 {
1597         int32_t ret;
1598         uint32_t i;
1599         struct rte_mbuf *m;
1600         struct ena_ring *tx_ring = (struct ena_ring *)(tx_queue);
1601         struct ipv4_hdr *ip_hdr;
1602         uint64_t ol_flags;
1603         uint16_t frag_field;
1604
1605         for (i = 0; i != nb_pkts; i++) {
1606                 m = tx_pkts[i];
1607                 ol_flags = m->ol_flags;
1608
1609                 if (!(ol_flags & PKT_TX_IPV4))
1610                         continue;
1611
1612                 /* If there was not L2 header length specified, assume it is
1613                  * length of the ethernet header.
1614                  */
1615                 if (unlikely(m->l2_len == 0))
1616                         m->l2_len = sizeof(struct ether_hdr);
1617
1618                 ip_hdr = rte_pktmbuf_mtod_offset(m, struct ipv4_hdr *,
1619                                                  m->l2_len);
1620                 frag_field = rte_be_to_cpu_16(ip_hdr->fragment_offset);
1621
1622                 if ((frag_field & IPV4_HDR_DF_FLAG) != 0) {
1623                         m->packet_type |= RTE_PTYPE_L4_NONFRAG;
1624
1625                         /* If IPv4 header has DF flag enabled and TSO support is
1626                          * disabled, partial chcecksum should not be calculated.
1627                          */
1628                         if (!tx_ring->adapter->tso4_supported)
1629                                 continue;
1630                 }
1631
1632                 if ((ol_flags & ENA_TX_OFFLOAD_NOTSUP_MASK) != 0 ||
1633                                 (ol_flags & PKT_TX_L4_MASK) ==
1634                                 PKT_TX_SCTP_CKSUM) {
1635                         rte_errno = -ENOTSUP;
1636                         return i;
1637                 }
1638
1639 #ifdef RTE_LIBRTE_ETHDEV_DEBUG
1640                 ret = rte_validate_tx_offload(m);
1641                 if (ret != 0) {
1642                         rte_errno = ret;
1643                         return i;
1644                 }
1645 #endif
1646
1647                 /* In case we are supposed to TSO and have DF not set (DF=0)
1648                  * hardware must be provided with partial checksum, otherwise
1649                  * it will take care of necessary calculations.
1650                  */
1651
1652                 ret = rte_net_intel_cksum_flags_prepare(m,
1653                         ol_flags & ~PKT_TX_TCP_SEG);
1654                 if (ret != 0) {
1655                         rte_errno = ret;
1656                         return i;
1657                 }
1658         }
1659
1660         return i;
1661 }
1662
1663 static uint16_t eth_ena_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
1664                                   uint16_t nb_pkts)
1665 {
1666         struct ena_ring *tx_ring = (struct ena_ring *)(tx_queue);
1667         uint16_t next_to_use = tx_ring->next_to_use;
1668         uint16_t next_to_clean = tx_ring->next_to_clean;
1669         struct rte_mbuf *mbuf;
1670         unsigned int ring_size = tx_ring->ring_size;
1671         unsigned int ring_mask = ring_size - 1;
1672         struct ena_com_tx_ctx ena_tx_ctx;
1673         struct ena_tx_buffer *tx_info;
1674         struct ena_com_buf *ebuf;
1675         uint16_t rc, req_id, total_tx_descs = 0;
1676         uint16_t sent_idx = 0, empty_tx_reqs;
1677         int nb_hw_desc;
1678
1679         /* Check adapter state */
1680         if (unlikely(tx_ring->adapter->state != ENA_ADAPTER_STATE_RUNNING)) {
1681                 RTE_LOG(ALERT, PMD,
1682                         "Trying to xmit pkts while device is NOT running\n");
1683                 return 0;
1684         }
1685
1686         empty_tx_reqs = ring_size - (next_to_use - next_to_clean);
1687         if (nb_pkts > empty_tx_reqs)
1688                 nb_pkts = empty_tx_reqs;
1689
1690         for (sent_idx = 0; sent_idx < nb_pkts; sent_idx++) {
1691                 mbuf = tx_pkts[sent_idx];
1692
1693                 req_id = tx_ring->empty_tx_reqs[next_to_use & ring_mask];
1694                 tx_info = &tx_ring->tx_buffer_info[req_id];
1695                 tx_info->mbuf = mbuf;
1696                 tx_info->num_of_bufs = 0;
1697                 ebuf = tx_info->bufs;
1698
1699                 /* Prepare TX context */
1700                 memset(&ena_tx_ctx, 0x0, sizeof(struct ena_com_tx_ctx));
1701                 memset(&ena_tx_ctx.ena_meta, 0x0,
1702                        sizeof(struct ena_com_tx_meta));
1703                 ena_tx_ctx.ena_bufs = ebuf;
1704                 ena_tx_ctx.req_id = req_id;
1705                 if (tx_ring->tx_mem_queue_type ==
1706                                 ENA_ADMIN_PLACEMENT_POLICY_DEV) {
1707                         /* prepare the push buffer with
1708                          * virtual address of the data
1709                          */
1710                         ena_tx_ctx.header_len =
1711                                 RTE_MIN(mbuf->data_len,
1712                                         tx_ring->tx_max_header_size);
1713                         ena_tx_ctx.push_header =
1714                                 (void *)((char *)mbuf->buf_addr +
1715                                          mbuf->data_off);
1716                 } /* there's no else as we take advantage of memset zeroing */
1717
1718                 /* Set TX offloads flags, if applicable */
1719                 ena_tx_mbuf_prepare(mbuf, &ena_tx_ctx);
1720
1721                 if (unlikely(mbuf->ol_flags &
1722                              (PKT_RX_L4_CKSUM_BAD | PKT_RX_IP_CKSUM_BAD)))
1723                         rte_atomic64_inc(&tx_ring->adapter->drv_stats->ierrors);
1724
1725                 rte_prefetch0(tx_pkts[(sent_idx + 4) & ring_mask]);
1726
1727                 /* Process first segment taking into
1728                  * consideration pushed header
1729                  */
1730                 if (mbuf->data_len > ena_tx_ctx.header_len) {
1731                         ebuf->paddr = mbuf->buf_iova +
1732                                       mbuf->data_off +
1733                                       ena_tx_ctx.header_len;
1734                         ebuf->len = mbuf->data_len - ena_tx_ctx.header_len;
1735                         ebuf++;
1736                         tx_info->num_of_bufs++;
1737                 }
1738
1739                 while ((mbuf = mbuf->next) != NULL) {
1740                         ebuf->paddr = mbuf->buf_iova + mbuf->data_off;
1741                         ebuf->len = mbuf->data_len;
1742                         ebuf++;
1743                         tx_info->num_of_bufs++;
1744                 }
1745
1746                 ena_tx_ctx.num_bufs = tx_info->num_of_bufs;
1747
1748                 /* Write data to device */
1749                 rc = ena_com_prepare_tx(tx_ring->ena_com_io_sq,
1750                                         &ena_tx_ctx, &nb_hw_desc);
1751                 if (unlikely(rc))
1752                         break;
1753
1754                 tx_info->tx_descs = nb_hw_desc;
1755
1756                 next_to_use++;
1757         }
1758
1759         /* If there are ready packets to be xmitted... */
1760         if (sent_idx > 0) {
1761                 /* ...let HW do its best :-) */
1762                 rte_wmb();
1763                 ena_com_write_sq_doorbell(tx_ring->ena_com_io_sq);
1764
1765                 tx_ring->next_to_use = next_to_use;
1766         }
1767
1768         /* Clear complete packets  */
1769         while (ena_com_tx_comp_req_id_get(tx_ring->ena_com_io_cq, &req_id) >= 0) {
1770                 /* Get Tx info & store how many descs were processed  */
1771                 tx_info = &tx_ring->tx_buffer_info[req_id];
1772                 total_tx_descs += tx_info->tx_descs;
1773
1774                 /* Free whole mbuf chain  */
1775                 mbuf = tx_info->mbuf;
1776                 rte_pktmbuf_free(mbuf);
1777                 tx_info->mbuf = NULL;
1778
1779                 /* Put back descriptor to the ring for reuse */
1780                 tx_ring->empty_tx_reqs[next_to_clean & ring_mask] = req_id;
1781                 next_to_clean++;
1782
1783                 /* If too many descs to clean, leave it for another run */
1784                 if (unlikely(total_tx_descs > ENA_RING_DESCS_RATIO(ring_size)))
1785                         break;
1786         }
1787
1788         if (total_tx_descs > 0) {
1789                 /* acknowledge completion of sent packets */
1790                 ena_com_comp_ack(tx_ring->ena_com_io_sq, total_tx_descs);
1791                 tx_ring->next_to_clean = next_to_clean;
1792         }
1793
1794         return sent_idx;
1795 }
1796
1797 static int eth_ena_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
1798         struct rte_pci_device *pci_dev)
1799 {
1800         return rte_eth_dev_pci_generic_probe(pci_dev,
1801                 sizeof(struct ena_adapter), eth_ena_dev_init);
1802 }
1803
1804 static int eth_ena_pci_remove(struct rte_pci_device *pci_dev)
1805 {
1806         return rte_eth_dev_pci_generic_remove(pci_dev, NULL);
1807 }
1808
1809 static struct rte_pci_driver rte_ena_pmd = {
1810         .id_table = pci_id_ena_map,
1811         .drv_flags = RTE_PCI_DRV_NEED_MAPPING,
1812         .probe = eth_ena_pci_probe,
1813         .remove = eth_ena_pci_remove,
1814 };
1815
1816 RTE_PMD_REGISTER_PCI(net_ena, rte_ena_pmd);
1817 RTE_PMD_REGISTER_PCI_TABLE(net_ena, pci_id_ena_map);
1818 RTE_PMD_REGISTER_KMOD_DEP(net_ena, "* igb_uio | uio_pci_generic | vfio-pci");