drivers/net/ena/ena_ethdev.c

   1 /*-
   2 * BSD LICENSE
   3 *
   4 * Copyright (c) 2015-2016 Amazon.com, Inc. or its affiliates.
   5 * All rights reserved.
   6 *
   7 * Redistribution and use in source and binary forms, with or without
   8 * modification, are permitted provided that the following conditions
   9 * are met:
  10 *
  11 * * Redistributions of source code must retain the above copyright
  12 * notice, this list of conditions and the following disclaimer.
  13 * * Redistributions in binary form must reproduce the above copyright
  14 * notice, this list of conditions and the following disclaimer in
  15 * the documentation and/or other materials provided with the
  16 * distribution.
  17 * * Neither the name of copyright holder nor the names of its
  18 * contributors may be used to endorse or promote products derived
  19 * from this software without specific prior written permission.
  20 *
  21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32 */
  33
  34 #include <rte_ether.h>
  35 #include <rte_ethdev.h>
  36 #include <rte_tcp.h>
  37 #include <rte_atomic.h>
  38 #include <rte_dev.h>
  39 #include <rte_errno.h>
  40 #include <rte_version.h>
  41 #include <rte_eal_memconfig.h>
  42
  43 #include "ena_ethdev.h"
  44 #include "ena_logs.h"
  45 #include "ena_platform.h"
  46 #include "ena_com.h"
  47 #include "ena_eth_com.h"
  48
  49 #include <ena_common_defs.h>
  50 #include <ena_regs_defs.h>
  51 #include <ena_admin_defs.h>
  52 #include <ena_eth_io_defs.h>
  53
  54 #define DRV_MODULE_VER_MAJOR    1
  55 #define DRV_MODULE_VER_MINOR    0
  56 #define DRV_MODULE_VER_SUBMINOR 0
  57
  58 #define ENA_IO_TXQ_IDX(q)       (2 * (q))
  59 #define ENA_IO_RXQ_IDX(q)       (2 * (q) + 1)
  60 /*reverse version of ENA_IO_RXQ_IDX*/
  61 #define ENA_IO_RXQ_IDX_REV(q)   ((q - 1) / 2)
  62
  63 /* While processing submitted and completed descriptors (rx and tx path
  64  * respectively) in a loop it is desired to:
  65  *  - perform batch submissions while populating sumbissmion queue
  66  *  - avoid blocking transmission of other packets during cleanup phase
  67  * Hence the utilization ratio of 1/8 of a queue size.
  68  */
  69 #define ENA_RING_DESCS_RATIO(ring_size) (ring_size / 8)
  70
  71 #define __MERGE_64B_H_L(h, l) (((uint64_t)h << 32) | l)
  72 #define TEST_BIT(val, bit_shift) (val & (1UL << bit_shift))
  73
  74 #define GET_L4_HDR_LEN(mbuf)                                    \
  75         ((rte_pktmbuf_mtod_offset(mbuf, struct tcp_hdr *,       \
  76                 mbuf->l3_len + mbuf->l2_len)->data_off) >> 4)
  77
  78 #define ENA_RX_RSS_TABLE_LOG_SIZE  7
  79 #define ENA_RX_RSS_TABLE_SIZE   (1 << ENA_RX_RSS_TABLE_LOG_SIZE)
  80 #define ENA_HASH_KEY_SIZE       40
  81 #define ENA_ETH_SS_STATS        0xFF
  82 #define ETH_GSTRING_LEN 32
  83
  84 #define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
  85
  86 enum ethtool_stringset {
  87         ETH_SS_TEST             = 0,
  88         ETH_SS_STATS,
  89 };
  90
  91 struct ena_stats {
  92         char name[ETH_GSTRING_LEN];
  93         int stat_offset;
  94 };
  95
  96 #define ENA_STAT_ENA_COM_ENTRY(stat) { \
  97         .name = #stat, \
  98         .stat_offset = offsetof(struct ena_com_stats_admin, stat) \
  99 }
 100
 101 #define ENA_STAT_ENTRY(stat, stat_type) { \
 102         .name = #stat, \
 103         .stat_offset = offsetof(struct ena_stats_##stat_type, stat) \
 104 }
 105
 106 #define ENA_STAT_RX_ENTRY(stat) \
 107         ENA_STAT_ENTRY(stat, rx)
 108
 109 #define ENA_STAT_TX_ENTRY(stat) \
 110         ENA_STAT_ENTRY(stat, tx)
 111
 112 #define ENA_STAT_GLOBAL_ENTRY(stat) \
 113         ENA_STAT_ENTRY(stat, dev)
 114
 115 static const struct ena_stats ena_stats_global_strings[] = {
 116         ENA_STAT_GLOBAL_ENTRY(tx_timeout),
 117         ENA_STAT_GLOBAL_ENTRY(io_suspend),
 118         ENA_STAT_GLOBAL_ENTRY(io_resume),
 119         ENA_STAT_GLOBAL_ENTRY(wd_expired),
 120         ENA_STAT_GLOBAL_ENTRY(interface_up),
 121         ENA_STAT_GLOBAL_ENTRY(interface_down),
 122         ENA_STAT_GLOBAL_ENTRY(admin_q_pause),
 123 };
 124
 125 static const struct ena_stats ena_stats_tx_strings[] = {
 126         ENA_STAT_TX_ENTRY(cnt),
 127         ENA_STAT_TX_ENTRY(bytes),
 128         ENA_STAT_TX_ENTRY(queue_stop),
 129         ENA_STAT_TX_ENTRY(queue_wakeup),
 130         ENA_STAT_TX_ENTRY(dma_mapping_err),
 131         ENA_STAT_TX_ENTRY(linearize),
 132         ENA_STAT_TX_ENTRY(linearize_failed),
 133         ENA_STAT_TX_ENTRY(tx_poll),
 134         ENA_STAT_TX_ENTRY(doorbells),
 135         ENA_STAT_TX_ENTRY(prepare_ctx_err),
 136         ENA_STAT_TX_ENTRY(missing_tx_comp),
 137         ENA_STAT_TX_ENTRY(bad_req_id),
 138 };
 139
 140 static const struct ena_stats ena_stats_rx_strings[] = {
 141         ENA_STAT_RX_ENTRY(cnt),
 142         ENA_STAT_RX_ENTRY(bytes),
 143         ENA_STAT_RX_ENTRY(refil_partial),
 144         ENA_STAT_RX_ENTRY(bad_csum),
 145         ENA_STAT_RX_ENTRY(page_alloc_fail),
 146         ENA_STAT_RX_ENTRY(skb_alloc_fail),
 147         ENA_STAT_RX_ENTRY(dma_mapping_err),
 148         ENA_STAT_RX_ENTRY(bad_desc_num),
 149         ENA_STAT_RX_ENTRY(small_copy_len_pkt),
 150 };
 151
 152 static const struct ena_stats ena_stats_ena_com_strings[] = {
 153         ENA_STAT_ENA_COM_ENTRY(aborted_cmd),
 154         ENA_STAT_ENA_COM_ENTRY(submitted_cmd),
 155         ENA_STAT_ENA_COM_ENTRY(completed_cmd),
 156         ENA_STAT_ENA_COM_ENTRY(out_of_space),
 157         ENA_STAT_ENA_COM_ENTRY(no_completion),
 158 };
 159
 160 #define ENA_STATS_ARRAY_GLOBAL  ARRAY_SIZE(ena_stats_global_strings)
 161 #define ENA_STATS_ARRAY_TX      ARRAY_SIZE(ena_stats_tx_strings)
 162 #define ENA_STATS_ARRAY_RX      ARRAY_SIZE(ena_stats_rx_strings)
 163 #define ENA_STATS_ARRAY_ENA_COM ARRAY_SIZE(ena_stats_ena_com_strings)
 164
 165 /** Vendor ID used by Amazon devices */
 166 #define PCI_VENDOR_ID_AMAZON 0x1D0F
 167 /** Amazon devices */
 168 #define PCI_DEVICE_ID_ENA_VF    0xEC20
 169 #define PCI_DEVICE_ID_ENA_LLQ_VF        0xEC21
 170
 171 static struct rte_pci_id pci_id_ena_map[] = {
 172         { RTE_PCI_DEVICE(PCI_VENDOR_ID_AMAZON, PCI_DEVICE_ID_ENA_VF) },
 173         { RTE_PCI_DEVICE(PCI_VENDOR_ID_AMAZON, PCI_DEVICE_ID_ENA_LLQ_VF) },
 174         { .device_id = 0 },
 175 };
 176
 177 static int ena_device_init(struct ena_com_dev *ena_dev,
 178                            struct ena_com_dev_get_features_ctx *get_feat_ctx);
 179 static int ena_dev_configure(struct rte_eth_dev *dev);
 180 static uint16_t eth_ena_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
 181                                   uint16_t nb_pkts);
 182 static int ena_tx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,
 183                               uint16_t nb_desc, unsigned int socket_id,
 184                               const struct rte_eth_txconf *tx_conf);
 185 static int ena_rx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,
 186                               uint16_t nb_desc, unsigned int socket_id,
 187                               const struct rte_eth_rxconf *rx_conf,
 188                               struct rte_mempool *mp);
 189 static uint16_t eth_ena_recv_pkts(void *rx_queue,
 190                                   struct rte_mbuf **rx_pkts, uint16_t nb_pkts);
 191 static int ena_populate_rx_queue(struct ena_ring *rxq, unsigned int count);
 192 static void ena_init_rings(struct ena_adapter *adapter);
 193 static int ena_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
 194 static int ena_start(struct rte_eth_dev *dev);
 195 static void ena_close(struct rte_eth_dev *dev);
 196 static void ena_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats);
 197 static void ena_rx_queue_release_all(struct rte_eth_dev *dev);
 198 static void ena_tx_queue_release_all(struct rte_eth_dev *dev);
 199 static void ena_rx_queue_release(void *queue);
 200 static void ena_tx_queue_release(void *queue);
 201 static void ena_rx_queue_release_bufs(struct ena_ring *ring);
 202 static void ena_tx_queue_release_bufs(struct ena_ring *ring);
 203 static int ena_link_update(struct rte_eth_dev *dev,
 204                            __rte_unused int wait_to_complete);
 205 static int ena_queue_restart(struct ena_ring *ring);
 206 static int ena_queue_restart_all(struct rte_eth_dev *dev,
 207                                  enum ena_ring_type ring_type);
 208 static void ena_stats_restart(struct rte_eth_dev *dev);
 209 static void ena_infos_get(__rte_unused struct rte_eth_dev *dev,
 210                           struct rte_eth_dev_info *dev_info);
 211 static int ena_rss_reta_update(struct rte_eth_dev *dev,
 212                                struct rte_eth_rss_reta_entry64 *reta_conf,
 213                                uint16_t reta_size);
 214 static int ena_rss_reta_query(struct rte_eth_dev *dev,
 215                               struct rte_eth_rss_reta_entry64 *reta_conf,
 216                               uint16_t reta_size);
 217 static int ena_get_sset_count(struct rte_eth_dev *dev, int sset);
 218
 219 static struct eth_dev_ops ena_dev_ops = {
 220         .dev_configure        = ena_dev_configure,
 221         .dev_infos_get        = ena_infos_get,
 222         .rx_queue_setup       = ena_rx_queue_setup,
 223         .tx_queue_setup       = ena_tx_queue_setup,
 224         .dev_start            = ena_start,
 225         .link_update          = ena_link_update,
 226         .stats_get            = ena_stats_get,
 227         .mtu_set              = ena_mtu_set,
 228         .rx_queue_release     = ena_rx_queue_release,
 229         .tx_queue_release     = ena_tx_queue_release,
 230         .dev_close            = ena_close,
 231         .reta_update          = ena_rss_reta_update,
 232         .reta_query           = ena_rss_reta_query,
 233 };
 234
 235 #define NUMA_NO_NODE    SOCKET_ID_ANY
 236
 237 static inline int ena_cpu_to_node(int cpu)
 238 {
 239         struct rte_config *config = rte_eal_get_configuration();
 240
 241         if (likely(cpu < RTE_MAX_MEMZONE))
 242                 return config->mem_config->memzone[cpu].socket_id;
 243
 244         return NUMA_NO_NODE;
 245 }
 246
 247 static inline void ena_rx_mbuf_prepare(struct rte_mbuf *mbuf,
 248                                        struct ena_com_rx_ctx *ena_rx_ctx)
 249 {
 250         uint64_t ol_flags = 0;
 251
 252         if (ena_rx_ctx->l4_proto == ENA_ETH_IO_L4_PROTO_TCP)
 253                 ol_flags |= PKT_TX_TCP_CKSUM;
 254         else if (ena_rx_ctx->l4_proto == ENA_ETH_IO_L4_PROTO_UDP)
 255                 ol_flags |= PKT_TX_UDP_CKSUM;
 256
 257         if (ena_rx_ctx->l3_proto == ENA_ETH_IO_L3_PROTO_IPV4)
 258                 ol_flags |= PKT_TX_IPV4;
 259         else if (ena_rx_ctx->l3_proto == ENA_ETH_IO_L3_PROTO_IPV6)
 260                 ol_flags |= PKT_TX_IPV6;
 261
 262         if (unlikely(ena_rx_ctx->l4_csum_err))
 263                 ol_flags |= PKT_RX_L4_CKSUM_BAD;
 264         if (unlikely(ena_rx_ctx->l3_csum_err))
 265                 ol_flags |= PKT_RX_IP_CKSUM_BAD;
 266
 267         mbuf->ol_flags = ol_flags;
 268 }
 269
 270 static inline void ena_tx_mbuf_prepare(struct rte_mbuf *mbuf,
 271                                        struct ena_com_tx_ctx *ena_tx_ctx)
 272 {
 273         struct ena_com_tx_meta *ena_meta = &ena_tx_ctx->ena_meta;
 274
 275         if (mbuf->ol_flags &
 276             (PKT_TX_L4_MASK | PKT_TX_IP_CKSUM | PKT_TX_TCP_SEG)) {
 277                 /* check if TSO is required */
 278                 if (mbuf->ol_flags & PKT_TX_TCP_SEG) {
 279                         ena_tx_ctx->tso_enable = true;
 280
 281                         ena_meta->l4_hdr_len = GET_L4_HDR_LEN(mbuf);
 282                 }
 283
 284                 /* check if L3 checksum is needed */
 285                 if (mbuf->ol_flags & PKT_TX_IP_CKSUM)
 286                         ena_tx_ctx->l3_csum_enable = true;
 287
 288                 if (mbuf->ol_flags & PKT_TX_IPV6) {
 289                         ena_tx_ctx->l3_proto = ENA_ETH_IO_L3_PROTO_IPV6;
 290                 } else {
 291                         ena_tx_ctx->l3_proto = ENA_ETH_IO_L3_PROTO_IPV4;
 292
 293                         /* set don't fragment (DF) flag */
 294                         if (mbuf->packet_type &
 295                                 (RTE_PTYPE_L4_NONFRAG
 296                                  | RTE_PTYPE_INNER_L4_NONFRAG))
 297                                 ena_tx_ctx->df = true;
 298                 }
 299
 300                 /* check if L4 checksum is needed */
 301                 switch (mbuf->ol_flags & PKT_TX_L4_MASK) {
 302                 case PKT_TX_TCP_CKSUM:
 303                         ena_tx_ctx->l4_proto = ENA_ETH_IO_L4_PROTO_TCP;
 304                         ena_tx_ctx->l4_csum_enable = true;
 305                         break;
 306                 case PKT_TX_UDP_CKSUM:
 307                         ena_tx_ctx->l4_proto = ENA_ETH_IO_L4_PROTO_UDP;
 308                         ena_tx_ctx->l4_csum_enable = true;
 309                         break;
 310                 default:
 311                         ena_tx_ctx->l4_proto = ENA_ETH_IO_L4_PROTO_UNKNOWN;
 312                         ena_tx_ctx->l4_csum_enable = false;
 313                         break;
 314                 }
 315
 316                 ena_meta->mss = mbuf->tso_segsz;
 317                 ena_meta->l3_hdr_len = mbuf->l3_len;
 318                 ena_meta->l3_hdr_offset = mbuf->l2_len;
 319                 /* this param needed only for TSO */
 320                 ena_meta->l3_outer_hdr_len = 0;
 321                 ena_meta->l3_outer_hdr_offset = 0;
 322
 323                 ena_tx_ctx->meta_valid = true;
 324         } else {
 325                 ena_tx_ctx->meta_valid = false;
 326         }
 327 }
 328
 329 static void ena_config_host_info(struct ena_com_dev *ena_dev)
 330 {
 331         struct ena_admin_host_info *host_info;
 332         int rc;
 333
 334         /* Allocate only the host info */
 335         rc = ena_com_allocate_host_info(ena_dev);
 336         if (rc) {
 337                 RTE_LOG(ERR, PMD, "Cannot allocate host info\n");
 338                 return;
 339         }
 340
 341         host_info = ena_dev->host_attr.host_info;
 342
 343         host_info->os_type = ENA_ADMIN_OS_DPDK;
 344         host_info->kernel_ver = RTE_VERSION;
 345         snprintf((char *)host_info->kernel_ver_str,
 346                  sizeof(host_info->kernel_ver_str),
 347                  "%s", rte_version());
 348         host_info->os_dist = RTE_VERSION;
 349         snprintf((char *)host_info->os_dist_str,
 350                  sizeof(host_info->os_dist_str),
 351                  "%s", rte_version());
 352         host_info->driver_version =
 353                 (DRV_MODULE_VER_MAJOR) |
 354                 (DRV_MODULE_VER_MINOR << ENA_ADMIN_HOST_INFO_MINOR_SHIFT) |
 355                 (DRV_MODULE_VER_SUBMINOR <<
 356                         ENA_ADMIN_HOST_INFO_SUB_MINOR_SHIFT);
 357
 358         rc = ena_com_set_host_attributes(ena_dev);
 359         if (rc) {
 360                 RTE_LOG(ERR, PMD, "Cannot set host attributes\n");
 361                 if (rc != -EPERM)
 362                         goto err;
 363         }
 364
 365         return;
 366
 367 err:
 368         ena_com_delete_host_info(ena_dev);
 369 }
 370
 371 static int
 372 ena_get_sset_count(struct rte_eth_dev *dev, int sset)
 373 {
 374         if (sset != ETH_SS_STATS)
 375                 return -EOPNOTSUPP;
 376
 377          /* Workaround for clang:
 378          * touch internal structures to prevent
 379          * compiler error
 380          */
 381         ENA_TOUCH(ena_stats_global_strings);
 382         ENA_TOUCH(ena_stats_tx_strings);
 383         ENA_TOUCH(ena_stats_rx_strings);
 384         ENA_TOUCH(ena_stats_ena_com_strings);
 385
 386         return  dev->data->nb_tx_queues *
 387                 (ENA_STATS_ARRAY_TX + ENA_STATS_ARRAY_RX) +
 388                 ENA_STATS_ARRAY_GLOBAL + ENA_STATS_ARRAY_ENA_COM;
 389 }
 390
 391 static void ena_config_debug_area(struct ena_adapter *adapter)
 392 {
 393         u32 debug_area_size;
 394         int rc, ss_count;
 395
 396         ss_count = ena_get_sset_count(adapter->rte_dev, ETH_SS_STATS);
 397         if (ss_count <= 0) {
 398                 RTE_LOG(ERR, PMD, "SS count is negative\n");
 399                 return;
 400         }
 401
 402         /* allocate 32 bytes for each string and 64bit for the value */
 403         debug_area_size = ss_count * ETH_GSTRING_LEN + sizeof(u64) * ss_count;
 404
 405         rc = ena_com_allocate_debug_area(&adapter->ena_dev, debug_area_size);
 406         if (rc) {
 407                 RTE_LOG(ERR, PMD, "Cannot allocate debug area\n");
 408                 return;
 409         }
 410
 411         rc = ena_com_set_host_attributes(&adapter->ena_dev);
 412         if (rc) {
 413                 RTE_LOG(WARNING, PMD, "Cannot set host attributes\n");
 414                 if (rc != -EPERM)
 415                         goto err;
 416         }
 417
 418         return;
 419 err:
 420         ena_com_delete_debug_area(&adapter->ena_dev);
 421 }
 422
 423 static void ena_close(struct rte_eth_dev *dev)
 424 {
 425         struct ena_adapter *adapter =
 426                 (struct ena_adapter *)(dev->data->dev_private);
 427
 428         adapter->state = ENA_ADAPTER_STATE_STOPPED;
 429
 430         ena_rx_queue_release_all(dev);
 431         ena_tx_queue_release_all(dev);
 432 }
 433
 434 static int ena_rss_reta_update(struct rte_eth_dev *dev,
 435                                struct rte_eth_rss_reta_entry64 *reta_conf,
 436                                uint16_t reta_size)
 437 {
 438         struct ena_adapter *adapter =
 439                 (struct ena_adapter *)(dev->data->dev_private);
 440         struct ena_com_dev *ena_dev = &adapter->ena_dev;
 441         int ret, i;
 442         u16 entry_value;
 443         int conf_idx;
 444         int idx;
 445
 446         if ((reta_size == 0) || (reta_conf == NULL))
 447                 return -EINVAL;
 448
 449         if (reta_size > ENA_RX_RSS_TABLE_SIZE) {
 450                 RTE_LOG(WARNING, PMD,
 451                         "indirection table %d is bigger than supported (%d)\n",
 452                         reta_size, ENA_RX_RSS_TABLE_SIZE);
 453                 ret = -EINVAL;
 454                 goto err;
 455         }
 456
 457         for (i = 0 ; i < reta_size ; i++) {
 458                 /* each reta_conf is for 64 entries.
 459                  * to support 128 we use 2 conf of 64
 460                  */
 461                 conf_idx = i / RTE_RETA_GROUP_SIZE;
 462                 idx = i % RTE_RETA_GROUP_SIZE;
 463                 if (TEST_BIT(reta_conf[conf_idx].mask, idx)) {
 464                         entry_value =
 465                                 ENA_IO_RXQ_IDX(reta_conf[conf_idx].reta[idx]);
 466                         ret = ena_com_indirect_table_fill_entry(ena_dev,
 467                                                                 i,
 468                                                                 entry_value);
 469                         if (unlikely(ret && (ret != ENA_COM_PERMISSION))) {
 470                                 RTE_LOG(ERR, PMD,
 471                                         "Cannot fill indirect table\n");
 472                                 ret = -ENOTSUP;
 473                                 goto err;
 474                         }
 475                 }
 476         }
 477
 478         ret = ena_com_indirect_table_set(ena_dev);
 479         if (unlikely(ret && (ret != ENA_COM_PERMISSION))) {
 480                 RTE_LOG(ERR, PMD, "Cannot flush the indirect table\n");
 481                 ret = -ENOTSUP;
 482                 goto err;
 483         }
 484
 485         RTE_LOG(DEBUG, PMD, "%s(): RSS configured %d entries  for port %d\n",
 486                 __func__, reta_size, adapter->rte_dev->data->port_id);
 487 err:
 488         return ret;
 489 }
 490
 491 /* Query redirection table. */
 492 static int ena_rss_reta_query(struct rte_eth_dev *dev,
 493                               struct rte_eth_rss_reta_entry64 *reta_conf,
 494                               uint16_t reta_size)
 495 {
 496         struct ena_adapter *adapter =
 497                 (struct ena_adapter *)(dev->data->dev_private);
 498         struct ena_com_dev *ena_dev = &adapter->ena_dev;
 499         int ret;
 500         int i;
 501         u32 indirect_table[ENA_RX_RSS_TABLE_SIZE] = {0};
 502         int reta_conf_idx;
 503         int reta_idx;
 504
 505         if (reta_size == 0 || reta_conf == NULL ||
 506             (reta_size > RTE_RETA_GROUP_SIZE && ((reta_conf + 1) == NULL)))
 507                 return -EINVAL;
 508
 509         ret = ena_com_indirect_table_get(ena_dev, indirect_table);
 510         if (unlikely(ret && (ret != ENA_COM_PERMISSION))) {
 511                 RTE_LOG(ERR, PMD, "cannot get indirect table\n");
 512                 ret = -ENOTSUP;
 513                 goto err;
 514         }
 515
 516         for (i = 0 ; i < reta_size ; i++) {
 517                 reta_conf_idx = i / RTE_RETA_GROUP_SIZE;
 518                 reta_idx = i % RTE_RETA_GROUP_SIZE;
 519                 if (TEST_BIT(reta_conf[reta_conf_idx].mask, reta_idx))
 520                         reta_conf[reta_conf_idx].reta[reta_idx] =
 521                                 ENA_IO_RXQ_IDX_REV(indirect_table[i]);
 522         }
 523 err:
 524         return ret;
 525 }
 526
 527 static int ena_rss_init_default(struct ena_adapter *adapter)
 528 {
 529         struct ena_com_dev *ena_dev = &adapter->ena_dev;
 530         uint16_t nb_rx_queues = adapter->rte_dev->data->nb_rx_queues;
 531         int rc, i;
 532         u32 val;
 533
 534         rc = ena_com_rss_init(ena_dev, ENA_RX_RSS_TABLE_LOG_SIZE);
 535         if (unlikely(rc)) {
 536                 RTE_LOG(ERR, PMD, "Cannot init indirect table\n");
 537                 goto err_rss_init;
 538         }
 539
 540         for (i = 0; i < ENA_RX_RSS_TABLE_SIZE; i++) {
 541                 val = i % nb_rx_queues;
 542                 rc = ena_com_indirect_table_fill_entry(ena_dev, i,
 543                                                        ENA_IO_RXQ_IDX(val));
 544                 if (unlikely(rc && (rc != ENA_COM_PERMISSION))) {
 545                         RTE_LOG(ERR, PMD, "Cannot fill indirect table\n");
 546                         goto err_fill_indir;
 547                 }
 548         }
 549
 550         rc = ena_com_fill_hash_function(ena_dev, ENA_ADMIN_CRC32, NULL,
 551                                         ENA_HASH_KEY_SIZE, 0xFFFFFFFF);
 552         if (unlikely(rc && (rc != ENA_COM_PERMISSION))) {
 553                 RTE_LOG(INFO, PMD, "Cannot fill hash function\n");
 554                 goto err_fill_indir;
 555         }
 556
 557         rc = ena_com_set_default_hash_ctrl(ena_dev);
 558         if (unlikely(rc && (rc != ENA_COM_PERMISSION))) {
 559                 RTE_LOG(INFO, PMD, "Cannot fill hash control\n");
 560                 goto err_fill_indir;
 561         }
 562
 563         rc = ena_com_indirect_table_set(ena_dev);
 564         if (unlikely(rc && (rc != ENA_COM_PERMISSION))) {
 565                 RTE_LOG(ERR, PMD, "Cannot flush the indirect table\n");
 566                 goto err_fill_indir;
 567         }
 568         RTE_LOG(DEBUG, PMD, "RSS configured for port %d\n",
 569                 adapter->rte_dev->data->port_id);
 570
 571         return 0;
 572
 573 err_fill_indir:
 574         ena_com_rss_destroy(ena_dev);
 575 err_rss_init:
 576
 577         return rc;
 578 }
 579
 580 static void ena_rx_queue_release_all(struct rte_eth_dev *dev)
 581 {
 582         struct ena_ring **queues = (struct ena_ring **)dev->data->rx_queues;
 583         int nb_queues = dev->data->nb_rx_queues;
 584         int i;
 585
 586         for (i = 0; i < nb_queues; i++)
 587                 ena_rx_queue_release(queues[i]);
 588 }
 589
 590 static void ena_tx_queue_release_all(struct rte_eth_dev *dev)
 591 {
 592         struct ena_ring **queues = (struct ena_ring **)dev->data->tx_queues;
 593         int nb_queues = dev->data->nb_tx_queues;
 594         int i;
 595
 596         for (i = 0; i < nb_queues; i++)
 597                 ena_tx_queue_release(queues[i]);
 598 }
 599
 600 static void ena_rx_queue_release(void *queue)
 601 {
 602         struct ena_ring *ring = (struct ena_ring *)queue;
 603         struct ena_adapter *adapter = ring->adapter;
 604         int ena_qid;
 605
 606         ena_assert_msg(ring->configured,
 607                        "API violation - releasing not configured queue");
 608         ena_assert_msg(ring->adapter->state != ENA_ADAPTER_STATE_RUNNING,
 609                        "API violation");
 610
 611         /* Destroy HW queue */
 612         ena_qid = ENA_IO_RXQ_IDX(ring->id);
 613         ena_com_destroy_io_queue(&adapter->ena_dev, ena_qid);
 614
 615         /* Free all bufs */
 616         ena_rx_queue_release_bufs(ring);
 617
 618         /* Free ring resources */
 619         if (ring->rx_buffer_info)
 620                 rte_free(ring->rx_buffer_info);
 621         ring->rx_buffer_info = NULL;
 622
 623         ring->configured = 0;
 624
 625         RTE_LOG(NOTICE, PMD, "RX Queue %d:%d released\n",
 626                 ring->port_id, ring->id);
 627 }
 628
 629 static void ena_tx_queue_release(void *queue)
 630 {
 631         struct ena_ring *ring = (struct ena_ring *)queue;
 632         struct ena_adapter *adapter = ring->adapter;
 633         int ena_qid;
 634
 635         ena_assert_msg(ring->configured,
 636                        "API violation. Releasing not configured queue");
 637         ena_assert_msg(ring->adapter->state != ENA_ADAPTER_STATE_RUNNING,
 638                        "API violation");
 639
 640         /* Destroy HW queue */
 641         ena_qid = ENA_IO_TXQ_IDX(ring->id);
 642         ena_com_destroy_io_queue(&adapter->ena_dev, ena_qid);
 643
 644         /* Free all bufs */
 645         ena_tx_queue_release_bufs(ring);
 646
 647         /* Free ring resources */
 648         if (ring->tx_buffer_info)
 649                 rte_free(ring->tx_buffer_info);
 650
 651         if (ring->empty_tx_reqs)
 652                 rte_free(ring->empty_tx_reqs);
 653
 654         ring->empty_tx_reqs = NULL;
 655         ring->tx_buffer_info = NULL;
 656
 657         ring->configured = 0;
 658
 659         RTE_LOG(NOTICE, PMD, "TX Queue %d:%d released\n",
 660                 ring->port_id, ring->id);
 661 }
 662
 663 static void ena_rx_queue_release_bufs(struct ena_ring *ring)
 664 {
 665         unsigned int ring_mask = ring->ring_size - 1;
 666
 667         while (ring->next_to_clean != ring->next_to_use) {
 668                 struct rte_mbuf *m =
 669                         ring->rx_buffer_info[ring->next_to_clean & ring_mask];
 670
 671                 if (m)
 672                         __rte_mbuf_raw_free(m);
 673
 674                 ring->next_to_clean++;
 675         }
 676 }
 677
 678 static void ena_tx_queue_release_bufs(struct ena_ring *ring)
 679 {
 680         unsigned int i;
 681
 682         for (i = 0; i < ring->ring_size; ++i) {
 683                 struct ena_tx_buffer *tx_buf = &ring->tx_buffer_info[i];
 684
 685                 if (tx_buf->mbuf)
 686                         rte_pktmbuf_free(tx_buf->mbuf);
 687
 688                 ring->next_to_clean++;
 689         }
 690 }
 691
 692 static int ena_link_update(struct rte_eth_dev *dev,
 693                            __rte_unused int wait_to_complete)
 694 {
 695         struct rte_eth_link *link = &dev->data->dev_link;
 696
 697         link->link_status = 1;
 698         link->link_speed = ETH_SPEED_NUM_10G;
 699         link->link_duplex = ETH_LINK_FULL_DUPLEX;
 700
 701         return 0;
 702 }
 703
 704 static int ena_queue_restart_all(struct rte_eth_dev *dev,
 705                                  enum ena_ring_type ring_type)
 706 {
 707         struct ena_adapter *adapter =
 708                 (struct ena_adapter *)(dev->data->dev_private);
 709         struct ena_ring *queues = NULL;
 710         int i = 0;
 711         int rc = 0;
 712
 713         queues = (ring_type == ENA_RING_TYPE_RX) ?
 714                 adapter->rx_ring : adapter->tx_ring;
 715
 716         for (i = 0; i < adapter->num_queues; i++) {
 717                 if (queues[i].configured) {
 718                         if (ring_type == ENA_RING_TYPE_RX) {
 719                                 ena_assert_msg(
 720                                         dev->data->rx_queues[i] == &queues[i],
 721                                         "Inconsistent state of rx queues\n");
 722                         } else {
 723                                 ena_assert_msg(
 724                                         dev->data->tx_queues[i] == &queues[i],
 725                                         "Inconsistent state of tx queues\n");
 726                         }
 727
 728                         rc = ena_queue_restart(&queues[i]);
 729
 730                         if (rc) {
 731                                 PMD_INIT_LOG(ERR,
 732                                              "failed to restart queue %d type(%d)\n",
 733                                              i, ring_type);
 734                                 return -1;
 735                         }
 736                 }
 737         }
 738
 739         return 0;
 740 }
 741
 742 static uint32_t ena_get_mtu_conf(struct ena_adapter *adapter)
 743 {
 744         uint32_t max_frame_len = adapter->max_mtu;
 745
 746         if (adapter->rte_eth_dev_data->dev_conf.rxmode.jumbo_frame == 1)
 747                 max_frame_len =
 748                         adapter->rte_eth_dev_data->dev_conf.rxmode.max_rx_pkt_len;
 749
 750         return max_frame_len;
 751 }
 752
 753 static int ena_check_valid_conf(struct ena_adapter *adapter)
 754 {
 755         uint32_t max_frame_len = ena_get_mtu_conf(adapter);
 756
 757         if (max_frame_len > adapter->max_mtu) {
 758                 PMD_INIT_LOG(ERR, "Unsupported MTU of %d\n", max_frame_len);
 759                 return -1;
 760         }
 761
 762         return 0;
 763 }
 764
 765 static int
 766 ena_calc_queue_size(struct ena_com_dev *ena_dev,
 767                     struct ena_com_dev_get_features_ctx *get_feat_ctx)
 768 {
 769         uint32_t queue_size = ENA_DEFAULT_RING_SIZE;
 770
 771         queue_size = RTE_MIN(queue_size,
 772                              get_feat_ctx->max_queues.max_cq_depth);
 773         queue_size = RTE_MIN(queue_size,
 774                              get_feat_ctx->max_queues.max_sq_depth);
 775
 776         if (ena_dev->tx_mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_DEV)
 777                 queue_size = RTE_MIN(queue_size,
 778                                      get_feat_ctx->max_queues.max_llq_depth);
 779
 780         /* Round down to power of 2 */
 781         if (!rte_is_power_of_2(queue_size))
 782                 queue_size = rte_align32pow2(queue_size >> 1);
 783
 784         if (queue_size == 0) {
 785                 PMD_INIT_LOG(ERR, "Invalid queue size\n");
 786                 return -EFAULT;
 787         }
 788
 789         return queue_size;
 790 }
 791
 792 static void ena_stats_restart(struct rte_eth_dev *dev)
 793 {
 794         struct ena_adapter *adapter =
 795                 (struct ena_adapter *)(dev->data->dev_private);
 796
 797         rte_atomic64_init(&adapter->drv_stats->ierrors);
 798         rte_atomic64_init(&adapter->drv_stats->oerrors);
 799         rte_atomic64_init(&adapter->drv_stats->rx_nombuf);
 800 }
 801
 802 static void ena_stats_get(struct rte_eth_dev *dev,
 803                           struct rte_eth_stats *stats)
 804 {
 805         struct ena_admin_basic_stats ena_stats;
 806         struct ena_adapter *adapter =
 807                 (struct ena_adapter *)(dev->data->dev_private);
 808         struct ena_com_dev *ena_dev = &adapter->ena_dev;
 809         int rc;
 810
 811         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
 812                 return;
 813
 814         memset(&ena_stats, 0, sizeof(ena_stats));
 815         rc = ena_com_get_dev_basic_stats(ena_dev, &ena_stats);
 816         if (unlikely(rc)) {
 817                 RTE_LOG(ERR, PMD, "Could not retrieve statistics from ENA");
 818                 return;
 819         }
 820
 821         /* Set of basic statistics from ENA */
 822         stats->ipackets = __MERGE_64B_H_L(ena_stats.rx_pkts_high,
 823                                           ena_stats.rx_pkts_low);
 824         stats->opackets = __MERGE_64B_H_L(ena_stats.tx_pkts_high,
 825                                           ena_stats.tx_pkts_low);
 826         stats->ibytes = __MERGE_64B_H_L(ena_stats.rx_bytes_high,
 827                                         ena_stats.rx_bytes_low);
 828         stats->obytes = __MERGE_64B_H_L(ena_stats.tx_bytes_high,
 829                                         ena_stats.tx_bytes_low);
 830         stats->imissed = __MERGE_64B_H_L(ena_stats.rx_drops_high,
 831                                          ena_stats.rx_drops_low);
 832
 833         /* Driver related stats */
 834         stats->ierrors = rte_atomic64_read(&adapter->drv_stats->ierrors);
 835         stats->oerrors = rte_atomic64_read(&adapter->drv_stats->oerrors);
 836         stats->rx_nombuf = rte_atomic64_read(&adapter->drv_stats->rx_nombuf);
 837 }
 838
 839 static int ena_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
 840 {
 841         struct ena_adapter *adapter;
 842         struct ena_com_dev *ena_dev;
 843         int rc = 0;
 844
 845         ena_assert_msg(dev->data != NULL, "Uninitialized device");
 846         ena_assert_msg(dev->data->dev_private != NULL, "Uninitialized device");
 847         adapter = (struct ena_adapter *)(dev->data->dev_private);
 848
 849         ena_dev = &adapter->ena_dev;
 850         ena_assert_msg(ena_dev != NULL, "Uninitialized device");
 851
 852         if (mtu > ena_get_mtu_conf(adapter)) {
 853                 RTE_LOG(ERR, PMD,
 854                         "Given MTU (%d) exceeds maximum MTU supported (%d)\n",
 855                         mtu, ena_get_mtu_conf(adapter));
 856                 rc = -EINVAL;
 857                 goto err;
 858         }
 859
 860         rc = ena_com_set_dev_mtu(ena_dev, mtu);
 861         if (rc)
 862                 RTE_LOG(ERR, PMD, "Could not set MTU: %d\n", mtu);
 863         else
 864                 RTE_LOG(NOTICE, PMD, "Set MTU: %d\n", mtu);
 865
 866 err:
 867         return rc;
 868 }
 869
 870 static int ena_start(struct rte_eth_dev *dev)
 871 {
 872         struct ena_adapter *adapter =
 873                 (struct ena_adapter *)(dev->data->dev_private);
 874         int rc = 0;
 875
 876         if (!(adapter->state == ENA_ADAPTER_STATE_CONFIG ||
 877               adapter->state == ENA_ADAPTER_STATE_STOPPED)) {
 878                 PMD_INIT_LOG(ERR, "API violation");
 879                 return -1;
 880         }
 881
 882         rc = ena_check_valid_conf(adapter);
 883         if (rc)
 884                 return rc;
 885
 886         rc = ena_queue_restart_all(dev, ENA_RING_TYPE_RX);
 887         if (rc)
 888                 return rc;
 889
 890         rc = ena_queue_restart_all(dev, ENA_RING_TYPE_TX);
 891         if (rc)
 892                 return rc;
 893
 894         if (adapter->rte_dev->data->dev_conf.rxmode.mq_mode &
 895             ETH_MQ_RX_RSS_FLAG) {
 896                 rc = ena_rss_init_default(adapter);
 897                 if (rc)
 898                         return rc;
 899         }
 900
 901         ena_stats_restart(dev);
 902
 903         adapter->state = ENA_ADAPTER_STATE_RUNNING;
 904
 905         return 0;
 906 }
 907
 908 static int ena_queue_restart(struct ena_ring *ring)
 909 {
 910         int rc, bufs_num;
 911
 912         ena_assert_msg(ring->configured == 1,
 913                        "Trying to restart unconfigured queue\n");
 914
 915         ring->next_to_clean = 0;
 916         ring->next_to_use = 0;
 917
 918         if (ring->type == ENA_RING_TYPE_TX)
 919                 return 0;
 920
 921         bufs_num = ring->ring_size - 1;
 922         rc = ena_populate_rx_queue(ring, bufs_num);
 923         if (rc != bufs_num) {
 924                 PMD_INIT_LOG(ERR, "Failed to populate rx ring !");
 925                 return (-1);
 926         }
 927
 928         return 0;
 929 }
 930
 931 static int ena_tx_queue_setup(struct rte_eth_dev *dev,
 932                               uint16_t queue_idx,
 933                               uint16_t nb_desc,
 934                               __rte_unused unsigned int socket_id,
 935                               __rte_unused const struct rte_eth_txconf *tx_conf)
 936 {
 937         struct ena_com_create_io_ctx ctx =
 938                 /* policy set to _HOST just to satisfy icc compiler */
 939                 { ENA_ADMIN_PLACEMENT_POLICY_HOST,
 940                   ENA_COM_IO_QUEUE_DIRECTION_TX, 0, 0, 0, 0 };
 941         struct ena_ring *txq = NULL;
 942         struct ena_adapter *adapter =
 943                 (struct ena_adapter *)(dev->data->dev_private);
 944         unsigned int i;
 945         int ena_qid;
 946         int rc;
 947         struct ena_com_dev *ena_dev = &adapter->ena_dev;
 948
 949         txq = &adapter->tx_ring[queue_idx];
 950
 951         if (txq->configured) {
 952                 RTE_LOG(CRIT, PMD,
 953                         "API violation. Queue %d is already configured\n",
 954                         queue_idx);
 955                 return -1;
 956         }
 957
 958         if (!rte_is_power_of_2(nb_desc)) {
 959                 RTE_LOG(ERR, PMD,
 960                         "Unsupported size of RX queue: %d is not a power of 2.",
 961                         nb_desc);
 962                 return -EINVAL;
 963         }
 964
 965         if (nb_desc > adapter->tx_ring_size) {
 966                 RTE_LOG(ERR, PMD,
 967                         "Unsupported size of TX queue (max size: %d)\n",
 968                         adapter->tx_ring_size);
 969                 return -EINVAL;
 970         }
 971
 972         ena_qid = ENA_IO_TXQ_IDX(queue_idx);
 973
 974         ctx.direction = ENA_COM_IO_QUEUE_DIRECTION_TX;
 975         ctx.qid = ena_qid;
 976         ctx.msix_vector = -1; /* admin interrupts not used */
 977         ctx.mem_queue_type = ena_dev->tx_mem_queue_type;
 978         ctx.queue_size = adapter->tx_ring_size;
 979         ctx.numa_node = ena_cpu_to_node(queue_idx);
 980
 981         rc = ena_com_create_io_queue(ena_dev, &ctx);
 982         if (rc) {
 983                 RTE_LOG(ERR, PMD,
 984                         "failed to create io TX queue #%d (qid:%d) rc: %d\n",
 985                         queue_idx, ena_qid, rc);
 986         }
 987         txq->ena_com_io_cq = &ena_dev->io_cq_queues[ena_qid];
 988         txq->ena_com_io_sq = &ena_dev->io_sq_queues[ena_qid];
 989
 990         rc = ena_com_get_io_handlers(ena_dev, ena_qid,
 991                                      &txq->ena_com_io_sq,
 992                                      &txq->ena_com_io_cq);
 993         if (rc) {
 994                 RTE_LOG(ERR, PMD,
 995                         "Failed to get TX queue handlers. TX queue num %d rc: %d\n",
 996                         queue_idx, rc);
 997                 ena_com_destroy_io_queue(ena_dev, ena_qid);
 998                 goto err;
 999         }
1000
1001         txq->port_id = dev->data->port_id;
1002         txq->next_to_clean = 0;
1003         txq->next_to_use = 0;
1004         txq->ring_size = nb_desc;
1005
1006         txq->tx_buffer_info = rte_zmalloc("txq->tx_buffer_info",
1007                                           sizeof(struct ena_tx_buffer) *
1008                                           txq->ring_size,
1009                                           RTE_CACHE_LINE_SIZE);
1010         if (!txq->tx_buffer_info) {
1011                 RTE_LOG(ERR, PMD, "failed to alloc mem for tx buffer info\n");
1012                 return -ENOMEM;
1013         }
1014
1015         txq->empty_tx_reqs = rte_zmalloc("txq->empty_tx_reqs",
1016                                          sizeof(u16) * txq->ring_size,
1017                                          RTE_CACHE_LINE_SIZE);
1018         if (!txq->empty_tx_reqs) {
1019                 RTE_LOG(ERR, PMD, "failed to alloc mem for tx reqs\n");
1020                 rte_free(txq->tx_buffer_info);
1021                 return -ENOMEM;
1022         }
1023         for (i = 0; i < txq->ring_size; i++)
1024                 txq->empty_tx_reqs[i] = i;
1025
1026         /* Store pointer to this queue in upper layer */
1027         txq->configured = 1;
1028         dev->data->tx_queues[queue_idx] = txq;
1029 err:
1030         return rc;
1031 }
1032
1033 static int ena_rx_queue_setup(struct rte_eth_dev *dev,
1034                               uint16_t queue_idx,
1035                               uint16_t nb_desc,
1036                               __rte_unused unsigned int socket_id,
1037                               __rte_unused const struct rte_eth_rxconf *rx_conf,
1038                               struct rte_mempool *mp)
1039 {
1040         struct ena_com_create_io_ctx ctx =
1041                 /* policy set to _HOST just to satisfy icc compiler */
1042                 { ENA_ADMIN_PLACEMENT_POLICY_HOST,
1043                   ENA_COM_IO_QUEUE_DIRECTION_RX, 0, 0, 0, 0 };
1044         struct ena_adapter *adapter =
1045                 (struct ena_adapter *)(dev->data->dev_private);
1046         struct ena_ring *rxq = NULL;
1047         uint16_t ena_qid = 0;
1048         int rc = 0;
1049         struct ena_com_dev *ena_dev = &adapter->ena_dev;
1050
1051         rxq = &adapter->rx_ring[queue_idx];
1052         if (rxq->configured) {
1053                 RTE_LOG(CRIT, PMD,
1054                         "API violation. Queue %d is already configured\n",
1055                         queue_idx);
1056                 return -1;
1057         }
1058
1059         if (!rte_is_power_of_2(nb_desc)) {
1060                 RTE_LOG(ERR, PMD,
1061                         "Unsupported size of TX queue: %d is not a power of 2.",
1062                         nb_desc);
1063                 return -EINVAL;
1064         }
1065
1066         if (nb_desc > adapter->rx_ring_size) {
1067                 RTE_LOG(ERR, PMD,
1068                         "Unsupported size of RX queue (max size: %d)\n",
1069                         adapter->rx_ring_size);
1070                 return -EINVAL;
1071         }
1072
1073         ena_qid = ENA_IO_RXQ_IDX(queue_idx);
1074
1075         ctx.qid = ena_qid;
1076         ctx.direction = ENA_COM_IO_QUEUE_DIRECTION_RX;
1077         ctx.mem_queue_type = ENA_ADMIN_PLACEMENT_POLICY_HOST;
1078         ctx.msix_vector = -1; /* admin interrupts not used */
1079         ctx.queue_size = adapter->rx_ring_size;
1080         ctx.numa_node = ena_cpu_to_node(queue_idx);
1081
1082         rc = ena_com_create_io_queue(ena_dev, &ctx);
1083         if (rc)
1084                 RTE_LOG(ERR, PMD, "failed to create io RX queue #%d rc: %d\n",
1085                         queue_idx, rc);
1086
1087         rxq->ena_com_io_cq = &ena_dev->io_cq_queues[ena_qid];
1088         rxq->ena_com_io_sq = &ena_dev->io_sq_queues[ena_qid];
1089
1090         rc = ena_com_get_io_handlers(ena_dev, ena_qid,
1091                                      &rxq->ena_com_io_sq,
1092                                      &rxq->ena_com_io_cq);
1093         if (rc) {
1094                 RTE_LOG(ERR, PMD,
1095                         "Failed to get RX queue handlers. RX queue num %d rc: %d\n",
1096                         queue_idx, rc);
1097                 ena_com_destroy_io_queue(ena_dev, ena_qid);
1098         }
1099
1100         rxq->port_id = dev->data->port_id;
1101         rxq->next_to_clean = 0;
1102         rxq->next_to_use = 0;
1103         rxq->ring_size = nb_desc;
1104         rxq->mb_pool = mp;
1105
1106         rxq->rx_buffer_info = rte_zmalloc("rxq->buffer_info",
1107                                           sizeof(struct rte_mbuf *) * nb_desc,
1108                                           RTE_CACHE_LINE_SIZE);
1109         if (!rxq->rx_buffer_info) {
1110                 RTE_LOG(ERR, PMD, "failed to alloc mem for rx buffer info\n");
1111                 return -ENOMEM;
1112         }
1113
1114         /* Store pointer to this queue in upper layer */
1115         rxq->configured = 1;
1116         dev->data->rx_queues[queue_idx] = rxq;
1117
1118         return rc;
1119 }
1120
1121 static int ena_populate_rx_queue(struct ena_ring *rxq, unsigned int count)
1122 {
1123         unsigned int i;
1124         int rc;
1125         uint16_t ring_size = rxq->ring_size;
1126         uint16_t ring_mask = ring_size - 1;
1127         uint16_t next_to_use = rxq->next_to_use;
1128         uint16_t in_use;
1129         struct rte_mbuf **mbufs = &rxq->rx_buffer_info[0];
1130
1131         if (unlikely(!count))
1132                 return 0;
1133
1134         in_use = rxq->next_to_use - rxq->next_to_clean;
1135         ena_assert_msg(((in_use + count) < ring_size), "bad ring state");
1136
1137         count = RTE_MIN(count,
1138                         (uint16_t)(ring_size - (next_to_use & ring_mask)));
1139
1140         /* get resources for incoming packets */
1141         rc = rte_mempool_get_bulk(rxq->mb_pool,
1142                                   (void **)(&mbufs[next_to_use & ring_mask]),
1143                                   count);
1144         if (unlikely(rc < 0)) {
1145                 rte_atomic64_inc(&rxq->adapter->drv_stats->rx_nombuf);
1146                 PMD_RX_LOG(DEBUG, "there are no enough free buffers");
1147                 return 0;
1148         }
1149
1150         for (i = 0; i < count; i++) {
1151                 uint16_t next_to_use_masked = next_to_use & ring_mask;
1152                 struct rte_mbuf *mbuf = mbufs[next_to_use_masked];
1153                 struct ena_com_buf ebuf;
1154
1155                 rte_prefetch0(mbufs[((next_to_use + 4) & ring_mask)]);
1156                 /* prepare physical address for DMA transaction */
1157                 ebuf.paddr = mbuf->buf_physaddr + RTE_PKTMBUF_HEADROOM;
1158                 ebuf.len = mbuf->buf_len - RTE_PKTMBUF_HEADROOM;
1159                 /* pass resource to device */
1160                 rc = ena_com_add_single_rx_desc(rxq->ena_com_io_sq,
1161                                                 &ebuf, next_to_use_masked);
1162                 if (unlikely(rc)) {
1163                         rte_mempool_put_bulk(rxq->mb_pool, (void **)(&mbuf),
1164                                              count - i);
1165                         RTE_LOG(WARNING, PMD, "failed adding rx desc\n");
1166                         break;
1167                 }
1168                 next_to_use++;
1169         }
1170
1171         /* When we submitted free recources to device... */
1172         if (i > 0) {
1173                 /* ...let HW know that it can fill buffers with data */
1174                 rte_wmb();
1175                 ena_com_write_sq_doorbell(rxq->ena_com_io_sq);
1176
1177                 rxq->next_to_use = next_to_use;
1178         }
1179
1180         return i;
1181 }
1182
1183 static int ena_device_init(struct ena_com_dev *ena_dev,
1184                            struct ena_com_dev_get_features_ctx *get_feat_ctx)
1185 {
1186         int rc;
1187         bool readless_supported;
1188
1189         /* Initialize mmio registers */
1190         rc = ena_com_mmio_reg_read_request_init(ena_dev);
1191         if (rc) {
1192                 RTE_LOG(ERR, PMD, "failed to init mmio read less\n");
1193                 return rc;
1194         }
1195
1196         /* The PCIe configuration space revision id indicate if mmio reg
1197          * read is disabled.
1198          */
1199         readless_supported =
1200                 !(((struct rte_pci_device *)ena_dev->dmadev)->id.class_id
1201                                & ENA_MMIO_DISABLE_REG_READ);
1202         ena_com_set_mmio_read_mode(ena_dev, readless_supported);
1203
1204         /* reset device */
1205         rc = ena_com_dev_reset(ena_dev);
1206         if (rc) {
1207                 RTE_LOG(ERR, PMD, "cannot reset device\n");
1208                 goto err_mmio_read_less;
1209         }
1210
1211         /* check FW version */
1212         rc = ena_com_validate_version(ena_dev);
1213         if (rc) {
1214                 RTE_LOG(ERR, PMD, "device version is too low\n");
1215                 goto err_mmio_read_less;
1216         }
1217
1218         ena_dev->dma_addr_bits = ena_com_get_dma_width(ena_dev);
1219
1220         /* ENA device administration layer init */
1221         rc = ena_com_admin_init(ena_dev, NULL, true);
1222         if (rc) {
1223                 RTE_LOG(ERR, PMD,
1224                         "cannot initialize ena admin queue with device\n");
1225                 goto err_mmio_read_less;
1226         }
1227
1228         /* To enable the msix interrupts the driver needs to know the number
1229          * of queues. So the driver uses polling mode to retrieve this
1230          * information.
1231          */
1232         ena_com_set_admin_polling_mode(ena_dev, true);
1233
1234         ena_config_host_info(ena_dev);
1235
1236         /* Get Device Attributes and features */
1237         rc = ena_com_get_dev_attr_feat(ena_dev, get_feat_ctx);
1238         if (rc) {
1239                 RTE_LOG(ERR, PMD,
1240                         "cannot get attribute for ena device rc= %d\n", rc);
1241                 goto err_admin_init;
1242         }
1243
1244         return 0;
1245
1246 err_admin_init:
1247         ena_com_admin_destroy(ena_dev);
1248
1249 err_mmio_read_less:
1250         ena_com_mmio_reg_read_request_destroy(ena_dev);
1251
1252         return rc;
1253 }
1254
1255 static int eth_ena_dev_init(struct rte_eth_dev *eth_dev)
1256 {
1257         struct rte_pci_device *pci_dev;
1258         struct ena_adapter *adapter =
1259                 (struct ena_adapter *)(eth_dev->data->dev_private);
1260         struct ena_com_dev *ena_dev = &adapter->ena_dev;
1261         struct ena_com_dev_get_features_ctx get_feat_ctx;
1262         int queue_size, rc;
1263
1264         static int adapters_found;
1265
1266         memset(adapter, 0, sizeof(struct ena_adapter));
1267         ena_dev = &adapter->ena_dev;
1268
1269         eth_dev->dev_ops = &ena_dev_ops;
1270         eth_dev->rx_pkt_burst = &eth_ena_recv_pkts;
1271         eth_dev->tx_pkt_burst = &eth_ena_xmit_pkts;
1272         adapter->rte_eth_dev_data = eth_dev->data;
1273         adapter->rte_dev = eth_dev;
1274
1275         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1276                 return 0;
1277
1278         pci_dev = eth_dev->pci_dev;
1279         adapter->pdev = pci_dev;
1280
1281         PMD_INIT_LOG(INFO, "Initializing %x:%x:%x.%d\n",
1282                      pci_dev->addr.domain,
1283                      pci_dev->addr.bus,
1284                      pci_dev->addr.devid,
1285                      pci_dev->addr.function);
1286
1287         adapter->regs = pci_dev->mem_resource[ENA_REGS_BAR].addr;
1288         adapter->dev_mem_base = pci_dev->mem_resource[ENA_MEM_BAR].addr;
1289
1290         /* Present ENA_MEM_BAR indicates available LLQ mode.
1291          * Use corresponding policy
1292          */
1293         if (adapter->dev_mem_base)
1294                 ena_dev->tx_mem_queue_type = ENA_ADMIN_PLACEMENT_POLICY_DEV;
1295         else if (adapter->regs)
1296                 ena_dev->tx_mem_queue_type = ENA_ADMIN_PLACEMENT_POLICY_HOST;
1297         else
1298                 PMD_INIT_LOG(CRIT, "Failed to access registers BAR(%d)\n",
1299                              ENA_REGS_BAR);
1300
1301         ena_dev->reg_bar = adapter->regs;
1302         ena_dev->dmadev = adapter->pdev;
1303
1304         adapter->id_number = adapters_found;
1305
1306         snprintf(adapter->name, ENA_NAME_MAX_LEN, "ena_%d",
1307                  adapter->id_number);
1308
1309         /* device specific initialization routine */
1310         rc = ena_device_init(ena_dev, &get_feat_ctx);
1311         if (rc) {
1312                 PMD_INIT_LOG(CRIT, "Failed to init ENA device\n");
1313                 return -1;
1314         }
1315
1316         if (ena_dev->tx_mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_DEV) {
1317                 if (get_feat_ctx.max_queues.max_llq_num == 0) {
1318                         PMD_INIT_LOG(ERR,
1319                                      "Trying to use LLQ but llq_num is 0.\n"
1320                                      "Fall back into regular queues.\n");
1321                         ena_dev->tx_mem_queue_type =
1322                                 ENA_ADMIN_PLACEMENT_POLICY_HOST;
1323                         adapter->num_queues =
1324                                 get_feat_ctx.max_queues.max_sq_num;
1325                 } else {
1326                         adapter->num_queues =
1327                                 get_feat_ctx.max_queues.max_llq_num;
1328                 }
1329         } else {
1330                 adapter->num_queues = get_feat_ctx.max_queues.max_sq_num;
1331         }
1332
1333         queue_size = ena_calc_queue_size(ena_dev, &get_feat_ctx);
1334         if ((queue_size <= 0) || (adapter->num_queues <= 0))
1335                 return -EFAULT;
1336
1337         adapter->tx_ring_size = queue_size;
1338         adapter->rx_ring_size = queue_size;
1339
1340         /* prepare ring structures */
1341         ena_init_rings(adapter);
1342
1343         ena_config_debug_area(adapter);
1344
1345         /* Set max MTU for this device */
1346         adapter->max_mtu = get_feat_ctx.dev_attr.max_mtu;
1347
1348         /* Copy MAC address and point DPDK to it */
1349         eth_dev->data->mac_addrs = (struct ether_addr *)adapter->mac_addr;
1350         ether_addr_copy((struct ether_addr *)get_feat_ctx.dev_attr.mac_addr,
1351                         (struct ether_addr *)adapter->mac_addr);
1352
1353         adapter->drv_stats = rte_zmalloc("adapter stats",
1354                                          sizeof(*adapter->drv_stats),
1355                                          RTE_CACHE_LINE_SIZE);
1356         if (!adapter->drv_stats) {
1357                 RTE_LOG(ERR, PMD, "failed to alloc mem for adapter stats\n");
1358                 return -ENOMEM;
1359         }
1360
1361         adapters_found++;
1362         adapter->state = ENA_ADAPTER_STATE_INIT;
1363
1364         return 0;
1365 }
1366
1367 static int ena_dev_configure(struct rte_eth_dev *dev)
1368 {
1369         struct ena_adapter *adapter =
1370                 (struct ena_adapter *)(dev->data->dev_private);
1371
1372         if (!(adapter->state == ENA_ADAPTER_STATE_INIT ||
1373               adapter->state == ENA_ADAPTER_STATE_STOPPED)) {
1374                 PMD_INIT_LOG(ERR, "Illegal adapter state: %d\n",
1375                              adapter->state);
1376                 return -1;
1377         }
1378
1379         switch (adapter->state) {
1380         case ENA_ADAPTER_STATE_INIT:
1381         case ENA_ADAPTER_STATE_STOPPED:
1382                 adapter->state = ENA_ADAPTER_STATE_CONFIG;
1383                 break;
1384         case ENA_ADAPTER_STATE_CONFIG:
1385                 RTE_LOG(WARNING, PMD,
1386                         "Ivalid driver state while trying to configure device\n");
1387                 break;
1388         default:
1389                 break;
1390         }
1391
1392         return 0;
1393 }
1394
1395 static void ena_init_rings(struct ena_adapter *adapter)
1396 {
1397         int i;
1398
1399         for (i = 0; i < adapter->num_queues; i++) {
1400                 struct ena_ring *ring = &adapter->tx_ring[i];
1401
1402                 ring->configured = 0;
1403                 ring->type = ENA_RING_TYPE_TX;
1404                 ring->adapter = adapter;
1405                 ring->id = i;
1406                 ring->tx_mem_queue_type = adapter->ena_dev.tx_mem_queue_type;
1407                 ring->tx_max_header_size = adapter->ena_dev.tx_max_header_size;
1408         }
1409
1410         for (i = 0; i < adapter->num_queues; i++) {
1411                 struct ena_ring *ring = &adapter->rx_ring[i];
1412
1413                 ring->configured = 0;
1414                 ring->type = ENA_RING_TYPE_RX;
1415                 ring->adapter = adapter;
1416                 ring->id = i;
1417         }
1418 }
1419
1420 static void ena_infos_get(struct rte_eth_dev *dev,
1421                           struct rte_eth_dev_info *dev_info)
1422 {
1423         struct ena_adapter *adapter;
1424         struct ena_com_dev *ena_dev;
1425         struct ena_com_dev_get_features_ctx feat;
1426         uint32_t rx_feat = 0, tx_feat = 0;
1427         int rc = 0;
1428
1429         ena_assert_msg(dev->data != NULL, "Uninitialized device");
1430         ena_assert_msg(dev->data->dev_private != NULL, "Uninitialized device");
1431         adapter = (struct ena_adapter *)(dev->data->dev_private);
1432
1433         ena_dev = &adapter->ena_dev;
1434         ena_assert_msg(ena_dev != NULL, "Uninitialized device");
1435
1436         dev_info->speed_capa =
1437                         ETH_LINK_SPEED_1G   |
1438                         ETH_LINK_SPEED_2_5G |
1439                         ETH_LINK_SPEED_5G   |
1440                         ETH_LINK_SPEED_10G  |
1441                         ETH_LINK_SPEED_25G  |
1442                         ETH_LINK_SPEED_40G  |
1443                         ETH_LINK_SPEED_50G  |
1444                         ETH_LINK_SPEED_100G;
1445
1446         /* Get supported features from HW */
1447         rc = ena_com_get_dev_attr_feat(ena_dev, &feat);
1448         if (unlikely(rc)) {
1449                 RTE_LOG(ERR, PMD,
1450                         "Cannot get attribute for ena device rc= %d\n", rc);
1451                 return;
1452         }
1453
1454         /* Set Tx & Rx features available for device */
1455         if (feat.offload.tx & ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_IPV4_MASK)
1456                 tx_feat |= DEV_TX_OFFLOAD_TCP_TSO;
1457
1458         if (feat.offload.tx &
1459             ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV4_CSUM_PART_MASK)
1460                 tx_feat |= DEV_TX_OFFLOAD_IPV4_CKSUM |
1461                         DEV_TX_OFFLOAD_UDP_CKSUM |
1462                         DEV_TX_OFFLOAD_TCP_CKSUM;
1463
1464         if (feat.offload.tx &
1465             ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L4_IPV4_CSUM_MASK)
1466                 rx_feat |= DEV_RX_OFFLOAD_IPV4_CKSUM |
1467                         DEV_RX_OFFLOAD_UDP_CKSUM  |
1468                         DEV_RX_OFFLOAD_TCP_CKSUM;
1469
1470         /* Inform framework about available features */
1471         dev_info->rx_offload_capa = rx_feat;
1472         dev_info->tx_offload_capa = tx_feat;
1473
1474         dev_info->min_rx_bufsize = ENA_MIN_FRAME_LEN;
1475         dev_info->max_rx_pktlen  = adapter->max_mtu;
1476         dev_info->max_mac_addrs = 1;
1477
1478         dev_info->max_rx_queues = adapter->num_queues;
1479         dev_info->max_tx_queues = adapter->num_queues;
1480         dev_info->reta_size = ENA_RX_RSS_TABLE_SIZE;
1481 }
1482
1483 static uint16_t eth_ena_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,
1484                                   uint16_t nb_pkts)
1485 {
1486         struct ena_ring *rx_ring = (struct ena_ring *)(rx_queue);
1487         unsigned int ring_size = rx_ring->ring_size;
1488         unsigned int ring_mask = ring_size - 1;
1489         uint16_t next_to_clean = rx_ring->next_to_clean;
1490         uint16_t desc_in_use = 0;
1491         unsigned int recv_idx = 0;
1492         struct rte_mbuf *mbuf = NULL;
1493         struct rte_mbuf *mbuf_head = NULL;
1494         struct rte_mbuf *mbuf_prev = NULL;
1495         struct rte_mbuf **rx_buff_info = rx_ring->rx_buffer_info;
1496         unsigned int completed;
1497
1498         struct ena_com_rx_ctx ena_rx_ctx;
1499         int rc = 0;
1500
1501         /* Check adapter state */
1502         if (unlikely(rx_ring->adapter->state != ENA_ADAPTER_STATE_RUNNING)) {
1503                 RTE_LOG(ALERT, PMD,
1504                         "Trying to receive pkts while device is NOT running\n");
1505                 return 0;
1506         }
1507
1508         desc_in_use = rx_ring->next_to_use - next_to_clean;
1509         if (unlikely(nb_pkts > desc_in_use))
1510                 nb_pkts = desc_in_use;
1511
1512         for (completed = 0; completed < nb_pkts; completed++) {
1513                 int segments = 0;
1514
1515                 ena_rx_ctx.max_bufs = rx_ring->ring_size;
1516                 ena_rx_ctx.ena_bufs = rx_ring->ena_bufs;
1517                 ena_rx_ctx.descs = 0;
1518                 /* receive packet context */
1519                 rc = ena_com_rx_pkt(rx_ring->ena_com_io_cq,
1520                                     rx_ring->ena_com_io_sq,
1521                                     &ena_rx_ctx);
1522                 if (unlikely(rc)) {
1523                         RTE_LOG(ERR, PMD, "ena_com_rx_pkt error %d\n", rc);
1524                         return 0;
1525                 }
1526
1527                 if (unlikely(ena_rx_ctx.descs == 0))
1528                         break;
1529
1530                 while (segments < ena_rx_ctx.descs) {
1531                         mbuf = rx_buff_info[next_to_clean & ring_mask];
1532                         mbuf->data_len = ena_rx_ctx.ena_bufs[segments].len;
1533                         mbuf->data_off = RTE_PKTMBUF_HEADROOM;
1534                         mbuf->refcnt = 1;
1535                         mbuf->next = NULL;
1536                         if (segments == 0) {
1537                                 mbuf->nb_segs = ena_rx_ctx.descs;
1538                                 mbuf->port = rx_ring->port_id;
1539                                 mbuf->pkt_len = 0;
1540                                 mbuf_head = mbuf;
1541                         } else {
1542                                 /* for multi-segment pkts create mbuf chain */
1543                                 mbuf_prev->next = mbuf;
1544                         }
1545                         mbuf_head->pkt_len += mbuf->data_len;
1546
1547                         mbuf_prev = mbuf;
1548                         segments++;
1549                         next_to_clean++;
1550                 }
1551
1552                 /* fill mbuf attributes if any */
1553                 ena_rx_mbuf_prepare(mbuf_head, &ena_rx_ctx);
1554                 mbuf_head->hash.rss = (uint32_t)rx_ring->id;
1555
1556                 /* pass to DPDK application head mbuf */
1557                 rx_pkts[recv_idx] = mbuf_head;
1558                 recv_idx++;
1559         }
1560
1561         rx_ring->next_to_clean = next_to_clean;
1562
1563         desc_in_use = desc_in_use - completed + 1;
1564         /* Burst refill to save doorbells, memory barriers, const interval */
1565         if (ring_size - desc_in_use > ENA_RING_DESCS_RATIO(ring_size))
1566                 ena_populate_rx_queue(rx_ring, ring_size - desc_in_use);
1567
1568         return recv_idx;
1569 }
1570
1571 static uint16_t eth_ena_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
1572                                   uint16_t nb_pkts)
1573 {
1574         struct ena_ring *tx_ring = (struct ena_ring *)(tx_queue);
1575         uint16_t next_to_use = tx_ring->next_to_use;
1576         uint16_t next_to_clean = tx_ring->next_to_clean;
1577         struct rte_mbuf *mbuf;
1578         unsigned int ring_size = tx_ring->ring_size;
1579         unsigned int ring_mask = ring_size - 1;
1580         struct ena_com_tx_ctx ena_tx_ctx;
1581         struct ena_tx_buffer *tx_info;
1582         struct ena_com_buf *ebuf;
1583         uint16_t rc, req_id, total_tx_descs = 0;
1584         uint16_t sent_idx = 0, empty_tx_reqs;
1585         int nb_hw_desc;
1586
1587         /* Check adapter state */
1588         if (unlikely(tx_ring->adapter->state != ENA_ADAPTER_STATE_RUNNING)) {
1589                 RTE_LOG(ALERT, PMD,
1590                         "Trying to xmit pkts while device is NOT running\n");
1591                 return 0;
1592         }
1593
1594         empty_tx_reqs = ring_size - (next_to_use - next_to_clean);
1595         if (nb_pkts > empty_tx_reqs)
1596                 nb_pkts = empty_tx_reqs;
1597
1598         for (sent_idx = 0; sent_idx < nb_pkts; sent_idx++) {
1599                 mbuf = tx_pkts[sent_idx];
1600
1601                 req_id = tx_ring->empty_tx_reqs[next_to_use & ring_mask];
1602                 tx_info = &tx_ring->tx_buffer_info[req_id];
1603                 tx_info->mbuf = mbuf;
1604                 tx_info->num_of_bufs = 0;
1605                 ebuf = tx_info->bufs;
1606
1607                 /* Prepare TX context */
1608                 memset(&ena_tx_ctx, 0x0, sizeof(struct ena_com_tx_ctx));
1609                 memset(&ena_tx_ctx.ena_meta, 0x0,
1610                        sizeof(struct ena_com_tx_meta));
1611                 ena_tx_ctx.ena_bufs = ebuf;
1612                 ena_tx_ctx.req_id = req_id;
1613                 if (tx_ring->tx_mem_queue_type ==
1614                                 ENA_ADMIN_PLACEMENT_POLICY_DEV) {
1615                         /* prepare the push buffer with
1616                          * virtual address of the data
1617                          */
1618                         ena_tx_ctx.header_len =
1619                                 RTE_MIN(mbuf->data_len,
1620                                         tx_ring->tx_max_header_size);
1621                         ena_tx_ctx.push_header =
1622                                 (void *)((char *)mbuf->buf_addr +
1623                                          mbuf->data_off);
1624                 } /* there's no else as we take advantage of memset zeroing */
1625
1626                 /* Set TX offloads flags, if applicable */
1627                 ena_tx_mbuf_prepare(mbuf, &ena_tx_ctx);
1628
1629                 if (unlikely(mbuf->ol_flags &
1630                              (PKT_RX_L4_CKSUM_BAD | PKT_RX_IP_CKSUM_BAD)))
1631                         rte_atomic64_inc(&tx_ring->adapter->drv_stats->ierrors);
1632
1633                 rte_prefetch0(tx_pkts[(sent_idx + 4) & ring_mask]);
1634
1635                 /* Process first segment taking into
1636                  * consideration pushed header
1637                  */
1638                 if (mbuf->data_len > ena_tx_ctx.header_len) {
1639                         ebuf->paddr = mbuf->buf_physaddr +
1640                                       mbuf->data_off +
1641                                       ena_tx_ctx.header_len;
1642                         ebuf->len = mbuf->data_len - ena_tx_ctx.header_len;
1643                         ebuf++;
1644                         tx_info->num_of_bufs++;
1645                 }
1646
1647                 while ((mbuf = mbuf->next) != NULL) {
1648                         ebuf->paddr = mbuf->buf_physaddr + mbuf->data_off;
1649                         ebuf->len = mbuf->data_len;
1650                         ebuf++;
1651                         tx_info->num_of_bufs++;
1652                 }
1653
1654                 ena_tx_ctx.num_bufs = tx_info->num_of_bufs;
1655
1656                 /* Write data to device */
1657                 rc = ena_com_prepare_tx(tx_ring->ena_com_io_sq,
1658                                         &ena_tx_ctx, &nb_hw_desc);
1659                 if (unlikely(rc))
1660                         break;
1661
1662                 tx_info->tx_descs = nb_hw_desc;
1663
1664                 next_to_use++;
1665         }
1666
1667         /* If there are ready packets to be xmitted... */
1668         if (sent_idx > 0) {
1669                 /* ...let HW do its best :-) */
1670                 rte_wmb();
1671                 ena_com_write_sq_doorbell(tx_ring->ena_com_io_sq);
1672
1673                 tx_ring->next_to_use = next_to_use;
1674         }
1675
1676         /* Clear complete packets  */
1677         while (ena_com_tx_comp_req_id_get(tx_ring->ena_com_io_cq, &req_id) >= 0) {
1678                 /* Get Tx info & store how many descs were processed  */
1679                 tx_info = &tx_ring->tx_buffer_info[req_id];
1680                 total_tx_descs += tx_info->tx_descs;
1681
1682                 /* Free whole mbuf chain  */
1683                 mbuf = tx_info->mbuf;
1684                 rte_pktmbuf_free(mbuf);
1685                 tx_info->mbuf = NULL;
1686
1687                 /* Put back descriptor to the ring for reuse */
1688                 tx_ring->empty_tx_reqs[next_to_clean & ring_mask] = req_id;
1689                 next_to_clean++;
1690
1691                 /* If too many descs to clean, leave it for another run */
1692                 if (unlikely(total_tx_descs > ENA_RING_DESCS_RATIO(ring_size)))
1693                         break;
1694         }
1695
1696         if (total_tx_descs > 0) {
1697                 /* acknowledge completion of sent packets */
1698                 ena_com_comp_ack(tx_ring->ena_com_io_sq, total_tx_descs);
1699                 tx_ring->next_to_clean = next_to_clean;
1700         }
1701
1702         return sent_idx;
1703 }
1704
1705 static struct eth_driver rte_ena_pmd = {
1706         .pci_drv = {
1707                 .id_table = pci_id_ena_map,
1708                 .drv_flags = RTE_PCI_DRV_NEED_MAPPING,
1709                 .probe = rte_eth_dev_pci_probe,
1710                 .remove = rte_eth_dev_pci_remove,
1711         },
1712         .eth_dev_init = eth_ena_dev_init,
1713         .dev_private_size = sizeof(struct ena_adapter),
1714 };
1715
1716 RTE_PMD_REGISTER_PCI(net_ena, rte_ena_pmd.pci_drv);
1717 RTE_PMD_REGISTER_PCI_TABLE(net_ena, pci_id_ena_map);