drivers/net/ena/ena_ethdev.c

   1 /*-
   2 * BSD LICENSE
   3 *
   4 * Copyright (c) 2015-2016 Amazon.com, Inc. or its affiliates.
   5 * All rights reserved.
   6 *
   7 * Redistribution and use in source and binary forms, with or without
   8 * modification, are permitted provided that the following conditions
   9 * are met:
  10 *
  11 * * Redistributions of source code must retain the above copyright
  12 * notice, this list of conditions and the following disclaimer.
  13 * * Redistributions in binary form must reproduce the above copyright
  14 * notice, this list of conditions and the following disclaimer in
  15 * the documentation and/or other materials provided with the
  16 * distribution.
  17 * * Neither the name of copyright holder nor the names of its
  18 * contributors may be used to endorse or promote products derived
  19 * from this software without specific prior written permission.
  20 *
  21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32 */
  33
  34 #include <rte_ether.h>
  35 #include <rte_ethdev.h>
  36 #include <rte_ethdev_pci.h>
  37 #include <rte_tcp.h>
  38 #include <rte_atomic.h>
  39 #include <rte_dev.h>
  40 #include <rte_errno.h>
  41 #include <rte_version.h>
  42 #include <rte_eal_memconfig.h>
  43 #include <rte_net.h>
  44
  45 #include "ena_ethdev.h"
  46 #include "ena_logs.h"
  47 #include "ena_platform.h"
  48 #include "ena_com.h"
  49 #include "ena_eth_com.h"
  50
  51 #include <ena_common_defs.h>
  52 #include <ena_regs_defs.h>
  53 #include <ena_admin_defs.h>
  54 #include <ena_eth_io_defs.h>
  55
  56 #define DRV_MODULE_VER_MAJOR    1
  57 #define DRV_MODULE_VER_MINOR    0
  58 #define DRV_MODULE_VER_SUBMINOR 0
  59
  60 #define ENA_IO_TXQ_IDX(q)       (2 * (q))
  61 #define ENA_IO_RXQ_IDX(q)       (2 * (q) + 1)
  62 /*reverse version of ENA_IO_RXQ_IDX*/
  63 #define ENA_IO_RXQ_IDX_REV(q)   ((q - 1) / 2)
  64
  65 /* While processing submitted and completed descriptors (rx and tx path
  66  * respectively) in a loop it is desired to:
  67  *  - perform batch submissions while populating sumbissmion queue
  68  *  - avoid blocking transmission of other packets during cleanup phase
  69  * Hence the utilization ratio of 1/8 of a queue size.
  70  */
  71 #define ENA_RING_DESCS_RATIO(ring_size) (ring_size / 8)
  72
  73 #define __MERGE_64B_H_L(h, l) (((uint64_t)h << 32) | l)
  74 #define TEST_BIT(val, bit_shift) (val & (1UL << bit_shift))
  75
  76 #define GET_L4_HDR_LEN(mbuf)                                    \
  77         ((rte_pktmbuf_mtod_offset(mbuf, struct tcp_hdr *,       \
  78                 mbuf->l3_len + mbuf->l2_len)->data_off) >> 4)
  79
  80 #define ENA_RX_RSS_TABLE_LOG_SIZE  7
  81 #define ENA_RX_RSS_TABLE_SIZE   (1 << ENA_RX_RSS_TABLE_LOG_SIZE)
  82 #define ENA_HASH_KEY_SIZE       40
  83 #define ENA_ETH_SS_STATS        0xFF
  84 #define ETH_GSTRING_LEN 32
  85
  86 #define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
  87
  88 enum ethtool_stringset {
  89         ETH_SS_TEST             = 0,
  90         ETH_SS_STATS,
  91 };
  92
  93 struct ena_stats {
  94         char name[ETH_GSTRING_LEN];
  95         int stat_offset;
  96 };
  97
  98 #define ENA_STAT_ENA_COM_ENTRY(stat) { \
  99         .name = #stat, \
 100         .stat_offset = offsetof(struct ena_com_stats_admin, stat) \
 101 }
 102
 103 #define ENA_STAT_ENTRY(stat, stat_type) { \
 104         .name = #stat, \
 105         .stat_offset = offsetof(struct ena_stats_##stat_type, stat) \
 106 }
 107
 108 #define ENA_STAT_RX_ENTRY(stat) \
 109         ENA_STAT_ENTRY(stat, rx)
 110
 111 #define ENA_STAT_TX_ENTRY(stat) \
 112         ENA_STAT_ENTRY(stat, tx)
 113
 114 #define ENA_STAT_GLOBAL_ENTRY(stat) \
 115         ENA_STAT_ENTRY(stat, dev)
 116
 117 static const struct ena_stats ena_stats_global_strings[] = {
 118         ENA_STAT_GLOBAL_ENTRY(tx_timeout),
 119         ENA_STAT_GLOBAL_ENTRY(io_suspend),
 120         ENA_STAT_GLOBAL_ENTRY(io_resume),
 121         ENA_STAT_GLOBAL_ENTRY(wd_expired),
 122         ENA_STAT_GLOBAL_ENTRY(interface_up),
 123         ENA_STAT_GLOBAL_ENTRY(interface_down),
 124         ENA_STAT_GLOBAL_ENTRY(admin_q_pause),
 125 };
 126
 127 static const struct ena_stats ena_stats_tx_strings[] = {
 128         ENA_STAT_TX_ENTRY(cnt),
 129         ENA_STAT_TX_ENTRY(bytes),
 130         ENA_STAT_TX_ENTRY(queue_stop),
 131         ENA_STAT_TX_ENTRY(queue_wakeup),
 132         ENA_STAT_TX_ENTRY(dma_mapping_err),
 133         ENA_STAT_TX_ENTRY(linearize),
 134         ENA_STAT_TX_ENTRY(linearize_failed),
 135         ENA_STAT_TX_ENTRY(tx_poll),
 136         ENA_STAT_TX_ENTRY(doorbells),
 137         ENA_STAT_TX_ENTRY(prepare_ctx_err),
 138         ENA_STAT_TX_ENTRY(missing_tx_comp),
 139         ENA_STAT_TX_ENTRY(bad_req_id),
 140 };
 141
 142 static const struct ena_stats ena_stats_rx_strings[] = {
 143         ENA_STAT_RX_ENTRY(cnt),
 144         ENA_STAT_RX_ENTRY(bytes),
 145         ENA_STAT_RX_ENTRY(refil_partial),
 146         ENA_STAT_RX_ENTRY(bad_csum),
 147         ENA_STAT_RX_ENTRY(page_alloc_fail),
 148         ENA_STAT_RX_ENTRY(skb_alloc_fail),
 149         ENA_STAT_RX_ENTRY(dma_mapping_err),
 150         ENA_STAT_RX_ENTRY(bad_desc_num),
 151         ENA_STAT_RX_ENTRY(small_copy_len_pkt),
 152 };
 153
 154 static const struct ena_stats ena_stats_ena_com_strings[] = {
 155         ENA_STAT_ENA_COM_ENTRY(aborted_cmd),
 156         ENA_STAT_ENA_COM_ENTRY(submitted_cmd),
 157         ENA_STAT_ENA_COM_ENTRY(completed_cmd),
 158         ENA_STAT_ENA_COM_ENTRY(out_of_space),
 159         ENA_STAT_ENA_COM_ENTRY(no_completion),
 160 };
 161
 162 #define ENA_STATS_ARRAY_GLOBAL  ARRAY_SIZE(ena_stats_global_strings)
 163 #define ENA_STATS_ARRAY_TX      ARRAY_SIZE(ena_stats_tx_strings)
 164 #define ENA_STATS_ARRAY_RX      ARRAY_SIZE(ena_stats_rx_strings)
 165 #define ENA_STATS_ARRAY_ENA_COM ARRAY_SIZE(ena_stats_ena_com_strings)
 166
 167 /** Vendor ID used by Amazon devices */
 168 #define PCI_VENDOR_ID_AMAZON 0x1D0F
 169 /** Amazon devices */
 170 #define PCI_DEVICE_ID_ENA_VF    0xEC20
 171 #define PCI_DEVICE_ID_ENA_LLQ_VF        0xEC21
 172
 173 #define ENA_TX_OFFLOAD_MASK     (\
 174         PKT_TX_L4_MASK |         \
 175         PKT_TX_IP_CKSUM |        \
 176         PKT_TX_TCP_SEG)
 177
 178 #define ENA_TX_OFFLOAD_NOTSUP_MASK      \
 179         (PKT_TX_OFFLOAD_MASK ^ ENA_TX_OFFLOAD_MASK)
 180
 181 static const struct rte_pci_id pci_id_ena_map[] = {
 182         { RTE_PCI_DEVICE(PCI_VENDOR_ID_AMAZON, PCI_DEVICE_ID_ENA_VF) },
 183         { RTE_PCI_DEVICE(PCI_VENDOR_ID_AMAZON, PCI_DEVICE_ID_ENA_LLQ_VF) },
 184         { .device_id = 0 },
 185 };
 186
 187 static int ena_device_init(struct ena_com_dev *ena_dev,
 188                            struct ena_com_dev_get_features_ctx *get_feat_ctx);
 189 static int ena_dev_configure(struct rte_eth_dev *dev);
 190 static uint16_t eth_ena_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
 191                                   uint16_t nb_pkts);
 192 static uint16_t eth_ena_prep_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
 193                 uint16_t nb_pkts);
 194 static int ena_tx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,
 195                               uint16_t nb_desc, unsigned int socket_id,
 196                               const struct rte_eth_txconf *tx_conf);
 197 static int ena_rx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,
 198                               uint16_t nb_desc, unsigned int socket_id,
 199                               const struct rte_eth_rxconf *rx_conf,
 200                               struct rte_mempool *mp);
 201 static uint16_t eth_ena_recv_pkts(void *rx_queue,
 202                                   struct rte_mbuf **rx_pkts, uint16_t nb_pkts);
 203 static int ena_populate_rx_queue(struct ena_ring *rxq, unsigned int count);
 204 static void ena_init_rings(struct ena_adapter *adapter);
 205 static int ena_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
 206 static int ena_start(struct rte_eth_dev *dev);
 207 static void ena_close(struct rte_eth_dev *dev);
 208 static void ena_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats);
 209 static void ena_rx_queue_release_all(struct rte_eth_dev *dev);
 210 static void ena_tx_queue_release_all(struct rte_eth_dev *dev);
 211 static void ena_rx_queue_release(void *queue);
 212 static void ena_tx_queue_release(void *queue);
 213 static void ena_rx_queue_release_bufs(struct ena_ring *ring);
 214 static void ena_tx_queue_release_bufs(struct ena_ring *ring);
 215 static int ena_link_update(struct rte_eth_dev *dev,
 216                            __rte_unused int wait_to_complete);
 217 static int ena_queue_restart(struct ena_ring *ring);
 218 static int ena_queue_restart_all(struct rte_eth_dev *dev,
 219                                  enum ena_ring_type ring_type);
 220 static void ena_stats_restart(struct rte_eth_dev *dev);
 221 static void ena_infos_get(__rte_unused struct rte_eth_dev *dev,
 222                           struct rte_eth_dev_info *dev_info);
 223 static int ena_rss_reta_update(struct rte_eth_dev *dev,
 224                                struct rte_eth_rss_reta_entry64 *reta_conf,
 225                                uint16_t reta_size);
 226 static int ena_rss_reta_query(struct rte_eth_dev *dev,
 227                               struct rte_eth_rss_reta_entry64 *reta_conf,
 228                               uint16_t reta_size);
 229 static int ena_get_sset_count(struct rte_eth_dev *dev, int sset);
 230
 231 static const struct eth_dev_ops ena_dev_ops = {
 232         .dev_configure        = ena_dev_configure,
 233         .dev_infos_get        = ena_infos_get,
 234         .rx_queue_setup       = ena_rx_queue_setup,
 235         .tx_queue_setup       = ena_tx_queue_setup,
 236         .dev_start            = ena_start,
 237         .link_update          = ena_link_update,
 238         .stats_get            = ena_stats_get,
 239         .mtu_set              = ena_mtu_set,
 240         .rx_queue_release     = ena_rx_queue_release,
 241         .tx_queue_release     = ena_tx_queue_release,
 242         .dev_close            = ena_close,
 243         .reta_update          = ena_rss_reta_update,
 244         .reta_query           = ena_rss_reta_query,
 245 };
 246
 247 #define NUMA_NO_NODE    SOCKET_ID_ANY
 248
 249 static inline int ena_cpu_to_node(int cpu)
 250 {
 251         struct rte_config *config = rte_eal_get_configuration();
 252
 253         if (likely(cpu < RTE_MAX_MEMZONE))
 254                 return config->mem_config->memzone[cpu].socket_id;
 255
 256         return NUMA_NO_NODE;
 257 }
 258
 259 static inline void ena_rx_mbuf_prepare(struct rte_mbuf *mbuf,
 260                                        struct ena_com_rx_ctx *ena_rx_ctx)
 261 {
 262         uint64_t ol_flags = 0;
 263
 264         if (ena_rx_ctx->l4_proto == ENA_ETH_IO_L4_PROTO_TCP)
 265                 ol_flags |= PKT_TX_TCP_CKSUM;
 266         else if (ena_rx_ctx->l4_proto == ENA_ETH_IO_L4_PROTO_UDP)
 267                 ol_flags |= PKT_TX_UDP_CKSUM;
 268
 269         if (ena_rx_ctx->l3_proto == ENA_ETH_IO_L3_PROTO_IPV4)
 270                 ol_flags |= PKT_TX_IPV4;
 271         else if (ena_rx_ctx->l3_proto == ENA_ETH_IO_L3_PROTO_IPV6)
 272                 ol_flags |= PKT_TX_IPV6;
 273
 274         if (unlikely(ena_rx_ctx->l4_csum_err))
 275                 ol_flags |= PKT_RX_L4_CKSUM_BAD;
 276         if (unlikely(ena_rx_ctx->l3_csum_err))
 277                 ol_flags |= PKT_RX_IP_CKSUM_BAD;
 278
 279         mbuf->ol_flags = ol_flags;
 280 }
 281
 282 static inline void ena_tx_mbuf_prepare(struct rte_mbuf *mbuf,
 283                                        struct ena_com_tx_ctx *ena_tx_ctx)
 284 {
 285         struct ena_com_tx_meta *ena_meta = &ena_tx_ctx->ena_meta;
 286
 287         if (mbuf->ol_flags &
 288             (PKT_TX_L4_MASK | PKT_TX_IP_CKSUM | PKT_TX_TCP_SEG)) {
 289                 /* check if TSO is required */
 290                 if (mbuf->ol_flags & PKT_TX_TCP_SEG) {
 291                         ena_tx_ctx->tso_enable = true;
 292
 293                         ena_meta->l4_hdr_len = GET_L4_HDR_LEN(mbuf);
 294                 }
 295
 296                 /* check if L3 checksum is needed */
 297                 if (mbuf->ol_flags & PKT_TX_IP_CKSUM)
 298                         ena_tx_ctx->l3_csum_enable = true;
 299
 300                 if (mbuf->ol_flags & PKT_TX_IPV6) {
 301                         ena_tx_ctx->l3_proto = ENA_ETH_IO_L3_PROTO_IPV6;
 302                 } else {
 303                         ena_tx_ctx->l3_proto = ENA_ETH_IO_L3_PROTO_IPV4;
 304
 305                         /* set don't fragment (DF) flag */
 306                         if (mbuf->packet_type &
 307                                 (RTE_PTYPE_L4_NONFRAG
 308                                  | RTE_PTYPE_INNER_L4_NONFRAG))
 309                                 ena_tx_ctx->df = true;
 310                 }
 311
 312                 /* check if L4 checksum is needed */
 313                 switch (mbuf->ol_flags & PKT_TX_L4_MASK) {
 314                 case PKT_TX_TCP_CKSUM:
 315                         ena_tx_ctx->l4_proto = ENA_ETH_IO_L4_PROTO_TCP;
 316                         ena_tx_ctx->l4_csum_enable = true;
 317                         break;
 318                 case PKT_TX_UDP_CKSUM:
 319                         ena_tx_ctx->l4_proto = ENA_ETH_IO_L4_PROTO_UDP;
 320                         ena_tx_ctx->l4_csum_enable = true;
 321                         break;
 322                 default:
 323                         ena_tx_ctx->l4_proto = ENA_ETH_IO_L4_PROTO_UNKNOWN;
 324                         ena_tx_ctx->l4_csum_enable = false;
 325                         break;
 326                 }
 327
 328                 ena_meta->mss = mbuf->tso_segsz;
 329                 ena_meta->l3_hdr_len = mbuf->l3_len;
 330                 ena_meta->l3_hdr_offset = mbuf->l2_len;
 331                 /* this param needed only for TSO */
 332                 ena_meta->l3_outer_hdr_len = 0;
 333                 ena_meta->l3_outer_hdr_offset = 0;
 334
 335                 ena_tx_ctx->meta_valid = true;
 336         } else {
 337                 ena_tx_ctx->meta_valid = false;
 338         }
 339 }
 340
 341 static void ena_config_host_info(struct ena_com_dev *ena_dev)
 342 {
 343         struct ena_admin_host_info *host_info;
 344         int rc;
 345
 346         /* Allocate only the host info */
 347         rc = ena_com_allocate_host_info(ena_dev);
 348         if (rc) {
 349                 RTE_LOG(ERR, PMD, "Cannot allocate host info\n");
 350                 return;
 351         }
 352
 353         host_info = ena_dev->host_attr.host_info;
 354
 355         host_info->os_type = ENA_ADMIN_OS_DPDK;
 356         host_info->kernel_ver = RTE_VERSION;
 357         snprintf((char *)host_info->kernel_ver_str,
 358                  sizeof(host_info->kernel_ver_str),
 359                  "%s", rte_version());
 360         host_info->os_dist = RTE_VERSION;
 361         snprintf((char *)host_info->os_dist_str,
 362                  sizeof(host_info->os_dist_str),
 363                  "%s", rte_version());
 364         host_info->driver_version =
 365                 (DRV_MODULE_VER_MAJOR) |
 366                 (DRV_MODULE_VER_MINOR << ENA_ADMIN_HOST_INFO_MINOR_SHIFT) |
 367                 (DRV_MODULE_VER_SUBMINOR <<
 368                         ENA_ADMIN_HOST_INFO_SUB_MINOR_SHIFT);
 369
 370         rc = ena_com_set_host_attributes(ena_dev);
 371         if (rc) {
 372                 RTE_LOG(ERR, PMD, "Cannot set host attributes\n");
 373                 if (rc != -EPERM)
 374                         goto err;
 375         }
 376
 377         return;
 378
 379 err:
 380         ena_com_delete_host_info(ena_dev);
 381 }
 382
 383 static int
 384 ena_get_sset_count(struct rte_eth_dev *dev, int sset)
 385 {
 386         if (sset != ETH_SS_STATS)
 387                 return -EOPNOTSUPP;
 388
 389          /* Workaround for clang:
 390          * touch internal structures to prevent
 391          * compiler error
 392          */
 393         ENA_TOUCH(ena_stats_global_strings);
 394         ENA_TOUCH(ena_stats_tx_strings);
 395         ENA_TOUCH(ena_stats_rx_strings);
 396         ENA_TOUCH(ena_stats_ena_com_strings);
 397
 398         return  dev->data->nb_tx_queues *
 399                 (ENA_STATS_ARRAY_TX + ENA_STATS_ARRAY_RX) +
 400                 ENA_STATS_ARRAY_GLOBAL + ENA_STATS_ARRAY_ENA_COM;
 401 }
 402
 403 static void ena_config_debug_area(struct ena_adapter *adapter)
 404 {
 405         u32 debug_area_size;
 406         int rc, ss_count;
 407
 408         ss_count = ena_get_sset_count(adapter->rte_dev, ETH_SS_STATS);
 409         if (ss_count <= 0) {
 410                 RTE_LOG(ERR, PMD, "SS count is negative\n");
 411                 return;
 412         }
 413
 414         /* allocate 32 bytes for each string and 64bit for the value */
 415         debug_area_size = ss_count * ETH_GSTRING_LEN + sizeof(u64) * ss_count;
 416
 417         rc = ena_com_allocate_debug_area(&adapter->ena_dev, debug_area_size);
 418         if (rc) {
 419                 RTE_LOG(ERR, PMD, "Cannot allocate debug area\n");
 420                 return;
 421         }
 422
 423         rc = ena_com_set_host_attributes(&adapter->ena_dev);
 424         if (rc) {
 425                 RTE_LOG(WARNING, PMD, "Cannot set host attributes\n");
 426                 if (rc != -EPERM)
 427                         goto err;
 428         }
 429
 430         return;
 431 err:
 432         ena_com_delete_debug_area(&adapter->ena_dev);
 433 }
 434
 435 static void ena_close(struct rte_eth_dev *dev)
 436 {
 437         struct ena_adapter *adapter =
 438                 (struct ena_adapter *)(dev->data->dev_private);
 439
 440         adapter->state = ENA_ADAPTER_STATE_STOPPED;
 441
 442         ena_rx_queue_release_all(dev);
 443         ena_tx_queue_release_all(dev);
 444 }
 445
 446 static int ena_rss_reta_update(struct rte_eth_dev *dev,
 447                                struct rte_eth_rss_reta_entry64 *reta_conf,
 448                                uint16_t reta_size)
 449 {
 450         struct ena_adapter *adapter =
 451                 (struct ena_adapter *)(dev->data->dev_private);
 452         struct ena_com_dev *ena_dev = &adapter->ena_dev;
 453         int ret, i;
 454         u16 entry_value;
 455         int conf_idx;
 456         int idx;
 457
 458         if ((reta_size == 0) || (reta_conf == NULL))
 459                 return -EINVAL;
 460
 461         if (reta_size > ENA_RX_RSS_TABLE_SIZE) {
 462                 RTE_LOG(WARNING, PMD,
 463                         "indirection table %d is bigger than supported (%d)\n",
 464                         reta_size, ENA_RX_RSS_TABLE_SIZE);
 465                 ret = -EINVAL;
 466                 goto err;
 467         }
 468
 469         for (i = 0 ; i < reta_size ; i++) {
 470                 /* each reta_conf is for 64 entries.
 471                  * to support 128 we use 2 conf of 64
 472                  */
 473                 conf_idx = i / RTE_RETA_GROUP_SIZE;
 474                 idx = i % RTE_RETA_GROUP_SIZE;
 475                 if (TEST_BIT(reta_conf[conf_idx].mask, idx)) {
 476                         entry_value =
 477                                 ENA_IO_RXQ_IDX(reta_conf[conf_idx].reta[idx]);
 478                         ret = ena_com_indirect_table_fill_entry(ena_dev,
 479                                                                 i,
 480                                                                 entry_value);
 481                         if (unlikely(ret && (ret != ENA_COM_PERMISSION))) {
 482                                 RTE_LOG(ERR, PMD,
 483                                         "Cannot fill indirect table\n");
 484                                 ret = -ENOTSUP;
 485                                 goto err;
 486                         }
 487                 }
 488         }
 489
 490         ret = ena_com_indirect_table_set(ena_dev);
 491         if (unlikely(ret && (ret != ENA_COM_PERMISSION))) {
 492                 RTE_LOG(ERR, PMD, "Cannot flush the indirect table\n");
 493                 ret = -ENOTSUP;
 494                 goto err;
 495         }
 496
 497         RTE_LOG(DEBUG, PMD, "%s(): RSS configured %d entries  for port %d\n",
 498                 __func__, reta_size, adapter->rte_dev->data->port_id);
 499 err:
 500         return ret;
 501 }
 502
 503 /* Query redirection table. */
 504 static int ena_rss_reta_query(struct rte_eth_dev *dev,
 505                               struct rte_eth_rss_reta_entry64 *reta_conf,
 506                               uint16_t reta_size)
 507 {
 508         struct ena_adapter *adapter =
 509                 (struct ena_adapter *)(dev->data->dev_private);
 510         struct ena_com_dev *ena_dev = &adapter->ena_dev;
 511         int ret;
 512         int i;
 513         u32 indirect_table[ENA_RX_RSS_TABLE_SIZE] = {0};
 514         int reta_conf_idx;
 515         int reta_idx;
 516
 517         if (reta_size == 0 || reta_conf == NULL ||
 518             (reta_size > RTE_RETA_GROUP_SIZE && ((reta_conf + 1) == NULL)))
 519                 return -EINVAL;
 520
 521         ret = ena_com_indirect_table_get(ena_dev, indirect_table);
 522         if (unlikely(ret && (ret != ENA_COM_PERMISSION))) {
 523                 RTE_LOG(ERR, PMD, "cannot get indirect table\n");
 524                 ret = -ENOTSUP;
 525                 goto err;
 526         }
 527
 528         for (i = 0 ; i < reta_size ; i++) {
 529                 reta_conf_idx = i / RTE_RETA_GROUP_SIZE;
 530                 reta_idx = i % RTE_RETA_GROUP_SIZE;
 531                 if (TEST_BIT(reta_conf[reta_conf_idx].mask, reta_idx))
 532                         reta_conf[reta_conf_idx].reta[reta_idx] =
 533                                 ENA_IO_RXQ_IDX_REV(indirect_table[i]);
 534         }
 535 err:
 536         return ret;
 537 }
 538
 539 static int ena_rss_init_default(struct ena_adapter *adapter)
 540 {
 541         struct ena_com_dev *ena_dev = &adapter->ena_dev;
 542         uint16_t nb_rx_queues = adapter->rte_dev->data->nb_rx_queues;
 543         int rc, i;
 544         u32 val;
 545
 546         rc = ena_com_rss_init(ena_dev, ENA_RX_RSS_TABLE_LOG_SIZE);
 547         if (unlikely(rc)) {
 548                 RTE_LOG(ERR, PMD, "Cannot init indirect table\n");
 549                 goto err_rss_init;
 550         }
 551
 552         for (i = 0; i < ENA_RX_RSS_TABLE_SIZE; i++) {
 553                 val = i % nb_rx_queues;
 554                 rc = ena_com_indirect_table_fill_entry(ena_dev, i,
 555                                                        ENA_IO_RXQ_IDX(val));
 556                 if (unlikely(rc && (rc != ENA_COM_PERMISSION))) {
 557                         RTE_LOG(ERR, PMD, "Cannot fill indirect table\n");
 558                         goto err_fill_indir;
 559                 }
 560         }
 561
 562         rc = ena_com_fill_hash_function(ena_dev, ENA_ADMIN_CRC32, NULL,
 563                                         ENA_HASH_KEY_SIZE, 0xFFFFFFFF);
 564         if (unlikely(rc && (rc != ENA_COM_PERMISSION))) {
 565                 RTE_LOG(INFO, PMD, "Cannot fill hash function\n");
 566                 goto err_fill_indir;
 567         }
 568
 569         rc = ena_com_set_default_hash_ctrl(ena_dev);
 570         if (unlikely(rc && (rc != ENA_COM_PERMISSION))) {
 571                 RTE_LOG(INFO, PMD, "Cannot fill hash control\n");
 572                 goto err_fill_indir;
 573         }
 574
 575         rc = ena_com_indirect_table_set(ena_dev);
 576         if (unlikely(rc && (rc != ENA_COM_PERMISSION))) {
 577                 RTE_LOG(ERR, PMD, "Cannot flush the indirect table\n");
 578                 goto err_fill_indir;
 579         }
 580         RTE_LOG(DEBUG, PMD, "RSS configured for port %d\n",
 581                 adapter->rte_dev->data->port_id);
 582
 583         return 0;
 584
 585 err_fill_indir:
 586         ena_com_rss_destroy(ena_dev);
 587 err_rss_init:
 588
 589         return rc;
 590 }
 591
 592 static void ena_rx_queue_release_all(struct rte_eth_dev *dev)
 593 {
 594         struct ena_ring **queues = (struct ena_ring **)dev->data->rx_queues;
 595         int nb_queues = dev->data->nb_rx_queues;
 596         int i;
 597
 598         for (i = 0; i < nb_queues; i++)
 599                 ena_rx_queue_release(queues[i]);
 600 }
 601
 602 static void ena_tx_queue_release_all(struct rte_eth_dev *dev)
 603 {
 604         struct ena_ring **queues = (struct ena_ring **)dev->data->tx_queues;
 605         int nb_queues = dev->data->nb_tx_queues;
 606         int i;
 607
 608         for (i = 0; i < nb_queues; i++)
 609                 ena_tx_queue_release(queues[i]);
 610 }
 611
 612 static void ena_rx_queue_release(void *queue)
 613 {
 614         struct ena_ring *ring = (struct ena_ring *)queue;
 615         struct ena_adapter *adapter = ring->adapter;
 616         int ena_qid;
 617
 618         ena_assert_msg(ring->configured,
 619                        "API violation - releasing not configured queue");
 620         ena_assert_msg(ring->adapter->state != ENA_ADAPTER_STATE_RUNNING,
 621                        "API violation");
 622
 623         /* Destroy HW queue */
 624         ena_qid = ENA_IO_RXQ_IDX(ring->id);
 625         ena_com_destroy_io_queue(&adapter->ena_dev, ena_qid);
 626
 627         /* Free all bufs */
 628         ena_rx_queue_release_bufs(ring);
 629
 630         /* Free ring resources */
 631         if (ring->rx_buffer_info)
 632                 rte_free(ring->rx_buffer_info);
 633         ring->rx_buffer_info = NULL;
 634
 635         ring->configured = 0;
 636
 637         RTE_LOG(NOTICE, PMD, "RX Queue %d:%d released\n",
 638                 ring->port_id, ring->id);
 639 }
 640
 641 static void ena_tx_queue_release(void *queue)
 642 {
 643         struct ena_ring *ring = (struct ena_ring *)queue;
 644         struct ena_adapter *adapter = ring->adapter;
 645         int ena_qid;
 646
 647         ena_assert_msg(ring->configured,
 648                        "API violation. Releasing not configured queue");
 649         ena_assert_msg(ring->adapter->state != ENA_ADAPTER_STATE_RUNNING,
 650                        "API violation");
 651
 652         /* Destroy HW queue */
 653         ena_qid = ENA_IO_TXQ_IDX(ring->id);
 654         ena_com_destroy_io_queue(&adapter->ena_dev, ena_qid);
 655
 656         /* Free all bufs */
 657         ena_tx_queue_release_bufs(ring);
 658
 659         /* Free ring resources */
 660         if (ring->tx_buffer_info)
 661                 rte_free(ring->tx_buffer_info);
 662
 663         if (ring->empty_tx_reqs)
 664                 rte_free(ring->empty_tx_reqs);
 665
 666         ring->empty_tx_reqs = NULL;
 667         ring->tx_buffer_info = NULL;
 668
 669         ring->configured = 0;
 670
 671         RTE_LOG(NOTICE, PMD, "TX Queue %d:%d released\n",
 672                 ring->port_id, ring->id);
 673 }
 674
 675 static void ena_rx_queue_release_bufs(struct ena_ring *ring)
 676 {
 677         unsigned int ring_mask = ring->ring_size - 1;
 678
 679         while (ring->next_to_clean != ring->next_to_use) {
 680                 struct rte_mbuf *m =
 681                         ring->rx_buffer_info[ring->next_to_clean & ring_mask];
 682
 683                 if (m)
 684                         rte_mbuf_raw_free(m);
 685
 686                 ring->next_to_clean++;
 687         }
 688 }
 689
 690 static void ena_tx_queue_release_bufs(struct ena_ring *ring)
 691 {
 692         unsigned int ring_mask = ring->ring_size - 1;
 693
 694         while (ring->next_to_clean != ring->next_to_use) {
 695                 struct ena_tx_buffer *tx_buf =
 696                         &ring->tx_buffer_info[ring->next_to_clean & ring_mask];
 697
 698                 if (tx_buf->mbuf)
 699                         rte_pktmbuf_free(tx_buf->mbuf);
 700
 701                 ring->next_to_clean++;
 702         }
 703 }
 704
 705 static int ena_link_update(struct rte_eth_dev *dev,
 706                            __rte_unused int wait_to_complete)
 707 {
 708         struct rte_eth_link *link = &dev->data->dev_link;
 709
 710         link->link_status = 1;
 711         link->link_speed = ETH_SPEED_NUM_10G;
 712         link->link_duplex = ETH_LINK_FULL_DUPLEX;
 713
 714         return 0;
 715 }
 716
 717 static int ena_queue_restart_all(struct rte_eth_dev *dev,
 718                                  enum ena_ring_type ring_type)
 719 {
 720         struct ena_adapter *adapter =
 721                 (struct ena_adapter *)(dev->data->dev_private);
 722         struct ena_ring *queues = NULL;
 723         int i = 0;
 724         int rc = 0;
 725
 726         queues = (ring_type == ENA_RING_TYPE_RX) ?
 727                 adapter->rx_ring : adapter->tx_ring;
 728
 729         for (i = 0; i < adapter->num_queues; i++) {
 730                 if (queues[i].configured) {
 731                         if (ring_type == ENA_RING_TYPE_RX) {
 732                                 ena_assert_msg(
 733                                         dev->data->rx_queues[i] == &queues[i],
 734                                         "Inconsistent state of rx queues\n");
 735                         } else {
 736                                 ena_assert_msg(
 737                                         dev->data->tx_queues[i] == &queues[i],
 738                                         "Inconsistent state of tx queues\n");
 739                         }
 740
 741                         rc = ena_queue_restart(&queues[i]);
 742
 743                         if (rc) {
 744                                 PMD_INIT_LOG(ERR,
 745                                              "failed to restart queue %d type(%d)",
 746                                              i, ring_type);
 747                                 return -1;
 748                         }
 749                 }
 750         }
 751
 752         return 0;
 753 }
 754
 755 static uint32_t ena_get_mtu_conf(struct ena_adapter *adapter)
 756 {
 757         uint32_t max_frame_len = adapter->max_mtu;
 758
 759         if (adapter->rte_eth_dev_data->dev_conf.rxmode.jumbo_frame == 1)
 760                 max_frame_len =
 761                         adapter->rte_eth_dev_data->dev_conf.rxmode.max_rx_pkt_len;
 762
 763         return max_frame_len;
 764 }
 765
 766 static int ena_check_valid_conf(struct ena_adapter *adapter)
 767 {
 768         uint32_t max_frame_len = ena_get_mtu_conf(adapter);
 769
 770         if (max_frame_len > adapter->max_mtu) {
 771                 PMD_INIT_LOG(ERR, "Unsupported MTU of %d", max_frame_len);
 772                 return -1;
 773         }
 774
 775         return 0;
 776 }
 777
 778 static int
 779 ena_calc_queue_size(struct ena_com_dev *ena_dev,
 780                     struct ena_com_dev_get_features_ctx *get_feat_ctx)
 781 {
 782         uint32_t queue_size = ENA_DEFAULT_RING_SIZE;
 783
 784         queue_size = RTE_MIN(queue_size,
 785                              get_feat_ctx->max_queues.max_cq_depth);
 786         queue_size = RTE_MIN(queue_size,
 787                              get_feat_ctx->max_queues.max_sq_depth);
 788
 789         if (ena_dev->tx_mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_DEV)
 790                 queue_size = RTE_MIN(queue_size,
 791                                      get_feat_ctx->max_queues.max_llq_depth);
 792
 793         /* Round down to power of 2 */
 794         if (!rte_is_power_of_2(queue_size))
 795                 queue_size = rte_align32pow2(queue_size >> 1);
 796
 797         if (queue_size == 0) {
 798                 PMD_INIT_LOG(ERR, "Invalid queue size");
 799                 return -EFAULT;
 800         }
 801
 802         return queue_size;
 803 }
 804
 805 static void ena_stats_restart(struct rte_eth_dev *dev)
 806 {
 807         struct ena_adapter *adapter =
 808                 (struct ena_adapter *)(dev->data->dev_private);
 809
 810         rte_atomic64_init(&adapter->drv_stats->ierrors);
 811         rte_atomic64_init(&adapter->drv_stats->oerrors);
 812         rte_atomic64_init(&adapter->drv_stats->rx_nombuf);
 813 }
 814
 815 static void ena_stats_get(struct rte_eth_dev *dev,
 816                           struct rte_eth_stats *stats)
 817 {
 818         struct ena_admin_basic_stats ena_stats;
 819         struct ena_adapter *adapter =
 820                 (struct ena_adapter *)(dev->data->dev_private);
 821         struct ena_com_dev *ena_dev = &adapter->ena_dev;
 822         int rc;
 823
 824         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
 825                 return;
 826
 827         memset(&ena_stats, 0, sizeof(ena_stats));
 828         rc = ena_com_get_dev_basic_stats(ena_dev, &ena_stats);
 829         if (unlikely(rc)) {
 830                 RTE_LOG(ERR, PMD, "Could not retrieve statistics from ENA");
 831                 return;
 832         }
 833
 834         /* Set of basic statistics from ENA */
 835         stats->ipackets = __MERGE_64B_H_L(ena_stats.rx_pkts_high,
 836                                           ena_stats.rx_pkts_low);
 837         stats->opackets = __MERGE_64B_H_L(ena_stats.tx_pkts_high,
 838                                           ena_stats.tx_pkts_low);
 839         stats->ibytes = __MERGE_64B_H_L(ena_stats.rx_bytes_high,
 840                                         ena_stats.rx_bytes_low);
 841         stats->obytes = __MERGE_64B_H_L(ena_stats.tx_bytes_high,
 842                                         ena_stats.tx_bytes_low);
 843         stats->imissed = __MERGE_64B_H_L(ena_stats.rx_drops_high,
 844                                          ena_stats.rx_drops_low);
 845
 846         /* Driver related stats */
 847         stats->ierrors = rte_atomic64_read(&adapter->drv_stats->ierrors);
 848         stats->oerrors = rte_atomic64_read(&adapter->drv_stats->oerrors);
 849         stats->rx_nombuf = rte_atomic64_read(&adapter->drv_stats->rx_nombuf);
 850 }
 851
 852 static int ena_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
 853 {
 854         struct ena_adapter *adapter;
 855         struct ena_com_dev *ena_dev;
 856         int rc = 0;
 857
 858         ena_assert_msg(dev->data != NULL, "Uninitialized device");
 859         ena_assert_msg(dev->data->dev_private != NULL, "Uninitialized device");
 860         adapter = (struct ena_adapter *)(dev->data->dev_private);
 861
 862         ena_dev = &adapter->ena_dev;
 863         ena_assert_msg(ena_dev != NULL, "Uninitialized device");
 864
 865         if (mtu > ena_get_mtu_conf(adapter)) {
 866                 RTE_LOG(ERR, PMD,
 867                         "Given MTU (%d) exceeds maximum MTU supported (%d)\n",
 868                         mtu, ena_get_mtu_conf(adapter));
 869                 rc = -EINVAL;
 870                 goto err;
 871         }
 872
 873         rc = ena_com_set_dev_mtu(ena_dev, mtu);
 874         if (rc)
 875                 RTE_LOG(ERR, PMD, "Could not set MTU: %d\n", mtu);
 876         else
 877                 RTE_LOG(NOTICE, PMD, "Set MTU: %d\n", mtu);
 878
 879 err:
 880         return rc;
 881 }
 882
 883 static int ena_start(struct rte_eth_dev *dev)
 884 {
 885         struct ena_adapter *adapter =
 886                 (struct ena_adapter *)(dev->data->dev_private);
 887         int rc = 0;
 888
 889         if (!(adapter->state == ENA_ADAPTER_STATE_CONFIG ||
 890               adapter->state == ENA_ADAPTER_STATE_STOPPED)) {
 891                 PMD_INIT_LOG(ERR, "API violation");
 892                 return -1;
 893         }
 894
 895         rc = ena_check_valid_conf(adapter);
 896         if (rc)
 897                 return rc;
 898
 899         rc = ena_queue_restart_all(dev, ENA_RING_TYPE_RX);
 900         if (rc)
 901                 return rc;
 902
 903         rc = ena_queue_restart_all(dev, ENA_RING_TYPE_TX);
 904         if (rc)
 905                 return rc;
 906
 907         if (adapter->rte_dev->data->dev_conf.rxmode.mq_mode &
 908             ETH_MQ_RX_RSS_FLAG) {
 909                 rc = ena_rss_init_default(adapter);
 910                 if (rc)
 911                         return rc;
 912         }
 913
 914         ena_stats_restart(dev);
 915
 916         adapter->state = ENA_ADAPTER_STATE_RUNNING;
 917
 918         return 0;
 919 }
 920
 921 static int ena_queue_restart(struct ena_ring *ring)
 922 {
 923         int rc, bufs_num;
 924
 925         ena_assert_msg(ring->configured == 1,
 926                        "Trying to restart unconfigured queue\n");
 927
 928         ring->next_to_clean = 0;
 929         ring->next_to_use = 0;
 930
 931         if (ring->type == ENA_RING_TYPE_TX)
 932                 return 0;
 933
 934         bufs_num = ring->ring_size - 1;
 935         rc = ena_populate_rx_queue(ring, bufs_num);
 936         if (rc != bufs_num) {
 937                 PMD_INIT_LOG(ERR, "Failed to populate rx ring !");
 938                 return (-1);
 939         }
 940
 941         return 0;
 942 }
 943
 944 static int ena_tx_queue_setup(struct rte_eth_dev *dev,
 945                               uint16_t queue_idx,
 946                               uint16_t nb_desc,
 947                               __rte_unused unsigned int socket_id,
 948                               __rte_unused const struct rte_eth_txconf *tx_conf)
 949 {
 950         struct ena_com_create_io_ctx ctx =
 951                 /* policy set to _HOST just to satisfy icc compiler */
 952                 { ENA_ADMIN_PLACEMENT_POLICY_HOST,
 953                   ENA_COM_IO_QUEUE_DIRECTION_TX, 0, 0, 0, 0 };
 954         struct ena_ring *txq = NULL;
 955         struct ena_adapter *adapter =
 956                 (struct ena_adapter *)(dev->data->dev_private);
 957         unsigned int i;
 958         int ena_qid;
 959         int rc;
 960         struct ena_com_dev *ena_dev = &adapter->ena_dev;
 961
 962         txq = &adapter->tx_ring[queue_idx];
 963
 964         if (txq->configured) {
 965                 RTE_LOG(CRIT, PMD,
 966                         "API violation. Queue %d is already configured\n",
 967                         queue_idx);
 968                 return -1;
 969         }
 970
 971         if (!rte_is_power_of_2(nb_desc)) {
 972                 RTE_LOG(ERR, PMD,
 973                         "Unsupported size of RX queue: %d is not a power of 2.",
 974                         nb_desc);
 975                 return -EINVAL;
 976         }
 977
 978         if (nb_desc > adapter->tx_ring_size) {
 979                 RTE_LOG(ERR, PMD,
 980                         "Unsupported size of TX queue (max size: %d)\n",
 981                         adapter->tx_ring_size);
 982                 return -EINVAL;
 983         }
 984
 985         ena_qid = ENA_IO_TXQ_IDX(queue_idx);
 986
 987         ctx.direction = ENA_COM_IO_QUEUE_DIRECTION_TX;
 988         ctx.qid = ena_qid;
 989         ctx.msix_vector = -1; /* admin interrupts not used */
 990         ctx.mem_queue_type = ena_dev->tx_mem_queue_type;
 991         ctx.queue_size = adapter->tx_ring_size;
 992         ctx.numa_node = ena_cpu_to_node(queue_idx);
 993
 994         rc = ena_com_create_io_queue(ena_dev, &ctx);
 995         if (rc) {
 996                 RTE_LOG(ERR, PMD,
 997                         "failed to create io TX queue #%d (qid:%d) rc: %d\n",
 998                         queue_idx, ena_qid, rc);
 999         }
1000         txq->ena_com_io_cq = &ena_dev->io_cq_queues[ena_qid];
1001         txq->ena_com_io_sq = &ena_dev->io_sq_queues[ena_qid];
1002
1003         rc = ena_com_get_io_handlers(ena_dev, ena_qid,
1004                                      &txq->ena_com_io_sq,
1005                                      &txq->ena_com_io_cq);
1006         if (rc) {
1007                 RTE_LOG(ERR, PMD,
1008                         "Failed to get TX queue handlers. TX queue num %d rc: %d\n",
1009                         queue_idx, rc);
1010                 ena_com_destroy_io_queue(ena_dev, ena_qid);
1011                 goto err;
1012         }
1013
1014         txq->port_id = dev->data->port_id;
1015         txq->next_to_clean = 0;
1016         txq->next_to_use = 0;
1017         txq->ring_size = nb_desc;
1018
1019         txq->tx_buffer_info = rte_zmalloc("txq->tx_buffer_info",
1020                                           sizeof(struct ena_tx_buffer) *
1021                                           txq->ring_size,
1022                                           RTE_CACHE_LINE_SIZE);
1023         if (!txq->tx_buffer_info) {
1024                 RTE_LOG(ERR, PMD, "failed to alloc mem for tx buffer info\n");
1025                 return -ENOMEM;
1026         }
1027
1028         txq->empty_tx_reqs = rte_zmalloc("txq->empty_tx_reqs",
1029                                          sizeof(u16) * txq->ring_size,
1030                                          RTE_CACHE_LINE_SIZE);
1031         if (!txq->empty_tx_reqs) {
1032                 RTE_LOG(ERR, PMD, "failed to alloc mem for tx reqs\n");
1033                 rte_free(txq->tx_buffer_info);
1034                 return -ENOMEM;
1035         }
1036         for (i = 0; i < txq->ring_size; i++)
1037                 txq->empty_tx_reqs[i] = i;
1038
1039         /* Store pointer to this queue in upper layer */
1040         txq->configured = 1;
1041         dev->data->tx_queues[queue_idx] = txq;
1042 err:
1043         return rc;
1044 }
1045
1046 static int ena_rx_queue_setup(struct rte_eth_dev *dev,
1047                               uint16_t queue_idx,
1048                               uint16_t nb_desc,
1049                               __rte_unused unsigned int socket_id,
1050                               __rte_unused const struct rte_eth_rxconf *rx_conf,
1051                               struct rte_mempool *mp)
1052 {
1053         struct ena_com_create_io_ctx ctx =
1054                 /* policy set to _HOST just to satisfy icc compiler */
1055                 { ENA_ADMIN_PLACEMENT_POLICY_HOST,
1056                   ENA_COM_IO_QUEUE_DIRECTION_RX, 0, 0, 0, 0 };
1057         struct ena_adapter *adapter =
1058                 (struct ena_adapter *)(dev->data->dev_private);
1059         struct ena_ring *rxq = NULL;
1060         uint16_t ena_qid = 0;
1061         int rc = 0;
1062         struct ena_com_dev *ena_dev = &adapter->ena_dev;
1063
1064         rxq = &adapter->rx_ring[queue_idx];
1065         if (rxq->configured) {
1066                 RTE_LOG(CRIT, PMD,
1067                         "API violation. Queue %d is already configured\n",
1068                         queue_idx);
1069                 return -1;
1070         }
1071
1072         if (!rte_is_power_of_2(nb_desc)) {
1073                 RTE_LOG(ERR, PMD,
1074                         "Unsupported size of TX queue: %d is not a power of 2.",
1075                         nb_desc);
1076                 return -EINVAL;
1077         }
1078
1079         if (nb_desc > adapter->rx_ring_size) {
1080                 RTE_LOG(ERR, PMD,
1081                         "Unsupported size of RX queue (max size: %d)\n",
1082                         adapter->rx_ring_size);
1083                 return -EINVAL;
1084         }
1085
1086         ena_qid = ENA_IO_RXQ_IDX(queue_idx);
1087
1088         ctx.qid = ena_qid;
1089         ctx.direction = ENA_COM_IO_QUEUE_DIRECTION_RX;
1090         ctx.mem_queue_type = ENA_ADMIN_PLACEMENT_POLICY_HOST;
1091         ctx.msix_vector = -1; /* admin interrupts not used */
1092         ctx.queue_size = adapter->rx_ring_size;
1093         ctx.numa_node = ena_cpu_to_node(queue_idx);
1094
1095         rc = ena_com_create_io_queue(ena_dev, &ctx);
1096         if (rc)
1097                 RTE_LOG(ERR, PMD, "failed to create io RX queue #%d rc: %d\n",
1098                         queue_idx, rc);
1099
1100         rxq->ena_com_io_cq = &ena_dev->io_cq_queues[ena_qid];
1101         rxq->ena_com_io_sq = &ena_dev->io_sq_queues[ena_qid];
1102
1103         rc = ena_com_get_io_handlers(ena_dev, ena_qid,
1104                                      &rxq->ena_com_io_sq,
1105                                      &rxq->ena_com_io_cq);
1106         if (rc) {
1107                 RTE_LOG(ERR, PMD,
1108                         "Failed to get RX queue handlers. RX queue num %d rc: %d\n",
1109                         queue_idx, rc);
1110                 ena_com_destroy_io_queue(ena_dev, ena_qid);
1111         }
1112
1113         rxq->port_id = dev->data->port_id;
1114         rxq->next_to_clean = 0;
1115         rxq->next_to_use = 0;
1116         rxq->ring_size = nb_desc;
1117         rxq->mb_pool = mp;
1118
1119         rxq->rx_buffer_info = rte_zmalloc("rxq->buffer_info",
1120                                           sizeof(struct rte_mbuf *) * nb_desc,
1121                                           RTE_CACHE_LINE_SIZE);
1122         if (!rxq->rx_buffer_info) {
1123                 RTE_LOG(ERR, PMD, "failed to alloc mem for rx buffer info\n");
1124                 return -ENOMEM;
1125         }
1126
1127         /* Store pointer to this queue in upper layer */
1128         rxq->configured = 1;
1129         dev->data->rx_queues[queue_idx] = rxq;
1130
1131         return rc;
1132 }
1133
1134 static int ena_populate_rx_queue(struct ena_ring *rxq, unsigned int count)
1135 {
1136         unsigned int i;
1137         int rc;
1138         uint16_t ring_size = rxq->ring_size;
1139         uint16_t ring_mask = ring_size - 1;
1140         uint16_t next_to_use = rxq->next_to_use;
1141         uint16_t in_use;
1142         struct rte_mbuf **mbufs = &rxq->rx_buffer_info[0];
1143
1144         if (unlikely(!count))
1145                 return 0;
1146
1147         in_use = rxq->next_to_use - rxq->next_to_clean;
1148         ena_assert_msg(((in_use + count) < ring_size), "bad ring state");
1149
1150         count = RTE_MIN(count,
1151                         (uint16_t)(ring_size - (next_to_use & ring_mask)));
1152
1153         /* get resources for incoming packets */
1154         rc = rte_mempool_get_bulk(rxq->mb_pool,
1155                                   (void **)(&mbufs[next_to_use & ring_mask]),
1156                                   count);
1157         if (unlikely(rc < 0)) {
1158                 rte_atomic64_inc(&rxq->adapter->drv_stats->rx_nombuf);
1159                 PMD_RX_LOG(DEBUG, "there are no enough free buffers");
1160                 return 0;
1161         }
1162
1163         for (i = 0; i < count; i++) {
1164                 uint16_t next_to_use_masked = next_to_use & ring_mask;
1165                 struct rte_mbuf *mbuf = mbufs[next_to_use_masked];
1166                 struct ena_com_buf ebuf;
1167
1168                 rte_prefetch0(mbufs[((next_to_use + 4) & ring_mask)]);
1169                 /* prepare physical address for DMA transaction */
1170                 ebuf.paddr = mbuf->buf_physaddr + RTE_PKTMBUF_HEADROOM;
1171                 ebuf.len = mbuf->buf_len - RTE_PKTMBUF_HEADROOM;
1172                 /* pass resource to device */
1173                 rc = ena_com_add_single_rx_desc(rxq->ena_com_io_sq,
1174                                                 &ebuf, next_to_use_masked);
1175                 if (unlikely(rc)) {
1176                         rte_mempool_put_bulk(rxq->mb_pool, (void **)(&mbuf),
1177                                              count - i);
1178                         RTE_LOG(WARNING, PMD, "failed adding rx desc\n");
1179                         break;
1180                 }
1181                 next_to_use++;
1182         }
1183
1184         /* When we submitted free recources to device... */
1185         if (i > 0) {
1186                 /* ...let HW know that it can fill buffers with data */
1187                 rte_wmb();
1188                 ena_com_write_sq_doorbell(rxq->ena_com_io_sq);
1189
1190                 rxq->next_to_use = next_to_use;
1191         }
1192
1193         return i;
1194 }
1195
1196 static int ena_device_init(struct ena_com_dev *ena_dev,
1197                            struct ena_com_dev_get_features_ctx *get_feat_ctx)
1198 {
1199         int rc;
1200         bool readless_supported;
1201
1202         /* Initialize mmio registers */
1203         rc = ena_com_mmio_reg_read_request_init(ena_dev);
1204         if (rc) {
1205                 RTE_LOG(ERR, PMD, "failed to init mmio read less\n");
1206                 return rc;
1207         }
1208
1209         /* The PCIe configuration space revision id indicate if mmio reg
1210          * read is disabled.
1211          */
1212         readless_supported =
1213                 !(((struct rte_pci_device *)ena_dev->dmadev)->id.class_id
1214                                & ENA_MMIO_DISABLE_REG_READ);
1215         ena_com_set_mmio_read_mode(ena_dev, readless_supported);
1216
1217         /* reset device */
1218         rc = ena_com_dev_reset(ena_dev);
1219         if (rc) {
1220                 RTE_LOG(ERR, PMD, "cannot reset device\n");
1221                 goto err_mmio_read_less;
1222         }
1223
1224         /* check FW version */
1225         rc = ena_com_validate_version(ena_dev);
1226         if (rc) {
1227                 RTE_LOG(ERR, PMD, "device version is too low\n");
1228                 goto err_mmio_read_less;
1229         }
1230
1231         ena_dev->dma_addr_bits = ena_com_get_dma_width(ena_dev);
1232
1233         /* ENA device administration layer init */
1234         rc = ena_com_admin_init(ena_dev, NULL, true);
1235         if (rc) {
1236                 RTE_LOG(ERR, PMD,
1237                         "cannot initialize ena admin queue with device\n");
1238                 goto err_mmio_read_less;
1239         }
1240
1241         /* To enable the msix interrupts the driver needs to know the number
1242          * of queues. So the driver uses polling mode to retrieve this
1243          * information.
1244          */
1245         ena_com_set_admin_polling_mode(ena_dev, true);
1246
1247         ena_config_host_info(ena_dev);
1248
1249         /* Get Device Attributes and features */
1250         rc = ena_com_get_dev_attr_feat(ena_dev, get_feat_ctx);
1251         if (rc) {
1252                 RTE_LOG(ERR, PMD,
1253                         "cannot get attribute for ena device rc= %d\n", rc);
1254                 goto err_admin_init;
1255         }
1256
1257         return 0;
1258
1259 err_admin_init:
1260         ena_com_admin_destroy(ena_dev);
1261
1262 err_mmio_read_less:
1263         ena_com_mmio_reg_read_request_destroy(ena_dev);
1264
1265         return rc;
1266 }
1267
1268 static int eth_ena_dev_init(struct rte_eth_dev *eth_dev)
1269 {
1270         struct rte_pci_device *pci_dev;
1271         struct ena_adapter *adapter =
1272                 (struct ena_adapter *)(eth_dev->data->dev_private);
1273         struct ena_com_dev *ena_dev = &adapter->ena_dev;
1274         struct ena_com_dev_get_features_ctx get_feat_ctx;
1275         int queue_size, rc;
1276
1277         static int adapters_found;
1278
1279         memset(adapter, 0, sizeof(struct ena_adapter));
1280         ena_dev = &adapter->ena_dev;
1281
1282         eth_dev->dev_ops = &ena_dev_ops;
1283         eth_dev->rx_pkt_burst = &eth_ena_recv_pkts;
1284         eth_dev->tx_pkt_burst = &eth_ena_xmit_pkts;
1285         eth_dev->tx_pkt_prepare = &eth_ena_prep_pkts;
1286         adapter->rte_eth_dev_data = eth_dev->data;
1287         adapter->rte_dev = eth_dev;
1288
1289         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1290                 return 0;
1291
1292         pci_dev = RTE_DEV_TO_PCI(eth_dev->device);
1293         adapter->pdev = pci_dev;
1294
1295         PMD_INIT_LOG(INFO, "Initializing %x:%x:%x.%d",
1296                      pci_dev->addr.domain,
1297                      pci_dev->addr.bus,
1298                      pci_dev->addr.devid,
1299                      pci_dev->addr.function);
1300
1301         adapter->regs = pci_dev->mem_resource[ENA_REGS_BAR].addr;
1302         adapter->dev_mem_base = pci_dev->mem_resource[ENA_MEM_BAR].addr;
1303
1304         /* Present ENA_MEM_BAR indicates available LLQ mode.
1305          * Use corresponding policy
1306          */
1307         if (adapter->dev_mem_base)
1308                 ena_dev->tx_mem_queue_type = ENA_ADMIN_PLACEMENT_POLICY_DEV;
1309         else if (adapter->regs)
1310                 ena_dev->tx_mem_queue_type = ENA_ADMIN_PLACEMENT_POLICY_HOST;
1311         else
1312                 PMD_INIT_LOG(CRIT, "Failed to access registers BAR(%d)",
1313                              ENA_REGS_BAR);
1314
1315         ena_dev->reg_bar = adapter->regs;
1316         ena_dev->dmadev = adapter->pdev;
1317
1318         adapter->id_number = adapters_found;
1319
1320         snprintf(adapter->name, ENA_NAME_MAX_LEN, "ena_%d",
1321                  adapter->id_number);
1322
1323         /* device specific initialization routine */
1324         rc = ena_device_init(ena_dev, &get_feat_ctx);
1325         if (rc) {
1326                 PMD_INIT_LOG(CRIT, "Failed to init ENA device");
1327                 return -1;
1328         }
1329
1330         if (ena_dev->tx_mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_DEV) {
1331                 if (get_feat_ctx.max_queues.max_llq_num == 0) {
1332                         PMD_INIT_LOG(ERR,
1333                                      "Trying to use LLQ but llq_num is 0.\n"
1334                                      "Fall back into regular queues.");
1335                         ena_dev->tx_mem_queue_type =
1336                                 ENA_ADMIN_PLACEMENT_POLICY_HOST;
1337                         adapter->num_queues =
1338                                 get_feat_ctx.max_queues.max_sq_num;
1339                 } else {
1340                         adapter->num_queues =
1341                                 get_feat_ctx.max_queues.max_llq_num;
1342                 }
1343         } else {
1344                 adapter->num_queues = get_feat_ctx.max_queues.max_sq_num;
1345         }
1346
1347         queue_size = ena_calc_queue_size(ena_dev, &get_feat_ctx);
1348         if ((queue_size <= 0) || (adapter->num_queues <= 0))
1349                 return -EFAULT;
1350
1351         adapter->tx_ring_size = queue_size;
1352         adapter->rx_ring_size = queue_size;
1353
1354         /* prepare ring structures */
1355         ena_init_rings(adapter);
1356
1357         ena_config_debug_area(adapter);
1358
1359         /* Set max MTU for this device */
1360         adapter->max_mtu = get_feat_ctx.dev_attr.max_mtu;
1361
1362         /* set device support for TSO */
1363         adapter->tso4_supported = get_feat_ctx.offload.tx &
1364                                   ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_IPV4_MASK;
1365
1366         /* Copy MAC address and point DPDK to it */
1367         eth_dev->data->mac_addrs = (struct ether_addr *)adapter->mac_addr;
1368         ether_addr_copy((struct ether_addr *)get_feat_ctx.dev_attr.mac_addr,
1369                         (struct ether_addr *)adapter->mac_addr);
1370
1371         adapter->drv_stats = rte_zmalloc("adapter stats",
1372                                          sizeof(*adapter->drv_stats),
1373                                          RTE_CACHE_LINE_SIZE);
1374         if (!adapter->drv_stats) {
1375                 RTE_LOG(ERR, PMD, "failed to alloc mem for adapter stats\n");
1376                 return -ENOMEM;
1377         }
1378
1379         adapters_found++;
1380         adapter->state = ENA_ADAPTER_STATE_INIT;
1381
1382         return 0;
1383 }
1384
1385 static int ena_dev_configure(struct rte_eth_dev *dev)
1386 {
1387         struct ena_adapter *adapter =
1388                 (struct ena_adapter *)(dev->data->dev_private);
1389
1390         if (!(adapter->state == ENA_ADAPTER_STATE_INIT ||
1391               adapter->state == ENA_ADAPTER_STATE_STOPPED)) {
1392                 PMD_INIT_LOG(ERR, "Illegal adapter state: %d",
1393                              adapter->state);
1394                 return -1;
1395         }
1396
1397         switch (adapter->state) {
1398         case ENA_ADAPTER_STATE_INIT:
1399         case ENA_ADAPTER_STATE_STOPPED:
1400                 adapter->state = ENA_ADAPTER_STATE_CONFIG;
1401                 break;
1402         case ENA_ADAPTER_STATE_CONFIG:
1403                 RTE_LOG(WARNING, PMD,
1404                         "Ivalid driver state while trying to configure device\n");
1405                 break;
1406         default:
1407                 break;
1408         }
1409
1410         return 0;
1411 }
1412
1413 static void ena_init_rings(struct ena_adapter *adapter)
1414 {
1415         int i;
1416
1417         for (i = 0; i < adapter->num_queues; i++) {
1418                 struct ena_ring *ring = &adapter->tx_ring[i];
1419
1420                 ring->configured = 0;
1421                 ring->type = ENA_RING_TYPE_TX;
1422                 ring->adapter = adapter;
1423                 ring->id = i;
1424                 ring->tx_mem_queue_type = adapter->ena_dev.tx_mem_queue_type;
1425                 ring->tx_max_header_size = adapter->ena_dev.tx_max_header_size;
1426         }
1427
1428         for (i = 0; i < adapter->num_queues; i++) {
1429                 struct ena_ring *ring = &adapter->rx_ring[i];
1430
1431                 ring->configured = 0;
1432                 ring->type = ENA_RING_TYPE_RX;
1433                 ring->adapter = adapter;
1434                 ring->id = i;
1435         }
1436 }
1437
1438 static void ena_infos_get(struct rte_eth_dev *dev,
1439                           struct rte_eth_dev_info *dev_info)
1440 {
1441         struct ena_adapter *adapter;
1442         struct ena_com_dev *ena_dev;
1443         struct ena_com_dev_get_features_ctx feat;
1444         uint32_t rx_feat = 0, tx_feat = 0;
1445         int rc = 0;
1446
1447         ena_assert_msg(dev->data != NULL, "Uninitialized device");
1448         ena_assert_msg(dev->data->dev_private != NULL, "Uninitialized device");
1449         adapter = (struct ena_adapter *)(dev->data->dev_private);
1450
1451         ena_dev = &adapter->ena_dev;
1452         ena_assert_msg(ena_dev != NULL, "Uninitialized device");
1453
1454         dev_info->pci_dev = RTE_DEV_TO_PCI(dev->device);
1455
1456         dev_info->speed_capa =
1457                         ETH_LINK_SPEED_1G   |
1458                         ETH_LINK_SPEED_2_5G |
1459                         ETH_LINK_SPEED_5G   |
1460                         ETH_LINK_SPEED_10G  |
1461                         ETH_LINK_SPEED_25G  |
1462                         ETH_LINK_SPEED_40G  |
1463                         ETH_LINK_SPEED_50G  |
1464                         ETH_LINK_SPEED_100G;
1465
1466         /* Get supported features from HW */
1467         rc = ena_com_get_dev_attr_feat(ena_dev, &feat);
1468         if (unlikely(rc)) {
1469                 RTE_LOG(ERR, PMD,
1470                         "Cannot get attribute for ena device rc= %d\n", rc);
1471                 return;
1472         }
1473
1474         /* Set Tx & Rx features available for device */
1475         if (feat.offload.tx & ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_IPV4_MASK)
1476                 tx_feat |= DEV_TX_OFFLOAD_TCP_TSO;
1477
1478         if (feat.offload.tx &
1479             ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV4_CSUM_PART_MASK)
1480                 tx_feat |= DEV_TX_OFFLOAD_IPV4_CKSUM |
1481                         DEV_TX_OFFLOAD_UDP_CKSUM |
1482                         DEV_TX_OFFLOAD_TCP_CKSUM;
1483
1484         if (feat.offload.rx_supported &
1485             ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L4_IPV4_CSUM_MASK)
1486                 rx_feat |= DEV_RX_OFFLOAD_IPV4_CKSUM |
1487                         DEV_RX_OFFLOAD_UDP_CKSUM  |
1488                         DEV_RX_OFFLOAD_TCP_CKSUM;
1489
1490         /* Inform framework about available features */
1491         dev_info->rx_offload_capa = rx_feat;
1492         dev_info->tx_offload_capa = tx_feat;
1493
1494         dev_info->min_rx_bufsize = ENA_MIN_FRAME_LEN;
1495         dev_info->max_rx_pktlen  = adapter->max_mtu;
1496         dev_info->max_mac_addrs = 1;
1497
1498         dev_info->max_rx_queues = adapter->num_queues;
1499         dev_info->max_tx_queues = adapter->num_queues;
1500         dev_info->reta_size = ENA_RX_RSS_TABLE_SIZE;
1501 }
1502
1503 static uint16_t eth_ena_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,
1504                                   uint16_t nb_pkts)
1505 {
1506         struct ena_ring *rx_ring = (struct ena_ring *)(rx_queue);
1507         unsigned int ring_size = rx_ring->ring_size;
1508         unsigned int ring_mask = ring_size - 1;
1509         uint16_t next_to_clean = rx_ring->next_to_clean;
1510         uint16_t desc_in_use = 0;
1511         unsigned int recv_idx = 0;
1512         struct rte_mbuf *mbuf = NULL;
1513         struct rte_mbuf *mbuf_head = NULL;
1514         struct rte_mbuf *mbuf_prev = NULL;
1515         struct rte_mbuf **rx_buff_info = rx_ring->rx_buffer_info;
1516         unsigned int completed;
1517
1518         struct ena_com_rx_ctx ena_rx_ctx;
1519         int rc = 0;
1520
1521         /* Check adapter state */
1522         if (unlikely(rx_ring->adapter->state != ENA_ADAPTER_STATE_RUNNING)) {
1523                 RTE_LOG(ALERT, PMD,
1524                         "Trying to receive pkts while device is NOT running\n");
1525                 return 0;
1526         }
1527
1528         desc_in_use = rx_ring->next_to_use - next_to_clean;
1529         if (unlikely(nb_pkts > desc_in_use))
1530                 nb_pkts = desc_in_use;
1531
1532         for (completed = 0; completed < nb_pkts; completed++) {
1533                 int segments = 0;
1534
1535                 ena_rx_ctx.max_bufs = rx_ring->ring_size;
1536                 ena_rx_ctx.ena_bufs = rx_ring->ena_bufs;
1537                 ena_rx_ctx.descs = 0;
1538                 /* receive packet context */
1539                 rc = ena_com_rx_pkt(rx_ring->ena_com_io_cq,
1540                                     rx_ring->ena_com_io_sq,
1541                                     &ena_rx_ctx);
1542                 if (unlikely(rc)) {
1543                         RTE_LOG(ERR, PMD, "ena_com_rx_pkt error %d\n", rc);
1544                         return 0;
1545                 }
1546
1547                 if (unlikely(ena_rx_ctx.descs == 0))
1548                         break;
1549
1550                 while (segments < ena_rx_ctx.descs) {
1551                         mbuf = rx_buff_info[next_to_clean & ring_mask];
1552                         mbuf->data_len = ena_rx_ctx.ena_bufs[segments].len;
1553                         mbuf->data_off = RTE_PKTMBUF_HEADROOM;
1554                         mbuf->refcnt = 1;
1555                         mbuf->next = NULL;
1556                         if (segments == 0) {
1557                                 mbuf->nb_segs = ena_rx_ctx.descs;
1558                                 mbuf->port = rx_ring->port_id;
1559                                 mbuf->pkt_len = 0;
1560                                 mbuf_head = mbuf;
1561                         } else {
1562                                 /* for multi-segment pkts create mbuf chain */
1563                                 mbuf_prev->next = mbuf;
1564                         }
1565                         mbuf_head->pkt_len += mbuf->data_len;
1566
1567                         mbuf_prev = mbuf;
1568                         segments++;
1569                         next_to_clean++;
1570                 }
1571
1572                 /* fill mbuf attributes if any */
1573                 ena_rx_mbuf_prepare(mbuf_head, &ena_rx_ctx);
1574                 mbuf_head->hash.rss = (uint32_t)rx_ring->id;
1575
1576                 /* pass to DPDK application head mbuf */
1577                 rx_pkts[recv_idx] = mbuf_head;
1578                 recv_idx++;
1579         }
1580
1581         rx_ring->next_to_clean = next_to_clean;
1582
1583         desc_in_use = desc_in_use - completed + 1;
1584         /* Burst refill to save doorbells, memory barriers, const interval */
1585         if (ring_size - desc_in_use > ENA_RING_DESCS_RATIO(ring_size))
1586                 ena_populate_rx_queue(rx_ring, ring_size - desc_in_use);
1587
1588         return recv_idx;
1589 }
1590
1591 static uint16_t
1592 eth_ena_prep_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
1593                 uint16_t nb_pkts)
1594 {
1595         int32_t ret;
1596         uint32_t i;
1597         struct rte_mbuf *m;
1598         struct ena_ring *tx_ring = (struct ena_ring *)(tx_queue);
1599         struct ipv4_hdr *ip_hdr;
1600         uint64_t ol_flags;
1601         uint16_t frag_field;
1602
1603         for (i = 0; i != nb_pkts; i++) {
1604                 m = tx_pkts[i];
1605                 ol_flags = m->ol_flags;
1606
1607                 if (!(ol_flags & PKT_TX_IPV4))
1608                         continue;
1609
1610                 /* If there was not L2 header length specified, assume it is
1611                  * length of the ethernet header.
1612                  */
1613                 if (unlikely(m->l2_len == 0))
1614                         m->l2_len = sizeof(struct ether_hdr);
1615
1616                 ip_hdr = rte_pktmbuf_mtod_offset(m, struct ipv4_hdr *,
1617                                                  m->l2_len);
1618                 frag_field = rte_be_to_cpu_16(ip_hdr->fragment_offset);
1619
1620                 if ((frag_field & IPV4_HDR_DF_FLAG) != 0) {
1621                         m->packet_type |= RTE_PTYPE_L4_NONFRAG;
1622
1623                         /* If IPv4 header has DF flag enabled and TSO support is
1624                          * disabled, partial chcecksum should not be calculated.
1625                          */
1626                         if (!tx_ring->adapter->tso4_supported)
1627                                 continue;
1628                 }
1629
1630                 if ((ol_flags & ENA_TX_OFFLOAD_NOTSUP_MASK) != 0 ||
1631                                 (ol_flags & PKT_TX_L4_MASK) ==
1632                                 PKT_TX_SCTP_CKSUM) {
1633                         rte_errno = -ENOTSUP;
1634                         return i;
1635                 }
1636
1637 #ifdef RTE_LIBRTE_ETHDEV_DEBUG
1638                 ret = rte_validate_tx_offload(m);
1639                 if (ret != 0) {
1640                         rte_errno = ret;
1641                         return i;
1642                 }
1643 #endif
1644
1645                 /* In case we are supposed to TSO and have DF not set (DF=0)
1646                  * hardware must be provided with partial checksum, otherwise
1647                  * it will take care of necessary calculations.
1648                  */
1649
1650                 ret = rte_net_intel_cksum_flags_prepare(m,
1651                         ol_flags & ~PKT_TX_TCP_SEG);
1652                 if (ret != 0) {
1653                         rte_errno = ret;
1654                         return i;
1655                 }
1656         }
1657
1658         return i;
1659 }
1660
1661 static uint16_t eth_ena_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
1662                                   uint16_t nb_pkts)
1663 {
1664         struct ena_ring *tx_ring = (struct ena_ring *)(tx_queue);
1665         uint16_t next_to_use = tx_ring->next_to_use;
1666         uint16_t next_to_clean = tx_ring->next_to_clean;
1667         struct rte_mbuf *mbuf;
1668         unsigned int ring_size = tx_ring->ring_size;
1669         unsigned int ring_mask = ring_size - 1;
1670         struct ena_com_tx_ctx ena_tx_ctx;
1671         struct ena_tx_buffer *tx_info;
1672         struct ena_com_buf *ebuf;
1673         uint16_t rc, req_id, total_tx_descs = 0;
1674         uint16_t sent_idx = 0, empty_tx_reqs;
1675         int nb_hw_desc;
1676
1677         /* Check adapter state */
1678         if (unlikely(tx_ring->adapter->state != ENA_ADAPTER_STATE_RUNNING)) {
1679                 RTE_LOG(ALERT, PMD,
1680                         "Trying to xmit pkts while device is NOT running\n");
1681                 return 0;
1682         }
1683
1684         empty_tx_reqs = ring_size - (next_to_use - next_to_clean);
1685         if (nb_pkts > empty_tx_reqs)
1686                 nb_pkts = empty_tx_reqs;
1687
1688         for (sent_idx = 0; sent_idx < nb_pkts; sent_idx++) {
1689                 mbuf = tx_pkts[sent_idx];
1690
1691                 req_id = tx_ring->empty_tx_reqs[next_to_use & ring_mask];
1692                 tx_info = &tx_ring->tx_buffer_info[req_id];
1693                 tx_info->mbuf = mbuf;
1694                 tx_info->num_of_bufs = 0;
1695                 ebuf = tx_info->bufs;
1696
1697                 /* Prepare TX context */
1698                 memset(&ena_tx_ctx, 0x0, sizeof(struct ena_com_tx_ctx));
1699                 memset(&ena_tx_ctx.ena_meta, 0x0,
1700                        sizeof(struct ena_com_tx_meta));
1701                 ena_tx_ctx.ena_bufs = ebuf;
1702                 ena_tx_ctx.req_id = req_id;
1703                 if (tx_ring->tx_mem_queue_type ==
1704                                 ENA_ADMIN_PLACEMENT_POLICY_DEV) {
1705                         /* prepare the push buffer with
1706                          * virtual address of the data
1707                          */
1708                         ena_tx_ctx.header_len =
1709                                 RTE_MIN(mbuf->data_len,
1710                                         tx_ring->tx_max_header_size);
1711                         ena_tx_ctx.push_header =
1712                                 (void *)((char *)mbuf->buf_addr +
1713                                          mbuf->data_off);
1714                 } /* there's no else as we take advantage of memset zeroing */
1715
1716                 /* Set TX offloads flags, if applicable */
1717                 ena_tx_mbuf_prepare(mbuf, &ena_tx_ctx);
1718
1719                 if (unlikely(mbuf->ol_flags &
1720                              (PKT_RX_L4_CKSUM_BAD | PKT_RX_IP_CKSUM_BAD)))
1721                         rte_atomic64_inc(&tx_ring->adapter->drv_stats->ierrors);
1722
1723                 rte_prefetch0(tx_pkts[(sent_idx + 4) & ring_mask]);
1724
1725                 /* Process first segment taking into
1726                  * consideration pushed header
1727                  */
1728                 if (mbuf->data_len > ena_tx_ctx.header_len) {
1729                         ebuf->paddr = mbuf->buf_physaddr +
1730                                       mbuf->data_off +
1731                                       ena_tx_ctx.header_len;
1732                         ebuf->len = mbuf->data_len - ena_tx_ctx.header_len;
1733                         ebuf++;
1734                         tx_info->num_of_bufs++;
1735                 }
1736
1737                 while ((mbuf = mbuf->next) != NULL) {
1738                         ebuf->paddr = mbuf->buf_physaddr + mbuf->data_off;
1739                         ebuf->len = mbuf->data_len;
1740                         ebuf++;
1741                         tx_info->num_of_bufs++;
1742                 }
1743
1744                 ena_tx_ctx.num_bufs = tx_info->num_of_bufs;
1745
1746                 /* Write data to device */
1747                 rc = ena_com_prepare_tx(tx_ring->ena_com_io_sq,
1748                                         &ena_tx_ctx, &nb_hw_desc);
1749                 if (unlikely(rc))
1750                         break;
1751
1752                 tx_info->tx_descs = nb_hw_desc;
1753
1754                 next_to_use++;
1755         }
1756
1757         /* If there are ready packets to be xmitted... */
1758         if (sent_idx > 0) {
1759                 /* ...let HW do its best :-) */
1760                 rte_wmb();
1761                 ena_com_write_sq_doorbell(tx_ring->ena_com_io_sq);
1762
1763                 tx_ring->next_to_use = next_to_use;
1764         }
1765
1766         /* Clear complete packets  */
1767         while (ena_com_tx_comp_req_id_get(tx_ring->ena_com_io_cq, &req_id) >= 0) {
1768                 /* Get Tx info & store how many descs were processed  */
1769                 tx_info = &tx_ring->tx_buffer_info[req_id];
1770                 total_tx_descs += tx_info->tx_descs;
1771
1772                 /* Free whole mbuf chain  */
1773                 mbuf = tx_info->mbuf;
1774                 rte_pktmbuf_free(mbuf);
1775
1776                 /* Put back descriptor to the ring for reuse */
1777                 tx_ring->empty_tx_reqs[next_to_clean & ring_mask] = req_id;
1778                 next_to_clean++;
1779
1780                 /* If too many descs to clean, leave it for another run */
1781                 if (unlikely(total_tx_descs > ENA_RING_DESCS_RATIO(ring_size)))
1782                         break;
1783         }
1784
1785         if (total_tx_descs > 0) {
1786                 /* acknowledge completion of sent packets */
1787                 ena_com_comp_ack(tx_ring->ena_com_io_sq, total_tx_descs);
1788                 tx_ring->next_to_clean = next_to_clean;
1789         }
1790
1791         return sent_idx;
1792 }
1793
1794 static int eth_ena_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
1795         struct rte_pci_device *pci_dev)
1796 {
1797         return rte_eth_dev_pci_generic_probe(pci_dev,
1798                 sizeof(struct ena_adapter), eth_ena_dev_init);
1799 }
1800
1801 static int eth_ena_pci_remove(struct rte_pci_device *pci_dev)
1802 {
1803         return rte_eth_dev_pci_generic_remove(pci_dev, NULL);
1804 }
1805
1806 static struct rte_pci_driver rte_ena_pmd = {
1807         .id_table = pci_id_ena_map,
1808         .drv_flags = RTE_PCI_DRV_NEED_MAPPING,
1809         .probe = eth_ena_pci_probe,
1810         .remove = eth_ena_pci_remove,
1811 };
1812
1813 RTE_PMD_REGISTER_PCI(net_ena, rte_ena_pmd);
1814 RTE_PMD_REGISTER_PCI_TABLE(net_ena, pci_id_ena_map);
1815 RTE_PMD_REGISTER_KMOD_DEP(net_ena, "* igb_uio | uio_pci_generic | vfio-pci");