drivers/net/ena/ena_ethdev.c

   1 /*-
   2 * BSD LICENSE
   3 *
   4 * Copyright (c) 2015-2016 Amazon.com, Inc. or its affiliates.
   5 * All rights reserved.
   6 *
   7 * Redistribution and use in source and binary forms, with or without
   8 * modification, are permitted provided that the following conditions
   9 * are met:
  10 *
  11 * * Redistributions of source code must retain the above copyright
  12 * notice, this list of conditions and the following disclaimer.
  13 * * Redistributions in binary form must reproduce the above copyright
  14 * notice, this list of conditions and the following disclaimer in
  15 * the documentation and/or other materials provided with the
  16 * distribution.
  17 * * Neither the name of copyright holder nor the names of its
  18 * contributors may be used to endorse or promote products derived
  19 * from this software without specific prior written permission.
  20 *
  21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32 */
  33
  34 #include <rte_ether.h>
  35 #include <rte_ethdev.h>
  36 #include <rte_ethdev_pci.h>
  37 #include <rte_tcp.h>
  38 #include <rte_atomic.h>
  39 #include <rte_dev.h>
  40 #include <rte_errno.h>
  41 #include <rte_version.h>
  42 #include <rte_eal_memconfig.h>
  43 #include <rte_net.h>
  44
  45 #include "ena_ethdev.h"
  46 #include "ena_logs.h"
  47 #include "ena_platform.h"
  48 #include "ena_com.h"
  49 #include "ena_eth_com.h"
  50
  51 #include <ena_common_defs.h>
  52 #include <ena_regs_defs.h>
  53 #include <ena_admin_defs.h>
  54 #include <ena_eth_io_defs.h>
  55
  56 #define DRV_MODULE_VER_MAJOR    1
  57 #define DRV_MODULE_VER_MINOR    0
  58 #define DRV_MODULE_VER_SUBMINOR 0
  59
  60 #define ENA_IO_TXQ_IDX(q)       (2 * (q))
  61 #define ENA_IO_RXQ_IDX(q)       (2 * (q) + 1)
  62 /*reverse version of ENA_IO_RXQ_IDX*/
  63 #define ENA_IO_RXQ_IDX_REV(q)   ((q - 1) / 2)
  64
  65 /* While processing submitted and completed descriptors (rx and tx path
  66  * respectively) in a loop it is desired to:
  67  *  - perform batch submissions while populating sumbissmion queue
  68  *  - avoid blocking transmission of other packets during cleanup phase
  69  * Hence the utilization ratio of 1/8 of a queue size.
  70  */
  71 #define ENA_RING_DESCS_RATIO(ring_size) (ring_size / 8)
  72
  73 #define __MERGE_64B_H_L(h, l) (((uint64_t)h << 32) | l)
  74 #define TEST_BIT(val, bit_shift) (val & (1UL << bit_shift))
  75
  76 #define GET_L4_HDR_LEN(mbuf)                                    \
  77         ((rte_pktmbuf_mtod_offset(mbuf, struct tcp_hdr *,       \
  78                 mbuf->l3_len + mbuf->l2_len)->data_off) >> 4)
  79
  80 #define ENA_RX_RSS_TABLE_LOG_SIZE  7
  81 #define ENA_RX_RSS_TABLE_SIZE   (1 << ENA_RX_RSS_TABLE_LOG_SIZE)
  82 #define ENA_HASH_KEY_SIZE       40
  83 #define ENA_ETH_SS_STATS        0xFF
  84 #define ETH_GSTRING_LEN 32
  85
  86 #define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
  87
  88 enum ethtool_stringset {
  89         ETH_SS_TEST             = 0,
  90         ETH_SS_STATS,
  91 };
  92
  93 struct ena_stats {
  94         char name[ETH_GSTRING_LEN];
  95         int stat_offset;
  96 };
  97
  98 #define ENA_STAT_ENA_COM_ENTRY(stat) { \
  99         .name = #stat, \
 100         .stat_offset = offsetof(struct ena_com_stats_admin, stat) \
 101 }
 102
 103 #define ENA_STAT_ENTRY(stat, stat_type) { \
 104         .name = #stat, \
 105         .stat_offset = offsetof(struct ena_stats_##stat_type, stat) \
 106 }
 107
 108 #define ENA_STAT_RX_ENTRY(stat) \
 109         ENA_STAT_ENTRY(stat, rx)
 110
 111 #define ENA_STAT_TX_ENTRY(stat) \
 112         ENA_STAT_ENTRY(stat, tx)
 113
 114 #define ENA_STAT_GLOBAL_ENTRY(stat) \
 115         ENA_STAT_ENTRY(stat, dev)
 116
 117 static const struct ena_stats ena_stats_global_strings[] = {
 118         ENA_STAT_GLOBAL_ENTRY(tx_timeout),
 119         ENA_STAT_GLOBAL_ENTRY(io_suspend),
 120         ENA_STAT_GLOBAL_ENTRY(io_resume),
 121         ENA_STAT_GLOBAL_ENTRY(wd_expired),
 122         ENA_STAT_GLOBAL_ENTRY(interface_up),
 123         ENA_STAT_GLOBAL_ENTRY(interface_down),
 124         ENA_STAT_GLOBAL_ENTRY(admin_q_pause),
 125 };
 126
 127 static const struct ena_stats ena_stats_tx_strings[] = {
 128         ENA_STAT_TX_ENTRY(cnt),
 129         ENA_STAT_TX_ENTRY(bytes),
 130         ENA_STAT_TX_ENTRY(queue_stop),
 131         ENA_STAT_TX_ENTRY(queue_wakeup),
 132         ENA_STAT_TX_ENTRY(dma_mapping_err),
 133         ENA_STAT_TX_ENTRY(linearize),
 134         ENA_STAT_TX_ENTRY(linearize_failed),
 135         ENA_STAT_TX_ENTRY(tx_poll),
 136         ENA_STAT_TX_ENTRY(doorbells),
 137         ENA_STAT_TX_ENTRY(prepare_ctx_err),
 138         ENA_STAT_TX_ENTRY(missing_tx_comp),
 139         ENA_STAT_TX_ENTRY(bad_req_id),
 140 };
 141
 142 static const struct ena_stats ena_stats_rx_strings[] = {
 143         ENA_STAT_RX_ENTRY(cnt),
 144         ENA_STAT_RX_ENTRY(bytes),
 145         ENA_STAT_RX_ENTRY(refil_partial),
 146         ENA_STAT_RX_ENTRY(bad_csum),
 147         ENA_STAT_RX_ENTRY(page_alloc_fail),
 148         ENA_STAT_RX_ENTRY(skb_alloc_fail),
 149         ENA_STAT_RX_ENTRY(dma_mapping_err),
 150         ENA_STAT_RX_ENTRY(bad_desc_num),
 151         ENA_STAT_RX_ENTRY(small_copy_len_pkt),
 152 };
 153
 154 static const struct ena_stats ena_stats_ena_com_strings[] = {
 155         ENA_STAT_ENA_COM_ENTRY(aborted_cmd),
 156         ENA_STAT_ENA_COM_ENTRY(submitted_cmd),
 157         ENA_STAT_ENA_COM_ENTRY(completed_cmd),
 158         ENA_STAT_ENA_COM_ENTRY(out_of_space),
 159         ENA_STAT_ENA_COM_ENTRY(no_completion),
 160 };
 161
 162 #define ENA_STATS_ARRAY_GLOBAL  ARRAY_SIZE(ena_stats_global_strings)
 163 #define ENA_STATS_ARRAY_TX      ARRAY_SIZE(ena_stats_tx_strings)
 164 #define ENA_STATS_ARRAY_RX      ARRAY_SIZE(ena_stats_rx_strings)
 165 #define ENA_STATS_ARRAY_ENA_COM ARRAY_SIZE(ena_stats_ena_com_strings)
 166
 167 /** Vendor ID used by Amazon devices */
 168 #define PCI_VENDOR_ID_AMAZON 0x1D0F
 169 /** Amazon devices */
 170 #define PCI_DEVICE_ID_ENA_VF    0xEC20
 171 #define PCI_DEVICE_ID_ENA_LLQ_VF        0xEC21
 172
 173 #define ENA_TX_OFFLOAD_MASK     (\
 174         PKT_TX_L4_MASK |         \
 175         PKT_TX_IP_CKSUM |        \
 176         PKT_TX_TCP_SEG)
 177
 178 #define ENA_TX_OFFLOAD_NOTSUP_MASK      \
 179         (PKT_TX_OFFLOAD_MASK ^ ENA_TX_OFFLOAD_MASK)
 180
 181 static const struct rte_pci_id pci_id_ena_map[] = {
 182         { RTE_PCI_DEVICE(PCI_VENDOR_ID_AMAZON, PCI_DEVICE_ID_ENA_VF) },
 183         { RTE_PCI_DEVICE(PCI_VENDOR_ID_AMAZON, PCI_DEVICE_ID_ENA_LLQ_VF) },
 184         { .device_id = 0 },
 185 };
 186
 187 static int ena_device_init(struct ena_com_dev *ena_dev,
 188                            struct ena_com_dev_get_features_ctx *get_feat_ctx);
 189 static int ena_dev_configure(struct rte_eth_dev *dev);
 190 static uint16_t eth_ena_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
 191                                   uint16_t nb_pkts);
 192 static uint16_t eth_ena_prep_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
 193                 uint16_t nb_pkts);
 194 static int ena_tx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,
 195                               uint16_t nb_desc, unsigned int socket_id,
 196                               const struct rte_eth_txconf *tx_conf);
 197 static int ena_rx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,
 198                               uint16_t nb_desc, unsigned int socket_id,
 199                               const struct rte_eth_rxconf *rx_conf,
 200                               struct rte_mempool *mp);
 201 static uint16_t eth_ena_recv_pkts(void *rx_queue,
 202                                   struct rte_mbuf **rx_pkts, uint16_t nb_pkts);
 203 static int ena_populate_rx_queue(struct ena_ring *rxq, unsigned int count);
 204 static void ena_init_rings(struct ena_adapter *adapter);
 205 static int ena_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
 206 static int ena_start(struct rte_eth_dev *dev);
 207 static void ena_close(struct rte_eth_dev *dev);
 208 static void ena_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats);
 209 static void ena_rx_queue_release_all(struct rte_eth_dev *dev);
 210 static void ena_tx_queue_release_all(struct rte_eth_dev *dev);
 211 static void ena_rx_queue_release(void *queue);
 212 static void ena_tx_queue_release(void *queue);
 213 static void ena_rx_queue_release_bufs(struct ena_ring *ring);
 214 static void ena_tx_queue_release_bufs(struct ena_ring *ring);
 215 static int ena_link_update(struct rte_eth_dev *dev,
 216                            int wait_to_complete);
 217 static int ena_queue_restart(struct ena_ring *ring);
 218 static int ena_queue_restart_all(struct rte_eth_dev *dev,
 219                                  enum ena_ring_type ring_type);
 220 static void ena_stats_restart(struct rte_eth_dev *dev);
 221 static void ena_infos_get(struct rte_eth_dev *dev,
 222                           struct rte_eth_dev_info *dev_info);
 223 static int ena_rss_reta_update(struct rte_eth_dev *dev,
 224                                struct rte_eth_rss_reta_entry64 *reta_conf,
 225                                uint16_t reta_size);
 226 static int ena_rss_reta_query(struct rte_eth_dev *dev,
 227                               struct rte_eth_rss_reta_entry64 *reta_conf,
 228                               uint16_t reta_size);
 229 static int ena_get_sset_count(struct rte_eth_dev *dev, int sset);
 230
 231 static const struct eth_dev_ops ena_dev_ops = {
 232         .dev_configure        = ena_dev_configure,
 233         .dev_infos_get        = ena_infos_get,
 234         .rx_queue_setup       = ena_rx_queue_setup,
 235         .tx_queue_setup       = ena_tx_queue_setup,
 236         .dev_start            = ena_start,
 237         .link_update          = ena_link_update,
 238         .stats_get            = ena_stats_get,
 239         .mtu_set              = ena_mtu_set,
 240         .rx_queue_release     = ena_rx_queue_release,
 241         .tx_queue_release     = ena_tx_queue_release,
 242         .dev_close            = ena_close,
 243         .reta_update          = ena_rss_reta_update,
 244         .reta_query           = ena_rss_reta_query,
 245 };
 246
 247 #define NUMA_NO_NODE    SOCKET_ID_ANY
 248
 249 static inline int ena_cpu_to_node(int cpu)
 250 {
 251         struct rte_config *config = rte_eal_get_configuration();
 252
 253         if (likely(cpu < RTE_MAX_MEMZONE))
 254                 return config->mem_config->memzone[cpu].socket_id;
 255
 256         return NUMA_NO_NODE;
 257 }
 258
 259 static inline void ena_rx_mbuf_prepare(struct rte_mbuf *mbuf,
 260                                        struct ena_com_rx_ctx *ena_rx_ctx)
 261 {
 262         uint64_t ol_flags = 0;
 263
 264         if (ena_rx_ctx->l4_proto == ENA_ETH_IO_L4_PROTO_TCP)
 265                 ol_flags |= PKT_TX_TCP_CKSUM;
 266         else if (ena_rx_ctx->l4_proto == ENA_ETH_IO_L4_PROTO_UDP)
 267                 ol_flags |= PKT_TX_UDP_CKSUM;
 268
 269         if (ena_rx_ctx->l3_proto == ENA_ETH_IO_L3_PROTO_IPV4)
 270                 ol_flags |= PKT_TX_IPV4;
 271         else if (ena_rx_ctx->l3_proto == ENA_ETH_IO_L3_PROTO_IPV6)
 272                 ol_flags |= PKT_TX_IPV6;
 273
 274         if (unlikely(ena_rx_ctx->l4_csum_err))
 275                 ol_flags |= PKT_RX_L4_CKSUM_BAD;
 276         if (unlikely(ena_rx_ctx->l3_csum_err))
 277                 ol_flags |= PKT_RX_IP_CKSUM_BAD;
 278
 279         mbuf->ol_flags = ol_flags;
 280 }
 281
 282 static inline void ena_tx_mbuf_prepare(struct rte_mbuf *mbuf,
 283                                        struct ena_com_tx_ctx *ena_tx_ctx)
 284 {
 285         struct ena_com_tx_meta *ena_meta = &ena_tx_ctx->ena_meta;
 286
 287         if (mbuf->ol_flags &
 288             (PKT_TX_L4_MASK | PKT_TX_IP_CKSUM | PKT_TX_TCP_SEG)) {
 289                 /* check if TSO is required */
 290                 if (mbuf->ol_flags & PKT_TX_TCP_SEG) {
 291                         ena_tx_ctx->tso_enable = true;
 292
 293                         ena_meta->l4_hdr_len = GET_L4_HDR_LEN(mbuf);
 294                 }
 295
 296                 /* check if L3 checksum is needed */
 297                 if (mbuf->ol_flags & PKT_TX_IP_CKSUM)
 298                         ena_tx_ctx->l3_csum_enable = true;
 299
 300                 if (mbuf->ol_flags & PKT_TX_IPV6) {
 301                         ena_tx_ctx->l3_proto = ENA_ETH_IO_L3_PROTO_IPV6;
 302                 } else {
 303                         ena_tx_ctx->l3_proto = ENA_ETH_IO_L3_PROTO_IPV4;
 304
 305                         /* set don't fragment (DF) flag */
 306                         if (mbuf->packet_type &
 307                                 (RTE_PTYPE_L4_NONFRAG
 308                                  | RTE_PTYPE_INNER_L4_NONFRAG))
 309                                 ena_tx_ctx->df = true;
 310                 }
 311
 312                 /* check if L4 checksum is needed */
 313                 switch (mbuf->ol_flags & PKT_TX_L4_MASK) {
 314                 case PKT_TX_TCP_CKSUM:
 315                         ena_tx_ctx->l4_proto = ENA_ETH_IO_L4_PROTO_TCP;
 316                         ena_tx_ctx->l4_csum_enable = true;
 317                         break;
 318                 case PKT_TX_UDP_CKSUM:
 319                         ena_tx_ctx->l4_proto = ENA_ETH_IO_L4_PROTO_UDP;
 320                         ena_tx_ctx->l4_csum_enable = true;
 321                         break;
 322                 default:
 323                         ena_tx_ctx->l4_proto = ENA_ETH_IO_L4_PROTO_UNKNOWN;
 324                         ena_tx_ctx->l4_csum_enable = false;
 325                         break;
 326                 }
 327
 328                 ena_meta->mss = mbuf->tso_segsz;
 329                 ena_meta->l3_hdr_len = mbuf->l3_len;
 330                 ena_meta->l3_hdr_offset = mbuf->l2_len;
 331                 /* this param needed only for TSO */
 332                 ena_meta->l3_outer_hdr_len = 0;
 333                 ena_meta->l3_outer_hdr_offset = 0;
 334
 335                 ena_tx_ctx->meta_valid = true;
 336         } else {
 337                 ena_tx_ctx->meta_valid = false;
 338         }
 339 }
 340
 341 static void ena_config_host_info(struct ena_com_dev *ena_dev)
 342 {
 343         struct ena_admin_host_info *host_info;
 344         int rc;
 345
 346         /* Allocate only the host info */
 347         rc = ena_com_allocate_host_info(ena_dev);
 348         if (rc) {
 349                 RTE_LOG(ERR, PMD, "Cannot allocate host info\n");
 350                 return;
 351         }
 352
 353         host_info = ena_dev->host_attr.host_info;
 354
 355         host_info->os_type = ENA_ADMIN_OS_DPDK;
 356         host_info->kernel_ver = RTE_VERSION;
 357         snprintf((char *)host_info->kernel_ver_str,
 358                  sizeof(host_info->kernel_ver_str),
 359                  "%s", rte_version());
 360         host_info->os_dist = RTE_VERSION;
 361         snprintf((char *)host_info->os_dist_str,
 362                  sizeof(host_info->os_dist_str),
 363                  "%s", rte_version());
 364         host_info->driver_version =
 365                 (DRV_MODULE_VER_MAJOR) |
 366                 (DRV_MODULE_VER_MINOR << ENA_ADMIN_HOST_INFO_MINOR_SHIFT) |
 367                 (DRV_MODULE_VER_SUBMINOR <<
 368                         ENA_ADMIN_HOST_INFO_SUB_MINOR_SHIFT);
 369
 370         rc = ena_com_set_host_attributes(ena_dev);
 371         if (rc) {
 372                 RTE_LOG(ERR, PMD, "Cannot set host attributes\n");
 373                 if (rc != -EPERM)
 374                         goto err;
 375         }
 376
 377         return;
 378
 379 err:
 380         ena_com_delete_host_info(ena_dev);
 381 }
 382
 383 static int
 384 ena_get_sset_count(struct rte_eth_dev *dev, int sset)
 385 {
 386         if (sset != ETH_SS_STATS)
 387                 return -EOPNOTSUPP;
 388
 389          /* Workaround for clang:
 390          * touch internal structures to prevent
 391          * compiler error
 392          */
 393         ENA_TOUCH(ena_stats_global_strings);
 394         ENA_TOUCH(ena_stats_tx_strings);
 395         ENA_TOUCH(ena_stats_rx_strings);
 396         ENA_TOUCH(ena_stats_ena_com_strings);
 397
 398         return  dev->data->nb_tx_queues *
 399                 (ENA_STATS_ARRAY_TX + ENA_STATS_ARRAY_RX) +
 400                 ENA_STATS_ARRAY_GLOBAL + ENA_STATS_ARRAY_ENA_COM;
 401 }
 402
 403 static void ena_config_debug_area(struct ena_adapter *adapter)
 404 {
 405         u32 debug_area_size;
 406         int rc, ss_count;
 407
 408         ss_count = ena_get_sset_count(adapter->rte_dev, ETH_SS_STATS);
 409         if (ss_count <= 0) {
 410                 RTE_LOG(ERR, PMD, "SS count is negative\n");
 411                 return;
 412         }
 413
 414         /* allocate 32 bytes for each string and 64bit for the value */
 415         debug_area_size = ss_count * ETH_GSTRING_LEN + sizeof(u64) * ss_count;
 416
 417         rc = ena_com_allocate_debug_area(&adapter->ena_dev, debug_area_size);
 418         if (rc) {
 419                 RTE_LOG(ERR, PMD, "Cannot allocate debug area\n");
 420                 return;
 421         }
 422
 423         rc = ena_com_set_host_attributes(&adapter->ena_dev);
 424         if (rc) {
 425                 RTE_LOG(WARNING, PMD, "Cannot set host attributes\n");
 426                 if (rc != -EPERM)
 427                         goto err;
 428         }
 429
 430         return;
 431 err:
 432         ena_com_delete_debug_area(&adapter->ena_dev);
 433 }
 434
 435 static void ena_close(struct rte_eth_dev *dev)
 436 {
 437         struct ena_adapter *adapter =
 438                 (struct ena_adapter *)(dev->data->dev_private);
 439
 440         adapter->state = ENA_ADAPTER_STATE_STOPPED;
 441
 442         ena_rx_queue_release_all(dev);
 443         ena_tx_queue_release_all(dev);
 444 }
 445
 446 static int ena_rss_reta_update(struct rte_eth_dev *dev,
 447                                struct rte_eth_rss_reta_entry64 *reta_conf,
 448                                uint16_t reta_size)
 449 {
 450         struct ena_adapter *adapter =
 451                 (struct ena_adapter *)(dev->data->dev_private);
 452         struct ena_com_dev *ena_dev = &adapter->ena_dev;
 453         int ret, i;
 454         u16 entry_value;
 455         int conf_idx;
 456         int idx;
 457
 458         if ((reta_size == 0) || (reta_conf == NULL))
 459                 return -EINVAL;
 460
 461         if (reta_size > ENA_RX_RSS_TABLE_SIZE) {
 462                 RTE_LOG(WARNING, PMD,
 463                         "indirection table %d is bigger than supported (%d)\n",
 464                         reta_size, ENA_RX_RSS_TABLE_SIZE);
 465                 ret = -EINVAL;
 466                 goto err;
 467         }
 468
 469         for (i = 0 ; i < reta_size ; i++) {
 470                 /* each reta_conf is for 64 entries.
 471                  * to support 128 we use 2 conf of 64
 472                  */
 473                 conf_idx = i / RTE_RETA_GROUP_SIZE;
 474                 idx = i % RTE_RETA_GROUP_SIZE;
 475                 if (TEST_BIT(reta_conf[conf_idx].mask, idx)) {
 476                         entry_value =
 477                                 ENA_IO_RXQ_IDX(reta_conf[conf_idx].reta[idx]);
 478                         ret = ena_com_indirect_table_fill_entry(ena_dev,
 479                                                                 i,
 480                                                                 entry_value);
 481                         if (unlikely(ret && (ret != ENA_COM_PERMISSION))) {
 482                                 RTE_LOG(ERR, PMD,
 483                                         "Cannot fill indirect table\n");
 484                                 ret = -ENOTSUP;
 485                                 goto err;
 486                         }
 487                 }
 488         }
 489
 490         ret = ena_com_indirect_table_set(ena_dev);
 491         if (unlikely(ret && (ret != ENA_COM_PERMISSION))) {
 492                 RTE_LOG(ERR, PMD, "Cannot flush the indirect table\n");
 493                 ret = -ENOTSUP;
 494                 goto err;
 495         }
 496
 497         RTE_LOG(DEBUG, PMD, "%s(): RSS configured %d entries  for port %d\n",
 498                 __func__, reta_size, adapter->rte_dev->data->port_id);
 499 err:
 500         return ret;
 501 }
 502
 503 /* Query redirection table. */
 504 static int ena_rss_reta_query(struct rte_eth_dev *dev,
 505                               struct rte_eth_rss_reta_entry64 *reta_conf,
 506                               uint16_t reta_size)
 507 {
 508         struct ena_adapter *adapter =
 509                 (struct ena_adapter *)(dev->data->dev_private);
 510         struct ena_com_dev *ena_dev = &adapter->ena_dev;
 511         int ret;
 512         int i;
 513         u32 indirect_table[ENA_RX_RSS_TABLE_SIZE] = {0};
 514         int reta_conf_idx;
 515         int reta_idx;
 516
 517         if (reta_size == 0 || reta_conf == NULL ||
 518             (reta_size > RTE_RETA_GROUP_SIZE && ((reta_conf + 1) == NULL)))
 519                 return -EINVAL;
 520
 521         ret = ena_com_indirect_table_get(ena_dev, indirect_table);
 522         if (unlikely(ret && (ret != ENA_COM_PERMISSION))) {
 523                 RTE_LOG(ERR, PMD, "cannot get indirect table\n");
 524                 ret = -ENOTSUP;
 525                 goto err;
 526         }
 527
 528         for (i = 0 ; i < reta_size ; i++) {
 529                 reta_conf_idx = i / RTE_RETA_GROUP_SIZE;
 530                 reta_idx = i % RTE_RETA_GROUP_SIZE;
 531                 if (TEST_BIT(reta_conf[reta_conf_idx].mask, reta_idx))
 532                         reta_conf[reta_conf_idx].reta[reta_idx] =
 533                                 ENA_IO_RXQ_IDX_REV(indirect_table[i]);
 534         }
 535 err:
 536         return ret;
 537 }
 538
 539 static int ena_rss_init_default(struct ena_adapter *adapter)
 540 {
 541         struct ena_com_dev *ena_dev = &adapter->ena_dev;
 542         uint16_t nb_rx_queues = adapter->rte_dev->data->nb_rx_queues;
 543         int rc, i;
 544         u32 val;
 545
 546         rc = ena_com_rss_init(ena_dev, ENA_RX_RSS_TABLE_LOG_SIZE);
 547         if (unlikely(rc)) {
 548                 RTE_LOG(ERR, PMD, "Cannot init indirect table\n");
 549                 goto err_rss_init;
 550         }
 551
 552         for (i = 0; i < ENA_RX_RSS_TABLE_SIZE; i++) {
 553                 val = i % nb_rx_queues;
 554                 rc = ena_com_indirect_table_fill_entry(ena_dev, i,
 555                                                        ENA_IO_RXQ_IDX(val));
 556                 if (unlikely(rc && (rc != ENA_COM_PERMISSION))) {
 557                         RTE_LOG(ERR, PMD, "Cannot fill indirect table\n");
 558                         goto err_fill_indir;
 559                 }
 560         }
 561
 562         rc = ena_com_fill_hash_function(ena_dev, ENA_ADMIN_CRC32, NULL,
 563                                         ENA_HASH_KEY_SIZE, 0xFFFFFFFF);
 564         if (unlikely(rc && (rc != ENA_COM_PERMISSION))) {
 565                 RTE_LOG(INFO, PMD, "Cannot fill hash function\n");
 566                 goto err_fill_indir;
 567         }
 568
 569         rc = ena_com_set_default_hash_ctrl(ena_dev);
 570         if (unlikely(rc && (rc != ENA_COM_PERMISSION))) {
 571                 RTE_LOG(INFO, PMD, "Cannot fill hash control\n");
 572                 goto err_fill_indir;
 573         }
 574
 575         rc = ena_com_indirect_table_set(ena_dev);
 576         if (unlikely(rc && (rc != ENA_COM_PERMISSION))) {
 577                 RTE_LOG(ERR, PMD, "Cannot flush the indirect table\n");
 578                 goto err_fill_indir;
 579         }
 580         RTE_LOG(DEBUG, PMD, "RSS configured for port %d\n",
 581                 adapter->rte_dev->data->port_id);
 582
 583         return 0;
 584
 585 err_fill_indir:
 586         ena_com_rss_destroy(ena_dev);
 587 err_rss_init:
 588
 589         return rc;
 590 }
 591
 592 static void ena_rx_queue_release_all(struct rte_eth_dev *dev)
 593 {
 594         struct ena_ring **queues = (struct ena_ring **)dev->data->rx_queues;
 595         int nb_queues = dev->data->nb_rx_queues;
 596         int i;
 597
 598         for (i = 0; i < nb_queues; i++)
 599                 ena_rx_queue_release(queues[i]);
 600 }
 601
 602 static void ena_tx_queue_release_all(struct rte_eth_dev *dev)
 603 {
 604         struct ena_ring **queues = (struct ena_ring **)dev->data->tx_queues;
 605         int nb_queues = dev->data->nb_tx_queues;
 606         int i;
 607
 608         for (i = 0; i < nb_queues; i++)
 609                 ena_tx_queue_release(queues[i]);
 610 }
 611
 612 static void ena_rx_queue_release(void *queue)
 613 {
 614         struct ena_ring *ring = (struct ena_ring *)queue;
 615         struct ena_adapter *adapter = ring->adapter;
 616         int ena_qid;
 617
 618         ena_assert_msg(ring->configured,
 619                        "API violation - releasing not configured queue");
 620         ena_assert_msg(ring->adapter->state != ENA_ADAPTER_STATE_RUNNING,
 621                        "API violation");
 622
 623         /* Destroy HW queue */
 624         ena_qid = ENA_IO_RXQ_IDX(ring->id);
 625         ena_com_destroy_io_queue(&adapter->ena_dev, ena_qid);
 626
 627         /* Free all bufs */
 628         ena_rx_queue_release_bufs(ring);
 629
 630         /* Free ring resources */
 631         if (ring->rx_buffer_info)
 632                 rte_free(ring->rx_buffer_info);
 633         ring->rx_buffer_info = NULL;
 634
 635         ring->configured = 0;
 636
 637         RTE_LOG(NOTICE, PMD, "RX Queue %d:%d released\n",
 638                 ring->port_id, ring->id);
 639 }
 640
 641 static void ena_tx_queue_release(void *queue)
 642 {
 643         struct ena_ring *ring = (struct ena_ring *)queue;
 644         struct ena_adapter *adapter = ring->adapter;
 645         int ena_qid;
 646
 647         ena_assert_msg(ring->configured,
 648                        "API violation. Releasing not configured queue");
 649         ena_assert_msg(ring->adapter->state != ENA_ADAPTER_STATE_RUNNING,
 650                        "API violation");
 651
 652         /* Destroy HW queue */
 653         ena_qid = ENA_IO_TXQ_IDX(ring->id);
 654         ena_com_destroy_io_queue(&adapter->ena_dev, ena_qid);
 655
 656         /* Free all bufs */
 657         ena_tx_queue_release_bufs(ring);
 658
 659         /* Free ring resources */
 660         if (ring->tx_buffer_info)
 661                 rte_free(ring->tx_buffer_info);
 662
 663         if (ring->empty_tx_reqs)
 664                 rte_free(ring->empty_tx_reqs);
 665
 666         ring->empty_tx_reqs = NULL;
 667         ring->tx_buffer_info = NULL;
 668
 669         ring->configured = 0;
 670
 671         RTE_LOG(NOTICE, PMD, "TX Queue %d:%d released\n",
 672                 ring->port_id, ring->id);
 673 }
 674
 675 static void ena_rx_queue_release_bufs(struct ena_ring *ring)
 676 {
 677         unsigned int ring_mask = ring->ring_size - 1;
 678
 679         while (ring->next_to_clean != ring->next_to_use) {
 680                 struct rte_mbuf *m =
 681                         ring->rx_buffer_info[ring->next_to_clean & ring_mask];
 682
 683                 if (m)
 684                         rte_mbuf_raw_free(m);
 685
 686                 ring->next_to_clean++;
 687         }
 688 }
 689
 690 static void ena_tx_queue_release_bufs(struct ena_ring *ring)
 691 {
 692         unsigned int i;
 693
 694         for (i = 0; i < ring->ring_size; ++i) {
 695                 struct ena_tx_buffer *tx_buf = &ring->tx_buffer_info[i];
 696
 697                 if (tx_buf->mbuf)
 698                         rte_pktmbuf_free(tx_buf->mbuf);
 699
 700                 ring->next_to_clean++;
 701         }
 702 }
 703
 704 static int ena_link_update(struct rte_eth_dev *dev,
 705                            __rte_unused int wait_to_complete)
 706 {
 707         struct rte_eth_link *link = &dev->data->dev_link;
 708
 709         link->link_status = 1;
 710         link->link_speed = ETH_SPEED_NUM_10G;
 711         link->link_duplex = ETH_LINK_FULL_DUPLEX;
 712
 713         return 0;
 714 }
 715
 716 static int ena_queue_restart_all(struct rte_eth_dev *dev,
 717                                  enum ena_ring_type ring_type)
 718 {
 719         struct ena_adapter *adapter =
 720                 (struct ena_adapter *)(dev->data->dev_private);
 721         struct ena_ring *queues = NULL;
 722         int i = 0;
 723         int rc = 0;
 724
 725         queues = (ring_type == ENA_RING_TYPE_RX) ?
 726                 adapter->rx_ring : adapter->tx_ring;
 727
 728         for (i = 0; i < adapter->num_queues; i++) {
 729                 if (queues[i].configured) {
 730                         if (ring_type == ENA_RING_TYPE_RX) {
 731                                 ena_assert_msg(
 732                                         dev->data->rx_queues[i] == &queues[i],
 733                                         "Inconsistent state of rx queues\n");
 734                         } else {
 735                                 ena_assert_msg(
 736                                         dev->data->tx_queues[i] == &queues[i],
 737                                         "Inconsistent state of tx queues\n");
 738                         }
 739
 740                         rc = ena_queue_restart(&queues[i]);
 741
 742                         if (rc) {
 743                                 PMD_INIT_LOG(ERR,
 744                                              "failed to restart queue %d type(%d)",
 745                                              i, ring_type);
 746                                 return -1;
 747                         }
 748                 }
 749         }
 750
 751         return 0;
 752 }
 753
 754 static uint32_t ena_get_mtu_conf(struct ena_adapter *adapter)
 755 {
 756         uint32_t max_frame_len = adapter->max_mtu;
 757
 758         if (adapter->rte_eth_dev_data->dev_conf.rxmode.jumbo_frame == 1)
 759                 max_frame_len =
 760                         adapter->rte_eth_dev_data->dev_conf.rxmode.max_rx_pkt_len;
 761
 762         return max_frame_len;
 763 }
 764
 765 static int ena_check_valid_conf(struct ena_adapter *adapter)
 766 {
 767         uint32_t max_frame_len = ena_get_mtu_conf(adapter);
 768
 769         if (max_frame_len > adapter->max_mtu) {
 770                 PMD_INIT_LOG(ERR, "Unsupported MTU of %d", max_frame_len);
 771                 return -1;
 772         }
 773
 774         return 0;
 775 }
 776
 777 static int
 778 ena_calc_queue_size(struct ena_com_dev *ena_dev,
 779                     struct ena_com_dev_get_features_ctx *get_feat_ctx)
 780 {
 781         uint32_t queue_size = ENA_DEFAULT_RING_SIZE;
 782
 783         queue_size = RTE_MIN(queue_size,
 784                              get_feat_ctx->max_queues.max_cq_depth);
 785         queue_size = RTE_MIN(queue_size,
 786                              get_feat_ctx->max_queues.max_sq_depth);
 787
 788         if (ena_dev->tx_mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_DEV)
 789                 queue_size = RTE_MIN(queue_size,
 790                                      get_feat_ctx->max_queues.max_llq_depth);
 791
 792         /* Round down to power of 2 */
 793         if (!rte_is_power_of_2(queue_size))
 794                 queue_size = rte_align32pow2(queue_size >> 1);
 795
 796         if (queue_size == 0) {
 797                 PMD_INIT_LOG(ERR, "Invalid queue size");
 798                 return -EFAULT;
 799         }
 800
 801         return queue_size;
 802 }
 803
 804 static void ena_stats_restart(struct rte_eth_dev *dev)
 805 {
 806         struct ena_adapter *adapter =
 807                 (struct ena_adapter *)(dev->data->dev_private);
 808
 809         rte_atomic64_init(&adapter->drv_stats->ierrors);
 810         rte_atomic64_init(&adapter->drv_stats->oerrors);
 811         rte_atomic64_init(&adapter->drv_stats->rx_nombuf);
 812 }
 813
 814 static void ena_stats_get(struct rte_eth_dev *dev,
 815                           struct rte_eth_stats *stats)
 816 {
 817         struct ena_admin_basic_stats ena_stats;
 818         struct ena_adapter *adapter =
 819                 (struct ena_adapter *)(dev->data->dev_private);
 820         struct ena_com_dev *ena_dev = &adapter->ena_dev;
 821         int rc;
 822
 823         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
 824                 return;
 825
 826         memset(&ena_stats, 0, sizeof(ena_stats));
 827         rc = ena_com_get_dev_basic_stats(ena_dev, &ena_stats);
 828         if (unlikely(rc)) {
 829                 RTE_LOG(ERR, PMD, "Could not retrieve statistics from ENA");
 830                 return;
 831         }
 832
 833         /* Set of basic statistics from ENA */
 834         stats->ipackets = __MERGE_64B_H_L(ena_stats.rx_pkts_high,
 835                                           ena_stats.rx_pkts_low);
 836         stats->opackets = __MERGE_64B_H_L(ena_stats.tx_pkts_high,
 837                                           ena_stats.tx_pkts_low);
 838         stats->ibytes = __MERGE_64B_H_L(ena_stats.rx_bytes_high,
 839                                         ena_stats.rx_bytes_low);
 840         stats->obytes = __MERGE_64B_H_L(ena_stats.tx_bytes_high,
 841                                         ena_stats.tx_bytes_low);
 842         stats->imissed = __MERGE_64B_H_L(ena_stats.rx_drops_high,
 843                                          ena_stats.rx_drops_low);
 844
 845         /* Driver related stats */
 846         stats->ierrors = rte_atomic64_read(&adapter->drv_stats->ierrors);
 847         stats->oerrors = rte_atomic64_read(&adapter->drv_stats->oerrors);
 848         stats->rx_nombuf = rte_atomic64_read(&adapter->drv_stats->rx_nombuf);
 849 }
 850
 851 static int ena_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
 852 {
 853         struct ena_adapter *adapter;
 854         struct ena_com_dev *ena_dev;
 855         int rc = 0;
 856
 857         ena_assert_msg(dev->data != NULL, "Uninitialized device");
 858         ena_assert_msg(dev->data->dev_private != NULL, "Uninitialized device");
 859         adapter = (struct ena_adapter *)(dev->data->dev_private);
 860
 861         ena_dev = &adapter->ena_dev;
 862         ena_assert_msg(ena_dev != NULL, "Uninitialized device");
 863
 864         if (mtu > ena_get_mtu_conf(adapter)) {
 865                 RTE_LOG(ERR, PMD,
 866                         "Given MTU (%d) exceeds maximum MTU supported (%d)\n",
 867                         mtu, ena_get_mtu_conf(adapter));
 868                 rc = -EINVAL;
 869                 goto err;
 870         }
 871
 872         rc = ena_com_set_dev_mtu(ena_dev, mtu);
 873         if (rc)
 874                 RTE_LOG(ERR, PMD, "Could not set MTU: %d\n", mtu);
 875         else
 876                 RTE_LOG(NOTICE, PMD, "Set MTU: %d\n", mtu);
 877
 878 err:
 879         return rc;
 880 }
 881
 882 static int ena_start(struct rte_eth_dev *dev)
 883 {
 884         struct ena_adapter *adapter =
 885                 (struct ena_adapter *)(dev->data->dev_private);
 886         int rc = 0;
 887
 888         if (!(adapter->state == ENA_ADAPTER_STATE_CONFIG ||
 889               adapter->state == ENA_ADAPTER_STATE_STOPPED)) {
 890                 PMD_INIT_LOG(ERR, "API violation");
 891                 return -1;
 892         }
 893
 894         rc = ena_check_valid_conf(adapter);
 895         if (rc)
 896                 return rc;
 897
 898         rc = ena_queue_restart_all(dev, ENA_RING_TYPE_RX);
 899         if (rc)
 900                 return rc;
 901
 902         rc = ena_queue_restart_all(dev, ENA_RING_TYPE_TX);
 903         if (rc)
 904                 return rc;
 905
 906         if (adapter->rte_dev->data->dev_conf.rxmode.mq_mode &
 907             ETH_MQ_RX_RSS_FLAG) {
 908                 rc = ena_rss_init_default(adapter);
 909                 if (rc)
 910                         return rc;
 911         }
 912
 913         ena_stats_restart(dev);
 914
 915         adapter->state = ENA_ADAPTER_STATE_RUNNING;
 916
 917         return 0;
 918 }
 919
 920 static int ena_queue_restart(struct ena_ring *ring)
 921 {
 922         int rc, bufs_num;
 923
 924         ena_assert_msg(ring->configured == 1,
 925                        "Trying to restart unconfigured queue\n");
 926
 927         ring->next_to_clean = 0;
 928         ring->next_to_use = 0;
 929
 930         if (ring->type == ENA_RING_TYPE_TX)
 931                 return 0;
 932
 933         bufs_num = ring->ring_size - 1;
 934         rc = ena_populate_rx_queue(ring, bufs_num);
 935         if (rc != bufs_num) {
 936                 PMD_INIT_LOG(ERR, "Failed to populate rx ring !");
 937                 return (-1);
 938         }
 939
 940         return 0;
 941 }
 942
 943 static int ena_tx_queue_setup(struct rte_eth_dev *dev,
 944                               uint16_t queue_idx,
 945                               uint16_t nb_desc,
 946                               __rte_unused unsigned int socket_id,
 947                               __rte_unused const struct rte_eth_txconf *tx_conf)
 948 {
 949         struct ena_com_create_io_ctx ctx =
 950                 /* policy set to _HOST just to satisfy icc compiler */
 951                 { ENA_ADMIN_PLACEMENT_POLICY_HOST,
 952                   ENA_COM_IO_QUEUE_DIRECTION_TX, 0, 0, 0, 0 };
 953         struct ena_ring *txq = NULL;
 954         struct ena_adapter *adapter =
 955                 (struct ena_adapter *)(dev->data->dev_private);
 956         unsigned int i;
 957         int ena_qid;
 958         int rc;
 959         struct ena_com_dev *ena_dev = &adapter->ena_dev;
 960
 961         txq = &adapter->tx_ring[queue_idx];
 962
 963         if (txq->configured) {
 964                 RTE_LOG(CRIT, PMD,
 965                         "API violation. Queue %d is already configured\n",
 966                         queue_idx);
 967                 return -1;
 968         }
 969
 970         if (!rte_is_power_of_2(nb_desc)) {
 971                 RTE_LOG(ERR, PMD,
 972                         "Unsupported size of RX queue: %d is not a power of 2.",
 973                         nb_desc);
 974                 return -EINVAL;
 975         }
 976
 977         if (nb_desc > adapter->tx_ring_size) {
 978                 RTE_LOG(ERR, PMD,
 979                         "Unsupported size of TX queue (max size: %d)\n",
 980                         adapter->tx_ring_size);
 981                 return -EINVAL;
 982         }
 983
 984         ena_qid = ENA_IO_TXQ_IDX(queue_idx);
 985
 986         ctx.direction = ENA_COM_IO_QUEUE_DIRECTION_TX;
 987         ctx.qid = ena_qid;
 988         ctx.msix_vector = -1; /* admin interrupts not used */
 989         ctx.mem_queue_type = ena_dev->tx_mem_queue_type;
 990         ctx.queue_size = adapter->tx_ring_size;
 991         ctx.numa_node = ena_cpu_to_node(queue_idx);
 992
 993         rc = ena_com_create_io_queue(ena_dev, &ctx);
 994         if (rc) {
 995                 RTE_LOG(ERR, PMD,
 996                         "failed to create io TX queue #%d (qid:%d) rc: %d\n",
 997                         queue_idx, ena_qid, rc);
 998         }
 999         txq->ena_com_io_cq = &ena_dev->io_cq_queues[ena_qid];
1000         txq->ena_com_io_sq = &ena_dev->io_sq_queues[ena_qid];
1001
1002         rc = ena_com_get_io_handlers(ena_dev, ena_qid,
1003                                      &txq->ena_com_io_sq,
1004                                      &txq->ena_com_io_cq);
1005         if (rc) {
1006                 RTE_LOG(ERR, PMD,
1007                         "Failed to get TX queue handlers. TX queue num %d rc: %d\n",
1008                         queue_idx, rc);
1009                 ena_com_destroy_io_queue(ena_dev, ena_qid);
1010                 goto err;
1011         }
1012
1013         txq->port_id = dev->data->port_id;
1014         txq->next_to_clean = 0;
1015         txq->next_to_use = 0;
1016         txq->ring_size = nb_desc;
1017
1018         txq->tx_buffer_info = rte_zmalloc("txq->tx_buffer_info",
1019                                           sizeof(struct ena_tx_buffer) *
1020                                           txq->ring_size,
1021                                           RTE_CACHE_LINE_SIZE);
1022         if (!txq->tx_buffer_info) {
1023                 RTE_LOG(ERR, PMD, "failed to alloc mem for tx buffer info\n");
1024                 return -ENOMEM;
1025         }
1026
1027         txq->empty_tx_reqs = rte_zmalloc("txq->empty_tx_reqs",
1028                                          sizeof(u16) * txq->ring_size,
1029                                          RTE_CACHE_LINE_SIZE);
1030         if (!txq->empty_tx_reqs) {
1031                 RTE_LOG(ERR, PMD, "failed to alloc mem for tx reqs\n");
1032                 rte_free(txq->tx_buffer_info);
1033                 return -ENOMEM;
1034         }
1035         for (i = 0; i < txq->ring_size; i++)
1036                 txq->empty_tx_reqs[i] = i;
1037
1038         /* Store pointer to this queue in upper layer */
1039         txq->configured = 1;
1040         dev->data->tx_queues[queue_idx] = txq;
1041 err:
1042         return rc;
1043 }
1044
1045 static int ena_rx_queue_setup(struct rte_eth_dev *dev,
1046                               uint16_t queue_idx,
1047                               uint16_t nb_desc,
1048                               __rte_unused unsigned int socket_id,
1049                               __rte_unused const struct rte_eth_rxconf *rx_conf,
1050                               struct rte_mempool *mp)
1051 {
1052         struct ena_com_create_io_ctx ctx =
1053                 /* policy set to _HOST just to satisfy icc compiler */
1054                 { ENA_ADMIN_PLACEMENT_POLICY_HOST,
1055                   ENA_COM_IO_QUEUE_DIRECTION_RX, 0, 0, 0, 0 };
1056         struct ena_adapter *adapter =
1057                 (struct ena_adapter *)(dev->data->dev_private);
1058         struct ena_ring *rxq = NULL;
1059         uint16_t ena_qid = 0;
1060         int rc = 0;
1061         struct ena_com_dev *ena_dev = &adapter->ena_dev;
1062
1063         rxq = &adapter->rx_ring[queue_idx];
1064         if (rxq->configured) {
1065                 RTE_LOG(CRIT, PMD,
1066                         "API violation. Queue %d is already configured\n",
1067                         queue_idx);
1068                 return -1;
1069         }
1070
1071         if (!rte_is_power_of_2(nb_desc)) {
1072                 RTE_LOG(ERR, PMD,
1073                         "Unsupported size of TX queue: %d is not a power of 2.",
1074                         nb_desc);
1075                 return -EINVAL;
1076         }
1077
1078         if (nb_desc > adapter->rx_ring_size) {
1079                 RTE_LOG(ERR, PMD,
1080                         "Unsupported size of RX queue (max size: %d)\n",
1081                         adapter->rx_ring_size);
1082                 return -EINVAL;
1083         }
1084
1085         ena_qid = ENA_IO_RXQ_IDX(queue_idx);
1086
1087         ctx.qid = ena_qid;
1088         ctx.direction = ENA_COM_IO_QUEUE_DIRECTION_RX;
1089         ctx.mem_queue_type = ENA_ADMIN_PLACEMENT_POLICY_HOST;
1090         ctx.msix_vector = -1; /* admin interrupts not used */
1091         ctx.queue_size = adapter->rx_ring_size;
1092         ctx.numa_node = ena_cpu_to_node(queue_idx);
1093
1094         rc = ena_com_create_io_queue(ena_dev, &ctx);
1095         if (rc)
1096                 RTE_LOG(ERR, PMD, "failed to create io RX queue #%d rc: %d\n",
1097                         queue_idx, rc);
1098
1099         rxq->ena_com_io_cq = &ena_dev->io_cq_queues[ena_qid];
1100         rxq->ena_com_io_sq = &ena_dev->io_sq_queues[ena_qid];
1101
1102         rc = ena_com_get_io_handlers(ena_dev, ena_qid,
1103                                      &rxq->ena_com_io_sq,
1104                                      &rxq->ena_com_io_cq);
1105         if (rc) {
1106                 RTE_LOG(ERR, PMD,
1107                         "Failed to get RX queue handlers. RX queue num %d rc: %d\n",
1108                         queue_idx, rc);
1109                 ena_com_destroy_io_queue(ena_dev, ena_qid);
1110         }
1111
1112         rxq->port_id = dev->data->port_id;
1113         rxq->next_to_clean = 0;
1114         rxq->next_to_use = 0;
1115         rxq->ring_size = nb_desc;
1116         rxq->mb_pool = mp;
1117
1118         rxq->rx_buffer_info = rte_zmalloc("rxq->buffer_info",
1119                                           sizeof(struct rte_mbuf *) * nb_desc,
1120                                           RTE_CACHE_LINE_SIZE);
1121         if (!rxq->rx_buffer_info) {
1122                 RTE_LOG(ERR, PMD, "failed to alloc mem for rx buffer info\n");
1123                 return -ENOMEM;
1124         }
1125
1126         /* Store pointer to this queue in upper layer */
1127         rxq->configured = 1;
1128         dev->data->rx_queues[queue_idx] = rxq;
1129
1130         return rc;
1131 }
1132
1133 static int ena_populate_rx_queue(struct ena_ring *rxq, unsigned int count)
1134 {
1135         unsigned int i;
1136         int rc;
1137         uint16_t ring_size = rxq->ring_size;
1138         uint16_t ring_mask = ring_size - 1;
1139         uint16_t next_to_use = rxq->next_to_use;
1140         uint16_t in_use;
1141         struct rte_mbuf **mbufs = &rxq->rx_buffer_info[0];
1142
1143         if (unlikely(!count))
1144                 return 0;
1145
1146         in_use = rxq->next_to_use - rxq->next_to_clean;
1147         ena_assert_msg(((in_use + count) < ring_size), "bad ring state");
1148
1149         count = RTE_MIN(count,
1150                         (uint16_t)(ring_size - (next_to_use & ring_mask)));
1151
1152         /* get resources for incoming packets */
1153         rc = rte_mempool_get_bulk(rxq->mb_pool,
1154                                   (void **)(&mbufs[next_to_use & ring_mask]),
1155                                   count);
1156         if (unlikely(rc < 0)) {
1157                 rte_atomic64_inc(&rxq->adapter->drv_stats->rx_nombuf);
1158                 PMD_RX_LOG(DEBUG, "there are no enough free buffers");
1159                 return 0;
1160         }
1161
1162         for (i = 0; i < count; i++) {
1163                 uint16_t next_to_use_masked = next_to_use & ring_mask;
1164                 struct rte_mbuf *mbuf = mbufs[next_to_use_masked];
1165                 struct ena_com_buf ebuf;
1166
1167                 rte_prefetch0(mbufs[((next_to_use + 4) & ring_mask)]);
1168                 /* prepare physical address for DMA transaction */
1169                 ebuf.paddr = mbuf->buf_physaddr + RTE_PKTMBUF_HEADROOM;
1170                 ebuf.len = mbuf->buf_len - RTE_PKTMBUF_HEADROOM;
1171                 /* pass resource to device */
1172                 rc = ena_com_add_single_rx_desc(rxq->ena_com_io_sq,
1173                                                 &ebuf, next_to_use_masked);
1174                 if (unlikely(rc)) {
1175                         rte_mempool_put_bulk(rxq->mb_pool, (void **)(&mbuf),
1176                                              count - i);
1177                         RTE_LOG(WARNING, PMD, "failed adding rx desc\n");
1178                         break;
1179                 }
1180                 next_to_use++;
1181         }
1182
1183         /* When we submitted free recources to device... */
1184         if (i > 0) {
1185                 /* ...let HW know that it can fill buffers with data */
1186                 rte_wmb();
1187                 ena_com_write_sq_doorbell(rxq->ena_com_io_sq);
1188
1189                 rxq->next_to_use = next_to_use;
1190         }
1191
1192         return i;
1193 }
1194
1195 static int ena_device_init(struct ena_com_dev *ena_dev,
1196                            struct ena_com_dev_get_features_ctx *get_feat_ctx)
1197 {
1198         int rc;
1199         bool readless_supported;
1200
1201         /* Initialize mmio registers */
1202         rc = ena_com_mmio_reg_read_request_init(ena_dev);
1203         if (rc) {
1204                 RTE_LOG(ERR, PMD, "failed to init mmio read less\n");
1205                 return rc;
1206         }
1207
1208         /* The PCIe configuration space revision id indicate if mmio reg
1209          * read is disabled.
1210          */
1211         readless_supported =
1212                 !(((struct rte_pci_device *)ena_dev->dmadev)->id.class_id
1213                                & ENA_MMIO_DISABLE_REG_READ);
1214         ena_com_set_mmio_read_mode(ena_dev, readless_supported);
1215
1216         /* reset device */
1217         rc = ena_com_dev_reset(ena_dev);
1218         if (rc) {
1219                 RTE_LOG(ERR, PMD, "cannot reset device\n");
1220                 goto err_mmio_read_less;
1221         }
1222
1223         /* check FW version */
1224         rc = ena_com_validate_version(ena_dev);
1225         if (rc) {
1226                 RTE_LOG(ERR, PMD, "device version is too low\n");
1227                 goto err_mmio_read_less;
1228         }
1229
1230         ena_dev->dma_addr_bits = ena_com_get_dma_width(ena_dev);
1231
1232         /* ENA device administration layer init */
1233         rc = ena_com_admin_init(ena_dev, NULL, true);
1234         if (rc) {
1235                 RTE_LOG(ERR, PMD,
1236                         "cannot initialize ena admin queue with device\n");
1237                 goto err_mmio_read_less;
1238         }
1239
1240         /* To enable the msix interrupts the driver needs to know the number
1241          * of queues. So the driver uses polling mode to retrieve this
1242          * information.
1243          */
1244         ena_com_set_admin_polling_mode(ena_dev, true);
1245
1246         ena_config_host_info(ena_dev);
1247
1248         /* Get Device Attributes and features */
1249         rc = ena_com_get_dev_attr_feat(ena_dev, get_feat_ctx);
1250         if (rc) {
1251                 RTE_LOG(ERR, PMD,
1252                         "cannot get attribute for ena device rc= %d\n", rc);
1253                 goto err_admin_init;
1254         }
1255
1256         return 0;
1257
1258 err_admin_init:
1259         ena_com_admin_destroy(ena_dev);
1260
1261 err_mmio_read_less:
1262         ena_com_mmio_reg_read_request_destroy(ena_dev);
1263
1264         return rc;
1265 }
1266
1267 static int eth_ena_dev_init(struct rte_eth_dev *eth_dev)
1268 {
1269         struct rte_pci_device *pci_dev;
1270         struct ena_adapter *adapter =
1271                 (struct ena_adapter *)(eth_dev->data->dev_private);
1272         struct ena_com_dev *ena_dev = &adapter->ena_dev;
1273         struct ena_com_dev_get_features_ctx get_feat_ctx;
1274         int queue_size, rc;
1275
1276         static int adapters_found;
1277
1278         memset(adapter, 0, sizeof(struct ena_adapter));
1279         ena_dev = &adapter->ena_dev;
1280
1281         eth_dev->dev_ops = &ena_dev_ops;
1282         eth_dev->rx_pkt_burst = &eth_ena_recv_pkts;
1283         eth_dev->tx_pkt_burst = &eth_ena_xmit_pkts;
1284         eth_dev->tx_pkt_prepare = &eth_ena_prep_pkts;
1285         adapter->rte_eth_dev_data = eth_dev->data;
1286         adapter->rte_dev = eth_dev;
1287
1288         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1289                 return 0;
1290
1291         pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1292         adapter->pdev = pci_dev;
1293
1294         PMD_INIT_LOG(INFO, "Initializing %x:%x:%x.%d",
1295                      pci_dev->addr.domain,
1296                      pci_dev->addr.bus,
1297                      pci_dev->addr.devid,
1298                      pci_dev->addr.function);
1299
1300         adapter->regs = pci_dev->mem_resource[ENA_REGS_BAR].addr;
1301         adapter->dev_mem_base = pci_dev->mem_resource[ENA_MEM_BAR].addr;
1302
1303         /* Present ENA_MEM_BAR indicates available LLQ mode.
1304          * Use corresponding policy
1305          */
1306         if (adapter->dev_mem_base)
1307                 ena_dev->tx_mem_queue_type = ENA_ADMIN_PLACEMENT_POLICY_DEV;
1308         else if (adapter->regs)
1309                 ena_dev->tx_mem_queue_type = ENA_ADMIN_PLACEMENT_POLICY_HOST;
1310         else
1311                 PMD_INIT_LOG(CRIT, "Failed to access registers BAR(%d)",
1312                              ENA_REGS_BAR);
1313
1314         ena_dev->reg_bar = adapter->regs;
1315         ena_dev->dmadev = adapter->pdev;
1316
1317         adapter->id_number = adapters_found;
1318
1319         snprintf(adapter->name, ENA_NAME_MAX_LEN, "ena_%d",
1320                  adapter->id_number);
1321
1322         /* device specific initialization routine */
1323         rc = ena_device_init(ena_dev, &get_feat_ctx);
1324         if (rc) {
1325                 PMD_INIT_LOG(CRIT, "Failed to init ENA device");
1326                 return -1;
1327         }
1328
1329         if (ena_dev->tx_mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_DEV) {
1330                 if (get_feat_ctx.max_queues.max_llq_num == 0) {
1331                         PMD_INIT_LOG(ERR,
1332                                      "Trying to use LLQ but llq_num is 0.\n"
1333                                      "Fall back into regular queues.");
1334                         ena_dev->tx_mem_queue_type =
1335                                 ENA_ADMIN_PLACEMENT_POLICY_HOST;
1336                         adapter->num_queues =
1337                                 get_feat_ctx.max_queues.max_sq_num;
1338                 } else {
1339                         adapter->num_queues =
1340                                 get_feat_ctx.max_queues.max_llq_num;
1341                 }
1342         } else {
1343                 adapter->num_queues = get_feat_ctx.max_queues.max_sq_num;
1344         }
1345
1346         queue_size = ena_calc_queue_size(ena_dev, &get_feat_ctx);
1347         if ((queue_size <= 0) || (adapter->num_queues <= 0))
1348                 return -EFAULT;
1349
1350         adapter->tx_ring_size = queue_size;
1351         adapter->rx_ring_size = queue_size;
1352
1353         /* prepare ring structures */
1354         ena_init_rings(adapter);
1355
1356         ena_config_debug_area(adapter);
1357
1358         /* Set max MTU for this device */
1359         adapter->max_mtu = get_feat_ctx.dev_attr.max_mtu;
1360
1361         /* set device support for TSO */
1362         adapter->tso4_supported = get_feat_ctx.offload.tx &
1363                                   ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_IPV4_MASK;
1364
1365         /* Copy MAC address and point DPDK to it */
1366         eth_dev->data->mac_addrs = (struct ether_addr *)adapter->mac_addr;
1367         ether_addr_copy((struct ether_addr *)get_feat_ctx.dev_attr.mac_addr,
1368                         (struct ether_addr *)adapter->mac_addr);
1369
1370         adapter->drv_stats = rte_zmalloc("adapter stats",
1371                                          sizeof(*adapter->drv_stats),
1372                                          RTE_CACHE_LINE_SIZE);
1373         if (!adapter->drv_stats) {
1374                 RTE_LOG(ERR, PMD, "failed to alloc mem for adapter stats\n");
1375                 return -ENOMEM;
1376         }
1377
1378         adapters_found++;
1379         adapter->state = ENA_ADAPTER_STATE_INIT;
1380
1381         return 0;
1382 }
1383
1384 static int ena_dev_configure(struct rte_eth_dev *dev)
1385 {
1386         struct ena_adapter *adapter =
1387                 (struct ena_adapter *)(dev->data->dev_private);
1388
1389         if (!(adapter->state == ENA_ADAPTER_STATE_INIT ||
1390               adapter->state == ENA_ADAPTER_STATE_STOPPED)) {
1391                 PMD_INIT_LOG(ERR, "Illegal adapter state: %d",
1392                              adapter->state);
1393                 return -1;
1394         }
1395
1396         switch (adapter->state) {
1397         case ENA_ADAPTER_STATE_INIT:
1398         case ENA_ADAPTER_STATE_STOPPED:
1399                 adapter->state = ENA_ADAPTER_STATE_CONFIG;
1400                 break;
1401         case ENA_ADAPTER_STATE_CONFIG:
1402                 RTE_LOG(WARNING, PMD,
1403                         "Ivalid driver state while trying to configure device\n");
1404                 break;
1405         default:
1406                 break;
1407         }
1408
1409         return 0;
1410 }
1411
1412 static void ena_init_rings(struct ena_adapter *adapter)
1413 {
1414         int i;
1415
1416         for (i = 0; i < adapter->num_queues; i++) {
1417                 struct ena_ring *ring = &adapter->tx_ring[i];
1418
1419                 ring->configured = 0;
1420                 ring->type = ENA_RING_TYPE_TX;
1421                 ring->adapter = adapter;
1422                 ring->id = i;
1423                 ring->tx_mem_queue_type = adapter->ena_dev.tx_mem_queue_type;
1424                 ring->tx_max_header_size = adapter->ena_dev.tx_max_header_size;
1425         }
1426
1427         for (i = 0; i < adapter->num_queues; i++) {
1428                 struct ena_ring *ring = &adapter->rx_ring[i];
1429
1430                 ring->configured = 0;
1431                 ring->type = ENA_RING_TYPE_RX;
1432                 ring->adapter = adapter;
1433                 ring->id = i;
1434         }
1435 }
1436
1437 static void ena_infos_get(struct rte_eth_dev *dev,
1438                           struct rte_eth_dev_info *dev_info)
1439 {
1440         struct ena_adapter *adapter;
1441         struct ena_com_dev *ena_dev;
1442         struct ena_com_dev_get_features_ctx feat;
1443         uint32_t rx_feat = 0, tx_feat = 0;
1444         int rc = 0;
1445
1446         ena_assert_msg(dev->data != NULL, "Uninitialized device");
1447         ena_assert_msg(dev->data->dev_private != NULL, "Uninitialized device");
1448         adapter = (struct ena_adapter *)(dev->data->dev_private);
1449
1450         ena_dev = &adapter->ena_dev;
1451         ena_assert_msg(ena_dev != NULL, "Uninitialized device");
1452
1453         dev_info->pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1454
1455         dev_info->speed_capa =
1456                         ETH_LINK_SPEED_1G   |
1457                         ETH_LINK_SPEED_2_5G |
1458                         ETH_LINK_SPEED_5G   |
1459                         ETH_LINK_SPEED_10G  |
1460                         ETH_LINK_SPEED_25G  |
1461                         ETH_LINK_SPEED_40G  |
1462                         ETH_LINK_SPEED_50G  |
1463                         ETH_LINK_SPEED_100G;
1464
1465         /* Get supported features from HW */
1466         rc = ena_com_get_dev_attr_feat(ena_dev, &feat);
1467         if (unlikely(rc)) {
1468                 RTE_LOG(ERR, PMD,
1469                         "Cannot get attribute for ena device rc= %d\n", rc);
1470                 return;
1471         }
1472
1473         /* Set Tx & Rx features available for device */
1474         if (feat.offload.tx & ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_IPV4_MASK)
1475                 tx_feat |= DEV_TX_OFFLOAD_TCP_TSO;
1476
1477         if (feat.offload.tx &
1478             ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV4_CSUM_PART_MASK)
1479                 tx_feat |= DEV_TX_OFFLOAD_IPV4_CKSUM |
1480                         DEV_TX_OFFLOAD_UDP_CKSUM |
1481                         DEV_TX_OFFLOAD_TCP_CKSUM;
1482
1483         if (feat.offload.rx_supported &
1484             ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L4_IPV4_CSUM_MASK)
1485                 rx_feat |= DEV_RX_OFFLOAD_IPV4_CKSUM |
1486                         DEV_RX_OFFLOAD_UDP_CKSUM  |
1487                         DEV_RX_OFFLOAD_TCP_CKSUM;
1488
1489         /* Inform framework about available features */
1490         dev_info->rx_offload_capa = rx_feat;
1491         dev_info->tx_offload_capa = tx_feat;
1492
1493         dev_info->min_rx_bufsize = ENA_MIN_FRAME_LEN;
1494         dev_info->max_rx_pktlen  = adapter->max_mtu;
1495         dev_info->max_mac_addrs = 1;
1496
1497         dev_info->max_rx_queues = adapter->num_queues;
1498         dev_info->max_tx_queues = adapter->num_queues;
1499         dev_info->reta_size = ENA_RX_RSS_TABLE_SIZE;
1500 }
1501
1502 static uint16_t eth_ena_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,
1503                                   uint16_t nb_pkts)
1504 {
1505         struct ena_ring *rx_ring = (struct ena_ring *)(rx_queue);
1506         unsigned int ring_size = rx_ring->ring_size;
1507         unsigned int ring_mask = ring_size - 1;
1508         uint16_t next_to_clean = rx_ring->next_to_clean;
1509         uint16_t desc_in_use = 0;
1510         unsigned int recv_idx = 0;
1511         struct rte_mbuf *mbuf = NULL;
1512         struct rte_mbuf *mbuf_head = NULL;
1513         struct rte_mbuf *mbuf_prev = NULL;
1514         struct rte_mbuf **rx_buff_info = rx_ring->rx_buffer_info;
1515         unsigned int completed;
1516
1517         struct ena_com_rx_ctx ena_rx_ctx;
1518         int rc = 0;
1519
1520         /* Check adapter state */
1521         if (unlikely(rx_ring->adapter->state != ENA_ADAPTER_STATE_RUNNING)) {
1522                 RTE_LOG(ALERT, PMD,
1523                         "Trying to receive pkts while device is NOT running\n");
1524                 return 0;
1525         }
1526
1527         desc_in_use = rx_ring->next_to_use - next_to_clean;
1528         if (unlikely(nb_pkts > desc_in_use))
1529                 nb_pkts = desc_in_use;
1530
1531         for (completed = 0; completed < nb_pkts; completed++) {
1532                 int segments = 0;
1533
1534                 ena_rx_ctx.max_bufs = rx_ring->ring_size;
1535                 ena_rx_ctx.ena_bufs = rx_ring->ena_bufs;
1536                 ena_rx_ctx.descs = 0;
1537                 /* receive packet context */
1538                 rc = ena_com_rx_pkt(rx_ring->ena_com_io_cq,
1539                                     rx_ring->ena_com_io_sq,
1540                                     &ena_rx_ctx);
1541                 if (unlikely(rc)) {
1542                         RTE_LOG(ERR, PMD, "ena_com_rx_pkt error %d\n", rc);
1543                         return 0;
1544                 }
1545
1546                 if (unlikely(ena_rx_ctx.descs == 0))
1547                         break;
1548
1549                 while (segments < ena_rx_ctx.descs) {
1550                         mbuf = rx_buff_info[next_to_clean & ring_mask];
1551                         mbuf->data_len = ena_rx_ctx.ena_bufs[segments].len;
1552                         mbuf->data_off = RTE_PKTMBUF_HEADROOM;
1553                         mbuf->refcnt = 1;
1554                         mbuf->next = NULL;
1555                         if (segments == 0) {
1556                                 mbuf->nb_segs = ena_rx_ctx.descs;
1557                                 mbuf->port = rx_ring->port_id;
1558                                 mbuf->pkt_len = 0;
1559                                 mbuf_head = mbuf;
1560                         } else {
1561                                 /* for multi-segment pkts create mbuf chain */
1562                                 mbuf_prev->next = mbuf;
1563                         }
1564                         mbuf_head->pkt_len += mbuf->data_len;
1565
1566                         mbuf_prev = mbuf;
1567                         segments++;
1568                         next_to_clean++;
1569                 }
1570
1571                 /* fill mbuf attributes if any */
1572                 ena_rx_mbuf_prepare(mbuf_head, &ena_rx_ctx);
1573                 mbuf_head->hash.rss = (uint32_t)rx_ring->id;
1574
1575                 /* pass to DPDK application head mbuf */
1576                 rx_pkts[recv_idx] = mbuf_head;
1577                 recv_idx++;
1578         }
1579
1580         rx_ring->next_to_clean = next_to_clean;
1581
1582         desc_in_use = desc_in_use - completed + 1;
1583         /* Burst refill to save doorbells, memory barriers, const interval */
1584         if (ring_size - desc_in_use > ENA_RING_DESCS_RATIO(ring_size))
1585                 ena_populate_rx_queue(rx_ring, ring_size - desc_in_use);
1586
1587         return recv_idx;
1588 }
1589
1590 static uint16_t
1591 eth_ena_prep_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
1592                 uint16_t nb_pkts)
1593 {
1594         int32_t ret;
1595         uint32_t i;
1596         struct rte_mbuf *m;
1597         struct ena_ring *tx_ring = (struct ena_ring *)(tx_queue);
1598         struct ipv4_hdr *ip_hdr;
1599         uint64_t ol_flags;
1600         uint16_t frag_field;
1601
1602         for (i = 0; i != nb_pkts; i++) {
1603                 m = tx_pkts[i];
1604                 ol_flags = m->ol_flags;
1605
1606                 if (!(ol_flags & PKT_TX_IPV4))
1607                         continue;
1608
1609                 /* If there was not L2 header length specified, assume it is
1610                  * length of the ethernet header.
1611                  */
1612                 if (unlikely(m->l2_len == 0))
1613                         m->l2_len = sizeof(struct ether_hdr);
1614
1615                 ip_hdr = rte_pktmbuf_mtod_offset(m, struct ipv4_hdr *,
1616                                                  m->l2_len);
1617                 frag_field = rte_be_to_cpu_16(ip_hdr->fragment_offset);
1618
1619                 if ((frag_field & IPV4_HDR_DF_FLAG) != 0) {
1620                         m->packet_type |= RTE_PTYPE_L4_NONFRAG;
1621
1622                         /* If IPv4 header has DF flag enabled and TSO support is
1623                          * disabled, partial chcecksum should not be calculated.
1624                          */
1625                         if (!tx_ring->adapter->tso4_supported)
1626                                 continue;
1627                 }
1628
1629                 if ((ol_flags & ENA_TX_OFFLOAD_NOTSUP_MASK) != 0 ||
1630                                 (ol_flags & PKT_TX_L4_MASK) ==
1631                                 PKT_TX_SCTP_CKSUM) {
1632                         rte_errno = -ENOTSUP;
1633                         return i;
1634                 }
1635
1636 #ifdef RTE_LIBRTE_ETHDEV_DEBUG
1637                 ret = rte_validate_tx_offload(m);
1638                 if (ret != 0) {
1639                         rte_errno = ret;
1640                         return i;
1641                 }
1642 #endif
1643
1644                 /* In case we are supposed to TSO and have DF not set (DF=0)
1645                  * hardware must be provided with partial checksum, otherwise
1646                  * it will take care of necessary calculations.
1647                  */
1648
1649                 ret = rte_net_intel_cksum_flags_prepare(m,
1650                         ol_flags & ~PKT_TX_TCP_SEG);
1651                 if (ret != 0) {
1652                         rte_errno = ret;
1653                         return i;
1654                 }
1655         }
1656
1657         return i;
1658 }
1659
1660 static uint16_t eth_ena_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
1661                                   uint16_t nb_pkts)
1662 {
1663         struct ena_ring *tx_ring = (struct ena_ring *)(tx_queue);
1664         uint16_t next_to_use = tx_ring->next_to_use;
1665         uint16_t next_to_clean = tx_ring->next_to_clean;
1666         struct rte_mbuf *mbuf;
1667         unsigned int ring_size = tx_ring->ring_size;
1668         unsigned int ring_mask = ring_size - 1;
1669         struct ena_com_tx_ctx ena_tx_ctx;
1670         struct ena_tx_buffer *tx_info;
1671         struct ena_com_buf *ebuf;
1672         uint16_t rc, req_id, total_tx_descs = 0;
1673         uint16_t sent_idx = 0, empty_tx_reqs;
1674         int nb_hw_desc;
1675
1676         /* Check adapter state */
1677         if (unlikely(tx_ring->adapter->state != ENA_ADAPTER_STATE_RUNNING)) {
1678                 RTE_LOG(ALERT, PMD,
1679                         "Trying to xmit pkts while device is NOT running\n");
1680                 return 0;
1681         }
1682
1683         empty_tx_reqs = ring_size - (next_to_use - next_to_clean);
1684         if (nb_pkts > empty_tx_reqs)
1685                 nb_pkts = empty_tx_reqs;
1686
1687         for (sent_idx = 0; sent_idx < nb_pkts; sent_idx++) {
1688                 mbuf = tx_pkts[sent_idx];
1689
1690                 req_id = tx_ring->empty_tx_reqs[next_to_use & ring_mask];
1691                 tx_info = &tx_ring->tx_buffer_info[req_id];
1692                 tx_info->mbuf = mbuf;
1693                 tx_info->num_of_bufs = 0;
1694                 ebuf = tx_info->bufs;
1695
1696                 /* Prepare TX context */
1697                 memset(&ena_tx_ctx, 0x0, sizeof(struct ena_com_tx_ctx));
1698                 memset(&ena_tx_ctx.ena_meta, 0x0,
1699                        sizeof(struct ena_com_tx_meta));
1700                 ena_tx_ctx.ena_bufs = ebuf;
1701                 ena_tx_ctx.req_id = req_id;
1702                 if (tx_ring->tx_mem_queue_type ==
1703                                 ENA_ADMIN_PLACEMENT_POLICY_DEV) {
1704                         /* prepare the push buffer with
1705                          * virtual address of the data
1706                          */
1707                         ena_tx_ctx.header_len =
1708                                 RTE_MIN(mbuf->data_len,
1709                                         tx_ring->tx_max_header_size);
1710                         ena_tx_ctx.push_header =
1711                                 (void *)((char *)mbuf->buf_addr +
1712                                          mbuf->data_off);
1713                 } /* there's no else as we take advantage of memset zeroing */
1714
1715                 /* Set TX offloads flags, if applicable */
1716                 ena_tx_mbuf_prepare(mbuf, &ena_tx_ctx);
1717
1718                 if (unlikely(mbuf->ol_flags &
1719                              (PKT_RX_L4_CKSUM_BAD | PKT_RX_IP_CKSUM_BAD)))
1720                         rte_atomic64_inc(&tx_ring->adapter->drv_stats->ierrors);
1721
1722                 rte_prefetch0(tx_pkts[(sent_idx + 4) & ring_mask]);
1723
1724                 /* Process first segment taking into
1725                  * consideration pushed header
1726                  */
1727                 if (mbuf->data_len > ena_tx_ctx.header_len) {
1728                         ebuf->paddr = mbuf->buf_physaddr +
1729                                       mbuf->data_off +
1730                                       ena_tx_ctx.header_len;
1731                         ebuf->len = mbuf->data_len - ena_tx_ctx.header_len;
1732                         ebuf++;
1733                         tx_info->num_of_bufs++;
1734                 }
1735
1736                 while ((mbuf = mbuf->next) != NULL) {
1737                         ebuf->paddr = mbuf->buf_physaddr + mbuf->data_off;
1738                         ebuf->len = mbuf->data_len;
1739                         ebuf++;
1740                         tx_info->num_of_bufs++;
1741                 }
1742
1743                 ena_tx_ctx.num_bufs = tx_info->num_of_bufs;
1744
1745                 /* Write data to device */
1746                 rc = ena_com_prepare_tx(tx_ring->ena_com_io_sq,
1747                                         &ena_tx_ctx, &nb_hw_desc);
1748                 if (unlikely(rc))
1749                         break;
1750
1751                 tx_info->tx_descs = nb_hw_desc;
1752
1753                 next_to_use++;
1754         }
1755
1756         /* If there are ready packets to be xmitted... */
1757         if (sent_idx > 0) {
1758                 /* ...let HW do its best :-) */
1759                 rte_wmb();
1760                 ena_com_write_sq_doorbell(tx_ring->ena_com_io_sq);
1761
1762                 tx_ring->next_to_use = next_to_use;
1763         }
1764
1765         /* Clear complete packets  */
1766         while (ena_com_tx_comp_req_id_get(tx_ring->ena_com_io_cq, &req_id) >= 0) {
1767                 /* Get Tx info & store how many descs were processed  */
1768                 tx_info = &tx_ring->tx_buffer_info[req_id];
1769                 total_tx_descs += tx_info->tx_descs;
1770
1771                 /* Free whole mbuf chain  */
1772                 mbuf = tx_info->mbuf;
1773                 rte_pktmbuf_free(mbuf);
1774                 tx_info->mbuf = NULL;
1775
1776                 /* Put back descriptor to the ring for reuse */
1777                 tx_ring->empty_tx_reqs[next_to_clean & ring_mask] = req_id;
1778                 next_to_clean++;
1779
1780                 /* If too many descs to clean, leave it for another run */
1781                 if (unlikely(total_tx_descs > ENA_RING_DESCS_RATIO(ring_size)))
1782                         break;
1783         }
1784
1785         if (total_tx_descs > 0) {
1786                 /* acknowledge completion of sent packets */
1787                 ena_com_comp_ack(tx_ring->ena_com_io_sq, total_tx_descs);
1788                 tx_ring->next_to_clean = next_to_clean;
1789         }
1790
1791         return sent_idx;
1792 }
1793
1794 static int eth_ena_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
1795         struct rte_pci_device *pci_dev)
1796 {
1797         return rte_eth_dev_pci_generic_probe(pci_dev,
1798                 sizeof(struct ena_adapter), eth_ena_dev_init);
1799 }
1800
1801 static int eth_ena_pci_remove(struct rte_pci_device *pci_dev)
1802 {
1803         return rte_eth_dev_pci_generic_remove(pci_dev, NULL);
1804 }
1805
1806 static struct rte_pci_driver rte_ena_pmd = {
1807         .id_table = pci_id_ena_map,
1808         .drv_flags = RTE_PCI_DRV_NEED_MAPPING,
1809         .probe = eth_ena_pci_probe,
1810         .remove = eth_ena_pci_remove,
1811 };
1812
1813 RTE_PMD_REGISTER_PCI(net_ena, rte_ena_pmd);
1814 RTE_PMD_REGISTER_PCI_TABLE(net_ena, pci_id_ena_map);
1815 RTE_PMD_REGISTER_KMOD_DEP(net_ena, "* igb_uio | uio_pci_generic | vfio-pci");