drivers/net/ena/ena_ethdev.c

   1 /*-
   2 * BSD LICENSE
   3 *
   4 * Copyright (c) 2015-2016 Amazon.com, Inc. or its affiliates.
   5 * All rights reserved.
   6 *
   7 * Redistribution and use in source and binary forms, with or without
   8 * modification, are permitted provided that the following conditions
   9 * are met:
  10 *
  11 * * Redistributions of source code must retain the above copyright
  12 * notice, this list of conditions and the following disclaimer.
  13 * * Redistributions in binary form must reproduce the above copyright
  14 * notice, this list of conditions and the following disclaimer in
  15 * the documentation and/or other materials provided with the
  16 * distribution.
  17 * * Neither the name of copyright holder nor the names of its
  18 * contributors may be used to endorse or promote products derived
  19 * from this software without specific prior written permission.
  20 *
  21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32 */
  33
  34 #include <rte_ether.h>
  35 #include <rte_ethdev_driver.h>
  36 #include <rte_ethdev_pci.h>
  37 #include <rte_tcp.h>
  38 #include <rte_atomic.h>
  39 #include <rte_dev.h>
  40 #include <rte_errno.h>
  41 #include <rte_version.h>
  42 #include <rte_eal_memconfig.h>
  43 #include <rte_net.h>
  44
  45 #include "ena_ethdev.h"
  46 #include "ena_logs.h"
  47 #include "ena_platform.h"
  48 #include "ena_com.h"
  49 #include "ena_eth_com.h"
  50
  51 #include <ena_common_defs.h>
  52 #include <ena_regs_defs.h>
  53 #include <ena_admin_defs.h>
  54 #include <ena_eth_io_defs.h>
  55
  56 #define DRV_MODULE_VER_MAJOR    1
  57 #define DRV_MODULE_VER_MINOR    1
  58 #define DRV_MODULE_VER_SUBMINOR 1
  59
  60 #define ENA_IO_TXQ_IDX(q)       (2 * (q))
  61 #define ENA_IO_RXQ_IDX(q)       (2 * (q) + 1)
  62 /*reverse version of ENA_IO_RXQ_IDX*/
  63 #define ENA_IO_RXQ_IDX_REV(q)   ((q - 1) / 2)
  64
  65 /* While processing submitted and completed descriptors (rx and tx path
  66  * respectively) in a loop it is desired to:
  67  *  - perform batch submissions while populating sumbissmion queue
  68  *  - avoid blocking transmission of other packets during cleanup phase
  69  * Hence the utilization ratio of 1/8 of a queue size.
  70  */
  71 #define ENA_RING_DESCS_RATIO(ring_size) (ring_size / 8)
  72
  73 #define __MERGE_64B_H_L(h, l) (((uint64_t)h << 32) | l)
  74 #define TEST_BIT(val, bit_shift) (val & (1UL << bit_shift))
  75
  76 #define GET_L4_HDR_LEN(mbuf)                                    \
  77         ((rte_pktmbuf_mtod_offset(mbuf, struct tcp_hdr *,       \
  78                 mbuf->l3_len + mbuf->l2_len)->data_off) >> 4)
  79
  80 #define ENA_RX_RSS_TABLE_LOG_SIZE  7
  81 #define ENA_RX_RSS_TABLE_SIZE   (1 << ENA_RX_RSS_TABLE_LOG_SIZE)
  82 #define ENA_HASH_KEY_SIZE       40
  83 #define ENA_ETH_SS_STATS        0xFF
  84 #define ETH_GSTRING_LEN 32
  85
  86 #define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
  87
  88 #define ENA_MAX_RING_DESC       ENA_DEFAULT_RING_SIZE
  89 #define ENA_MIN_RING_DESC       128
  90
  91 enum ethtool_stringset {
  92         ETH_SS_TEST             = 0,
  93         ETH_SS_STATS,
  94 };
  95
  96 struct ena_stats {
  97         char name[ETH_GSTRING_LEN];
  98         int stat_offset;
  99 };
 100
 101 #define ENA_STAT_ENA_COM_ENTRY(stat) { \
 102         .name = #stat, \
 103         .stat_offset = offsetof(struct ena_com_stats_admin, stat) \
 104 }
 105
 106 #define ENA_STAT_ENTRY(stat, stat_type) { \
 107         .name = #stat, \
 108         .stat_offset = offsetof(struct ena_stats_##stat_type, stat) \
 109 }
 110
 111 #define ENA_STAT_RX_ENTRY(stat) \
 112         ENA_STAT_ENTRY(stat, rx)
 113
 114 #define ENA_STAT_TX_ENTRY(stat) \
 115         ENA_STAT_ENTRY(stat, tx)
 116
 117 #define ENA_STAT_GLOBAL_ENTRY(stat) \
 118         ENA_STAT_ENTRY(stat, dev)
 119
 120 /*
 121  * Each rte_memzone should have unique name.
 122  * To satisfy it, count number of allocation and add it to name.
 123  */
 124 uint32_t ena_alloc_cnt;
 125
 126 static const struct ena_stats ena_stats_global_strings[] = {
 127         ENA_STAT_GLOBAL_ENTRY(tx_timeout),
 128         ENA_STAT_GLOBAL_ENTRY(io_suspend),
 129         ENA_STAT_GLOBAL_ENTRY(io_resume),
 130         ENA_STAT_GLOBAL_ENTRY(wd_expired),
 131         ENA_STAT_GLOBAL_ENTRY(interface_up),
 132         ENA_STAT_GLOBAL_ENTRY(interface_down),
 133         ENA_STAT_GLOBAL_ENTRY(admin_q_pause),
 134 };
 135
 136 static const struct ena_stats ena_stats_tx_strings[] = {
 137         ENA_STAT_TX_ENTRY(cnt),
 138         ENA_STAT_TX_ENTRY(bytes),
 139         ENA_STAT_TX_ENTRY(queue_stop),
 140         ENA_STAT_TX_ENTRY(queue_wakeup),
 141         ENA_STAT_TX_ENTRY(dma_mapping_err),
 142         ENA_STAT_TX_ENTRY(linearize),
 143         ENA_STAT_TX_ENTRY(linearize_failed),
 144         ENA_STAT_TX_ENTRY(tx_poll),
 145         ENA_STAT_TX_ENTRY(doorbells),
 146         ENA_STAT_TX_ENTRY(prepare_ctx_err),
 147         ENA_STAT_TX_ENTRY(missing_tx_comp),
 148         ENA_STAT_TX_ENTRY(bad_req_id),
 149 };
 150
 151 static const struct ena_stats ena_stats_rx_strings[] = {
 152         ENA_STAT_RX_ENTRY(cnt),
 153         ENA_STAT_RX_ENTRY(bytes),
 154         ENA_STAT_RX_ENTRY(refil_partial),
 155         ENA_STAT_RX_ENTRY(bad_csum),
 156         ENA_STAT_RX_ENTRY(page_alloc_fail),
 157         ENA_STAT_RX_ENTRY(skb_alloc_fail),
 158         ENA_STAT_RX_ENTRY(dma_mapping_err),
 159         ENA_STAT_RX_ENTRY(bad_desc_num),
 160         ENA_STAT_RX_ENTRY(small_copy_len_pkt),
 161 };
 162
 163 static const struct ena_stats ena_stats_ena_com_strings[] = {
 164         ENA_STAT_ENA_COM_ENTRY(aborted_cmd),
 165         ENA_STAT_ENA_COM_ENTRY(submitted_cmd),
 166         ENA_STAT_ENA_COM_ENTRY(completed_cmd),
 167         ENA_STAT_ENA_COM_ENTRY(out_of_space),
 168         ENA_STAT_ENA_COM_ENTRY(no_completion),
 169 };
 170
 171 #define ENA_STATS_ARRAY_GLOBAL  ARRAY_SIZE(ena_stats_global_strings)
 172 #define ENA_STATS_ARRAY_TX      ARRAY_SIZE(ena_stats_tx_strings)
 173 #define ENA_STATS_ARRAY_RX      ARRAY_SIZE(ena_stats_rx_strings)
 174 #define ENA_STATS_ARRAY_ENA_COM ARRAY_SIZE(ena_stats_ena_com_strings)
 175
 176 #define QUEUE_OFFLOADS (DEV_TX_OFFLOAD_TCP_CKSUM |\
 177                         DEV_TX_OFFLOAD_UDP_CKSUM |\
 178                         DEV_TX_OFFLOAD_IPV4_CKSUM |\
 179                         DEV_TX_OFFLOAD_TCP_TSO)
 180 #define MBUF_OFFLOADS (PKT_TX_L4_MASK |\
 181                        PKT_TX_IP_CKSUM |\
 182                        PKT_TX_TCP_SEG)
 183
 184 /** Vendor ID used by Amazon devices */
 185 #define PCI_VENDOR_ID_AMAZON 0x1D0F
 186 /** Amazon devices */
 187 #define PCI_DEVICE_ID_ENA_VF    0xEC20
 188 #define PCI_DEVICE_ID_ENA_LLQ_VF        0xEC21
 189
 190 #define ENA_TX_OFFLOAD_MASK     (\
 191         PKT_TX_L4_MASK |         \
 192         PKT_TX_IP_CKSUM |        \
 193         PKT_TX_TCP_SEG)
 194
 195 #define ENA_TX_OFFLOAD_NOTSUP_MASK      \
 196         (PKT_TX_OFFLOAD_MASK ^ ENA_TX_OFFLOAD_MASK)
 197
 198 int ena_logtype_init;
 199 int ena_logtype_driver;
 200
 201 static const struct rte_pci_id pci_id_ena_map[] = {
 202         { RTE_PCI_DEVICE(PCI_VENDOR_ID_AMAZON, PCI_DEVICE_ID_ENA_VF) },
 203         { RTE_PCI_DEVICE(PCI_VENDOR_ID_AMAZON, PCI_DEVICE_ID_ENA_LLQ_VF) },
 204         { .device_id = 0 },
 205 };
 206
 207 static struct ena_aenq_handlers aenq_handlers;
 208
 209 static int ena_device_init(struct ena_com_dev *ena_dev,
 210                            struct ena_com_dev_get_features_ctx *get_feat_ctx,
 211                            bool *wd_state);
 212 static int ena_dev_configure(struct rte_eth_dev *dev);
 213 static uint16_t eth_ena_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
 214                                   uint16_t nb_pkts);
 215 static uint16_t eth_ena_prep_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
 216                 uint16_t nb_pkts);
 217 static int ena_tx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,
 218                               uint16_t nb_desc, unsigned int socket_id,
 219                               const struct rte_eth_txconf *tx_conf);
 220 static int ena_rx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,
 221                               uint16_t nb_desc, unsigned int socket_id,
 222                               const struct rte_eth_rxconf *rx_conf,
 223                               struct rte_mempool *mp);
 224 static uint16_t eth_ena_recv_pkts(void *rx_queue,
 225                                   struct rte_mbuf **rx_pkts, uint16_t nb_pkts);
 226 static int ena_populate_rx_queue(struct ena_ring *rxq, unsigned int count);
 227 static void ena_init_rings(struct ena_adapter *adapter);
 228 static int ena_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
 229 static int ena_start(struct rte_eth_dev *dev);
 230 static void ena_stop(struct rte_eth_dev *dev);
 231 static void ena_close(struct rte_eth_dev *dev);
 232 static int ena_dev_reset(struct rte_eth_dev *dev);
 233 static int ena_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats);
 234 static void ena_rx_queue_release_all(struct rte_eth_dev *dev);
 235 static void ena_tx_queue_release_all(struct rte_eth_dev *dev);
 236 static void ena_rx_queue_release(void *queue);
 237 static void ena_tx_queue_release(void *queue);
 238 static void ena_rx_queue_release_bufs(struct ena_ring *ring);
 239 static void ena_tx_queue_release_bufs(struct ena_ring *ring);
 240 static int ena_link_update(struct rte_eth_dev *dev,
 241                            int wait_to_complete);
 242 static int ena_create_io_queue(struct ena_ring *ring);
 243 static void ena_free_io_queues_all(struct ena_adapter *adapter);
 244 static int ena_queue_restart(struct ena_ring *ring);
 245 static int ena_queue_restart_all(struct rte_eth_dev *dev,
 246                                  enum ena_ring_type ring_type);
 247 static void ena_stats_restart(struct rte_eth_dev *dev);
 248 static void ena_infos_get(struct rte_eth_dev *dev,
 249                           struct rte_eth_dev_info *dev_info);
 250 static int ena_rss_reta_update(struct rte_eth_dev *dev,
 251                                struct rte_eth_rss_reta_entry64 *reta_conf,
 252                                uint16_t reta_size);
 253 static int ena_rss_reta_query(struct rte_eth_dev *dev,
 254                               struct rte_eth_rss_reta_entry64 *reta_conf,
 255                               uint16_t reta_size);
 256 static int ena_get_sset_count(struct rte_eth_dev *dev, int sset);
 257 static void ena_interrupt_handler_rte(void *cb_arg);
 258 static void ena_timer_wd_callback(struct rte_timer *timer, void *arg);
 259
 260 static const struct eth_dev_ops ena_dev_ops = {
 261         .dev_configure        = ena_dev_configure,
 262         .dev_infos_get        = ena_infos_get,
 263         .rx_queue_setup       = ena_rx_queue_setup,
 264         .tx_queue_setup       = ena_tx_queue_setup,
 265         .dev_start            = ena_start,
 266         .dev_stop             = ena_stop,
 267         .link_update          = ena_link_update,
 268         .stats_get            = ena_stats_get,
 269         .mtu_set              = ena_mtu_set,
 270         .rx_queue_release     = ena_rx_queue_release,
 271         .tx_queue_release     = ena_tx_queue_release,
 272         .dev_close            = ena_close,
 273         .dev_reset            = ena_dev_reset,
 274         .reta_update          = ena_rss_reta_update,
 275         .reta_query           = ena_rss_reta_query,
 276 };
 277
 278 #define NUMA_NO_NODE    SOCKET_ID_ANY
 279
 280 static inline int ena_cpu_to_node(int cpu)
 281 {
 282         struct rte_config *config = rte_eal_get_configuration();
 283         struct rte_fbarray *arr = &config->mem_config->memzones;
 284         const struct rte_memzone *mz;
 285
 286         if (unlikely(cpu >= RTE_MAX_MEMZONE))
 287                 return NUMA_NO_NODE;
 288
 289         mz = rte_fbarray_get(arr, cpu);
 290
 291         return mz->socket_id;
 292 }
 293
 294 static inline void ena_rx_mbuf_prepare(struct rte_mbuf *mbuf,
 295                                        struct ena_com_rx_ctx *ena_rx_ctx)
 296 {
 297         uint64_t ol_flags = 0;
 298         uint32_t packet_type = 0;
 299
 300         if (ena_rx_ctx->l4_proto == ENA_ETH_IO_L4_PROTO_TCP)
 301                 packet_type |= RTE_PTYPE_L4_TCP;
 302         else if (ena_rx_ctx->l4_proto == ENA_ETH_IO_L4_PROTO_UDP)
 303                 packet_type |= RTE_PTYPE_L4_UDP;
 304
 305         if (ena_rx_ctx->l3_proto == ENA_ETH_IO_L3_PROTO_IPV4)
 306                 packet_type |= RTE_PTYPE_L3_IPV4;
 307         else if (ena_rx_ctx->l3_proto == ENA_ETH_IO_L3_PROTO_IPV6)
 308                 packet_type |= RTE_PTYPE_L3_IPV6;
 309
 310         if (unlikely(ena_rx_ctx->l4_csum_err))
 311                 ol_flags |= PKT_RX_L4_CKSUM_BAD;
 312         if (unlikely(ena_rx_ctx->l3_csum_err))
 313                 ol_flags |= PKT_RX_IP_CKSUM_BAD;
 314
 315         mbuf->ol_flags = ol_flags;
 316         mbuf->packet_type = packet_type;
 317 }
 318
 319 static inline void ena_tx_mbuf_prepare(struct rte_mbuf *mbuf,
 320                                        struct ena_com_tx_ctx *ena_tx_ctx,
 321                                        uint64_t queue_offloads)
 322 {
 323         struct ena_com_tx_meta *ena_meta = &ena_tx_ctx->ena_meta;
 324
 325         if ((mbuf->ol_flags & MBUF_OFFLOADS) &&
 326             (queue_offloads & QUEUE_OFFLOADS)) {
 327                 /* check if TSO is required */
 328                 if ((mbuf->ol_flags & PKT_TX_TCP_SEG) &&
 329                     (queue_offloads & DEV_TX_OFFLOAD_TCP_TSO)) {
 330                         ena_tx_ctx->tso_enable = true;
 331
 332                         ena_meta->l4_hdr_len = GET_L4_HDR_LEN(mbuf);
 333                 }
 334
 335                 /* check if L3 checksum is needed */
 336                 if ((mbuf->ol_flags & PKT_TX_IP_CKSUM) &&
 337                     (queue_offloads & DEV_TX_OFFLOAD_IPV4_CKSUM))
 338                         ena_tx_ctx->l3_csum_enable = true;
 339
 340                 if (mbuf->ol_flags & PKT_TX_IPV6) {
 341                         ena_tx_ctx->l3_proto = ENA_ETH_IO_L3_PROTO_IPV6;
 342                 } else {
 343                         ena_tx_ctx->l3_proto = ENA_ETH_IO_L3_PROTO_IPV4;
 344
 345                         /* set don't fragment (DF) flag */
 346                         if (mbuf->packet_type &
 347                                 (RTE_PTYPE_L4_NONFRAG
 348                                  | RTE_PTYPE_INNER_L4_NONFRAG))
 349                                 ena_tx_ctx->df = true;
 350                 }
 351
 352                 /* check if L4 checksum is needed */
 353                 if ((mbuf->ol_flags & PKT_TX_TCP_CKSUM) &&
 354                     (queue_offloads & DEV_TX_OFFLOAD_TCP_CKSUM)) {
 355                         ena_tx_ctx->l4_proto = ENA_ETH_IO_L4_PROTO_TCP;
 356                         ena_tx_ctx->l4_csum_enable = true;
 357                 } else if ((mbuf->ol_flags & PKT_TX_UDP_CKSUM) &&
 358                            (queue_offloads & DEV_TX_OFFLOAD_UDP_CKSUM)) {
 359                         ena_tx_ctx->l4_proto = ENA_ETH_IO_L4_PROTO_UDP;
 360                         ena_tx_ctx->l4_csum_enable = true;
 361                 } else {
 362                         ena_tx_ctx->l4_proto = ENA_ETH_IO_L4_PROTO_UNKNOWN;
 363                         ena_tx_ctx->l4_csum_enable = false;
 364                 }
 365
 366                 ena_meta->mss = mbuf->tso_segsz;
 367                 ena_meta->l3_hdr_len = mbuf->l3_len;
 368                 ena_meta->l3_hdr_offset = mbuf->l2_len;
 369
 370                 ena_tx_ctx->meta_valid = true;
 371         } else {
 372                 ena_tx_ctx->meta_valid = false;
 373         }
 374 }
 375
 376 static inline int validate_rx_req_id(struct ena_ring *rx_ring, uint16_t req_id)
 377 {
 378         if (likely(req_id < rx_ring->ring_size))
 379                 return 0;
 380
 381         RTE_LOG(ERR, PMD, "Invalid rx req_id: %hu\n", req_id);
 382
 383         rx_ring->adapter->reset_reason = ENA_REGS_RESET_INV_RX_REQ_ID;
 384         rx_ring->adapter->trigger_reset = true;
 385
 386         return -EFAULT;
 387 }
 388
 389 static int validate_tx_req_id(struct ena_ring *tx_ring, u16 req_id)
 390 {
 391         struct ena_tx_buffer *tx_info = NULL;
 392
 393         if (likely(req_id < tx_ring->ring_size)) {
 394                 tx_info = &tx_ring->tx_buffer_info[req_id];
 395                 if (likely(tx_info->mbuf))
 396                         return 0;
 397         }
 398
 399         if (tx_info)
 400                 RTE_LOG(ERR, PMD, "tx_info doesn't have valid mbuf\n");
 401         else
 402                 RTE_LOG(ERR, PMD, "Invalid req_id: %hu\n", req_id);
 403
 404         /* Trigger device reset */
 405         tx_ring->adapter->reset_reason = ENA_REGS_RESET_INV_TX_REQ_ID;
 406         tx_ring->adapter->trigger_reset = true;
 407         return -EFAULT;
 408 }
 409
 410 static void ena_config_host_info(struct ena_com_dev *ena_dev)
 411 {
 412         struct ena_admin_host_info *host_info;
 413         int rc;
 414
 415         /* Allocate only the host info */
 416         rc = ena_com_allocate_host_info(ena_dev);
 417         if (rc) {
 418                 RTE_LOG(ERR, PMD, "Cannot allocate host info\n");
 419                 return;
 420         }
 421
 422         host_info = ena_dev->host_attr.host_info;
 423
 424         host_info->os_type = ENA_ADMIN_OS_DPDK;
 425         host_info->kernel_ver = RTE_VERSION;
 426         snprintf((char *)host_info->kernel_ver_str,
 427                  sizeof(host_info->kernel_ver_str),
 428                  "%s", rte_version());
 429         host_info->os_dist = RTE_VERSION;
 430         snprintf((char *)host_info->os_dist_str,
 431                  sizeof(host_info->os_dist_str),
 432                  "%s", rte_version());
 433         host_info->driver_version =
 434                 (DRV_MODULE_VER_MAJOR) |
 435                 (DRV_MODULE_VER_MINOR << ENA_ADMIN_HOST_INFO_MINOR_SHIFT) |
 436                 (DRV_MODULE_VER_SUBMINOR <<
 437                         ENA_ADMIN_HOST_INFO_SUB_MINOR_SHIFT);
 438
 439         rc = ena_com_set_host_attributes(ena_dev);
 440         if (rc) {
 441                 if (rc == -ENA_COM_UNSUPPORTED)
 442                         RTE_LOG(WARNING, PMD, "Cannot set host attributes\n");
 443                 else
 444                         RTE_LOG(ERR, PMD, "Cannot set host attributes\n");
 445
 446                 goto err;
 447         }
 448
 449         return;
 450
 451 err:
 452         ena_com_delete_host_info(ena_dev);
 453 }
 454
 455 static int
 456 ena_get_sset_count(struct rte_eth_dev *dev, int sset)
 457 {
 458         if (sset != ETH_SS_STATS)
 459                 return -EOPNOTSUPP;
 460
 461          /* Workaround for clang:
 462          * touch internal structures to prevent
 463          * compiler error
 464          */
 465         ENA_TOUCH(ena_stats_global_strings);
 466         ENA_TOUCH(ena_stats_tx_strings);
 467         ENA_TOUCH(ena_stats_rx_strings);
 468         ENA_TOUCH(ena_stats_ena_com_strings);
 469
 470         return  dev->data->nb_tx_queues *
 471                 (ENA_STATS_ARRAY_TX + ENA_STATS_ARRAY_RX) +
 472                 ENA_STATS_ARRAY_GLOBAL + ENA_STATS_ARRAY_ENA_COM;
 473 }
 474
 475 static void ena_config_debug_area(struct ena_adapter *adapter)
 476 {
 477         u32 debug_area_size;
 478         int rc, ss_count;
 479
 480         ss_count = ena_get_sset_count(adapter->rte_dev, ETH_SS_STATS);
 481         if (ss_count <= 0) {
 482                 RTE_LOG(ERR, PMD, "SS count is negative\n");
 483                 return;
 484         }
 485
 486         /* allocate 32 bytes for each string and 64bit for the value */
 487         debug_area_size = ss_count * ETH_GSTRING_LEN + sizeof(u64) * ss_count;
 488
 489         rc = ena_com_allocate_debug_area(&adapter->ena_dev, debug_area_size);
 490         if (rc) {
 491                 RTE_LOG(ERR, PMD, "Cannot allocate debug area\n");
 492                 return;
 493         }
 494
 495         rc = ena_com_set_host_attributes(&adapter->ena_dev);
 496         if (rc) {
 497                 if (rc == -ENA_COM_UNSUPPORTED)
 498                         RTE_LOG(WARNING, PMD, "Cannot set host attributes\n");
 499                 else
 500                         RTE_LOG(ERR, PMD, "Cannot set host attributes\n");
 501
 502                 goto err;
 503         }
 504
 505         return;
 506 err:
 507         ena_com_delete_debug_area(&adapter->ena_dev);
 508 }
 509
 510 static void ena_close(struct rte_eth_dev *dev)
 511 {
 512         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
 513         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
 514         struct ena_adapter *adapter =
 515                 (struct ena_adapter *)(dev->data->dev_private);
 516
 517         if (adapter->state == ENA_ADAPTER_STATE_RUNNING)
 518                 ena_stop(dev);
 519         adapter->state = ENA_ADAPTER_STATE_CLOSED;
 520
 521         ena_rx_queue_release_all(dev);
 522         ena_tx_queue_release_all(dev);
 523
 524         rte_free(adapter->drv_stats);
 525         adapter->drv_stats = NULL;
 526
 527         rte_intr_disable(intr_handle);
 528         rte_intr_callback_unregister(intr_handle,
 529                                      ena_interrupt_handler_rte,
 530                                      adapter);
 531
 532         /*
 533          * Pass the information to the rte_eth_dev_close() that it should also
 534          * release the private port resources.
 535          */
 536         dev->data->dev_flags |= RTE_ETH_DEV_CLOSE_REMOVE;
 537         /*
 538          * MAC is not allocated dynamically. Setting NULL should prevent from
 539          * release of the resource in the rte_eth_dev_release_port().
 540          */
 541         dev->data->mac_addrs = NULL;
 542 }
 543
 544 static int
 545 ena_dev_reset(struct rte_eth_dev *dev)
 546 {
 547         struct rte_mempool *mb_pool_rx[ENA_MAX_NUM_QUEUES];
 548         struct rte_eth_dev *eth_dev;
 549         struct rte_pci_device *pci_dev;
 550         struct rte_intr_handle *intr_handle;
 551         struct ena_com_dev *ena_dev;
 552         struct ena_com_dev_get_features_ctx get_feat_ctx;
 553         struct ena_adapter *adapter;
 554         int nb_queues;
 555         int rc, i;
 556         bool wd_state;
 557
 558         adapter = (struct ena_adapter *)(dev->data->dev_private);
 559         ena_dev = &adapter->ena_dev;
 560         eth_dev = adapter->rte_dev;
 561         pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
 562         intr_handle = &pci_dev->intr_handle;
 563         nb_queues = eth_dev->data->nb_rx_queues;
 564
 565         ena_com_set_admin_running_state(ena_dev, false);
 566
 567         rc = ena_com_dev_reset(ena_dev, adapter->reset_reason);
 568         if (rc)
 569                 RTE_LOG(ERR, PMD, "Device reset failed\n");
 570
 571         for (i = 0; i < nb_queues; i++)
 572                 mb_pool_rx[i] = adapter->rx_ring[i].mb_pool;
 573
 574         ena_rx_queue_release_all(eth_dev);
 575         ena_tx_queue_release_all(eth_dev);
 576
 577         rte_intr_disable(intr_handle);
 578
 579         ena_com_abort_admin_commands(ena_dev);
 580         ena_com_wait_for_abort_completion(ena_dev);
 581         ena_com_admin_destroy(ena_dev);
 582         ena_com_mmio_reg_read_request_destroy(ena_dev);
 583
 584         rc = ena_device_init(ena_dev, &get_feat_ctx, &wd_state);
 585         if (rc) {
 586                 PMD_INIT_LOG(CRIT, "Cannot initialize device\n");
 587                 return rc;
 588         }
 589         adapter->wd_state = wd_state;
 590
 591         rte_intr_enable(intr_handle);
 592         ena_com_set_admin_polling_mode(ena_dev, false);
 593         ena_com_admin_aenq_enable(ena_dev);
 594
 595         for (i = 0; i < nb_queues; ++i)
 596                 ena_rx_queue_setup(eth_dev, i, adapter->rx_ring_size, 0, NULL,
 597                         mb_pool_rx[i]);
 598
 599         for (i = 0; i < nb_queues; ++i)
 600                 ena_tx_queue_setup(eth_dev, i, adapter->tx_ring_size, 0, NULL);
 601
 602         adapter->trigger_reset = false;
 603
 604         return 0;
 605 }
 606
 607 static int ena_rss_reta_update(struct rte_eth_dev *dev,
 608                                struct rte_eth_rss_reta_entry64 *reta_conf,
 609                                uint16_t reta_size)
 610 {
 611         struct ena_adapter *adapter =
 612                 (struct ena_adapter *)(dev->data->dev_private);
 613         struct ena_com_dev *ena_dev = &adapter->ena_dev;
 614         int rc, i;
 615         u16 entry_value;
 616         int conf_idx;
 617         int idx;
 618
 619         if ((reta_size == 0) || (reta_conf == NULL))
 620                 return -EINVAL;
 621
 622         if (reta_size > ENA_RX_RSS_TABLE_SIZE) {
 623                 RTE_LOG(WARNING, PMD,
 624                         "indirection table %d is bigger than supported (%d)\n",
 625                         reta_size, ENA_RX_RSS_TABLE_SIZE);
 626                 return -EINVAL;
 627         }
 628
 629         for (i = 0 ; i < reta_size ; i++) {
 630                 /* each reta_conf is for 64 entries.
 631                  * to support 128 we use 2 conf of 64
 632                  */
 633                 conf_idx = i / RTE_RETA_GROUP_SIZE;
 634                 idx = i % RTE_RETA_GROUP_SIZE;
 635                 if (TEST_BIT(reta_conf[conf_idx].mask, idx)) {
 636                         entry_value =
 637                                 ENA_IO_RXQ_IDX(reta_conf[conf_idx].reta[idx]);
 638
 639                         rc = ena_com_indirect_table_fill_entry(ena_dev,
 640                                                                i,
 641                                                                entry_value);
 642                         if (unlikely(rc && rc != ENA_COM_UNSUPPORTED)) {
 643                                 RTE_LOG(ERR, PMD,
 644                                         "Cannot fill indirect table\n");
 645                                 return rc;
 646                         }
 647                 }
 648         }
 649
 650         rc = ena_com_indirect_table_set(ena_dev);
 651         if (unlikely(rc && rc != ENA_COM_UNSUPPORTED)) {
 652                 RTE_LOG(ERR, PMD, "Cannot flush the indirect table\n");
 653                 return rc;
 654         }
 655
 656         RTE_LOG(DEBUG, PMD, "%s(): RSS configured %d entries  for port %d\n",
 657                 __func__, reta_size, adapter->rte_dev->data->port_id);
 658
 659         return 0;
 660 }
 661
 662 /* Query redirection table. */
 663 static int ena_rss_reta_query(struct rte_eth_dev *dev,
 664                               struct rte_eth_rss_reta_entry64 *reta_conf,
 665                               uint16_t reta_size)
 666 {
 667         struct ena_adapter *adapter =
 668                 (struct ena_adapter *)(dev->data->dev_private);
 669         struct ena_com_dev *ena_dev = &adapter->ena_dev;
 670         int rc;
 671         int i;
 672         u32 indirect_table[ENA_RX_RSS_TABLE_SIZE] = {0};
 673         int reta_conf_idx;
 674         int reta_idx;
 675
 676         if (reta_size == 0 || reta_conf == NULL ||
 677             (reta_size > RTE_RETA_GROUP_SIZE && ((reta_conf + 1) == NULL)))
 678                 return -EINVAL;
 679
 680         rc = ena_com_indirect_table_get(ena_dev, indirect_table);
 681         if (unlikely(rc && rc != ENA_COM_UNSUPPORTED)) {
 682                 RTE_LOG(ERR, PMD, "cannot get indirect table\n");
 683                 return -ENOTSUP;
 684         }
 685
 686         for (i = 0 ; i < reta_size ; i++) {
 687                 reta_conf_idx = i / RTE_RETA_GROUP_SIZE;
 688                 reta_idx = i % RTE_RETA_GROUP_SIZE;
 689                 if (TEST_BIT(reta_conf[reta_conf_idx].mask, reta_idx))
 690                         reta_conf[reta_conf_idx].reta[reta_idx] =
 691                                 ENA_IO_RXQ_IDX_REV(indirect_table[i]);
 692         }
 693
 694         return 0;
 695 }
 696
 697 static int ena_rss_init_default(struct ena_adapter *adapter)
 698 {
 699         struct ena_com_dev *ena_dev = &adapter->ena_dev;
 700         uint16_t nb_rx_queues = adapter->rte_dev->data->nb_rx_queues;
 701         int rc, i;
 702         u32 val;
 703
 704         rc = ena_com_rss_init(ena_dev, ENA_RX_RSS_TABLE_LOG_SIZE);
 705         if (unlikely(rc)) {
 706                 RTE_LOG(ERR, PMD, "Cannot init indirect table\n");
 707                 goto err_rss_init;
 708         }
 709
 710         for (i = 0; i < ENA_RX_RSS_TABLE_SIZE; i++) {
 711                 val = i % nb_rx_queues;
 712                 rc = ena_com_indirect_table_fill_entry(ena_dev, i,
 713                                                        ENA_IO_RXQ_IDX(val));
 714                 if (unlikely(rc && (rc != ENA_COM_UNSUPPORTED))) {
 715                         RTE_LOG(ERR, PMD, "Cannot fill indirect table\n");
 716                         goto err_fill_indir;
 717                 }
 718         }
 719
 720         rc = ena_com_fill_hash_function(ena_dev, ENA_ADMIN_CRC32, NULL,
 721                                         ENA_HASH_KEY_SIZE, 0xFFFFFFFF);
 722         if (unlikely(rc && (rc != ENA_COM_UNSUPPORTED))) {
 723                 RTE_LOG(INFO, PMD, "Cannot fill hash function\n");
 724                 goto err_fill_indir;
 725         }
 726
 727         rc = ena_com_set_default_hash_ctrl(ena_dev);
 728         if (unlikely(rc && (rc != ENA_COM_UNSUPPORTED))) {
 729                 RTE_LOG(INFO, PMD, "Cannot fill hash control\n");
 730                 goto err_fill_indir;
 731         }
 732
 733         rc = ena_com_indirect_table_set(ena_dev);
 734         if (unlikely(rc && (rc != ENA_COM_UNSUPPORTED))) {
 735                 RTE_LOG(ERR, PMD, "Cannot flush the indirect table\n");
 736                 goto err_fill_indir;
 737         }
 738         RTE_LOG(DEBUG, PMD, "RSS configured for port %d\n",
 739                 adapter->rte_dev->data->port_id);
 740
 741         return 0;
 742
 743 err_fill_indir:
 744         ena_com_rss_destroy(ena_dev);
 745 err_rss_init:
 746
 747         return rc;
 748 }
 749
 750 static void ena_rx_queue_release_all(struct rte_eth_dev *dev)
 751 {
 752         struct ena_ring **queues = (struct ena_ring **)dev->data->rx_queues;
 753         int nb_queues = dev->data->nb_rx_queues;
 754         int i;
 755
 756         for (i = 0; i < nb_queues; i++)
 757                 ena_rx_queue_release(queues[i]);
 758 }
 759
 760 static void ena_tx_queue_release_all(struct rte_eth_dev *dev)
 761 {
 762         struct ena_ring **queues = (struct ena_ring **)dev->data->tx_queues;
 763         int nb_queues = dev->data->nb_tx_queues;
 764         int i;
 765
 766         for (i = 0; i < nb_queues; i++)
 767                 ena_tx_queue_release(queues[i]);
 768 }
 769
 770 static void ena_rx_queue_release(void *queue)
 771 {
 772         struct ena_ring *ring = (struct ena_ring *)queue;
 773
 774         ena_assert_msg(ring->configured,
 775                        "API violation - releasing not configured queue");
 776         ena_assert_msg(ring->adapter->state != ENA_ADAPTER_STATE_RUNNING,
 777                        "API violation");
 778
 779         /* Free ring resources */
 780         if (ring->rx_buffer_info)
 781                 rte_free(ring->rx_buffer_info);
 782         ring->rx_buffer_info = NULL;
 783
 784         if (ring->empty_rx_reqs)
 785                 rte_free(ring->empty_rx_reqs);
 786         ring->empty_rx_reqs = NULL;
 787
 788         ring->configured = 0;
 789
 790         RTE_LOG(NOTICE, PMD, "RX Queue %d:%d released\n",
 791                 ring->port_id, ring->id);
 792 }
 793
 794 static void ena_tx_queue_release(void *queue)
 795 {
 796         struct ena_ring *ring = (struct ena_ring *)queue;
 797
 798         ena_assert_msg(ring->configured,
 799                        "API violation. Releasing not configured queue");
 800         ena_assert_msg(ring->adapter->state != ENA_ADAPTER_STATE_RUNNING,
 801                        "API violation");
 802
 803         /* Free all bufs */
 804         ena_tx_queue_release_bufs(ring);
 805
 806         /* Free ring resources */
 807         if (ring->tx_buffer_info)
 808                 rte_free(ring->tx_buffer_info);
 809
 810         if (ring->empty_tx_reqs)
 811                 rte_free(ring->empty_tx_reqs);
 812
 813         ring->empty_tx_reqs = NULL;
 814         ring->tx_buffer_info = NULL;
 815
 816         ring->configured = 0;
 817
 818         RTE_LOG(NOTICE, PMD, "TX Queue %d:%d released\n",
 819                 ring->port_id, ring->id);
 820 }
 821
 822 static void ena_rx_queue_release_bufs(struct ena_ring *ring)
 823 {
 824         unsigned int ring_mask = ring->ring_size - 1;
 825
 826         while (ring->next_to_clean != ring->next_to_use) {
 827                 struct rte_mbuf *m =
 828                         ring->rx_buffer_info[ring->next_to_clean & ring_mask];
 829
 830                 if (m)
 831                         rte_mbuf_raw_free(m);
 832
 833                 ring->next_to_clean++;
 834         }
 835 }
 836
 837 static void ena_tx_queue_release_bufs(struct ena_ring *ring)
 838 {
 839         unsigned int i;
 840
 841         for (i = 0; i < ring->ring_size; ++i) {
 842                 struct ena_tx_buffer *tx_buf = &ring->tx_buffer_info[i];
 843
 844                 if (tx_buf->mbuf)
 845                         rte_pktmbuf_free(tx_buf->mbuf);
 846
 847                 ring->next_to_clean++;
 848         }
 849 }
 850
 851 static int ena_link_update(struct rte_eth_dev *dev,
 852                            __rte_unused int wait_to_complete)
 853 {
 854         struct rte_eth_link *link = &dev->data->dev_link;
 855         struct ena_adapter *adapter;
 856
 857         adapter = (struct ena_adapter *)(dev->data->dev_private);
 858
 859         link->link_status = adapter->link_status ? ETH_LINK_UP : ETH_LINK_DOWN;
 860         link->link_speed = ETH_SPEED_NUM_NONE;
 861         link->link_duplex = ETH_LINK_FULL_DUPLEX;
 862
 863         return 0;
 864 }
 865
 866 static int ena_queue_restart_all(struct rte_eth_dev *dev,
 867                                  enum ena_ring_type ring_type)
 868 {
 869         struct ena_adapter *adapter =
 870                 (struct ena_adapter *)(dev->data->dev_private);
 871         struct ena_ring *queues = NULL;
 872         int nb_queues;
 873         int i = 0;
 874         int rc = 0;
 875
 876         if (ring_type == ENA_RING_TYPE_RX) {
 877                 queues = adapter->rx_ring;
 878                 nb_queues = dev->data->nb_rx_queues;
 879         } else {
 880                 queues = adapter->tx_ring;
 881                 nb_queues = dev->data->nb_tx_queues;
 882         }
 883         for (i = 0; i < nb_queues; i++) {
 884                 if (queues[i].configured) {
 885                         if (ring_type == ENA_RING_TYPE_RX) {
 886                                 ena_assert_msg(
 887                                         dev->data->rx_queues[i] == &queues[i],
 888                                         "Inconsistent state of rx queues\n");
 889                         } else {
 890                                 ena_assert_msg(
 891                                         dev->data->tx_queues[i] == &queues[i],
 892                                         "Inconsistent state of tx queues\n");
 893                         }
 894
 895                         rc = ena_queue_restart(&queues[i]);
 896
 897                         if (rc) {
 898                                 PMD_INIT_LOG(ERR,
 899                                              "failed to restart queue %d type(%d)",
 900                                              i, ring_type);
 901                                 return rc;
 902                         }
 903                 }
 904         }
 905
 906         return 0;
 907 }
 908
 909 static uint32_t ena_get_mtu_conf(struct ena_adapter *adapter)
 910 {
 911         uint32_t max_frame_len = adapter->max_mtu;
 912
 913         if (adapter->rte_eth_dev_data->dev_conf.rxmode.offloads &
 914             DEV_RX_OFFLOAD_JUMBO_FRAME)
 915                 max_frame_len =
 916                         adapter->rte_eth_dev_data->dev_conf.rxmode.max_rx_pkt_len;
 917
 918         return max_frame_len;
 919 }
 920
 921 static int ena_check_valid_conf(struct ena_adapter *adapter)
 922 {
 923         uint32_t max_frame_len = ena_get_mtu_conf(adapter);
 924
 925         if (max_frame_len > adapter->max_mtu || max_frame_len < ENA_MIN_MTU) {
 926                 PMD_INIT_LOG(ERR, "Unsupported MTU of %d. "
 927                                   "max mtu: %d, min mtu: %d\n",
 928                              max_frame_len, adapter->max_mtu, ENA_MIN_MTU);
 929                 return ENA_COM_UNSUPPORTED;
 930         }
 931
 932         return 0;
 933 }
 934
 935 static int
 936 ena_calc_queue_size(struct ena_com_dev *ena_dev,
 937                     u16 *max_tx_sgl_size,
 938                     struct ena_com_dev_get_features_ctx *get_feat_ctx)
 939 {
 940         uint32_t queue_size = ENA_DEFAULT_RING_SIZE;
 941
 942         queue_size = RTE_MIN(queue_size,
 943                              get_feat_ctx->max_queues.max_cq_depth);
 944         queue_size = RTE_MIN(queue_size,
 945                              get_feat_ctx->max_queues.max_sq_depth);
 946
 947         if (ena_dev->tx_mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_DEV)
 948                 queue_size = RTE_MIN(queue_size,
 949                                      get_feat_ctx->max_queues.max_llq_depth);
 950
 951         /* Round down to power of 2 */
 952         if (!rte_is_power_of_2(queue_size))
 953                 queue_size = rte_align32pow2(queue_size >> 1);
 954
 955         if (unlikely(queue_size == 0)) {
 956                 PMD_INIT_LOG(ERR, "Invalid queue size");
 957                 return -EFAULT;
 958         }
 959
 960         *max_tx_sgl_size = RTE_MIN(ENA_PKT_MAX_BUFS,
 961                 get_feat_ctx->max_queues.max_packet_tx_descs);
 962
 963         return queue_size;
 964 }
 965
 966 static void ena_stats_restart(struct rte_eth_dev *dev)
 967 {
 968         struct ena_adapter *adapter =
 969                 (struct ena_adapter *)(dev->data->dev_private);
 970
 971         rte_atomic64_init(&adapter->drv_stats->ierrors);
 972         rte_atomic64_init(&adapter->drv_stats->oerrors);
 973         rte_atomic64_init(&adapter->drv_stats->rx_nombuf);
 974 }
 975
 976 static int ena_stats_get(struct rte_eth_dev *dev,
 977                           struct rte_eth_stats *stats)
 978 {
 979         struct ena_admin_basic_stats ena_stats;
 980         struct ena_adapter *adapter =
 981                 (struct ena_adapter *)(dev->data->dev_private);
 982         struct ena_com_dev *ena_dev = &adapter->ena_dev;
 983         int rc;
 984
 985         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
 986                 return -ENOTSUP;
 987
 988         memset(&ena_stats, 0, sizeof(ena_stats));
 989         rc = ena_com_get_dev_basic_stats(ena_dev, &ena_stats);
 990         if (unlikely(rc)) {
 991                 RTE_LOG(ERR, PMD, "Could not retrieve statistics from ENA");
 992                 return rc;
 993         }
 994
 995         /* Set of basic statistics from ENA */
 996         stats->ipackets = __MERGE_64B_H_L(ena_stats.rx_pkts_high,
 997                                           ena_stats.rx_pkts_low);
 998         stats->opackets = __MERGE_64B_H_L(ena_stats.tx_pkts_high,
 999                                           ena_stats.tx_pkts_low);
1000         stats->ibytes = __MERGE_64B_H_L(ena_stats.rx_bytes_high,
1001                                         ena_stats.rx_bytes_low);
1002         stats->obytes = __MERGE_64B_H_L(ena_stats.tx_bytes_high,
1003                                         ena_stats.tx_bytes_low);
1004         stats->imissed = __MERGE_64B_H_L(ena_stats.rx_drops_high,
1005                                          ena_stats.rx_drops_low);
1006
1007         /* Driver related stats */
1008         stats->ierrors = rte_atomic64_read(&adapter->drv_stats->ierrors);
1009         stats->oerrors = rte_atomic64_read(&adapter->drv_stats->oerrors);
1010         stats->rx_nombuf = rte_atomic64_read(&adapter->drv_stats->rx_nombuf);
1011         return 0;
1012 }
1013
1014 static int ena_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
1015 {
1016         struct ena_adapter *adapter;
1017         struct ena_com_dev *ena_dev;
1018         int rc = 0;
1019
1020         ena_assert_msg(dev->data != NULL, "Uninitialized device");
1021         ena_assert_msg(dev->data->dev_private != NULL, "Uninitialized device");
1022         adapter = (struct ena_adapter *)(dev->data->dev_private);
1023
1024         ena_dev = &adapter->ena_dev;
1025         ena_assert_msg(ena_dev != NULL, "Uninitialized device");
1026
1027         if (mtu > ena_get_mtu_conf(adapter) || mtu < ENA_MIN_MTU) {
1028                 RTE_LOG(ERR, PMD,
1029                         "Invalid MTU setting. new_mtu: %d "
1030                         "max mtu: %d min mtu: %d\n",
1031                         mtu, ena_get_mtu_conf(adapter), ENA_MIN_MTU);
1032                 return -EINVAL;
1033         }
1034
1035         rc = ena_com_set_dev_mtu(ena_dev, mtu);
1036         if (rc)
1037                 RTE_LOG(ERR, PMD, "Could not set MTU: %d\n", mtu);
1038         else
1039                 RTE_LOG(NOTICE, PMD, "Set MTU: %d\n", mtu);
1040
1041         return rc;
1042 }
1043
1044 static int ena_start(struct rte_eth_dev *dev)
1045 {
1046         struct ena_adapter *adapter =
1047                 (struct ena_adapter *)(dev->data->dev_private);
1048         uint64_t ticks;
1049         int rc = 0;
1050
1051         rc = ena_check_valid_conf(adapter);
1052         if (rc)
1053                 return rc;
1054
1055         rc = ena_queue_restart_all(dev, ENA_RING_TYPE_RX);
1056         if (rc)
1057                 return rc;
1058
1059         rc = ena_queue_restart_all(dev, ENA_RING_TYPE_TX);
1060         if (rc)
1061                 return rc;
1062
1063         if (adapter->rte_dev->data->dev_conf.rxmode.mq_mode &
1064             ETH_MQ_RX_RSS_FLAG && adapter->rte_dev->data->nb_rx_queues > 0) {
1065                 rc = ena_rss_init_default(adapter);
1066                 if (rc)
1067                         return rc;
1068         }
1069
1070         ena_stats_restart(dev);
1071
1072         adapter->timestamp_wd = rte_get_timer_cycles();
1073         adapter->keep_alive_timeout = ENA_DEVICE_KALIVE_TIMEOUT;
1074
1075         ticks = rte_get_timer_hz();
1076         rte_timer_reset(&adapter->timer_wd, ticks, PERIODICAL, rte_lcore_id(),
1077                         ena_timer_wd_callback, adapter);
1078
1079         adapter->state = ENA_ADAPTER_STATE_RUNNING;
1080
1081         return 0;
1082 }
1083
1084 static void ena_stop(struct rte_eth_dev *dev)
1085 {
1086         struct ena_adapter *adapter =
1087                 (struct ena_adapter *)(dev->data->dev_private);
1088
1089         rte_timer_stop_sync(&adapter->timer_wd);
1090         ena_free_io_queues_all(adapter);
1091
1092         adapter->state = ENA_ADAPTER_STATE_STOPPED;
1093 }
1094
1095 static int ena_create_io_queue(struct ena_ring *ring)
1096 {
1097         struct ena_adapter *adapter;
1098         struct ena_com_dev *ena_dev;
1099         struct ena_com_create_io_ctx ctx =
1100                 /* policy set to _HOST just to satisfy icc compiler */
1101                 { ENA_ADMIN_PLACEMENT_POLICY_HOST,
1102                   0, 0, 0, 0, 0 };
1103         uint16_t ena_qid;
1104         int rc;
1105
1106         adapter = ring->adapter;
1107         ena_dev = &adapter->ena_dev;
1108
1109         if (ring->type == ENA_RING_TYPE_TX) {
1110                 ena_qid = ENA_IO_TXQ_IDX(ring->id);
1111                 ctx.direction = ENA_COM_IO_QUEUE_DIRECTION_TX;
1112                 ctx.mem_queue_type = ena_dev->tx_mem_queue_type;
1113                 ctx.queue_size = adapter->tx_ring_size;
1114         } else {
1115                 ena_qid = ENA_IO_RXQ_IDX(ring->id);
1116                 ctx.direction = ENA_COM_IO_QUEUE_DIRECTION_RX;
1117                 ctx.queue_size = adapter->rx_ring_size;
1118         }
1119         ctx.qid = ena_qid;
1120         ctx.msix_vector = -1; /* interrupts not used */
1121         ctx.numa_node = ena_cpu_to_node(ring->id);
1122
1123         rc = ena_com_create_io_queue(ena_dev, &ctx);
1124         if (rc) {
1125                 RTE_LOG(ERR, PMD,
1126                         "failed to create io queue #%d (qid:%d) rc: %d\n",
1127                         ring->id, ena_qid, rc);
1128                 return rc;
1129         }
1130
1131         rc = ena_com_get_io_handlers(ena_dev, ena_qid,
1132                                      &ring->ena_com_io_sq,
1133                                      &ring->ena_com_io_cq);
1134         if (rc) {
1135                 RTE_LOG(ERR, PMD,
1136                         "Failed to get io queue handlers. queue num %d rc: %d\n",
1137                         ring->id, rc);
1138                 ena_com_destroy_io_queue(ena_dev, ena_qid);
1139                 return rc;
1140         }
1141
1142         if (ring->type == ENA_RING_TYPE_TX)
1143                 ena_com_update_numa_node(ring->ena_com_io_cq, ctx.numa_node);
1144
1145         return 0;
1146 }
1147
1148 static void ena_free_io_queues_all(struct ena_adapter *adapter)
1149 {
1150         struct rte_eth_dev *eth_dev = adapter->rte_dev;
1151         struct ena_com_dev *ena_dev = &adapter->ena_dev;
1152         int i;
1153         uint16_t ena_qid;
1154         uint16_t nb_rxq = eth_dev->data->nb_rx_queues;
1155         uint16_t nb_txq = eth_dev->data->nb_tx_queues;
1156
1157         for (i = 0; i < nb_txq; ++i) {
1158                 ena_qid = ENA_IO_TXQ_IDX(i);
1159                 ena_com_destroy_io_queue(ena_dev, ena_qid);
1160         }
1161
1162         for (i = 0; i < nb_rxq; ++i) {
1163                 ena_qid = ENA_IO_RXQ_IDX(i);
1164                 ena_com_destroy_io_queue(ena_dev, ena_qid);
1165
1166                 ena_rx_queue_release_bufs(&adapter->rx_ring[i]);
1167         }
1168 }
1169
1170 static int ena_queue_restart(struct ena_ring *ring)
1171 {
1172         int rc, bufs_num;
1173
1174         ena_assert_msg(ring->configured == 1,
1175                        "Trying to restart unconfigured queue\n");
1176
1177         rc = ena_create_io_queue(ring);
1178         if (rc) {
1179                 PMD_INIT_LOG(ERR, "Failed to create IO queue!\n");
1180                 return rc;
1181         }
1182
1183         ring->next_to_clean = 0;
1184         ring->next_to_use = 0;
1185
1186         if (ring->type == ENA_RING_TYPE_TX)
1187                 return 0;
1188
1189         bufs_num = ring->ring_size - 1;
1190         rc = ena_populate_rx_queue(ring, bufs_num);
1191         if (rc != bufs_num) {
1192                 PMD_INIT_LOG(ERR, "Failed to populate rx ring !");
1193                 return ENA_COM_FAULT;
1194         }
1195
1196         return 0;
1197 }
1198
1199 static int ena_tx_queue_setup(struct rte_eth_dev *dev,
1200                               uint16_t queue_idx,
1201                               uint16_t nb_desc,
1202                               __rte_unused unsigned int socket_id,
1203                               const struct rte_eth_txconf *tx_conf)
1204 {
1205         struct ena_ring *txq = NULL;
1206         struct ena_adapter *adapter =
1207                 (struct ena_adapter *)(dev->data->dev_private);
1208         unsigned int i;
1209
1210         txq = &adapter->tx_ring[queue_idx];
1211
1212         if (txq->configured) {
1213                 RTE_LOG(CRIT, PMD,
1214                         "API violation. Queue %d is already configured\n",
1215                         queue_idx);
1216                 return ENA_COM_FAULT;
1217         }
1218
1219         if (!rte_is_power_of_2(nb_desc)) {
1220                 RTE_LOG(ERR, PMD,
1221                         "Unsupported size of TX queue: %d is not a power of 2.",
1222                         nb_desc);
1223                 return -EINVAL;
1224         }
1225
1226         if (nb_desc > adapter->tx_ring_size) {
1227                 RTE_LOG(ERR, PMD,
1228                         "Unsupported size of TX queue (max size: %d)\n",
1229                         adapter->tx_ring_size);
1230                 return -EINVAL;
1231         }
1232
1233         txq->port_id = dev->data->port_id;
1234         txq->next_to_clean = 0;
1235         txq->next_to_use = 0;
1236         txq->ring_size = nb_desc;
1237
1238         txq->tx_buffer_info = rte_zmalloc("txq->tx_buffer_info",
1239                                           sizeof(struct ena_tx_buffer) *
1240                                           txq->ring_size,
1241                                           RTE_CACHE_LINE_SIZE);
1242         if (!txq->tx_buffer_info) {
1243                 RTE_LOG(ERR, PMD, "failed to alloc mem for tx buffer info\n");
1244                 return -ENOMEM;
1245         }
1246
1247         txq->empty_tx_reqs = rte_zmalloc("txq->empty_tx_reqs",
1248                                          sizeof(u16) * txq->ring_size,
1249                                          RTE_CACHE_LINE_SIZE);
1250         if (!txq->empty_tx_reqs) {
1251                 RTE_LOG(ERR, PMD, "failed to alloc mem for tx reqs\n");
1252                 rte_free(txq->tx_buffer_info);
1253                 return -ENOMEM;
1254         }
1255
1256         for (i = 0; i < txq->ring_size; i++)
1257                 txq->empty_tx_reqs[i] = i;
1258
1259         if (tx_conf != NULL) {
1260                 txq->offloads =
1261                         tx_conf->offloads | dev->data->dev_conf.txmode.offloads;
1262         }
1263
1264         /* Store pointer to this queue in upper layer */
1265         txq->configured = 1;
1266         dev->data->tx_queues[queue_idx] = txq;
1267
1268         return 0;
1269 }
1270
1271 static int ena_rx_queue_setup(struct rte_eth_dev *dev,
1272                               uint16_t queue_idx,
1273                               uint16_t nb_desc,
1274                               __rte_unused unsigned int socket_id,
1275                               __rte_unused const struct rte_eth_rxconf *rx_conf,
1276                               struct rte_mempool *mp)
1277 {
1278         struct ena_adapter *adapter =
1279                 (struct ena_adapter *)(dev->data->dev_private);
1280         struct ena_ring *rxq = NULL;
1281         int i;
1282
1283         rxq = &adapter->rx_ring[queue_idx];
1284         if (rxq->configured) {
1285                 RTE_LOG(CRIT, PMD,
1286                         "API violation. Queue %d is already configured\n",
1287                         queue_idx);
1288                 return ENA_COM_FAULT;
1289         }
1290
1291         if (!rte_is_power_of_2(nb_desc)) {
1292                 RTE_LOG(ERR, PMD,
1293                         "Unsupported size of RX queue: %d is not a power of 2.",
1294                         nb_desc);
1295                 return -EINVAL;
1296         }
1297
1298         if (nb_desc > adapter->rx_ring_size) {
1299                 RTE_LOG(ERR, PMD,
1300                         "Unsupported size of RX queue (max size: %d)\n",
1301                         adapter->rx_ring_size);
1302                 return -EINVAL;
1303         }
1304
1305         rxq->port_id = dev->data->port_id;
1306         rxq->next_to_clean = 0;
1307         rxq->next_to_use = 0;
1308         rxq->ring_size = nb_desc;
1309         rxq->mb_pool = mp;
1310
1311         rxq->rx_buffer_info = rte_zmalloc("rxq->buffer_info",
1312                                           sizeof(struct rte_mbuf *) * nb_desc,
1313                                           RTE_CACHE_LINE_SIZE);
1314         if (!rxq->rx_buffer_info) {
1315                 RTE_LOG(ERR, PMD, "failed to alloc mem for rx buffer info\n");
1316                 return -ENOMEM;
1317         }
1318
1319         rxq->empty_rx_reqs = rte_zmalloc("rxq->empty_rx_reqs",
1320                                          sizeof(uint16_t) * nb_desc,
1321                                          RTE_CACHE_LINE_SIZE);
1322         if (!rxq->empty_rx_reqs) {
1323                 RTE_LOG(ERR, PMD, "failed to alloc mem for empty rx reqs\n");
1324                 rte_free(rxq->rx_buffer_info);
1325                 rxq->rx_buffer_info = NULL;
1326                 return -ENOMEM;
1327         }
1328
1329         for (i = 0; i < nb_desc; i++)
1330                 rxq->empty_tx_reqs[i] = i;
1331
1332         /* Store pointer to this queue in upper layer */
1333         rxq->configured = 1;
1334         dev->data->rx_queues[queue_idx] = rxq;
1335
1336         return 0;
1337 }
1338
1339 static int ena_populate_rx_queue(struct ena_ring *rxq, unsigned int count)
1340 {
1341         unsigned int i;
1342         int rc;
1343         uint16_t ring_size = rxq->ring_size;
1344         uint16_t ring_mask = ring_size - 1;
1345         uint16_t next_to_use = rxq->next_to_use;
1346         uint16_t in_use, req_id;
1347         struct rte_mbuf **mbufs = &rxq->rx_buffer_info[0];
1348
1349         if (unlikely(!count))
1350                 return 0;
1351
1352         in_use = rxq->next_to_use - rxq->next_to_clean;
1353         ena_assert_msg(((in_use + count) < ring_size), "bad ring state");
1354
1355         count = RTE_MIN(count,
1356                         (uint16_t)(ring_size - (next_to_use & ring_mask)));
1357
1358         /* get resources for incoming packets */
1359         rc = rte_mempool_get_bulk(rxq->mb_pool,
1360                                   (void **)(&mbufs[next_to_use & ring_mask]),
1361                                   count);
1362         if (unlikely(rc < 0)) {
1363                 rte_atomic64_inc(&rxq->adapter->drv_stats->rx_nombuf);
1364                 PMD_RX_LOG(DEBUG, "there are no enough free buffers");
1365                 return 0;
1366         }
1367
1368         for (i = 0; i < count; i++) {
1369                 uint16_t next_to_use_masked = next_to_use & ring_mask;
1370                 struct rte_mbuf *mbuf = mbufs[next_to_use_masked];
1371                 struct ena_com_buf ebuf;
1372
1373                 rte_prefetch0(mbufs[((next_to_use + 4) & ring_mask)]);
1374
1375                 req_id = rxq->empty_rx_reqs[next_to_use_masked];
1376                 rc = validate_rx_req_id(rxq, req_id);
1377                 if (unlikely(rc < 0))
1378                         break;
1379
1380                 /* prepare physical address for DMA transaction */
1381                 ebuf.paddr = mbuf->buf_iova + RTE_PKTMBUF_HEADROOM;
1382                 ebuf.len = mbuf->buf_len - RTE_PKTMBUF_HEADROOM;
1383                 /* pass resource to device */
1384                 rc = ena_com_add_single_rx_desc(rxq->ena_com_io_sq,
1385                                                 &ebuf, req_id);
1386                 if (unlikely(rc)) {
1387                         rte_mempool_put_bulk(rxq->mb_pool, (void **)(&mbuf),
1388                                              count - i);
1389                         RTE_LOG(WARNING, PMD, "failed adding rx desc\n");
1390                         break;
1391                 }
1392                 next_to_use++;
1393         }
1394
1395         if (unlikely(i < count))
1396                 RTE_LOG(WARNING, PMD, "refilled rx qid %d with only %d "
1397                         "buffers (from %d)\n", rxq->id, i, count);
1398
1399         /* When we submitted free recources to device... */
1400         if (likely(i > 0)) {
1401                 /* ...let HW know that it can fill buffers with data
1402                  *
1403                  * Add memory barrier to make sure the desc were written before
1404                  * issue a doorbell
1405                  */
1406                 rte_wmb();
1407                 ena_com_write_sq_doorbell(rxq->ena_com_io_sq);
1408
1409                 rxq->next_to_use = next_to_use;
1410         }
1411
1412         return i;
1413 }
1414
1415 static int ena_device_init(struct ena_com_dev *ena_dev,
1416                            struct ena_com_dev_get_features_ctx *get_feat_ctx,
1417                            bool *wd_state)
1418 {
1419         uint32_t aenq_groups;
1420         int rc;
1421         bool readless_supported;
1422
1423         /* Initialize mmio registers */
1424         rc = ena_com_mmio_reg_read_request_init(ena_dev);
1425         if (rc) {
1426                 RTE_LOG(ERR, PMD, "failed to init mmio read less\n");
1427                 return rc;
1428         }
1429
1430         /* The PCIe configuration space revision id indicate if mmio reg
1431          * read is disabled.
1432          */
1433         readless_supported =
1434                 !(((struct rte_pci_device *)ena_dev->dmadev)->id.class_id
1435                                & ENA_MMIO_DISABLE_REG_READ);
1436         ena_com_set_mmio_read_mode(ena_dev, readless_supported);
1437
1438         /* reset device */
1439         rc = ena_com_dev_reset(ena_dev, ENA_REGS_RESET_NORMAL);
1440         if (rc) {
1441                 RTE_LOG(ERR, PMD, "cannot reset device\n");
1442                 goto err_mmio_read_less;
1443         }
1444
1445         /* check FW version */
1446         rc = ena_com_validate_version(ena_dev);
1447         if (rc) {
1448                 RTE_LOG(ERR, PMD, "device version is too low\n");
1449                 goto err_mmio_read_less;
1450         }
1451
1452         ena_dev->dma_addr_bits = ena_com_get_dma_width(ena_dev);
1453
1454         /* ENA device administration layer init */
1455         rc = ena_com_admin_init(ena_dev, &aenq_handlers, true);
1456         if (rc) {
1457                 RTE_LOG(ERR, PMD,
1458                         "cannot initialize ena admin queue with device\n");
1459                 goto err_mmio_read_less;
1460         }
1461
1462         /* To enable the msix interrupts the driver needs to know the number
1463          * of queues. So the driver uses polling mode to retrieve this
1464          * information.
1465          */
1466         ena_com_set_admin_polling_mode(ena_dev, true);
1467
1468         ena_config_host_info(ena_dev);
1469
1470         /* Get Device Attributes and features */
1471         rc = ena_com_get_dev_attr_feat(ena_dev, get_feat_ctx);
1472         if (rc) {
1473                 RTE_LOG(ERR, PMD,
1474                         "cannot get attribute for ena device rc= %d\n", rc);
1475                 goto err_admin_init;
1476         }
1477
1478         aenq_groups = BIT(ENA_ADMIN_LINK_CHANGE) |
1479                       BIT(ENA_ADMIN_NOTIFICATION) |
1480                       BIT(ENA_ADMIN_KEEP_ALIVE) |
1481                       BIT(ENA_ADMIN_FATAL_ERROR) |
1482                       BIT(ENA_ADMIN_WARNING);
1483
1484         aenq_groups &= get_feat_ctx->aenq.supported_groups;
1485         rc = ena_com_set_aenq_config(ena_dev, aenq_groups);
1486         if (rc) {
1487                 RTE_LOG(ERR, PMD, "Cannot configure aenq groups rc: %d\n", rc);
1488                 goto err_admin_init;
1489         }
1490
1491         *wd_state = !!(aenq_groups & BIT(ENA_ADMIN_KEEP_ALIVE));
1492
1493         return 0;
1494
1495 err_admin_init:
1496         ena_com_admin_destroy(ena_dev);
1497
1498 err_mmio_read_less:
1499         ena_com_mmio_reg_read_request_destroy(ena_dev);
1500
1501         return rc;
1502 }
1503
1504 static void ena_interrupt_handler_rte(void *cb_arg)
1505 {
1506         struct ena_adapter *adapter = (struct ena_adapter *)cb_arg;
1507         struct ena_com_dev *ena_dev = &adapter->ena_dev;
1508
1509         ena_com_admin_q_comp_intr_handler(ena_dev);
1510         if (likely(adapter->state != ENA_ADAPTER_STATE_CLOSED))
1511                 ena_com_aenq_intr_handler(ena_dev, adapter);
1512 }
1513
1514 static void check_for_missing_keep_alive(struct ena_adapter *adapter)
1515 {
1516         if (!adapter->wd_state)
1517                 return;
1518
1519         if (adapter->keep_alive_timeout == ENA_HW_HINTS_NO_TIMEOUT)
1520                 return;
1521
1522         if (unlikely((rte_get_timer_cycles() - adapter->timestamp_wd) >=
1523             adapter->keep_alive_timeout)) {
1524                 RTE_LOG(ERR, PMD, "Keep alive timeout\n");
1525                 adapter->reset_reason = ENA_REGS_RESET_KEEP_ALIVE_TO;
1526                 adapter->trigger_reset = true;
1527         }
1528 }
1529
1530 /* Check if admin queue is enabled */
1531 static void check_for_admin_com_state(struct ena_adapter *adapter)
1532 {
1533         if (unlikely(!ena_com_get_admin_running_state(&adapter->ena_dev))) {
1534                 RTE_LOG(ERR, PMD, "ENA admin queue is not in running state!\n");
1535                 adapter->reset_reason = ENA_REGS_RESET_ADMIN_TO;
1536                 adapter->trigger_reset = true;
1537         }
1538 }
1539
1540 static void ena_timer_wd_callback(__rte_unused struct rte_timer *timer,
1541                                   void *arg)
1542 {
1543         struct ena_adapter *adapter = (struct ena_adapter *)arg;
1544         struct rte_eth_dev *dev = adapter->rte_dev;
1545
1546         check_for_missing_keep_alive(adapter);
1547         check_for_admin_com_state(adapter);
1548
1549         if (unlikely(adapter->trigger_reset)) {
1550                 RTE_LOG(ERR, PMD, "Trigger reset is on\n");
1551                 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_RESET,
1552                         NULL);
1553         }
1554 }
1555
1556 static int ena_calc_io_queue_num(__rte_unused struct ena_com_dev *ena_dev,
1557                                  struct ena_com_dev_get_features_ctx *get_feat_ctx)
1558 {
1559         int io_sq_num, io_cq_num, io_queue_num;
1560
1561         io_sq_num = get_feat_ctx->max_queues.max_sq_num;
1562         io_cq_num = get_feat_ctx->max_queues.max_cq_num;
1563
1564         io_queue_num = RTE_MIN(io_sq_num, io_cq_num);
1565
1566         if (unlikely(io_queue_num == 0)) {
1567                 RTE_LOG(ERR, PMD, "Number of IO queues should not be 0\n");
1568                 return -EFAULT;
1569         }
1570
1571         return io_queue_num;
1572 }
1573
1574 static int eth_ena_dev_init(struct rte_eth_dev *eth_dev)
1575 {
1576         struct rte_pci_device *pci_dev;
1577         struct rte_intr_handle *intr_handle;
1578         struct ena_adapter *adapter =
1579                 (struct ena_adapter *)(eth_dev->data->dev_private);
1580         struct ena_com_dev *ena_dev = &adapter->ena_dev;
1581         struct ena_com_dev_get_features_ctx get_feat_ctx;
1582         int queue_size, rc;
1583         u16 tx_sgl_size = 0;
1584
1585         static int adapters_found;
1586         bool wd_state;
1587
1588         memset(adapter, 0, sizeof(struct ena_adapter));
1589         ena_dev = &adapter->ena_dev;
1590
1591         eth_dev->dev_ops = &ena_dev_ops;
1592         eth_dev->rx_pkt_burst = &eth_ena_recv_pkts;
1593         eth_dev->tx_pkt_burst = &eth_ena_xmit_pkts;
1594         eth_dev->tx_pkt_prepare = &eth_ena_prep_pkts;
1595         adapter->rte_eth_dev_data = eth_dev->data;
1596         adapter->rte_dev = eth_dev;
1597
1598         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1599                 return 0;
1600
1601         pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1602         adapter->pdev = pci_dev;
1603
1604         PMD_INIT_LOG(INFO, "Initializing %x:%x:%x.%d",
1605                      pci_dev->addr.domain,
1606                      pci_dev->addr.bus,
1607                      pci_dev->addr.devid,
1608                      pci_dev->addr.function);
1609
1610         intr_handle = &pci_dev->intr_handle;
1611
1612         adapter->regs = pci_dev->mem_resource[ENA_REGS_BAR].addr;
1613         adapter->dev_mem_base = pci_dev->mem_resource[ENA_MEM_BAR].addr;
1614
1615         if (!adapter->regs) {
1616                 PMD_INIT_LOG(CRIT, "Failed to access registers BAR(%d)",
1617                              ENA_REGS_BAR);
1618                 return -ENXIO;
1619         }
1620
1621         ena_dev->reg_bar = adapter->regs;
1622         ena_dev->dmadev = adapter->pdev;
1623
1624         adapter->id_number = adapters_found;
1625
1626         snprintf(adapter->name, ENA_NAME_MAX_LEN, "ena_%d",
1627                  adapter->id_number);
1628
1629         /* device specific initialization routine */
1630         rc = ena_device_init(ena_dev, &get_feat_ctx, &wd_state);
1631         if (rc) {
1632                 PMD_INIT_LOG(CRIT, "Failed to init ENA device");
1633                 goto err;
1634         }
1635         adapter->wd_state = wd_state;
1636
1637         ena_dev->tx_mem_queue_type = ENA_ADMIN_PLACEMENT_POLICY_HOST;
1638         adapter->num_queues = ena_calc_io_queue_num(ena_dev,
1639                                                     &get_feat_ctx);
1640
1641         queue_size = ena_calc_queue_size(ena_dev, &tx_sgl_size, &get_feat_ctx);
1642         if (queue_size <= 0 || adapter->num_queues <= 0) {
1643                 rc = -EFAULT;
1644                 goto err_device_destroy;
1645         }
1646
1647         adapter->tx_ring_size = queue_size;
1648         adapter->rx_ring_size = queue_size;
1649
1650         adapter->max_tx_sgl_size = tx_sgl_size;
1651
1652         /* prepare ring structures */
1653         ena_init_rings(adapter);
1654
1655         ena_config_debug_area(adapter);
1656
1657         /* Set max MTU for this device */
1658         adapter->max_mtu = get_feat_ctx.dev_attr.max_mtu;
1659
1660         /* set device support for TSO */
1661         adapter->tso4_supported = get_feat_ctx.offload.tx &
1662                                   ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_IPV4_MASK;
1663
1664         /* Copy MAC address and point DPDK to it */
1665         eth_dev->data->mac_addrs = (struct ether_addr *)adapter->mac_addr;
1666         ether_addr_copy((struct ether_addr *)get_feat_ctx.dev_attr.mac_addr,
1667                         (struct ether_addr *)adapter->mac_addr);
1668
1669         adapter->drv_stats = rte_zmalloc("adapter stats",
1670                                          sizeof(*adapter->drv_stats),
1671                                          RTE_CACHE_LINE_SIZE);
1672         if (!adapter->drv_stats) {
1673                 RTE_LOG(ERR, PMD, "failed to alloc mem for adapter stats\n");
1674                 rc = -ENOMEM;
1675                 goto err_delete_debug_area;
1676         }
1677
1678         rte_intr_callback_register(intr_handle,
1679                                    ena_interrupt_handler_rte,
1680                                    adapter);
1681         rte_intr_enable(intr_handle);
1682         ena_com_set_admin_polling_mode(ena_dev, false);
1683         ena_com_admin_aenq_enable(ena_dev);
1684
1685         if (adapters_found == 0)
1686                 rte_timer_subsystem_init();
1687         rte_timer_init(&adapter->timer_wd);
1688
1689         adapters_found++;
1690         adapter->state = ENA_ADAPTER_STATE_INIT;
1691
1692         return 0;
1693
1694 err_delete_debug_area:
1695         ena_com_delete_debug_area(ena_dev);
1696
1697 err_device_destroy:
1698         ena_com_delete_host_info(ena_dev);
1699         ena_com_admin_destroy(ena_dev);
1700
1701 err:
1702         return rc;
1703 }
1704
1705 static int eth_ena_dev_uninit(struct rte_eth_dev *eth_dev)
1706 {
1707         struct ena_adapter *adapter =
1708                 (struct ena_adapter *)(eth_dev->data->dev_private);
1709
1710         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1711                 return 0;
1712
1713         if (adapter->state != ENA_ADAPTER_STATE_CLOSED)
1714                 ena_close(eth_dev);
1715
1716         eth_dev->dev_ops = NULL;
1717         eth_dev->rx_pkt_burst = NULL;
1718         eth_dev->tx_pkt_burst = NULL;
1719         eth_dev->tx_pkt_prepare = NULL;
1720
1721         adapter->state = ENA_ADAPTER_STATE_FREE;
1722
1723         return 0;
1724 }
1725
1726 static int ena_dev_configure(struct rte_eth_dev *dev)
1727 {
1728         struct ena_adapter *adapter =
1729                 (struct ena_adapter *)(dev->data->dev_private);
1730
1731         adapter->state = ENA_ADAPTER_STATE_CONFIG;
1732
1733         adapter->tx_selected_offloads = dev->data->dev_conf.txmode.offloads;
1734         adapter->rx_selected_offloads = dev->data->dev_conf.rxmode.offloads;
1735         return 0;
1736 }
1737
1738 static void ena_init_rings(struct ena_adapter *adapter)
1739 {
1740         int i;
1741
1742         for (i = 0; i < adapter->num_queues; i++) {
1743                 struct ena_ring *ring = &adapter->tx_ring[i];
1744
1745                 ring->configured = 0;
1746                 ring->type = ENA_RING_TYPE_TX;
1747                 ring->adapter = adapter;
1748                 ring->id = i;
1749                 ring->tx_mem_queue_type = adapter->ena_dev.tx_mem_queue_type;
1750                 ring->tx_max_header_size = adapter->ena_dev.tx_max_header_size;
1751                 ring->sgl_size = adapter->max_tx_sgl_size;
1752         }
1753
1754         for (i = 0; i < adapter->num_queues; i++) {
1755                 struct ena_ring *ring = &adapter->rx_ring[i];
1756
1757                 ring->configured = 0;
1758                 ring->type = ENA_RING_TYPE_RX;
1759                 ring->adapter = adapter;
1760                 ring->id = i;
1761         }
1762 }
1763
1764 static void ena_infos_get(struct rte_eth_dev *dev,
1765                           struct rte_eth_dev_info *dev_info)
1766 {
1767         struct ena_adapter *adapter;
1768         struct ena_com_dev *ena_dev;
1769         struct ena_com_dev_get_features_ctx feat;
1770         uint64_t rx_feat = 0, tx_feat = 0;
1771         int rc = 0;
1772
1773         ena_assert_msg(dev->data != NULL, "Uninitialized device");
1774         ena_assert_msg(dev->data->dev_private != NULL, "Uninitialized device");
1775         adapter = (struct ena_adapter *)(dev->data->dev_private);
1776
1777         ena_dev = &adapter->ena_dev;
1778         ena_assert_msg(ena_dev != NULL, "Uninitialized device");
1779
1780         dev_info->speed_capa =
1781                         ETH_LINK_SPEED_1G   |
1782                         ETH_LINK_SPEED_2_5G |
1783                         ETH_LINK_SPEED_5G   |
1784                         ETH_LINK_SPEED_10G  |
1785                         ETH_LINK_SPEED_25G  |
1786                         ETH_LINK_SPEED_40G  |
1787                         ETH_LINK_SPEED_50G  |
1788                         ETH_LINK_SPEED_100G;
1789
1790         /* Get supported features from HW */
1791         rc = ena_com_get_dev_attr_feat(ena_dev, &feat);
1792         if (unlikely(rc)) {
1793                 RTE_LOG(ERR, PMD,
1794                         "Cannot get attribute for ena device rc= %d\n", rc);
1795                 return;
1796         }
1797
1798         /* Set Tx & Rx features available for device */
1799         if (feat.offload.tx & ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_IPV4_MASK)
1800                 tx_feat |= DEV_TX_OFFLOAD_TCP_TSO;
1801
1802         if (feat.offload.tx &
1803             ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV4_CSUM_PART_MASK)
1804                 tx_feat |= DEV_TX_OFFLOAD_IPV4_CKSUM |
1805                         DEV_TX_OFFLOAD_UDP_CKSUM |
1806                         DEV_TX_OFFLOAD_TCP_CKSUM;
1807
1808         if (feat.offload.rx_supported &
1809             ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L4_IPV4_CSUM_MASK)
1810                 rx_feat |= DEV_RX_OFFLOAD_IPV4_CKSUM |
1811                         DEV_RX_OFFLOAD_UDP_CKSUM  |
1812                         DEV_RX_OFFLOAD_TCP_CKSUM;
1813
1814         rx_feat |= DEV_RX_OFFLOAD_JUMBO_FRAME;
1815
1816         /* Inform framework about available features */
1817         dev_info->rx_offload_capa = rx_feat;
1818         dev_info->rx_queue_offload_capa = rx_feat;
1819         dev_info->tx_offload_capa = tx_feat;
1820         dev_info->tx_queue_offload_capa = tx_feat;
1821
1822         dev_info->min_rx_bufsize = ENA_MIN_FRAME_LEN;
1823         dev_info->max_rx_pktlen  = adapter->max_mtu;
1824         dev_info->max_mac_addrs = 1;
1825
1826         dev_info->max_rx_queues = adapter->num_queues;
1827         dev_info->max_tx_queues = adapter->num_queues;
1828         dev_info->reta_size = ENA_RX_RSS_TABLE_SIZE;
1829
1830         adapter->tx_supported_offloads = tx_feat;
1831         adapter->rx_supported_offloads = rx_feat;
1832
1833         dev_info->rx_desc_lim.nb_max = ENA_MAX_RING_DESC;
1834         dev_info->rx_desc_lim.nb_min = ENA_MIN_RING_DESC;
1835
1836         dev_info->tx_desc_lim.nb_max = ENA_MAX_RING_DESC;
1837         dev_info->tx_desc_lim.nb_min = ENA_MIN_RING_DESC;
1838         dev_info->tx_desc_lim.nb_seg_max = RTE_MIN(ENA_PKT_MAX_BUFS,
1839                                         feat.max_queues.max_packet_tx_descs);
1840         dev_info->tx_desc_lim.nb_mtu_seg_max = RTE_MIN(ENA_PKT_MAX_BUFS,
1841                                         feat.max_queues.max_packet_tx_descs);
1842 }
1843
1844 static uint16_t eth_ena_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,
1845                                   uint16_t nb_pkts)
1846 {
1847         struct ena_ring *rx_ring = (struct ena_ring *)(rx_queue);
1848         unsigned int ring_size = rx_ring->ring_size;
1849         unsigned int ring_mask = ring_size - 1;
1850         uint16_t next_to_clean = rx_ring->next_to_clean;
1851         uint16_t desc_in_use = 0;
1852         uint16_t req_id;
1853         unsigned int recv_idx = 0;
1854         struct rte_mbuf *mbuf = NULL;
1855         struct rte_mbuf *mbuf_head = NULL;
1856         struct rte_mbuf *mbuf_prev = NULL;
1857         struct rte_mbuf **rx_buff_info = rx_ring->rx_buffer_info;
1858         unsigned int completed;
1859
1860         struct ena_com_rx_ctx ena_rx_ctx;
1861         int rc = 0;
1862
1863         /* Check adapter state */
1864         if (unlikely(rx_ring->adapter->state != ENA_ADAPTER_STATE_RUNNING)) {
1865                 RTE_LOG(ALERT, PMD,
1866                         "Trying to receive pkts while device is NOT running\n");
1867                 return 0;
1868         }
1869
1870         desc_in_use = rx_ring->next_to_use - next_to_clean;
1871         if (unlikely(nb_pkts > desc_in_use))
1872                 nb_pkts = desc_in_use;
1873
1874         for (completed = 0; completed < nb_pkts; completed++) {
1875                 int segments = 0;
1876
1877                 ena_rx_ctx.max_bufs = rx_ring->ring_size;
1878                 ena_rx_ctx.ena_bufs = rx_ring->ena_bufs;
1879                 ena_rx_ctx.descs = 0;
1880                 /* receive packet context */
1881                 rc = ena_com_rx_pkt(rx_ring->ena_com_io_cq,
1882                                     rx_ring->ena_com_io_sq,
1883                                     &ena_rx_ctx);
1884                 if (unlikely(rc)) {
1885                         RTE_LOG(ERR, PMD, "ena_com_rx_pkt error %d\n", rc);
1886                         rx_ring->adapter->trigger_reset = true;
1887                         return 0;
1888                 }
1889
1890                 if (unlikely(ena_rx_ctx.descs == 0))
1891                         break;
1892
1893                 while (segments < ena_rx_ctx.descs) {
1894                         req_id = ena_rx_ctx.ena_bufs[segments].req_id;
1895                         rc = validate_rx_req_id(rx_ring, req_id);
1896                         if (unlikely(rc))
1897                                 break;
1898
1899                         mbuf = rx_buff_info[req_id];
1900                         mbuf->data_len = ena_rx_ctx.ena_bufs[segments].len;
1901                         mbuf->data_off = RTE_PKTMBUF_HEADROOM;
1902                         mbuf->refcnt = 1;
1903                         mbuf->next = NULL;
1904                         if (unlikely(segments == 0)) {
1905                                 mbuf->nb_segs = ena_rx_ctx.descs;
1906                                 mbuf->port = rx_ring->port_id;
1907                                 mbuf->pkt_len = 0;
1908                                 mbuf_head = mbuf;
1909                         } else {
1910                                 /* for multi-segment pkts create mbuf chain */
1911                                 mbuf_prev->next = mbuf;
1912                         }
1913                         mbuf_head->pkt_len += mbuf->data_len;
1914
1915                         mbuf_prev = mbuf;
1916                         rx_ring->empty_rx_reqs[next_to_clean & ring_mask] =
1917                                 req_id;
1918                         segments++;
1919                         next_to_clean++;
1920                 }
1921
1922                 /* fill mbuf attributes if any */
1923                 ena_rx_mbuf_prepare(mbuf_head, &ena_rx_ctx);
1924                 mbuf_head->hash.rss = ena_rx_ctx.hash;
1925
1926                 /* pass to DPDK application head mbuf */
1927                 rx_pkts[recv_idx] = mbuf_head;
1928                 recv_idx++;
1929         }
1930
1931         rx_ring->next_to_clean = next_to_clean;
1932
1933         desc_in_use = desc_in_use - completed + 1;
1934         /* Burst refill to save doorbells, memory barriers, const interval */
1935         if (ring_size - desc_in_use > ENA_RING_DESCS_RATIO(ring_size))
1936                 ena_populate_rx_queue(rx_ring, ring_size - desc_in_use);
1937
1938         return recv_idx;
1939 }
1940
1941 static uint16_t
1942 eth_ena_prep_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
1943                 uint16_t nb_pkts)
1944 {
1945         int32_t ret;
1946         uint32_t i;
1947         struct rte_mbuf *m;
1948         struct ena_ring *tx_ring = (struct ena_ring *)(tx_queue);
1949         struct ipv4_hdr *ip_hdr;
1950         uint64_t ol_flags;
1951         uint16_t frag_field;
1952
1953         for (i = 0; i != nb_pkts; i++) {
1954                 m = tx_pkts[i];
1955                 ol_flags = m->ol_flags;
1956
1957                 if (!(ol_flags & PKT_TX_IPV4))
1958                         continue;
1959
1960                 /* If there was not L2 header length specified, assume it is
1961                  * length of the ethernet header.
1962                  */
1963                 if (unlikely(m->l2_len == 0))
1964                         m->l2_len = sizeof(struct ether_hdr);
1965
1966                 ip_hdr = rte_pktmbuf_mtod_offset(m, struct ipv4_hdr *,
1967                                                  m->l2_len);
1968                 frag_field = rte_be_to_cpu_16(ip_hdr->fragment_offset);
1969
1970                 if ((frag_field & IPV4_HDR_DF_FLAG) != 0) {
1971                         m->packet_type |= RTE_PTYPE_L4_NONFRAG;
1972
1973                         /* If IPv4 header has DF flag enabled and TSO support is
1974                          * disabled, partial chcecksum should not be calculated.
1975                          */
1976                         if (!tx_ring->adapter->tso4_supported)
1977                                 continue;
1978                 }
1979
1980                 if ((ol_flags & ENA_TX_OFFLOAD_NOTSUP_MASK) != 0 ||
1981                                 (ol_flags & PKT_TX_L4_MASK) ==
1982                                 PKT_TX_SCTP_CKSUM) {
1983                         rte_errno = -ENOTSUP;
1984                         return i;
1985                 }
1986
1987 #ifdef RTE_LIBRTE_ETHDEV_DEBUG
1988                 ret = rte_validate_tx_offload(m);
1989                 if (ret != 0) {
1990                         rte_errno = ret;
1991                         return i;
1992                 }
1993 #endif
1994
1995                 /* In case we are supposed to TSO and have DF not set (DF=0)
1996                  * hardware must be provided with partial checksum, otherwise
1997                  * it will take care of necessary calculations.
1998                  */
1999
2000                 ret = rte_net_intel_cksum_flags_prepare(m,
2001                         ol_flags & ~PKT_TX_TCP_SEG);
2002                 if (ret != 0) {
2003                         rte_errno = ret;
2004                         return i;
2005                 }
2006         }
2007
2008         return i;
2009 }
2010
2011 static void ena_update_hints(struct ena_adapter *adapter,
2012                              struct ena_admin_ena_hw_hints *hints)
2013 {
2014         if (hints->admin_completion_tx_timeout)
2015                 adapter->ena_dev.admin_queue.completion_timeout =
2016                         hints->admin_completion_tx_timeout * 1000;
2017
2018         if (hints->mmio_read_timeout)
2019                 /* convert to usec */
2020                 adapter->ena_dev.mmio_read.reg_read_to =
2021                         hints->mmio_read_timeout * 1000;
2022
2023         if (hints->driver_watchdog_timeout) {
2024                 if (hints->driver_watchdog_timeout == ENA_HW_HINTS_NO_TIMEOUT)
2025                         adapter->keep_alive_timeout = ENA_HW_HINTS_NO_TIMEOUT;
2026                 else
2027                         // Convert msecs to ticks
2028                         adapter->keep_alive_timeout =
2029                                 (hints->driver_watchdog_timeout *
2030                                 rte_get_timer_hz()) / 1000;
2031         }
2032 }
2033
2034 static int ena_check_and_linearize_mbuf(struct ena_ring *tx_ring,
2035                                         struct rte_mbuf *mbuf)
2036 {
2037         int num_segments, rc;
2038
2039         num_segments = mbuf->nb_segs;
2040
2041         if (likely(num_segments < tx_ring->sgl_size))
2042                 return 0;
2043
2044         rc = rte_pktmbuf_linearize(mbuf);
2045         if (unlikely(rc))
2046                 RTE_LOG(WARNING, PMD, "Mbuf linearize failed\n");
2047
2048         return rc;
2049 }
2050
2051 static uint16_t eth_ena_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
2052                                   uint16_t nb_pkts)
2053 {
2054         struct ena_ring *tx_ring = (struct ena_ring *)(tx_queue);
2055         uint16_t next_to_use = tx_ring->next_to_use;
2056         uint16_t next_to_clean = tx_ring->next_to_clean;
2057         struct rte_mbuf *mbuf;
2058         unsigned int ring_size = tx_ring->ring_size;
2059         unsigned int ring_mask = ring_size - 1;
2060         struct ena_com_tx_ctx ena_tx_ctx;
2061         struct ena_tx_buffer *tx_info;
2062         struct ena_com_buf *ebuf;
2063         uint16_t rc, req_id, total_tx_descs = 0;
2064         uint16_t sent_idx = 0, empty_tx_reqs;
2065         int nb_hw_desc;
2066
2067         /* Check adapter state */
2068         if (unlikely(tx_ring->adapter->state != ENA_ADAPTER_STATE_RUNNING)) {
2069                 RTE_LOG(ALERT, PMD,
2070                         "Trying to xmit pkts while device is NOT running\n");
2071                 return 0;
2072         }
2073
2074         empty_tx_reqs = ring_size - (next_to_use - next_to_clean);
2075         if (nb_pkts > empty_tx_reqs)
2076                 nb_pkts = empty_tx_reqs;
2077
2078         for (sent_idx = 0; sent_idx < nb_pkts; sent_idx++) {
2079                 mbuf = tx_pkts[sent_idx];
2080
2081                 rc = ena_check_and_linearize_mbuf(tx_ring, mbuf);
2082                 if (unlikely(rc))
2083                         break;
2084
2085                 req_id = tx_ring->empty_tx_reqs[next_to_use & ring_mask];
2086                 tx_info = &tx_ring->tx_buffer_info[req_id];
2087                 tx_info->mbuf = mbuf;
2088                 tx_info->num_of_bufs = 0;
2089                 ebuf = tx_info->bufs;
2090
2091                 /* Prepare TX context */
2092                 memset(&ena_tx_ctx, 0x0, sizeof(struct ena_com_tx_ctx));
2093                 memset(&ena_tx_ctx.ena_meta, 0x0,
2094                        sizeof(struct ena_com_tx_meta));
2095                 ena_tx_ctx.ena_bufs = ebuf;
2096                 ena_tx_ctx.req_id = req_id;
2097                 if (tx_ring->tx_mem_queue_type ==
2098                                 ENA_ADMIN_PLACEMENT_POLICY_DEV) {
2099                         /* prepare the push buffer with
2100                          * virtual address of the data
2101                          */
2102                         ena_tx_ctx.header_len =
2103                                 RTE_MIN(mbuf->data_len,
2104                                         tx_ring->tx_max_header_size);
2105                         ena_tx_ctx.push_header =
2106                                 (void *)((char *)mbuf->buf_addr +
2107                                          mbuf->data_off);
2108                 } /* there's no else as we take advantage of memset zeroing */
2109
2110                 /* Set TX offloads flags, if applicable */
2111                 ena_tx_mbuf_prepare(mbuf, &ena_tx_ctx, tx_ring->offloads);
2112
2113                 if (unlikely(mbuf->ol_flags &
2114                              (PKT_RX_L4_CKSUM_BAD | PKT_RX_IP_CKSUM_BAD)))
2115                         rte_atomic64_inc(&tx_ring->adapter->drv_stats->ierrors);
2116
2117                 rte_prefetch0(tx_pkts[(sent_idx + 4) & ring_mask]);
2118
2119                 /* Process first segment taking into
2120                  * consideration pushed header
2121                  */
2122                 if (mbuf->data_len > ena_tx_ctx.header_len) {
2123                         ebuf->paddr = mbuf->buf_iova +
2124                                       mbuf->data_off +
2125                                       ena_tx_ctx.header_len;
2126                         ebuf->len = mbuf->data_len - ena_tx_ctx.header_len;
2127                         ebuf++;
2128                         tx_info->num_of_bufs++;
2129                 }
2130
2131                 while ((mbuf = mbuf->next) != NULL) {
2132                         ebuf->paddr = mbuf->buf_iova + mbuf->data_off;
2133                         ebuf->len = mbuf->data_len;
2134                         ebuf++;
2135                         tx_info->num_of_bufs++;
2136                 }
2137
2138                 ena_tx_ctx.num_bufs = tx_info->num_of_bufs;
2139
2140                 /* Write data to device */
2141                 rc = ena_com_prepare_tx(tx_ring->ena_com_io_sq,
2142                                         &ena_tx_ctx, &nb_hw_desc);
2143                 if (unlikely(rc))
2144                         break;
2145
2146                 tx_info->tx_descs = nb_hw_desc;
2147
2148                 next_to_use++;
2149         }
2150
2151         /* If there are ready packets to be xmitted... */
2152         if (sent_idx > 0) {
2153                 /* ...let HW do its best :-) */
2154                 rte_wmb();
2155                 ena_com_write_sq_doorbell(tx_ring->ena_com_io_sq);
2156
2157                 tx_ring->next_to_use = next_to_use;
2158         }
2159
2160         /* Clear complete packets  */
2161         while (ena_com_tx_comp_req_id_get(tx_ring->ena_com_io_cq, &req_id) >= 0) {
2162                 rc = validate_tx_req_id(tx_ring, req_id);
2163                 if (rc)
2164                         break;
2165
2166                 /* Get Tx info & store how many descs were processed  */
2167                 tx_info = &tx_ring->tx_buffer_info[req_id];
2168                 total_tx_descs += tx_info->tx_descs;
2169
2170                 /* Free whole mbuf chain  */
2171                 mbuf = tx_info->mbuf;
2172                 rte_pktmbuf_free(mbuf);
2173                 tx_info->mbuf = NULL;
2174
2175                 /* Put back descriptor to the ring for reuse */
2176                 tx_ring->empty_tx_reqs[next_to_clean & ring_mask] = req_id;
2177                 next_to_clean++;
2178
2179                 /* If too many descs to clean, leave it for another run */
2180                 if (unlikely(total_tx_descs > ENA_RING_DESCS_RATIO(ring_size)))
2181                         break;
2182         }
2183
2184         if (total_tx_descs > 0) {
2185                 /* acknowledge completion of sent packets */
2186                 ena_com_comp_ack(tx_ring->ena_com_io_sq, total_tx_descs);
2187                 tx_ring->next_to_clean = next_to_clean;
2188         }
2189
2190         return sent_idx;
2191 }
2192
2193 /*********************************************************************
2194  *  PMD configuration
2195  *********************************************************************/
2196 static int eth_ena_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
2197         struct rte_pci_device *pci_dev)
2198 {
2199         return rte_eth_dev_pci_generic_probe(pci_dev,
2200                 sizeof(struct ena_adapter), eth_ena_dev_init);
2201 }
2202
2203 static int eth_ena_pci_remove(struct rte_pci_device *pci_dev)
2204 {
2205         return rte_eth_dev_pci_generic_remove(pci_dev, eth_ena_dev_uninit);
2206 }
2207
2208 static struct rte_pci_driver rte_ena_pmd = {
2209         .id_table = pci_id_ena_map,
2210         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC |
2211                      RTE_PCI_DRV_WC_ACTIVATE,
2212         .probe = eth_ena_pci_probe,
2213         .remove = eth_ena_pci_remove,
2214 };
2215
2216 RTE_PMD_REGISTER_PCI(net_ena, rte_ena_pmd);
2217 RTE_PMD_REGISTER_PCI_TABLE(net_ena, pci_id_ena_map);
2218 RTE_PMD_REGISTER_KMOD_DEP(net_ena, "* igb_uio | uio_pci_generic | vfio-pci");
2219
2220 RTE_INIT(ena_init_log)
2221 {
2222         ena_logtype_init = rte_log_register("pmd.net.ena.init");
2223         if (ena_logtype_init >= 0)
2224                 rte_log_set_level(ena_logtype_init, RTE_LOG_NOTICE);
2225         ena_logtype_driver = rte_log_register("pmd.net.ena.driver");
2226         if (ena_logtype_driver >= 0)
2227                 rte_log_set_level(ena_logtype_driver, RTE_LOG_NOTICE);
2228 }
2229
2230 /******************************************************************************
2231  ******************************** AENQ Handlers *******************************
2232  *****************************************************************************/
2233 static void ena_update_on_link_change(void *adapter_data,
2234                                       struct ena_admin_aenq_entry *aenq_e)
2235 {
2236         struct rte_eth_dev *eth_dev;
2237         struct ena_adapter *adapter;
2238         struct ena_admin_aenq_link_change_desc *aenq_link_desc;
2239         uint32_t status;
2240
2241         adapter = (struct ena_adapter *)adapter_data;
2242         aenq_link_desc = (struct ena_admin_aenq_link_change_desc *)aenq_e;
2243         eth_dev = adapter->rte_dev;
2244
2245         status = get_ena_admin_aenq_link_change_desc_link_status(aenq_link_desc);
2246         adapter->link_status = status;
2247
2248         ena_link_update(eth_dev, 0);
2249         _rte_eth_dev_callback_process(eth_dev, RTE_ETH_EVENT_INTR_LSC, NULL);
2250 }
2251
2252 static void ena_notification(void *data,
2253                              struct ena_admin_aenq_entry *aenq_e)
2254 {
2255         struct ena_adapter *adapter = (struct ena_adapter *)data;
2256         struct ena_admin_ena_hw_hints *hints;
2257
2258         if (aenq_e->aenq_common_desc.group != ENA_ADMIN_NOTIFICATION)
2259                 RTE_LOG(WARNING, PMD, "Invalid group(%x) expected %x\n",
2260                         aenq_e->aenq_common_desc.group,
2261                         ENA_ADMIN_NOTIFICATION);
2262
2263         switch (aenq_e->aenq_common_desc.syndrom) {
2264         case ENA_ADMIN_UPDATE_HINTS:
2265                 hints = (struct ena_admin_ena_hw_hints *)
2266                         (&aenq_e->inline_data_w4);
2267                 ena_update_hints(adapter, hints);
2268                 break;
2269         default:
2270                 RTE_LOG(ERR, PMD, "Invalid aenq notification link state %d\n",
2271                         aenq_e->aenq_common_desc.syndrom);
2272         }
2273 }
2274
2275 static void ena_keep_alive(void *adapter_data,
2276                            __rte_unused struct ena_admin_aenq_entry *aenq_e)
2277 {
2278         struct ena_adapter *adapter = (struct ena_adapter *)adapter_data;
2279
2280         adapter->timestamp_wd = rte_get_timer_cycles();
2281 }
2282
2283 /**
2284  * This handler will called for unknown event group or unimplemented handlers
2285  **/
2286 static void unimplemented_aenq_handler(__rte_unused void *data,
2287                                        __rte_unused struct ena_admin_aenq_entry *aenq_e)
2288 {
2289         RTE_LOG(ERR, PMD, "Unknown event was received or event with "
2290                           "unimplemented handler\n");
2291 }
2292
2293 static struct ena_aenq_handlers aenq_handlers = {
2294         .handlers = {
2295                 [ENA_ADMIN_LINK_CHANGE] = ena_update_on_link_change,
2296                 [ENA_ADMIN_NOTIFICATION] = ena_notification,
2297                 [ENA_ADMIN_KEEP_ALIVE] = ena_keep_alive
2298         },
2299         .unimplemented_handler = unimplemented_aenq_handler
2300 };