drivers/net/enic/enic_rxtx.c

   1 /* Copyright 2008-2016 Cisco Systems, Inc.  All rights reserved.
   2  * Copyright 2007 Nuova Systems, Inc.  All rights reserved.
   3  *
   4  * Copyright (c) 2014, Cisco Systems, Inc.
   5  * All rights reserved.
   6  *
   7  * Redistribution and use in source and binary forms, with or without
   8  * modification, are permitted provided that the following conditions
   9  * are met:
  10  *
  11  * 1. Redistributions of source code must retain the above copyright
  12  * notice, this list of conditions and the following disclaimer.
  13  *
  14  * 2. Redistributions in binary form must reproduce the above copyright
  15  * notice, this list of conditions and the following disclaimer in
  16  * the documentation and/or other materials provided with the
  17  * distribution.
  18  *
  19  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  20  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  21  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
  22  * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
  23  * COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
  24  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
  25  * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
  26  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
  27  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  28  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
  29  * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  30  * POSSIBILITY OF SUCH DAMAGE.
  31  */
  32
  33 #include <rte_mbuf.h>
  34 #include <rte_ethdev.h>
  35 #include <rte_prefetch.h>
  36
  37 #include "enic_compat.h"
  38 #include "rq_enet_desc.h"
  39 #include "enic.h"
  40
  41 #define RTE_PMD_USE_PREFETCH
  42
  43 #ifdef RTE_PMD_USE_PREFETCH
  44 /*Prefetch a cache line into all cache levels. */
  45 #define rte_enic_prefetch(p) rte_prefetch0(p)
  46 #else
  47 #define rte_enic_prefetch(p) do {} while (0)
  48 #endif
  49
  50 #ifdef RTE_PMD_PACKET_PREFETCH
  51 #define rte_packet_prefetch(p) rte_prefetch1(p)
  52 #else
  53 #define rte_packet_prefetch(p) do {} while (0)
  54 #endif
  55
  56 static inline uint16_t
  57 enic_cq_rx_desc_ciflags(struct cq_enet_rq_desc *crd)
  58 {
  59         return le16_to_cpu(crd->completed_index_flags) & ~CQ_DESC_COMP_NDX_MASK;
  60 }
  61
  62 static inline uint16_t
  63 enic_cq_rx_desc_bwflags(struct cq_enet_rq_desc *crd)
  64 {
  65         return le16_to_cpu(crd->bytes_written_flags) &
  66                            ~CQ_ENET_RQ_DESC_BYTES_WRITTEN_MASK;
  67 }
  68
  69 static inline uint8_t
  70 enic_cq_rx_desc_packet_error(uint16_t bwflags)
  71 {
  72         return (bwflags & CQ_ENET_RQ_DESC_FLAGS_TRUNCATED) ==
  73                 CQ_ENET_RQ_DESC_FLAGS_TRUNCATED;
  74 }
  75
  76 static inline uint8_t
  77 enic_cq_rx_desc_eop(uint16_t ciflags)
  78 {
  79         return (ciflags & CQ_ENET_RQ_DESC_FLAGS_EOP)
  80                 == CQ_ENET_RQ_DESC_FLAGS_EOP;
  81 }
  82
  83 static inline uint8_t
  84 enic_cq_rx_desc_csum_not_calc(struct cq_enet_rq_desc *cqrd)
  85 {
  86         return (le16_to_cpu(cqrd->q_number_rss_type_flags) &
  87                 CQ_ENET_RQ_DESC_FLAGS_CSUM_NOT_CALC) ==
  88                 CQ_ENET_RQ_DESC_FLAGS_CSUM_NOT_CALC;
  89 }
  90
  91 static inline uint8_t
  92 enic_cq_rx_desc_ipv4_csum_ok(struct cq_enet_rq_desc *cqrd)
  93 {
  94         return (cqrd->flags & CQ_ENET_RQ_DESC_FLAGS_IPV4_CSUM_OK) ==
  95                 CQ_ENET_RQ_DESC_FLAGS_IPV4_CSUM_OK;
  96 }
  97
  98 static inline uint8_t
  99 enic_cq_rx_desc_tcp_udp_csum_ok(struct cq_enet_rq_desc *cqrd)
 100 {
 101         return (cqrd->flags & CQ_ENET_RQ_DESC_FLAGS_TCP_UDP_CSUM_OK) ==
 102                 CQ_ENET_RQ_DESC_FLAGS_TCP_UDP_CSUM_OK;
 103 }
 104
 105 static inline uint8_t
 106 enic_cq_rx_desc_rss_type(struct cq_enet_rq_desc *cqrd)
 107 {
 108         return (uint8_t)((le16_to_cpu(cqrd->q_number_rss_type_flags) >>
 109                 CQ_DESC_Q_NUM_BITS) & CQ_ENET_RQ_DESC_RSS_TYPE_MASK);
 110 }
 111
 112 static inline uint32_t
 113 enic_cq_rx_desc_rss_hash(struct cq_enet_rq_desc *cqrd)
 114 {
 115         return le32_to_cpu(cqrd->rss_hash);
 116 }
 117
 118 static inline uint16_t
 119 enic_cq_rx_desc_vlan(struct cq_enet_rq_desc *cqrd)
 120 {
 121         return le16_to_cpu(cqrd->vlan);
 122 }
 123
 124 static inline uint16_t
 125 enic_cq_rx_desc_n_bytes(struct cq_desc *cqd)
 126 {
 127         struct cq_enet_rq_desc *cqrd = (struct cq_enet_rq_desc *)cqd;
 128         return le16_to_cpu(cqrd->bytes_written_flags) &
 129                 CQ_ENET_RQ_DESC_BYTES_WRITTEN_MASK;
 130 }
 131
 132 static inline uint8_t
 133 enic_cq_rx_check_err(struct cq_desc *cqd)
 134 {
 135         struct cq_enet_rq_desc *cqrd = (struct cq_enet_rq_desc *)cqd;
 136         uint16_t bwflags;
 137
 138         bwflags = enic_cq_rx_desc_bwflags(cqrd);
 139         if (unlikely(enic_cq_rx_desc_packet_error(bwflags)))
 140                 return 1;
 141         return 0;
 142 }
 143
 144 /* Lookup table to translate RX CQ flags to mbuf flags. */
 145 static inline uint32_t
 146 enic_cq_rx_flags_to_pkt_type(struct cq_desc *cqd)
 147 {
 148         struct cq_enet_rq_desc *cqrd = (struct cq_enet_rq_desc *)cqd;
 149         uint8_t cqrd_flags = cqrd->flags;
 150         static const uint32_t cq_type_table[128] __rte_cache_aligned = {
 151                 [0x00] = RTE_PTYPE_UNKNOWN,
 152                 [0x20] = RTE_PTYPE_L3_IPV4_EXT_UNKNOWN | RTE_PTYPE_L4_NONFRAG,
 153                 [0x22] = RTE_PTYPE_L3_IPV4_EXT_UNKNOWN | RTE_PTYPE_L4_UDP,
 154                 [0x24] = RTE_PTYPE_L3_IPV4_EXT_UNKNOWN | RTE_PTYPE_L4_TCP,
 155                 [0x60] = RTE_PTYPE_L3_IPV4_EXT_UNKNOWN | RTE_PTYPE_L4_FRAG,
 156                 [0x62] = RTE_PTYPE_L3_IPV4_EXT_UNKNOWN | RTE_PTYPE_L4_UDP,
 157                 [0x64] = RTE_PTYPE_L3_IPV4_EXT_UNKNOWN | RTE_PTYPE_L4_TCP,
 158                 [0x10] = RTE_PTYPE_L3_IPV6_EXT_UNKNOWN | RTE_PTYPE_L4_NONFRAG,
 159                 [0x12] = RTE_PTYPE_L3_IPV6_EXT_UNKNOWN | RTE_PTYPE_L4_UDP,
 160                 [0x14] = RTE_PTYPE_L3_IPV6_EXT_UNKNOWN | RTE_PTYPE_L4_TCP,
 161                 [0x50] = RTE_PTYPE_L3_IPV6_EXT_UNKNOWN | RTE_PTYPE_L4_FRAG,
 162                 [0x52] = RTE_PTYPE_L3_IPV6_EXT_UNKNOWN | RTE_PTYPE_L4_UDP,
 163                 [0x54] = RTE_PTYPE_L3_IPV6_EXT_UNKNOWN | RTE_PTYPE_L4_TCP,
 164                 /* All others reserved */
 165         };
 166         cqrd_flags &= CQ_ENET_RQ_DESC_FLAGS_IPV4_FRAGMENT
 167                 | CQ_ENET_RQ_DESC_FLAGS_IPV4 | CQ_ENET_RQ_DESC_FLAGS_IPV6
 168                 | CQ_ENET_RQ_DESC_FLAGS_TCP | CQ_ENET_RQ_DESC_FLAGS_UDP;
 169         return cq_type_table[cqrd_flags];
 170 }
 171
 172 static inline void
 173 enic_cq_rx_to_pkt_flags(struct cq_desc *cqd, struct rte_mbuf *mbuf)
 174 {
 175         struct cq_enet_rq_desc *cqrd = (struct cq_enet_rq_desc *)cqd;
 176         uint16_t ciflags, bwflags, pkt_flags = 0, vlan_tci;
 177         ciflags = enic_cq_rx_desc_ciflags(cqrd);
 178         bwflags = enic_cq_rx_desc_bwflags(cqrd);
 179         vlan_tci = enic_cq_rx_desc_vlan(cqrd);
 180
 181         mbuf->ol_flags = 0;
 182
 183         /* flags are meaningless if !EOP */
 184         if (unlikely(!enic_cq_rx_desc_eop(ciflags)))
 185                 goto mbuf_flags_done;
 186
 187         /* VLAN STRIPPED flag. The L2 packet type updated here also */
 188         if (bwflags & CQ_ENET_RQ_DESC_FLAGS_VLAN_STRIPPED) {
 189                 pkt_flags |= PKT_RX_VLAN_PKT | PKT_RX_VLAN_STRIPPED;
 190                 mbuf->packet_type |= RTE_PTYPE_L2_ETHER;
 191         } else {
 192                 if (vlan_tci != 0)
 193                         mbuf->packet_type |= RTE_PTYPE_L2_ETHER_VLAN;
 194                 else
 195                         mbuf->packet_type |= RTE_PTYPE_L2_ETHER;
 196         }
 197         mbuf->vlan_tci = vlan_tci;
 198
 199         /* RSS flag */
 200         if (enic_cq_rx_desc_rss_type(cqrd)) {
 201                 pkt_flags |= PKT_RX_RSS_HASH;
 202                 mbuf->hash.rss = enic_cq_rx_desc_rss_hash(cqrd);
 203         }
 204
 205         /* checksum flags */
 206         if (!enic_cq_rx_desc_csum_not_calc(cqrd) &&
 207                 (mbuf->packet_type & RTE_PTYPE_L3_IPV4)) {
 208                 uint32_t l4_flags = mbuf->packet_type & RTE_PTYPE_L4_MASK;
 209
 210                 if (unlikely(!enic_cq_rx_desc_ipv4_csum_ok(cqrd)))
 211                         pkt_flags |= PKT_RX_IP_CKSUM_BAD;
 212                 if (l4_flags == RTE_PTYPE_L4_UDP ||
 213                     l4_flags == RTE_PTYPE_L4_TCP) {
 214                         if (unlikely(!enic_cq_rx_desc_tcp_udp_csum_ok(cqrd)))
 215                                 pkt_flags |= PKT_RX_L4_CKSUM_BAD;
 216                 }
 217         }
 218
 219  mbuf_flags_done:
 220         mbuf->ol_flags = pkt_flags;
 221 }
 222
 223 /* dummy receive function to replace actual function in
 224  * order to do safe reconfiguration operations.
 225  */
 226 uint16_t
 227 enic_dummy_recv_pkts(__rte_unused void *rx_queue,
 228                      __rte_unused struct rte_mbuf **rx_pkts,
 229                      __rte_unused uint16_t nb_pkts)
 230 {
 231         return 0;
 232 }
 233
 234 uint16_t
 235 enic_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,
 236                uint16_t nb_pkts)
 237 {
 238         struct vnic_rq *sop_rq = rx_queue;
 239         struct vnic_rq *data_rq;
 240         struct vnic_rq *rq;
 241         struct enic *enic = vnic_dev_priv(sop_rq->vdev);
 242         uint16_t cq_idx;
 243         uint16_t rq_idx;
 244         uint16_t rq_num;
 245         struct rte_mbuf *nmb, *rxmb;
 246         uint16_t nb_rx = 0;
 247         struct vnic_cq *cq;
 248         volatile struct cq_desc *cqd_ptr;
 249         uint8_t color;
 250         uint16_t seg_length;
 251         struct rte_mbuf *first_seg = sop_rq->pkt_first_seg;
 252         struct rte_mbuf *last_seg = sop_rq->pkt_last_seg;
 253
 254         cq = &enic->cq[enic_cq_rq(enic, sop_rq->index)];
 255         cq_idx = cq->to_clean;          /* index of cqd, rqd, mbuf_table */
 256         cqd_ptr = (struct cq_desc *)(cq->ring.descs) + cq_idx;
 257
 258         data_rq = &enic->rq[sop_rq->data_queue_idx];
 259
 260         while (nb_rx < nb_pkts) {
 261                 volatile struct rq_enet_desc *rqd_ptr;
 262                 dma_addr_t dma_addr;
 263                 struct cq_desc cqd;
 264                 uint8_t packet_error;
 265                 uint16_t ciflags;
 266
 267                 /* Check for pkts available */
 268                 color = (cqd_ptr->type_color >> CQ_DESC_COLOR_SHIFT)
 269                         & CQ_DESC_COLOR_MASK;
 270                 if (color == cq->last_color)
 271                         break;
 272
 273                 /* Get the cq descriptor and extract rq info from it */
 274                 cqd = *cqd_ptr;
 275                 rq_num = cqd.q_number & CQ_DESC_Q_NUM_MASK;
 276                 rq_idx = cqd.completed_index & CQ_DESC_COMP_NDX_MASK;
 277
 278                 rq = &enic->rq[rq_num];
 279                 rqd_ptr = ((struct rq_enet_desc *)rq->ring.descs) + rq_idx;
 280
 281                 /* allocate a new mbuf */
 282                 nmb = rte_mbuf_raw_alloc(rq->mp);
 283                 if (nmb == NULL) {
 284                         rte_atomic64_inc(&enic->soft_stats.rx_nombuf);
 285                         break;
 286                 }
 287
 288                 /* A packet error means descriptor and data are untrusted */
 289                 packet_error = enic_cq_rx_check_err(&cqd);
 290
 291                 /* Get the mbuf to return and replace with one just allocated */
 292                 rxmb = rq->mbuf_ring[rq_idx];
 293                 rq->mbuf_ring[rq_idx] = nmb;
 294
 295                 /* Increment cqd, rqd, mbuf_table index */
 296                 cq_idx++;
 297                 if (unlikely(cq_idx == cq->ring.desc_count)) {
 298                         cq_idx = 0;
 299                         cq->last_color = cq->last_color ? 0 : 1;
 300                 }
 301
 302                 /* Prefetch next mbuf & desc while processing current one */
 303                 cqd_ptr = (struct cq_desc *)(cq->ring.descs) + cq_idx;
 304                 rte_enic_prefetch(cqd_ptr);
 305
 306                 ciflags = enic_cq_rx_desc_ciflags(
 307                         (struct cq_enet_rq_desc *)&cqd);
 308
 309                 /* Push descriptor for newly allocated mbuf */
 310                 nmb->data_off = RTE_PKTMBUF_HEADROOM;
 311                 dma_addr = (dma_addr_t)(nmb->buf_physaddr +
 312                                         RTE_PKTMBUF_HEADROOM);
 313                 rq_enet_desc_enc(rqd_ptr, dma_addr,
 314                                 (rq->is_sop ? RQ_ENET_TYPE_ONLY_SOP
 315                                 : RQ_ENET_TYPE_NOT_SOP),
 316                                 nmb->buf_len - RTE_PKTMBUF_HEADROOM);
 317
 318                 /* Fill in the rest of the mbuf */
 319                 seg_length = enic_cq_rx_desc_n_bytes(&cqd);
 320
 321                 if (rq->is_sop) {
 322                         first_seg = rxmb;
 323                         first_seg->nb_segs = 1;
 324                         first_seg->pkt_len = seg_length;
 325                 } else {
 326                         first_seg->pkt_len = (uint16_t)(first_seg->pkt_len
 327                                                         + seg_length);
 328                         first_seg->nb_segs++;
 329                         last_seg->next = rxmb;
 330                 }
 331
 332                 rxmb->next = NULL;
 333                 rxmb->port = enic->port_id;
 334                 rxmb->data_len = seg_length;
 335
 336                 rq->rx_nb_hold++;
 337
 338                 if (!(enic_cq_rx_desc_eop(ciflags))) {
 339                         last_seg = rxmb;
 340                         continue;
 341                 }
 342
 343                 /* cq rx flags are only valid if eop bit is set */
 344                 first_seg->packet_type = enic_cq_rx_flags_to_pkt_type(&cqd);
 345                 enic_cq_rx_to_pkt_flags(&cqd, first_seg);
 346
 347                 if (unlikely(packet_error)) {
 348                         rte_pktmbuf_free(first_seg);
 349                         rte_atomic64_inc(&enic->soft_stats.rx_packet_errors);
 350                         continue;
 351                 }
 352
 353
 354                 /* prefetch mbuf data for caller */
 355                 rte_packet_prefetch(RTE_PTR_ADD(first_seg->buf_addr,
 356                                     RTE_PKTMBUF_HEADROOM));
 357
 358                 /* store the mbuf address into the next entry of the array */
 359                 rx_pkts[nb_rx++] = first_seg;
 360         }
 361
 362         sop_rq->pkt_first_seg = first_seg;
 363         sop_rq->pkt_last_seg = last_seg;
 364
 365         cq->to_clean = cq_idx;
 366
 367         if ((sop_rq->rx_nb_hold + data_rq->rx_nb_hold) >
 368             sop_rq->rx_free_thresh) {
 369                 if (data_rq->in_use) {
 370                         data_rq->posted_index =
 371                                 enic_ring_add(data_rq->ring.desc_count,
 372                                               data_rq->posted_index,
 373                                               data_rq->rx_nb_hold);
 374                         data_rq->rx_nb_hold = 0;
 375                 }
 376                 sop_rq->posted_index = enic_ring_add(sop_rq->ring.desc_count,
 377                                                      sop_rq->posted_index,
 378                                                      sop_rq->rx_nb_hold);
 379                 sop_rq->rx_nb_hold = 0;
 380
 381                 rte_mb();
 382                 if (data_rq->in_use)
 383                         iowrite32(data_rq->posted_index,
 384                                   &data_rq->ctrl->posted_index);
 385                 rte_compiler_barrier();
 386                 iowrite32(sop_rq->posted_index, &sop_rq->ctrl->posted_index);
 387         }
 388
 389
 390         return nb_rx;
 391 }
 392
 393 static inline void enic_free_wq_bufs(struct vnic_wq *wq, u16 completed_index)
 394 {
 395         struct vnic_wq_buf *buf;
 396         struct rte_mbuf *m, *free[ENIC_MAX_WQ_DESCS];
 397         unsigned int nb_to_free, nb_free = 0, i;
 398         struct rte_mempool *pool;
 399         unsigned int tail_idx;
 400         unsigned int desc_count = wq->ring.desc_count;
 401
 402         nb_to_free = enic_ring_sub(desc_count, wq->tail_idx, completed_index)
 403                                    + 1;
 404         tail_idx = wq->tail_idx;
 405         buf = &wq->bufs[tail_idx];
 406         pool = ((struct rte_mbuf *)buf->mb)->pool;
 407         for (i = 0; i < nb_to_free; i++) {
 408                 buf = &wq->bufs[tail_idx];
 409                 m = __rte_pktmbuf_prefree_seg((struct rte_mbuf *)(buf->mb));
 410                 buf->mb = NULL;
 411
 412                 if (unlikely(m == NULL)) {
 413                         tail_idx = enic_ring_incr(desc_count, tail_idx);
 414                         continue;
 415                 }
 416
 417                 if (likely(m->pool == pool)) {
 418                         RTE_ASSERT(nb_free < ENIC_MAX_WQ_DESCS);
 419                         free[nb_free++] = m;
 420                 } else {
 421                         rte_mempool_put_bulk(pool, (void *)free, nb_free);
 422                         free[0] = m;
 423                         nb_free = 1;
 424                         pool = m->pool;
 425                 }
 426                 tail_idx = enic_ring_incr(desc_count, tail_idx);
 427         }
 428
 429         rte_mempool_put_bulk(pool, (void **)free, nb_free);
 430
 431         wq->tail_idx = tail_idx;
 432         wq->ring.desc_avail += nb_to_free;
 433 }
 434
 435 unsigned int enic_cleanup_wq(__rte_unused struct enic *enic, struct vnic_wq *wq)
 436 {
 437         u16 completed_index;
 438
 439         completed_index = *((uint32_t *)wq->cqmsg_rz->addr) & 0xffff;
 440
 441         if (wq->last_completed_index != completed_index) {
 442                 enic_free_wq_bufs(wq, completed_index);
 443                 wq->last_completed_index = completed_index;
 444         }
 445         return 0;
 446 }
 447
 448 uint16_t enic_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
 449         uint16_t nb_pkts)
 450 {
 451         uint16_t index;
 452         unsigned int pkt_len, data_len;
 453         unsigned int nb_segs;
 454         struct rte_mbuf *tx_pkt;
 455         struct vnic_wq *wq = (struct vnic_wq *)tx_queue;
 456         struct enic *enic = vnic_dev_priv(wq->vdev);
 457         unsigned short vlan_id;
 458         uint64_t ol_flags;
 459         uint64_t ol_flags_mask;
 460         unsigned int wq_desc_avail;
 461         int head_idx;
 462         struct vnic_wq_buf *buf;
 463         unsigned int desc_count;
 464         struct wq_enet_desc *descs, *desc_p, desc_tmp;
 465         uint16_t mss;
 466         uint8_t vlan_tag_insert;
 467         uint8_t eop;
 468         uint64_t bus_addr;
 469
 470         enic_cleanup_wq(enic, wq);
 471         wq_desc_avail = vnic_wq_desc_avail(wq);
 472         head_idx = wq->head_idx;
 473         desc_count = wq->ring.desc_count;
 474         ol_flags_mask = PKT_TX_VLAN_PKT | PKT_TX_IP_CKSUM | PKT_TX_L4_MASK;
 475
 476         nb_pkts = RTE_MIN(nb_pkts, ENIC_TX_XMIT_MAX);
 477
 478         for (index = 0; index < nb_pkts; index++) {
 479                 tx_pkt = *tx_pkts++;
 480                 nb_segs = tx_pkt->nb_segs;
 481                 if (nb_segs > wq_desc_avail) {
 482                         if (index > 0)
 483                                 goto post;
 484                         goto done;
 485                 }
 486
 487                 pkt_len = tx_pkt->pkt_len;
 488                 data_len = tx_pkt->data_len;
 489                 ol_flags = tx_pkt->ol_flags;
 490                 mss = 0;
 491                 vlan_id = 0;
 492                 vlan_tag_insert = 0;
 493                 bus_addr = (dma_addr_t)
 494                            (tx_pkt->buf_physaddr + tx_pkt->data_off);
 495
 496                 descs = (struct wq_enet_desc *)wq->ring.descs;
 497                 desc_p = descs + head_idx;
 498
 499                 eop = (data_len == pkt_len);
 500
 501                 if (ol_flags & ol_flags_mask) {
 502                         if (ol_flags & PKT_TX_VLAN_PKT) {
 503                                 vlan_tag_insert = 1;
 504                                 vlan_id = tx_pkt->vlan_tci;
 505                         }
 506
 507                         if (ol_flags & PKT_TX_IP_CKSUM)
 508                                 mss |= ENIC_CALC_IP_CKSUM;
 509
 510                         /* Nic uses just 1 bit for UDP and TCP */
 511                         switch (ol_flags & PKT_TX_L4_MASK) {
 512                         case PKT_TX_TCP_CKSUM:
 513                         case PKT_TX_UDP_CKSUM:
 514                                 mss |= ENIC_CALC_TCP_UDP_CKSUM;
 515                                 break;
 516                         }
 517                 }
 518
 519                 wq_enet_desc_enc(&desc_tmp, bus_addr, data_len, mss, 0, 0, eop,
 520                                  eop, 0, vlan_tag_insert, vlan_id, 0);
 521
 522                 *desc_p = desc_tmp;
 523                 buf = &wq->bufs[head_idx];
 524                 buf->mb = (void *)tx_pkt;
 525                 head_idx = enic_ring_incr(desc_count, head_idx);
 526                 wq_desc_avail--;
 527
 528                 if (!eop) {
 529                         for (tx_pkt = tx_pkt->next; tx_pkt; tx_pkt =
 530                             tx_pkt->next) {
 531                                 data_len = tx_pkt->data_len;
 532
 533                                 if (tx_pkt->next == NULL)
 534                                         eop = 1;
 535                                 desc_p = descs + head_idx;
 536                                 bus_addr = (dma_addr_t)(tx_pkt->buf_physaddr
 537                                            + tx_pkt->data_off);
 538                                 wq_enet_desc_enc((struct wq_enet_desc *)
 539                                                  &desc_tmp, bus_addr, data_len,
 540                                                  mss, 0, 0, eop, eop, 0,
 541                                                  vlan_tag_insert, vlan_id, 0);
 542
 543                                 *desc_p = desc_tmp;
 544                                 buf = &wq->bufs[head_idx];
 545                                 buf->mb = (void *)tx_pkt;
 546                                 head_idx = enic_ring_incr(desc_count, head_idx);
 547                                 wq_desc_avail--;
 548                         }
 549                 }
 550         }
 551  post:
 552         rte_wmb();
 553         iowrite32(head_idx, &wq->ctrl->posted_index);
 554  done:
 555         wq->ring.desc_avail = wq_desc_avail;
 556         wq->head_idx = head_idx;
 557
 558         return index;
 559 }
 560
 561